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dewildcard stage.py
author
Luke Kenneth Casson Leighton
<lkcl@lkcl.net>
Wed, 11 Mar 2020 16:51:57 +0000
(16:51 +0000)
committer
Luke Kenneth Casson Leighton
<lkcl@lkcl.net>
Wed, 11 Mar 2020 16:51:57 +0000
(16:51 +0000)
src/soc/minerva/stage.py
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diff --git
a/src/soc/minerva/stage.py
b/src/soc/minerva/stage.py
index 33d941deb338e00868f5a2edcbd6f0524711d58d..9144cc2be9c476a530504439f030b2be998fecf6 100644
(file)
--- a/
src/soc/minerva/stage.py
+++ b/
src/soc/minerva/stage.py
@@
-1,8
+1,8
@@
from functools import reduce
from operator import or_
-from nmigen import
*
-from nmigen.hdl.rec import
*
+from nmigen import
Elaboratable, Module, Mux, Record, Signal,
+from nmigen.hdl.rec import
DIR_FANIN, DIR_FANOUT, DIR_NONE
__all__ = ["Stage"]