mem_types.py wb_types.py add name constructor to all RecordObjects

diff --git a/src/soc/experiment/mem_types.py b/src/soc/experiment/mem_types.py
index 42618a237fb7827e9fc4337eb991df8474b7fab8..d766fb9099218aa87bfeb0496d4d90bb96c0b999 100644 (file)
--- a/src/soc/experiment/mem_types.py
+++ b/src/soc/experiment/mem_types.py
@@ -27,8 +27,8 @@ class DCacheToMMUType(RecordObject):
 
 
 class Fetch1ToICacheType(RecordObject):
-    def __init__(self):
-        super().__init__()
+    def __init__(self, name=None):
+        super().__init__(name=name)
         self.req           = Signal()
         self.virt_mode     = Signal()
         self.priv_mode     = Signal()
@@ -38,8 +38,8 @@ class Fetch1ToICacheType(RecordObject):
 
 
 class ICacheToDecode1Type(RecordObject):
-    def __init__(self):
-        super().__init__()
+    def __init__(self, name=None):
+        super().__init__(name=name)
         self.valid         = Signal()
         self.stop_mark     = Signal()
         self.fetch_failed  = Signal()
@@ -63,8 +63,8 @@ class LoadStore1ToDCacheType(RecordObject):
 
 
 class LoadStore1ToMMUType(RecordObject):
-    def __init__(self):
-        super().__init__()
+    def __init__(self, name=None):
+        super().__init__(name=name)
         self.valid         = Signal()
         self.tlbie         = Signal()
         self.slbia         = Signal()
@@ -78,8 +78,8 @@ class LoadStore1ToMMUType(RecordObject):
 
 
 class MMUToLoadStore1Type(RecordObject):
-    def __init__(self):
-        super().__init__()
+    def __init__(self, name=None):
+        super().__init__(name=name)
         self.done          = Signal()
         self.err           = Signal()
         self.invalid       = Signal()
@@ -102,8 +102,8 @@ class MMUToDCacheType(RecordObject):
 
 
 class MMUToICacheType(RecordObject):
-    def __init__(self):
-        super().__init__()
+    def __init__(self, name=None):
+        super().__init__(name=name)
         self.tlbld         = Signal()
         self.tlbie         = Signal()
         self.doall         = Signal()

diff --git a/src/soc/experiment/wb_types.py b/src/soc/experiment/wb_types.py
index 0f89871cb158c411d93984b9fa3ef8ceea840538..4385a3eddfb9c514693614eedc7afe45be7daa83 100644 (file)
--- a/src/soc/experiment/wb_types.py
+++ b/src/soc/experiment/wb_types.py
@@ -71,8 +71,8 @@ def WBMasterOutInit():
 #     stall : std_ulogic;
 # end record;
 class WBSlaveOut(RecordObject):
-    def __init__(self):
-        super().__init__()
+    def __init__(self, name=None):
+        super().__init__(name=name)
         self.dat   = WBDataType()
         self.ack   = Signal()
         self.stall = Signal()
@@ -104,8 +104,8 @@ def WBSlaveOutVector():
 # end record;
 # IO Bus to a device, 30-bit address, 32-bits data
 class WBIOMasterOut(RecordObject):
-    def __init__(self):
-        super().__init__()
+    def __init__(self, name=None):
+        super().__init__(name=name)
         self.adr = Signal(30)
         self.dat = Signal(32)
         self.sel = Signal(4)
@@ -119,8 +119,8 @@ class WBIOMasterOut(RecordObject):
 #     stall : std_ulogic;
 # end record;
 class WBIOSlaveOut(RecordObject):
-    def __init__(self):
-        super().__init__()
+    def __init__(self, name=None):
+        super().__init__(name=name)
         self.data  = Signal(32)
         self.ack   = Signal()
         self.stall = Signal()