check trap compunit output properly

diff --git a/src/soc/fu/compunits/test/test_trap_compunit.py b/src/soc/fu/compunits/test/test_trap_compunit.py
index 3dcf143ba9580904edcc6ae7b500279788d4e47a..4f4b44d3d7eae28ce89ec81524736cbce37c5de5 100644 (file)
--- a/src/soc/fu/compunits/test/test_trap_compunit.py
+++ b/src/soc/fu/compunits/test/test_trap_compunit.py
@@ -24,30 +24,21 @@ class TrapTestRunner(TestRunner):
         """naming (res) must conform to TrapFunctionUnit output regspec
         """
 
-        rc = yield dec2.e.do.rc.data
-        op = yield dec2.e.do.insn_type
-        cridx_ok = yield dec2.e.write_cr.ok
-        cridx = yield dec2.e.write_cr.data
-
-        print ("check extra output", repr(code), cridx_ok, cridx)
-
-        if rc:
-            self.assertEqual(cridx_ok, 1, code)
-            self.assertEqual(cridx, 0, code)
-
         sim_o = {}
 
         yield from ALUHelpers.get_sim_int_o(sim_o, sim, dec2)
-        yield from ALUHelpers.get_wr_sim_cr_a(sim_o, sim, dec2)
-        yield from ALUHelpers.get_sim_xer_ov(sim_o, sim, dec2)
-        yield from ALUHelpers.get_wr_sim_xer_ca(sim_o, sim, dec2)
-        yield from ALUHelpers.get_sim_xer_so(sim_o, sim, dec2)
-
-        ALUHelpers.check_cr_a(self, res, sim_o, "CR%d %s" % (cridx, code))
-        ALUHelpers.check_xer_ov(self, res, sim_o, code)
-        ALUHelpers.check_xer_ca(self, res, sim_o, code)
+        yield from ALUHelpers.get_wr_fast_spr1(sim_o, sim, dec2)
+        yield from ALUHelpers.get_wr_fast_spr2(sim_o, sim, dec2)
+        ALUHelpers.get_sim_nia(sim_o, sim, dec2)
+        ALUHelpers.get_sim_msr(sim_o, sim, dec2)
+
+        print ("sim output", sim_o)
+
         ALUHelpers.check_int_o(self, res, sim_o, code)
-        ALUHelpers.check_xer_so(self, res, sim_o, code)
+        ALUHelpers.check_fast_spr1(self, res, sim_o, code)
+        ALUHelpers.check_fast_spr2(self, res, sim_o, code)
+        ALUHelpers.check_nia(self, res, sim_o, code)
+        ALUHelpers.check_msr(self, res, sim_o, code)
 
 
 if __name__ == "__main__":