update trap with comments

diff --git a/src/soc/fu/trap/main_stage.py b/src/soc/fu/trap/main_stage.py
index 650dc8a8602327f847bce7e79ec885abc387e1f8..bd1611f864a5b67491bc21c4b427eb23e8b61673 100644 (file)
--- a/src/soc/fu/trap/main_stage.py
+++ b/src/soc/fu/trap/main_stage.py
@@ -73,16 +73,20 @@ class TrapMainStage(PipeModBase):
         self.fields = DecodeFields(SignalBitRange, [self.i.ctx.op.insn])
         self.fields.create_specs()
 
-    def trap(self, m, addr, trap_addr):
+    def trap(self, m, return_addr, trap_addr):
+        """trap """ # TODO add descriptive docstring
         comb  = m.d.comb
-        nia_o, srr0_o = self.o.nia, self.o.srr0
+        nia_o, srr0_o = self.o.nia, self.o.srr0 # add srr1 as well
 
+        # trap address
         comb += nia_o.data.eq(trap_addr)
         comb += nia_o.ok.eq(1)
 
-        comb += srr0_o.data.eq(addr) # addr to begin from on return
-        comb += srro_o.ok.eq(1)
+        # addr to begin from on return
+        comb += srr0_o.data.eq(return_addr)
+        comb += srro_o.ok.eq(1) # spelling
 
+        # TODO: MSR (into srr1)
 
     def ispec(self):
         return TrapInputData(self.pspec)