Implement op_bcreg

diff --git a/src/soc/branch/main_stage.py b/src/soc/branch/main_stage.py
index 7d21be6a0dcae2993c837a799fa0324fb8454c51..b2cbc37a376411e265bbe0a65d91b73c1bd6ab97 100644 (file)
--- a/src/soc/branch/main_stage.py
+++ b/src/soc/branch/main_stage.py
@@ -100,7 +100,9 @@ class BranchMainStage(PipeModBase):
                 comb += br_imm_addr.eq(br_ext(bd))
                 comb += br_taken.eq(bc_taken)
             #### branch conditional reg ####
-            # TODOwith m.Case(InternalOp.OP_BCREG):
+            with m.Case(InternalOp.OP_BCREG):
+                comb += br_imm_addr.eq(self.i.spr)
+                comb += br_taken.eq(bc_taken)
 
         ###### output next instruction address #####