add experiments10, to add C4M JTAG

diff --git a/experiments10/Makefile b/experiments10/Makefile
new file mode 100755 (executable)
index 0000000..2343504
--- /dev/null
+++ b/experiments10/Makefile
@@ -0,0 +1,43 @@
+# -*- explicit-buffer-name: "Makefile<6502/cmos45>" -*-
+
+        LOGICAL_SYNTHESIS = Yosys
+       PHYSICAL_SYNTHESIS = Coriolis
+               DESIGN_KIT = sxlib
+
+#           YOSYS_FLATTEN = Yes
+                     CHIP = chip
+                     CORE = add
+                   MARGIN = 2
+                  BOOMOPT =  # -A
+                  BOOGOPT =
+                  LOONOPT =
+                NSL2VHOPT = -vasy # -split -p
+            USE_CLOCKTREE = Yes
+                USE_DEBUG = No
+                 USE_KITE = No
+#                 RM_CHIP = Yes
+
+                 NETLISTS = $(shell cat nets.txt)
+#                PATTERNS = add_r
+
+
+ include ./mk/design-flow.mk
+
+
+blif:      add.blif
+vst:       add.vst
+
+lvx:       lvx-chip_cts_r
+druc:      druc-chip_cts_r
+dreal:     dreal-chip_cts_r
+flatph:     flatph-chip_cts_r
+view:      cgt-chip_cts_r
+
+layout:    chip_cts_r.ap
+gds:       chip_cts_r.gds
+gds_flat:  chip_cts_r_flat.gds
+cif:      chip_cts_r.cif
+
+
+view:      cgt-chip_cts_r
+sim:       asimut-add_cts_r

diff --git a/experiments10/add.py b/experiments10/add.py
new file mode 100644 (file)
index 0000000..68aecc1
--- /dev/null
+++ b/experiments10/add.py
@@ -0,0 +1,24 @@
+from nmigen import *
+from nmigen.cli import rtlil
+
+
+class ADD(Elaboratable):
+    def __init__(self, width):
+        self.a   = Signal(width)
+        self.b   = Signal(width)
+        self.f   = Signal(width)
+
+    def elaborate(self, platform):
+        m = Module()
+        m.d.sync += self.f.eq(self.a + self.b)
+        return m
+
+
+def create_ilang(dut, ports, test_name):
+    vl = rtlil.convert(dut, name=test_name, ports=ports)
+    with open("%s.il" % test_name, "w") as f:
+        f.write(vl)
+
+if __name__ == "__main__":
+    alu = ADD(width=4)
+    create_ilang(alu, [alu.a, alu.b, alu.f], "add")

diff --git a/experiments10/coriolis2/__init__.py b/experiments10/coriolis2/__init__.py
new file mode 100644 (file)
index 0000000..e69de29

diff --git a/experiments10/coriolis2/ioring.py b/experiments10/coriolis2/ioring.py
new file mode 100644 (file)
index 0000000..5b43d14
--- /dev/null
+++ b/experiments10/coriolis2/ioring.py
@@ -0,0 +1,39 @@
+#!/usr/bin/env python
+
+from helpers import l, u, n
+
+
+chip = { 'pads.ioPadGauge' : 'pxlib',
+
+      #   | Instance  | Pad   | To Core          | From Core     | Enable    |
+       'pads.instances' :[
+        # "a" input.
+        [ 'p_a0'    , 'a(0)', 'a(0)' ],
+        [ 'p_a1'    , 'a(1)', 'a(1)' ],
+        [ 'p_a2'    , 'a(2)', 'a(2)' ],
+        [ 'p_a3'    , 'a(3)', 'a(3)' ],
+        # "b" input.
+        [ 'p_b0'    , 'b(0)', 'b(0)' ],
+        [ 'p_b1'    , 'b(1)', 'b(1)' ],
+        [ 'p_b2'    , 'b(2)', 'b(2)' ],
+        [ 'p_b3'    , 'b(3)', 'b(3)' ],
+        # "f" output.
+        [ 'p_f0'    , 'f(0)',   'f(0)' ], # , 'f_oe' ],
+        [ 'p_f1'    , 'f(1)',   'f(1)' ], # , 'f_oe' ],
+        [ 'p_f2'    , 'f(2)',   'f(2)' ], # , 'f_oe' ],
+        [ 'p_f3'    , 'f(3)',   'f(3)' ], # , 'f_oe' ],
+        ],
+        'pads.south'      :
+            [ 'p_a1', 'p_vddick_0', 'p_vssick_0' , 'p_a0'       ],
+       'pads.east'       :
+            [ 'p_a2', 'p_a3'       , 'p_b3'        , 'p_b2'       ],
+       'pads.north'      :
+            [ 'p_b1', 'p_vddeck_0', 'p_b0'        , 'p_vsseck_0', 'rst' ],
+       'pads.west'       :
+            [ 'p_f3', 'p_f2'       , 'p_clk_0', 'p_f1'       , 'p_f0' ],
+       'core.size'       : ( l( 1200), l( 1200) ),
+       'chip.size'       : ( l(3200), l(3200) ),
+       'pads.useCoreSize'  : True,
+       'chip.clockTree'  : True,
+       }
+

diff --git a/experiments10/coriolis2/katana.py b/experiments10/coriolis2/katana.py
new file mode 100644 (file)
index 0000000..442b2fc
--- /dev/null
+++ b/experiments10/coriolis2/katana.py
@@ -0,0 +1,12 @@
+
+from Hurricane import DebugSession
+
+#DebugSession.addToTrace( katana.getCell().getNet( 'abc_12494_n543' ) )
+#DebugSession.addToTrace( katana.getCell().getNet( 'dl(6)' ) )
+#DebugSession.addToTrace( katana.getCell().getNet( 'n0_dl_7_0_6' ) )
+#DebugSession.addToTrace( katana.getCell().getNet( 'abc_12509_n822' ) )
+#DebugSession.addToTrace( katana.getCell().getNet( 'abc_12509_n734' ) )
+#DebugSession.addToTrace( katana.getCell().getNet( 'abc_12509_n1386' ) )
+#DebugSession.addToTrace( katana.getCell().getNet( 'abc_12494_n763' ) )
+#DebugSession.addToTrace( katana.getCell().getNet( 'abc_12494_n800' ) )
+#DebugSession.addToTrace( katana.getCell().getNet( 'abc_12491_n428_1' ) )

diff --git a/experiments10/coriolis2/settings.py b/experiments10/coriolis2/settings.py
new file mode 100644 (file)
index 0000000..85b6b47
--- /dev/null
+++ b/experiments10/coriolis2/settings.py
@@ -0,0 +1,58 @@
+# -*- Mode:Python -*-
+
+import os
+import Cfg
+import CRL
+import Viewer
+#import node180.scn6m_deep_09
+import symbolic.cmos
+from   helpers       import l, u, n
+
+
+Cfg.Configuration.pushDefaultPriority( Cfg.Parameter.Priority.UserFile )
+
+
+Viewer.Graphics.setStyle( 'Alliance.Classic [black]' )
+ 
+Cfg.getParamBool      ( 'misc.catchCore'              ).setBool      ( False   )
+Cfg.getParamBool      ( 'misc.info'                   ).setBool      ( False   )
+Cfg.getParamBool      ( 'misc.paranoid'               ).setBool      ( False   )
+Cfg.getParamBool      ( 'misc.bug'                    ).setBool      ( False   )
+Cfg.getParamBool      ( 'misc.logMode'                ).setBool      ( True   )
+Cfg.getParamBool      ( 'misc.verboseLevel1'          ).setBool      ( True    )
+Cfg.getParamBool      ( 'misc.verboseLevel2'          ).setBool      ( True    )
+#Cfg.getParamInt       ( 'misc.minTraceLevel'          ).setInt       ( 159     )
+#Cfg.getParamInt       ( 'misc.maxTraceLevel'          ).setInt       ( 160     )
+Cfg.getParamEnumerate ( 'etesian.effort'              ).setInt       ( 2       )
+Cfg.getParamPercentage( 'etesian.spaceMargin'         ).setPercentage( 20.0    )
+Cfg.getParamPercentage( 'etesian.aspectRatio'         ).setPercentage( 100.0   )
+Cfg.getParamBool      ( 'etesian.uniformDensity'      ).setBool      ( True    )
+Cfg.getParamInt       ( 'anabatic.edgeLenght'         ).setInt       ( 24      )
+Cfg.getParamInt       ( 'anabatic.edgeWidth'          ).setInt       ( 8       )
+Cfg.getParamString    ( 'anabatic.topRoutingLayer'    ).setString    ( 'METAL4')
+Cfg.getParamInt       ( 'katana.eventsLimit'          ).setInt       ( 1000000 )
+Cfg.getParamInt       ( 'katana.hTracksReservedLocal' ).setInt       ( 7       )
+Cfg.getParamInt       ( 'katana.vTracksReservedLocal' ).setInt       ( 6       )
+#Cfg.getParamInt       ( 'clockTree.minimumSide'       ).setInt       ( l(1000) )
+
+Cfg.Configuration.popDefaultPriority()
+
+#cellsTop = os.path.abspath( os.getcwd()+'/../cells' )
+if os.environ.has_key('CELLS_TOP'):
+  cellsTop = os.environ['CELLS_TOP']
+else:
+  cellsTop = '../../../cells'
+
+af  = CRL.AllianceFramework.get()
+env = af.getEnvironment()
+env.addSYSTEM_LIBRARY( library=cellsTop+'/nsxlib', mode=CRL.Environment.Prepend )
+env.addSYSTEM_LIBRARY( library=cellsTop+'/mpxlib', mode=CRL.Environment.Prepend )
+#env.setCLOCK( '^clk$|m_clock' )
+env.setCLOCK( 'clk|ck|cki' )
+env.setPOWER( 'vdd' )
+env.setGROUND( 'vss' )
+
+Cfg.Configuration.popDefaultPriority()
+
+print 'Successfully read user configuration'
+

diff --git a/experiments10/mksym.sh b/experiments10/mksym.sh
new file mode 120000 (symlink)
index 0000000..645c607
--- /dev/null
+++ b/experiments10/mksym.sh
@@ -0,0 +1 @@
+../mksym.sh
\ No newline at end of file

diff --git a/experiments10/nets.txt b/experiments10/nets.txt
new file mode 100644 (file)
index 0000000..76d4bb8
--- /dev/null
+++ b/experiments10/nets.txt
@@ -0,0 +1 @@
+add