quick hack to SRAM test and to dcache to enable classic wishbone

diff --git a/src/soc/bus/sram.py b/src/soc/bus/sram.py
index 7d63490901a041279fd16315e73a2ecd5f1353d1..9819302ff80e2ed2492efc6406bbe055dcecd901 100644 (file)
--- a/src/soc/bus/sram.py
+++ b/src/soc/bus/sram.py
@@ -99,7 +99,7 @@ class SRAM(Elaboratable):
 
         # generate ack (no "pipeline" mode here)
         m.d.sync += self.bus.ack.eq(0)
-        with m.If(self.bus.cyc & self.bus.stb):
+        with m.If(self.bus.cyc & self.bus.stb & ~self.bus.ack):
             m.d.sync += self.bus.ack.eq(1)
 
         return m

diff --git a/src/soc/experiment/dcache.py b/src/soc/experiment/dcache.py
index c81043010c1dceb26664050b7db0108eee68ef4e..7059cf83a8e2462a1b80b2423af1d837a717d179 100644 (file)
--- a/src/soc/experiment/dcache.py
+++ b/src/soc/experiment/dcache.py
@@ -1652,7 +1652,7 @@ cache_tags(r1.store_index)((i + 1) * TAG_WIDTH - 1 downto i * TAG_WIDTH) <=
         # deal with litex not doing wishbone pipeline mode
         # XXX in wrong way.  FIFOs are needed in the SRAM test
         # so that stb/ack match up
-        #comb += self.wb_in.stall.eq(self.wb_out.cyc & ~self.wb_in.ack)
+        comb += self.wb_in.stall.eq(self.wb_out.cyc & ~self.wb_in.ack)
 
         # call sub-functions putting everything together, using shared
         # signals established above