add fetch of MSR in LD/ST pipe_data

diff --git a/src/soc/fu/ldst/pipe_data.py b/src/soc/fu/ldst/pipe_data.py
index c2d8a43cb47c0096d31e34e60e243ac7f5aba8b9..fc0546a9b6c620fa6fb31deaec1aadb2320a20eb 100644 (file)
--- a/src/soc/fu/ldst/pipe_data.py
+++ b/src/soc/fu/ldst/pipe_data.py
@@ -10,6 +10,7 @@ class LDSTInputData(FUBaseData):
                ('INT', 'rb', '0:63'), # RB/immediate
                ('INT', 'rc', '0:63'), # RC
                # XXX TODO, later ('XER', 'xer_so', '32') # XER bit 32: SO
+               ('STATE', 'msr', '0:63'),  # MSR
                ]
     def __init__(self, pspec):
         super().__init__(pspec, False)