relax rv32si timer test a bit

diff --git a/isa/rv32si/timer.S b/isa/rv32si/timer.S
index d46c2fd5914fba502ddd2fead2a45c6be9c30a86..40488753112878913b81f6ff7899d94a9833ebd0 100644 (file)
--- a/isa/rv32si/timer.S
+++ b/isa/rv32si/timer.S
@@ -23,7 +23,7 @@ RVTEST_CODE_BEGIN
   csrsi status, 4 # enable interrupts
 
   li TESTNUM, 2
-  li a0,1000
+  li a0,10000
 loop:
   div x0, x0, x0
   addi a0, a0, -1
@@ -33,6 +33,7 @@ loop:
   TEST_PASSFAIL
 
 evec:
+  li TESTNUM, 3
   li t1, 0x80000000|IRQ_TIMER
   csrr t0, cause
   bne t0, t1, fail