whoops syntax error

diff --git a/src/experiment/compldst.py b/src/experiment/compldst.py
index 18acbff814cc2d2796d89f4d968bb036633747ea..77ad39dd1ace5a41406a97c4544c707cea8e4e15 100644 (file)
--- a/src/experiment/compldst.py
+++ b/src/experiment/compldst.py
@@ -215,7 +215,7 @@ class LDSTCompUnit(Elaboratable):
                 m.d.comb += self.alu.p_valid_i.eq(1) # so indicate valid
 
         # put the register directly onto the output bus on a go_write
-        with m.If((self.go_wr_i):
+        with m.If(self.go_wr_i):
             comb += self.data_o.eq(data_r)
 
         # put the register directly onto the address bus