more openpower-isa conversion

diff --git a/src/soc/fu/mmu/test/test_non_production_core.py b/src/soc/fu/mmu/test/test_non_production_core.py
index ee01ca5bfbc41c038dd738ba066026477ccd4a24..c498d71b402048bce82e2da13d12b522a367bc34 100644 (file)
--- a/src/soc/fu/mmu/test/test_non_production_core.py
+++ b/src/soc/fu/mmu/test/test_non_production_core.py
@@ -12,7 +12,7 @@ from openpower.decoder.selectable_int import SelectableInt
 from openpower.simulator.program import Program
 from openpower.decoder.isa.all import ISA
 from soc.config.endian import bigendian
-from soc.consts import MSR
+from openpower.consts import MSR
 
 
 from soc.fu.test.common import (

diff --git a/src/soc/fu/mmu/test/test_pipe_caller.py b/src/soc/fu/mmu/test/test_pipe_caller.py
index df489dbcc81b3f1647afa7740d3e354e37d40288..24d39044d849d0fcc0e51ca8360ac468c05845c3 100644 (file)
--- a/src/soc/fu/mmu/test/test_pipe_caller.py
+++ b/src/soc/fu/mmu/test/test_pipe_caller.py
@@ -14,7 +14,7 @@ from openpower.decoder.selectable_int import SelectableInt
 from openpower.simulator.program import Program
 from openpower.decoder.isa.all import ISA
 from soc.config.endian import bigendian
-from soc.consts import MSR
+from openpower.consts import MSR
 
 
 from soc.fu.test.common import (

diff --git a/src/soc/fu/shift_rot/formal/proof_main_stage.py b/src/soc/fu/shift_rot/formal/proof_main_stage.py
index dde891ecb228be041c5aef13c083aa082588b2ed..5d8bae28fd3773f655679a9596902dc6644e2511 100644 (file)
--- a/src/soc/fu/shift_rot/formal/proof_main_stage.py
+++ b/src/soc/fu/shift_rot/formal/proof_main_stage.py
@@ -16,7 +16,7 @@ from soc.fu.shift_rot.rotator import right_mask, left_mask
 from soc.fu.shift_rot.pipe_data import ShiftRotPipeSpec
 from soc.fu.shift_rot.sr_input_record import CompSROpSubset
 from openpower.decoder.power_enums import MicrOp
-from soc.consts import field
+from openpower.consts import field
 
 import unittest
 from nmutil.extend import exts

diff --git a/src/soc/fu/spr/test/test_pipe_caller.py b/src/soc/fu/spr/test/test_pipe_caller.py
index 87ba83ca70ba754f1595a04dac66ace5542f9162..1f70041c5d88ad34f1cc3f61c7ce410567cacbe7 100644 (file)
--- a/src/soc/fu/spr/test/test_pipe_caller.py
+++ b/src/soc/fu/spr/test/test_pipe_caller.py
@@ -14,7 +14,7 @@ from openpower.decoder.selectable_int import SelectableInt
 from openpower.simulator.program import Program
 from openpower.decoder.isa.all import ISA
 from soc.config.endian import bigendian
-from soc.consts import MSR
+from openpower.consts import MSR
 
 
 from soc.fu.test.common import (

diff --git a/src/soc/fu/trap/formal/proof_main_stage.py b/src/soc/fu/trap/formal/proof_main_stage.py
index c88c0ac20f584b70fe661dc5b20a96680c8f3d93..235df615a896928e43c036520acd46e6049858bf 100644 (file)
--- a/src/soc/fu/trap/formal/proof_main_stage.py
+++ b/src/soc/fu/trap/formal/proof_main_stage.py
@@ -19,7 +19,7 @@ from nmigen.cli import rtlil
 from nmutil.extend import exts
 from nmutil.formaltest import FHDLTestCase
 
-from soc.consts import MSR, MSRb, PI, TT, field
+from openpower.consts import MSR, MSRb, PI, TT, field
 
 from openpower.decoder.power_enums import MicrOp
 

diff --git a/src/soc/fu/trap/main_stage.py b/src/soc/fu/trap/main_stage.py
index 5b272e63c44a3a85568a24f7d86561d52b44c797..afc2e677dd84fa16c88505dcde051fce23ed88b4 100644 (file)
--- a/src/soc/fu/trap/main_stage.py
+++ b/src/soc/fu/trap/main_stage.py
@@ -20,7 +20,7 @@ from soc.experiment.mem_types import LDSTException
 from openpower.decoder.power_fields import DecodeFields
 from openpower.decoder.power_fieldsn import SignalBitRange
 
-from soc.consts import MSR, PI, TT, field, field_slice
+from openpower.consts import MSR, PI, TT, field, field_slice
 
 
 def msr_copy(msr_o, msr_i, zero_me=True):

diff --git a/src/soc/fu/trap/test/test_pipe_caller.py b/src/soc/fu/trap/test/test_pipe_caller.py
index f9fa09ce5a2d87251924f9a5b9456b4599d51690..b9cea5c5f2c538bca169a8c48972e42f067f275e 100644 (file)
--- a/src/soc/fu/trap/test/test_pipe_caller.py
+++ b/src/soc/fu/trap/test/test_pipe_caller.py
@@ -15,7 +15,7 @@ from openpower.decoder.selectable_int import SelectableInt
 from openpower.simulator.program import Program
 from openpower.decoder.isa.all import ISA
 from soc.config.endian import bigendian
-from soc.consts import MSR
+from openpower.consts import MSR
 
 from soc.fu.test.common import (TestAccumulatorBase, TestCase, ALUHelpers)
 from soc.fu.trap.pipeline import TrapBasePipe

diff --git a/src/soc/fu/trap/trap_input_record.py b/src/soc/fu/trap/trap_input_record.py
index 0d08f5ecb0d469ddfc5af5eadecee160eff4fb06..5b86693fd7d95d9b2bd59a316fcb3618480a3e85 100644 (file)
--- a/src/soc/fu/trap/trap_input_record.py
+++ b/src/soc/fu/trap/trap_input_record.py
@@ -1,6 +1,6 @@
 from soc.fu.base_input_record import CompOpSubsetBase
 from openpower.decoder.power_enums import (MicrOp, Function)
-from soc.consts import TT
+from openpower.consts import TT
 from soc.experiment.mem_types import LDSTException
 
 class CompTrapOpSubset(CompOpSubsetBase):

diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py
index 4afa0d7a2f3a2551c9402573b729c8c5ee3ea152..6c2e3cf6acf7b5de4f4dcfdb40b34f11a26e2b3a 100644 (file)
--- a/src/soc/simple/issuer.py
+++ b/src/soc/simple/issuer.py
@@ -27,24 +27,24 @@ from openpower.decoder.power_decoder import create_pdecode
 from openpower.decoder.power_decoder2 import PowerDecode2, SVP64PrefixDecoder
 from openpower.decoder.decode2execute1 import IssuerDecode2ToOperand
 from openpower.decoder.decode2execute1 import Data
+from openpower.decoder.power_enums import (MicrOp, SVP64PredInt, SVP64PredCR,
+                                     SVP64PredMode)
+from openpower.state import CoreState
+from openpower.consts import (CR, SVP64CROffs)
 from soc.experiment.testmem import TestMemory # test only for instructions
 from soc.regfile.regfiles import StateRegs, FastRegs
 from soc.simple.core import NonProductionCore
 from soc.config.test.test_loadstore import TestMemPspec
 from soc.config.ifetch import ConfigFetchUnit
-from openpower.decoder.power_enums import (MicrOp, SVP64PredInt, SVP64PredCR,
-                                     SVP64PredMode)
-from soc.consts import (CR, SVP64CROffs)
 from soc.debug.dmi import CoreDebug, DMIInterface
 from soc.debug.jtag import JTAG
 from soc.config.pinouts import get_pinspecs
-from soc.config.state import CoreState
 from soc.interrupts.xics import XICS_ICP, XICS_ICS
 from soc.bus.simple_gpio import SimpleGPIO
 from soc.bus.SPBlock512W64B8W import SPBlock512W64B8W
 from soc.clock.select import ClockSelect
 from soc.clock.dummypll import DummyPLL
-from soc.sv.svstate import SVSTATERec
+from openpower.sv.svstate import SVSTATERec
 
 
 from nmutil.util import rising_edge