found bug in mmu with calculating addrsh, should have been a right

shift

diff --git a/src/soc/experiment/mmu.py b/src/soc/experiment/mmu.py
index 5787f1103aa43806cbdba645f6e9cb9e4e3f7042..a245ddbd7d1af973ee09d6560279759affb04ee8 100644 (file)
--- a/src/soc/experiment/mmu.py
+++ b/src/soc/experiment/mmu.py
@@ -522,7 +522,7 @@ class MMU(Elaboratable):
 
         # Shift address bits 61--12 right by 0--47 bits and
         # supply the least significant 16 bits of the result.
-        comb += addrsh.eq(r.addr[12:62] << r.shift)
+        comb += addrsh.eq(r.addr[12:62] >> r.shift)
 
         with m.If(r.state != State.IDLE):
             sync += Display("MMU state %d %016x", r.state, data)