}
assert(num_records >= 0 && num_records <= UINT_MAX);
+ uint32_t rsrc_word3 = velems->rsrc_word3[i];
+
+ /* OOB_SELECT chooses the out-of-bounds check:
+ * - 1: index >= NUM_RECORDS (Structured)
+ * - 3: offset >= NUM_RECORDS (Raw)
+ */
+ if (sctx->chip_class >= GFX10)
+ rsrc_word3 |= S_008F0C_OOB_SELECT(vb->stride ? 1 : 3);
+
desc[0] = va;
desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) |
S_008F04_STRIDE(vb->stride);
desc[2] = num_records;
- desc[3] = velems->rsrc_word3[i];
+ desc[3] = rsrc_word3;
if (first_vb_use_mask & (1 << i)) {
radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3]));
- unsigned data_format, num_format;
- data_format = si_translate_buffer_dataformat(ctx->screen, desc, first_non_void);
- num_format = si_translate_buffer_numformat(ctx->screen, desc, first_non_void);
- v->rsrc_word3[i] |= S_008F0C_NUM_FORMAT(num_format) |
- S_008F0C_DATA_FORMAT(data_format);
+ if (sscreen->info.chip_class >= GFX10) {
+ const struct gfx10_format *fmt =
+ &gfx10_format_table[elements[i].src_format];
+ assert(fmt->img_format != 0 && fmt->img_format < 128);
+ v->rsrc_word3[i] |= S_008F0C_FORMAT(fmt->img_format) |
+ S_008F0C_RESOURCE_LEVEL(1);
+ } else {
+ unsigned data_format, num_format;
+ data_format = si_translate_buffer_dataformat(ctx->screen, desc, first_non_void);
+ num_format = si_translate_buffer_numformat(ctx->screen, desc, first_non_void);
+ v->rsrc_word3[i] |= S_008F0C_NUM_FORMAT(num_format) |
+ S_008F0C_DATA_FORMAT(data_format);
+ }
}
if (v->instance_divisor_is_fetched) {