dcbz symbol rename

diff --git a/src/soc/config/test/test_pi2ls.py b/src/soc/config/test/test_pi2ls.py
index 149d3bb7cbf3abf2876e445198e6b314e9b0b257..c9d5df38a72c72c1fc4eba84d5f096320a86097b 100644 (file)
--- a/src/soc/config/test/test_pi2ls.py
+++ b/src/soc/config/test/test_pi2ls.py
@@ -69,7 +69,7 @@ def pi_st(port1, addr, data, datalen, msr_pr=0):
     # can go straight to reset.
     yield port1.is_st_i.eq(0)  # end
     yield port1.addr.ok.eq(0)  # set !ok
-    yield port1.is_dcbz.eq(0)  # reset dcbz too
+    yield port1.is_dcbz_i.eq(0)  # reset dcbz too
 
 
 # copy of pi_st
@@ -82,7 +82,7 @@ def pi_dcbz(port1, addr, msr_pr=0):
     yield port1.is_st_i.eq(1)  # indicate ST
     yield port1.msr_pr.eq(msr_pr)  # MSR PR bit (1==>virt, 0==>real)
 
-    yield port1.is_dcbz.eq(1) # set dcbz
+    yield port1.is_dcbz_i.eq(1) # set dcbz #FIXME
 
     yield port1.addr.data.eq(addr)  # set address
     yield port1.addr.ok.eq(1)  # set ok
@@ -104,7 +104,7 @@ def pi_dcbz(port1, addr, msr_pr=0):
     # can go straight to reset.
     yield port1.is_st_i.eq(0)  # end
     yield port1.addr.ok.eq(0)  # set !ok
-    yield port1.is_dcbz.eq(0)  # reset dcbz too
+    yield port1.is_dcbz_i.eq(0)  # reset dcbz too
 
 
 def pi_ld(port1, addr, datalen, msr_pr=0):

diff --git a/src/soc/experiment/compldst_multi.py b/src/soc/experiment/compldst_multi.py
index 32e754b18e32278b553317da542bfece1858a6a6..822fe109aa0ba32e8e5fc2e385b465224b431bde 100644 (file)
--- a/src/soc/experiment/compldst_multi.py
+++ b/src/soc/experiment/compldst_multi.py
@@ -526,7 +526,7 @@ class LDSTCompUnit(RegSpecAPI, Elaboratable):
         # address: use sync to avoid long latency
         sync += pi.addr.data.eq(addr_r)           # EA from adder
         sync += Display("EA from adder %i op_is_dcbz %i",addr_r,op_is_dcbz)
-        sync += pi.is_dcbz.eq(op_is_dcbz) # set dcbz
+        ## do not use ### sync += pi.is_dcbz.eq(op_is_dcbz) # set dcbz
 
         sync += pi.addr.ok.eq(alu_ok & lsd_l.q)  # "do address stuff" (once)
         comb += self.exc_o.eq(pi.exc_o)  # exception occurred

diff --git a/src/soc/experiment/pimem.py b/src/soc/experiment/pimem.py
index 3119c3bac8db0d8de7c486579ed623ad2e02bf5b..c561357a634f9cbafe8e3f0a0561a86386c1ffca 100644 (file)
--- a/src/soc/experiment/pimem.py
+++ b/src/soc/experiment/pimem.py
@@ -100,7 +100,7 @@ class PortInterface(RecordObject):
         self.is_ld_i    = Signal(reset_less=True)
         self.is_st_i    = Signal(reset_less=True)
         self.is_dcbz_i  = Signal(reset_less=True)
-        self.is_dcbz = self.is_dcbz_i # renamed signal hack
+        ## self.is_dcbz = self.is_dcbz_i # renamed signal hack
 
         # LD/ST data length (TODO: other things may be needed)
         self.data_len = Signal(4, reset_less=True)
@@ -134,7 +134,7 @@ class PortInterface(RecordObject):
         return [self.is_ld_i.eq(inport.is_ld_i),
                 self.is_st_i.eq(inport.is_st_i),
                 self.is_nc.eq(inport.is_nc),
-                self.is_dcbz.eq(inport.is_dcbz),
+                self.is_dcbz_i.eq(inport.is_dcbz_i),
                 self.data_len.eq(inport.data_len),
                 self.go_die_i.eq(inport.go_die_i),
                 self.addr.data.eq(inport.addr.data),

diff --git a/src/soc/fu/ldst/loadstore.py b/src/soc/fu/ldst/loadstore.py
index 6cfc7c01a93a9d7d61567e72c2f4cbebc10bb845..a318b6f0ac06a2ce10d1c08d6a0d671328c38546 100644 (file)
--- a/src/soc/fu/ldst/loadstore.py
+++ b/src/soc/fu/ldst/loadstore.py
@@ -138,11 +138,6 @@ class LoadStore1(PortInterfaceBase):
         m.d.comb += self.req.virt_mode.eq(msr_pr) # problem-state ==> virt
         m.d.comb += self.req.align_intr.eq(misalign)
 
-        dcbz = self.pi.is_dcbz
-        with m.If(dcbz):
-            m.d.comb += Display("set_wr_addr: is_dcbz")
-        m.d.comb += self.req.dcbz.eq(dcbz)
-
         # option to disable the cache entirely for write
         if self.disable_cache:
             m.d.comb += self.req.nc.eq(1)