switch off internal gpio (testing)

diff --git a/src/soc/simple/issuer_verilog.py b/src/soc/simple/issuer_verilog.py
index 394913c2226b21922509f51ee372975b70305b65..820e5fd32ddfb3603efcd53b0639d1eb22080ff7 100644 (file)
--- a/src/soc/simple/issuer_verilog.py
+++ b/src/soc/simple/issuer_verilog.py
@@ -28,7 +28,7 @@ if __name__ == '__main__':
                          # set to 32 to make data wishbone bus 32-bit
                          #wb_data_wid=32,
                          xics=True,
-                         gpio=True, # for test purposes
+                         gpio=False, # for test purposes
                          debug="jtag", # set to jtag or dmi
                          units=units)