move to common ALUHelpers for branch test_pipe_caller.py

diff --git a/src/soc/fu/branch/test/test_pipe_caller.py b/src/soc/fu/branch/test/test_pipe_caller.py
index 199a5eba9e9b17adb22d3e06c73ad6c4df3e7e07..b7d5ec8a01d26c1493e9a47cf9ff6e0cab0f132f 100644 (file)
--- a/src/soc/fu/branch/test/test_pipe_caller.py
+++ b/src/soc/fu/branch/test/test_pipe_caller.py
@@ -12,7 +12,7 @@ from soc.simulator.program import Program
 from soc.decoder.isa.all import ISA
 from soc.regfile.regfiles import FastRegs
 
-from soc.fu.test.common import TestCase
+from soc.fu.test.common import TestCase, ALUHelpers
 from soc.fu.branch.pipeline import BranchBasePipe
 from soc.fu.branch.pipe_data import BranchPipeSpec
 import random
@@ -248,14 +248,10 @@ class TestRunner(FHDLTestCase):
 
         inp = yield from get_cu_inputs(dec2, sim)
 
-        if 'cia' in inp:
-            yield branch.p.data_i.cia.eq(inp['cia'])
-        if 'spr1' in inp:
-            yield branch.p.data_i.spr1.eq(inp['spr1'])
-        if 'spr2' in inp:
-            yield branch.p.data_i.spr2.eq(inp['spr2'])
-        if 'cr_a' in inp:
-            yield branch.p.data_i.cr.eq(inp['cr_a'])
+        yield from ALUHelpers.set_fast_cia(branch, dec2, inp)
+        yield from ALUHelpers.set_fast_spr1(branch, dec2, inp)
+        yield from ALUHelpers.set_fast_spr2(branch, dec2, inp)
+        yield from ALUHelpers.set_cr_a(branch, dec2, inp)
 
 
 if __name__ == "__main__":

diff --git a/src/soc/fu/test/common.py b/src/soc/fu/test/common.py
index 9d034f4b839198c618f52edce79ad57923109c9e..302d1b797e412f163f57316d307dd37896513600 100644 (file)
--- a/src/soc/fu/test/common.py
+++ b/src/soc/fu/test/common.py
@@ -43,3 +43,19 @@ class ALUHelpers:
             print ("extra inputs: so", so)
             yield alu.p.data_i.xer_so.eq(so)
 
+    def set_fast_cia(alu, dec2, inp):
+        if 'cia' in inp:
+            yield alu.p.data_i.cia.eq(inp['cia'])
+
+    def set_fast_spr1(alu, dec2, inp):
+        if 'spr1' in inp:
+            yield alu.p.data_i.spr1.eq(inp['spr1'])
+
+    def set_fast_spr2(alu, dec2, inp):
+        if 'spr2' in inp:
+            yield alu.p.data_i.spr2.eq(inp['spr2'])
+
+    def set_cr_a(alu, dec2, inp):
+        if 'cr_a' in inp:
+            yield alu.p.data_i.cr.eq(inp['cr_a'])
+