grr

diff --git a/src/ls2.py b/src/ls2.py
index ea500f5274b2afe543be878eef309f09b133be56..267f88fdd70e1a96c84d379473000fd9873c584d 100644 (file)
--- a/src/ls2.py
+++ b/src/ls2.py
@@ -273,7 +273,7 @@ class DDR3SoC(SoC, Elaboratable):
         # set up clock request generator
         pod_bits = 25
         if fpga in ['versa_ecp5', 'versa_ecp5_85', 'isim', 'ulx3s']:
-            if fpga == ['isim']:
+            if fpga in ['isim']:
                 pod_bits = 2
             self.crg = ECP5CRG(clk_freq, pod_bits)
         if fpga in ['arty_a7']: