Revert "Implement bug 278, comment 1 - better version of EXTS"

This reverts commit b5e4e847c2841189386da3509949d9206de92f8b.

diff --git a/src/soc/decoder/helpers.py b/src/soc/decoder/helpers.py
index 9cb43b269f568a0df3688e975587523c59e58709..98b3e672f16158f7dd54286c2a843664f1e7bab0 100644 (file)
--- a/src/soc/decoder/helpers.py
+++ b/src/soc/decoder/helpers.py
@@ -11,7 +11,7 @@ def EXTS(value):
     """ extends sign bit out from current MSB to all 256 bits
     """
     assert isinstance(value, SelectableInt)
-    return exts(value.value, value.bits)
+    return SelectableInt(exts(value.value, value.bits) & ((1 << 256)-1), 256)
 
 def EXTS64(value):
     """ extends sign bit out from current MSB to 64 bits

diff --git a/src/soc/decoder/isa/caller.py b/src/soc/decoder/isa/caller.py
index 5b1c4c997148f30f25cf7af60151cf870c04bcd7..874a06973f3666d63917ce2adcf4a11f4efc4690 100644 (file)
--- a/src/soc/decoder/isa/caller.py
+++ b/src/soc/decoder/isa/caller.py
@@ -110,9 +110,7 @@ class ISACaller:
         for name, output in zip(output_names, results):
             regnum = yield getattr(self.decoder, name)
             print('writing reg %d' % regnum)
-            if isinstance(output, int):
-                output = SelectableInt(output, 64)
-            self.gpr[regnum] = output
+            self.gpr[regnum] = output.narrow(64)
 
 
 def inject():

diff --git a/src/soc/decoder/isa/test_caller.py b/src/soc/decoder/isa/test_caller.py
index 12db98471e02806cd293c8603f7a2af741536d7a..aa6f23ae90f0fe318d06a99717fc9c48a5780a5c 100644 (file)
--- a/src/soc/decoder/isa/test_caller.py
+++ b/src/soc/decoder/isa/test_caller.py
@@ -9,7 +9,7 @@ from soc.simulator.program import Program
 from soc.decoder.isa.caller import ISACaller, inject
 from soc.decoder.selectable_int import SelectableInt
 from soc.decoder.orderedset import OrderedSet
-from soc.decoder.isa.all import ISA
+from soc.decoder.isa import ISA
 
 
 class Register: