format div code

diff --git a/src/soc/fu/div/formal/proof_main_stage.py b/src/soc/fu/div/formal/proof_main_stage.py
index 469127dddf4bfcee01444e3c87a591ee70bb0a96..5a2c0f8b2d18e12c43a4576e74e86f38905b6f6b 100644 (file)
--- a/src/soc/fu/div/formal/proof_main_stage.py
+++ b/src/soc/fu/div/formal/proof_main_stage.py
@@ -121,10 +121,10 @@ class Driver(Elaboratable):
                         comb += peo.eq(32)
                     with m.Else():
                         comb += peo.eq(pe32.o)
-                    with m.If(XO[-1]): # cnttzw
+                    with m.If(XO[-1]):  # cnttzw
                         comb += pe32.i.eq(a[0:32])
                         comb += Assert(dut.o.o == peo)
-                    with m.Else(): # cntlzw
+                    with m.Else():  # cntlzw
                         comb += pe32.i.eq(a[0:32][::-1])
                         comb += Assert(dut.o.o == peo)
                 with m.Else():
@@ -134,14 +134,13 @@ class Driver(Elaboratable):
                         comb += peo64.eq(64)
                     with m.Else():
                         comb += peo64.eq(pe64.o)
-                    with m.If(XO[-1]): # cnttzd
+                    with m.If(XO[-1]):  # cnttzd
                         comb += pe64.i.eq(a[0:64])
                         comb += Assert(dut.o.o == peo64)
-                    with m.Else(): # cntlzd
+                    with m.Else():  # cntlzd
                         comb += pe64.i.eq(a[0:64][::-1])
                         comb += Assert(dut.o.o == peo64)
 
-
         return m
 
 
@@ -150,6 +149,7 @@ class LogicalTestCase(FHDLTestCase):
         module = Driver()
         self.assertFormal(module, mode="bmc", depth=2)
         self.assertFormal(module, mode="cover", depth=2)
+
     def test_ilang(self):
         dut = Driver()
         vl = rtlil.convert(dut, ports=[])

diff --git a/src/soc/fu/div/input_stage.py b/src/soc/fu/div/input_stage.py
index a9ad6652cf0e2429765180cf4cab3976a3c3b2e5..01888cb2e78a820c1920d765bf7ff1d980d83074 100644 (file)
--- a/src/soc/fu/div/input_stage.py
+++ b/src/soc/fu/div/input_stage.py
@@ -6,10 +6,11 @@ from soc.fu.alu.input_stage import ALUInputStage
 from soc.fu.div.pipe_data import DIVInputData
 
 # simply over-ride ALUInputStage ispec / ospec
+
+
 class DivMulInputStage(ALUInputStage):
     def __init__(self, pspec):
         super().__init__(pspec)
 
     def ispec(self): return DIVInputData(self.pspec)
     def ospec(self): return DIVInputData(self.pspec)
-

diff --git a/src/soc/fu/div/output_stage.py b/src/soc/fu/div/output_stage.py
index 5da7f6c7244aeb4980e429875ae01fa35a508002..7348538c56a821cdf28103bf74dda52d2602fdba 100644 (file)
--- a/src/soc/fu/div/output_stage.py
+++ b/src/soc/fu/div/output_stage.py
@@ -23,7 +23,7 @@ class DivOutputStage(PipeModBase):
         self.fields.create_specs()
         self.quotient_neg = Signal()
         self.remainder_neg = Signal()
-        self.quotient_65 = Signal(65) # one extra spare bit for overflow
+        self.quotient_65 = Signal(65)  # one extra spare bit for overflow
         self.remainder_64 = Signal(64)
 
     def ispec(self):
@@ -79,12 +79,12 @@ class DivOutputStage(PipeModBase):
             ov = Signal(reset_less=True)
             with m.If(op.is_signed):
                 comb += ov.eq(overflow
-                                  | (abs_quotient > sign_bit_mask)
-                                  | ((abs_quotient == sign_bit_mask)
-                                     & ~self.quotient_neg))
+                              | (abs_quotient > sign_bit_mask)
+                              | ((abs_quotient == sign_bit_mask)
+                                 & ~self.quotient_neg))
             with m.Else():
                 comb += ov.eq(overflow)
-            comb += xer_ov.eq(Repl(ov, 2)) # set OV _and_ OV32
+            comb += xer_ov.eq(Repl(ov, 2))  # set OV _and_ OV32
 
         # check 32/64 bit version of overflow
         with m.If(op.is_32bit):
@@ -106,14 +106,14 @@ class DivOutputStage(PipeModBase):
                 comb += ov.eq(1)
         with m.Else():
             comb += ov.eq(self.i.dive_abs_ov32)
-        comb += xer_ov.eq(Repl(ov, 2)) # set OV _and_ OV32
+        comb += xer_ov.eq(Repl(ov, 2))  # set OV _and_ OV32
 
         ##########################
         # main switch for DIV
 
         o = self.o.o.data
 
-        with m.If(~ov): # result is valid (no overflow)
+        with m.If(~ov):  # result is valid (no overflow)
             with m.Switch(op.insn_type):
                 with m.Case(MicrOp.OP_DIVE):
                     with m.If(op.is_32bit):

diff --git a/src/soc/fu/div/pipe_data.py b/src/soc/fu/div/pipe_data.py
index 02f169f9304f867ffd442cbf567c6d2dc2f164b9..80a408beb81d19dd3f752ac4b7790c071e11479d 100644 (file)
--- a/src/soc/fu/div/pipe_data.py
+++ b/src/soc/fu/div/pipe_data.py
@@ -8,9 +8,10 @@ from ieee754.div_rem_sqrt_rsqrt.core import (
 
 
 class DIVInputData(IntegerData):
-    regspec = [('INT', 'ra', '0:63'), # RA
-               ('INT', 'rb', '0:63'), # RB/immediate
-               ('XER', 'xer_so', '32'),] # XER bit 32: SO
+    regspec = [('INT', 'ra', '0:63'),  # RA
+               ('INT', 'rb', '0:63'),  # RB/immediate
+               ('XER', 'xer_so', '32'), ]  # XER bit 32: SO
+
     def __init__(self, pspec):
         super().__init__(pspec, False)
         # convenience
@@ -21,15 +22,15 @@ class DIVInputData(IntegerData):
 class DivMulOutputData(IntegerData):
     regspec = [('INT', 'o', '0:63'),
                ('CR', 'cr_a', '0:3'),
-               ('XER', 'xer_ov', '33,44'), # bit0: ov, bit1: ov32
+               ('XER', 'xer_ov', '33,44'),  # bit0: ov, bit1: ov32
                ('XER', 'xer_so', '32')]
+
     def __init__(self, pspec):
         super().__init__(pspec, True)
         # convenience
         self.cr0 = self.cr_a
 
 
-
 class DIVPipeSpec(CommonPipeSpec):
     regspec = (DIVInputData.regspec, DivMulOutputData.regspec)
     opsubsetkls = CompLogicalOpSubset

diff --git a/src/soc/fu/div/pipeline.py b/src/soc/fu/div/pipeline.py
index 801cd44a995a8183398ff7f5d19ae278c45b3a5e..3fa563501c8eb4821cd08fe27fea0e08f7132ae8 100644 (file)
--- a/src/soc/fu/div/pipeline.py
+++ b/src/soc/fu/div/pipeline.py
@@ -34,7 +34,7 @@ class DivStagesEnd(PipeModBaseChain):
         core_final = DivCoreFinalStage(self.pspec)
         div_out = DivOutputStage(self.pspec)
         alu_out = DivMulOutputStage(self.pspec)
-        self.div_out = div_out # debugging - bug #425
+        self.div_out = div_out  # debugging - bug #425
         return [core_final, div_out, alu_out]
 
 

diff --git a/src/soc/fu/div/setup_stage.py b/src/soc/fu/div/setup_stage.py
index 11619fc7d22c78f5a218e9bb8468a0b6d47ad5e5..679c9cc61c9973d17a344cd1a9595a530dd31011 100644 (file)
--- a/src/soc/fu/div/setup_stage.py
+++ b/src/soc/fu/div/setup_stage.py
@@ -41,14 +41,15 @@ class DivSetupStage(PipeModBase):
         comb += core_o.operation.eq(int(DivPipeCoreOperation.UDivRem))
 
         # work out if a/b are negative (check 32-bit / signed)
-        comb += dividend_neg_o.eq(Mux(op.is_32bit, a[31], a[63]) & op.is_signed)
+        comb += dividend_neg_o.eq(Mux(op.is_32bit,
+                                      a[31], a[63]) & op.is_signed)
         comb += divisor_neg_o.eq(Mux(op.is_32bit, b[31], b[63]) & op.is_signed)
 
         # negation of a 64-bit value produces the same lower 32-bit
         # result as negation of just the lower 32-bits, so we don't
         # need to do anything special before negating
-        abs_dor = Signal(64, reset_less=True) # absolute of divisor
-        abs_dend = Signal(64, reset_less=True) # absolute of dividend
+        abs_dor = Signal(64, reset_less=True)  # absolute of divisor
+        abs_dend = Signal(64, reset_less=True)  # absolute of dividend
         comb += abs_dor.eq(Mux(divisor_neg_o, -b, b))
         comb += abs_dend.eq(Mux(dividend_neg_o, -a, a))
 

diff --git a/src/soc/fu/div/test/test_pipe_caller.py b/src/soc/fu/div/test/test_pipe_caller.py
index 204e43154626ec08988537cefb78519a0edb6037..35d211820d9936403198d030b986d0c0c4286fe7 100644 (file)
--- a/src/soc/fu/div/test/test_pipe_caller.py
+++ b/src/soc/fu/div/test/test_pipe_caller.py
@@ -17,25 +17,26 @@ from soc.fu.div.pipeline import DIVBasePipe
 from soc.fu.div.pipe_data import DIVPipeSpec
 import random
 
+
 def log_rand(n, min_val=1):
     logrange = random.randint(1, n)
-    return random.randint(min_val, (1<<logrange)-1)
+    return random.randint(min_val, (1 << logrange)-1)
+
 
 def get_cu_inputs(dec2, sim):
     """naming (res) must conform to DIVFunctionUnit input regspec
     """
     res = {}
 
-    yield from ALUHelpers.get_sim_int_ra(res, sim, dec2) # RA
-    yield from ALUHelpers.get_sim_int_rb(res, sim, dec2) # RB
-    yield from ALUHelpers.get_sim_xer_so(res, sim, dec2) # XER.so
+    yield from ALUHelpers.get_sim_int_ra(res, sim, dec2)  # RA
+    yield from ALUHelpers.get_sim_int_rb(res, sim, dec2)  # RB
+    yield from ALUHelpers.get_sim_xer_so(res, sim, dec2)  # XER.so
 
-    print ("alu get_cu_inputs", res)
+    print("alu get_cu_inputs", res)
 
     return res
 
 
-
 def set_alu_inputs(alu, dec2, sim):
     # TODO: see https://bugs.libre-soc.org/show_bug.cgi?id=305#c43
     # detect the immediate here (with m.If(self.i.ctx.op.imm_data.imm_ok))
@@ -154,7 +155,7 @@ class DIVTestCase(FHDLTestCase):
         lst = ["divw. 3, 1, 2"]
         initial_regs = [0] * 32
         initial_regs[1] = 0x80000000
-        initial_regs[2] = 0xffffffffffffffff # top bits don't seem to matter
+        initial_regs[2] = 0xffffffffffffffff  # top bits don't seem to matter
         self.run_tst_program(Program(lst, bigendian), initial_regs)
 
     def tst_divw_overflow3(self):
@@ -229,14 +230,15 @@ class TestRunner(FHDLTestCase):
         sim = Simulator(m)
 
         sim.add_clock(1e-6)
+
         def process():
             for test in self.test_data:
                 print(test.name)
                 program = test.program
                 self.subTest(test.name)
                 sim = ISA(pdecode2, test.regs, test.sprs, test.cr,
-                                test.mem, test.msr,
-                                bigendian=bigendian)
+                          test.mem, test.msr,
+                          bigendian=bigendian)
                 gen = program.generate_instructions()
                 instructions = list(zip(gen, program.assembly.splitlines()))
                 yield Settle()
@@ -251,7 +253,7 @@ class TestRunner(FHDLTestCase):
                         so = 1 if sim.spr['XER'][XER_bits['SO']] else 0
                         ov = 1 if sim.spr['XER'][XER_bits['OV']] else 0
                         ov32 = 1 if sim.spr['XER'][XER_bits['OV32']] else 0
-                        print ("before: so/ov/32", so, ov, ov32)
+                        print("before: so/ov/32", so, ov, ov32)
 
                     # ask the decoder to decode this binary data (endian'd)
                     yield pdecode2.dec.bigendian.eq(bigendian)  # little / big?
@@ -284,14 +286,14 @@ class TestRunner(FHDLTestCase):
                         dive_abs_ov32 = yield do.i.dive_abs_ov32
                         div_by_zero = yield do.i.div_by_zero
                         quotient_neg = yield do.quotient_neg
-                        print ("32bit", hex(is_32bit))
-                        print ("signed", hex(is_signed))
-                        print ("quotient_root", hex(quotient_root))
-                        print ("quotient_65", hex(quotient_65))
-                        print ("div_by_zero", hex(div_by_zero))
-                        print ("dive_abs_ov32", hex(dive_abs_ov32))
-                        print ("quotient_neg", hex(quotient_neg))
-                        print ("")
+                        print("32bit", hex(is_32bit))
+                        print("signed", hex(is_signed))
+                        print("quotient_root", hex(quotient_root))
+                        print("quotient_65", hex(quotient_65))
+                        print("div_by_zero", hex(div_by_zero))
+                        print("dive_abs_ov32", hex(dive_abs_ov32))
+                        print("quotient_neg", hex(quotient_neg))
+                        print("")
                     yield
 
                     yield from self.check_alu_outputs(alu, pdecode2, sim, code)
@@ -299,7 +301,7 @@ class TestRunner(FHDLTestCase):
 
         sim.add_sync_process(process)
         with sim.write_vcd("div_simulator.vcd", "div_simulator.gtkw",
-                            traces=[]):
+                           traces=[]):
             sim.run()
 
     def check_alu_outputs(self, alu, dec2, sim, code):
@@ -308,7 +310,7 @@ class TestRunner(FHDLTestCase):
         cridx_ok = yield dec2.e.write_cr.ok
         cridx = yield dec2.e.write_cr.data
 
-        print ("check extra output", repr(code), cridx_ok, cridx)
+        print("check extra output", repr(code), cridx_ok, cridx)
         if rc:
             self.assertEqual(cridx, 0, code)
 
@@ -320,14 +322,14 @@ class TestRunner(FHDLTestCase):
         yield from ALUHelpers.get_int_o(res, alu, dec2)
         yield from ALUHelpers.get_xer_so(res, alu, dec2)
 
-        print ("res output", res)
+        print("res output", res)
 
         yield from ALUHelpers.get_sim_int_o(sim_o, sim, dec2)
         yield from ALUHelpers.get_wr_sim_cr_a(sim_o, sim, dec2)
         yield from ALUHelpers.get_sim_xer_ov(sim_o, sim, dec2)
         yield from ALUHelpers.get_sim_xer_so(sim_o, sim, dec2)
 
-        print ("sim output", sim_o)
+        print("sim output", sim_o)
 
         ALUHelpers.check_int_o(self, res, sim_o, code)
         ALUHelpers.check_cr_a(self, res, sim_o, "CR%d %s" % (cridx, code))
@@ -336,12 +338,12 @@ class TestRunner(FHDLTestCase):
 
         oe = yield dec2.e.do.oe.oe
         oe_ok = yield dec2.e.do.oe.ok
-        print ("oe, oe_ok", oe, oe_ok)
+        print("oe, oe_ok", oe, oe_ok)
         if not oe or not oe_ok:
             # if OE not enabled, XER SO and OV must not be activated
             so_ok = yield alu.n.data_o.xer_so.ok
             ov_ok = yield alu.n.data_o.xer_ov.ok
-            print ("so, ov", so_ok, ov_ok)
+            print("so, ov", so_ok, ov_ok)
             self.assertEqual(ov_ok, False, code)
             self.assertEqual(so_ok, False, code)