from copy import deepcopy
+def namesuffix(name, suffix, namelist):
+ names = []
+ for n in namelist:
+ if n:
+ names.append("%s%s_%s" % (name, suffix, n))
+ else:
+ names.append("%s_%s" % (name, suffix))
+ return names
+
class Pinouts(object):
- def __init__(self):
+ def __init__(self, bankspec):
+ self.bankspec = bankspec
self.pins = {}
self.fnspec = {}
return self.pins[k]
+ def i2s(self, suffix, offs, bank, mux=1, spec=None, limit=None):
+ i2spins = ['MCK+', 'BCK+', 'LRCK+', 'DI-', 'DO+']
+ # for i in range(4):
+ # i2spins.append("DO%d+" % i)
+ pins = Pins('IIS', i2spins, self.bankspec, suffix, offs, bank, mux, spec, limit,
+ origsuffix=suffix)
+ self.pinmerge(pins)
+
+
+ def emmc(self, suffix, offs, bank, mux=1, spec=None):
+ emmcpins = ['CMD+', 'CLK+']
+ for i in range(8):
+ emmcpins.append("D%d*" % i)
+ pins = Pins('MMC', emmcpins, self.bankspec, suffix, offs, bank, mux, spec,
+ origsuffix=suffix)
+ self.pinmerge(pins)
+
+
+ def sdmmc(self, suffix, offs, bank, mux=1, spec=None,
+ start=None, limit=None):
+ sdmmcpins = ['CMD+', 'CLK+']
+ for i in range(4):
+ sdmmcpins.append("D%d*" % i)
+ sdmmcpins = sdmmcpins[start:limit]
+ pins = Pins('SD', sdmmcpins, self.bankspec, suffix, offs, bank, mux, spec,
+ origsuffix=suffix)
+ self.pinmerge(pins)
+
+
+ def spi(self, suffix, offs, bank, mux=1, spec=None):
+ spipins = ['CLK*', 'NSS*', 'MOSI*', 'MISO*']
+ pins = Pins('SPI', spipins, self.bankspec, suffix, offs, bank, mux, spec,
+ origsuffix=suffix)
+ self.pinmerge(pins)
+
+
+ def quadspi(self, suffix, offs, bank, mux=1, spec=None, limit=None):
+ spipins = ['CK*', 'NSS*', 'IO0*', 'IO1*', 'IO2*', 'IO3*']
+ pins = Pins(
+ 'QSPI',
+ spipins,
+ self.bankspec,
+ suffix,
+ offs,
+ bank,
+ mux,
+ spec,
+ limit,
+ origsuffix=suffix)
+ self.pinmerge(pins)
+
+
+ def i2c(self, suffix, offs, bank, mux=1, spec=None):
+ spipins = ['SDA*', 'SCL*']
+ pins = Pins('TWI', spipins, self.bankspec, suffix, offs, bank, mux, spec,
+ origsuffix=suffix)
+ self.pinmerge(pins)
+
+
+ def jtag(self, suffix, offs, bank, mux=1, spec=None):
+ jtagpins = ['MS+', 'DI-', 'DO+', 'CK+']
+ pins = Pins('JTAG', jtagpins, self.bankspec, suffix, offs, bank, mux, spec,
+ origsuffix=suffix)
+ self.pinmerge(pins)
+
+
+ def uart(self, suffix, offs, bank, mux=1, spec=None):
+ uartpins = ['TX+', 'RX-']
+ pins = Pins('UART', uartpins, self.bankspec, suffix, offs, bank, mux, spec,
+ origsuffix=suffix)
+ self.pinmerge(pins)
+
+
+
+ def ulpi(self, suffix, offs, bank, mux=1, spec=None):
+ ulpipins = ['CK+', 'DIR+', 'STP+', 'NXT+']
+ for i in range(8):
+ ulpipins.append('D%d*' % i)
+ pins = Pins('ULPI', ulpipins, self.bankspec, suffix, offs, bank, mux, spec,
+ origsuffix=suffix)
+ self.pinmerge(pins)
+
+
+ def uartfull(self, suffix, offs, bank, mux=1, spec=None):
+ uartpins = ['TX+', 'RX-', 'CTS-', 'RTS+']
+ pins = Pins('UARTQ', uartpins, self.bankspec, suffix, offs, bank, mux, spec,
+ origsuffix=suffix)
+ self.pinmerge(pins)
+
+
+ def rgbttl(self, suffix, offs, bank, mux=1, spec=None):
+ ttlpins = ['CK+', 'DE+', 'HS+', 'VS+']
+ for i in range(24):
+ ttlpins.append("D%d+" % i)
+ pins = Pins('LCD', ttlpins, self.bankspec, suffix, offs, bank, mux, spec,
+ origsuffix=suffix)
+ self.pinmerge(pins)
+
+
+ def rgmii(self, suffix, offs, bank, mux=1, spec=None):
+ buspins = []
+ for i in range(4):
+ buspins.append("ERXD%d-" % i)
+ for i in range(4):
+ buspins.append("ETXD%d+" % i)
+ buspins += ['ERXCK-', 'ERXERR-', 'ERXDV-',
+ 'EMDC+', 'EMDIO*',
+ 'ETXEN+', 'ETXCK+', 'ECRS-',
+ 'ECOL+', 'ETXERR+']
+ pins = Pins('RG', buspins, self.bankspec, suffix, offs, bank, mux, spec,
+ origsuffix=suffix)
+ self.pinmerge(pins)
+
+
+ def flexbus1(self, suffix, offs, bank, mux=1, spec=None, limit=None):
+ buspins = []
+ for i in range(8):
+ buspins.append("AD%d*" % i)
+ for i in range(2):
+ buspins.append("CS%d+" % i)
+ buspins += ['ALE', 'OE', 'RW', 'TA', 'CLK+',
+ 'A0', 'A1', 'TS', 'TBST',
+ 'TSIZ0', 'TSIZ1']
+ for i in range(4):
+ buspins.append("BWE%d" % i)
+ for i in range(2, 6):
+ buspins.append("CS%d+" % i)
+ pins = Pins('FB', buspins, self.bankspec, suffix, offs, bank, mux, spec, limit,
+ origsuffix=suffix)
+ self.pinmerge(pins)
+
+
+ def flexbus2(self, suffix, offs, bank, mux=1, spec=None, limit=None):
+ buspins = []
+ for i in range(8, 32):
+ buspins.append("AD%d*" % i)
+ pins = Pins('FB', buspins, self.bankspec, suffix, offs, bank, mux, spec, limit,
+ origsuffix=suffix)
+ self.pinmerge(pins)
+
+
+ def sdram1(self, suffix, offs, bank, mux=1, spec=None):
+ buspins = []
+ for i in range(16):
+ buspins.append("SDRDQM%d*" % i)
+ for i in range(12):
+ buspins.append("SDRAD%d+" % i)
+ for i in range(8):
+ buspins.append("SDRDQ%d+" % i)
+ for i in range(3):
+ buspins.append("SDRCS%d#+" % i)
+ for i in range(2):
+ buspins.append("SDRDQ%d+" % i)
+ for i in range(2):
+ buspins.append("SDRBA%d+" % i)
+ buspins += ['SDRCKE+', 'SDRRAS#+', 'SDRCAS#+', 'SDRWE#+',
+ 'SDRRST+']
+ pins = Pins('SDR', buspins, self.bankspec, suffix, offs, bank, mux, spec,
+ origsuffix=suffix)
+ self.pinmerge(pins)
+
+ def sdram2(self, suffix, offs, bank, mux=1, spec=None, limit=None):
+ buspins = []
+ for i in range(3, 6):
+ buspins.append("SDRCS%d#+" % i)
+ for i in range(8, 32):
+ buspins.append("SDRDQ%d*" % i)
+ pins = Pins('SDR', buspins, self.bankspec, suffix, offs, bank, mux, spec,
+ limit,
+ origsuffix=suffix)
+ self.pinmerge(pins)
+
+ def mcu8080(self, suffix, offs, bank, mux=1, spec=None):
+ buspins = []
+ for i in range(8):
+ buspins.append("MCUD%d*" % i)
+ for i in range(8):
+ buspins.append("MCUAD%d+" % (i + 8))
+ for i in range(6):
+ buspins.append("MCUCS%d+" % i)
+ for i in range(2):
+ buspins.append("MCUNRB%d+" % i)
+ buspins += ['MCUCD+', 'MCURD+', 'MCUWR+', 'MCUCLE+', 'MCUALE+',
+ 'MCURST+']
+ pins = Pins('MCU', buspins, self.bankspec, suffix, offs, bank, mux, spec,
+ origsuffix=suffix)
+ self.pinmerge(pins)
+
+ def _pinbank(self, prefix, suffix, offs, bank, gpiooffs, gpionum=1, mux=1,
+ spec=None):
+ gpiopins = []
+ for i in range(gpiooffs, gpiooffs + gpionum):
+ gpiopins.append("%s%d*" % (bank, i))
+ pins = Pins(prefix, gpiopins, self.bankspec, suffix, offs, bank, mux, spec,
+ origsuffix=suffix)
+ self.pinmerge(pins)
+
+ def eint(self, suffix, offs, bank, gpiooffs, gpionum=1, mux=1, spec=None):
+ gpiopins = []
+ for i in range(gpiooffs, gpiooffs + gpionum):
+ gpiopins.append("%d*" % (i))
+ pins = Pins('EINT', gpiopins, self.bankspec, suffix, offs, bank, mux, spec,
+ origsuffix=suffix)
+ self.pinmerge(pins)
+
+ def pwm(self, suffix, offs, bank, pwmoffs, pwmnum=1, mux=1, spec=None):
+ pwmpins = []
+ for i in range(pwmoffs, pwmoffs + pwmnum):
+ pwmpins.append("%d+" % (i))
+ pins = Pins('PWM', pwmpins, self.bankspec, suffix, offs, bank, mux, spec,
+ origsuffix=suffix)
+ self.pinmerge(pins)
+
+
+ def gpio(self, suffix, offs, bank, gpiooffs, gpionum=1, mux=1, spec=None):
+ self._pinbank("GPIO%s" % bank, suffix, offs, bank, gpiooffs,
+ gpionum, mux=0, spec=None)
+
+
+ def pinmerge(self, fn):
+ # hack, store the function specs in the pins dict
+ fname = fn.fname
+ suffix = fn.origsuffix
+ bank = fn.bank
+
+ if not hasattr(self, 'fnspec'):
+ self.fnspec = pins
+ if fname == 'GPIO':
+ fname = fname + bank
+ assert 'EINT' not in self
+ if fname not in self.fnspec:
+ self.add_spec(fname, {})
+ if suffix or fname == 'EINT' or fname == 'PWM':
+ specname = fname + suffix
+ else:
+ specname = fname
+ print "fname bank specname suffix ", fname, bank, specname, repr(suffix)
+ if specname in self.fnspec[fname]:
+ # ok so some declarations may bring in different
+ # names at different stages (EINT, PWM, flexbus1/2)
+ # so we have to merge the names in. main thing is
+ # the pingroup
+ tomerge = self.fnspec[fname][specname]
+ for p in fn.pingroup:
+ if p not in tomerge.pingroup:
+ tomerge.pingroup.append(p)
+ tomerge.pins.update(fn.pins)
+ tomerge.fntype.update(fn.fntype)
+ else:
+ self.fnspec[fname][specname] = deepcopy(fn)
+
+ # merge actual pins
+ for (pinidx, v) in fn.pins.items():
+ self.update(pinidx, v)
+
+
class Pins(object):
def __init__(self, fname, pingroup, bankspec, suffix, offs, bank, mux,
self.pins = res
-
-def i2s(bankspec, suffix, offs, bank, mux=1, spec=None, limit=None):
- i2spins = ['MCK+', 'BCK+', 'LRCK+', 'DI-', 'DO+']
- # for i in range(4):
- # i2spins.append("DO%d+" % i)
- return Pins('IIS', i2spins, bankspec, suffix, offs, bank, mux, spec, limit,
- origsuffix=suffix)
-
-
-def emmc(bankspec, suffix, offs, bank, mux=1, spec=None):
- emmcpins = ['CMD+', 'CLK+']
- for i in range(8):
- emmcpins.append("D%d*" % i)
- return Pins('MMC', emmcpins, bankspec, suffix, offs, bank, mux, spec,
- origsuffix=suffix)
-
-
-def sdmmc(bankspec, suffix, offs, bank, mux=1, spec=None,
- start=None, limit=None):
- sdmmcpins = ['CMD+', 'CLK+']
- for i in range(4):
- sdmmcpins.append("D%d*" % i)
- sdmmcpins = sdmmcpins[start:limit]
- return Pins('SD', sdmmcpins, bankspec, suffix, offs, bank, mux, spec,
- origsuffix=suffix)
-
-
-def spi(bankspec, suffix, offs, bank, mux=1, spec=None):
- spipins = ['CLK*', 'NSS*', 'MOSI*', 'MISO*']
- return Pins('SPI', spipins, bankspec, suffix, offs, bank, mux, spec,
- origsuffix=suffix)
-
-
-def quadspi(bankspec, suffix, offs, bank, mux=1, spec=None, limit=None):
- spipins = ['CK*', 'NSS*', 'IO0*', 'IO1*', 'IO2*', 'IO3*']
- return Pins(
- 'QSPI',
- spipins,
- bankspec,
- suffix,
- offs,
- bank,
- mux,
- spec,
- limit,
- origsuffix=suffix)
-
-
-def i2c(bankspec, suffix, offs, bank, mux=1, spec=None):
- spipins = ['SDA*', 'SCL*']
- return Pins('TWI', spipins, bankspec, suffix, offs, bank, mux, spec,
- origsuffix=suffix)
-
-
-def jtag(bankspec, suffix, offs, bank, mux=1, spec=None):
- jtagpins = ['MS+', 'DI-', 'DO+', 'CK+']
- return Pins('JTAG', jtagpins, bankspec, suffix, offs, bank, mux, spec,
- origsuffix=suffix)
-
-
-def uart(bankspec, suffix, offs, bank, mux=1, spec=None):
- uartpins = ['TX+', 'RX-']
- return Pins('UART', uartpins, bankspec, suffix, offs, bank, mux, spec,
- origsuffix=suffix)
-
-
-def namesuffix(name, suffix, namelist):
- names = []
- for n in namelist:
- if n:
- names.append("%s%s_%s" % (name, suffix, n))
- else:
- names.append("%s_%s" % (name, suffix))
- return names
-
-
-def ulpi(bankspec, suffix, offs, bank, mux=1, spec=None):
- ulpipins = ['CK+', 'DIR+', 'STP+', 'NXT+']
- for i in range(8):
- ulpipins.append('D%d*' % i)
- return Pins('ULPI', ulpipins, bankspec, suffix, offs, bank, mux, spec,
- origsuffix=suffix)
-
-
-def uartfull(bankspec, suffix, offs, bank, mux=1, spec=None):
- uartpins = ['TX+', 'RX-', 'CTS-', 'RTS+']
- return Pins('UARTQ', uartpins, bankspec, suffix, offs, bank, mux, spec,
- origsuffix=suffix)
-
-
-def rgbttl(bankspec, suffix, offs, bank, mux=1, spec=None):
- ttlpins = ['CK+', 'DE+', 'HS+', 'VS+']
- for i in range(24):
- ttlpins.append("D%d+" % i)
- return Pins('LCD', ttlpins, bankspec, suffix, offs, bank, mux, spec,
- origsuffix=suffix)
-
-
-def rgmii(bankspec, suffix, offs, bank, mux=1, spec=None):
- buspins = []
- for i in range(4):
- buspins.append("ERXD%d-" % i)
- for i in range(4):
- buspins.append("ETXD%d+" % i)
- buspins += ['ERXCK-', 'ERXERR-', 'ERXDV-',
- 'EMDC+', 'EMDIO*',
- 'ETXEN+', 'ETXCK+', 'ECRS-',
- 'ECOL+', 'ETXERR+']
- return Pins('RG', buspins, bankspec, suffix, offs, bank, mux, spec,
- origsuffix=suffix)
-
-
-def flexbus1(bankspec, suffix, offs, bank, mux=1, spec=None, limit=None):
- buspins = []
- for i in range(8):
- buspins.append("AD%d*" % i)
- for i in range(2):
- buspins.append("CS%d+" % i)
- buspins += ['ALE', 'OE', 'RW', 'TA', 'CLK+',
- 'A0', 'A1', 'TS', 'TBST',
- 'TSIZ0', 'TSIZ1']
- for i in range(4):
- buspins.append("BWE%d" % i)
- for i in range(2, 6):
- buspins.append("CS%d+" % i)
- return Pins('FB', buspins, bankspec, suffix, offs, bank, mux, spec, limit,
- origsuffix=suffix)
-
-
-def flexbus2(bankspec, suffix, offs, bank, mux=1, spec=None, limit=None):
- buspins = []
- for i in range(8, 32):
- buspins.append("AD%d*" % i)
- return Pins('FB', buspins, bankspec, suffix, offs, bank, mux, spec, limit,
- origsuffix=suffix)
-
-
-def sdram1(bankspec, suffix, offs, bank, mux=1, spec=None):
- buspins = []
- for i in range(16):
- buspins.append("SDRDQM%d*" % i)
- for i in range(12):
- buspins.append("SDRAD%d+" % i)
- for i in range(8):
- buspins.append("SDRDQ%d+" % i)
- for i in range(3):
- buspins.append("SDRCS%d#+" % i)
- for i in range(2):
- buspins.append("SDRDQ%d+" % i)
- for i in range(2):
- buspins.append("SDRBA%d+" % i)
- buspins += ['SDRCKE+', 'SDRRAS#+', 'SDRCAS#+', 'SDRWE#+',
- 'SDRRST+']
- return Pins('SDR', buspins, bankspec, suffix, offs, bank, mux, spec,
- origsuffix=suffix)
-
-
-def sdram2(bankspec, suffix, offs, bank, mux=1, spec=None, limit=None):
- buspins = []
- for i in range(3, 6):
- buspins.append("SDRCS%d#+" % i)
- for i in range(8, 32):
- buspins.append("SDRDQ%d*" % i)
- return Pins('SDR', buspins, bankspec, suffix, offs, bank, mux, spec, limit,
- origsuffix=suffix)
-
-
-def mcu8080(bankspec, suffix, offs, bank, mux=1, spec=None):
- buspins = []
- for i in range(8):
- buspins.append("MCUD%d*" % i)
- for i in range(8):
- buspins.append("MCUAD%d+" % (i + 8))
- for i in range(6):
- buspins.append("MCUCS%d+" % i)
- for i in range(2):
- buspins.append("MCUNRB%d+" % i)
- buspins += ['MCUCD+', 'MCURD+', 'MCUWR+', 'MCUCLE+', 'MCUALE+',
- 'MCURST+']
- return Pins('MCU', buspins, bankspec, suffix, offs, bank, mux, spec,
- origsuffix=suffix)
-
-
-def _pinbank(bankspec, prefix, suffix, offs, bank, gpiooffs, gpionum=1, mux=1,
- spec=None):
- gpiopins = []
- for i in range(gpiooffs, gpiooffs + gpionum):
- gpiopins.append("%s%d*" % (bank, i))
- return Pins(prefix, gpiopins, bankspec, suffix, offs, bank, mux, spec,
- origsuffix=suffix)
-
-
-def eint(bankspec, suffix, offs, bank, gpiooffs, gpionum=1, mux=1, spec=None):
- gpiopins = []
- for i in range(gpiooffs, gpiooffs + gpionum):
- gpiopins.append("%d*" % (i))
- return Pins('EINT', gpiopins, bankspec, suffix, offs, bank, mux, spec,
- origsuffix=suffix)
-
-
-def pwm(bankspec, suffix, offs, bank, pwmoffs, pwmnum=1, mux=1, spec=None):
- pwmpins = []
- for i in range(pwmoffs, pwmoffs + pwmnum):
- pwmpins.append("%d+" % (i))
- return Pins('PWM', pwmpins, bankspec, suffix, offs, bank, mux, spec,
- origsuffix=suffix)
-
-
-def gpio(bankspec, suffix, offs, bank, gpiooffs, gpionum=1, mux=1, spec=None):
- return _pinbank(bankspec, "GPIO%s" % bank, suffix, offs, bank, gpiooffs,
- gpionum, mux=0, spec=None)
-
-
-def pinmerge(pins, fn):
- # hack, store the function specs in the pins dict
- fname = fn.fname
- suffix = fn.origsuffix
- bank = fn.bank
-
- if not hasattr(pins, 'fnspec'):
- pins.fnspec = pins
- if fname == 'GPIO':
- fname = fname + bank
- assert 'EINT' not in pins
- if fname not in pins.fnspec:
- pins.add_spec(fname, {})
- if suffix or fname == 'EINT' or fname == 'PWM':
- specname = fname + suffix
- else:
- specname = fname
- print "fname bank specname suffix ", fname, bank, specname, repr(suffix)
- if specname in pins.fnspec[fname]:
- # ok so some declarations may bring in different
- # names at different stages (EINT, PWM, flexbus1/2)
- # so we have to merge the names in. main thing is
- # the pingroup
- tomerge = pins.fnspec[fname][specname]
- for p in fn.pingroup:
- if p not in tomerge.pingroup:
- tomerge.pingroup.append(p)
- tomerge.pins.update(fn.pins)
- tomerge.fntype.update(fn.fntype)
- else:
- pins.fnspec[fname][specname] = deepcopy(fn)
-
- # merge actual pins
- for (pinidx, v) in fn.pins.items():
- pins.update(pinidx, v)
#!/usr/bin/env python
-from spec.interfaces import jtag, uart, ulpi, uartfull, rgbttl, rgmii
-from spec.interfaces import flexbus1, flexbus2, sdram1, sdram2, mcu8080
-from spec.interfaces import eint, pwm, gpio, spi, i2c, emmc, sdmmc
-from spec.interfaces import quadspi, i2s
-from spec.interfaces import pinmerge, Pinouts
+from spec.interfaces import Pinouts
from spec.ifaceprint import display, display_fns, check_functions
from spec.ifaceprint import display_fixed
def pinspec():
- pinouts = Pinouts()
-
pinbanks = {'A': 16,
'B': 28,
'C': 24,
bankspec[kn] = offs
offs += pinbanks[kn]
+ pinouts = Pinouts(bankspec)
+
# Bank A, 0-15
- pinmerge(pinouts, gpio(bankspec, "", ('A', 0), "A", 0, 16, 0))
- pinmerge(pinouts, spi(bankspec, "1", ('A', 0), "A", 3))
- pinmerge(pinouts, uartfull(bankspec, "1", ('A', 0), "A", 2))
- pinmerge(pinouts, i2c(bankspec, "1", ('A', 4), "A", 2))
- pinmerge(pinouts, emmc(bankspec, "", ('A', 0), "A", 1))
- #pinmerge(pinouts, uart(bankspec, "2", ('A', 14), "A", 1))
- pinmerge(pinouts, spi(bankspec, "2", ('A', 6), "A", 2))
- pinmerge(pinouts, eint(bankspec, "", ('A', 10), "A", 0, 6))
- pinmerge(pinouts, eint(bankspec, "", ('A', 4), "A", 0, 6, mux=3))
- pinmerge(pinouts, sdmmc(bankspec, "1", ('A', 10), "A", 2))
- pinmerge(pinouts, jtag(bankspec, "1", ('A', 10), "A", 3))
- pinmerge(pinouts, uart(bankspec, "2", ('A', 14), "A", 3))
+ pinouts.gpio("", ('A', 0), "A", 0, 16, 0)
+ pinouts.spi("1", ('A', 0), "A", 3)
+ pinouts.uartfull("1", ('A', 0), "A", 2)
+ pinouts.i2c("1", ('A', 4), "A", 2)
+ pinouts.emmc("", ('A', 0), "A", 1)
+ #pinouts.uart("2", ('A', 14), "A", 1)
+ pinouts.spi("2", ('A', 6), "A", 2)
+ pinouts.eint("", ('A', 10), "A", 0, 6)
+ pinouts.eint("", ('A', 4), "A", 0, 6, mux=3)
+ pinouts.sdmmc("1", ('A', 10), "A", 2)
+ pinouts.jtag("1", ('A', 10), "A", 3)
+ pinouts.uart("2", ('A', 14), "A", 3)
# Bank B, 16-47
- pinmerge(pinouts, gpio(bankspec, "", ('B', 0), "B", 0, 28, 0))
- pinmerge(pinouts, rgbttl(bankspec, "0", ('B', 0), "B", 1))
- pinmerge(pinouts, spi(bankspec, "1", ('B', 12), "B", 2))
- pinmerge(pinouts, quadspi(bankspec, "", ('B', 4), "B", 2, limit=4))
- pinmerge(pinouts, uart(bankspec, "3", ('B', 16), "B", 2))
- pinmerge(pinouts, i2c(bankspec, "3", ('B', 18), "B", 2))
- pinmerge(pinouts, pwm(bankspec, "", ('B', 9), "B", 0, 1, mux=2))
- pinmerge(pinouts, pwm(bankspec, "", ('B', 20), "B", 1, 2, mux=2))
- pinmerge(pinouts, sdmmc(bankspec, "1", ('B', 22), "B", 2))
- pinmerge(pinouts, eint(bankspec, "", ('B', 0), "B", 6, 4, mux=3))
- pinmerge(pinouts, flexbus2(bankspec, "", ('B', 4), "B", 3))
- pinmerge(pinouts, i2c(bankspec, "1", ('B', 0), "B", 2))
- pinmerge(pinouts, uart(bankspec, "2", ('B', 2), "B", 2))
- pinmerge(pinouts, uart(bankspec, "4", ('B', 10), "B", 2))
+ pinouts.gpio("", ('B', 0), "B", 0, 28, 0)
+ pinouts.rgbttl("0", ('B', 0), "B", 1)
+ pinouts.spi("1", ('B', 12), "B", 2)
+ pinouts.quadspi("", ('B', 4), "B", 2, limit=4)
+ pinouts.uart("3", ('B', 16), "B", 2)
+ pinouts.i2c("3", ('B', 18), "B", 2)
+ pinouts.pwm("", ('B', 9), "B", 0, 1, mux=2)
+ pinouts.pwm("", ('B', 20), "B", 1, 2, mux=2)
+ pinouts.sdmmc("1", ('B', 22), "B", 2)
+ pinouts.eint("", ('B', 0), "B", 6, 4, mux=3)
+ pinouts.flexbus2("", ('B', 4), "B", 3)
+ pinouts.i2c("1", ('B', 0), "B", 2)
+ pinouts.uart("2", ('B', 2), "B", 2)
+ pinouts.uart("4", ('B', 10), "B", 2)
# Bank C, 48-71
- pinmerge(pinouts, gpio(bankspec, "", ("C", 0), "C", 0, 24, 0))
- pinmerge(pinouts, ulpi(bankspec, "1", ('C', 0), "C", 1))
- pinmerge(pinouts, ulpi(bankspec, "2", ('C', 12), "C", 1))
- pinmerge(pinouts, spi(bankspec, "2", ('C', 8), "C", 2))
- #pinmerge(pinouts, spi(bankspec, "2", ('C', 28), "C", 2))
- pinmerge(pinouts, uartfull(bankspec, "0", ('C', 20), "C", 3))
- pinmerge(pinouts, eint(bankspec, "", ('C', 0), "C", 10, 8, mux=3))
- pinmerge(pinouts, jtag(bankspec, "2", ('C', 8), "C", 3))
- pinmerge(pinouts, eint(bankspec, "", ('C', 12), "C", 22, 8, mux=3))
- pinmerge(pinouts, uart(bankspec, "2", ('C', 22), "C", 2))
- pinmerge(pinouts, i2s(bankspec, "", ('C', 13), "C", 2))
- pinmerge(pinouts, pwm(bankspec, "", ('C', 21), "C", 2, 1, mux=2))
+ pinouts.gpio("", ("C", 0), "C", 0, 24, 0)
+ pinouts.ulpi("1", ('C', 0), "C", 1)
+ pinouts.ulpi("2", ('C', 12), "C", 1)
+ pinouts.spi("2", ('C', 8), "C", 2)
+ #pinouts.spi("2", ('C', 28), "C", 2)
+ pinouts.uartfull("0", ('C', 20), "C", 3)
+ pinouts.eint("", ('C', 0), "C", 10, 8, mux=3)
+ pinouts.jtag("2", ('C', 8), "C", 3)
+ pinouts.eint("", ('C', 12), "C", 22, 8, mux=3)
+ pinouts.uart("2", ('C', 22), "C", 2)
+ pinouts.i2s("", ('C', 13), "C", 2)
+ pinouts.pwm("", ('C', 21), "C", 2, 1, mux=2)
# Bank D, 72-96
flexspec = {
'FB_TSIZ0': ('FB_BWE0', 2, "D"),
'FB_TSIZ1': ('FB_BWE1', 2, "D"),
}
- #pinmerge(pinouts, mcu8080("", 72, "D", 1))
- pinmerge(pinouts, gpio(bankspec, "", ('D', 0), "D", 0, 24, 0))
- pinmerge(pinouts, flexbus1(bankspec, "", ('D', 0), "D", 1, spec=flexspec))
- pinmerge(pinouts, i2c(bankspec, "2", ('D', 8), "D", 3))
- pinmerge(pinouts, pwm(bankspec, "", ('D', 21), "D", 0, 3, mux=1))
- pinmerge(pinouts, i2c(bankspec, "1", ('D', 10), "D", 3))
- pinmerge(pinouts, i2c(bankspec, "3", ('D', 19), "D", 2))
- pinmerge(pinouts, uartfull(bankspec, "0", ('D', 0), "D", 2))
- pinmerge(pinouts, uart(bankspec, "3", ('D', 21), "D", 2))
- pinmerge(pinouts, uart(bankspec, "4", ('D', 13), "D", 2))
- pinmerge(pinouts, eint(bankspec, "", ('D', 19), "D", 18, 4, mux=3))
- pinmerge(pinouts, eint(bankspec, "", ('D', 23), "D", 9, 1, mux=3))
- pinmerge(pinouts, eint(bankspec, "", ('D', 13), "D", 5, 4, mux=3))
- pinmerge(pinouts, eint(bankspec, "", ('D', 0), "D", 30, 2, mux=3))
- pinmerge(pinouts, i2c(bankspec, "2", ('D', 2), "D", 3))
- pinmerge(pinouts, sdmmc(bankspec, "2", ('D', 4), "D", 2))
+ #pinouts.mcu8080("", 72, "D", 1)
+ pinouts.gpio("", ('D', 0), "D", 0, 24, 0)
+ pinouts.flexbus1("", ('D', 0), "D", 1, spec=flexspec)
+ pinouts.i2c("2", ('D', 8), "D", 3)
+ pinouts.pwm("", ('D', 21), "D", 0, 3, mux=1)
+ pinouts.i2c("1", ('D', 10), "D", 3)
+ pinouts.i2c("3", ('D', 19), "D", 2)
+ pinouts.uartfull("0", ('D', 0), "D", 2)
+ pinouts.uart("3", ('D', 21), "D", 2)
+ pinouts.uart("4", ('D', 13), "D", 2)
+ pinouts.eint("", ('D', 19), "D", 18, 4, mux=3)
+ pinouts.eint("", ('D', 23), "D", 9, 1, mux=3)
+ pinouts.eint("", ('D', 13), "D", 5, 4, mux=3)
+ pinouts.eint("", ('D', 0), "D", 30, 2, mux=3)
+ pinouts.i2c("2", ('D', 2), "D", 3)
+ pinouts.sdmmc("2", ('D', 4), "D", 2)
# Bank E
- pinmerge(pinouts, gpio(bankspec, "", ('E', 0), "E", 0, 24, 0))
- pinmerge(pinouts, flexbus2(bankspec, "", ('E', 0), "E", 1))
- pinmerge(pinouts, sdmmc(bankspec, "2", ('E', 0), "E", 2))
- pinmerge(pinouts, sdmmc(bankspec, "3", ('E', 8), "E", 2))
- pinmerge(pinouts, quadspi(bankspec, "", ('E', 18), "E", 2))
- pinmerge(pinouts, uartfull(bankspec, "1", ('E', 14), "E", 2))
- pinmerge(pinouts, i2c(bankspec, "2", ('E', 6), "E", 2))
- pinmerge(pinouts, eint(bankspec, "", ('E', 0), "E", 10, 8, mux=3))
- pinmerge(pinouts, eint(bankspec, "", ('E', 8), "E", 22, 6, mux=3))
- pinmerge(pinouts, emmc(bankspec, "", ('E', 14), "E", 3))
+ pinouts.gpio("", ('E', 0), "E", 0, 24, 0)
+ pinouts.flexbus2("", ('E', 0), "E", 1)
+ pinouts.sdmmc("2", ('E', 0), "E", 2)
+ pinouts.sdmmc("3", ('E', 8), "E", 2)
+ pinouts.quadspi("", ('E', 18), "E", 2)
+ pinouts.uartfull("1", ('E', 14), "E", 2)
+ pinouts.i2c("2", ('E', 6), "E", 2)
+ pinouts.eint("", ('E', 0), "E", 10, 8, mux=3)
+ pinouts.eint("", ('E', 8), "E", 22, 6, mux=3)
+ pinouts.emmc("", ('E', 14), "E", 3)
# Bank F
- pinmerge(pinouts, gpio(bankspec, "", ('F', 0), "F", 0, 10, 0))
- pinmerge(pinouts, i2s(bankspec, "", ('F', 0), "F", 1))
- pinmerge(pinouts, i2c(bankspec, "1", ('F', 6), "F", 2))
- pinmerge(pinouts, pwm(bankspec, "", ('F', 8), "F", 0, 1, mux=2))
- pinmerge(pinouts, pwm(bankspec, "", ('F', 9), "F", 1, 1, mux=2))
- pinmerge(pinouts, uart(bankspec, "4", ('F', 8), "F", 1))
- pinmerge(pinouts, sdmmc(bankspec, "3", ('F', 0), "F", 2))
- pinmerge(pinouts, eint(bankspec, "", ('F', 0), "F", 18, 4, mux=3))
- pinmerge(pinouts, pwm(bankspec, "", ('F', 4), "F", 2, 1, mux=3))
- pinmerge(pinouts, eint(bankspec, "", ('F', 5), "F", 7, 1, mux=3))
- pinmerge(pinouts, eint(bankspec, "", ('F', 6), "F", 28, 4, mux=3))
+ pinouts.gpio("", ('F', 0), "F", 0, 10, 0)
+ pinouts.i2s("", ('F', 0), "F", 1)
+ pinouts.i2c("1", ('F', 6), "F", 2)
+ pinouts.pwm("", ('F', 8), "F", 0, 1, mux=2)
+ pinouts.pwm("", ('F', 9), "F", 1, 1, mux=2)
+ pinouts.uart("4", ('F', 8), "F", 1)
+ pinouts.sdmmc("3", ('F', 0), "F", 2)
+ pinouts.eint("", ('F', 0), "F", 18, 4, mux=3)
+ pinouts.pwm("", ('F', 4), "F", 2, 1, mux=3)
+ pinouts.eint("", ('F', 5), "F", 7, 1, mux=3)
+ pinouts.eint("", ('F', 6), "F", 28, 4, mux=3)
# Bank G
- pinmerge(pinouts, gpio(bankspec, "", ('G', 0), "G", 0, 32, 0))
- pinmerge(pinouts, rgmii(bankspec, "", ('G', 0), "G", 1))
- pinmerge(pinouts, ulpi(bankspec, "3", ('G', 20), "G", 1))
- pinmerge(pinouts, rgbttl(bankspec, "1", ('G', 0), "G", 2))
- pinmerge(pinouts, quadspi(bankspec, "", ('G', 26), "G", 3))
- pinmerge(pinouts, flexbus2(bankspec, "", ('G', 0), "G", 3))
- mmc2 = sdmmc(bankspec, "2", ('G', 24), "G", 3, limit=2)
- pinmerge(pinouts, mmc2)
- mmc2 = sdmmc(bankspec, "2", ('G', 28), "G", 2, start=2)
- pinmerge(pinouts, mmc2)
+ pinouts.gpio("", ('G', 0), "G", 0, 32, 0)
+ pinouts.rgmii("", ('G', 0), "G", 1)
+ pinouts.ulpi("3", ('G', 20), "G", 1)
+ pinouts.rgbttl("1", ('G', 0), "G", 2)
+ pinouts.quadspi("", ('G', 26), "G", 3)
+ pinouts.flexbus2("", ('G', 0), "G", 3)
+ pinouts.sdmmc("2", ('G', 24), "G", 3, limit=2)
+ pinouts.sdmmc("2", ('G', 28), "G", 2, start=2)
print ("""# Pinouts (PinMux)
auto-generated by [[pinouts.py]]
projects / pinmux.git / commitdiff