set various clocks to use H-Tree

diff --git a/experiments10_verilog/doDesign.py b/experiments10_verilog/doDesign.py
index 33a2ed943b719f95fbd84e1b8295c0bdbabcc9fc..f79a3cc14a4f65c50bb5d99515993e19151f1ec1 100644 (file)
--- a/experiments10_verilog/doDesign.py
+++ b/experiments10_verilog/doDesign.py
@@ -81,6 +81,8 @@ def scriptMain ( **kw ):
         adderConf.chipConf.name = 'chip'
         #adderConf.chipConf.ioPadGauge = 'LibreSOCIO'
         adderConf.chipConf.ioPadGauge = 'niolib'
+        adderConf.useHTree('jtag_tck_from_pad')
+        adderConf.useHTree('sys_clk_from_pad')
         adderConf.coreSize = ( l(coreSize), l(coreSize) )
         adderConf.chipSize = ( l(coreSize+3500), l(coreSize+3500) )
         adderToChip = CoreToChip( adderConf )

diff --git a/experiments9/doDesign.py b/experiments9/doDesign.py
index 86b1d12cd7e1f4cac77512fb1f8955725bedcf22..fd61b7ab7ca8432c8c26bda6723f38423d258fdd 100644 (file)
--- a/experiments9/doDesign.py
+++ b/experiments9/doDesign.py
@@ -58,6 +58,8 @@ def scriptMain (**kw):
         ls180Conf.chipConf.ioPadGauge = 'niolib'
         ls180Conf.coreSize = (l(coreSize     ), l(coreSize     ))
         ls180Conf.chipSize = (l(coreSize+3360), l(coreSize+3360))
+        ls180Conf.useHTree('core.por_clk')
+        ls180Conf.useHTree('jtag_tck_from_pad')
 
         ls180ToChip = CoreToChip( ls180Conf )
         ls180ToChip.buildChip()