sigh. convert Fast regfile to binary

diff --git a/src/soc/decoder/power_regspec_map.py b/src/soc/decoder/power_regspec_map.py
index 74a955cb7e917306f1b51a29e8b142c8f215e48a..81298e8e63ad6c97b9a5806339e018796d4333e5 100644 (file)
--- a/src/soc/decoder/power_regspec_map.py
+++ b/src/soc/decoder/power_regspec_map.py
@@ -97,15 +97,10 @@ def regspec_decode_read(e, regfile, name):
 
     if regfile == 'FAST':
         # FAST register numbering is *unary* encoded
-        CTR = 1<<FastRegs.CTR
-        LR = 1<<FastRegs.LR
-        TAR = 1<<FastRegs.TAR
-        SRR0 = 1<<FastRegs.SRR0
-        SRR1 = 1<<FastRegs.SRR1
         if name == 'fast1':
-            return e.read_fast1.ok, 1<<e.read_fast1.data
+            return e.read_fast1.ok, e.read_fast1.data
         if name == 'fast2':
-            return e.read_fast2.ok, 1<<e.read_fast2.data
+            return e.read_fast2.ok, e.read_fast2.data
 
     # SPR regfile
 
@@ -170,9 +165,9 @@ def regspec_decode_write(e, regfile, name):
     if regfile == 'FAST':
         # FAST register numbering is *unary* encoded
         if name == 'fast1':
-            return e.write_fast1, 1<<e.write_fast1.data
+            return e.write_fast1, e.write_fast1.data
         if name == 'fast2':
-            return e.write_fast2, 1<<e.write_fast2.data
+            return e.write_fast2, e.write_fast2.data
 
     # SPR regfile
 

diff --git a/src/soc/regfile/regfiles.py b/src/soc/regfile/regfiles.py
index d088fe600a466ffd9b39aa01e0152f7a2208844c..88b232096c5e96aba3bd190e4ba8f27814b6a691 100644 (file)
--- a/src/soc/regfile/regfiles.py
+++ b/src/soc/regfile/regfiles.py
@@ -75,7 +75,7 @@ class IntRegs(RegFileMem): #class IntRegs(RegFileArray):
 
 
 # Fast SPRs Regfile
-class FastRegs(RegFileArray):
+class FastRegs(RegFileMem): #RegFileArray):
     """FastRegs
 
     FAST regfile  - CTR, LR, TAR, SRR1, SRR2