Implement signed branch immediates

diff --git a/src/soc/branch/main_stage.py b/src/soc/branch/main_stage.py
index b7348ef6adbd5e824c883eb5d72a2e0cdca578ed..607cd6bd55f0f8315fbcc16b86c371a8f2be7ca2 100644 (file)
--- a/src/soc/branch/main_stage.py
+++ b/src/soc/branch/main_stage.py
@@ -59,7 +59,10 @@ class BranchMainStage(PipeModBase):
             with m.Case(InternalOp.OP_B):
                 li = Signal(i_fields['LI'][0:-1].shape())
                 comb += li.eq(i_fields['LI'][0:-1])
-                comb += branch_imm_addr.eq(Cat(Const(0, 2), li))
+                li_sgn = li[-1]
+                comb += branch_imm_addr.eq(
+                    Cat(Const(0, 2), li,
+                        Repl(li_sgn, 64-(li.width + 2))))
                 comb += branch_taken.eq(1)
 
         comb += self.o.nia_out.data.eq(branch_addr)

diff --git a/src/soc/branch/test/test_pipe_caller.py b/src/soc/branch/test/test_pipe_caller.py
index cc9f3e08ec60586fcc63c0568fda22441f8cd338..0a15808113ec33156e7b995c5ecb568e6e933e51 100644 (file)
--- a/src/soc/branch/test/test_pipe_caller.py
+++ b/src/soc/branch/test/test_pipe_caller.py
@@ -63,15 +63,14 @@ class BranchTestCase(FHDLTestCase):
         tc = TestCase(prog, initial_regs, initial_sprs, self.test_name)
         test_data.append(tc)
 
-    def test_ba(self):
-        lst = ["ba 0x1234"]
-        initial_regs = [0] * 32
-        self.run_tst_program(Program(lst), initial_regs)
-
-    def test_b(self):
-        lst = ["bl 0x1234"]
-        initial_regs = [0] * 32
-        self.run_tst_program(Program(lst), initial_regs)
+    def test_unconditional(self):
+        choices = ["b", "ba", "bl", "bla"]
+        for i in range(20):
+            choice = random.choice(choices)
+            imm = random.randrange(-1<<23, (1<<23)-1) * 4
+            lst = [f"{choice} {imm}"]
+            initial_regs = [0] * 32
+            self.run_tst_program(Program(lst), initial_regs)
 
     def test_ilang(self):
         rec = CompALUOpSubset()