whoops wrong variable names

diff --git a/src/soc/experiment/pimem.py b/src/soc/experiment/pimem.py
index cb17807d89031d1592c96a42c17da8523b4e8856..51a6abef2b5bb82ced399d9efadbf09686c745dc 100644 (file)
--- a/src/soc/experiment/pimem.py
+++ b/src/soc/experiment/pimem.py
@@ -226,8 +226,8 @@ class PortInterfaceBase(Elaboratable):
         # TODO: construct an MSRspec here and pass it over in
         # self.set_rd_addr and set_wr_addr below rather than just pr
         pr = ~pi.priv_mode
-        dr = ~pi.virt_mode   # not yet used
-        sf = self.mode_32bit   # not yet used
+        dr = pi.virt_mode   # not yet used
+        sf = pi.mode_32bit   # not yet used
 
         # detect busy "edge"
         busy_delay = Signal()