add SVP64 RM fields to ALU input record

diff --git a/src/soc/fu/alu/alu_input_record.py b/src/soc/fu/alu/alu_input_record.py
index 4126fc6c5500c2e81cd3723ada8dee34d90e05be..39585f31aa344b1ff77b3efabe16f476c0d78b37 100644 (file)
--- a/src/soc/fu/alu/alu_input_record.py
+++ b/src/soc/fu/alu/alu_input_record.py
@@ -2,6 +2,8 @@ from soc.fu.base_input_record import CompOpSubsetBase
 from openpower.decoder.power_enums import MicrOp, Function, CryIn
 from nmigen.hdl.rec import Layout
 
+# needed for SVP64 information at the pipeline
+from openpower.decoder.power_svp64_rm import sv_input_record_layout
 
 class CompALUOpSubset(CompOpSubsetBase):
     """CompALUOpSubset
@@ -11,7 +13,7 @@ class CompALUOpSubset(CompOpSubsetBase):
     grab subsets.
     """
     def __init__(self, name=None):
-        layout = (('insn_type', MicrOp),
+        layout = [('insn_type', MicrOp),
                   ('fn_unit', Function),
                   ('imm_data', Layout((("data", 64), ("ok", 1)))),
                   ('rc', Layout((("rc", 1), ("ok", 1)))), # Data
@@ -26,6 +28,6 @@ class CompALUOpSubset(CompOpSubsetBase):
                   ('is_signed', 1),
                   ('data_len', 4), # actually used by ALU, in OP_EXTS
                   ('insn', 32),
-                  )
+                  ] + sv_input_record_layout
         super().__init__(layout, name=name)