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authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Fri, 17 Jul 2020 17:46:06 +0000 (18:46 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Fri, 17 Jul 2020 17:46:06 +0000 (18:46 +0100)
src/soc/fu/spr/formal/proof_main_stage.py

index cb98bf65db3ed98acf3649078be10a85b6118641..11ff8d8e6602481083ccdb61832d3232f3670c02 100644 (file)
@@ -82,6 +82,8 @@ class Driver(Elaboratable):
         comb += spr.eq(decode_spr_num(xfx.SPR))
 
         with m.Switch(dut.i.ctx.op.insn_type):
+
+            # OP_MTSPR
             with m.Case(MicrOp.OP_MTSPR):
                 with m.Switch(spr):
                     with m.Case(SPR.CTR, SPR.LR, SPR.TAR, SPR.SRR0, SPR.SRR1):
@@ -112,6 +114,8 @@ class Driver(Elaboratable):
                             Assert(~dut.o.fast1.ok),
                         ]
                     # slow SPRs TODO
+
+            # OP_MFSPR
             with m.Case(MicrOp.OP_MFSPR):
                 comb += Assert(o.ok)
                 with m.Switch(spr):