disable cxxsim test

diff --git a/src/soc/fu/shift_rot/test/test_pipe_caller.py b/src/soc/fu/shift_rot/test/test_pipe_caller.py
index bbd496ba3204e2afcef2283bff963706b5db3bd9..fdb2089a989ac4f6ffb353454a420c63fd4c293b 100644 (file)
--- a/src/soc/fu/shift_rot/test/test_pipe_caller.py
+++ b/src/soc/fu/shift_rot/test/test_pipe_caller.py
@@ -1,6 +1,6 @@
 from nmigen import Module, Signal
 from nmigen.back.pysim import Delay, Settle
-cxxsim = True
+cxxsim = False
 if cxxsim:
     from nmigen.sim.cxxsim import Simulator
 else: