whoops should be cyc & ~ack

diff --git a/src/soc/experiment/dcache.py b/src/soc/experiment/dcache.py
index 09c907b5394b7ca3ae0d19cd7aca54f8a561f878..4500d55fa565ec154b60c8181ffc2175b0ab1b9f 100644 (file)
--- a/src/soc/experiment/dcache.py
+++ b/src/soc/experiment/dcache.py
@@ -1625,7 +1625,7 @@ class DCache(Elaboratable):
         comb += self.wb_out.adr.eq(r1.wb.adr[3:]) # truncate LSBs
 
         # deal with litex not doing wishbone pipeline mode
-        comb += self.wb_in.stall.eq(self.wb_out.cyc & self.wb_in.ack)
+        comb += self.wb_in.stall.eq(self.wb_out.cyc & ~self.wb_in.ack)
 
         # call sub-functions putting everything together, using shared
         # signals established above