rename CROutputData.cr_o to just CROutputData.cr

diff --git a/src/soc/fu/cr/formal/proof_main_stage.py b/src/soc/fu/cr/formal/proof_main_stage.py
index 16295e9002d7fe7cc2386d58bda191e4fc578a7c..ddf0089e4b54ec35fc39987a2c4b2d4370b73111 100644 (file)
--- a/src/soc/fu/cr/formal/proof_main_stage.py
+++ b/src/soc/fu/cr/formal/proof_main_stage.py
@@ -103,7 +103,7 @@ class Driver(Elaboratable):
                     with m.If(i != bt):
                         comb += cr_output_arr[i].eq(cr_input_arr[i])
                     with m.Else():
-                        comb += cr_output_arr[i].eq(dut.o.cr_o.data)
+                        comb += cr_output_arr[i].eq(dut.o.cr.data)
 
             with m.Case(InternalOp.OP_MCRF):
                 # This does a similar thing to OP_CROP above, with
@@ -123,7 +123,7 @@ class Driver(Elaboratable):
                     with m.If(i != bf):
                         comb += cr_output_arr[i].eq(cr_input_arr[i])
                     with m.Else():
-                        comb += cr_output_arr[i].eq(dut.o.cr_o.data)
+                        comb += cr_output_arr[i].eq(dut.o.cr.data)
 
             # For the other two, they take the full CR as input, and
             # output a full CR. This handles that
@@ -231,7 +231,7 @@ class Driver(Elaboratable):
 
         # check that data ok was only enabled when op actioned
         comb += Assert(dut.o.o.ok == o_ok)
-        comb += Assert(dut.o.cr_o.ok == cr_o_ok)
+        comb += Assert(dut.o.cr.ok == cr_o_ok)
         comb += Assert(dut.o.full_cr.ok == full_cr_o_ok)
 
         return m

diff --git a/src/soc/fu/cr/main_stage.py b/src/soc/fu/cr/main_stage.py
index 7c43fffd97157e4d8f9ffbfefb38c015cad24bdc..f3a5ee49433c623ec85ed70c8144fa02908a71ff 100644 (file)
--- a/src/soc/fu/cr/main_stage.py
+++ b/src/soc/fu/cr/main_stage.py
@@ -36,7 +36,7 @@ class CRMainStage(PipeModBase):
         op = self.i.ctx.op
         a, b, full_cr = self.i.a, self.i.b, self.i.full_cr
         cr_a, cr_b, cr_c = self.i.cr_a, self.i.cr_b, self.i.cr_c
-        cr_o, full_cr_o, rt_o = self.o.cr_o, self.o.full_cr, self.o.o
+        cr_o, full_cr_o, rt_o = self.o.cr, self.o.full_cr, self.o.o
 
         xl_fields = self.fields.FormXL
         xfx_fields = self.fields.FormXFX

diff --git a/src/soc/fu/cr/pipe_data.py b/src/soc/fu/cr/pipe_data.py
index 4b736a0b85c3176c6616c9d1023fe5db67c2ec04..9879955ceff9e599ecdd1888b85edfbc58d1e6b0 100644 (file)
--- a/src/soc/fu/cr/pipe_data.py
+++ b/src/soc/fu/cr/pipe_data.py
@@ -47,24 +47,24 @@ class CRInputData(IntegerData):
 class CROutputData(IntegerData):
     regspec = [('INT', 'o', '0:63'),      # 64 bit range
                ('CR', 'full_cr', '0:31'), # 32 bit range
-               ('CR', 'cr_o', '0:3')]     # 4 bit range
+               ('CR', 'cr', '0:3')]     # 4 bit range
     def __init__(self, pspec):
         super().__init__(pspec)
         self.o = Data(64, name="o") # RA
         self.full_cr = Data(32, name="cr_out") # CR in
-        self.cr_o = Data(4, name="cr_o")
+        self.cr = Data(4, name="cr_o")
 
     def __iter__(self):
         yield from super().__iter__()
         yield self.o
         yield self.full_cr
-        yield self.cr_o
+        yield self.cr
 
     def eq(self, i):
         lst = super().eq(i)
         return lst + [self.o.eq(i.o),
                       self.full_cr.eq(i.full_cr),
-                      self.cr_o.eq(i.cr_o)]
+                      self.cr.eq(i.cr)]
 
 
 class CRPipeSpec(CommonPipeSpec):

diff --git a/src/soc/fu/cr/test/test_pipe_caller.py b/src/soc/fu/cr/test/test_pipe_caller.py
index 7fc0493b991d609e96d49efc2a361ffaf14312f1..5a5c20350a955d126b171e07db23452af8a92614 100644 (file)
--- a/src/soc/fu/cr/test/test_pipe_caller.py
+++ b/src/soc/fu/cr/test/test_pipe_caller.py
@@ -177,7 +177,7 @@ class TestRunner(FHDLTestCase):
         elif cr_en:
             cr_sel = yield dec2.e.write_cr.data
             expected_cr = simulator.crl[cr_sel].get_range().value
-            real_cr = yield alu.n.data_o.cr_o.data
+            real_cr = yield alu.n.data_o.cr.data
             self.assertEqual(expected_cr, real_cr, code)
         alu_out = yield alu.n.data_o.o.data
         out_reg_valid = yield dec2.e.write_reg.ok