self.in_b = FPOp(width)
self.out_z = FPOp(width)
- def get_fragment(self, platform=None):
+ def elaborate(self, platform=None):
""" creates the HDL code-fragment for FPAdd
"""
m = Module()
self.states.append(state)
return state
- def get_fragment(self, platform=None):
+ def elaborate(self, platform=None):
""" creates the HDL code-fragment for FPMUL
"""
m = Module()
fus.append(rs)
self.fus = Array(fus)
- def get_fragment(self, platform=None):
+ def elaborate(self, platform=None):
""" creates the HDL code-fragment for ReservationStationRow
"""
m = Module()
self.states.append(state)
return state
- def get_fragment(self, platform=None):
+ def elaborate(self, platform=None):
""" creates the HDL code-fragment for FPDiv
"""
m = Module()
self.m = Module()
self.p = ObjectBasedPipelineExample(self.m)
- def get_fragment(self, platform=None):
+ def elaborate(self, platform=None):
return self.m
def __init__(self):
self._loopback = Signal(4, name="loopback")
- def get_fragment(self, platform=None):
+ def elaborate(self, platform=None):
m = Module()
def __init__(self):
self.loopback = Signal(4)
- def get_fragment(self, platform=None):
+ def elaborate(self, platform=None):
m = Module()
def __init__(self):
self._loopback = Signal(4)
- def get_fragment(self, platform=None):
+ def elaborate(self, platform=None):
m = Module()
# TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR
# MODIFICATIONS.
-from nmigen import Module, Signal, Memory, Mux
+from nmigen import Module, Signal, Memory, Mux, Elaboratable
from nmigen.tools import bits_for
from nmigen.cli import main
from nmigen.lib.fifo import FIFOInterface
# translated from https://github.com/freechipsproject/chisel3/blob/a4a29e29c3f1eed18f851dcf10bdc845571dfcb6/src/main/scala/chisel3/util/Decoupled.scala#L185 # noqa
-class Queue(FIFOInterface):
+class Queue(FIFOInterface, Elaboratable):
def __init__(self, width, depth, fwft=True, pipe=False):
""" Queue (FIFO) with pipe mode and first-write fall-through capability
-from nmigen import Module, Signal, Mux, Const
+from nmigen import Module, Signal, Mux, Const, Elaboratable
from nmigen.hdl.rec import Record, Layout, DIR_NONE
from nmigen.compat.sim import run_simulation
from nmigen.cli import verilog, rtlil
-class RecordTest2:
+class RecordTest2(Elaboratable):
def __init__(self):
self.r1 = RecordObject()
self.id_wid = id_wid
self.out_z = Signal(width)
- def get_fragment(self, platform=None):
+ def elaborate(self, platform=None):
""" creates the HDL code-fragment for ReservationStationRow
"""
m = Module()
https://github.com/ZipCPU/dbgbus/blob/master/hexbus/rtl/hbdeword.v
"""
-from nmigen import Signal, Cat, Const, Mux, Module, Value
+from nmigen import Signal, Cat, Const, Mux, Module, Value, Elaboratable
from nmigen.cli import verilog, rtlil
from nmigen.lib.fifo import SyncFIFO, SyncFIFOBuffered
from nmigen.hdl.ast import ArrayProxy
return list(self)
-class PrevControl:
+class PrevControl(Elaboratable):
""" contains signals that come *from* the previous stage (both in and out)
* i_valid: previous stage indicating all incoming data is valid.
may be a multi-bit signal, where all bits are required
return list(self)
-class NextControl:
+class NextControl(Elaboratable):
""" contains the signals that go *to* the next stage (both in and out)
* o_valid: output indicating to next stage that data is valid
* i_ready: input from next stage indicating that it can accept data
return self.o # conform to Stage API: return last-loop output
-class ControlBase:
+class ControlBase(Elaboratable):
""" Common functions for Pipeline API
"""
def __init__(self, stage=None, in_multi=None, stage_ctl=False):
def ports(self):
return list(self)
- def _elaborate(self, platform):
+ def elaborate(self, platform):
""" handles case where stage has dynamic ready/valid functions
"""
m = Module()
"""
def elaborate(self, platform):
- self.m = ControlBase._elaborate(self, platform)
+ self.m = ControlBase.elaborate(self, platform)
result = self.stage.ospec()
r_data = self.stage.ospec()
"""
def elaborate(self, platform):
- self.m = m = ControlBase._elaborate(self, platform)
+ self.m = m = ControlBase.elaborate(self, platform)
r_busy = Signal()
result = self.stage.ospec()
"""
def elaborate(self, platform):
- self.m = m = ControlBase._elaborate(self, platform)
+ self.m = m = ControlBase.elaborate(self, platform)
data_valid = Signal() # is data valid or not
r_data = self.stage.ospec() # output type
"""
def elaborate(self, platform):
- self.m = m = ControlBase._elaborate(self, platform)
+ self.m = m = ControlBase.elaborate(self, platform)
buf_full = Signal() # is data valid or not
buf = self.stage.ospec() # output type
"""
def elaborate(self, platform):
- self.m = m = ControlBase._elaborate(self, platform)
+ self.m = m = ControlBase.elaborate(self, platform)
r_data = self.stage.ospec() # output type
ControlBase.__init__(self, stage, in_multi, stage_ctl)
def elaborate(self, platform):
- self.m = m = ControlBase._elaborate(self, platform)
+ self.m = m = ControlBase.elaborate(self, platform)
# make a FIFO with a signal of equal width to the o_data.
(fwidth, _) = shape(self.n.o_data)
"""
-from nmigen import Module, Signal, Mux, Const
+from nmigen import Module, Signal, Mux, Const, Elaboratable
from nmigen.hdl.rec import Record
from nmigen.compat.sim import run_simulation
from nmigen.cli import verilog, rtlil
"""
def elaborate(self, platform):
- m = Module()
+ m = ControlBase.elaborate(self, platform)
pipe1 = ExampleBufPipe()
pipe2 = ExampleBufPipe()
# Test 6 and 10
######################################################################
-class SetLessThan:
+class SetLessThan(Elaboratable):
def __init__(self, width, signed):
self.m = Module()
self.src1 = Signal((width, signed), name="src1")
return self.o
-class LTStageDerived(SetLessThan, StageCls):
+class LTStageDerived(SetLessThan, StageCls, Elaboratable):
""" special version of a nmigen module where the module is also a stage
shows that you don't actually need to combinatorially connect
# Test 12
######################################################################
-class ExampleStageDelayCls(StageCls):
+class ExampleStageDelayCls(StageCls, Elaboratable):
""" an example of how to use the buffered pipeline, in a static class
fashion
"""
class ExampleBufModeUnBufPipe(ControlBase):
def elaborate(self, platform):
- m = ControlBase._elaborate(self, platform)
+ m = ControlBase.elaborate(self, platform)
pipe1 = ExampleBufModeAdd1Pipe()
pipe2 = ExampleBufAdd1Pipe()
class ExampleBufPassThruPipe(ControlBase):
def elaborate(self, platform):
- m = ControlBase._elaborate(self, platform)
+ m = ControlBase.elaborate(self, platform)
# XXX currently fails: any other permutation works fine.
# p1=u,p2=b ok p1=u,p2=u ok p1=b,p2=b ok
class ExampleFIFOPassThruPipe1(ControlBase):
def elaborate(self, platform):
- m = ControlBase._elaborate(self, platform)
+ m = ControlBase.elaborate(self, platform)
pipe1 = FIFOTest16()
pipe2 = ExamplePassAdd1Pipe()
class ExampleFIFORecordObjectPipe(ControlBase):
def elaborate(self, platform):
- m = ControlBase._elaborate(self, platform)
+ m = ControlBase.elaborate(self, platform)
pipe1 = FIFOTestRecordControl()
pipe2 = ExampleRecordHandshakeAddClass()
class ExampleFIFOAdd2Pipe(ControlBase):
def elaborate(self, platform):
- m = ControlBase._elaborate(self, platform)
+ m = ControlBase.elaborate(self, platform)
pipe1 = FIFOTestAdd16()
pipe2 = FIFOTestAdd16()
class ExampleBufPassThruPipe2(ControlBase):
def elaborate(self, platform):
- m = ControlBase._elaborate(self, platform)
+ m = ControlBase.elaborate(self, platform)
# XXX currently fails: any other permutation works fine.
# p1=u,p2=b ok p1=u,p2=u ok p1=b,p2=b ok
"""
def elaborate(self, platform):
- m = ControlBase._elaborate(self, platform)
+ m = ControlBase.elaborate(self, platform)
pipe1 = ExampleBufDelayedPipe()
pipe2 = ExampleBufPipe()
class ExampleBufUnBufPipe(ControlBase):
def elaborate(self, platform):
- m = ControlBase._elaborate(self, platform)
+ m = ControlBase.elaborate(self, platform)
# XXX currently fails: any other permutation works fine.
# p1=u,p2=b ok p1=u,p2=u ok p1=b,p2=b ok
self.b = Signal()
self.x = Signal()
- def get_fragment(self, platform=None):
+ def elaborate(self, platform=None):
m = Module()
m.d.comb += self.x.eq(self.a | self.b)
self.a = FPNum(width)
self.ediff = Signal((self.a.e_width, True))
- def get_fragment(self, platform=None):
+ def elaborate(self, platform=None):
m = Module()
#m.d.sync += self.a.decode(self.a.v)
self.b = Signal(self.ms.smax)
self.x = Signal(width)
- def get_fragment(self, platform=None):
+ def elaborate(self, platform=None):
m = Module()
m.d.comb += self.x.eq(self.ms.lshift(self.a, self.b))
self.b = Signal(self.ms.smax)
self.x = Signal(width)
- def get_fragment(self, platform=None):
+ def elaborate(self, platform=None):
m = Module()
m.d.comb += self.x.eq(self.ms.rshift(self.a, self.b))
self.b = Signal(self.ms.smax)
self.x = Signal(width)
- def get_fragment(self, platform=None):
+ def elaborate(self, platform=None):
m = Module()
m.submodules += self.ms
self.b = Signal(self.ms.smax)
self.x = Signal(width)
- def get_fragment(self, platform=None):
+ def elaborate(self, platform=None):
m = Module()
m.submodules += self.ms
projects / ieee754fpu.git / commitdiff