vhdl conversion not really working for plru

diff --git a/src/soc/experiment/plru.py b/src/soc/experiment/plru.py
index d2ba72324da697e74f821da6a5377fe8034a4dd1..99e51f6d2d6ced6cfb56de1914720ff9dc86bc22 100644 (file)
--- a/src/soc/experiment/plru.py
+++ b/src/soc/experiment/plru.py
@@ -1,6 +1,6 @@
 # based on microwatt plru.vhdl
 
-from nmigen import Elaboratable, Signal, Array, Module
+from nmigen import Elaboratable, Signal, Array, Module, Mux
 from nmigen.cli import rtlil
 
 
@@ -21,36 +21,30 @@ class PLRU(Elaboratable):
         # XXX Check if we can turn that into a little ROM instead that
         # takes the tree bit vector and returns the LRU. See if it's better
         # in term of FPGA resouces usage...
-        node = Signal(self.BITS)
+        node = Const(0, self.bits)
         for i in range(self.BITS):
-            node_next = Signal(self.BITS)
-            node2 = Signal(self.BITS)
             # report "GET: i:" & integer'image(i) & " node:" & 
             # integer'image(node) & " val:" & Signal()'image(tree(node))
             comb += self.lru_o[self.BITS-1-i].eq(tree[node])
             if i != self.BITS-1:
+                node_next = Signal(self.BITS)
+                node2 = Signal(self.BITS)
                 comb += node2.eq(node << 1)
-                with m.If(tree[node2]):
-                    comb += node_next.eq(node2 + 2)
-                with m.Else():
-                    comb += node_next.eq(node2 + 1)
+                comb += node_next.eq(Mux(tree[node2], node2+2, node2+1))
                 node = node_next
 
         with m.If(self.acc_en):
-            node = Signal(self.BITS)
+            node = Const(0, self.bits)
             for i in range(self.BITS):
-                node_next = Signal(self.BITS)
-                node2 = Signal(self.BITS)
                 # report "GET: i:" & integer'image(i) & " node:" & 
                 # integer'image(node) & " val:" & Signal()'image(tree(node))
                 abit = self.acc_i[self.BITS-1-i]
                 sync += tree[node].eq(~abit)
                 if i != self.BITS-1:
+                    node_next = Signal(self.BITS)
+                    node2 = Signal(self.BITS)
                     comb += node2.eq(node << 1)
-                    with m.If(abit):
-                        comb += node_next.eq(node2 + 2)
-                    with m.Else():
-                        comb += node_next.eq(node2 + 1)
+                    comb += node_next.eq(Mux(abit, node2+2, node2+1))
                     node = node_next
 
         return m
@@ -59,7 +53,7 @@ class PLRU(Elaboratable):
         return [self.acc_en, self.lru_o, self.acc_i]
 
 if __name__ == '__main__':
-    dut = PLRU(3)
+    dut = PLRU(2)
     vl = rtlil.convert(dut, ports=dut.ports())
     with open("test_plru.il", "w") as f:
         f.write(vl)