move LDSTException to mem_types

diff --git a/src/soc/experiment/mem_types.py b/src/soc/experiment/mem_types.py
index d766fb9099218aa87bfeb0496d4d90bb96c0b999..2d7308585bd20fc759745d2b7b42444baf70b949 100644 (file)
--- a/src/soc/experiment/mem_types.py
+++ b/src/soc/experiment/mem_types.py
@@ -6,6 +6,19 @@ based on Anton Blanchard microwatt common.vhdl
 from nmutil.iocontrol import RecordObject
 from nmigen import Signal
 
+# https://bugs.libre-soc.org/show_bug.cgi?id=465
+class LDSTException(RecordObject):
+    def __init__(self, name=None):
+        RecordObject.__init__(self, name=name)
+        self.happened = Signal()
+        self.alignment = Signal()
+        self.instr_fault = Signal()
+        self.invalid = Signal()
+        self.badtree = Signal()
+        self.perm_error = Signal()
+        self.rc_error = Signal()
+        self.segment_fault = Signal()
+
 
 class DCacheToLoadStore1Type(RecordObject):
     def __init__(self, name=None):

diff --git a/src/soc/experiment/pimem.py b/src/soc/experiment/pimem.py
index dc846c127aca528038e164dd0549a79c7979522a..2f089c91fbf0ef2fd93527032e6895f6ee96d835 100644 (file)
--- a/src/soc/experiment/pimem.py
+++ b/src/soc/experiment/pimem.py
@@ -25,26 +25,14 @@ from nmutil.latch import SRLatch, latchregister
 from nmutil.util import rising_edge
 from soc.decoder.power_decoder2 import Data
 from soc.scoreboard.addr_match import LenExpand
+from soc.experiment.mem_types import LDSTException
 
 # for testing purposes
 from soc.experiment.testmem import TestMemory
 #from soc.scoreboard.addr_split import LDSTSplitter
 
-
 import unittest
 
-class LDSTException(RecordObject):
-    def __init__(self, name=None):
-        RecordObject.__init__(self, name=name)
-        self.happened = Signal()
-        self.alignment = Signal()
-        self.instr_fault = Signal()
-        self.invalid = Signal()
-        self.badtree = Signal()
-        self.perm_error = Signal()
-        self.rc_error = Signal()
-        self.segment_fault = Signal()
-
 
 class PortInterface(RecordObject):
     """PortInterface