track down error in CORDIC pipe_data, "yield from" used instead of just "yield"

diff --git a/src/ieee754/cordic/pipe_data.py b/src/ieee754/cordic/pipe_data.py
index c3f600ae1026aa982bdb04d5e9fe7462966f2a10..d83dbe7b9d41a6cccbb0359bcbb126f4dfa7eebb 100644 (file)
--- a/src/ieee754/cordic/pipe_data.py
+++ b/src/ieee754/cordic/pipe_data.py
@@ -28,8 +28,8 @@ class CordicOutputData:
         self.muxid = self.ctx.muxid
 
     def __iter__(self):
-        yield from self.x
-        yield from self.y
+        yield self.x
+        yield self.y
         yield from self.ctx
 
     def eq(self, i):

diff --git a/src/ieee754/cordic/test/test_fp_pipe.py b/src/ieee754/cordic/test/test_fp_pipe.py
index 22d2f20a025bd62d1ffd116c1b0118b8aad3f476..db8c7a178c026f1bc77681bbaf133da41fee9344 100644 (file)
--- a/src/ieee754/cordic/test/test_fp_pipe.py
+++ b/src/ieee754/cordic/test/test_fp_pipe.py
@@ -20,9 +20,9 @@ class SinCosTestCase(FHDLTestCase):
         # write out module (useful for seeing what's going on)
         # XXX WHOOPS can't do this at the moment, need to track down
         # an issue in the ports
-        # vl = rtlil.convert(dut, ports=dut.ports())
-        # with open("test_cordic_pipe_sin_cos.il", "w") as f:
-        #     f.write(vl)
+        vl = rtlil.convert(dut, ports=dut.ports())
+        with open("test_cordic_pipe_sin_cos.il", "w") as f:
+            f.write(vl)
 
         z = Signal(dut.p.data_i.a.shape())
         z_valid = Signal()