return to latch on src for oper

diff --git a/src/experiment/compalu.py b/src/experiment/compalu.py
index a240a6b458f9330b13d41f48d35ed0febb3f027f..6209ae0ec1650b34b1b1fe116d358e08b145ced0 100644 (file)
--- a/src/experiment/compalu.py
+++ b/src/experiment/compalu.py
@@ -60,7 +60,7 @@ class ComputationUnitNoDelay(Elaboratable):
         #    m.d.comb += self.alu.op.eq(self.oper_i)
 
         # create a latch/register for the operand
-        latchregister(m, self.oper_i, self.alu.op, opc_l.q)
+        latchregister(m, self.oper_i, self.alu.op, src_l.q)
 
         # and one for the output from the ALU
         data_o = Signal(self.rwid, reset_less=True) # Dest register