remove div1.py

diff --git a/src/ieee754/fpdiv/div1.py b/src/ieee754/fpdiv/div1.py
deleted file mode 100644 (file)
index 6cf49ab..0000000
--- a/src/ieee754/fpdiv/div1.py
+++ /dev/null
@@ -1,70 +0,0 @@
-"""IEEE754 Floating Point Divider
-
-Relevant bugreport: http://bugs.libre-riscv.org/show_bug.cgi?id=99
-"""
-
-from nmigen import Module, Signal, Cat, Elaboratable
-from nmigen.cli import main, verilog
-
-from ieee754.fpcommon.fpbase import FPNumBaseRecord
-from ieee754.fpcommon.fpbase import FPState
-from ieee754.fpcommon.denorm import FPSCData
-from .div0 import FPDivStage0Data # TODO: replace with DivPipeCoreInterstageData
-
-
-class FPDivStage1Mod(Elaboratable):
-
-    def __init__(self, pspec):
-        self.pspec = pspec
-        self.i = self.ispec()
-        self.o = self.ospec()
-
-    def ispec(self):
-        # TODO: DivPipeCoreInterstageData, here
-        return FPDivStage0Data(self.pspec) # Q/Rem (etc) in...
-
-    def ospec(self):
-        # TODO: DivPipeCoreInterstageData, here
-        return FPDivStage0Data(self.pspec) # ... Q/Rem (etc) out
-
-    def process(self, i):
-        return self.o
-
-    def setup(self, m, i):
-        """ links module to inputs and outputs
-        """
-        m.submodules.div0 = self
-        m.d.comb += self.i.eq(i)
-
-    def elaborate(self, platform):
-        m = Module()
-
-        # XXX TODO, actual DIV code here.  this class would be
-        # here is where Q and R are used, TODO: Q/REM (etc) need to be in
-        # FPDivStage0Data.
-
-        # NOTE: this does ONE step of Q/REM processing.  it does NOT do
-        # MULTIPLE stages of Q/REM processing.  it *MUST* be PURE
-        # combinatorial and one step ONLY.
-
-        # store intermediate tests (and zero-extended mantissas)
-        am0 = Signal(len(self.i.a.m)+1, reset_less=True)
-        bm0 = Signal(len(self.i.b.m)+1, reset_less=True)
-        m.d.comb += [
-                     am0.eq(Cat(self.i.a.m, 0)),
-                     bm0.eq(Cat(self.i.b.m, 0))
-                    ]
-        # same-sign (both negative or both positive) div mantissas
-        with m.If(~self.i.out_do_z):
-            m.d.comb += [self.o.z.e.eq(self.i.a.e + self.i.b.e + 1),
-                         # TODO: no, not product, first stage Q and R etc. etc.
-                         # go here.
-                         self.o.product.eq(am0 * bm0 * 4),
-                         self.o.z.s.eq(self.i.a.s ^ self.i.b.s)
-                ]
-
-        m.d.comb += self.o.oz.eq(self.i.oz)
-        m.d.comb += self.o.out_do_z.eq(self.i.out_do_z)
-        m.d.comb += self.o.ctx.eq(self.i.ctx)
-        return m
-

diff --git a/src/ieee754/fpdiv/pipeline.py b/src/ieee754/fpdiv/pipeline.py
index 9600e72b53889993d0146ddf82d1c3f1b2aeaff8..13cac17b4edcc1dc1222bc833592a2e4b8d46bd5 100644 (file)
--- a/src/ieee754/fpdiv/pipeline.py
+++ b/src/ieee754/fpdiv/pipeline.py
@@ -11,7 +11,7 @@ scnorm   - FPDIVSpecialCasesDeNorm ispec FPADDBaseData
                             FPAddDeNormMod
 
 pipediv0 - FPDivStagesSetup        ispec FPSCData
---------                           ospec DivPipeCoreInterstageData
+--------                           ospec DivPipeInterstageData
 
                 StageChain: FPDivStage0Mod,
                             DivPipeSetupStage,
@@ -19,8 +19,8 @@ pipediv0 - FPDivStagesSetup        ispec FPSCData
                             ...
                             DivPipeCalculateStage
 
-pipediv1 - FPDivStagesIntermediate ispec DivPipeCoreInterstageData
---------                           ospec DivPipeCoreInterstageData
+pipediv1 - FPDivStagesIntermediate ispec DivPipeInterstageData
+--------                           ospec DivPipeInterstageData
 
                 StageChain: DivPipeCalculateStage,
                             ...