PHYSICAL_SYNTHESIS = Coriolis
DESIGN_KIT = cmos45
YOSYS_FLATTEN = No
- YOSYS_BLACKBOXES = pll spblock_512w64b8w
+ YOSYS_BLACKBOXES = pll spblock512w64b8w
# YOSYS_SET_TOP = Yes
CHIP = chip
CORE = ls180
`include "litex_ls180.v"
-`include "spblock_512w64b8w.v"
+`include "spblock512w64b8w.v"
`include "libresoc.v"
--- /dev/null
+(* blackbox = 1 *)
+module spblock512w64b8w(a, d, q, we, clk);
+ input [8:0] a;
+ input [63:0] d;
+ output [63:0] q;
+ input [7:0] we;
+ input clk;
+endmodule // SPBlock_512W64B8W
+
+++ /dev/null
-(* blackbox = 1 *)
-module spblock_512w64b8w(a, d, q, we, clk);
- input [8:0] a;
- input [63:0] d;
- output [63:0] q;
- input [7:0] we;
- input clk;
-endmodule // SPBlock_512W64B8W
-