whoops broke downconvert rounding

diff --git a/src/ieee754/fcvt/downsize.py b/src/ieee754/fcvt/downsize.py
index 2e61dcfb2fe4d8d9a80ef605a97a531a7d4563f6..b76e3f5e2c42a574e8ea555b601c72daad739b2a 100644 (file)
--- a/src/ieee754/fcvt/downsize.py
+++ b/src/ieee754/fcvt/downsize.py
@@ -108,7 +108,7 @@ class FPCVTDownConvertMod(PipeModBase):
             mo = Signal(self.o.z.m_width-1)
             comb += mo.eq(a1.m[ms:me])
             with m.If(self.o.of.roundz):
-                with m.If((mo.bool())):  # mantissa-out is all 1s
+                with m.If(((~mo).bool())):  # mantissa-out is all 1s
                     comb += self.o.z.create(a1.s, a1.e, mo+1)
                 with m.Else():
                     comb += self.o.z.create(a1.s, a1.e+1, mo+1)

diff --git a/src/ieee754/fcvt/test/fcvt_data_32_16.py b/src/ieee754/fcvt/test/fcvt_data_32_16.py
index 7be0829aaf9e2195e918f8810f24dff9162125b6..ed960a3f389a8ead2ffa410a2dc2255d20ad79de 100644 (file)
--- a/src/ieee754/fcvt/test/fcvt_data_32_16.py
+++ b/src/ieee754/fcvt/test/fcvt_data_32_16.py
@@ -14,4 +14,4 @@ def regressions():
     yield 0x358637BD,
     yield 0x3340f2a7,
     yield 0x33D6BF95,
-
+    yield 0x40801d50,