use soc.bus.sram instead of nmigen_soc.wishbone.sram

diff --git a/src/soc/bus/test/test_minerva.py b/src/soc/bus/test/test_minerva.py
index 9e34add2a44c783af46fe2c26a15af680bb39509..4e59437ec7a6e20bd7f4c72c6c54dee8a249098f 100644 (file)
--- a/src/soc/bus/test/test_minerva.py
+++ b/src/soc/bus/test/test_minerva.py
@@ -1,4 +1,4 @@
-from nmigen_soc.wishbone.sram import SRAM
+from soc.bus.sram import SRAM
 from nmigen import Memory, Signal, Module
 from soc.minerva.units.loadstore import BareLoadStoreUnit, CachedLoadStoreUnit
 from soc.minerva.units.fetch import BareFetchUnit, CachedFetchUnit

diff --git a/src/soc/bus/test/test_sram_wb_downconvert.py b/src/soc/bus/test/test_sram_wb_downconvert.py
index fe87bf49a0818e16ada6c00de9d63fa86b739d43..7b5a5e9dc607c9ca59a21782e050c4a84339ebe6 100644 (file)
--- a/src/soc/bus/test/test_sram_wb_downconvert.py
+++ b/src/soc/bus/test/test_sram_wb_downconvert.py
@@ -1,7 +1,7 @@
 """demonstration of nmigen-soc SRAM behind a wishbone bus and a downconverter
 """
 from nmigen_soc.wishbone.bus import Interface
-from nmigen_soc.wishbone.sram import SRAM
+from soc.bus.sram import SRAM
 from nmigen import Memory, Signal, Module
 from nmigen.utils import log2_int
 from soc.bus.wb_downconvert import WishboneDownConvert

diff --git a/src/soc/bus/test/test_sram_wishbone.py b/src/soc/bus/test/test_sram_wishbone.py
index 05ecc202624cd63fa3de5375d6d55836ece04a3b..6011845d95203a7849a56912c405bc5dca69cf39 100644 (file)
--- a/src/soc/bus/test/test_sram_wishbone.py
+++ b/src/soc/bus/test/test_sram_wishbone.py
@@ -2,7 +2,7 @@
 Bugs:
 * https://bugs.libre-soc.org/show_bug.cgi?id=382
 """
-from nmigen_soc.wishbone.sram import SRAM
+from soc.bus.sram import SRAM
 from nmigen import Memory, Signal, Module
 
 # NOTE: to use cxxsim, export NMIGEN_SIM_MODE=cxxsim from the shell

diff --git a/src/soc/debug/dmi2jtag.py b/src/soc/debug/dmi2jtag.py
index bc32f58045cca2a7f1c4a004e69536c2c4da3c3c..50b21166c19da5f86ea4925679cb67a055a829db 100644 (file)
--- a/src/soc/debug/dmi2jtag.py
+++ b/src/soc/debug/dmi2jtag.py
@@ -7,7 +7,7 @@ from nmigen import (Module, Signal, Elaboratable, Const)
 from nmigen.cli import rtlil
 from c4m.nmigen.jtag.tap import TAP, IOType
 
-from nmigen_soc.wishbone.sram import SRAM
+from soc.bus.sram import SRAM
 from nmigen import Memory, Signal, Module
 
 from nmigen.back.pysim import Simulator, Delay, Settle, Tick

diff --git a/src/soc/debug/firmware_upload.py b/src/soc/debug/firmware_upload.py
index e0e16867619b12a53f4b46db6b804feff8ef9a93..053b386025256d1ece2ebb9983aa893f684889fd 100644 (file)
--- a/src/soc/debug/firmware_upload.py
+++ b/src/soc/debug/firmware_upload.py
@@ -13,7 +13,7 @@ from soc.debug.test.dmi_sim import dmi_sim
 from soc.debug.jtag import JTAG
 from soc.debug.test.jtagremote import JTAGServer, JTAGClient
 
-from nmigen_soc.wishbone.sram import SRAM
+from soc.bus.sram import SRAM
 from nmigen import Memory, Signal, Module
 
 from nmigen.back.pysim import Simulator, Delay, Settle, Tick

diff --git a/src/soc/debug/test/test_jtag_tap.py b/src/soc/debug/test/test_jtag_tap.py
index 757c313c54a67db054097cc8dba979cac64424b1..528aa34ab2e19fb8bc29a948b8db3e967f25cb17 100644 (file)
--- a/src/soc/debug/test/test_jtag_tap.py
+++ b/src/soc/debug/test/test_jtag_tap.py
@@ -9,7 +9,7 @@ from soc.debug.dmi import DMIInterface, DBGCore
 from soc.debug.test.dmi_sim import dmi_sim
 from soc.debug.dmi2jtag import DMITAP
 
-from nmigen_soc.wishbone.sram import SRAM
+from soc.bus.sram import SRAM
 from nmigen import Memory, Signal, Module
 
 from nmigen.back.pysim import Simulator, Delay, Settle, Tick

diff --git a/src/soc/debug/test/test_jtag_tap_srv.py b/src/soc/debug/test/test_jtag_tap_srv.py
index cbc25463e00fa53dd2471ec1f7f6ccc330663456..a72145754974946a705cb126d68064e5cf6ab5e1 100644 (file)
--- a/src/soc/debug/test/test_jtag_tap_srv.py
+++ b/src/soc/debug/test/test_jtag_tap_srv.py
@@ -12,7 +12,7 @@ from soc.debug.test.dmi_sim import dmi_sim
 from soc.debug.jtag import JTAG
 from soc.debug.test.jtagremote import JTAGServer, JTAGClient
 
-from nmigen_soc.wishbone.sram import SRAM
+from soc.bus.sram import SRAM
 from nmigen import Memory, Signal, Module
 
 from nmigen.back.pysim import Simulator, Delay, Settle, Tick

diff --git a/src/soc/experiment/dcache.py b/src/soc/experiment/dcache.py
index e1f82b77dc337467c1f9eeff306adc2ade4a7120..959bff5626fff64b6142839436156c71f49e2116 100644 (file)
--- a/src/soc/experiment/dcache.py
+++ b/src/soc/experiment/dcache.py
@@ -30,7 +30,7 @@ from soc.experiment.cache_ram import CacheRam
 from nmutil.plru import PLRU
 
 # for test
-from nmigen_soc.wishbone.sram import SRAM
+from soc.bus.sram import SRAM
 from nmigen import Memory
 from nmigen.cli import rtlil
 

diff --git a/src/soc/experiment/icache.py b/src/soc/experiment/icache.py
index 732245c1c26ceeef31a3743e4bbf943dff15874e..1b8aa8586a761337cf5cb09359b807cd66576516 100644 (file)
--- a/src/soc/experiment/icache.py
+++ b/src/soc/experiment/icache.py
@@ -41,7 +41,7 @@ from soc.experiment.wb_types import (WB_ADDR_BITS, WB_DATA_BITS,
                                      WBIOMasterOut, WBIOSlaveOut)
 
 # for test
-from nmigen_soc.wishbone.sram import SRAM
+from soc.bus.sram import SRAM
 from nmigen import Memory
 from nmutil.util import wrap
 from nmigen.cli import main, rtlil