add cached fetch unit pass-through args

diff --git a/src/soc/minerva/units/fetch.py b/src/soc/minerva/units/fetch.py
index 6b78e801fc912a896d26bf5e5ff3da9c85645c35..023f8909511a1a6d5b655fe20a693d20de25b9df 100644 (file)
--- a/src/soc/minerva/units/fetch.py
+++ b/src/soc/minerva/units/fetch.py
@@ -75,13 +75,13 @@ class BareFetchUnit(FetchUnitInterface, Elaboratable):
 
 
 class CachedFetchUnit(FetchUnitInterface, Elaboratable):
-    def __init__(self, *icache_args):
-        super().__init__()
+    def __init__(self, *icache_args, addr_wid=32, data_wid=32):
+        super().__init__(addr_wid=addr_wid, data_wid=data_wid)
 
         self.icache_args = icache_args
 
         self.a_flush = Signal()
-        self.f_pc = Signal(32)
+        self.f_pc = Signal(addr_wid)
 
     def elaborate(self, platform):
         m = Module()