delayed_part_ops is a local

diff --git a/src/ieee754/part_mul_add/multiply.py b/src/ieee754/part_mul_add/multiply.py
index d048065ffb5852b2df430250aa9b90590269fed0..d852b18cc4fa947dd9b49b7da8831695e5f7613b 100644 (file)
--- a/src/ieee754/part_mul_add/multiply.py
+++ b/src/ieee754/part_mul_add/multiply.py
@@ -557,10 +557,6 @@ class Mul8_16_32_64(Elaboratable):
         self.output = Signal(64)
         self.register_levels = list(register_levels)
         self._intermediate_output = Signal(128)
-        self._delayed_part_ops = [
-            [Signal(2, name=f"_delayed_part_ops_{delay}_{i}")
-             for i in range(8)]
-            for delay in range(1 + len(self.register_levels))]
         self._output_64 = Signal(64)
         self._output_32 = Signal(64)
         self._output_16 = Signal(64)
@@ -586,10 +582,14 @@ class Mul8_16_32_64(Elaboratable):
             tl.append(pb)
         m.d.comb += pbs.eq(Cat(*tl))
 
+        delayed_part_ops = [
+            [Signal(2, name=f"_delayed_part_ops_{delay}_{i}")
+             for i in range(8)]
+            for delay in range(1 + len(self.register_levels))]
         for i in range(len(self.part_ops)):
-            m.d.comb += self._delayed_part_ops[0][i].eq(self.part_ops[i])
-            m.d.sync += [self._delayed_part_ops[j + 1][i]
-                         .eq(self._delayed_part_ops[j][i])
+            m.d.comb += delayed_part_ops[0][i].eq(self.part_ops[i])
+            m.d.sync += [delayed_part_ops[j + 1][i]
+                         .eq(delayed_part_ops[j][i])
                          for j in range(len(self.register_levels))]
 
         n_levels = len(self.register_levels)+1
@@ -663,7 +663,7 @@ class Mul8_16_32_64(Elaboratable):
         m.submodules.add_reduce = add_reduce
         m.d.comb += self._intermediate_output.eq(add_reduce.output)
         m.d.comb += self._output_64.eq(
-            Mux(self._delayed_part_ops[-1][0] == OP_MUL_LOW,
+            Mux(delayed_part_ops[-1][0] == OP_MUL_LOW,
                 self._intermediate_output.bit_select(0, 64),
                 self._intermediate_output.bit_select(64, 64)))
 
@@ -672,7 +672,7 @@ class Mul8_16_32_64(Elaboratable):
         for i in range(2):
             op = Signal(32, reset_less=True, name="op32_%d" % i)
             m.d.comb += op.eq(
-                Mux(self._delayed_part_ops[-1][4 * i] == OP_MUL_LOW,
+                Mux(delayed_part_ops[-1][4 * i] == OP_MUL_LOW,
                     self._intermediate_output.bit_select(i * 64, 32),
                     self._intermediate_output.bit_select(i * 64 + 32, 32)))
             ol.append(op)
@@ -683,7 +683,7 @@ class Mul8_16_32_64(Elaboratable):
         for i in range(4):
             op = Signal(16, reset_less=True, name="op16_%d" % i)
             m.d.comb += op.eq(
-                Mux(self._delayed_part_ops[-1][2 * i] == OP_MUL_LOW,
+                Mux(delayed_part_ops[-1][2 * i] == OP_MUL_LOW,
                     self._intermediate_output.bit_select(i * 32, 16),
                     self._intermediate_output.bit_select(i * 32 + 16, 16)))
             ol.append(op)
@@ -694,7 +694,7 @@ class Mul8_16_32_64(Elaboratable):
         for i in range(8):
             op = Signal(8, reset_less=True, name="op8_%d" % i)
             m.d.comb += op.eq(
-                Mux(self._delayed_part_ops[-1][i] == OP_MUL_LOW,
+                Mux(delayed_part_ops[-1][i] == OP_MUL_LOW,
                     self._intermediate_output.bit_select(i * 16, 8),
                     self._intermediate_output.bit_select(i * 16 + 8, 8)))
             ol.append(op)

diff --git a/src/ieee754/part_mul_add/test/test_multiply.py b/src/ieee754/part_mul_add/test/test_multiply.py
index d96d45c138d97e8f88edc39bb4e49d202f7bb8dd..0c0b420b7f53cbeb9623207fba82eabaf8221bc1 100644 (file)
--- a/src/ieee754/part_mul_add/test/test_multiply.py
+++ b/src/ieee754/part_mul_add/test/test_multiply.py
@@ -525,8 +525,6 @@ class TestMul8_16_32_64(unittest.TestCase):
                  module.output]
         ports.extend(module.part_ops)
         ports.extend(module.part_pts.values())
-        for signals in module._delayed_part_ops:
-            ports.extend(signals)
         ports += [module._output_64,
                   module._output_32,
                   module._output_16,