Enable the Simple-V loop test case

diff --git a/src/soc/fu/alu/test/svp64_cases.py b/src/soc/fu/alu/test/svp64_cases.py
index 59b39db4977c42bac4aafcffd98788777bbc4763..335e3bfdb46215ce894232f100d0ef0ab2890ad5 100644 (file)
--- a/src/soc/fu/alu/test/svp64_cases.py
+++ b/src/soc/fu/alu/test/svp64_cases.py
@@ -7,7 +7,6 @@ from soc.sv.trans.svp64 import SVP64Asm
 
 class SVP64ALUTestCase(TestAccumulatorBase):
 
-    @skip_case("VL hardware loop is not yet implemented")
     def case_1_sv_add(self):
         # adds:
         #       1 = 5 + 9   => 0x5555 = 0x4321 + 0x1234