add missing ECP5 model OBZ.v and rename testbench

diff --git a/runsimsoc_hyperram.sh b/runsimsoc_hyperram.sh
index 4e235d45a70139fc46c8116d8e1987f3946bdc44..3bba16d08a159ac1accc6c73e37c921e9ddd2160 100755 (executable)
--- a/runsimsoc_hyperram.sh
+++ b/runsimsoc_hyperram.sh
@@ -23,7 +23,7 @@ iverilog -Wall -g2012 -s simsoc_hyperram_tb -o simsoc \
     ${LIB_DIR}/PUR.v ${LIB_DIR}/GSR.v \
        ${LIB_DIR}/FD1S3AX.v ${LIB_DIR}/SGSR.v ${LIB_DIR}/ODDRX2F.v \
     ${LIB_DIR}/ODDRX2DQA.v ${LIB_DIR}/DELAYF.v ${LIB_DIR}/BB.v \
-    ${LIB_DIR}/OB.v ${LIB_DIR}/IB.v \
+    ${LIB_DIR}/OB.v ${LIB_DIR}/IB.v ${LIB_DIR}/OBZ.v \
        ${LIB_DIR}/DQSBUFM.v ${LIB_DIR}/UDFDL5_UDP_X.v \
     ${LIB_DIR}/TSHX2DQSA.v ${LIB_DIR}/TSHX2DQA.v \
     ${LIB_DIR}/ODDRX2DQSB.v ${LIB_DIR}/IDDRX2DQA.v \

diff --git a/src/simsoc_hyperram_tb.v b/src/simsoc_hyperram_tb.v
index be28bd213a66963bd8614a0503ab1f8726bd003c..e19a4a0b249e720a225aad604dd56e94de661726 100644 (file)
--- a/src/simsoc_hyperram_tb.v
+++ b/src/simsoc_hyperram_tb.v
@@ -3,7 +3,7 @@
 
 `timescale 1 ns / 1 ns
 
-module simsoctb;
+module simsoc_hyperram_tb;
   // GSR & PUR init requires for Lattice models
   GSR GSR_INST (
     .GSR(1'b1)