change name of submodule to real_pll

diff --git a/src/soc/clock/dummypll.py b/src/soc/clock/dummypll.py
index f8eb0abb31af6a68053c4e0079ae3962487ab430..fd437ef1410ba05a00581dcf10e07527e7e14491 100644 (file)
--- a/src/soc/clock/dummypll.py
+++ b/src/soc/clock/dummypll.py
@@ -25,13 +25,13 @@ class DummyPLL(Elaboratable):
                                   o_div_out_test=self.pll_test_o,
                                   o_vco_test_ana=self.pll_vco_o,
                            )
-            m.submodules['pll'] = pll
+            m.submodules['real_pll'] = pll
             #pll.attrs['blackbox'] = 1
         else:
             m.d.comb += self.clk_pll_o.eq(self.clk_24_i) # just pass through
             # just get something, stops yosys destroying (optimising) these out
             with m.If(self.clk_sel_i == 0):
-                m.d.comb += self.pll_ana_o.eq(self.clk_24_i)
+                m.d.comb += self.pll_test_o.eq(self.clk_24_i)
                 m.d.comb += self.pll_vco_o.eq(~self.clk_24_i)
 
 

diff --git a/src/soc/litex/florent b/src/soc/litex/florent
index e4ffa78b6ca6cc9ed8d0407c4a73394991003663..670638591d786b042f85f3839c59eb92e34ba1e6 160000 (submodule)
--- a/src/soc/litex/florent
+++ b/src/soc/litex/florent
@@ -1 +1 @@
-Subproject commit e4ffa78b6ca6cc9ed8d0407c4a73394991003663
+Subproject commit 670638591d786b042f85f3839c59eb92e34ba1e6