re-examining dcache.vhdl, still did not get the store-page

address quite right

diff --git a/src/soc/experiment/dcache.py b/src/soc/experiment/dcache.py
index eb8b8bf938245030e9063a6d1deaef3ea063e0fe..b7c059aa77051089ff47966805900ec9f4193023 100644 (file)
--- a/src/soc/experiment/dcache.py
+++ b/src/soc/experiment/dcache.py
@@ -1639,8 +1639,8 @@ class DCache(Elaboratable):
                     # See if there is another store waiting
                     # to be done which is in the same real page.
                     with m.If(req.valid):
-                        _ra = req.real_addr[0:SET_SIZE_BITS]
-                        sync += r1.wb.adr[0:SET_SIZE_BITS].eq(_ra)
+                        _ra = req.real_addr[ROW_OFF_BITS:SET_SIZE_BITS]
+                        sync += r1.wb.adr[0:SET_SIZE_BITS-ROW_OFF_BITS].eq(_ra)
                         sync += r1.wb.dat.eq(req.data)
                         sync += r1.wb.sel.eq(req.byte_sel)