connect \_idblock_id_bypass \$9
connect \_idblock_select_id \$7
end
-attribute \src "ls180.v:4.1-10563.10"
+attribute \src "ls180.v:4.1-10555.10"
attribute \cells_not_processed 1
module \ls180
- attribute \src "ls180.v:10047.1-10057.4"
- wire width 7 $0$memwr$\mem$ls180.v:10049$1_ADDR[6:0]$2681
- attribute \src "ls180.v:10047.1-10057.4"
- wire width 32 $0$memwr$\mem$ls180.v:10049$1_DATA[31:0]$2682
- attribute \src "ls180.v:10047.1-10057.4"
- wire width 32 $0$memwr$\mem$ls180.v:10049$1_EN[31:0]$2683
- attribute \src "ls180.v:10047.1-10057.4"
- wire width 7 $0$memwr$\mem$ls180.v:10051$2_ADDR[6:0]$2684
- attribute \src "ls180.v:10047.1-10057.4"
- wire width 32 $0$memwr$\mem$ls180.v:10051$2_DATA[31:0]$2685
- attribute \src "ls180.v:10047.1-10057.4"
- wire width 32 $0$memwr$\mem$ls180.v:10051$2_EN[31:0]$2686
- attribute \src "ls180.v:10047.1-10057.4"
- wire width 7 $0$memwr$\mem$ls180.v:10053$3_ADDR[6:0]$2687
- attribute \src "ls180.v:10047.1-10057.4"
- wire width 32 $0$memwr$\mem$ls180.v:10053$3_DATA[31:0]$2688
- attribute \src "ls180.v:10047.1-10057.4"
- wire width 32 $0$memwr$\mem$ls180.v:10053$3_EN[31:0]$2689
- attribute \src "ls180.v:10047.1-10057.4"
- wire width 7 $0$memwr$\mem$ls180.v:10055$4_ADDR[6:0]$2690
- attribute \src "ls180.v:10047.1-10057.4"
- wire width 32 $0$memwr$\mem$ls180.v:10055$4_DATA[31:0]$2691
- attribute \src "ls180.v:10047.1-10057.4"
- wire width 32 $0$memwr$\mem$ls180.v:10055$4_EN[31:0]$2692
- attribute \src "ls180.v:10067.1-10071.4"
- wire width 3 $0$memwr$\storage$ls180.v:10069$5_ADDR[2:0]$2695
- attribute \src "ls180.v:10067.1-10071.4"
- wire width 25 $0$memwr$\storage$ls180.v:10069$5_DATA[24:0]$2696
- attribute \src "ls180.v:10067.1-10071.4"
- wire width 25 $0$memwr$\storage$ls180.v:10069$5_EN[24:0]$2697
- attribute \src "ls180.v:10081.1-10085.4"
- wire width 3 $0$memwr$\storage_1$ls180.v:10083$6_ADDR[2:0]$2702
- attribute \src "ls180.v:10081.1-10085.4"
- wire width 25 $0$memwr$\storage_1$ls180.v:10083$6_DATA[24:0]$2703
- attribute \src "ls180.v:10081.1-10085.4"
- wire width 25 $0$memwr$\storage_1$ls180.v:10083$6_EN[24:0]$2704
- attribute \src "ls180.v:10095.1-10099.4"
- wire width 3 $0$memwr$\storage_2$ls180.v:10097$7_ADDR[2:0]$2709
- attribute \src "ls180.v:10095.1-10099.4"
- wire width 25 $0$memwr$\storage_2$ls180.v:10097$7_DATA[24:0]$2710
- attribute \src "ls180.v:10095.1-10099.4"
- wire width 25 $0$memwr$\storage_2$ls180.v:10097$7_EN[24:0]$2711
- attribute \src "ls180.v:10109.1-10113.4"
- wire width 3 $0$memwr$\storage_3$ls180.v:10111$8_ADDR[2:0]$2716
- attribute \src "ls180.v:10109.1-10113.4"
- wire width 25 $0$memwr$\storage_3$ls180.v:10111$8_DATA[24:0]$2717
- attribute \src "ls180.v:10109.1-10113.4"
- wire width 25 $0$memwr$\storage_3$ls180.v:10111$8_EN[24:0]$2718
- attribute \src "ls180.v:10124.1-10128.4"
- wire width 4 $0$memwr$\storage_4$ls180.v:10126$9_ADDR[3:0]$2723
- attribute \src "ls180.v:10124.1-10128.4"
- wire width 10 $0$memwr$\storage_4$ls180.v:10126$9_DATA[9:0]$2724
- attribute \src "ls180.v:10124.1-10128.4"
- wire width 10 $0$memwr$\storage_4$ls180.v:10126$9_EN[9:0]$2725
- attribute \src "ls180.v:10141.1-10145.4"
- wire width 4 $0$memwr$\storage_5$ls180.v:10143$10_ADDR[3:0]$2730
- attribute \src "ls180.v:10141.1-10145.4"
- wire width 10 $0$memwr$\storage_5$ls180.v:10143$10_DATA[9:0]$2731
- attribute \src "ls180.v:10141.1-10145.4"
- wire width 10 $0$memwr$\storage_5$ls180.v:10143$10_EN[9:0]$2732
- attribute \src "ls180.v:10157.1-10161.4"
- wire width 5 $0$memwr$\storage_6$ls180.v:10159$11_ADDR[4:0]$2737
- attribute \src "ls180.v:10157.1-10161.4"
- wire width 10 $0$memwr$\storage_6$ls180.v:10159$11_DATA[9:0]$2738
- attribute \src "ls180.v:10157.1-10161.4"
- wire width 10 $0$memwr$\storage_6$ls180.v:10159$11_EN[9:0]$2739
- attribute \src "ls180.v:10171.1-10175.4"
- wire width 5 $0$memwr$\storage_7$ls180.v:10173$12_ADDR[4:0]$2744
- attribute \src "ls180.v:10171.1-10175.4"
- wire width 10 $0$memwr$\storage_7$ls180.v:10173$12_DATA[9:0]$2745
- attribute \src "ls180.v:10171.1-10175.4"
- wire width 10 $0$memwr$\storage_7$ls180.v:10173$12_EN[9:0]$2746
- attribute \src "ls180.v:3226.1-3319.4"
+ attribute \src "ls180.v:10043.1-10053.4"
+ wire width 7 $0$memwr$\mem$ls180.v:10045$1_ADDR[6:0]$2681
+ attribute \src "ls180.v:10043.1-10053.4"
+ wire width 32 $0$memwr$\mem$ls180.v:10045$1_DATA[31:0]$2682
+ attribute \src "ls180.v:10043.1-10053.4"
+ wire width 32 $0$memwr$\mem$ls180.v:10045$1_EN[31:0]$2683
+ attribute \src "ls180.v:10043.1-10053.4"
+ wire width 7 $0$memwr$\mem$ls180.v:10047$2_ADDR[6:0]$2684
+ attribute \src "ls180.v:10043.1-10053.4"
+ wire width 32 $0$memwr$\mem$ls180.v:10047$2_DATA[31:0]$2685
+ attribute \src "ls180.v:10043.1-10053.4"
+ wire width 32 $0$memwr$\mem$ls180.v:10047$2_EN[31:0]$2686
+ attribute \src "ls180.v:10043.1-10053.4"
+ wire width 7 $0$memwr$\mem$ls180.v:10049$3_ADDR[6:0]$2687
+ attribute \src "ls180.v:10043.1-10053.4"
+ wire width 32 $0$memwr$\mem$ls180.v:10049$3_DATA[31:0]$2688
+ attribute \src "ls180.v:10043.1-10053.4"
+ wire width 32 $0$memwr$\mem$ls180.v:10049$3_EN[31:0]$2689
+ attribute \src "ls180.v:10043.1-10053.4"
+ wire width 7 $0$memwr$\mem$ls180.v:10051$4_ADDR[6:0]$2690
+ attribute \src "ls180.v:10043.1-10053.4"
+ wire width 32 $0$memwr$\mem$ls180.v:10051$4_DATA[31:0]$2691
+ attribute \src "ls180.v:10043.1-10053.4"
+ wire width 32 $0$memwr$\mem$ls180.v:10051$4_EN[31:0]$2692
+ attribute \src "ls180.v:10063.1-10067.4"
+ wire width 3 $0$memwr$\storage$ls180.v:10065$5_ADDR[2:0]$2695
+ attribute \src "ls180.v:10063.1-10067.4"
+ wire width 25 $0$memwr$\storage$ls180.v:10065$5_DATA[24:0]$2696
+ attribute \src "ls180.v:10063.1-10067.4"
+ wire width 25 $0$memwr$\storage$ls180.v:10065$5_EN[24:0]$2697
+ attribute \src "ls180.v:10077.1-10081.4"
+ wire width 3 $0$memwr$\storage_1$ls180.v:10079$6_ADDR[2:0]$2702
+ attribute \src "ls180.v:10077.1-10081.4"
+ wire width 25 $0$memwr$\storage_1$ls180.v:10079$6_DATA[24:0]$2703
+ attribute \src "ls180.v:10077.1-10081.4"
+ wire width 25 $0$memwr$\storage_1$ls180.v:10079$6_EN[24:0]$2704
+ attribute \src "ls180.v:10091.1-10095.4"
+ wire width 3 $0$memwr$\storage_2$ls180.v:10093$7_ADDR[2:0]$2709
+ attribute \src "ls180.v:10091.1-10095.4"
+ wire width 25 $0$memwr$\storage_2$ls180.v:10093$7_DATA[24:0]$2710
+ attribute \src "ls180.v:10091.1-10095.4"
+ wire width 25 $0$memwr$\storage_2$ls180.v:10093$7_EN[24:0]$2711
+ attribute \src "ls180.v:10105.1-10109.4"
+ wire width 3 $0$memwr$\storage_3$ls180.v:10107$8_ADDR[2:0]$2716
+ attribute \src "ls180.v:10105.1-10109.4"
+ wire width 25 $0$memwr$\storage_3$ls180.v:10107$8_DATA[24:0]$2717
+ attribute \src "ls180.v:10105.1-10109.4"
+ wire width 25 $0$memwr$\storage_3$ls180.v:10107$8_EN[24:0]$2718
+ attribute \src "ls180.v:10120.1-10124.4"
+ wire width 4 $0$memwr$\storage_4$ls180.v:10122$9_ADDR[3:0]$2723
+ attribute \src "ls180.v:10120.1-10124.4"
+ wire width 10 $0$memwr$\storage_4$ls180.v:10122$9_DATA[9:0]$2724
+ attribute \src "ls180.v:10120.1-10124.4"
+ wire width 10 $0$memwr$\storage_4$ls180.v:10122$9_EN[9:0]$2725
+ attribute \src "ls180.v:10137.1-10141.4"
+ wire width 4 $0$memwr$\storage_5$ls180.v:10139$10_ADDR[3:0]$2730
+ attribute \src "ls180.v:10137.1-10141.4"
+ wire width 10 $0$memwr$\storage_5$ls180.v:10139$10_DATA[9:0]$2731
+ attribute \src "ls180.v:10137.1-10141.4"
+ wire width 10 $0$memwr$\storage_5$ls180.v:10139$10_EN[9:0]$2732
+ attribute \src "ls180.v:10153.1-10157.4"
+ wire width 5 $0$memwr$\storage_6$ls180.v:10155$11_ADDR[4:0]$2737
+ attribute \src "ls180.v:10153.1-10157.4"
+ wire width 10 $0$memwr$\storage_6$ls180.v:10155$11_DATA[9:0]$2738
+ attribute \src "ls180.v:10153.1-10157.4"
+ wire width 10 $0$memwr$\storage_6$ls180.v:10155$11_EN[9:0]$2739
+ attribute \src "ls180.v:10167.1-10171.4"
+ wire width 5 $0$memwr$\storage_7$ls180.v:10169$12_ADDR[4:0]$2744
+ attribute \src "ls180.v:10167.1-10171.4"
+ wire width 10 $0$memwr$\storage_7$ls180.v:10169$12_DATA[9:0]$2745
+ attribute \src "ls180.v:10167.1-10171.4"
+ wire width 10 $0$memwr$\storage_7$ls180.v:10169$12_EN[9:0]$2746
+ attribute \src "ls180.v:3222.1-3315.4"
wire width 3 $0\builder_bankmachine0_next_state[2:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 3 $0\builder_bankmachine0_state[2:0]
- attribute \src "ls180.v:3383.1-3476.4"
+ attribute \src "ls180.v:3379.1-3472.4"
wire width 3 $0\builder_bankmachine1_next_state[2:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 3 $0\builder_bankmachine1_state[2:0]
- attribute \src "ls180.v:3540.1-3633.4"
+ attribute \src "ls180.v:3536.1-3629.4"
wire width 3 $0\builder_bankmachine2_next_state[2:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 3 $0\builder_bankmachine2_state[2:0]
- attribute \src "ls180.v:3697.1-3790.4"
+ attribute \src "ls180.v:3693.1-3786.4"
wire width 3 $0\builder_bankmachine3_next_state[2:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 3 $0\builder_bankmachine3_state[2:0]
- attribute \src "ls180.v:6520.1-6536.4"
+ attribute \src "ls180.v:6516.1-6532.4"
wire $0\builder_comb_rhs_array_muxed0[0:0]
- attribute \src "ls180.v:6741.1-6757.4"
+ attribute \src "ls180.v:6737.1-6753.4"
wire $0\builder_comb_rhs_array_muxed10[0:0]
- attribute \src "ls180.v:6758.1-6774.4"
+ attribute \src "ls180.v:6754.1-6770.4"
wire $0\builder_comb_rhs_array_muxed11[0:0]
- attribute \src "ls180.v:6826.1-6833.4"
+ attribute \src "ls180.v:6822.1-6829.4"
wire width 22 $0\builder_comb_rhs_array_muxed12[21:0]
- attribute \src "ls180.v:6834.1-6841.4"
+ attribute \src "ls180.v:6830.1-6837.4"
wire $0\builder_comb_rhs_array_muxed13[0:0]
- attribute \src "ls180.v:6842.1-6849.4"
+ attribute \src "ls180.v:6838.1-6845.4"
wire $0\builder_comb_rhs_array_muxed14[0:0]
- attribute \src "ls180.v:6850.1-6857.4"
+ attribute \src "ls180.v:6846.1-6853.4"
wire width 22 $0\builder_comb_rhs_array_muxed15[21:0]
- attribute \src "ls180.v:6858.1-6865.4"
+ attribute \src "ls180.v:6854.1-6861.4"
wire $0\builder_comb_rhs_array_muxed16[0:0]
- attribute \src "ls180.v:6866.1-6873.4"
+ attribute \src "ls180.v:6862.1-6869.4"
wire $0\builder_comb_rhs_array_muxed17[0:0]
- attribute \src "ls180.v:6874.1-6881.4"
+ attribute \src "ls180.v:6870.1-6877.4"
wire width 22 $0\builder_comb_rhs_array_muxed18[21:0]
- attribute \src "ls180.v:6882.1-6889.4"
+ attribute \src "ls180.v:6878.1-6885.4"
wire $0\builder_comb_rhs_array_muxed19[0:0]
- attribute \src "ls180.v:6537.1-6553.4"
+ attribute \src "ls180.v:6533.1-6549.4"
wire width 13 $0\builder_comb_rhs_array_muxed1[12:0]
- attribute \src "ls180.v:6890.1-6897.4"
+ attribute \src "ls180.v:6886.1-6893.4"
wire $0\builder_comb_rhs_array_muxed20[0:0]
- attribute \src "ls180.v:6898.1-6905.4"
+ attribute \src "ls180.v:6894.1-6901.4"
wire width 22 $0\builder_comb_rhs_array_muxed21[21:0]
- attribute \src "ls180.v:6906.1-6913.4"
+ attribute \src "ls180.v:6902.1-6909.4"
wire $0\builder_comb_rhs_array_muxed22[0:0]
- attribute \src "ls180.v:6914.1-6921.4"
+ attribute \src "ls180.v:6910.1-6917.4"
wire $0\builder_comb_rhs_array_muxed23[0:0]
- attribute \src "ls180.v:6922.1-6941.4"
+ attribute \src "ls180.v:6918.1-6937.4"
wire width 32 $0\builder_comb_rhs_array_muxed24[31:0]
- attribute \src "ls180.v:6942.1-6961.4"
+ attribute \src "ls180.v:6938.1-6957.4"
wire width 32 $0\builder_comb_rhs_array_muxed25[31:0]
- attribute \src "ls180.v:6962.1-6981.4"
+ attribute \src "ls180.v:6958.1-6977.4"
wire width 4 $0\builder_comb_rhs_array_muxed26[3:0]
- attribute \src "ls180.v:6982.1-7001.4"
+ attribute \src "ls180.v:6978.1-6997.4"
wire $0\builder_comb_rhs_array_muxed27[0:0]
- attribute \src "ls180.v:7002.1-7021.4"
+ attribute \src "ls180.v:6998.1-7017.4"
wire $0\builder_comb_rhs_array_muxed28[0:0]
- attribute \src "ls180.v:7022.1-7041.4"
+ attribute \src "ls180.v:7018.1-7037.4"
wire $0\builder_comb_rhs_array_muxed29[0:0]
- attribute \src "ls180.v:6554.1-6570.4"
+ attribute \src "ls180.v:6550.1-6566.4"
wire width 2 $0\builder_comb_rhs_array_muxed2[1:0]
- attribute \src "ls180.v:7042.1-7061.4"
+ attribute \src "ls180.v:7038.1-7057.4"
wire width 3 $0\builder_comb_rhs_array_muxed30[2:0]
- attribute \src "ls180.v:7062.1-7081.4"
+ attribute \src "ls180.v:7058.1-7077.4"
wire width 2 $0\builder_comb_rhs_array_muxed31[1:0]
- attribute \src "ls180.v:6571.1-6587.4"
+ attribute \src "ls180.v:6567.1-6583.4"
wire $0\builder_comb_rhs_array_muxed3[0:0]
- attribute \src "ls180.v:6588.1-6604.4"
+ attribute \src "ls180.v:6584.1-6600.4"
wire $0\builder_comb_rhs_array_muxed4[0:0]
- attribute \src "ls180.v:6605.1-6621.4"
+ attribute \src "ls180.v:6601.1-6617.4"
wire $0\builder_comb_rhs_array_muxed5[0:0]
- attribute \src "ls180.v:6673.1-6689.4"
+ attribute \src "ls180.v:6669.1-6685.4"
wire $0\builder_comb_rhs_array_muxed6[0:0]
- attribute \src "ls180.v:6690.1-6706.4"
+ attribute \src "ls180.v:6686.1-6702.4"
wire width 13 $0\builder_comb_rhs_array_muxed7[12:0]
- attribute \src "ls180.v:6707.1-6723.4"
+ attribute \src "ls180.v:6703.1-6719.4"
wire width 2 $0\builder_comb_rhs_array_muxed8[1:0]
- attribute \src "ls180.v:6724.1-6740.4"
+ attribute \src "ls180.v:6720.1-6736.4"
wire $0\builder_comb_rhs_array_muxed9[0:0]
- attribute \src "ls180.v:6622.1-6638.4"
+ attribute \src "ls180.v:6618.1-6634.4"
wire $0\builder_comb_t_array_muxed0[0:0]
- attribute \src "ls180.v:6639.1-6655.4"
+ attribute \src "ls180.v:6635.1-6651.4"
wire $0\builder_comb_t_array_muxed1[0:0]
- attribute \src "ls180.v:6656.1-6672.4"
+ attribute \src "ls180.v:6652.1-6668.4"
wire $0\builder_comb_t_array_muxed2[0:0]
- attribute \src "ls180.v:6775.1-6791.4"
+ attribute \src "ls180.v:6771.1-6787.4"
wire $0\builder_comb_t_array_muxed3[0:0]
- attribute \src "ls180.v:6792.1-6808.4"
+ attribute \src "ls180.v:6788.1-6804.4"
wire $0\builder_comb_t_array_muxed4[0:0]
- attribute \src "ls180.v:6809.1-6825.4"
+ attribute \src "ls180.v:6805.1-6821.4"
wire $0\builder_comb_t_array_muxed5[0:0]
- attribute \src "ls180.v:2790.1-2836.4"
+ attribute \src "ls180.v:2786.1-2832.4"
wire $0\builder_converter0_next_state[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\builder_converter0_state[0:0]
- attribute \src "ls180.v:2850.1-2896.4"
+ attribute \src "ls180.v:2846.1-2892.4"
wire $0\builder_converter1_next_state[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\builder_converter1_state[0:0]
- attribute \src "ls180.v:2910.1-2956.4"
+ attribute \src "ls180.v:2906.1-2952.4"
wire $0\builder_converter2_next_state[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\builder_converter2_state[0:0]
- attribute \src "ls180.v:4043.1-4089.4"
+ attribute \src "ls180.v:4039.1-4085.4"
wire $0\builder_converter_next_state[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\builder_converter_state[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 20 $0\builder_count[19:0]
- attribute \src "ls180.v:5760.1-5771.4"
+ attribute \src "ls180.v:5756.1-5767.4"
wire $0\builder_error[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 3 $0\builder_grant[2:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 8 $0\builder_interface0_bank_bus_dat_r[7:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 8 $0\builder_interface10_bank_bus_dat_r[7:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 8 $0\builder_interface11_bank_bus_dat_r[7:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 8 $0\builder_interface12_bank_bus_dat_r[7:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 8 $0\builder_interface13_bank_bus_dat_r[7:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 8 $0\builder_interface14_bank_bus_dat_r[7:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 8 $0\builder_interface1_bank_bus_dat_r[7:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 8 $0\builder_interface2_bank_bus_dat_r[7:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 8 $0\builder_interface3_bank_bus_dat_r[7:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 8 $0\builder_interface4_bank_bus_dat_r[7:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 8 $0\builder_interface5_bank_bus_dat_r[7:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 8 $0\builder_interface6_bank_bus_dat_r[7:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 8 $0\builder_interface7_bank_bus_dat_r[7:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 8 $0\builder_interface8_bank_bus_dat_r[7:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 8 $0\builder_interface9_bank_bus_dat_r[7:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 14 $0\builder_libresocsim_adr[13:0]
- attribute \src "ls180.v:5649.1-5685.4"
+ attribute \src "ls180.v:5645.1-5681.4"
wire width 14 $0\builder_libresocsim_adr_next_value1[13:0]
- attribute \src "ls180.v:5649.1-5685.4"
+ attribute \src "ls180.v:5645.1-5681.4"
wire $0\builder_libresocsim_adr_next_value_ce1[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 8 $0\builder_libresocsim_dat_w[7:0]
- attribute \src "ls180.v:5649.1-5685.4"
+ attribute \src "ls180.v:5645.1-5681.4"
wire width 8 $0\builder_libresocsim_dat_w_next_value0[7:0]
- attribute \src "ls180.v:5649.1-5685.4"
+ attribute \src "ls180.v:5645.1-5681.4"
wire $0\builder_libresocsim_dat_w_next_value_ce0[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\builder_libresocsim_we[0:0]
- attribute \src "ls180.v:5649.1-5685.4"
+ attribute \src "ls180.v:5645.1-5681.4"
wire $0\builder_libresocsim_we_next_value2[0:0]
- attribute \src "ls180.v:5649.1-5685.4"
+ attribute \src "ls180.v:5645.1-5681.4"
wire $0\builder_libresocsim_we_next_value_ce2[0:0]
- attribute \src "ls180.v:5649.1-5685.4"
+ attribute \src "ls180.v:5645.1-5681.4"
wire $0\builder_libresocsim_wishbone_ack[0:0]
- attribute \src "ls180.v:5649.1-5685.4"
+ attribute \src "ls180.v:5645.1-5681.4"
wire width 32 $0\builder_libresocsim_wishbone_dat_r[31:0]
- attribute \src "ls180.v:1881.5-1881.44"
+ attribute \src "ls180.v:1877.5-1877.44"
wire $0\builder_libresocsim_wishbone_err[0:0]
- attribute \src "ls180.v:1770.5-1770.27"
+ attribute \src "ls180.v:1766.5-1766.27"
wire $0\builder_locked0[0:0]
- attribute \src "ls180.v:1771.5-1771.27"
+ attribute \src "ls180.v:1767.5-1767.27"
wire $0\builder_locked1[0:0]
- attribute \src "ls180.v:1772.5-1772.27"
+ attribute \src "ls180.v:1768.5-1768.27"
wire $0\builder_locked2[0:0]
- attribute \src "ls180.v:1773.5-1773.27"
+ attribute \src "ls180.v:1769.5-1769.27"
wire $0\builder_locked3[0:0]
- attribute \src "ls180.v:3915.1-3987.4"
+ attribute \src "ls180.v:3911.1-3983.4"
wire width 3 $0\builder_multiplexer_next_state[2:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 3 $0\builder_multiplexer_state[2:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\builder_multiregimpl0_regs0[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\builder_multiregimpl0_regs1[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\builder_multiregimpl10_regs0[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\builder_multiregimpl10_regs1[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\builder_multiregimpl11_regs0[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\builder_multiregimpl11_regs1[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\builder_multiregimpl12_regs0[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\builder_multiregimpl12_regs1[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\builder_multiregimpl13_regs0[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\builder_multiregimpl13_regs1[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\builder_multiregimpl14_regs0[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\builder_multiregimpl14_regs1[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\builder_multiregimpl15_regs0[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\builder_multiregimpl15_regs1[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\builder_multiregimpl16_regs0[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\builder_multiregimpl16_regs1[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\builder_multiregimpl1_regs0[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\builder_multiregimpl1_regs1[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\builder_multiregimpl2_regs0[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\builder_multiregimpl2_regs1[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\builder_multiregimpl3_regs0[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\builder_multiregimpl3_regs1[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\builder_multiregimpl4_regs0[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\builder_multiregimpl4_regs1[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\builder_multiregimpl5_regs0[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\builder_multiregimpl5_regs1[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\builder_multiregimpl6_regs0[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\builder_multiregimpl6_regs1[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\builder_multiregimpl7_regs0[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\builder_multiregimpl7_regs1[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\builder_multiregimpl8_regs0[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\builder_multiregimpl8_regs1[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\builder_multiregimpl9_regs0[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\builder_multiregimpl9_regs1[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\builder_new_master_rdata_valid0[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\builder_new_master_rdata_valid1[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\builder_new_master_rdata_valid2[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\builder_new_master_rdata_valid3[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\builder_new_master_wdata_ready[0:0]
- attribute \src "ls180.v:5649.1-5685.4"
+ attribute \src "ls180.v:5645.1-5681.4"
wire width 2 $0\builder_next_state[1:0]
- attribute \src "ls180.v:3132.1-3162.4"
+ attribute \src "ls180.v:3128.1-3158.4"
wire width 2 $0\builder_refresher_next_state[1:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 2 $0\builder_refresher_state[1:0]
- attribute \src "ls180.v:5459.1-5498.4"
+ attribute \src "ls180.v:5455.1-5494.4"
wire width 2 $0\builder_sdblock2memdma_next_state[1:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 2 $0\builder_sdblock2memdma_state[1:0]
- attribute \src "ls180.v:5026.1-5105.4"
+ attribute \src "ls180.v:5022.1-5101.4"
wire $0\builder_sdcore_crcupstreaminserter_next_state[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\builder_sdcore_crcupstreaminserter_state[0:0]
- attribute \src "ls180.v:5208.1-5398.4"
+ attribute \src "ls180.v:5204.1-5394.4"
wire width 3 $0\builder_sdcore_fsm_next_state[2:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 3 $0\builder_sdcore_fsm_state[2:0]
- attribute \src "ls180.v:5518.1-5555.4"
+ attribute \src "ls180.v:5514.1-5551.4"
wire $0\builder_sdmem2blockdma_fsm_next_state[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\builder_sdmem2blockdma_fsm_state[0:0]
- attribute \src "ls180.v:5556.1-5592.4"
+ attribute \src "ls180.v:5552.1-5588.4"
wire width 2 $0\builder_sdmem2blockdma_resetinserter_next_state[1:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 2 $0\builder_sdmem2blockdma_resetinserter_state[1:0]
- attribute \src "ls180.v:4701.1-4773.4"
+ attribute \src "ls180.v:4697.1-4769.4"
wire width 3 $0\builder_sdphy_fsm_next_state[2:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 3 $0\builder_sdphy_fsm_state[2:0]
- attribute \src "ls180.v:4546.1-4639.4"
+ attribute \src "ls180.v:4542.1-4635.4"
wire width 3 $0\builder_sdphy_sdphycmdr_next_state[2:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 3 $0\builder_sdphy_sdphycmdr_state[2:0]
- attribute \src "ls180.v:4436.1-4512.4"
+ attribute \src "ls180.v:4432.1-4508.4"
wire width 2 $0\builder_sdphy_sdphycmdw_next_state[1:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 2 $0\builder_sdphy_sdphycmdw_state[1:0]
- attribute \src "ls180.v:4673.1-4700.4"
+ attribute \src "ls180.v:4669.1-4696.4"
wire $0\builder_sdphy_sdphycrcr_next_state[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\builder_sdphy_sdphycrcr_state[0:0]
- attribute \src "ls180.v:4807.1-4908.4"
+ attribute \src "ls180.v:4803.1-4904.4"
wire width 3 $0\builder_sdphy_sdphydatar_next_state[2:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 3 $0\builder_sdphy_sdphydatar_state[2:0]
- attribute \src "ls180.v:4402.1-4435.4"
+ attribute \src "ls180.v:4398.1-4431.4"
wire $0\builder_sdphy_sdphyinit_next_state[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\builder_sdphy_sdphyinit_state[0:0]
- attribute \src "ls180.v:5760.1-5771.4"
+ attribute \src "ls180.v:5756.1-5767.4"
wire $0\builder_shared_ack[0:0]
- attribute \src "ls180.v:5760.1-5771.4"
+ attribute \src "ls180.v:5756.1-5767.4"
wire width 32 $0\builder_shared_dat_r[31:0]
- attribute \src "ls180.v:5710.1-5717.4"
+ attribute \src "ls180.v:5706.1-5713.4"
wire width 5 $0\builder_slave_sel[4:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 5 $0\builder_slave_sel_r[4:0]
- attribute \src "ls180.v:4233.1-4281.4"
+ attribute \src "ls180.v:4229.1-4277.4"
wire width 2 $0\builder_spimaster0_next_state[1:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 2 $0\builder_spimaster0_state[1:0]
- attribute \src "ls180.v:4292.1-4340.4"
+ attribute \src "ls180.v:4288.1-4336.4"
wire width 2 $0\builder_spimaster1_next_state[1:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 2 $0\builder_spimaster1_state[1:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 2 $0\builder_state[1:0]
- attribute \src "ls180.v:7201.1-7229.4"
+ attribute \src "ls180.v:7197.1-7225.4"
wire $0\builder_sync_f_array_muxed0[0:0]
- attribute \src "ls180.v:7230.1-7258.4"
+ attribute \src "ls180.v:7226.1-7254.4"
wire $0\builder_sync_f_array_muxed1[0:0]
- attribute \src "ls180.v:7082.1-7098.4"
+ attribute \src "ls180.v:7078.1-7094.4"
wire width 2 $0\builder_sync_rhs_array_muxed0[1:0]
- attribute \src "ls180.v:7099.1-7115.4"
+ attribute \src "ls180.v:7095.1-7111.4"
wire width 13 $0\builder_sync_rhs_array_muxed1[12:0]
- attribute \src "ls180.v:7116.1-7132.4"
+ attribute \src "ls180.v:7112.1-7128.4"
wire $0\builder_sync_rhs_array_muxed2[0:0]
- attribute \src "ls180.v:7133.1-7149.4"
+ attribute \src "ls180.v:7129.1-7145.4"
wire $0\builder_sync_rhs_array_muxed3[0:0]
- attribute \src "ls180.v:7150.1-7166.4"
+ attribute \src "ls180.v:7146.1-7162.4"
wire $0\builder_sync_rhs_array_muxed4[0:0]
- attribute \src "ls180.v:7167.1-7183.4"
+ attribute \src "ls180.v:7163.1-7179.4"
wire $0\builder_sync_rhs_array_muxed5[0:0]
- attribute \src "ls180.v:7184.1-7200.4"
+ attribute \src "ls180.v:7180.1-7196.4"
wire $0\builder_sync_rhs_array_muxed6[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\main_cmd_consumed[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\main_converter_counter[0:0]
- attribute \src "ls180.v:4043.1-4089.4"
+ attribute \src "ls180.v:4039.1-4085.4"
wire $0\main_converter_counter_converter_next_value[0:0]
- attribute \src "ls180.v:4043.1-4089.4"
+ attribute \src "ls180.v:4039.1-4085.4"
wire $0\main_converter_counter_converter_next_value_ce[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 32 $0\main_converter_dat_r[31:0]
- attribute \src "ls180.v:4043.1-4089.4"
+ attribute \src "ls180.v:4039.1-4085.4"
wire $0\main_converter_skip[0:0]
- attribute \src "ls180.v:7359.1-7429.4"
+ attribute \src "ls180.v:7355.1-7425.4"
wire width 16 $0\main_dfi_p0_rddata[15:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\main_dfi_p0_rddata_valid[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 24 $0\main_dummy[23:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\main_gpio_oe_re[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 16 $0\main_gpio_oe_storage[15:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\main_gpio_out_re[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 16 $0\main_gpio_out_storage[15:0]
- attribute \src "ls180.v:7316.1-7334.4"
+ attribute \src "ls180.v:7312.1-7330.4"
wire width 16 $0\main_gpio_status[15:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\main_i2c_re[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 3 $0\main_i2c_storage[2:0]
- attribute \src "ls180.v:7355.1-7357.4"
+ attribute \src "ls180.v:7351.1-7353.4"
wire $0\main_int_rst[0:0]
- attribute \src "ls180.v:1558.11-1558.41"
+ attribute \src "ls180.v:1554.11-1554.41"
wire width 2 $0\main_interface0_bus_bte[1:0]
- attribute \src "ls180.v:1557.11-1557.41"
+ attribute \src "ls180.v:1553.11-1553.41"
wire width 3 $0\main_interface0_bus_cti[2:0]
- attribute \src "ls180.v:5518.1-5555.4"
+ attribute \src "ls180.v:5514.1-5551.4"
wire width 32 $0\main_interface1_bus_adr[31:0]
- attribute \src "ls180.v:1649.11-1649.41"
+ attribute \src "ls180.v:1645.11-1645.41"
wire width 2 $0\main_interface1_bus_bte[1:0]
- attribute \src "ls180.v:1648.11-1648.41"
+ attribute \src "ls180.v:1644.11-1644.41"
wire width 3 $0\main_interface1_bus_cti[2:0]
- attribute \src "ls180.v:5518.1-5555.4"
+ attribute \src "ls180.v:5514.1-5551.4"
wire $0\main_interface1_bus_cyc[0:0]
- attribute \src "ls180.v:1641.12-1641.45"
+ attribute \src "ls180.v:1637.12-1637.45"
wire width 32 $0\main_interface1_bus_dat_w[31:0]
- attribute \src "ls180.v:5518.1-5555.4"
+ attribute \src "ls180.v:5514.1-5551.4"
wire width 4 $0\main_interface1_bus_sel[3:0]
- attribute \src "ls180.v:5518.1-5555.4"
+ attribute \src "ls180.v:5514.1-5551.4"
wire $0\main_interface1_bus_stb[0:0]
- attribute \src "ls180.v:5518.1-5555.4"
+ attribute \src "ls180.v:5514.1-5551.4"
wire $0\main_interface1_bus_we[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 32 $0\main_libresocsim_bus_errors[31:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\main_libresocsim_converter0_counter[0:0]
- attribute \src "ls180.v:2790.1-2836.4"
+ attribute \src "ls180.v:2786.1-2832.4"
wire $0\main_libresocsim_converter0_counter_converter0_next_value[0:0]
- attribute \src "ls180.v:2790.1-2836.4"
+ attribute \src "ls180.v:2786.1-2832.4"
wire $0\main_libresocsim_converter0_counter_converter0_next_value_ce[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 64 $0\main_libresocsim_converter0_dat_r[63:0]
- attribute \src "ls180.v:2790.1-2836.4"
+ attribute \src "ls180.v:2786.1-2832.4"
wire $0\main_libresocsim_converter0_skip[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\main_libresocsim_converter1_counter[0:0]
- attribute \src "ls180.v:2850.1-2896.4"
+ attribute \src "ls180.v:2846.1-2892.4"
wire $0\main_libresocsim_converter1_counter_converter1_next_value[0:0]
- attribute \src "ls180.v:2850.1-2896.4"
+ attribute \src "ls180.v:2846.1-2892.4"
wire $0\main_libresocsim_converter1_counter_converter1_next_value_ce[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 64 $0\main_libresocsim_converter1_dat_r[63:0]
- attribute \src "ls180.v:2850.1-2896.4"
+ attribute \src "ls180.v:2846.1-2892.4"
wire $0\main_libresocsim_converter1_skip[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\main_libresocsim_converter2_counter[0:0]
- attribute \src "ls180.v:2910.1-2956.4"
+ attribute \src "ls180.v:2906.1-2952.4"
wire $0\main_libresocsim_converter2_counter_converter2_next_value[0:0]
- attribute \src "ls180.v:2910.1-2956.4"
+ attribute \src "ls180.v:2906.1-2952.4"
wire $0\main_libresocsim_converter2_counter_converter2_next_value_ce[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 64 $0\main_libresocsim_converter2_dat_r[63:0]
- attribute \src "ls180.v:2910.1-2956.4"
+ attribute \src "ls180.v:2906.1-2952.4"
wire $0\main_libresocsim_converter2_skip[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\main_libresocsim_en_re[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\main_libresocsim_en_storage[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\main_libresocsim_eventmanager_re[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\main_libresocsim_eventmanager_storage[0:0]
- attribute \src "ls180.v:2790.1-2836.4"
+ attribute \src "ls180.v:2786.1-2832.4"
wire width 30 $0\main_libresocsim_interface0_converted_interface_adr[29:0]
- attribute \src "ls180.v:171.11-171.69"
+ attribute \src "ls180.v:167.11-167.69"
wire width 2 $0\main_libresocsim_interface0_converted_interface_bte[1:0]
- attribute \src "ls180.v:170.11-170.69"
+ attribute \src "ls180.v:166.11-166.69"
wire width 3 $0\main_libresocsim_interface0_converted_interface_cti[2:0]
- attribute \src "ls180.v:2790.1-2836.4"
+ attribute \src "ls180.v:2786.1-2832.4"
wire $0\main_libresocsim_interface0_converted_interface_cyc[0:0]
- attribute \src "ls180.v:2778.1-2788.4"
+ attribute \src "ls180.v:2774.1-2784.4"
wire width 32 $0\main_libresocsim_interface0_converted_interface_dat_w[31:0]
- attribute \src "ls180.v:2790.1-2836.4"
+ attribute \src "ls180.v:2786.1-2832.4"
wire width 4 $0\main_libresocsim_interface0_converted_interface_sel[3:0]
- attribute \src "ls180.v:2790.1-2836.4"
+ attribute \src "ls180.v:2786.1-2832.4"
wire $0\main_libresocsim_interface0_converted_interface_stb[0:0]
- attribute \src "ls180.v:2790.1-2836.4"
+ attribute \src "ls180.v:2786.1-2832.4"
wire $0\main_libresocsim_interface0_converted_interface_we[0:0]
- attribute \src "ls180.v:2850.1-2896.4"
+ attribute \src "ls180.v:2846.1-2892.4"
wire width 30 $0\main_libresocsim_interface1_converted_interface_adr[29:0]
- attribute \src "ls180.v:186.11-186.69"
+ attribute \src "ls180.v:182.11-182.69"
wire width 2 $0\main_libresocsim_interface1_converted_interface_bte[1:0]
- attribute \src "ls180.v:185.11-185.69"
+ attribute \src "ls180.v:181.11-181.69"
wire width 3 $0\main_libresocsim_interface1_converted_interface_cti[2:0]
- attribute \src "ls180.v:2850.1-2896.4"
+ attribute \src "ls180.v:2846.1-2892.4"
wire $0\main_libresocsim_interface1_converted_interface_cyc[0:0]
- attribute \src "ls180.v:2838.1-2848.4"
+ attribute \src "ls180.v:2834.1-2844.4"
wire width 32 $0\main_libresocsim_interface1_converted_interface_dat_w[31:0]
- attribute \src "ls180.v:2850.1-2896.4"
+ attribute \src "ls180.v:2846.1-2892.4"
wire width 4 $0\main_libresocsim_interface1_converted_interface_sel[3:0]
- attribute \src "ls180.v:2850.1-2896.4"
+ attribute \src "ls180.v:2846.1-2892.4"
wire $0\main_libresocsim_interface1_converted_interface_stb[0:0]
- attribute \src "ls180.v:2850.1-2896.4"
+ attribute \src "ls180.v:2846.1-2892.4"
wire $0\main_libresocsim_interface1_converted_interface_we[0:0]
- attribute \src "ls180.v:2910.1-2956.4"
+ attribute \src "ls180.v:2906.1-2952.4"
wire width 30 $0\main_libresocsim_interface2_converted_interface_adr[29:0]
- attribute \src "ls180.v:201.11-201.69"
+ attribute \src "ls180.v:197.11-197.69"
wire width 2 $0\main_libresocsim_interface2_converted_interface_bte[1:0]
- attribute \src "ls180.v:200.11-200.69"
+ attribute \src "ls180.v:196.11-196.69"
wire width 3 $0\main_libresocsim_interface2_converted_interface_cti[2:0]
- attribute \src "ls180.v:2910.1-2956.4"
+ attribute \src "ls180.v:2906.1-2952.4"
wire $0\main_libresocsim_interface2_converted_interface_cyc[0:0]
- attribute \src "ls180.v:2898.1-2908.4"
+ attribute \src "ls180.v:2894.1-2904.4"
wire width 32 $0\main_libresocsim_interface2_converted_interface_dat_w[31:0]
- attribute \src "ls180.v:2910.1-2956.4"
+ attribute \src "ls180.v:2906.1-2952.4"
wire width 4 $0\main_libresocsim_interface2_converted_interface_sel[3:0]
- attribute \src "ls180.v:2910.1-2956.4"
+ attribute \src "ls180.v:2906.1-2952.4"
wire $0\main_libresocsim_interface2_converted_interface_stb[0:0]
- attribute \src "ls180.v:2910.1-2956.4"
+ attribute \src "ls180.v:2906.1-2952.4"
wire $0\main_libresocsim_interface2_converted_interface_we[0:0]
- attribute \src "ls180.v:2850.1-2896.4"
+ attribute \src "ls180.v:2846.1-2892.4"
wire $0\main_libresocsim_libresoc_dbus_ack[0:0]
- attribute \src "ls180.v:76.5-76.46"
+ attribute \src "ls180.v:74.5-74.46"
wire $0\main_libresocsim_libresoc_dbus_err[0:0]
- attribute \src "ls180.v:2790.1-2836.4"
+ attribute \src "ls180.v:2786.1-2832.4"
wire $0\main_libresocsim_libresoc_ibus_ack[0:0]
- attribute \src "ls180.v:87.5-87.46"
+ attribute \src "ls180.v:83.5-83.46"
wire $0\main_libresocsim_libresoc_ibus_err[0:0]
- attribute \src "ls180.v:2771.1-2776.4"
+ attribute \src "ls180.v:2767.1-2772.4"
wire width 16 $0\main_libresocsim_libresoc_interrupt[15:0]
- attribute \src "ls180.v:2910.1-2956.4"
+ attribute \src "ls180.v:2906.1-2952.4"
wire $0\main_libresocsim_libresoc_jtag_wb_ack[0:0]
- attribute \src "ls180.v:118.5-118.49"
+ attribute \src "ls180.v:114.5-114.49"
wire $0\main_libresocsim_libresoc_jtag_wb_err[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\main_libresocsim_load_re[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 32 $0\main_libresocsim_load_storage[31:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\main_libresocsim_ram_bus_ack[0:0]
- attribute \src "ls180.v:217.5-217.40"
+ attribute \src "ls180.v:213.5-213.40"
wire $0\main_libresocsim_ram_bus_err[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\main_libresocsim_reload_re[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 32 $0\main_libresocsim_reload_storage[31:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\main_libresocsim_reset_re[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\main_libresocsim_reset_storage[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\main_libresocsim_scratch_re[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 32 $0\main_libresocsim_scratch_storage[31:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\main_libresocsim_update_value_re[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\main_libresocsim_update_value_storage[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 32 $0\main_libresocsim_value[31:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 32 $0\main_libresocsim_value_status[31:0]
- attribute \src "ls180.v:2959.1-2965.4"
+ attribute \src "ls180.v:2955.1-2961.4"
wire width 4 $0\main_libresocsim_we[3:0]
- attribute \src "ls180.v:2971.1-2976.4"
+ attribute \src "ls180.v:2967.1-2972.4"
wire $0\main_libresocsim_zero_clear[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\main_libresocsim_zero_old_trigger[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\main_libresocsim_zero_pending[0:0]
- attribute \src "ls180.v:4043.1-4089.4"
+ attribute \src "ls180.v:4039.1-4085.4"
wire width 30 $0\main_litedram_wb_adr[29:0]
- attribute \src "ls180.v:4043.1-4089.4"
+ attribute \src "ls180.v:4039.1-4085.4"
wire $0\main_litedram_wb_cyc[0:0]
- attribute \src "ls180.v:4031.1-4041.4"
+ attribute \src "ls180.v:4027.1-4037.4"
wire width 16 $0\main_litedram_wb_dat_w[15:0]
- attribute \src "ls180.v:4043.1-4089.4"
+ attribute \src "ls180.v:4039.1-4085.4"
wire width 2 $0\main_litedram_wb_sel[1:0]
- attribute \src "ls180.v:4043.1-4089.4"
+ attribute \src "ls180.v:4039.1-4085.4"
wire $0\main_litedram_wb_stb[0:0]
- attribute \src "ls180.v:4043.1-4089.4"
+ attribute \src "ls180.v:4039.1-4085.4"
wire $0\main_litedram_wb_we[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 32 $0\main_pwm0_counter[31:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\main_pwm0_enable_re[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\main_pwm0_enable_storage[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\main_pwm0_period_re[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 32 $0\main_pwm0_period_storage[31:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\main_pwm0_width_re[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 32 $0\main_pwm0_width_storage[31:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 32 $0\main_pwm1_counter[31:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\main_pwm1_enable_re[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\main_pwm1_enable_storage[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\main_pwm1_period_re[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 32 $0\main_pwm1_period_storage[31:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\main_pwm1_width_re[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 32 $0\main_pwm1_width_storage[31:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 3 $0\main_rddata_en[2:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 2 $0\main_sdblock2mem_converter_demux[1:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\main_sdblock2mem_converter_source_first[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\main_sdblock2mem_converter_source_last[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 32 $0\main_sdblock2mem_converter_source_payload_data[31:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 3 $0\main_sdblock2mem_converter_source_payload_valid_token_count[2:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\main_sdblock2mem_converter_strobe_all[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 5 $0\main_sdblock2mem_fifo_consume[4:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 6 $0\main_sdblock2mem_fifo_level[5:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 5 $0\main_sdblock2mem_fifo_produce[4:0]
- attribute \src "ls180.v:1582.5-1582.41"
+ attribute \src "ls180.v:1578.5-1578.41"
wire $0\main_sdblock2mem_fifo_replace[0:0]
- attribute \src "ls180.v:5426.1-5433.4"
+ attribute \src "ls180.v:5422.1-5429.4"
wire width 5 $0\main_sdblock2mem_fifo_wrport_adr[4:0]
- attribute \src "ls180.v:5459.1-5498.4"
+ attribute \src "ls180.v:5455.1-5494.4"
wire width 32 $0\main_sdblock2mem_sink_sink_payload_address[31:0]
- attribute \src "ls180.v:5459.1-5498.4"
+ attribute \src "ls180.v:5455.1-5494.4"
wire width 32 $0\main_sdblock2mem_sink_sink_payload_data1[31:0]
- attribute \src "ls180.v:5459.1-5498.4"
+ attribute \src "ls180.v:5455.1-5494.4"
wire $0\main_sdblock2mem_sink_sink_valid1[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\main_sdblock2mem_wishbonedmawriter_base_re[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 64 $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\main_sdblock2mem_wishbonedmawriter_enable_re[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\main_sdblock2mem_wishbonedmawriter_length_re[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 32 $0\main_sdblock2mem_wishbonedmawriter_length_storage[31:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\main_sdblock2mem_wishbonedmawriter_loop_re[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 32 $0\main_sdblock2mem_wishbonedmawriter_offset[31:0]
- attribute \src "ls180.v:5459.1-5498.4"
+ attribute \src "ls180.v:5455.1-5494.4"
wire width 32 $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0]
- attribute \src "ls180.v:5459.1-5498.4"
+ attribute \src "ls180.v:5455.1-5494.4"
wire $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0]
- attribute \src "ls180.v:5459.1-5498.4"
+ attribute \src "ls180.v:5455.1-5494.4"
wire $0\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0]
- attribute \src "ls180.v:5459.1-5498.4"
+ attribute \src "ls180.v:5455.1-5494.4"
wire $0\main_sdblock2mem_wishbonedmawriter_status[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\main_sdcore_block_count_re[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 32 $0\main_sdcore_block_count_storage[31:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\main_sdcore_block_length_re[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 10 $0\main_sdcore_block_length_storage[9:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\main_sdcore_cmd_argument_re[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 32 $0\main_sdcore_cmd_argument_storage[31:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\main_sdcore_cmd_command_re[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 32 $0\main_sdcore_cmd_command_storage[31:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 3 $0\main_sdcore_cmd_count[2:0]
- attribute \src "ls180.v:5208.1-5398.4"
+ attribute \src "ls180.v:5204.1-5394.4"
wire width 3 $0\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0]
- attribute \src "ls180.v:5208.1-5398.4"
+ attribute \src "ls180.v:5204.1-5394.4"
wire $0\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\main_sdcore_cmd_done[0:0]
- attribute \src "ls180.v:5208.1-5398.4"
+ attribute \src "ls180.v:5204.1-5394.4"
wire $0\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0]
- attribute \src "ls180.v:5208.1-5398.4"
+ attribute \src "ls180.v:5204.1-5394.4"
wire $0\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\main_sdcore_cmd_error[0:0]
- attribute \src "ls180.v:5208.1-5398.4"
+ attribute \src "ls180.v:5204.1-5394.4"
wire $0\main_sdcore_cmd_error_sdcore_fsm_next_value4[0:0]
- attribute \src "ls180.v:5208.1-5398.4"
+ attribute \src "ls180.v:5204.1-5394.4"
wire $0\main_sdcore_cmd_error_sdcore_fsm_next_value_ce4[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 128 $0\main_sdcore_cmd_response_status[127:0]
- attribute \src "ls180.v:5208.1-5398.4"
+ attribute \src "ls180.v:5204.1-5394.4"
wire width 128 $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0]
- attribute \src "ls180.v:5208.1-5398.4"
+ attribute \src "ls180.v:5204.1-5394.4"
wire $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0]
- attribute \src "ls180.v:1391.5-1391.34"
+ attribute \src "ls180.v:1387.5-1387.34"
wire $0\main_sdcore_cmd_send_w[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\main_sdcore_cmd_timeout[0:0]
- attribute \src "ls180.v:5208.1-5398.4"
+ attribute \src "ls180.v:5204.1-5394.4"
wire $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0]
- attribute \src "ls180.v:5208.1-5398.4"
+ attribute \src "ls180.v:5204.1-5394.4"
wire $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 4 $0\main_sdcore_crc16_checker_cnt[3:0]
- attribute \src "ls180.v:5114.1-5121.4"
+ attribute \src "ls180.v:5110.1-5117.4"
wire $0\main_sdcore_crc16_checker_crc0_clr[0:0]
- attribute \src "ls180.v:5170.1-5177.4"
+ attribute \src "ls180.v:5166.1-5173.4"
wire width 16 $0\main_sdcore_crc16_checker_crc0_crc[15:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 16 $0\main_sdcore_crc16_checker_crc0_crcreg0[15:0]
- attribute \src "ls180.v:5124.1-5131.4"
+ attribute \src "ls180.v:5120.1-5127.4"
wire $0\main_sdcore_crc16_checker_crc1_clr[0:0]
- attribute \src "ls180.v:5180.1-5187.4"
+ attribute \src "ls180.v:5176.1-5183.4"
wire width 16 $0\main_sdcore_crc16_checker_crc1_crc[15:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 16 $0\main_sdcore_crc16_checker_crc1_crcreg0[15:0]
- attribute \src "ls180.v:5134.1-5141.4"
+ attribute \src "ls180.v:5130.1-5137.4"
wire $0\main_sdcore_crc16_checker_crc2_clr[0:0]
- attribute \src "ls180.v:5190.1-5197.4"
+ attribute \src "ls180.v:5186.1-5193.4"
wire width 16 $0\main_sdcore_crc16_checker_crc2_crc[15:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 16 $0\main_sdcore_crc16_checker_crc2_crcreg0[15:0]
- attribute \src "ls180.v:5144.1-5151.4"
+ attribute \src "ls180.v:5140.1-5147.4"
wire $0\main_sdcore_crc16_checker_crc3_clr[0:0]
- attribute \src "ls180.v:5200.1-5207.4"
+ attribute \src "ls180.v:5196.1-5203.4"
wire width 16 $0\main_sdcore_crc16_checker_crc3_crc[15:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 16 $0\main_sdcore_crc16_checker_crc3_crcreg0[15:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 16 $0\main_sdcore_crc16_checker_crctmp0[15:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 16 $0\main_sdcore_crc16_checker_crctmp1[15:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 16 $0\main_sdcore_crc16_checker_crctmp2[15:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 16 $0\main_sdcore_crc16_checker_crctmp3[15:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 16 $0\main_sdcore_crc16_checker_fifo0[15:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 16 $0\main_sdcore_crc16_checker_fifo1[15:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 16 $0\main_sdcore_crc16_checker_fifo2[15:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 16 $0\main_sdcore_crc16_checker_fifo3[15:0]
- attribute \src "ls180.v:5208.1-5398.4"
+ attribute \src "ls180.v:5204.1-5394.4"
wire $0\main_sdcore_crc16_checker_sink_first[0:0]
- attribute \src "ls180.v:5208.1-5398.4"
+ attribute \src "ls180.v:5204.1-5394.4"
wire $0\main_sdcore_crc16_checker_sink_last[0:0]
- attribute \src "ls180.v:5208.1-5398.4"
+ attribute \src "ls180.v:5204.1-5394.4"
wire width 8 $0\main_sdcore_crc16_checker_sink_payload_data[7:0]
- attribute \src "ls180.v:5159.1-5166.4"
+ attribute \src "ls180.v:5155.1-5162.4"
wire $0\main_sdcore_crc16_checker_sink_ready[0:0]
- attribute \src "ls180.v:5208.1-5398.4"
+ attribute \src "ls180.v:5204.1-5394.4"
wire $0\main_sdcore_crc16_checker_sink_valid[0:0]
- attribute \src "ls180.v:1497.5-1497.50"
+ attribute \src "ls180.v:1493.5-1493.50"
wire $0\main_sdcore_crc16_checker_source_first[0:0]
- attribute \src "ls180.v:5153.1-5158.4"
+ attribute \src "ls180.v:5149.1-5154.4"
wire $0\main_sdcore_crc16_checker_source_valid[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 8 $0\main_sdcore_crc16_checker_val[7:0]
- attribute \src "ls180.v:5106.1-5111.4"
+ attribute \src "ls180.v:5102.1-5107.4"
wire $0\main_sdcore_crc16_checker_valid[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 3 $0\main_sdcore_crc16_inserter_cnt[2:0]
- attribute \src "ls180.v:5026.1-5105.4"
+ attribute \src "ls180.v:5022.1-5101.4"
wire width 3 $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0]
- attribute \src "ls180.v:5026.1-5105.4"
+ attribute \src "ls180.v:5022.1-5101.4"
wire $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0]
- attribute \src "ls180.v:4988.1-4995.4"
+ attribute \src "ls180.v:4984.1-4991.4"
wire width 16 $0\main_sdcore_crc16_inserter_crc0_crc[15:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 16 $0\main_sdcore_crc16_inserter_crc0_crcreg0[15:0]
- attribute \src "ls180.v:4998.1-5005.4"
+ attribute \src "ls180.v:4994.1-5001.4"
wire width 16 $0\main_sdcore_crc16_inserter_crc1_crc[15:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 16 $0\main_sdcore_crc16_inserter_crc1_crcreg0[15:0]
- attribute \src "ls180.v:5008.1-5015.4"
+ attribute \src "ls180.v:5004.1-5011.4"
wire width 16 $0\main_sdcore_crc16_inserter_crc2_crc[15:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 16 $0\main_sdcore_crc16_inserter_crc2_crcreg0[15:0]
- attribute \src "ls180.v:5018.1-5025.4"
+ attribute \src "ls180.v:5014.1-5021.4"
wire width 16 $0\main_sdcore_crc16_inserter_crc3_crc[15:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 16 $0\main_sdcore_crc16_inserter_crc3_crcreg0[15:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 16 $0\main_sdcore_crc16_inserter_crctmp0[15:0]
- attribute \src "ls180.v:5026.1-5105.4"
+ attribute \src "ls180.v:5022.1-5101.4"
wire width 16 $0\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0]
- attribute \src "ls180.v:5026.1-5105.4"
+ attribute \src "ls180.v:5022.1-5101.4"
wire $0\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 16 $0\main_sdcore_crc16_inserter_crctmp1[15:0]
- attribute \src "ls180.v:5026.1-5105.4"
+ attribute \src "ls180.v:5022.1-5101.4"
wire width 16 $0\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0]
- attribute \src "ls180.v:5026.1-5105.4"
+ attribute \src "ls180.v:5022.1-5101.4"
wire $0\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 16 $0\main_sdcore_crc16_inserter_crctmp2[15:0]
- attribute \src "ls180.v:5026.1-5105.4"
+ attribute \src "ls180.v:5022.1-5101.4"
wire width 16 $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0]
- attribute \src "ls180.v:5026.1-5105.4"
+ attribute \src "ls180.v:5022.1-5101.4"
wire $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 16 $0\main_sdcore_crc16_inserter_crctmp3[15:0]
- attribute \src "ls180.v:5026.1-5105.4"
+ attribute \src "ls180.v:5022.1-5101.4"
wire width 16 $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0]
- attribute \src "ls180.v:5026.1-5105.4"
+ attribute \src "ls180.v:5022.1-5101.4"
wire $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0]
- attribute \src "ls180.v:5026.1-5105.4"
+ attribute \src "ls180.v:5022.1-5101.4"
wire $0\main_sdcore_crc16_inserter_sink_ready[0:0]
- attribute \src "ls180.v:1454.5-1454.51"
+ attribute \src "ls180.v:1450.5-1450.51"
wire $0\main_sdcore_crc16_inserter_source_first[0:0]
- attribute \src "ls180.v:5026.1-5105.4"
+ attribute \src "ls180.v:5022.1-5101.4"
wire $0\main_sdcore_crc16_inserter_source_last[0:0]
- attribute \src "ls180.v:5026.1-5105.4"
+ attribute \src "ls180.v:5022.1-5101.4"
wire width 8 $0\main_sdcore_crc16_inserter_source_payload_data[7:0]
- attribute \src "ls180.v:5208.1-5398.4"
+ attribute \src "ls180.v:5204.1-5394.4"
wire $0\main_sdcore_crc16_inserter_source_ready[0:0]
- attribute \src "ls180.v:5026.1-5105.4"
+ attribute \src "ls180.v:5022.1-5101.4"
wire $0\main_sdcore_crc16_inserter_source_valid[0:0]
- attribute \src "ls180.v:4966.1-4973.4"
+ attribute \src "ls180.v:4962.1-4969.4"
wire width 7 $0\main_sdcore_crc7_inserter_crc[6:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 7 $0\main_sdcore_crc7_inserter_crcreg0[6:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 32 $0\main_sdcore_data_count[31:0]
- attribute \src "ls180.v:5208.1-5398.4"
+ attribute \src "ls180.v:5204.1-5394.4"
wire width 32 $0\main_sdcore_data_count_sdcore_fsm_next_value3[31:0]
- attribute \src "ls180.v:5208.1-5398.4"
+ attribute \src "ls180.v:5204.1-5394.4"
wire $0\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\main_sdcore_data_done[0:0]
- attribute \src "ls180.v:5208.1-5398.4"
+ attribute \src "ls180.v:5204.1-5394.4"
wire $0\main_sdcore_data_done_sdcore_fsm_next_value1[0:0]
- attribute \src "ls180.v:5208.1-5398.4"
+ attribute \src "ls180.v:5204.1-5394.4"
wire $0\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\main_sdcore_data_error[0:0]
- attribute \src "ls180.v:5208.1-5398.4"
+ attribute \src "ls180.v:5204.1-5394.4"
wire $0\main_sdcore_data_error_sdcore_fsm_next_value6[0:0]
- attribute \src "ls180.v:5208.1-5398.4"
+ attribute \src "ls180.v:5204.1-5394.4"
wire $0\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\main_sdcore_data_timeout[0:0]
- attribute \src "ls180.v:5208.1-5398.4"
+ attribute \src "ls180.v:5204.1-5394.4"
wire $0\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0]
- attribute \src "ls180.v:5208.1-5398.4"
+ attribute \src "ls180.v:5204.1-5394.4"
wire $0\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 2 $0\main_sdmem2block_converter_mux[1:0]
- attribute \src "ls180.v:5604.1-5620.4"
+ attribute \src "ls180.v:5600.1-5616.4"
wire width 8 $0\main_sdmem2block_converter_source_payload_data[7:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\main_sdmem2block_dma_base_re[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 64 $0\main_sdmem2block_dma_base_storage[63:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 32 $0\main_sdmem2block_dma_data[31:0]
- attribute \src "ls180.v:5518.1-5555.4"
+ attribute \src "ls180.v:5514.1-5551.4"
wire width 32 $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[31:0]
- attribute \src "ls180.v:5518.1-5555.4"
+ attribute \src "ls180.v:5514.1-5551.4"
wire $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0]
- attribute \src "ls180.v:5556.1-5592.4"
+ attribute \src "ls180.v:5552.1-5588.4"
wire $0\main_sdmem2block_dma_done_status[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\main_sdmem2block_dma_enable_re[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\main_sdmem2block_dma_enable_storage[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\main_sdmem2block_dma_length_re[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 32 $0\main_sdmem2block_dma_length_storage[31:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\main_sdmem2block_dma_loop_re[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\main_sdmem2block_dma_loop_storage[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 32 $0\main_sdmem2block_dma_offset[31:0]
- attribute \src "ls180.v:5556.1-5592.4"
+ attribute \src "ls180.v:5552.1-5588.4"
wire width 32 $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0]
- attribute \src "ls180.v:5556.1-5592.4"
+ attribute \src "ls180.v:5552.1-5588.4"
wire $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0]
- attribute \src "ls180.v:5556.1-5592.4"
+ attribute \src "ls180.v:5552.1-5588.4"
wire $0\main_sdmem2block_dma_sink_last[0:0]
- attribute \src "ls180.v:5556.1-5592.4"
+ attribute \src "ls180.v:5552.1-5588.4"
wire width 32 $0\main_sdmem2block_dma_sink_payload_address[31:0]
- attribute \src "ls180.v:5518.1-5555.4"
+ attribute \src "ls180.v:5514.1-5551.4"
wire $0\main_sdmem2block_dma_sink_ready[0:0]
- attribute \src "ls180.v:5556.1-5592.4"
+ attribute \src "ls180.v:5552.1-5588.4"
wire $0\main_sdmem2block_dma_sink_valid[0:0]
- attribute \src "ls180.v:1662.5-1662.45"
+ attribute \src "ls180.v:1658.5-1658.45"
wire $0\main_sdmem2block_dma_source_first[0:0]
- attribute \src "ls180.v:5518.1-5555.4"
+ attribute \src "ls180.v:5514.1-5551.4"
wire $0\main_sdmem2block_dma_source_last[0:0]
- attribute \src "ls180.v:5518.1-5555.4"
+ attribute \src "ls180.v:5514.1-5551.4"
wire width 32 $0\main_sdmem2block_dma_source_payload_data[31:0]
- attribute \src "ls180.v:5518.1-5555.4"
+ attribute \src "ls180.v:5514.1-5551.4"
wire $0\main_sdmem2block_dma_source_valid[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 5 $0\main_sdmem2block_fifo_consume[4:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 6 $0\main_sdmem2block_fifo_level[5:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 5 $0\main_sdmem2block_fifo_produce[4:0]
- attribute \src "ls180.v:1718.5-1718.41"
+ attribute \src "ls180.v:1714.5-1714.41"
wire $0\main_sdmem2block_fifo_replace[0:0]
- attribute \src "ls180.v:5634.1-5641.4"
+ attribute \src "ls180.v:5630.1-5637.4"
wire width 5 $0\main_sdmem2block_fifo_wrport_adr[4:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\main_sdphy_clocker_clk0[0:0]
- attribute \src "ls180.v:4372.1-4400.4"
+ attribute \src "ls180.v:4368.1-4396.4"
wire $0\main_sdphy_clocker_clk1[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\main_sdphy_clocker_clk_d[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 9 $0\main_sdphy_clocker_clks[8:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\main_sdphy_clocker_re[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 9 $0\main_sdphy_clocker_storage[8:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\main_sdphy_cmdr_cmdr_buf_source_first[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\main_sdphy_cmdr_cmdr_buf_source_last[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 8 $0\main_sdphy_cmdr_cmdr_buf_source_payload_data[7:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\main_sdphy_cmdr_cmdr_buf_source_valid[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 3 $0\main_sdphy_cmdr_cmdr_converter_demux[2:0]
- attribute \src "ls180.v:1183.5-1183.53"
+ attribute \src "ls180.v:1179.5-1179.53"
wire $0\main_sdphy_cmdr_cmdr_converter_sink_first[0:0]
- attribute \src "ls180.v:1184.5-1184.52"
+ attribute \src "ls180.v:1180.5-1180.52"
wire $0\main_sdphy_cmdr_cmdr_converter_sink_last[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\main_sdphy_cmdr_cmdr_converter_source_first[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\main_sdphy_cmdr_cmdr_converter_source_last[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 8 $0\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 4 $0\main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count[3:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0]
- attribute \src "ls180.v:1164.5-1164.46"
+ attribute \src "ls180.v:1160.5-1160.46"
wire $0\main_sdphy_cmdr_cmdr_pads_in_ready[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\main_sdphy_cmdr_cmdr_reset[0:0]
- attribute \src "ls180.v:4546.1-4639.4"
+ attribute \src "ls180.v:4542.1-4635.4"
wire $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0]
- attribute \src "ls180.v:4546.1-4639.4"
+ attribute \src "ls180.v:4542.1-4635.4"
wire $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\main_sdphy_cmdr_cmdr_run[0:0]
- attribute \src "ls180.v:4546.1-4639.4"
+ attribute \src "ls180.v:4542.1-4635.4"
wire $0\main_sdphy_cmdr_cmdr_source_source_ready0[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 8 $0\main_sdphy_cmdr_count[7:0]
- attribute \src "ls180.v:4546.1-4639.4"
+ attribute \src "ls180.v:4542.1-4635.4"
wire width 8 $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0]
- attribute \src "ls180.v:4546.1-4639.4"
+ attribute \src "ls180.v:4542.1-4635.4"
wire $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0]
- attribute \src "ls180.v:1137.5-1137.49"
+ attribute \src "ls180.v:1133.5-1133.49"
wire $0\main_sdphy_cmdr_pads_in_pads_in_first[0:0]
- attribute \src "ls180.v:1138.5-1138.48"
+ attribute \src "ls180.v:1134.5-1134.48"
wire $0\main_sdphy_cmdr_pads_in_pads_in_last[0:0]
- attribute \src "ls180.v:1139.5-1139.55"
+ attribute \src "ls180.v:1135.5-1135.55"
wire $0\main_sdphy_cmdr_pads_in_pads_in_payload_clk[0:0]
- attribute \src "ls180.v:1141.5-1141.57"
+ attribute \src "ls180.v:1137.5-1137.57"
wire $0\main_sdphy_cmdr_pads_in_pads_in_payload_cmd_o[0:0]
- attribute \src "ls180.v:1142.5-1142.58"
+ attribute \src "ls180.v:1138.5-1138.58"
wire $0\main_sdphy_cmdr_pads_in_pads_in_payload_cmd_oe[0:0]
- attribute \src "ls180.v:1144.11-1144.64"
+ attribute \src "ls180.v:1140.11-1140.64"
wire width 4 $0\main_sdphy_cmdr_pads_in_pads_in_payload_data_o[3:0]
- attribute \src "ls180.v:1145.5-1145.59"
+ attribute \src "ls180.v:1141.5-1141.59"
wire $0\main_sdphy_cmdr_pads_in_pads_in_payload_data_oe[0:0]
- attribute \src "ls180.v:4546.1-4639.4"
+ attribute \src "ls180.v:4542.1-4635.4"
wire $0\main_sdphy_cmdr_pads_out_payload_clk[0:0]
- attribute \src "ls180.v:4546.1-4639.4"
+ attribute \src "ls180.v:4542.1-4635.4"
wire $0\main_sdphy_cmdr_pads_out_payload_cmd_o[0:0]
- attribute \src "ls180.v:4546.1-4639.4"
+ attribute \src "ls180.v:4542.1-4635.4"
wire $0\main_sdphy_cmdr_pads_out_payload_cmd_oe[0:0]
- attribute \src "ls180.v:1150.11-1150.57"
+ attribute \src "ls180.v:1146.11-1146.57"
wire width 4 $0\main_sdphy_cmdr_pads_out_payload_data_o[3:0]
- attribute \src "ls180.v:1151.5-1151.52"
+ attribute \src "ls180.v:1147.5-1147.52"
wire $0\main_sdphy_cmdr_pads_out_payload_data_oe[0:0]
- attribute \src "ls180.v:5208.1-5398.4"
+ attribute \src "ls180.v:5204.1-5394.4"
wire $0\main_sdphy_cmdr_sink_last[0:0]
- attribute \src "ls180.v:5208.1-5398.4"
+ attribute \src "ls180.v:5204.1-5394.4"
wire width 8 $0\main_sdphy_cmdr_sink_payload_length[7:0]
- attribute \src "ls180.v:4546.1-4639.4"
+ attribute \src "ls180.v:4542.1-4635.4"
wire $0\main_sdphy_cmdr_sink_ready[0:0]
- attribute \src "ls180.v:5208.1-5398.4"
+ attribute \src "ls180.v:5204.1-5394.4"
wire $0\main_sdphy_cmdr_sink_valid[0:0]
- attribute \src "ls180.v:4546.1-4639.4"
+ attribute \src "ls180.v:4542.1-4635.4"
wire $0\main_sdphy_cmdr_source_last[0:0]
- attribute \src "ls180.v:4546.1-4639.4"
+ attribute \src "ls180.v:4542.1-4635.4"
wire width 8 $0\main_sdphy_cmdr_source_payload_data[7:0]
- attribute \src "ls180.v:4546.1-4639.4"
+ attribute \src "ls180.v:4542.1-4635.4"
wire width 3 $0\main_sdphy_cmdr_source_payload_status[2:0]
- attribute \src "ls180.v:5208.1-5398.4"
+ attribute \src "ls180.v:5204.1-5394.4"
wire $0\main_sdphy_cmdr_source_ready[0:0]
- attribute \src "ls180.v:4546.1-4639.4"
+ attribute \src "ls180.v:4542.1-4635.4"
wire $0\main_sdphy_cmdr_source_valid[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 32 $0\main_sdphy_cmdr_timeout[31:0]
- attribute \src "ls180.v:4546.1-4639.4"
+ attribute \src "ls180.v:4542.1-4635.4"
wire width 32 $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0]
- attribute \src "ls180.v:4546.1-4639.4"
+ attribute \src "ls180.v:4542.1-4635.4"
wire $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 8 $0\main_sdphy_cmdw_count[7:0]
- attribute \src "ls180.v:4436.1-4512.4"
+ attribute \src "ls180.v:4432.1-4508.4"
wire width 8 $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0]
- attribute \src "ls180.v:4436.1-4512.4"
+ attribute \src "ls180.v:4432.1-4508.4"
wire $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0]
- attribute \src "ls180.v:4436.1-4512.4"
+ attribute \src "ls180.v:4432.1-4508.4"
wire $0\main_sdphy_cmdw_done[0:0]
- attribute \src "ls180.v:4436.1-4512.4"
+ attribute \src "ls180.v:4432.1-4508.4"
wire $0\main_sdphy_cmdw_pads_out_payload_clk[0:0]
- attribute \src "ls180.v:4436.1-4512.4"
+ attribute \src "ls180.v:4432.1-4508.4"
wire $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0]
- attribute \src "ls180.v:4436.1-4512.4"
+ attribute \src "ls180.v:4432.1-4508.4"
wire $0\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0]
- attribute \src "ls180.v:1127.11-1127.57"
+ attribute \src "ls180.v:1123.11-1123.57"
wire width 4 $0\main_sdphy_cmdw_pads_out_payload_data_o[3:0]
- attribute \src "ls180.v:1128.5-1128.52"
+ attribute \src "ls180.v:1124.5-1124.52"
wire $0\main_sdphy_cmdw_pads_out_payload_data_oe[0:0]
- attribute \src "ls180.v:5208.1-5398.4"
+ attribute \src "ls180.v:5204.1-5394.4"
wire $0\main_sdphy_cmdw_sink_last[0:0]
- attribute \src "ls180.v:5208.1-5398.4"
+ attribute \src "ls180.v:5204.1-5394.4"
wire width 8 $0\main_sdphy_cmdw_sink_payload_data[7:0]
- attribute \src "ls180.v:4436.1-4512.4"
+ attribute \src "ls180.v:4432.1-4508.4"
wire $0\main_sdphy_cmdw_sink_ready[0:0]
- attribute \src "ls180.v:5208.1-5398.4"
+ attribute \src "ls180.v:5204.1-5394.4"
wire $0\main_sdphy_cmdw_sink_valid[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 10 $0\main_sdphy_datar_count[9:0]
- attribute \src "ls180.v:4807.1-4908.4"
+ attribute \src "ls180.v:4803.1-4904.4"
wire width 10 $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0]
- attribute \src "ls180.v:4807.1-4908.4"
+ attribute \src "ls180.v:4803.1-4904.4"
wire $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\main_sdphy_datar_datar_buf_source_first[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\main_sdphy_datar_datar_buf_source_last[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 8 $0\main_sdphy_datar_datar_buf_source_payload_data[7:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\main_sdphy_datar_datar_buf_source_valid[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\main_sdphy_datar_datar_converter_demux[0:0]
- attribute \src "ls180.v:1339.5-1339.55"
+ attribute \src "ls180.v:1335.5-1335.55"
wire $0\main_sdphy_datar_datar_converter_sink_first[0:0]
- attribute \src "ls180.v:1340.5-1340.54"
+ attribute \src "ls180.v:1336.5-1336.54"
wire $0\main_sdphy_datar_datar_converter_sink_last[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\main_sdphy_datar_datar_converter_source_first[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\main_sdphy_datar_datar_converter_source_last[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 8 $0\main_sdphy_datar_datar_converter_source_payload_data[7:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 2 $0\main_sdphy_datar_datar_converter_source_payload_valid_token_count[1:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\main_sdphy_datar_datar_converter_strobe_all[0:0]
- attribute \src "ls180.v:1320.5-1320.48"
+ attribute \src "ls180.v:1316.5-1316.48"
wire $0\main_sdphy_datar_datar_pads_in_ready[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\main_sdphy_datar_datar_reset[0:0]
- attribute \src "ls180.v:4807.1-4908.4"
+ attribute \src "ls180.v:4803.1-4904.4"
wire $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0]
- attribute \src "ls180.v:4807.1-4908.4"
+ attribute \src "ls180.v:4803.1-4904.4"
wire $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\main_sdphy_datar_datar_run[0:0]
- attribute \src "ls180.v:4807.1-4908.4"
+ attribute \src "ls180.v:4803.1-4904.4"
wire $0\main_sdphy_datar_datar_source_source_ready0[0:0]
- attribute \src "ls180.v:1291.5-1291.50"
+ attribute \src "ls180.v:1287.5-1287.50"
wire $0\main_sdphy_datar_pads_in_pads_in_first[0:0]
- attribute \src "ls180.v:1292.5-1292.49"
+ attribute \src "ls180.v:1288.5-1288.49"
wire $0\main_sdphy_datar_pads_in_pads_in_last[0:0]
- attribute \src "ls180.v:1293.5-1293.56"
+ attribute \src "ls180.v:1289.5-1289.56"
wire $0\main_sdphy_datar_pads_in_pads_in_payload_clk[0:0]
- attribute \src "ls180.v:1295.5-1295.58"
+ attribute \src "ls180.v:1291.5-1291.58"
wire $0\main_sdphy_datar_pads_in_pads_in_payload_cmd_o[0:0]
- attribute \src "ls180.v:1296.5-1296.59"
+ attribute \src "ls180.v:1292.5-1292.59"
wire $0\main_sdphy_datar_pads_in_pads_in_payload_cmd_oe[0:0]
- attribute \src "ls180.v:1298.11-1298.65"
+ attribute \src "ls180.v:1294.11-1294.65"
wire width 4 $0\main_sdphy_datar_pads_in_pads_in_payload_data_o[3:0]
- attribute \src "ls180.v:1299.5-1299.60"
+ attribute \src "ls180.v:1295.5-1295.60"
wire $0\main_sdphy_datar_pads_in_pads_in_payload_data_oe[0:0]
- attribute \src "ls180.v:4807.1-4908.4"
+ attribute \src "ls180.v:4803.1-4904.4"
wire $0\main_sdphy_datar_pads_out_payload_clk[0:0]
- attribute \src "ls180.v:1302.5-1302.51"
+ attribute \src "ls180.v:1298.5-1298.51"
wire $0\main_sdphy_datar_pads_out_payload_cmd_o[0:0]
- attribute \src "ls180.v:1303.5-1303.52"
+ attribute \src "ls180.v:1299.5-1299.52"
wire $0\main_sdphy_datar_pads_out_payload_cmd_oe[0:0]
- attribute \src "ls180.v:1304.11-1304.58"
+ attribute \src "ls180.v:1300.11-1300.58"
wire width 4 $0\main_sdphy_datar_pads_out_payload_data_o[3:0]
- attribute \src "ls180.v:1305.5-1305.53"
+ attribute \src "ls180.v:1301.5-1301.53"
wire $0\main_sdphy_datar_pads_out_payload_data_oe[0:0]
- attribute \src "ls180.v:5208.1-5398.4"
+ attribute \src "ls180.v:5204.1-5394.4"
wire $0\main_sdphy_datar_sink_last[0:0]
- attribute \src "ls180.v:5208.1-5398.4"
+ attribute \src "ls180.v:5204.1-5394.4"
wire width 10 $0\main_sdphy_datar_sink_payload_block_length[9:0]
- attribute \src "ls180.v:4807.1-4908.4"
+ attribute \src "ls180.v:4803.1-4904.4"
wire $0\main_sdphy_datar_sink_ready[0:0]
- attribute \src "ls180.v:5208.1-5398.4"
+ attribute \src "ls180.v:5204.1-5394.4"
wire $0\main_sdphy_datar_sink_valid[0:0]
- attribute \src "ls180.v:1312.5-1312.41"
+ attribute \src "ls180.v:1308.5-1308.41"
wire $0\main_sdphy_datar_source_first[0:0]
- attribute \src "ls180.v:4807.1-4908.4"
+ attribute \src "ls180.v:4803.1-4904.4"
wire $0\main_sdphy_datar_source_last[0:0]
- attribute \src "ls180.v:4807.1-4908.4"
+ attribute \src "ls180.v:4803.1-4904.4"
wire width 8 $0\main_sdphy_datar_source_payload_data[7:0]
- attribute \src "ls180.v:4807.1-4908.4"
+ attribute \src "ls180.v:4803.1-4904.4"
wire width 3 $0\main_sdphy_datar_source_payload_status[2:0]
- attribute \src "ls180.v:5208.1-5398.4"
+ attribute \src "ls180.v:5204.1-5394.4"
wire $0\main_sdphy_datar_source_ready[0:0]
- attribute \src "ls180.v:4807.1-4908.4"
+ attribute \src "ls180.v:4803.1-4904.4"
wire $0\main_sdphy_datar_source_valid[0:0]
- attribute \src "ls180.v:4807.1-4908.4"
+ attribute \src "ls180.v:4803.1-4904.4"
wire $0\main_sdphy_datar_stop[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 32 $0\main_sdphy_datar_timeout[31:0]
- attribute \src "ls180.v:4807.1-4908.4"
+ attribute \src "ls180.v:4803.1-4904.4"
wire width 32 $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0]
- attribute \src "ls180.v:4807.1-4908.4"
+ attribute \src "ls180.v:4803.1-4904.4"
wire $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 8 $0\main_sdphy_dataw_count[7:0]
- attribute \src "ls180.v:4701.1-4773.4"
+ attribute \src "ls180.v:4697.1-4769.4"
wire width 8 $0\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0]
- attribute \src "ls180.v:4701.1-4773.4"
+ attribute \src "ls180.v:4697.1-4769.4"
wire $0\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\main_sdphy_dataw_crcr_buf_source_first[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\main_sdphy_dataw_crcr_buf_source_last[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 8 $0\main_sdphy_dataw_crcr_buf_source_payload_data[7:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\main_sdphy_dataw_crcr_buf_source_valid[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 3 $0\main_sdphy_dataw_crcr_converter_demux[2:0]
- attribute \src "ls180.v:1261.5-1261.54"
+ attribute \src "ls180.v:1257.5-1257.54"
wire $0\main_sdphy_dataw_crcr_converter_sink_first[0:0]
- attribute \src "ls180.v:1262.5-1262.53"
+ attribute \src "ls180.v:1258.5-1258.53"
wire $0\main_sdphy_dataw_crcr_converter_sink_last[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\main_sdphy_dataw_crcr_converter_source_first[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\main_sdphy_dataw_crcr_converter_source_last[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 8 $0\main_sdphy_dataw_crcr_converter_source_payload_data[7:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 4 $0\main_sdphy_dataw_crcr_converter_source_payload_valid_token_count[3:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\main_sdphy_dataw_crcr_converter_strobe_all[0:0]
- attribute \src "ls180.v:1242.5-1242.47"
+ attribute \src "ls180.v:1238.5-1238.47"
wire $0\main_sdphy_dataw_crcr_pads_in_ready[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\main_sdphy_dataw_crcr_reset[0:0]
- attribute \src "ls180.v:4673.1-4700.4"
+ attribute \src "ls180.v:4669.1-4696.4"
wire $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0]
- attribute \src "ls180.v:4673.1-4700.4"
+ attribute \src "ls180.v:4669.1-4696.4"
wire $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\main_sdphy_dataw_crcr_run[0:0]
- attribute \src "ls180.v:4673.1-4700.4"
+ attribute \src "ls180.v:4669.1-4696.4"
wire $0\main_sdphy_dataw_crcr_source_source_ready0[0:0]
- attribute \src "ls180.v:4673.1-4700.4"
+ attribute \src "ls180.v:4669.1-4696.4"
wire $0\main_sdphy_dataw_error[0:0]
- attribute \src "ls180.v:1229.5-1229.50"
+ attribute \src "ls180.v:1225.5-1225.50"
wire $0\main_sdphy_dataw_pads_in_pads_in_first[0:0]
- attribute \src "ls180.v:1230.5-1230.49"
+ attribute \src "ls180.v:1226.5-1226.49"
wire $0\main_sdphy_dataw_pads_in_pads_in_last[0:0]
- attribute \src "ls180.v:1231.5-1231.56"
+ attribute \src "ls180.v:1227.5-1227.56"
wire $0\main_sdphy_dataw_pads_in_pads_in_payload_clk[0:0]
- attribute \src "ls180.v:1232.5-1232.58"
+ attribute \src "ls180.v:1228.5-1228.58"
wire $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_i[0:0]
- attribute \src "ls180.v:1233.5-1233.58"
+ attribute \src "ls180.v:1229.5-1229.58"
wire $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_o[0:0]
- attribute \src "ls180.v:1234.5-1234.59"
+ attribute \src "ls180.v:1230.5-1230.59"
wire $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_oe[0:0]
- attribute \src "ls180.v:1235.11-1235.65"
+ attribute \src "ls180.v:1231.11-1231.65"
wire width 4 $0\main_sdphy_dataw_pads_in_pads_in_payload_data_i[3:0]
- attribute \src "ls180.v:1236.11-1236.65"
+ attribute \src "ls180.v:1232.11-1232.65"
wire width 4 $0\main_sdphy_dataw_pads_in_pads_in_payload_data_o[3:0]
- attribute \src "ls180.v:1237.5-1237.60"
+ attribute \src "ls180.v:1233.5-1233.60"
wire $0\main_sdphy_dataw_pads_in_pads_in_payload_data_oe[0:0]
- attribute \src "ls180.v:1227.5-1227.50"
+ attribute \src "ls180.v:1223.5-1223.50"
wire $0\main_sdphy_dataw_pads_in_pads_in_valid[0:0]
- attribute \src "ls180.v:4701.1-4773.4"
+ attribute \src "ls180.v:4697.1-4769.4"
wire $0\main_sdphy_dataw_pads_out_payload_clk[0:0]
- attribute \src "ls180.v:1216.5-1216.51"
+ attribute \src "ls180.v:1212.5-1212.51"
wire $0\main_sdphy_dataw_pads_out_payload_cmd_o[0:0]
- attribute \src "ls180.v:1217.5-1217.52"
+ attribute \src "ls180.v:1213.5-1213.52"
wire $0\main_sdphy_dataw_pads_out_payload_cmd_oe[0:0]
- attribute \src "ls180.v:4701.1-4773.4"
+ attribute \src "ls180.v:4697.1-4769.4"
wire width 4 $0\main_sdphy_dataw_pads_out_payload_data_o[3:0]
- attribute \src "ls180.v:4701.1-4773.4"
+ attribute \src "ls180.v:4697.1-4769.4"
wire $0\main_sdphy_dataw_pads_out_payload_data_oe[0:0]
- attribute \src "ls180.v:5208.1-5398.4"
+ attribute \src "ls180.v:5204.1-5394.4"
wire $0\main_sdphy_dataw_sink_first[0:0]
- attribute \src "ls180.v:5208.1-5398.4"
+ attribute \src "ls180.v:5204.1-5394.4"
wire $0\main_sdphy_dataw_sink_last[0:0]
- attribute \src "ls180.v:5208.1-5398.4"
+ attribute \src "ls180.v:5204.1-5394.4"
wire width 8 $0\main_sdphy_dataw_sink_payload_data[7:0]
- attribute \src "ls180.v:4701.1-4773.4"
+ attribute \src "ls180.v:4697.1-4769.4"
wire $0\main_sdphy_dataw_sink_ready[0:0]
- attribute \src "ls180.v:5208.1-5398.4"
+ attribute \src "ls180.v:5204.1-5394.4"
wire $0\main_sdphy_dataw_sink_valid[0:0]
- attribute \src "ls180.v:4701.1-4773.4"
+ attribute \src "ls180.v:4697.1-4769.4"
wire $0\main_sdphy_dataw_start[0:0]
- attribute \src "ls180.v:4701.1-4773.4"
+ attribute \src "ls180.v:4697.1-4769.4"
wire $0\main_sdphy_dataw_stop[0:0]
- attribute \src "ls180.v:4673.1-4700.4"
+ attribute \src "ls180.v:4669.1-4696.4"
wire $0\main_sdphy_dataw_valid[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 8 $0\main_sdphy_init_count[7:0]
- attribute \src "ls180.v:4402.1-4435.4"
+ attribute \src "ls180.v:4398.1-4431.4"
wire width 8 $0\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0]
- attribute \src "ls180.v:4402.1-4435.4"
+ attribute \src "ls180.v:4398.1-4431.4"
wire $0\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0]
- attribute \src "ls180.v:1109.5-1109.40"
+ attribute \src "ls180.v:1105.5-1105.40"
wire $0\main_sdphy_init_initialize_w[0:0]
- attribute \src "ls180.v:4402.1-4435.4"
+ attribute \src "ls180.v:4398.1-4431.4"
wire $0\main_sdphy_init_pads_out_payload_clk[0:0]
- attribute \src "ls180.v:4402.1-4435.4"
+ attribute \src "ls180.v:4398.1-4431.4"
wire $0\main_sdphy_init_pads_out_payload_cmd_o[0:0]
- attribute \src "ls180.v:4402.1-4435.4"
+ attribute \src "ls180.v:4398.1-4431.4"
wire $0\main_sdphy_init_pads_out_payload_cmd_oe[0:0]
- attribute \src "ls180.v:4402.1-4435.4"
+ attribute \src "ls180.v:4398.1-4431.4"
wire width 4 $0\main_sdphy_init_pads_out_payload_data_o[3:0]
- attribute \src "ls180.v:4402.1-4435.4"
+ attribute \src "ls180.v:4398.1-4431.4"
wire $0\main_sdphy_init_pads_out_payload_data_oe[0:0]
- attribute \src "ls180.v:7359.1-7429.4"
+ attribute \src "ls180.v:7355.1-7425.4"
wire $0\main_sdphy_sdpads_cmd_i[0:0]
- attribute \src "ls180.v:7359.1-7429.4"
+ attribute \src "ls180.v:7355.1-7425.4"
wire width 4 $0\main_sdphy_sdpads_data_i[3:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\main_sdram_address_re[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 13 $0\main_sdram_address_storage[12:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\main_sdram_baddress_re[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 2 $0\main_sdram_baddress_storage[1:0]
- attribute \src "ls180.v:3188.1-3195.4"
+ attribute \src "ls180.v:3184.1-3191.4"
wire $0\main_sdram_bankmachine0_auto_precharge[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 3 $0\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 4 $0\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 3 $0\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0]
- attribute \src "ls180.v:449.5-449.64"
+ attribute \src "ls180.v:445.5-445.64"
wire $0\main_sdram_bankmachine0_cmd_buffer_lookahead_replace[0:0]
- attribute \src "ls180.v:432.5-432.67"
+ attribute \src "ls180.v:428.5-428.67"
wire $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first[0:0]
- attribute \src "ls180.v:433.5-433.66"
+ attribute \src "ls180.v:429.5-429.66"
wire $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last[0:0]
- attribute \src "ls180.v:3210.1-3217.4"
+ attribute \src "ls180.v:3206.1-3213.4"
wire width 3 $0\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\main_sdram_bankmachine0_cmd_buffer_source_first[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\main_sdram_bankmachine0_cmd_buffer_source_last[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 22 $0\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0]
- attribute \src "ls180.v:3177.1-3184.4"
+ attribute \src "ls180.v:3173.1-3180.4"
wire width 13 $0\main_sdram_bankmachine0_cmd_payload_a[12:0]
- attribute \src "ls180.v:3226.1-3319.4"
+ attribute \src "ls180.v:3222.1-3315.4"
wire $0\main_sdram_bankmachine0_cmd_payload_cas[0:0]
- attribute \src "ls180.v:3226.1-3319.4"
+ attribute \src "ls180.v:3222.1-3315.4"
wire $0\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0]
- attribute \src "ls180.v:3226.1-3319.4"
+ attribute \src "ls180.v:3222.1-3315.4"
wire $0\main_sdram_bankmachine0_cmd_payload_is_read[0:0]
- attribute \src "ls180.v:3226.1-3319.4"
+ attribute \src "ls180.v:3222.1-3315.4"
wire $0\main_sdram_bankmachine0_cmd_payload_is_write[0:0]
- attribute \src "ls180.v:3226.1-3319.4"
+ attribute \src "ls180.v:3222.1-3315.4"
wire $0\main_sdram_bankmachine0_cmd_payload_ras[0:0]
- attribute \src "ls180.v:3226.1-3319.4"
+ attribute \src "ls180.v:3222.1-3315.4"
wire $0\main_sdram_bankmachine0_cmd_payload_we[0:0]
- attribute \src "ls180.v:3875.1-3883.4"
+ attribute \src "ls180.v:3871.1-3879.4"
wire $0\main_sdram_bankmachine0_cmd_ready[0:0]
- attribute \src "ls180.v:3226.1-3319.4"
+ attribute \src "ls180.v:3222.1-3315.4"
wire $0\main_sdram_bankmachine0_cmd_valid[0:0]
- attribute \src "ls180.v:3226.1-3319.4"
+ attribute \src "ls180.v:3222.1-3315.4"
wire $0\main_sdram_bankmachine0_refresh_gnt[0:0]
- attribute \src "ls180.v:3226.1-3319.4"
+ attribute \src "ls180.v:3222.1-3315.4"
wire $0\main_sdram_bankmachine0_req_rdata_valid[0:0]
- attribute \src "ls180.v:3226.1-3319.4"
+ attribute \src "ls180.v:3222.1-3315.4"
wire $0\main_sdram_bankmachine0_req_wdata_ready[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 13 $0\main_sdram_bankmachine0_row[12:0]
- attribute \src "ls180.v:3226.1-3319.4"
+ attribute \src "ls180.v:3222.1-3315.4"
wire $0\main_sdram_bankmachine0_row_close[0:0]
- attribute \src "ls180.v:3226.1-3319.4"
+ attribute \src "ls180.v:3222.1-3315.4"
wire $0\main_sdram_bankmachine0_row_col_n_addr_sel[0:0]
- attribute \src "ls180.v:3226.1-3319.4"
+ attribute \src "ls180.v:3222.1-3315.4"
wire $0\main_sdram_bankmachine0_row_open[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\main_sdram_bankmachine0_row_opened[0:0]
- attribute \src "ls180.v:491.32-491.76"
+ attribute \src "ls180.v:487.32-487.76"
wire $0\main_sdram_bankmachine0_trascon_ready[0:0]
- attribute \src "ls180.v:489.32-489.75"
+ attribute \src "ls180.v:485.32-485.75"
wire $0\main_sdram_bankmachine0_trccon_ready[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 3 $0\main_sdram_bankmachine0_twtpcon_count[2:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\main_sdram_bankmachine0_twtpcon_ready[0:0]
- attribute \src "ls180.v:3345.1-3352.4"
+ attribute \src "ls180.v:3341.1-3348.4"
wire $0\main_sdram_bankmachine1_auto_precharge[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 3 $0\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 4 $0\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 3 $0\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0]
- attribute \src "ls180.v:531.5-531.64"
+ attribute \src "ls180.v:527.5-527.64"
wire $0\main_sdram_bankmachine1_cmd_buffer_lookahead_replace[0:0]
- attribute \src "ls180.v:514.5-514.67"
+ attribute \src "ls180.v:510.5-510.67"
wire $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first[0:0]
- attribute \src "ls180.v:515.5-515.66"
+ attribute \src "ls180.v:511.5-511.66"
wire $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last[0:0]
- attribute \src "ls180.v:3367.1-3374.4"
+ attribute \src "ls180.v:3363.1-3370.4"
wire width 3 $0\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\main_sdram_bankmachine1_cmd_buffer_source_first[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\main_sdram_bankmachine1_cmd_buffer_source_last[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 22 $0\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\main_sdram_bankmachine1_cmd_buffer_source_payload_we[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0]
- attribute \src "ls180.v:3334.1-3341.4"
+ attribute \src "ls180.v:3330.1-3337.4"
wire width 13 $0\main_sdram_bankmachine1_cmd_payload_a[12:0]
- attribute \src "ls180.v:3383.1-3476.4"
+ attribute \src "ls180.v:3379.1-3472.4"
wire $0\main_sdram_bankmachine1_cmd_payload_cas[0:0]
- attribute \src "ls180.v:3383.1-3476.4"
+ attribute \src "ls180.v:3379.1-3472.4"
wire $0\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0]
- attribute \src "ls180.v:3383.1-3476.4"
+ attribute \src "ls180.v:3379.1-3472.4"
wire $0\main_sdram_bankmachine1_cmd_payload_is_read[0:0]
- attribute \src "ls180.v:3383.1-3476.4"
+ attribute \src "ls180.v:3379.1-3472.4"
wire $0\main_sdram_bankmachine1_cmd_payload_is_write[0:0]
- attribute \src "ls180.v:3383.1-3476.4"
+ attribute \src "ls180.v:3379.1-3472.4"
wire $0\main_sdram_bankmachine1_cmd_payload_ras[0:0]
- attribute \src "ls180.v:3383.1-3476.4"
+ attribute \src "ls180.v:3379.1-3472.4"
wire $0\main_sdram_bankmachine1_cmd_payload_we[0:0]
- attribute \src "ls180.v:3884.1-3892.4"
+ attribute \src "ls180.v:3880.1-3888.4"
wire $0\main_sdram_bankmachine1_cmd_ready[0:0]
- attribute \src "ls180.v:3383.1-3476.4"
+ attribute \src "ls180.v:3379.1-3472.4"
wire $0\main_sdram_bankmachine1_cmd_valid[0:0]
- attribute \src "ls180.v:3383.1-3476.4"
+ attribute \src "ls180.v:3379.1-3472.4"
wire $0\main_sdram_bankmachine1_refresh_gnt[0:0]
- attribute \src "ls180.v:3383.1-3476.4"
+ attribute \src "ls180.v:3379.1-3472.4"
wire $0\main_sdram_bankmachine1_req_rdata_valid[0:0]
- attribute \src "ls180.v:3383.1-3476.4"
+ attribute \src "ls180.v:3379.1-3472.4"
wire $0\main_sdram_bankmachine1_req_wdata_ready[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 13 $0\main_sdram_bankmachine1_row[12:0]
- attribute \src "ls180.v:3383.1-3476.4"
+ attribute \src "ls180.v:3379.1-3472.4"
wire $0\main_sdram_bankmachine1_row_close[0:0]
- attribute \src "ls180.v:3383.1-3476.4"
+ attribute \src "ls180.v:3379.1-3472.4"
wire $0\main_sdram_bankmachine1_row_col_n_addr_sel[0:0]
- attribute \src "ls180.v:3383.1-3476.4"
+ attribute \src "ls180.v:3379.1-3472.4"
wire $0\main_sdram_bankmachine1_row_open[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\main_sdram_bankmachine1_row_opened[0:0]
- attribute \src "ls180.v:573.32-573.76"
+ attribute \src "ls180.v:569.32-569.76"
wire $0\main_sdram_bankmachine1_trascon_ready[0:0]
- attribute \src "ls180.v:571.32-571.75"
+ attribute \src "ls180.v:567.32-567.75"
wire $0\main_sdram_bankmachine1_trccon_ready[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 3 $0\main_sdram_bankmachine1_twtpcon_count[2:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\main_sdram_bankmachine1_twtpcon_ready[0:0]
- attribute \src "ls180.v:3502.1-3509.4"
+ attribute \src "ls180.v:3498.1-3505.4"
wire $0\main_sdram_bankmachine2_auto_precharge[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 3 $0\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 4 $0\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 3 $0\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0]
- attribute \src "ls180.v:613.5-613.64"
+ attribute \src "ls180.v:609.5-609.64"
wire $0\main_sdram_bankmachine2_cmd_buffer_lookahead_replace[0:0]
- attribute \src "ls180.v:596.5-596.67"
+ attribute \src "ls180.v:592.5-592.67"
wire $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first[0:0]
- attribute \src "ls180.v:597.5-597.66"
+ attribute \src "ls180.v:593.5-593.66"
wire $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last[0:0]
- attribute \src "ls180.v:3524.1-3531.4"
+ attribute \src "ls180.v:3520.1-3527.4"
wire width 3 $0\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\main_sdram_bankmachine2_cmd_buffer_source_first[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\main_sdram_bankmachine2_cmd_buffer_source_last[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 22 $0\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0]
- attribute \src "ls180.v:3491.1-3498.4"
+ attribute \src "ls180.v:3487.1-3494.4"
wire width 13 $0\main_sdram_bankmachine2_cmd_payload_a[12:0]
- attribute \src "ls180.v:3540.1-3633.4"
+ attribute \src "ls180.v:3536.1-3629.4"
wire $0\main_sdram_bankmachine2_cmd_payload_cas[0:0]
- attribute \src "ls180.v:3540.1-3633.4"
+ attribute \src "ls180.v:3536.1-3629.4"
wire $0\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0]
- attribute \src "ls180.v:3540.1-3633.4"
+ attribute \src "ls180.v:3536.1-3629.4"
wire $0\main_sdram_bankmachine2_cmd_payload_is_read[0:0]
- attribute \src "ls180.v:3540.1-3633.4"
+ attribute \src "ls180.v:3536.1-3629.4"
wire $0\main_sdram_bankmachine2_cmd_payload_is_write[0:0]
- attribute \src "ls180.v:3540.1-3633.4"
+ attribute \src "ls180.v:3536.1-3629.4"
wire $0\main_sdram_bankmachine2_cmd_payload_ras[0:0]
- attribute \src "ls180.v:3540.1-3633.4"
+ attribute \src "ls180.v:3536.1-3629.4"
wire $0\main_sdram_bankmachine2_cmd_payload_we[0:0]
- attribute \src "ls180.v:3893.1-3901.4"
+ attribute \src "ls180.v:3889.1-3897.4"
wire $0\main_sdram_bankmachine2_cmd_ready[0:0]
- attribute \src "ls180.v:3540.1-3633.4"
+ attribute \src "ls180.v:3536.1-3629.4"
wire $0\main_sdram_bankmachine2_cmd_valid[0:0]
- attribute \src "ls180.v:3540.1-3633.4"
+ attribute \src "ls180.v:3536.1-3629.4"
wire $0\main_sdram_bankmachine2_refresh_gnt[0:0]
- attribute \src "ls180.v:3540.1-3633.4"
+ attribute \src "ls180.v:3536.1-3629.4"
wire $0\main_sdram_bankmachine2_req_rdata_valid[0:0]
- attribute \src "ls180.v:3540.1-3633.4"
+ attribute \src "ls180.v:3536.1-3629.4"
wire $0\main_sdram_bankmachine2_req_wdata_ready[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 13 $0\main_sdram_bankmachine2_row[12:0]
- attribute \src "ls180.v:3540.1-3633.4"
+ attribute \src "ls180.v:3536.1-3629.4"
wire $0\main_sdram_bankmachine2_row_close[0:0]
- attribute \src "ls180.v:3540.1-3633.4"
+ attribute \src "ls180.v:3536.1-3629.4"
wire $0\main_sdram_bankmachine2_row_col_n_addr_sel[0:0]
- attribute \src "ls180.v:3540.1-3633.4"
+ attribute \src "ls180.v:3536.1-3629.4"
wire $0\main_sdram_bankmachine2_row_open[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\main_sdram_bankmachine2_row_opened[0:0]
- attribute \src "ls180.v:655.32-655.76"
+ attribute \src "ls180.v:651.32-651.76"
wire $0\main_sdram_bankmachine2_trascon_ready[0:0]
- attribute \src "ls180.v:653.32-653.75"
+ attribute \src "ls180.v:649.32-649.75"
wire $0\main_sdram_bankmachine2_trccon_ready[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 3 $0\main_sdram_bankmachine2_twtpcon_count[2:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\main_sdram_bankmachine2_twtpcon_ready[0:0]
- attribute \src "ls180.v:3659.1-3666.4"
+ attribute \src "ls180.v:3655.1-3662.4"
wire $0\main_sdram_bankmachine3_auto_precharge[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 3 $0\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 4 $0\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 3 $0\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0]
- attribute \src "ls180.v:695.5-695.64"
+ attribute \src "ls180.v:691.5-691.64"
wire $0\main_sdram_bankmachine3_cmd_buffer_lookahead_replace[0:0]
- attribute \src "ls180.v:678.5-678.67"
+ attribute \src "ls180.v:674.5-674.67"
wire $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first[0:0]
- attribute \src "ls180.v:679.5-679.66"
+ attribute \src "ls180.v:675.5-675.66"
wire $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last[0:0]
- attribute \src "ls180.v:3681.1-3688.4"
+ attribute \src "ls180.v:3677.1-3684.4"
wire width 3 $0\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\main_sdram_bankmachine3_cmd_buffer_source_first[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\main_sdram_bankmachine3_cmd_buffer_source_last[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 22 $0\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0]
- attribute \src "ls180.v:3648.1-3655.4"
+ attribute \src "ls180.v:3644.1-3651.4"
wire width 13 $0\main_sdram_bankmachine3_cmd_payload_a[12:0]
- attribute \src "ls180.v:3697.1-3790.4"
+ attribute \src "ls180.v:3693.1-3786.4"
wire $0\main_sdram_bankmachine3_cmd_payload_cas[0:0]
- attribute \src "ls180.v:3697.1-3790.4"
+ attribute \src "ls180.v:3693.1-3786.4"
wire $0\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0]
- attribute \src "ls180.v:3697.1-3790.4"
+ attribute \src "ls180.v:3693.1-3786.4"
wire $0\main_sdram_bankmachine3_cmd_payload_is_read[0:0]
- attribute \src "ls180.v:3697.1-3790.4"
+ attribute \src "ls180.v:3693.1-3786.4"
wire $0\main_sdram_bankmachine3_cmd_payload_is_write[0:0]
- attribute \src "ls180.v:3697.1-3790.4"
+ attribute \src "ls180.v:3693.1-3786.4"
wire $0\main_sdram_bankmachine3_cmd_payload_ras[0:0]
- attribute \src "ls180.v:3697.1-3790.4"
+ attribute \src "ls180.v:3693.1-3786.4"
wire $0\main_sdram_bankmachine3_cmd_payload_we[0:0]
- attribute \src "ls180.v:3902.1-3910.4"
+ attribute \src "ls180.v:3898.1-3906.4"
wire $0\main_sdram_bankmachine3_cmd_ready[0:0]
- attribute \src "ls180.v:3697.1-3790.4"
+ attribute \src "ls180.v:3693.1-3786.4"
wire $0\main_sdram_bankmachine3_cmd_valid[0:0]
- attribute \src "ls180.v:3697.1-3790.4"
+ attribute \src "ls180.v:3693.1-3786.4"
wire $0\main_sdram_bankmachine3_refresh_gnt[0:0]
- attribute \src "ls180.v:3697.1-3790.4"
+ attribute \src "ls180.v:3693.1-3786.4"
wire $0\main_sdram_bankmachine3_req_rdata_valid[0:0]
- attribute \src "ls180.v:3697.1-3790.4"
+ attribute \src "ls180.v:3693.1-3786.4"
wire $0\main_sdram_bankmachine3_req_wdata_ready[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 13 $0\main_sdram_bankmachine3_row[12:0]
- attribute \src "ls180.v:3697.1-3790.4"
+ attribute \src "ls180.v:3693.1-3786.4"
wire $0\main_sdram_bankmachine3_row_close[0:0]
- attribute \src "ls180.v:3697.1-3790.4"
+ attribute \src "ls180.v:3693.1-3786.4"
wire $0\main_sdram_bankmachine3_row_col_n_addr_sel[0:0]
- attribute \src "ls180.v:3697.1-3790.4"
+ attribute \src "ls180.v:3693.1-3786.4"
wire $0\main_sdram_bankmachine3_row_open[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\main_sdram_bankmachine3_row_opened[0:0]
- attribute \src "ls180.v:737.32-737.76"
+ attribute \src "ls180.v:733.32-733.76"
wire $0\main_sdram_bankmachine3_trascon_ready[0:0]
- attribute \src "ls180.v:735.32-735.75"
+ attribute \src "ls180.v:731.32-731.75"
wire $0\main_sdram_bankmachine3_trccon_ready[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 3 $0\main_sdram_bankmachine3_twtpcon_count[2:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\main_sdram_bankmachine3_twtpcon_ready[0:0]
- attribute \src "ls180.v:3824.1-3829.4"
+ attribute \src "ls180.v:3820.1-3825.4"
wire $0\main_sdram_choose_cmd_cmd_payload_cas[0:0]
- attribute \src "ls180.v:3830.1-3835.4"
+ attribute \src "ls180.v:3826.1-3831.4"
wire $0\main_sdram_choose_cmd_cmd_payload_ras[0:0]
- attribute \src "ls180.v:3836.1-3841.4"
+ attribute \src "ls180.v:3832.1-3837.4"
wire $0\main_sdram_choose_cmd_cmd_payload_we[0:0]
- attribute \src "ls180.v:745.5-745.43"
+ attribute \src "ls180.v:741.5-741.43"
wire $0\main_sdram_choose_cmd_cmd_ready[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 2 $0\main_sdram_choose_cmd_grant[1:0]
- attribute \src "ls180.v:3810.1-3816.4"
+ attribute \src "ls180.v:3806.1-3812.4"
wire width 4 $0\main_sdram_choose_cmd_valids[3:0]
- attribute \src "ls180.v:743.5-743.48"
+ attribute \src "ls180.v:739.5-739.48"
wire $0\main_sdram_choose_cmd_want_activates[0:0]
- attribute \src "ls180.v:742.5-742.43"
+ attribute \src "ls180.v:738.5-738.43"
wire $0\main_sdram_choose_cmd_want_cmds[0:0]
- attribute \src "ls180.v:740.5-740.44"
+ attribute \src "ls180.v:736.5-736.44"
wire $0\main_sdram_choose_cmd_want_reads[0:0]
- attribute \src "ls180.v:741.5-741.45"
+ attribute \src "ls180.v:737.5-737.45"
wire $0\main_sdram_choose_cmd_want_writes[0:0]
- attribute \src "ls180.v:3857.1-3862.4"
+ attribute \src "ls180.v:3853.1-3858.4"
wire $0\main_sdram_choose_req_cmd_payload_cas[0:0]
- attribute \src "ls180.v:3863.1-3868.4"
+ attribute \src "ls180.v:3859.1-3864.4"
wire $0\main_sdram_choose_req_cmd_payload_ras[0:0]
- attribute \src "ls180.v:3869.1-3874.4"
+ attribute \src "ls180.v:3865.1-3870.4"
wire $0\main_sdram_choose_req_cmd_payload_we[0:0]
- attribute \src "ls180.v:3915.1-3987.4"
+ attribute \src "ls180.v:3911.1-3983.4"
wire $0\main_sdram_choose_req_cmd_ready[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 2 $0\main_sdram_choose_req_grant[1:0]
- attribute \src "ls180.v:3843.1-3849.4"
+ attribute \src "ls180.v:3839.1-3845.4"
wire width 4 $0\main_sdram_choose_req_valids[3:0]
- attribute \src "ls180.v:3915.1-3987.4"
+ attribute \src "ls180.v:3911.1-3983.4"
wire $0\main_sdram_choose_req_want_activates[0:0]
- attribute \src "ls180.v:3915.1-3987.4"
+ attribute \src "ls180.v:3911.1-3983.4"
wire $0\main_sdram_choose_req_want_reads[0:0]
- attribute \src "ls180.v:3915.1-3987.4"
+ attribute \src "ls180.v:3911.1-3983.4"
wire $0\main_sdram_choose_req_want_writes[0:0]
- attribute \src "ls180.v:3132.1-3162.4"
+ attribute \src "ls180.v:3128.1-3158.4"
wire $0\main_sdram_cmd_last[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 13 $0\main_sdram_cmd_payload_a[12:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 2 $0\main_sdram_cmd_payload_ba[1:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\main_sdram_cmd_payload_cas[0:0]
- attribute \src "ls180.v:393.5-393.42"
+ attribute \src "ls180.v:389.5-389.42"
wire $0\main_sdram_cmd_payload_is_read[0:0]
- attribute \src "ls180.v:394.5-394.43"
+ attribute \src "ls180.v:390.5-390.43"
wire $0\main_sdram_cmd_payload_is_write[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\main_sdram_cmd_payload_ras[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\main_sdram_cmd_payload_we[0:0]
- attribute \src "ls180.v:3915.1-3987.4"
+ attribute \src "ls180.v:3911.1-3983.4"
wire $0\main_sdram_cmd_ready[0:0]
- attribute \src "ls180.v:3132.1-3162.4"
+ attribute \src "ls180.v:3128.1-3158.4"
wire $0\main_sdram_cmd_valid[0:0]
- attribute \src "ls180.v:329.5-329.38"
+ attribute \src "ls180.v:325.5-325.38"
wire $0\main_sdram_command_issue_w[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\main_sdram_command_re[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 6 $0\main_sdram_command_storage[5:0]
- attribute \src "ls180.v:378.5-378.35"
+ attribute \src "ls180.v:374.5-374.35"
wire $0\main_sdram_dfi_p0_act_n[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 13 $0\main_sdram_dfi_p0_address[12:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 2 $0\main_sdram_dfi_p0_bank[1:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\main_sdram_dfi_p0_cas_n[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\main_sdram_dfi_p0_cs_n[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\main_sdram_dfi_p0_ras_n[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\main_sdram_dfi_p0_rddata_en[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\main_sdram_dfi_p0_we_n[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\main_sdram_dfi_p0_wrdata_en[0:0]
- attribute \src "ls180.v:3915.1-3987.4"
+ attribute \src "ls180.v:3911.1-3983.4"
wire $0\main_sdram_en0[0:0]
- attribute \src "ls180.v:3915.1-3987.4"
+ attribute \src "ls180.v:3911.1-3983.4"
wire $0\main_sdram_en1[0:0]
- attribute \src "ls180.v:4011.1-4024.4"
+ attribute \src "ls180.v:4007.1-4020.4"
wire width 16 $0\main_sdram_interface_wdata[15:0]
- attribute \src "ls180.v:4011.1-4024.4"
+ attribute \src "ls180.v:4007.1-4020.4"
wire width 2 $0\main_sdram_interface_wdata_we[1:0]
- attribute \src "ls180.v:279.5-279.36"
+ attribute \src "ls180.v:275.5-275.36"
wire $0\main_sdram_inti_p0_act_n[0:0]
- attribute \src "ls180.v:3073.1-3089.4"
+ attribute \src "ls180.v:3069.1-3085.4"
wire $0\main_sdram_inti_p0_cas_n[0:0]
- attribute \src "ls180.v:3073.1-3089.4"
+ attribute \src "ls180.v:3069.1-3085.4"
wire $0\main_sdram_inti_p0_cs_n[0:0]
- attribute \src "ls180.v:3073.1-3089.4"
+ attribute \src "ls180.v:3069.1-3085.4"
wire $0\main_sdram_inti_p0_ras_n[0:0]
- attribute \src "ls180.v:3015.1-3069.4"
+ attribute \src "ls180.v:3011.1-3065.4"
wire width 16 $0\main_sdram_inti_p0_rddata[15:0]
- attribute \src "ls180.v:3015.1-3069.4"
+ attribute \src "ls180.v:3011.1-3065.4"
wire $0\main_sdram_inti_p0_rddata_valid[0:0]
- attribute \src "ls180.v:3073.1-3089.4"
+ attribute \src "ls180.v:3069.1-3085.4"
wire $0\main_sdram_inti_p0_we_n[0:0]
- attribute \src "ls180.v:3015.1-3069.4"
+ attribute \src "ls180.v:3011.1-3065.4"
wire $0\main_sdram_master_p0_act_n[0:0]
- attribute \src "ls180.v:3015.1-3069.4"
+ attribute \src "ls180.v:3011.1-3065.4"
wire width 13 $0\main_sdram_master_p0_address[12:0]
- attribute \src "ls180.v:3015.1-3069.4"
+ attribute \src "ls180.v:3011.1-3065.4"
wire width 2 $0\main_sdram_master_p0_bank[1:0]
- attribute \src "ls180.v:3015.1-3069.4"
+ attribute \src "ls180.v:3011.1-3065.4"
wire $0\main_sdram_master_p0_cas_n[0:0]
- attribute \src "ls180.v:3015.1-3069.4"
+ attribute \src "ls180.v:3011.1-3065.4"
wire $0\main_sdram_master_p0_cke[0:0]
- attribute \src "ls180.v:3015.1-3069.4"
+ attribute \src "ls180.v:3011.1-3065.4"
wire $0\main_sdram_master_p0_cs_n[0:0]
- attribute \src "ls180.v:3015.1-3069.4"
+ attribute \src "ls180.v:3011.1-3065.4"
wire $0\main_sdram_master_p0_odt[0:0]
- attribute \src "ls180.v:3015.1-3069.4"
+ attribute \src "ls180.v:3011.1-3065.4"
wire $0\main_sdram_master_p0_ras_n[0:0]
- attribute \src "ls180.v:3015.1-3069.4"
+ attribute \src "ls180.v:3011.1-3065.4"
wire $0\main_sdram_master_p0_rddata_en[0:0]
- attribute \src "ls180.v:3015.1-3069.4"
+ attribute \src "ls180.v:3011.1-3065.4"
wire $0\main_sdram_master_p0_reset_n[0:0]
- attribute \src "ls180.v:3015.1-3069.4"
+ attribute \src "ls180.v:3011.1-3065.4"
wire $0\main_sdram_master_p0_we_n[0:0]
- attribute \src "ls180.v:3015.1-3069.4"
+ attribute \src "ls180.v:3011.1-3065.4"
wire width 16 $0\main_sdram_master_p0_wrdata[15:0]
- attribute \src "ls180.v:3015.1-3069.4"
+ attribute \src "ls180.v:3011.1-3065.4"
wire $0\main_sdram_master_p0_wrdata_en[0:0]
- attribute \src "ls180.v:3015.1-3069.4"
+ attribute \src "ls180.v:3011.1-3065.4"
wire width 2 $0\main_sdram_master_p0_wrdata_mask[1:0]
- attribute \src "ls180.v:776.12-776.36"
+ attribute \src "ls180.v:772.12-772.36"
wire width 13 $0\main_sdram_nop_a[12:0]
- attribute \src "ls180.v:777.11-777.35"
+ attribute \src "ls180.v:773.11-773.35"
wire width 2 $0\main_sdram_nop_ba[1:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\main_sdram_postponer_count[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\main_sdram_postponer_req_o[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\main_sdram_re[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\main_sdram_sequencer_count[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 4 $0\main_sdram_sequencer_counter[3:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\main_sdram_sequencer_done1[0:0]
- attribute \src "ls180.v:3132.1-3162.4"
+ attribute \src "ls180.v:3128.1-3158.4"
wire $0\main_sdram_sequencer_start0[0:0]
- attribute \src "ls180.v:3015.1-3069.4"
+ attribute \src "ls180.v:3011.1-3065.4"
wire width 16 $0\main_sdram_slave_p0_rddata[15:0]
- attribute \src "ls180.v:3015.1-3069.4"
+ attribute \src "ls180.v:3011.1-3065.4"
wire $0\main_sdram_slave_p0_rddata_valid[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 16 $0\main_sdram_status[15:0]
- attribute \src "ls180.v:779.5-779.31"
+ attribute \src "ls180.v:775.5-775.31"
wire $0\main_sdram_steerer0[0:0]
- attribute \src "ls180.v:780.5-780.31"
+ attribute \src "ls180.v:776.5-776.31"
wire $0\main_sdram_steerer1[0:0]
- attribute \src "ls180.v:3915.1-3987.4"
+ attribute \src "ls180.v:3911.1-3983.4"
wire width 2 $0\main_sdram_steerer_sel[1:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 4 $0\main_sdram_storage[3:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\main_sdram_tccdcon_count[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\main_sdram_tccdcon_ready[0:0]
- attribute \src "ls180.v:784.32-784.63"
+ attribute \src "ls180.v:780.32-780.63"
wire $0\main_sdram_tfawcon_ready[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 5 $0\main_sdram_time0[4:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 4 $0\main_sdram_time1[3:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 10 $0\main_sdram_timer_count1[9:0]
- attribute \src "ls180.v:782.32-782.63"
+ attribute \src "ls180.v:778.32-778.63"
wire $0\main_sdram_trrdcon_ready[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 3 $0\main_sdram_twtrcon_count[2:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\main_sdram_twtrcon_ready[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\main_sdram_wrdata_re[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 16 $0\main_sdram_wrdata_storage[15:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 16 $0\main_spimaster11_storage[15:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\main_spimaster12_re[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 8 $0\main_spimaster16_storage[7:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\main_spimaster17_re[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\main_spimaster1_re[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 16 $0\main_spimaster1_storage[15:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\main_spimaster21_storage[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\main_spimaster22_re[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\main_spimaster23_storage[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\main_spimaster24_re[0:0]
- attribute \src "ls180.v:4233.1-4281.4"
+ attribute \src "ls180.v:4229.1-4277.4"
wire $0\main_spimaster25_clk_enable[0:0]
- attribute \src "ls180.v:4233.1-4281.4"
+ attribute \src "ls180.v:4229.1-4277.4"
wire $0\main_spimaster26_cs_enable[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 3 $0\main_spimaster27_count[2:0]
- attribute \src "ls180.v:4233.1-4281.4"
+ attribute \src "ls180.v:4229.1-4277.4"
wire width 3 $0\main_spimaster27_count_spimaster0_next_value[2:0]
- attribute \src "ls180.v:4233.1-4281.4"
+ attribute \src "ls180.v:4229.1-4277.4"
wire $0\main_spimaster27_count_spimaster0_next_value_ce[0:0]
- attribute \src "ls180.v:4233.1-4281.4"
+ attribute \src "ls180.v:4229.1-4277.4"
wire $0\main_spimaster28_mosi_latch[0:0]
- attribute \src "ls180.v:4233.1-4281.4"
+ attribute \src "ls180.v:4229.1-4277.4"
wire $0\main_spimaster29_miso_latch[0:0]
- attribute \src "ls180.v:4233.1-4281.4"
+ attribute \src "ls180.v:4229.1-4277.4"
wire $0\main_spimaster2_done[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 16 $0\main_spimaster30_clk_divider[15:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 8 $0\main_spimaster33_mosi_data[7:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 3 $0\main_spimaster34_mosi_sel[2:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 8 $0\main_spimaster35_miso_data[7:0]
- attribute \src "ls180.v:4233.1-4281.4"
+ attribute \src "ls180.v:4229.1-4277.4"
wire $0\main_spimaster3_irq[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 8 $0\main_spimaster5_miso[7:0]
- attribute \src "ls180.v:1000.12-1000.47"
+ attribute \src "ls180.v:996.12-996.47"
wire width 16 $0\main_spimaster8_clk_divider[15:0]
- attribute \src "ls180.v:6285.1-6290.4"
+ attribute \src "ls180.v:6281.1-6286.4"
wire $0\main_spimaster9_start[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 16 $0\main_spisdcard_clk_divider1[15:0]
- attribute \src "ls180.v:4292.1-4340.4"
+ attribute \src "ls180.v:4288.1-4336.4"
wire $0\main_spisdcard_clk_enable[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\main_spisdcard_control_re[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 16 $0\main_spisdcard_control_storage[15:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 3 $0\main_spisdcard_count[2:0]
- attribute \src "ls180.v:4292.1-4340.4"
+ attribute \src "ls180.v:4288.1-4336.4"
wire width 3 $0\main_spisdcard_count_spimaster1_next_value[2:0]
- attribute \src "ls180.v:4292.1-4340.4"
+ attribute \src "ls180.v:4288.1-4336.4"
wire $0\main_spisdcard_count_spimaster1_next_value_ce[0:0]
- attribute \src "ls180.v:4292.1-4340.4"
+ attribute \src "ls180.v:4288.1-4336.4"
wire $0\main_spisdcard_cs_enable[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\main_spisdcard_cs_re[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\main_spisdcard_cs_storage[0:0]
- attribute \src "ls180.v:4292.1-4340.4"
+ attribute \src "ls180.v:4288.1-4336.4"
wire $0\main_spisdcard_done0[0:0]
- attribute \src "ls180.v:4292.1-4340.4"
+ attribute \src "ls180.v:4288.1-4336.4"
wire $0\main_spisdcard_irq[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\main_spisdcard_loopback_re[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\main_spisdcard_loopback_storage[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 8 $0\main_spisdcard_miso[7:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 8 $0\main_spisdcard_miso_data[7:0]
- attribute \src "ls180.v:4292.1-4340.4"
+ attribute \src "ls180.v:4288.1-4336.4"
wire $0\main_spisdcard_miso_latch[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 8 $0\main_spisdcard_mosi_data[7:0]
- attribute \src "ls180.v:4292.1-4340.4"
+ attribute \src "ls180.v:4288.1-4336.4"
wire $0\main_spisdcard_mosi_latch[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\main_spisdcard_mosi_re[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 3 $0\main_spisdcard_mosi_sel[2:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 8 $0\main_spisdcard_mosi_storage[7:0]
- attribute \src "ls180.v:6331.1-6336.4"
+ attribute \src "ls180.v:6327.1-6332.4"
wire $0\main_spisdcard_start1[0:0]
- attribute \src "ls180.v:4151.1-4155.4"
+ attribute \src "ls180.v:4147.1-4151.4"
wire width 2 $0\main_uart_eventmanager_pending_w[1:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\main_uart_eventmanager_re[0:0]
- attribute \src "ls180.v:4140.1-4144.4"
+ attribute \src "ls180.v:4136.1-4140.4"
wire width 2 $0\main_uart_eventmanager_status_w[1:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 2 $0\main_uart_eventmanager_storage[1:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 32 $0\main_uart_phy_phase_accumulator_rx[31:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 32 $0\main_uart_phy_phase_accumulator_tx[31:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\main_uart_phy_re[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 4 $0\main_uart_phy_rx_bitcount[3:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\main_uart_phy_rx_busy[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\main_uart_phy_rx_r[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 8 $0\main_uart_phy_rx_reg[7:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\main_uart_phy_sink_ready[0:0]
- attribute \src "ls180.v:855.5-855.38"
+ attribute \src "ls180.v:851.5-851.38"
wire $0\main_uart_phy_source_first[0:0]
- attribute \src "ls180.v:856.5-856.37"
+ attribute \src "ls180.v:852.5-852.37"
wire $0\main_uart_phy_source_last[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 8 $0\main_uart_phy_source_payload_data[7:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\main_uart_phy_source_valid[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 32 $0\main_uart_phy_storage[31:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 4 $0\main_uart_phy_tx_bitcount[3:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\main_uart_phy_tx_busy[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 8 $0\main_uart_phy_tx_reg[7:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\main_uart_phy_uart_clk_rxen[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\main_uart_phy_uart_clk_txen[0:0]
- attribute \src "ls180.v:982.5-982.27"
+ attribute \src "ls180.v:978.5-978.27"
wire $0\main_uart_reset[0:0]
- attribute \src "ls180.v:4145.1-4150.4"
+ attribute \src "ls180.v:4141.1-4146.4"
wire $0\main_uart_rx_clear[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 4 $0\main_uart_rx_fifo_consume[3:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 5 $0\main_uart_rx_fifo_level0[4:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 4 $0\main_uart_rx_fifo_produce[3:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\main_uart_rx_fifo_readable[0:0]
- attribute \src "ls180.v:964.5-964.37"
+ attribute \src "ls180.v:960.5-960.37"
wire $0\main_uart_rx_fifo_replace[0:0]
- attribute \src "ls180.v:4203.1-4210.4"
+ attribute \src "ls180.v:4199.1-4206.4"
wire width 4 $0\main_uart_rx_fifo_wrport_adr[3:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\main_uart_rx_old_trigger[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\main_uart_rx_pending[0:0]
- attribute \src "ls180.v:4134.1-4139.4"
+ attribute \src "ls180.v:4130.1-4135.4"
wire $0\main_uart_tx_clear[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 4 $0\main_uart_tx_fifo_consume[3:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 5 $0\main_uart_tx_fifo_level0[4:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 4 $0\main_uart_tx_fifo_produce[3:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\main_uart_tx_fifo_readable[0:0]
- attribute \src "ls180.v:927.5-927.37"
+ attribute \src "ls180.v:923.5-923.37"
wire $0\main_uart_tx_fifo_replace[0:0]
- attribute \src "ls180.v:910.5-910.40"
+ attribute \src "ls180.v:906.5-906.40"
wire $0\main_uart_tx_fifo_sink_first[0:0]
- attribute \src "ls180.v:911.5-911.39"
+ attribute \src "ls180.v:907.5-907.39"
wire $0\main_uart_tx_fifo_sink_last[0:0]
- attribute \src "ls180.v:4173.1-4180.4"
+ attribute \src "ls180.v:4169.1-4176.4"
wire width 4 $0\main_uart_tx_fifo_wrport_adr[3:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\main_uart_tx_old_trigger[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\main_uart_tx_pending[0:0]
- attribute \src "ls180.v:4043.1-4089.4"
+ attribute \src "ls180.v:4039.1-4085.4"
wire $0\main_wb_sdram_ack[0:0]
- attribute \src "ls180.v:823.5-823.29"
+ attribute \src "ls180.v:819.5-819.29"
wire $0\main_wb_sdram_err[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\main_wdata_consumed[0:0]
- attribute \src "ls180.v:10047.1-10057.4"
+ attribute \src "ls180.v:10043.1-10053.4"
wire width 7 $0\memadr[6:0]
- attribute \src "ls180.v:10067.1-10071.4"
+ attribute \src "ls180.v:10063.1-10067.4"
wire width 25 $0\memdat[24:0]
- attribute \src "ls180.v:10081.1-10085.4"
+ attribute \src "ls180.v:10077.1-10081.4"
wire width 25 $0\memdat_1[24:0]
- attribute \src "ls180.v:10095.1-10099.4"
+ attribute \src "ls180.v:10091.1-10095.4"
wire width 25 $0\memdat_2[24:0]
- attribute \src "ls180.v:10109.1-10113.4"
+ attribute \src "ls180.v:10105.1-10109.4"
wire width 25 $0\memdat_3[24:0]
- attribute \src "ls180.v:10124.1-10128.4"
+ attribute \src "ls180.v:10120.1-10124.4"
wire width 10 $0\memdat_4[9:0]
- attribute \src "ls180.v:10130.1-10133.4"
+ attribute \src "ls180.v:10126.1-10129.4"
wire width 10 $0\memdat_5[9:0]
- attribute \src "ls180.v:10141.1-10145.4"
+ attribute \src "ls180.v:10137.1-10141.4"
wire width 10 $0\memdat_6[9:0]
- attribute \src "ls180.v:10147.1-10150.4"
+ attribute \src "ls180.v:10143.1-10146.4"
wire width 10 $0\memdat_7[9:0]
- attribute \src "ls180.v:10157.1-10161.4"
+ attribute \src "ls180.v:10153.1-10157.4"
wire width 10 $0\memdat_8[9:0]
- attribute \src "ls180.v:10171.1-10175.4"
+ attribute \src "ls180.v:10167.1-10171.4"
wire width 10 $0\memdat_9[9:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire width 2 $0\pwm[1:0]
- attribute \src "ls180.v:7359.1-7429.4"
+ attribute \src "ls180.v:7355.1-7425.4"
wire $0\sdcard_clk[0:0]
- attribute \src "ls180.v:7359.1-7429.4"
+ attribute \src "ls180.v:7355.1-7425.4"
wire $0\sdcard_cmd_o[0:0]
- attribute \src "ls180.v:7359.1-7429.4"
+ attribute \src "ls180.v:7355.1-7425.4"
wire $0\sdcard_cmd_oe[0:0]
- attribute \src "ls180.v:7359.1-7429.4"
+ attribute \src "ls180.v:7355.1-7425.4"
wire width 4 $0\sdcard_data_o[3:0]
- attribute \src "ls180.v:7359.1-7429.4"
+ attribute \src "ls180.v:7355.1-7425.4"
wire $0\sdcard_data_oe[0:0]
- attribute \src "ls180.v:7359.1-7429.4"
+ attribute \src "ls180.v:7355.1-7425.4"
wire width 13 $0\sdram_a[12:0]
- attribute \src "ls180.v:7359.1-7429.4"
+ attribute \src "ls180.v:7355.1-7425.4"
wire width 2 $0\sdram_ba[1:0]
- attribute \src "ls180.v:7359.1-7429.4"
+ attribute \src "ls180.v:7355.1-7425.4"
wire $0\sdram_cas_n[0:0]
- attribute \src "ls180.v:7359.1-7429.4"
+ attribute \src "ls180.v:7355.1-7425.4"
wire $0\sdram_cke[0:0]
- attribute \src "ls180.v:7359.1-7429.4"
+ attribute \src "ls180.v:7355.1-7425.4"
wire $0\sdram_clock[0:0]
- attribute \src "ls180.v:7359.1-7429.4"
+ attribute \src "ls180.v:7355.1-7425.4"
wire $0\sdram_cs_n[0:0]
- attribute \src "ls180.v:7359.1-7429.4"
+ attribute \src "ls180.v:7355.1-7425.4"
wire width 2 $0\sdram_dm[1:0]
- attribute \src "ls180.v:7359.1-7429.4"
+ attribute \src "ls180.v:7355.1-7425.4"
wire width 16 $0\sdram_dq_o[15:0]
- attribute \src "ls180.v:7359.1-7429.4"
+ attribute \src "ls180.v:7355.1-7425.4"
wire $0\sdram_dq_oe[0:0]
- attribute \src "ls180.v:7359.1-7429.4"
+ attribute \src "ls180.v:7355.1-7425.4"
wire $0\sdram_ras_n[0:0]
- attribute \src "ls180.v:7359.1-7429.4"
+ attribute \src "ls180.v:7355.1-7425.4"
wire $0\sdram_we_n[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\spimaster_clk[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\spimaster_cs_n[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\spimaster_mosi[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\spisdcard_clk[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\spisdcard_cs_n[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\spisdcard_mosi[0:0]
- attribute \src "ls180.v:7431.1-10043.4"
+ attribute \src "ls180.v:7427.1-10039.4"
wire $0\uart_tx[0:0]
- attribute \src "ls180.v:1749.11-1749.49"
+ attribute \src "ls180.v:1745.11-1745.49"
wire width 3 $1\builder_bankmachine0_next_state[2:0]
- attribute \src "ls180.v:1748.11-1748.44"
+ attribute \src "ls180.v:1744.11-1744.44"
wire width 3 $1\builder_bankmachine0_state[2:0]
- attribute \src "ls180.v:1751.11-1751.49"
+ attribute \src "ls180.v:1747.11-1747.49"
wire width 3 $1\builder_bankmachine1_next_state[2:0]
- attribute \src "ls180.v:1750.11-1750.44"
+ attribute \src "ls180.v:1746.11-1746.44"
wire width 3 $1\builder_bankmachine1_state[2:0]
- attribute \src "ls180.v:1753.11-1753.49"
+ attribute \src "ls180.v:1749.11-1749.49"
wire width 3 $1\builder_bankmachine2_next_state[2:0]
- attribute \src "ls180.v:1752.11-1752.44"
+ attribute \src "ls180.v:1748.11-1748.44"
wire width 3 $1\builder_bankmachine2_state[2:0]
- attribute \src "ls180.v:1755.11-1755.49"
+ attribute \src "ls180.v:1751.11-1751.49"
wire width 3 $1\builder_bankmachine3_next_state[2:0]
- attribute \src "ls180.v:1754.11-1754.44"
+ attribute \src "ls180.v:1750.11-1750.44"
wire width 3 $1\builder_bankmachine3_state[2:0]
- attribute \src "ls180.v:2600.5-2600.41"
+ attribute \src "ls180.v:2596.5-2596.41"
wire $1\builder_comb_rhs_array_muxed0[0:0]
- attribute \src "ls180.v:2613.5-2613.42"
+ attribute \src "ls180.v:2609.5-2609.42"
wire $1\builder_comb_rhs_array_muxed10[0:0]
- attribute \src "ls180.v:2614.5-2614.42"
+ attribute \src "ls180.v:2610.5-2610.42"
wire $1\builder_comb_rhs_array_muxed11[0:0]
- attribute \src "ls180.v:2618.12-2618.50"
+ attribute \src "ls180.v:2614.12-2614.50"
wire width 22 $1\builder_comb_rhs_array_muxed12[21:0]
- attribute \src "ls180.v:2619.5-2619.42"
+ attribute \src "ls180.v:2615.5-2615.42"
wire $1\builder_comb_rhs_array_muxed13[0:0]
- attribute \src "ls180.v:2620.5-2620.42"
+ attribute \src "ls180.v:2616.5-2616.42"
wire $1\builder_comb_rhs_array_muxed14[0:0]
- attribute \src "ls180.v:2621.12-2621.50"
+ attribute \src "ls180.v:2617.12-2617.50"
wire width 22 $1\builder_comb_rhs_array_muxed15[21:0]
- attribute \src "ls180.v:2622.5-2622.42"
+ attribute \src "ls180.v:2618.5-2618.42"
wire $1\builder_comb_rhs_array_muxed16[0:0]
- attribute \src "ls180.v:2623.5-2623.42"
+ attribute \src "ls180.v:2619.5-2619.42"
wire $1\builder_comb_rhs_array_muxed17[0:0]
- attribute \src "ls180.v:2624.12-2624.50"
+ attribute \src "ls180.v:2620.12-2620.50"
wire width 22 $1\builder_comb_rhs_array_muxed18[21:0]
- attribute \src "ls180.v:2625.5-2625.42"
+ attribute \src "ls180.v:2621.5-2621.42"
wire $1\builder_comb_rhs_array_muxed19[0:0]
- attribute \src "ls180.v:2601.12-2601.49"
+ attribute \src "ls180.v:2597.12-2597.49"
wire width 13 $1\builder_comb_rhs_array_muxed1[12:0]
- attribute \src "ls180.v:2626.5-2626.42"
+ attribute \src "ls180.v:2622.5-2622.42"
wire $1\builder_comb_rhs_array_muxed20[0:0]
- attribute \src "ls180.v:2627.12-2627.50"
+ attribute \src "ls180.v:2623.12-2623.50"
wire width 22 $1\builder_comb_rhs_array_muxed21[21:0]
- attribute \src "ls180.v:2628.5-2628.42"
+ attribute \src "ls180.v:2624.5-2624.42"
wire $1\builder_comb_rhs_array_muxed22[0:0]
- attribute \src "ls180.v:2629.5-2629.42"
+ attribute \src "ls180.v:2625.5-2625.42"
wire $1\builder_comb_rhs_array_muxed23[0:0]
- attribute \src "ls180.v:2630.12-2630.50"
+ attribute \src "ls180.v:2626.12-2626.50"
wire width 32 $1\builder_comb_rhs_array_muxed24[31:0]
- attribute \src "ls180.v:2631.12-2631.50"
+ attribute \src "ls180.v:2627.12-2627.50"
wire width 32 $1\builder_comb_rhs_array_muxed25[31:0]
- attribute \src "ls180.v:2632.11-2632.48"
+ attribute \src "ls180.v:2628.11-2628.48"
wire width 4 $1\builder_comb_rhs_array_muxed26[3:0]
- attribute \src "ls180.v:2633.5-2633.42"
+ attribute \src "ls180.v:2629.5-2629.42"
wire $1\builder_comb_rhs_array_muxed27[0:0]
- attribute \src "ls180.v:2634.5-2634.42"
+ attribute \src "ls180.v:2630.5-2630.42"
wire $1\builder_comb_rhs_array_muxed28[0:0]
- attribute \src "ls180.v:2635.5-2635.42"
+ attribute \src "ls180.v:2631.5-2631.42"
wire $1\builder_comb_rhs_array_muxed29[0:0]
- attribute \src "ls180.v:2602.11-2602.47"
+ attribute \src "ls180.v:2598.11-2598.47"
wire width 2 $1\builder_comb_rhs_array_muxed2[1:0]
- attribute \src "ls180.v:2636.11-2636.48"
+ attribute \src "ls180.v:2632.11-2632.48"
wire width 3 $1\builder_comb_rhs_array_muxed30[2:0]
- attribute \src "ls180.v:2637.11-2637.48"
+ attribute \src "ls180.v:2633.11-2633.48"
wire width 2 $1\builder_comb_rhs_array_muxed31[1:0]
- attribute \src "ls180.v:2603.5-2603.41"
+ attribute \src "ls180.v:2599.5-2599.41"
wire $1\builder_comb_rhs_array_muxed3[0:0]
- attribute \src "ls180.v:2604.5-2604.41"
+ attribute \src "ls180.v:2600.5-2600.41"
wire $1\builder_comb_rhs_array_muxed4[0:0]
- attribute \src "ls180.v:2605.5-2605.41"
+ attribute \src "ls180.v:2601.5-2601.41"
wire $1\builder_comb_rhs_array_muxed5[0:0]
- attribute \src "ls180.v:2609.5-2609.41"
+ attribute \src "ls180.v:2605.5-2605.41"
wire $1\builder_comb_rhs_array_muxed6[0:0]
- attribute \src "ls180.v:2610.12-2610.49"
+ attribute \src "ls180.v:2606.12-2606.49"
wire width 13 $1\builder_comb_rhs_array_muxed7[12:0]
- attribute \src "ls180.v:2611.11-2611.47"
+ attribute \src "ls180.v:2607.11-2607.47"
wire width 2 $1\builder_comb_rhs_array_muxed8[1:0]
- attribute \src "ls180.v:2612.5-2612.41"
+ attribute \src "ls180.v:2608.5-2608.41"
wire $1\builder_comb_rhs_array_muxed9[0:0]
- attribute \src "ls180.v:2606.5-2606.39"
+ attribute \src "ls180.v:2602.5-2602.39"
wire $1\builder_comb_t_array_muxed0[0:0]
- attribute \src "ls180.v:2607.5-2607.39"
+ attribute \src "ls180.v:2603.5-2603.39"
wire $1\builder_comb_t_array_muxed1[0:0]
- attribute \src "ls180.v:2608.5-2608.39"
+ attribute \src "ls180.v:2604.5-2604.39"
wire $1\builder_comb_t_array_muxed2[0:0]
- attribute \src "ls180.v:2615.5-2615.39"
+ attribute \src "ls180.v:2611.5-2611.39"
wire $1\builder_comb_t_array_muxed3[0:0]
- attribute \src "ls180.v:2616.5-2616.39"
+ attribute \src "ls180.v:2612.5-2612.39"
wire $1\builder_comb_t_array_muxed4[0:0]
- attribute \src "ls180.v:2617.5-2617.39"
+ attribute \src "ls180.v:2613.5-2613.39"
wire $1\builder_comb_t_array_muxed5[0:0]
- attribute \src "ls180.v:1735.5-1735.41"
+ attribute \src "ls180.v:1731.5-1731.41"
wire $1\builder_converter0_next_state[0:0]
- attribute \src "ls180.v:1734.5-1734.36"
+ attribute \src "ls180.v:1730.5-1730.36"
wire $1\builder_converter0_state[0:0]
- attribute \src "ls180.v:1739.5-1739.41"
+ attribute \src "ls180.v:1735.5-1735.41"
wire $1\builder_converter1_next_state[0:0]
- attribute \src "ls180.v:1738.5-1738.36"
+ attribute \src "ls180.v:1734.5-1734.36"
wire $1\builder_converter1_state[0:0]
- attribute \src "ls180.v:1743.5-1743.41"
+ attribute \src "ls180.v:1739.5-1739.41"
wire $1\builder_converter2_next_state[0:0]
- attribute \src "ls180.v:1742.5-1742.36"
+ attribute \src "ls180.v:1738.5-1738.36"
wire $1\builder_converter2_state[0:0]
- attribute \src "ls180.v:1780.5-1780.40"
+ attribute \src "ls180.v:1776.5-1776.40"
wire $1\builder_converter_next_state[0:0]
- attribute \src "ls180.v:1779.5-1779.35"
+ attribute \src "ls180.v:1775.5-1775.35"
wire $1\builder_converter_state[0:0]
- attribute \src "ls180.v:1900.12-1900.39"
+ attribute \src "ls180.v:1896.12-1896.39"
wire width 20 $1\builder_count[19:0]
- attribute \src "ls180.v:1897.5-1897.25"
+ attribute \src "ls180.v:1893.5-1893.25"
wire $1\builder_error[0:0]
- attribute \src "ls180.v:1894.11-1894.31"
+ attribute \src "ls180.v:1890.11-1890.31"
wire width 3 $1\builder_grant[2:0]
- attribute \src "ls180.v:1904.11-1904.51"
+ attribute \src "ls180.v:1900.11-1900.51"
wire width 8 $1\builder_interface0_bank_bus_dat_r[7:0]
- attribute \src "ls180.v:2406.11-2406.52"
+ attribute \src "ls180.v:2402.11-2402.52"
wire width 8 $1\builder_interface10_bank_bus_dat_r[7:0]
- attribute \src "ls180.v:2439.11-2439.52"
+ attribute \src "ls180.v:2435.11-2435.52"
wire width 8 $1\builder_interface11_bank_bus_dat_r[7:0]
- attribute \src "ls180.v:2480.11-2480.52"
+ attribute \src "ls180.v:2476.11-2476.52"
wire width 8 $1\builder_interface12_bank_bus_dat_r[7:0]
- attribute \src "ls180.v:2545.11-2545.52"
+ attribute \src "ls180.v:2541.11-2541.52"
wire width 8 $1\builder_interface13_bank_bus_dat_r[7:0]
- attribute \src "ls180.v:2570.11-2570.52"
+ attribute \src "ls180.v:2566.11-2566.52"
wire width 8 $1\builder_interface14_bank_bus_dat_r[7:0]
- attribute \src "ls180.v:1945.11-1945.51"
+ attribute \src "ls180.v:1941.11-1941.51"
wire width 8 $1\builder_interface1_bank_bus_dat_r[7:0]
- attribute \src "ls180.v:1974.11-1974.51"
+ attribute \src "ls180.v:1970.11-1970.51"
wire width 8 $1\builder_interface2_bank_bus_dat_r[7:0]
- attribute \src "ls180.v:1987.11-1987.51"
+ attribute \src "ls180.v:1983.11-1983.51"
wire width 8 $1\builder_interface3_bank_bus_dat_r[7:0]
- attribute \src "ls180.v:2028.11-2028.51"
+ attribute \src "ls180.v:2024.11-2024.51"
wire width 8 $1\builder_interface4_bank_bus_dat_r[7:0]
- attribute \src "ls180.v:2069.11-2069.51"
+ attribute \src "ls180.v:2065.11-2065.51"
wire width 8 $1\builder_interface5_bank_bus_dat_r[7:0]
- attribute \src "ls180.v:2134.11-2134.51"
+ attribute \src "ls180.v:2130.11-2130.51"
wire width 8 $1\builder_interface6_bank_bus_dat_r[7:0]
- attribute \src "ls180.v:2267.11-2267.51"
+ attribute \src "ls180.v:2263.11-2263.51"
wire width 8 $1\builder_interface7_bank_bus_dat_r[7:0]
- attribute \src "ls180.v:2348.11-2348.51"
+ attribute \src "ls180.v:2344.11-2344.51"
wire width 8 $1\builder_interface8_bank_bus_dat_r[7:0]
- attribute \src "ls180.v:2365.11-2365.51"
+ attribute \src "ls180.v:2361.11-2361.51"
wire width 8 $1\builder_interface9_bank_bus_dat_r[7:0]
- attribute \src "ls180.v:1867.12-1867.43"
+ attribute \src "ls180.v:1863.12-1863.43"
wire width 14 $1\builder_libresocsim_adr[13:0]
- attribute \src "ls180.v:2596.12-2596.55"
+ attribute \src "ls180.v:2592.12-2592.55"
wire width 14 $1\builder_libresocsim_adr_next_value1[13:0]
- attribute \src "ls180.v:2597.5-2597.50"
+ attribute \src "ls180.v:2593.5-2593.50"
wire $1\builder_libresocsim_adr_next_value_ce1[0:0]
- attribute \src "ls180.v:1869.11-1869.43"
+ attribute \src "ls180.v:1865.11-1865.43"
wire width 8 $1\builder_libresocsim_dat_w[7:0]
- attribute \src "ls180.v:2594.11-2594.55"
+ attribute \src "ls180.v:2590.11-2590.55"
wire width 8 $1\builder_libresocsim_dat_w_next_value0[7:0]
- attribute \src "ls180.v:2595.5-2595.52"
+ attribute \src "ls180.v:2591.5-2591.52"
wire $1\builder_libresocsim_dat_w_next_value_ce0[0:0]
- attribute \src "ls180.v:1868.5-1868.34"
+ attribute \src "ls180.v:1864.5-1864.34"
wire $1\builder_libresocsim_we[0:0]
- attribute \src "ls180.v:2598.5-2598.46"
+ attribute \src "ls180.v:2594.5-2594.46"
wire $1\builder_libresocsim_we_next_value2[0:0]
- attribute \src "ls180.v:2599.5-2599.49"
+ attribute \src "ls180.v:2595.5-2595.49"
wire $1\builder_libresocsim_we_next_value_ce2[0:0]
- attribute \src "ls180.v:1877.5-1877.44"
+ attribute \src "ls180.v:1873.5-1873.44"
wire $1\builder_libresocsim_wishbone_ack[0:0]
- attribute \src "ls180.v:1873.12-1873.54"
+ attribute \src "ls180.v:1869.12-1869.54"
wire width 32 $1\builder_libresocsim_wishbone_dat_r[31:0]
- attribute \src "ls180.v:1757.11-1757.48"
+ attribute \src "ls180.v:1753.11-1753.48"
wire width 3 $1\builder_multiplexer_next_state[2:0]
- attribute \src "ls180.v:1756.11-1756.43"
+ attribute \src "ls180.v:1752.11-1752.43"
wire width 3 $1\builder_multiplexer_state[2:0]
- attribute \src "ls180.v:2703.32-2703.66"
+ attribute \src "ls180.v:2699.32-2699.66"
wire $1\builder_multiregimpl0_regs0[0:0]
- attribute \src "ls180.v:2704.32-2704.66"
+ attribute \src "ls180.v:2700.32-2700.66"
wire $1\builder_multiregimpl0_regs1[0:0]
- attribute \src "ls180.v:2723.32-2723.67"
+ attribute \src "ls180.v:2719.32-2719.67"
wire $1\builder_multiregimpl10_regs0[0:0]
- attribute \src "ls180.v:2724.32-2724.67"
+ attribute \src "ls180.v:2720.32-2720.67"
wire $1\builder_multiregimpl10_regs1[0:0]
- attribute \src "ls180.v:2725.32-2725.67"
+ attribute \src "ls180.v:2721.32-2721.67"
wire $1\builder_multiregimpl11_regs0[0:0]
- attribute \src "ls180.v:2726.32-2726.67"
+ attribute \src "ls180.v:2722.32-2722.67"
wire $1\builder_multiregimpl11_regs1[0:0]
- attribute \src "ls180.v:2727.32-2727.67"
+ attribute \src "ls180.v:2723.32-2723.67"
wire $1\builder_multiregimpl12_regs0[0:0]
- attribute \src "ls180.v:2728.32-2728.67"
+ attribute \src "ls180.v:2724.32-2724.67"
wire $1\builder_multiregimpl12_regs1[0:0]
- attribute \src "ls180.v:2729.32-2729.67"
+ attribute \src "ls180.v:2725.32-2725.67"
wire $1\builder_multiregimpl13_regs0[0:0]
- attribute \src "ls180.v:2730.32-2730.67"
+ attribute \src "ls180.v:2726.32-2726.67"
wire $1\builder_multiregimpl13_regs1[0:0]
- attribute \src "ls180.v:2731.32-2731.67"
+ attribute \src "ls180.v:2727.32-2727.67"
wire $1\builder_multiregimpl14_regs0[0:0]
- attribute \src "ls180.v:2732.32-2732.67"
+ attribute \src "ls180.v:2728.32-2728.67"
wire $1\builder_multiregimpl14_regs1[0:0]
- attribute \src "ls180.v:2733.32-2733.67"
+ attribute \src "ls180.v:2729.32-2729.67"
wire $1\builder_multiregimpl15_regs0[0:0]
- attribute \src "ls180.v:2734.32-2734.67"
+ attribute \src "ls180.v:2730.32-2730.67"
wire $1\builder_multiregimpl15_regs1[0:0]
- attribute \src "ls180.v:2735.32-2735.67"
+ attribute \src "ls180.v:2731.32-2731.67"
wire $1\builder_multiregimpl16_regs0[0:0]
- attribute \src "ls180.v:2736.32-2736.67"
+ attribute \src "ls180.v:2732.32-2732.67"
wire $1\builder_multiregimpl16_regs1[0:0]
- attribute \src "ls180.v:2705.32-2705.66"
+ attribute \src "ls180.v:2701.32-2701.66"
wire $1\builder_multiregimpl1_regs0[0:0]
- attribute \src "ls180.v:2706.32-2706.66"
+ attribute \src "ls180.v:2702.32-2702.66"
wire $1\builder_multiregimpl1_regs1[0:0]
- attribute \src "ls180.v:2707.32-2707.66"
+ attribute \src "ls180.v:2703.32-2703.66"
wire $1\builder_multiregimpl2_regs0[0:0]
- attribute \src "ls180.v:2708.32-2708.66"
+ attribute \src "ls180.v:2704.32-2704.66"
wire $1\builder_multiregimpl2_regs1[0:0]
- attribute \src "ls180.v:2709.32-2709.66"
+ attribute \src "ls180.v:2705.32-2705.66"
wire $1\builder_multiregimpl3_regs0[0:0]
- attribute \src "ls180.v:2710.32-2710.66"
+ attribute \src "ls180.v:2706.32-2706.66"
wire $1\builder_multiregimpl3_regs1[0:0]
- attribute \src "ls180.v:2711.32-2711.66"
+ attribute \src "ls180.v:2707.32-2707.66"
wire $1\builder_multiregimpl4_regs0[0:0]
- attribute \src "ls180.v:2712.32-2712.66"
+ attribute \src "ls180.v:2708.32-2708.66"
wire $1\builder_multiregimpl4_regs1[0:0]
- attribute \src "ls180.v:2713.32-2713.66"
+ attribute \src "ls180.v:2709.32-2709.66"
wire $1\builder_multiregimpl5_regs0[0:0]
- attribute \src "ls180.v:2714.32-2714.66"
+ attribute \src "ls180.v:2710.32-2710.66"
wire $1\builder_multiregimpl5_regs1[0:0]
- attribute \src "ls180.v:2715.32-2715.66"
+ attribute \src "ls180.v:2711.32-2711.66"
wire $1\builder_multiregimpl6_regs0[0:0]
- attribute \src "ls180.v:2716.32-2716.66"
+ attribute \src "ls180.v:2712.32-2712.66"
wire $1\builder_multiregimpl6_regs1[0:0]
- attribute \src "ls180.v:2717.32-2717.66"
+ attribute \src "ls180.v:2713.32-2713.66"
wire $1\builder_multiregimpl7_regs0[0:0]
- attribute \src "ls180.v:2718.32-2718.66"
+ attribute \src "ls180.v:2714.32-2714.66"
wire $1\builder_multiregimpl7_regs1[0:0]
- attribute \src "ls180.v:2719.32-2719.66"
+ attribute \src "ls180.v:2715.32-2715.66"
wire $1\builder_multiregimpl8_regs0[0:0]
- attribute \src "ls180.v:2720.32-2720.66"
+ attribute \src "ls180.v:2716.32-2716.66"
wire $1\builder_multiregimpl8_regs1[0:0]
- attribute \src "ls180.v:2721.32-2721.66"
+ attribute \src "ls180.v:2717.32-2717.66"
wire $1\builder_multiregimpl9_regs0[0:0]
- attribute \src "ls180.v:2722.32-2722.66"
+ attribute \src "ls180.v:2718.32-2718.66"
wire $1\builder_multiregimpl9_regs1[0:0]
- attribute \src "ls180.v:1775.5-1775.43"
+ attribute \src "ls180.v:1771.5-1771.43"
wire $1\builder_new_master_rdata_valid0[0:0]
- attribute \src "ls180.v:1776.5-1776.43"
+ attribute \src "ls180.v:1772.5-1772.43"
wire $1\builder_new_master_rdata_valid1[0:0]
- attribute \src "ls180.v:1777.5-1777.43"
+ attribute \src "ls180.v:1773.5-1773.43"
wire $1\builder_new_master_rdata_valid2[0:0]
- attribute \src "ls180.v:1778.5-1778.43"
+ attribute \src "ls180.v:1774.5-1774.43"
wire $1\builder_new_master_rdata_valid3[0:0]
- attribute \src "ls180.v:1774.5-1774.42"
+ attribute \src "ls180.v:1770.5-1770.42"
wire $1\builder_new_master_wdata_ready[0:0]
- attribute \src "ls180.v:2593.11-2593.36"
+ attribute \src "ls180.v:2589.11-2589.36"
wire width 2 $1\builder_next_state[1:0]
- attribute \src "ls180.v:1747.11-1747.46"
+ attribute \src "ls180.v:1743.11-1743.46"
wire width 2 $1\builder_refresher_next_state[1:0]
- attribute \src "ls180.v:1746.11-1746.41"
+ attribute \src "ls180.v:1742.11-1742.41"
wire width 2 $1\builder_refresher_state[1:0]
- attribute \src "ls180.v:1856.11-1856.51"
+ attribute \src "ls180.v:1852.11-1852.51"
wire width 2 $1\builder_sdblock2memdma_next_state[1:0]
- attribute \src "ls180.v:1855.11-1855.46"
+ attribute \src "ls180.v:1851.11-1851.46"
wire width 2 $1\builder_sdblock2memdma_state[1:0]
- attribute \src "ls180.v:1824.5-1824.57"
+ attribute \src "ls180.v:1820.5-1820.57"
wire $1\builder_sdcore_crcupstreaminserter_next_state[0:0]
- attribute \src "ls180.v:1823.5-1823.52"
+ attribute \src "ls180.v:1819.5-1819.52"
wire $1\builder_sdcore_crcupstreaminserter_state[0:0]
- attribute \src "ls180.v:1836.11-1836.47"
+ attribute \src "ls180.v:1832.11-1832.47"
wire width 3 $1\builder_sdcore_fsm_next_state[2:0]
- attribute \src "ls180.v:1835.11-1835.42"
+ attribute \src "ls180.v:1831.11-1831.42"
wire width 3 $1\builder_sdcore_fsm_state[2:0]
- attribute \src "ls180.v:1860.5-1860.49"
+ attribute \src "ls180.v:1856.5-1856.49"
wire $1\builder_sdmem2blockdma_fsm_next_state[0:0]
- attribute \src "ls180.v:1859.5-1859.44"
+ attribute \src "ls180.v:1855.5-1855.44"
wire $1\builder_sdmem2blockdma_fsm_state[0:0]
- attribute \src "ls180.v:1864.11-1864.65"
+ attribute \src "ls180.v:1860.11-1860.65"
wire width 2 $1\builder_sdmem2blockdma_resetinserter_next_state[1:0]
- attribute \src "ls180.v:1863.11-1863.60"
+ attribute \src "ls180.v:1859.11-1859.60"
wire width 2 $1\builder_sdmem2blockdma_resetinserter_state[1:0]
- attribute \src "ls180.v:1812.11-1812.46"
+ attribute \src "ls180.v:1808.11-1808.46"
wire width 3 $1\builder_sdphy_fsm_next_state[2:0]
- attribute \src "ls180.v:1811.11-1811.41"
+ attribute \src "ls180.v:1807.11-1807.41"
wire width 3 $1\builder_sdphy_fsm_state[2:0]
- attribute \src "ls180.v:1800.11-1800.52"
+ attribute \src "ls180.v:1796.11-1796.52"
wire width 3 $1\builder_sdphy_sdphycmdr_next_state[2:0]
- attribute \src "ls180.v:1799.11-1799.47"
+ attribute \src "ls180.v:1795.11-1795.47"
wire width 3 $1\builder_sdphy_sdphycmdr_state[2:0]
- attribute \src "ls180.v:1796.11-1796.52"
+ attribute \src "ls180.v:1792.11-1792.52"
wire width 2 $1\builder_sdphy_sdphycmdw_next_state[1:0]
- attribute \src "ls180.v:1795.11-1795.47"
+ attribute \src "ls180.v:1791.11-1791.47"
wire width 2 $1\builder_sdphy_sdphycmdw_state[1:0]
- attribute \src "ls180.v:1808.5-1808.46"
+ attribute \src "ls180.v:1804.5-1804.46"
wire $1\builder_sdphy_sdphycrcr_next_state[0:0]
- attribute \src "ls180.v:1807.5-1807.41"
+ attribute \src "ls180.v:1803.5-1803.41"
wire $1\builder_sdphy_sdphycrcr_state[0:0]
- attribute \src "ls180.v:1816.11-1816.53"
+ attribute \src "ls180.v:1812.11-1812.53"
wire width 3 $1\builder_sdphy_sdphydatar_next_state[2:0]
- attribute \src "ls180.v:1815.11-1815.48"
+ attribute \src "ls180.v:1811.11-1811.48"
wire width 3 $1\builder_sdphy_sdphydatar_state[2:0]
- attribute \src "ls180.v:1792.5-1792.46"
+ attribute \src "ls180.v:1788.5-1788.46"
wire $1\builder_sdphy_sdphyinit_next_state[0:0]
- attribute \src "ls180.v:1791.5-1791.41"
+ attribute \src "ls180.v:1787.5-1787.41"
wire $1\builder_sdphy_sdphyinit_state[0:0]
- attribute \src "ls180.v:1888.5-1888.30"
+ attribute \src "ls180.v:1884.5-1884.30"
wire $1\builder_shared_ack[0:0]
- attribute \src "ls180.v:1884.12-1884.40"
+ attribute \src "ls180.v:1880.12-1880.40"
wire width 32 $1\builder_shared_dat_r[31:0]
- attribute \src "ls180.v:1895.11-1895.35"
+ attribute \src "ls180.v:1891.11-1891.35"
wire width 5 $1\builder_slave_sel[4:0]
- attribute \src "ls180.v:1896.11-1896.37"
+ attribute \src "ls180.v:1892.11-1892.37"
wire width 5 $1\builder_slave_sel_r[4:0]
- attribute \src "ls180.v:1784.11-1784.47"
+ attribute \src "ls180.v:1780.11-1780.47"
wire width 2 $1\builder_spimaster0_next_state[1:0]
- attribute \src "ls180.v:1783.11-1783.42"
+ attribute \src "ls180.v:1779.11-1779.42"
wire width 2 $1\builder_spimaster0_state[1:0]
- attribute \src "ls180.v:1788.11-1788.47"
+ attribute \src "ls180.v:1784.11-1784.47"
wire width 2 $1\builder_spimaster1_next_state[1:0]
- attribute \src "ls180.v:1787.11-1787.42"
+ attribute \src "ls180.v:1783.11-1783.42"
wire width 2 $1\builder_spimaster1_state[1:0]
- attribute \src "ls180.v:2592.11-2592.31"
+ attribute \src "ls180.v:2588.11-2588.31"
wire width 2 $1\builder_state[1:0]
- attribute \src "ls180.v:2645.5-2645.39"
+ attribute \src "ls180.v:2641.5-2641.39"
wire $1\builder_sync_f_array_muxed0[0:0]
- attribute \src "ls180.v:2646.5-2646.39"
+ attribute \src "ls180.v:2642.5-2642.39"
wire $1\builder_sync_f_array_muxed1[0:0]
- attribute \src "ls180.v:2638.11-2638.47"
+ attribute \src "ls180.v:2634.11-2634.47"
wire width 2 $1\builder_sync_rhs_array_muxed0[1:0]
- attribute \src "ls180.v:2639.12-2639.49"
+ attribute \src "ls180.v:2635.12-2635.49"
wire width 13 $1\builder_sync_rhs_array_muxed1[12:0]
- attribute \src "ls180.v:2640.5-2640.41"
+ attribute \src "ls180.v:2636.5-2636.41"
wire $1\builder_sync_rhs_array_muxed2[0:0]
- attribute \src "ls180.v:2641.5-2641.41"
+ attribute \src "ls180.v:2637.5-2637.41"
wire $1\builder_sync_rhs_array_muxed3[0:0]
- attribute \src "ls180.v:2642.5-2642.41"
+ attribute \src "ls180.v:2638.5-2638.41"
wire $1\builder_sync_rhs_array_muxed4[0:0]
- attribute \src "ls180.v:2643.5-2643.41"
+ attribute \src "ls180.v:2639.5-2639.41"
wire $1\builder_sync_rhs_array_muxed5[0:0]
- attribute \src "ls180.v:2644.5-2644.41"
+ attribute \src "ls180.v:2640.5-2640.41"
wire $1\builder_sync_rhs_array_muxed6[0:0]
- attribute \src "ls180.v:836.5-836.29"
+ attribute \src "ls180.v:832.5-832.29"
wire $1\main_cmd_consumed[0:0]
- attribute \src "ls180.v:833.5-833.34"
+ attribute \src "ls180.v:829.5-829.34"
wire $1\main_converter_counter[0:0]
- attribute \src "ls180.v:1781.5-1781.55"
+ attribute \src "ls180.v:1777.5-1777.55"
wire $1\main_converter_counter_converter_next_value[0:0]
- attribute \src "ls180.v:1782.5-1782.58"
+ attribute \src "ls180.v:1778.5-1778.58"
wire $1\main_converter_counter_converter_next_value_ce[0:0]
- attribute \src "ls180.v:835.12-835.40"
+ attribute \src "ls180.v:831.12-831.40"
wire width 32 $1\main_converter_dat_r[31:0]
- attribute \src "ls180.v:832.5-832.31"
+ attribute \src "ls180.v:828.5-828.31"
wire $1\main_converter_skip[0:0]
- attribute \src "ls180.v:267.12-267.38"
+ attribute \src "ls180.v:263.12-263.38"
wire width 16 $1\main_dfi_p0_rddata[15:0]
- attribute \src "ls180.v:268.5-268.36"
+ attribute \src "ls180.v:264.5-264.36"
wire $1\main_dfi_p0_rddata_valid[0:0]
- attribute \src "ls180.v:1067.12-1067.30"
+ attribute \src "ls180.v:1063.12-1063.30"
wire width 24 $1\main_dummy[23:0]
- attribute \src "ls180.v:984.5-984.27"
+ attribute \src "ls180.v:980.5-980.27"
wire $1\main_gpio_oe_re[0:0]
- attribute \src "ls180.v:983.12-983.40"
+ attribute \src "ls180.v:979.12-979.40"
wire width 16 $1\main_gpio_oe_storage[15:0]
- attribute \src "ls180.v:988.5-988.28"
+ attribute \src "ls180.v:984.5-984.28"
wire $1\main_gpio_out_re[0:0]
- attribute \src "ls180.v:987.12-987.41"
+ attribute \src "ls180.v:983.12-983.41"
wire width 16 $1\main_gpio_out_storage[15:0]
- attribute \src "ls180.v:985.12-985.36"
+ attribute \src "ls180.v:981.12-981.36"
wire width 16 $1\main_gpio_status[15:0]
- attribute \src "ls180.v:1092.5-1092.23"
+ attribute \src "ls180.v:1088.5-1088.23"
wire $1\main_i2c_re[0:0]
- attribute \src "ls180.v:1091.11-1091.34"
+ attribute \src "ls180.v:1087.11-1087.34"
wire width 3 $1\main_i2c_storage[2:0]
- attribute \src "ls180.v:252.5-252.24"
+ attribute \src "ls180.v:248.5-248.24"
wire $1\main_int_rst[0:0]
- attribute \src "ls180.v:1640.12-1640.43"
+ attribute \src "ls180.v:1636.12-1636.43"
wire width 32 $1\main_interface1_bus_adr[31:0]
- attribute \src "ls180.v:1644.5-1644.35"
+ attribute \src "ls180.v:1640.5-1640.35"
wire $1\main_interface1_bus_cyc[0:0]
- attribute \src "ls180.v:1643.11-1643.41"
+ attribute \src "ls180.v:1639.11-1639.41"
wire width 4 $1\main_interface1_bus_sel[3:0]
- attribute \src "ls180.v:1645.5-1645.35"
+ attribute \src "ls180.v:1641.5-1641.35"
wire $1\main_interface1_bus_stb[0:0]
- attribute \src "ls180.v:1647.5-1647.34"
+ attribute \src "ls180.v:1643.5-1643.34"
wire $1\main_interface1_bus_we[0:0]
attribute \src "ls180.v:63.12-63.47"
wire width 32 $1\main_libresocsim_bus_errors[31:0]
- attribute \src "ls180.v:174.5-174.47"
+ attribute \src "ls180.v:170.5-170.47"
wire $1\main_libresocsim_converter0_counter[0:0]
- attribute \src "ls180.v:1736.5-1736.69"
+ attribute \src "ls180.v:1732.5-1732.69"
wire $1\main_libresocsim_converter0_counter_converter0_next_value[0:0]
- attribute \src "ls180.v:1737.5-1737.72"
+ attribute \src "ls180.v:1733.5-1733.72"
wire $1\main_libresocsim_converter0_counter_converter0_next_value_ce[0:0]
- attribute \src "ls180.v:176.12-176.53"
+ attribute \src "ls180.v:172.12-172.53"
wire width 64 $1\main_libresocsim_converter0_dat_r[63:0]
- attribute \src "ls180.v:173.5-173.44"
+ attribute \src "ls180.v:169.5-169.44"
wire $1\main_libresocsim_converter0_skip[0:0]
- attribute \src "ls180.v:189.5-189.47"
+ attribute \src "ls180.v:185.5-185.47"
wire $1\main_libresocsim_converter1_counter[0:0]
- attribute \src "ls180.v:1740.5-1740.69"
+ attribute \src "ls180.v:1736.5-1736.69"
wire $1\main_libresocsim_converter1_counter_converter1_next_value[0:0]
- attribute \src "ls180.v:1741.5-1741.72"
+ attribute \src "ls180.v:1737.5-1737.72"
wire $1\main_libresocsim_converter1_counter_converter1_next_value_ce[0:0]
- attribute \src "ls180.v:191.12-191.53"
+ attribute \src "ls180.v:187.12-187.53"
wire width 64 $1\main_libresocsim_converter1_dat_r[63:0]
- attribute \src "ls180.v:188.5-188.44"
+ attribute \src "ls180.v:184.5-184.44"
wire $1\main_libresocsim_converter1_skip[0:0]
- attribute \src "ls180.v:204.5-204.47"
+ attribute \src "ls180.v:200.5-200.47"
wire $1\main_libresocsim_converter2_counter[0:0]
- attribute \src "ls180.v:1744.5-1744.69"
+ attribute \src "ls180.v:1740.5-1740.69"
wire $1\main_libresocsim_converter2_counter_converter2_next_value[0:0]
- attribute \src "ls180.v:1745.5-1745.72"
+ attribute \src "ls180.v:1741.5-1741.72"
wire $1\main_libresocsim_converter2_counter_converter2_next_value_ce[0:0]
- attribute \src "ls180.v:206.12-206.53"
+ attribute \src "ls180.v:202.12-202.53"
wire width 64 $1\main_libresocsim_converter2_dat_r[63:0]
- attribute \src "ls180.v:203.5-203.44"
+ attribute \src "ls180.v:199.5-199.44"
wire $1\main_libresocsim_converter2_skip[0:0]
- attribute \src "ls180.v:227.5-227.34"
+ attribute \src "ls180.v:223.5-223.34"
wire $1\main_libresocsim_en_re[0:0]
- attribute \src "ls180.v:226.5-226.39"
+ attribute \src "ls180.v:222.5-222.39"
wire $1\main_libresocsim_en_storage[0:0]
- attribute \src "ls180.v:247.5-247.44"
+ attribute \src "ls180.v:243.5-243.44"
wire $1\main_libresocsim_eventmanager_re[0:0]
- attribute \src "ls180.v:246.5-246.49"
+ attribute \src "ls180.v:242.5-242.49"
wire $1\main_libresocsim_eventmanager_storage[0:0]
- attribute \src "ls180.v:162.12-162.71"
+ attribute \src "ls180.v:158.12-158.71"
wire width 30 $1\main_libresocsim_interface0_converted_interface_adr[29:0]
- attribute \src "ls180.v:166.5-166.63"
+ attribute \src "ls180.v:162.5-162.63"
wire $1\main_libresocsim_interface0_converted_interface_cyc[0:0]
- attribute \src "ls180.v:163.12-163.73"
+ attribute \src "ls180.v:159.12-159.73"
wire width 32 $1\main_libresocsim_interface0_converted_interface_dat_w[31:0]
- attribute \src "ls180.v:165.11-165.69"
+ attribute \src "ls180.v:161.11-161.69"
wire width 4 $1\main_libresocsim_interface0_converted_interface_sel[3:0]
- attribute \src "ls180.v:167.5-167.63"
+ attribute \src "ls180.v:163.5-163.63"
wire $1\main_libresocsim_interface0_converted_interface_stb[0:0]
- attribute \src "ls180.v:169.5-169.62"
+ attribute \src "ls180.v:165.5-165.62"
wire $1\main_libresocsim_interface0_converted_interface_we[0:0]
- attribute \src "ls180.v:177.12-177.71"
+ attribute \src "ls180.v:173.12-173.71"
wire width 30 $1\main_libresocsim_interface1_converted_interface_adr[29:0]
- attribute \src "ls180.v:181.5-181.63"
+ attribute \src "ls180.v:177.5-177.63"
wire $1\main_libresocsim_interface1_converted_interface_cyc[0:0]
- attribute \src "ls180.v:178.12-178.73"
+ attribute \src "ls180.v:174.12-174.73"
wire width 32 $1\main_libresocsim_interface1_converted_interface_dat_w[31:0]
- attribute \src "ls180.v:180.11-180.69"
+ attribute \src "ls180.v:176.11-176.69"
wire width 4 $1\main_libresocsim_interface1_converted_interface_sel[3:0]
- attribute \src "ls180.v:182.5-182.63"
+ attribute \src "ls180.v:178.5-178.63"
wire $1\main_libresocsim_interface1_converted_interface_stb[0:0]
- attribute \src "ls180.v:184.5-184.62"
+ attribute \src "ls180.v:180.5-180.62"
wire $1\main_libresocsim_interface1_converted_interface_we[0:0]
- attribute \src "ls180.v:192.12-192.71"
+ attribute \src "ls180.v:188.12-188.71"
wire width 30 $1\main_libresocsim_interface2_converted_interface_adr[29:0]
- attribute \src "ls180.v:196.5-196.63"
+ attribute \src "ls180.v:192.5-192.63"
wire $1\main_libresocsim_interface2_converted_interface_cyc[0:0]
- attribute \src "ls180.v:193.12-193.73"
+ attribute \src "ls180.v:189.12-189.73"
wire width 32 $1\main_libresocsim_interface2_converted_interface_dat_w[31:0]
- attribute \src "ls180.v:195.11-195.69"
+ attribute \src "ls180.v:191.11-191.69"
wire width 4 $1\main_libresocsim_interface2_converted_interface_sel[3:0]
- attribute \src "ls180.v:197.5-197.63"
+ attribute \src "ls180.v:193.5-193.63"
wire $1\main_libresocsim_interface2_converted_interface_stb[0:0]
- attribute \src "ls180.v:199.5-199.62"
+ attribute \src "ls180.v:195.5-195.62"
wire $1\main_libresocsim_interface2_converted_interface_we[0:0]
attribute \src "ls180.v:72.5-72.46"
wire $1\main_libresocsim_libresoc_dbus_ack[0:0]
- attribute \src "ls180.v:83.5-83.46"
+ attribute \src "ls180.v:81.5-81.46"
wire $1\main_libresocsim_libresoc_ibus_ack[0:0]
attribute \src "ls180.v:65.12-65.55"
wire width 16 $1\main_libresocsim_libresoc_interrupt[15:0]
- attribute \src "ls180.v:116.5-116.49"
+ attribute \src "ls180.v:112.5-112.49"
wire $1\main_libresocsim_libresoc_jtag_wb_ack[0:0]
- attribute \src "ls180.v:223.5-223.36"
+ attribute \src "ls180.v:219.5-219.36"
wire $1\main_libresocsim_load_re[0:0]
- attribute \src "ls180.v:222.12-222.49"
+ attribute \src "ls180.v:218.12-218.49"
wire width 32 $1\main_libresocsim_load_storage[31:0]
- attribute \src "ls180.v:213.5-213.40"
+ attribute \src "ls180.v:209.5-209.40"
wire $1\main_libresocsim_ram_bus_ack[0:0]
- attribute \src "ls180.v:225.5-225.38"
+ attribute \src "ls180.v:221.5-221.38"
wire $1\main_libresocsim_reload_re[0:0]
- attribute \src "ls180.v:224.12-224.51"
+ attribute \src "ls180.v:220.12-220.51"
wire width 32 $1\main_libresocsim_reload_storage[31:0]
attribute \src "ls180.v:56.5-56.37"
wire $1\main_libresocsim_reset_re[0:0]
wire $1\main_libresocsim_scratch_re[0:0]
attribute \src "ls180.v:57.12-57.60"
wire width 32 $1\main_libresocsim_scratch_storage[31:0]
- attribute \src "ls180.v:229.5-229.44"
+ attribute \src "ls180.v:225.5-225.44"
wire $1\main_libresocsim_update_value_re[0:0]
- attribute \src "ls180.v:228.5-228.49"
+ attribute \src "ls180.v:224.5-224.49"
wire $1\main_libresocsim_update_value_storage[0:0]
- attribute \src "ls180.v:248.12-248.42"
+ attribute \src "ls180.v:244.12-244.42"
wire width 32 $1\main_libresocsim_value[31:0]
- attribute \src "ls180.v:230.12-230.49"
+ attribute \src "ls180.v:226.12-226.49"
wire width 32 $1\main_libresocsim_value_status[31:0]
- attribute \src "ls180.v:220.11-220.37"
+ attribute \src "ls180.v:216.11-216.37"
wire width 4 $1\main_libresocsim_we[3:0]
- attribute \src "ls180.v:236.5-236.39"
+ attribute \src "ls180.v:232.5-232.39"
wire $1\main_libresocsim_zero_clear[0:0]
- attribute \src "ls180.v:237.5-237.45"
+ attribute \src "ls180.v:233.5-233.45"
wire $1\main_libresocsim_zero_old_trigger[0:0]
- attribute \src "ls180.v:234.5-234.41"
+ attribute \src "ls180.v:230.5-230.41"
wire $1\main_libresocsim_zero_pending[0:0]
- attribute \src "ls180.v:824.12-824.40"
+ attribute \src "ls180.v:820.12-820.40"
wire width 30 $1\main_litedram_wb_adr[29:0]
- attribute \src "ls180.v:828.5-828.32"
+ attribute \src "ls180.v:824.5-824.32"
wire $1\main_litedram_wb_cyc[0:0]
- attribute \src "ls180.v:825.12-825.42"
+ attribute \src "ls180.v:821.12-821.42"
wire width 16 $1\main_litedram_wb_dat_w[15:0]
- attribute \src "ls180.v:827.11-827.38"
+ attribute \src "ls180.v:823.11-823.38"
wire width 2 $1\main_litedram_wb_sel[1:0]
- attribute \src "ls180.v:829.5-829.32"
+ attribute \src "ls180.v:825.5-825.32"
wire $1\main_litedram_wb_stb[0:0]
- attribute \src "ls180.v:831.5-831.31"
+ attribute \src "ls180.v:827.5-827.31"
wire $1\main_litedram_wb_we[0:0]
- attribute \src "ls180.v:1071.12-1071.37"
+ attribute \src "ls180.v:1067.12-1067.37"
wire width 32 $1\main_pwm0_counter[31:0]
- attribute \src "ls180.v:1073.5-1073.31"
+ attribute \src "ls180.v:1069.5-1069.31"
wire $1\main_pwm0_enable_re[0:0]
- attribute \src "ls180.v:1072.5-1072.36"
+ attribute \src "ls180.v:1068.5-1068.36"
wire $1\main_pwm0_enable_storage[0:0]
- attribute \src "ls180.v:1077.5-1077.31"
+ attribute \src "ls180.v:1073.5-1073.31"
wire $1\main_pwm0_period_re[0:0]
- attribute \src "ls180.v:1076.12-1076.44"
+ attribute \src "ls180.v:1072.12-1072.44"
wire width 32 $1\main_pwm0_period_storage[31:0]
- attribute \src "ls180.v:1075.5-1075.30"
+ attribute \src "ls180.v:1071.5-1071.30"
wire $1\main_pwm0_width_re[0:0]
- attribute \src "ls180.v:1074.12-1074.43"
+ attribute \src "ls180.v:1070.12-1070.43"
wire width 32 $1\main_pwm0_width_storage[31:0]
- attribute \src "ls180.v:1081.12-1081.37"
+ attribute \src "ls180.v:1077.12-1077.37"
wire width 32 $1\main_pwm1_counter[31:0]
- attribute \src "ls180.v:1083.5-1083.31"
+ attribute \src "ls180.v:1079.5-1079.31"
wire $1\main_pwm1_enable_re[0:0]
- attribute \src "ls180.v:1082.5-1082.36"
+ attribute \src "ls180.v:1078.5-1078.36"
wire $1\main_pwm1_enable_storage[0:0]
- attribute \src "ls180.v:1087.5-1087.31"
+ attribute \src "ls180.v:1083.5-1083.31"
wire $1\main_pwm1_period_re[0:0]
- attribute \src "ls180.v:1086.12-1086.44"
+ attribute \src "ls180.v:1082.12-1082.44"
wire width 32 $1\main_pwm1_period_storage[31:0]
- attribute \src "ls180.v:1085.5-1085.30"
+ attribute \src "ls180.v:1081.5-1081.30"
wire $1\main_pwm1_width_re[0:0]
- attribute \src "ls180.v:1084.12-1084.43"
+ attribute \src "ls180.v:1080.12-1080.43"
wire width 32 $1\main_pwm1_width_storage[31:0]
- attribute \src "ls180.v:269.11-269.32"
+ attribute \src "ls180.v:265.11-265.32"
wire width 3 $1\main_rddata_en[2:0]
- attribute \src "ls180.v:1609.11-1609.50"
+ attribute \src "ls180.v:1605.11-1605.50"
wire width 2 $1\main_sdblock2mem_converter_demux[1:0]
- attribute \src "ls180.v:1605.5-1605.51"
+ attribute \src "ls180.v:1601.5-1601.51"
wire $1\main_sdblock2mem_converter_source_first[0:0]
- attribute \src "ls180.v:1606.5-1606.50"
+ attribute \src "ls180.v:1602.5-1602.50"
wire $1\main_sdblock2mem_converter_source_last[0:0]
- attribute \src "ls180.v:1607.12-1607.66"
+ attribute \src "ls180.v:1603.12-1603.66"
wire width 32 $1\main_sdblock2mem_converter_source_payload_data[31:0]
- attribute \src "ls180.v:1608.11-1608.77"
+ attribute \src "ls180.v:1604.11-1604.77"
wire width 3 $1\main_sdblock2mem_converter_source_payload_valid_token_count[2:0]
- attribute \src "ls180.v:1611.5-1611.49"
+ attribute \src "ls180.v:1607.5-1607.49"
wire $1\main_sdblock2mem_converter_strobe_all[0:0]
- attribute \src "ls180.v:1584.11-1584.47"
+ attribute \src "ls180.v:1580.11-1580.47"
wire width 5 $1\main_sdblock2mem_fifo_consume[4:0]
- attribute \src "ls180.v:1581.11-1581.45"
+ attribute \src "ls180.v:1577.11-1577.45"
wire width 6 $1\main_sdblock2mem_fifo_level[5:0]
- attribute \src "ls180.v:1583.11-1583.47"
+ attribute \src "ls180.v:1579.11-1579.47"
wire width 5 $1\main_sdblock2mem_fifo_produce[4:0]
- attribute \src "ls180.v:1585.11-1585.50"
+ attribute \src "ls180.v:1581.11-1581.50"
wire width 5 $1\main_sdblock2mem_fifo_wrport_adr[4:0]
- attribute \src "ls180.v:1619.12-1619.62"
+ attribute \src "ls180.v:1615.12-1615.62"
wire width 32 $1\main_sdblock2mem_sink_sink_payload_address[31:0]
- attribute \src "ls180.v:1620.12-1620.60"
+ attribute \src "ls180.v:1616.12-1616.60"
wire width 32 $1\main_sdblock2mem_sink_sink_payload_data1[31:0]
- attribute \src "ls180.v:1617.5-1617.45"
+ attribute \src "ls180.v:1613.5-1613.45"
wire $1\main_sdblock2mem_sink_sink_valid1[0:0]
- attribute \src "ls180.v:1627.5-1627.54"
+ attribute \src "ls180.v:1623.5-1623.54"
wire $1\main_sdblock2mem_wishbonedmawriter_base_re[0:0]
- attribute \src "ls180.v:1626.12-1626.67"
+ attribute \src "ls180.v:1622.12-1622.67"
wire width 64 $1\main_sdblock2mem_wishbonedmawriter_base_storage[63:0]
- attribute \src "ls180.v:1631.5-1631.56"
+ attribute \src "ls180.v:1627.5-1627.56"
wire $1\main_sdblock2mem_wishbonedmawriter_enable_re[0:0]
- attribute \src "ls180.v:1630.5-1630.61"
+ attribute \src "ls180.v:1626.5-1626.61"
wire $1\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0]
- attribute \src "ls180.v:1629.5-1629.56"
+ attribute \src "ls180.v:1625.5-1625.56"
wire $1\main_sdblock2mem_wishbonedmawriter_length_re[0:0]
- attribute \src "ls180.v:1628.12-1628.69"
+ attribute \src "ls180.v:1624.12-1624.69"
wire width 32 $1\main_sdblock2mem_wishbonedmawriter_length_storage[31:0]
- attribute \src "ls180.v:1635.5-1635.54"
+ attribute \src "ls180.v:1631.5-1631.54"
wire $1\main_sdblock2mem_wishbonedmawriter_loop_re[0:0]
- attribute \src "ls180.v:1634.5-1634.59"
+ attribute \src "ls180.v:1630.5-1630.59"
wire $1\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0]
- attribute \src "ls180.v:1637.12-1637.61"
+ attribute \src "ls180.v:1633.12-1633.61"
wire width 32 $1\main_sdblock2mem_wishbonedmawriter_offset[31:0]
- attribute \src "ls180.v:1857.12-1857.87"
+ attribute \src "ls180.v:1853.12-1853.87"
wire width 32 $1\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0]
- attribute \src "ls180.v:1858.5-1858.82"
+ attribute \src "ls180.v:1854.5-1854.82"
wire $1\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0]
- attribute \src "ls180.v:1622.5-1622.57"
+ attribute \src "ls180.v:1618.5-1618.57"
wire $1\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0]
- attribute \src "ls180.v:1632.5-1632.53"
+ attribute \src "ls180.v:1628.5-1628.53"
wire $1\main_sdblock2mem_wishbonedmawriter_status[0:0]
- attribute \src "ls180.v:1401.5-1401.38"
+ attribute \src "ls180.v:1397.5-1397.38"
wire $1\main_sdcore_block_count_re[0:0]
- attribute \src "ls180.v:1400.12-1400.51"
+ attribute \src "ls180.v:1396.12-1396.51"
wire width 32 $1\main_sdcore_block_count_storage[31:0]
- attribute \src "ls180.v:1399.5-1399.39"
+ attribute \src "ls180.v:1395.5-1395.39"
wire $1\main_sdcore_block_length_re[0:0]
- attribute \src "ls180.v:1398.11-1398.51"
+ attribute \src "ls180.v:1394.11-1394.51"
wire width 10 $1\main_sdcore_block_length_storage[9:0]
- attribute \src "ls180.v:1385.5-1385.39"
+ attribute \src "ls180.v:1381.5-1381.39"
wire $1\main_sdcore_cmd_argument_re[0:0]
- attribute \src "ls180.v:1384.12-1384.52"
+ attribute \src "ls180.v:1380.12-1380.52"
wire width 32 $1\main_sdcore_cmd_argument_storage[31:0]
- attribute \src "ls180.v:1387.5-1387.38"
+ attribute \src "ls180.v:1383.5-1383.38"
wire $1\main_sdcore_cmd_command_re[0:0]
- attribute \src "ls180.v:1386.12-1386.51"
+ attribute \src "ls180.v:1382.12-1382.51"
wire width 32 $1\main_sdcore_cmd_command_storage[31:0]
- attribute \src "ls180.v:1540.11-1540.39"
+ attribute \src "ls180.v:1536.11-1536.39"
wire width 3 $1\main_sdcore_cmd_count[2:0]
- attribute \src "ls180.v:1841.11-1841.62"
+ attribute \src "ls180.v:1837.11-1837.62"
wire width 3 $1\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0]
- attribute \src "ls180.v:1842.5-1842.59"
+ attribute \src "ls180.v:1838.5-1838.59"
wire $1\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0]
- attribute \src "ls180.v:1541.5-1541.32"
+ attribute \src "ls180.v:1537.5-1537.32"
wire $1\main_sdcore_cmd_done[0:0]
- attribute \src "ls180.v:1837.5-1837.55"
+ attribute \src "ls180.v:1833.5-1833.55"
wire $1\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0]
- attribute \src "ls180.v:1838.5-1838.58"
+ attribute \src "ls180.v:1834.5-1834.58"
wire $1\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0]
- attribute \src "ls180.v:1542.5-1542.33"
+ attribute \src "ls180.v:1538.5-1538.33"
wire $1\main_sdcore_cmd_error[0:0]
- attribute \src "ls180.v:1845.5-1845.56"
+ attribute \src "ls180.v:1841.5-1841.56"
wire $1\main_sdcore_cmd_error_sdcore_fsm_next_value4[0:0]
- attribute \src "ls180.v:1846.5-1846.59"
+ attribute \src "ls180.v:1842.5-1842.59"
wire $1\main_sdcore_cmd_error_sdcore_fsm_next_value_ce4[0:0]
- attribute \src "ls180.v:1392.13-1392.53"
+ attribute \src "ls180.v:1388.13-1388.53"
wire width 128 $1\main_sdcore_cmd_response_status[127:0]
- attribute \src "ls180.v:1853.13-1853.76"
+ attribute \src "ls180.v:1849.13-1849.76"
wire width 128 $1\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0]
- attribute \src "ls180.v:1854.5-1854.69"
+ attribute \src "ls180.v:1850.5-1850.69"
wire $1\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0]
- attribute \src "ls180.v:1543.5-1543.35"
+ attribute \src "ls180.v:1539.5-1539.35"
wire $1\main_sdcore_cmd_timeout[0:0]
- attribute \src "ls180.v:1847.5-1847.58"
+ attribute \src "ls180.v:1843.5-1843.58"
wire $1\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0]
- attribute \src "ls180.v:1848.5-1848.61"
+ attribute \src "ls180.v:1844.5-1844.61"
wire $1\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0]
- attribute \src "ls180.v:1501.11-1501.47"
+ attribute \src "ls180.v:1497.11-1497.47"
wire width 4 $1\main_sdcore_crc16_checker_cnt[3:0]
- attribute \src "ls180.v:1507.5-1507.46"
+ attribute \src "ls180.v:1503.5-1503.46"
wire $1\main_sdcore_crc16_checker_crc0_clr[0:0]
- attribute \src "ls180.v:1506.12-1506.54"
+ attribute \src "ls180.v:1502.12-1502.54"
wire width 16 $1\main_sdcore_crc16_checker_crc0_crc[15:0]
- attribute \src "ls180.v:1502.12-1502.58"
+ attribute \src "ls180.v:1498.12-1498.58"
wire width 16 $1\main_sdcore_crc16_checker_crc0_crcreg0[15:0]
- attribute \src "ls180.v:1514.5-1514.46"
+ attribute \src "ls180.v:1510.5-1510.46"
wire $1\main_sdcore_crc16_checker_crc1_clr[0:0]
- attribute \src "ls180.v:1513.12-1513.54"
+ attribute \src "ls180.v:1509.12-1509.54"
wire width 16 $1\main_sdcore_crc16_checker_crc1_crc[15:0]
- attribute \src "ls180.v:1509.12-1509.58"
+ attribute \src "ls180.v:1505.12-1505.58"
wire width 16 $1\main_sdcore_crc16_checker_crc1_crcreg0[15:0]
- attribute \src "ls180.v:1521.5-1521.46"
+ attribute \src "ls180.v:1517.5-1517.46"
wire $1\main_sdcore_crc16_checker_crc2_clr[0:0]
- attribute \src "ls180.v:1520.12-1520.54"
+ attribute \src "ls180.v:1516.12-1516.54"
wire width 16 $1\main_sdcore_crc16_checker_crc2_crc[15:0]
- attribute \src "ls180.v:1516.12-1516.58"
+ attribute \src "ls180.v:1512.12-1512.58"
wire width 16 $1\main_sdcore_crc16_checker_crc2_crcreg0[15:0]
- attribute \src "ls180.v:1528.5-1528.46"
+ attribute \src "ls180.v:1524.5-1524.46"
wire $1\main_sdcore_crc16_checker_crc3_clr[0:0]
- attribute \src "ls180.v:1527.12-1527.54"
+ attribute \src "ls180.v:1523.12-1523.54"
wire width 16 $1\main_sdcore_crc16_checker_crc3_crc[15:0]
- attribute \src "ls180.v:1523.12-1523.58"
+ attribute \src "ls180.v:1519.12-1519.58"
wire width 16 $1\main_sdcore_crc16_checker_crc3_crcreg0[15:0]
- attribute \src "ls180.v:1530.12-1530.53"
+ attribute \src "ls180.v:1526.12-1526.53"
wire width 16 $1\main_sdcore_crc16_checker_crctmp0[15:0]
- attribute \src "ls180.v:1531.12-1531.53"
+ attribute \src "ls180.v:1527.12-1527.53"
wire width 16 $1\main_sdcore_crc16_checker_crctmp1[15:0]
- attribute \src "ls180.v:1532.12-1532.53"
+ attribute \src "ls180.v:1528.12-1528.53"
wire width 16 $1\main_sdcore_crc16_checker_crctmp2[15:0]
- attribute \src "ls180.v:1533.12-1533.53"
+ attribute \src "ls180.v:1529.12-1529.53"
wire width 16 $1\main_sdcore_crc16_checker_crctmp3[15:0]
- attribute \src "ls180.v:1535.12-1535.51"
+ attribute \src "ls180.v:1531.12-1531.51"
wire width 16 $1\main_sdcore_crc16_checker_fifo0[15:0]
- attribute \src "ls180.v:1536.12-1536.51"
+ attribute \src "ls180.v:1532.12-1532.51"
wire width 16 $1\main_sdcore_crc16_checker_fifo1[15:0]
- attribute \src "ls180.v:1537.12-1537.51"
+ attribute \src "ls180.v:1533.12-1533.51"
wire width 16 $1\main_sdcore_crc16_checker_fifo2[15:0]
- attribute \src "ls180.v:1538.12-1538.51"
+ attribute \src "ls180.v:1534.12-1534.51"
wire width 16 $1\main_sdcore_crc16_checker_fifo3[15:0]
- attribute \src "ls180.v:1492.5-1492.48"
+ attribute \src "ls180.v:1488.5-1488.48"
wire $1\main_sdcore_crc16_checker_sink_first[0:0]
- attribute \src "ls180.v:1493.5-1493.47"
+ attribute \src "ls180.v:1489.5-1489.47"
wire $1\main_sdcore_crc16_checker_sink_last[0:0]
- attribute \src "ls180.v:1494.11-1494.61"
+ attribute \src "ls180.v:1490.11-1490.61"
wire width 8 $1\main_sdcore_crc16_checker_sink_payload_data[7:0]
- attribute \src "ls180.v:1491.5-1491.48"
+ attribute \src "ls180.v:1487.5-1487.48"
wire $1\main_sdcore_crc16_checker_sink_ready[0:0]
- attribute \src "ls180.v:1490.5-1490.48"
+ attribute \src "ls180.v:1486.5-1486.48"
wire $1\main_sdcore_crc16_checker_sink_valid[0:0]
- attribute \src "ls180.v:1495.5-1495.50"
+ attribute \src "ls180.v:1491.5-1491.50"
wire $1\main_sdcore_crc16_checker_source_valid[0:0]
- attribute \src "ls180.v:1500.11-1500.47"
+ attribute \src "ls180.v:1496.11-1496.47"
wire width 8 $1\main_sdcore_crc16_checker_val[7:0]
- attribute \src "ls180.v:1534.5-1534.43"
+ attribute \src "ls180.v:1530.5-1530.43"
wire $1\main_sdcore_crc16_checker_valid[0:0]
- attribute \src "ls180.v:1457.11-1457.48"
+ attribute \src "ls180.v:1453.11-1453.48"
wire width 3 $1\main_sdcore_crc16_inserter_cnt[2:0]
- attribute \src "ls180.v:1833.11-1833.87"
+ attribute \src "ls180.v:1829.11-1829.87"
wire width 3 $1\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0]
- attribute \src "ls180.v:1834.5-1834.84"
+ attribute \src "ls180.v:1830.5-1830.84"
wire $1\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0]
- attribute \src "ls180.v:1462.12-1462.55"
+ attribute \src "ls180.v:1458.12-1458.55"
wire width 16 $1\main_sdcore_crc16_inserter_crc0_crc[15:0]
- attribute \src "ls180.v:1458.12-1458.59"
+ attribute \src "ls180.v:1454.12-1454.59"
wire width 16 $1\main_sdcore_crc16_inserter_crc0_crcreg0[15:0]
- attribute \src "ls180.v:1469.12-1469.55"
+ attribute \src "ls180.v:1465.12-1465.55"
wire width 16 $1\main_sdcore_crc16_inserter_crc1_crc[15:0]
- attribute \src "ls180.v:1465.12-1465.59"
+ attribute \src "ls180.v:1461.12-1461.59"
wire width 16 $1\main_sdcore_crc16_inserter_crc1_crcreg0[15:0]
- attribute \src "ls180.v:1476.12-1476.55"
+ attribute \src "ls180.v:1472.12-1472.55"
wire width 16 $1\main_sdcore_crc16_inserter_crc2_crc[15:0]
- attribute \src "ls180.v:1472.12-1472.59"
+ attribute \src "ls180.v:1468.12-1468.59"
wire width 16 $1\main_sdcore_crc16_inserter_crc2_crcreg0[15:0]
- attribute \src "ls180.v:1483.12-1483.55"
+ attribute \src "ls180.v:1479.12-1479.55"
wire width 16 $1\main_sdcore_crc16_inserter_crc3_crc[15:0]
- attribute \src "ls180.v:1479.12-1479.59"
+ attribute \src "ls180.v:1475.12-1475.59"
wire width 16 $1\main_sdcore_crc16_inserter_crc3_crcreg0[15:0]
- attribute \src "ls180.v:1486.12-1486.54"
+ attribute \src "ls180.v:1482.12-1482.54"
wire width 16 $1\main_sdcore_crc16_inserter_crctmp0[15:0]
- attribute \src "ls180.v:1825.12-1825.93"
+ attribute \src "ls180.v:1821.12-1821.93"
wire width 16 $1\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0]
- attribute \src "ls180.v:1826.5-1826.88"
+ attribute \src "ls180.v:1822.5-1822.88"
wire $1\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0]
- attribute \src "ls180.v:1487.12-1487.54"
+ attribute \src "ls180.v:1483.12-1483.54"
wire width 16 $1\main_sdcore_crc16_inserter_crctmp1[15:0]
- attribute \src "ls180.v:1827.12-1827.93"
+ attribute \src "ls180.v:1823.12-1823.93"
wire width 16 $1\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0]
- attribute \src "ls180.v:1828.5-1828.88"
+ attribute \src "ls180.v:1824.5-1824.88"
wire $1\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0]
- attribute \src "ls180.v:1488.12-1488.54"
+ attribute \src "ls180.v:1484.12-1484.54"
wire width 16 $1\main_sdcore_crc16_inserter_crctmp2[15:0]
- attribute \src "ls180.v:1829.12-1829.93"
+ attribute \src "ls180.v:1825.12-1825.93"
wire width 16 $1\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0]
- attribute \src "ls180.v:1830.5-1830.88"
+ attribute \src "ls180.v:1826.5-1826.88"
wire $1\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0]
- attribute \src "ls180.v:1489.12-1489.54"
+ attribute \src "ls180.v:1485.12-1485.54"
wire width 16 $1\main_sdcore_crc16_inserter_crctmp3[15:0]
- attribute \src "ls180.v:1831.12-1831.93"
+ attribute \src "ls180.v:1827.12-1827.93"
wire width 16 $1\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0]
- attribute \src "ls180.v:1832.5-1832.88"
+ attribute \src "ls180.v:1828.5-1828.88"
wire $1\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0]
- attribute \src "ls180.v:1448.5-1448.49"
+ attribute \src "ls180.v:1444.5-1444.49"
wire $1\main_sdcore_crc16_inserter_sink_ready[0:0]
- attribute \src "ls180.v:1455.5-1455.50"
+ attribute \src "ls180.v:1451.5-1451.50"
wire $1\main_sdcore_crc16_inserter_source_last[0:0]
- attribute \src "ls180.v:1456.11-1456.64"
+ attribute \src "ls180.v:1452.11-1452.64"
wire width 8 $1\main_sdcore_crc16_inserter_source_payload_data[7:0]
- attribute \src "ls180.v:1453.5-1453.51"
+ attribute \src "ls180.v:1449.5-1449.51"
wire $1\main_sdcore_crc16_inserter_source_ready[0:0]
- attribute \src "ls180.v:1452.5-1452.51"
+ attribute \src "ls180.v:1448.5-1448.51"
wire $1\main_sdcore_crc16_inserter_source_valid[0:0]
- attribute \src "ls180.v:1444.11-1444.47"
+ attribute \src "ls180.v:1440.11-1440.47"
wire width 7 $1\main_sdcore_crc7_inserter_crc[6:0]
- attribute \src "ls180.v:1402.11-1402.51"
+ attribute \src "ls180.v:1398.11-1398.51"
wire width 7 $1\main_sdcore_crc7_inserter_crcreg0[6:0]
- attribute \src "ls180.v:1545.12-1545.42"
+ attribute \src "ls180.v:1541.12-1541.42"
wire width 32 $1\main_sdcore_data_count[31:0]
- attribute \src "ls180.v:1843.12-1843.65"
+ attribute \src "ls180.v:1839.12-1839.65"
wire width 32 $1\main_sdcore_data_count_sdcore_fsm_next_value3[31:0]
- attribute \src "ls180.v:1844.5-1844.60"
+ attribute \src "ls180.v:1840.5-1840.60"
wire $1\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0]
- attribute \src "ls180.v:1546.5-1546.33"
+ attribute \src "ls180.v:1542.5-1542.33"
wire $1\main_sdcore_data_done[0:0]
- attribute \src "ls180.v:1839.5-1839.56"
+ attribute \src "ls180.v:1835.5-1835.56"
wire $1\main_sdcore_data_done_sdcore_fsm_next_value1[0:0]
- attribute \src "ls180.v:1840.5-1840.59"
+ attribute \src "ls180.v:1836.5-1836.59"
wire $1\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0]
- attribute \src "ls180.v:1547.5-1547.34"
+ attribute \src "ls180.v:1543.5-1543.34"
wire $1\main_sdcore_data_error[0:0]
- attribute \src "ls180.v:1849.5-1849.57"
+ attribute \src "ls180.v:1845.5-1845.57"
wire $1\main_sdcore_data_error_sdcore_fsm_next_value6[0:0]
- attribute \src "ls180.v:1850.5-1850.60"
+ attribute \src "ls180.v:1846.5-1846.60"
wire $1\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0]
- attribute \src "ls180.v:1548.5-1548.36"
+ attribute \src "ls180.v:1544.5-1544.36"
wire $1\main_sdcore_data_timeout[0:0]
- attribute \src "ls180.v:1851.5-1851.59"
+ attribute \src "ls180.v:1847.5-1847.59"
wire $1\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0]
- attribute \src "ls180.v:1852.5-1852.62"
+ attribute \src "ls180.v:1848.5-1848.62"
wire $1\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0]
- attribute \src "ls180.v:1693.11-1693.48"
+ attribute \src "ls180.v:1689.11-1689.48"
wire width 2 $1\main_sdmem2block_converter_mux[1:0]
- attribute \src "ls180.v:1691.11-1691.64"
+ attribute \src "ls180.v:1687.11-1687.64"
wire width 8 $1\main_sdmem2block_converter_source_payload_data[7:0]
- attribute \src "ls180.v:1667.5-1667.40"
+ attribute \src "ls180.v:1663.5-1663.40"
wire $1\main_sdmem2block_dma_base_re[0:0]
- attribute \src "ls180.v:1666.12-1666.53"
+ attribute \src "ls180.v:1662.12-1662.53"
wire width 64 $1\main_sdmem2block_dma_base_storage[63:0]
- attribute \src "ls180.v:1665.12-1665.45"
+ attribute \src "ls180.v:1661.12-1661.45"
wire width 32 $1\main_sdmem2block_dma_data[31:0]
- attribute \src "ls180.v:1861.12-1861.75"
+ attribute \src "ls180.v:1857.12-1857.75"
wire width 32 $1\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[31:0]
- attribute \src "ls180.v:1862.5-1862.70"
+ attribute \src "ls180.v:1858.5-1858.70"
wire $1\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0]
- attribute \src "ls180.v:1672.5-1672.44"
+ attribute \src "ls180.v:1668.5-1668.44"
wire $1\main_sdmem2block_dma_done_status[0:0]
- attribute \src "ls180.v:1671.5-1671.42"
+ attribute \src "ls180.v:1667.5-1667.42"
wire $1\main_sdmem2block_dma_enable_re[0:0]
- attribute \src "ls180.v:1670.5-1670.47"
+ attribute \src "ls180.v:1666.5-1666.47"
wire $1\main_sdmem2block_dma_enable_storage[0:0]
- attribute \src "ls180.v:1669.5-1669.42"
+ attribute \src "ls180.v:1665.5-1665.42"
wire $1\main_sdmem2block_dma_length_re[0:0]
- attribute \src "ls180.v:1668.12-1668.55"
+ attribute \src "ls180.v:1664.12-1664.55"
wire width 32 $1\main_sdmem2block_dma_length_storage[31:0]
- attribute \src "ls180.v:1675.5-1675.40"
+ attribute \src "ls180.v:1671.5-1671.40"
wire $1\main_sdmem2block_dma_loop_re[0:0]
- attribute \src "ls180.v:1674.5-1674.45"
+ attribute \src "ls180.v:1670.5-1670.45"
wire $1\main_sdmem2block_dma_loop_storage[0:0]
- attribute \src "ls180.v:1679.12-1679.47"
+ attribute \src "ls180.v:1675.12-1675.47"
wire width 32 $1\main_sdmem2block_dma_offset[31:0]
- attribute \src "ls180.v:1865.12-1865.87"
+ attribute \src "ls180.v:1861.12-1861.87"
wire width 32 $1\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0]
- attribute \src "ls180.v:1866.5-1866.82"
+ attribute \src "ls180.v:1862.5-1862.82"
wire $1\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0]
- attribute \src "ls180.v:1658.5-1658.42"
+ attribute \src "ls180.v:1654.5-1654.42"
wire $1\main_sdmem2block_dma_sink_last[0:0]
- attribute \src "ls180.v:1659.12-1659.61"
+ attribute \src "ls180.v:1655.12-1655.61"
wire width 32 $1\main_sdmem2block_dma_sink_payload_address[31:0]
- attribute \src "ls180.v:1657.5-1657.43"
+ attribute \src "ls180.v:1653.5-1653.43"
wire $1\main_sdmem2block_dma_sink_ready[0:0]
- attribute \src "ls180.v:1656.5-1656.43"
+ attribute \src "ls180.v:1652.5-1652.43"
wire $1\main_sdmem2block_dma_sink_valid[0:0]
- attribute \src "ls180.v:1663.5-1663.44"
+ attribute \src "ls180.v:1659.5-1659.44"
wire $1\main_sdmem2block_dma_source_last[0:0]
- attribute \src "ls180.v:1664.12-1664.60"
+ attribute \src "ls180.v:1660.12-1660.60"
wire width 32 $1\main_sdmem2block_dma_source_payload_data[31:0]
- attribute \src "ls180.v:1660.5-1660.45"
+ attribute \src "ls180.v:1656.5-1656.45"
wire $1\main_sdmem2block_dma_source_valid[0:0]
- attribute \src "ls180.v:1720.11-1720.47"
+ attribute \src "ls180.v:1716.11-1716.47"
wire width 5 $1\main_sdmem2block_fifo_consume[4:0]
- attribute \src "ls180.v:1717.11-1717.45"
+ attribute \src "ls180.v:1713.11-1713.45"
wire width 6 $1\main_sdmem2block_fifo_level[5:0]
- attribute \src "ls180.v:1719.11-1719.47"
+ attribute \src "ls180.v:1715.11-1715.47"
wire width 5 $1\main_sdmem2block_fifo_produce[4:0]
- attribute \src "ls180.v:1721.11-1721.50"
+ attribute \src "ls180.v:1717.11-1717.50"
wire width 5 $1\main_sdmem2block_fifo_wrport_adr[4:0]
- attribute \src "ls180.v:1101.5-1101.35"
+ attribute \src "ls180.v:1097.5-1097.35"
wire $1\main_sdphy_clocker_clk0[0:0]
- attribute \src "ls180.v:1104.5-1104.35"
+ attribute \src "ls180.v:1100.5-1100.35"
wire $1\main_sdphy_clocker_clk1[0:0]
- attribute \src "ls180.v:1105.5-1105.36"
+ attribute \src "ls180.v:1101.5-1101.36"
wire $1\main_sdphy_clocker_clk_d[0:0]
- attribute \src "ls180.v:1103.11-1103.41"
+ attribute \src "ls180.v:1099.11-1099.41"
wire width 9 $1\main_sdphy_clocker_clks[8:0]
- attribute \src "ls180.v:1099.5-1099.33"
+ attribute \src "ls180.v:1095.5-1095.33"
wire $1\main_sdphy_clocker_re[0:0]
- attribute \src "ls180.v:1098.11-1098.46"
+ attribute \src "ls180.v:1094.11-1094.46"
wire width 9 $1\main_sdphy_clocker_storage[8:0]
- attribute \src "ls180.v:1207.5-1207.49"
+ attribute \src "ls180.v:1203.5-1203.49"
wire $1\main_sdphy_cmdr_cmdr_buf_source_first[0:0]
- attribute \src "ls180.v:1208.5-1208.48"
+ attribute \src "ls180.v:1204.5-1204.48"
wire $1\main_sdphy_cmdr_cmdr_buf_source_last[0:0]
- attribute \src "ls180.v:1209.11-1209.62"
+ attribute \src "ls180.v:1205.11-1205.62"
wire width 8 $1\main_sdphy_cmdr_cmdr_buf_source_payload_data[7:0]
- attribute \src "ls180.v:1205.5-1205.49"
+ attribute \src "ls180.v:1201.5-1201.49"
wire $1\main_sdphy_cmdr_cmdr_buf_source_valid[0:0]
- attribute \src "ls180.v:1192.11-1192.54"
+ attribute \src "ls180.v:1188.11-1188.54"
wire width 3 $1\main_sdphy_cmdr_cmdr_converter_demux[2:0]
- attribute \src "ls180.v:1188.5-1188.55"
+ attribute \src "ls180.v:1184.5-1184.55"
wire $1\main_sdphy_cmdr_cmdr_converter_source_first[0:0]
- attribute \src "ls180.v:1189.5-1189.54"
+ attribute \src "ls180.v:1185.5-1185.54"
wire $1\main_sdphy_cmdr_cmdr_converter_source_last[0:0]
- attribute \src "ls180.v:1190.11-1190.68"
+ attribute \src "ls180.v:1186.11-1186.68"
wire width 8 $1\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0]
- attribute \src "ls180.v:1191.11-1191.81"
+ attribute \src "ls180.v:1187.11-1187.81"
wire width 4 $1\main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count[3:0]
- attribute \src "ls180.v:1194.5-1194.53"
+ attribute \src "ls180.v:1190.5-1190.53"
wire $1\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0]
- attribute \src "ls180.v:1210.5-1210.38"
+ attribute \src "ls180.v:1206.5-1206.38"
wire $1\main_sdphy_cmdr_cmdr_reset[0:0]
- attribute \src "ls180.v:1805.5-1805.66"
+ attribute \src "ls180.v:1801.5-1801.66"
wire $1\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0]
- attribute \src "ls180.v:1806.5-1806.69"
+ attribute \src "ls180.v:1802.5-1802.69"
wire $1\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0]
- attribute \src "ls180.v:1180.5-1180.36"
+ attribute \src "ls180.v:1176.5-1176.36"
wire $1\main_sdphy_cmdr_cmdr_run[0:0]
- attribute \src "ls180.v:1175.5-1175.53"
+ attribute \src "ls180.v:1171.5-1171.53"
wire $1\main_sdphy_cmdr_cmdr_source_source_ready0[0:0]
- attribute \src "ls180.v:1162.11-1162.39"
+ attribute \src "ls180.v:1158.11-1158.39"
wire width 8 $1\main_sdphy_cmdr_count[7:0]
- attribute \src "ls180.v:1801.11-1801.67"
+ attribute \src "ls180.v:1797.11-1797.67"
wire width 8 $1\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0]
- attribute \src "ls180.v:1802.5-1802.64"
+ attribute \src "ls180.v:1798.5-1798.64"
wire $1\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0]
- attribute \src "ls180.v:1147.5-1147.48"
+ attribute \src "ls180.v:1143.5-1143.48"
wire $1\main_sdphy_cmdr_pads_out_payload_clk[0:0]
- attribute \src "ls180.v:1148.5-1148.50"
+ attribute \src "ls180.v:1144.5-1144.50"
wire $1\main_sdphy_cmdr_pads_out_payload_cmd_o[0:0]
- attribute \src "ls180.v:1149.5-1149.51"
+ attribute \src "ls180.v:1145.5-1145.51"
wire $1\main_sdphy_cmdr_pads_out_payload_cmd_oe[0:0]
- attribute \src "ls180.v:1154.5-1154.37"
+ attribute \src "ls180.v:1150.5-1150.37"
wire $1\main_sdphy_cmdr_sink_last[0:0]
- attribute \src "ls180.v:1155.11-1155.53"
+ attribute \src "ls180.v:1151.11-1151.53"
wire width 8 $1\main_sdphy_cmdr_sink_payload_length[7:0]
- attribute \src "ls180.v:1153.5-1153.38"
+ attribute \src "ls180.v:1149.5-1149.38"
wire $1\main_sdphy_cmdr_sink_ready[0:0]
- attribute \src "ls180.v:1152.5-1152.38"
+ attribute \src "ls180.v:1148.5-1148.38"
wire $1\main_sdphy_cmdr_sink_valid[0:0]
- attribute \src "ls180.v:1158.5-1158.39"
+ attribute \src "ls180.v:1154.5-1154.39"
wire $1\main_sdphy_cmdr_source_last[0:0]
- attribute \src "ls180.v:1159.11-1159.53"
+ attribute \src "ls180.v:1155.11-1155.53"
wire width 8 $1\main_sdphy_cmdr_source_payload_data[7:0]
- attribute \src "ls180.v:1160.11-1160.55"
+ attribute \src "ls180.v:1156.11-1156.55"
wire width 3 $1\main_sdphy_cmdr_source_payload_status[2:0]
- attribute \src "ls180.v:1157.5-1157.40"
+ attribute \src "ls180.v:1153.5-1153.40"
wire $1\main_sdphy_cmdr_source_ready[0:0]
- attribute \src "ls180.v:1156.5-1156.40"
+ attribute \src "ls180.v:1152.5-1152.40"
wire $1\main_sdphy_cmdr_source_valid[0:0]
- attribute \src "ls180.v:1161.12-1161.48"
+ attribute \src "ls180.v:1157.12-1157.48"
wire width 32 $1\main_sdphy_cmdr_timeout[31:0]
- attribute \src "ls180.v:1803.12-1803.71"
+ attribute \src "ls180.v:1799.12-1799.71"
wire width 32 $1\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0]
- attribute \src "ls180.v:1804.5-1804.66"
+ attribute \src "ls180.v:1800.5-1800.66"
wire $1\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0]
- attribute \src "ls180.v:1134.11-1134.39"
+ attribute \src "ls180.v:1130.11-1130.39"
wire width 8 $1\main_sdphy_cmdw_count[7:0]
- attribute \src "ls180.v:1797.11-1797.66"
+ attribute \src "ls180.v:1793.11-1793.66"
wire width 8 $1\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0]
- attribute \src "ls180.v:1798.5-1798.63"
+ attribute \src "ls180.v:1794.5-1794.63"
wire $1\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0]
- attribute \src "ls180.v:1133.5-1133.32"
+ attribute \src "ls180.v:1129.5-1129.32"
wire $1\main_sdphy_cmdw_done[0:0]
- attribute \src "ls180.v:1124.5-1124.48"
+ attribute \src "ls180.v:1120.5-1120.48"
wire $1\main_sdphy_cmdw_pads_out_payload_clk[0:0]
- attribute \src "ls180.v:1125.5-1125.50"
+ attribute \src "ls180.v:1121.5-1121.50"
wire $1\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0]
- attribute \src "ls180.v:1126.5-1126.51"
+ attribute \src "ls180.v:1122.5-1122.51"
wire $1\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0]
- attribute \src "ls180.v:1131.5-1131.37"
+ attribute \src "ls180.v:1127.5-1127.37"
wire $1\main_sdphy_cmdw_sink_last[0:0]
- attribute \src "ls180.v:1132.11-1132.51"
+ attribute \src "ls180.v:1128.11-1128.51"
wire width 8 $1\main_sdphy_cmdw_sink_payload_data[7:0]
- attribute \src "ls180.v:1130.5-1130.38"
+ attribute \src "ls180.v:1126.5-1126.38"
wire $1\main_sdphy_cmdw_sink_ready[0:0]
- attribute \src "ls180.v:1129.5-1129.38"
+ attribute \src "ls180.v:1125.5-1125.38"
wire $1\main_sdphy_cmdw_sink_valid[0:0]
- attribute \src "ls180.v:1318.11-1318.41"
+ attribute \src "ls180.v:1314.11-1314.41"
wire width 10 $1\main_sdphy_datar_count[9:0]
- attribute \src "ls180.v:1817.11-1817.70"
+ attribute \src "ls180.v:1813.11-1813.70"
wire width 10 $1\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0]
- attribute \src "ls180.v:1818.5-1818.66"
+ attribute \src "ls180.v:1814.5-1814.66"
wire $1\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0]
- attribute \src "ls180.v:1363.5-1363.51"
+ attribute \src "ls180.v:1359.5-1359.51"
wire $1\main_sdphy_datar_datar_buf_source_first[0:0]
- attribute \src "ls180.v:1364.5-1364.50"
+ attribute \src "ls180.v:1360.5-1360.50"
wire $1\main_sdphy_datar_datar_buf_source_last[0:0]
- attribute \src "ls180.v:1365.11-1365.64"
+ attribute \src "ls180.v:1361.11-1361.64"
wire width 8 $1\main_sdphy_datar_datar_buf_source_payload_data[7:0]
- attribute \src "ls180.v:1361.5-1361.51"
+ attribute \src "ls180.v:1357.5-1357.51"
wire $1\main_sdphy_datar_datar_buf_source_valid[0:0]
- attribute \src "ls180.v:1348.5-1348.50"
+ attribute \src "ls180.v:1344.5-1344.50"
wire $1\main_sdphy_datar_datar_converter_demux[0:0]
- attribute \src "ls180.v:1344.5-1344.57"
+ attribute \src "ls180.v:1340.5-1340.57"
wire $1\main_sdphy_datar_datar_converter_source_first[0:0]
- attribute \src "ls180.v:1345.5-1345.56"
+ attribute \src "ls180.v:1341.5-1341.56"
wire $1\main_sdphy_datar_datar_converter_source_last[0:0]
- attribute \src "ls180.v:1346.11-1346.70"
+ attribute \src "ls180.v:1342.11-1342.70"
wire width 8 $1\main_sdphy_datar_datar_converter_source_payload_data[7:0]
- attribute \src "ls180.v:1347.11-1347.83"
+ attribute \src "ls180.v:1343.11-1343.83"
wire width 2 $1\main_sdphy_datar_datar_converter_source_payload_valid_token_count[1:0]
- attribute \src "ls180.v:1350.5-1350.55"
+ attribute \src "ls180.v:1346.5-1346.55"
wire $1\main_sdphy_datar_datar_converter_strobe_all[0:0]
- attribute \src "ls180.v:1366.5-1366.40"
+ attribute \src "ls180.v:1362.5-1362.40"
wire $1\main_sdphy_datar_datar_reset[0:0]
- attribute \src "ls180.v:1821.5-1821.69"
+ attribute \src "ls180.v:1817.5-1817.69"
wire $1\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0]
- attribute \src "ls180.v:1822.5-1822.72"
+ attribute \src "ls180.v:1818.5-1818.72"
wire $1\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0]
- attribute \src "ls180.v:1336.5-1336.38"
+ attribute \src "ls180.v:1332.5-1332.38"
wire $1\main_sdphy_datar_datar_run[0:0]
- attribute \src "ls180.v:1331.5-1331.55"
+ attribute \src "ls180.v:1327.5-1327.55"
wire $1\main_sdphy_datar_datar_source_source_ready0[0:0]
- attribute \src "ls180.v:1301.5-1301.49"
+ attribute \src "ls180.v:1297.5-1297.49"
wire $1\main_sdphy_datar_pads_out_payload_clk[0:0]
- attribute \src "ls180.v:1308.5-1308.38"
+ attribute \src "ls180.v:1304.5-1304.38"
wire $1\main_sdphy_datar_sink_last[0:0]
- attribute \src "ls180.v:1309.11-1309.61"
+ attribute \src "ls180.v:1305.11-1305.61"
wire width 10 $1\main_sdphy_datar_sink_payload_block_length[9:0]
- attribute \src "ls180.v:1307.5-1307.39"
+ attribute \src "ls180.v:1303.5-1303.39"
wire $1\main_sdphy_datar_sink_ready[0:0]
- attribute \src "ls180.v:1306.5-1306.39"
+ attribute \src "ls180.v:1302.5-1302.39"
wire $1\main_sdphy_datar_sink_valid[0:0]
- attribute \src "ls180.v:1313.5-1313.40"
+ attribute \src "ls180.v:1309.5-1309.40"
wire $1\main_sdphy_datar_source_last[0:0]
- attribute \src "ls180.v:1314.11-1314.54"
+ attribute \src "ls180.v:1310.11-1310.54"
wire width 8 $1\main_sdphy_datar_source_payload_data[7:0]
- attribute \src "ls180.v:1315.11-1315.56"
+ attribute \src "ls180.v:1311.11-1311.56"
wire width 3 $1\main_sdphy_datar_source_payload_status[2:0]
- attribute \src "ls180.v:1311.5-1311.41"
+ attribute \src "ls180.v:1307.5-1307.41"
wire $1\main_sdphy_datar_source_ready[0:0]
- attribute \src "ls180.v:1310.5-1310.41"
+ attribute \src "ls180.v:1306.5-1306.41"
wire $1\main_sdphy_datar_source_valid[0:0]
- attribute \src "ls180.v:1316.5-1316.33"
+ attribute \src "ls180.v:1312.5-1312.33"
wire $1\main_sdphy_datar_stop[0:0]
- attribute \src "ls180.v:1317.12-1317.49"
+ attribute \src "ls180.v:1313.12-1313.49"
wire width 32 $1\main_sdphy_datar_timeout[31:0]
- attribute \src "ls180.v:1819.12-1819.73"
+ attribute \src "ls180.v:1815.12-1815.73"
wire width 32 $1\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0]
- attribute \src "ls180.v:1820.5-1820.68"
+ attribute \src "ls180.v:1816.5-1816.68"
wire $1\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0]
- attribute \src "ls180.v:1226.11-1226.40"
+ attribute \src "ls180.v:1222.11-1222.40"
wire width 8 $1\main_sdphy_dataw_count[7:0]
- attribute \src "ls180.v:1813.11-1813.61"
+ attribute \src "ls180.v:1809.11-1809.61"
wire width 8 $1\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0]
- attribute \src "ls180.v:1814.5-1814.58"
+ attribute \src "ls180.v:1810.5-1810.58"
wire $1\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0]
- attribute \src "ls180.v:1285.5-1285.50"
+ attribute \src "ls180.v:1281.5-1281.50"
wire $1\main_sdphy_dataw_crcr_buf_source_first[0:0]
- attribute \src "ls180.v:1286.5-1286.49"
+ attribute \src "ls180.v:1282.5-1282.49"
wire $1\main_sdphy_dataw_crcr_buf_source_last[0:0]
- attribute \src "ls180.v:1287.11-1287.63"
+ attribute \src "ls180.v:1283.11-1283.63"
wire width 8 $1\main_sdphy_dataw_crcr_buf_source_payload_data[7:0]
- attribute \src "ls180.v:1283.5-1283.50"
+ attribute \src "ls180.v:1279.5-1279.50"
wire $1\main_sdphy_dataw_crcr_buf_source_valid[0:0]
- attribute \src "ls180.v:1270.11-1270.55"
+ attribute \src "ls180.v:1266.11-1266.55"
wire width 3 $1\main_sdphy_dataw_crcr_converter_demux[2:0]
- attribute \src "ls180.v:1266.5-1266.56"
+ attribute \src "ls180.v:1262.5-1262.56"
wire $1\main_sdphy_dataw_crcr_converter_source_first[0:0]
- attribute \src "ls180.v:1267.5-1267.55"
+ attribute \src "ls180.v:1263.5-1263.55"
wire $1\main_sdphy_dataw_crcr_converter_source_last[0:0]
- attribute \src "ls180.v:1268.11-1268.69"
+ attribute \src "ls180.v:1264.11-1264.69"
wire width 8 $1\main_sdphy_dataw_crcr_converter_source_payload_data[7:0]
- attribute \src "ls180.v:1269.11-1269.82"
+ attribute \src "ls180.v:1265.11-1265.82"
wire width 4 $1\main_sdphy_dataw_crcr_converter_source_payload_valid_token_count[3:0]
- attribute \src "ls180.v:1272.5-1272.54"
+ attribute \src "ls180.v:1268.5-1268.54"
wire $1\main_sdphy_dataw_crcr_converter_strobe_all[0:0]
- attribute \src "ls180.v:1288.5-1288.39"
+ attribute \src "ls180.v:1284.5-1284.39"
wire $1\main_sdphy_dataw_crcr_reset[0:0]
- attribute \src "ls180.v:1809.5-1809.66"
+ attribute \src "ls180.v:1805.5-1805.66"
wire $1\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0]
- attribute \src "ls180.v:1810.5-1810.69"
+ attribute \src "ls180.v:1806.5-1806.69"
wire $1\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0]
- attribute \src "ls180.v:1258.5-1258.37"
+ attribute \src "ls180.v:1254.5-1254.37"
wire $1\main_sdphy_dataw_crcr_run[0:0]
- attribute \src "ls180.v:1253.5-1253.54"
+ attribute \src "ls180.v:1249.5-1249.54"
wire $1\main_sdphy_dataw_crcr_source_source_ready0[0:0]
- attribute \src "ls180.v:1240.5-1240.34"
+ attribute \src "ls180.v:1236.5-1236.34"
wire $1\main_sdphy_dataw_error[0:0]
- attribute \src "ls180.v:1215.5-1215.49"
+ attribute \src "ls180.v:1211.5-1211.49"
wire $1\main_sdphy_dataw_pads_out_payload_clk[0:0]
- attribute \src "ls180.v:1218.11-1218.58"
+ attribute \src "ls180.v:1214.11-1214.58"
wire width 4 $1\main_sdphy_dataw_pads_out_payload_data_o[3:0]
- attribute \src "ls180.v:1219.5-1219.53"
+ attribute \src "ls180.v:1215.5-1215.53"
wire $1\main_sdphy_dataw_pads_out_payload_data_oe[0:0]
- attribute \src "ls180.v:1222.5-1222.39"
+ attribute \src "ls180.v:1218.5-1218.39"
wire $1\main_sdphy_dataw_sink_first[0:0]
- attribute \src "ls180.v:1223.5-1223.38"
+ attribute \src "ls180.v:1219.5-1219.38"
wire $1\main_sdphy_dataw_sink_last[0:0]
- attribute \src "ls180.v:1224.11-1224.52"
+ attribute \src "ls180.v:1220.11-1220.52"
wire width 8 $1\main_sdphy_dataw_sink_payload_data[7:0]
- attribute \src "ls180.v:1221.5-1221.39"
+ attribute \src "ls180.v:1217.5-1217.39"
wire $1\main_sdphy_dataw_sink_ready[0:0]
- attribute \src "ls180.v:1220.5-1220.39"
+ attribute \src "ls180.v:1216.5-1216.39"
wire $1\main_sdphy_dataw_sink_valid[0:0]
- attribute \src "ls180.v:1238.5-1238.34"
+ attribute \src "ls180.v:1234.5-1234.34"
wire $1\main_sdphy_dataw_start[0:0]
- attribute \src "ls180.v:1225.5-1225.33"
+ attribute \src "ls180.v:1221.5-1221.33"
wire $1\main_sdphy_dataw_stop[0:0]
- attribute \src "ls180.v:1239.5-1239.34"
+ attribute \src "ls180.v:1235.5-1235.34"
wire $1\main_sdphy_dataw_valid[0:0]
- attribute \src "ls180.v:1119.11-1119.39"
+ attribute \src "ls180.v:1115.11-1115.39"
wire width 8 $1\main_sdphy_init_count[7:0]
- attribute \src "ls180.v:1793.11-1793.66"
+ attribute \src "ls180.v:1789.11-1789.66"
wire width 8 $1\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0]
- attribute \src "ls180.v:1794.5-1794.63"
+ attribute \src "ls180.v:1790.5-1790.63"
wire $1\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0]
- attribute \src "ls180.v:1114.5-1114.48"
+ attribute \src "ls180.v:1110.5-1110.48"
wire $1\main_sdphy_init_pads_out_payload_clk[0:0]
- attribute \src "ls180.v:1115.5-1115.50"
+ attribute \src "ls180.v:1111.5-1111.50"
wire $1\main_sdphy_init_pads_out_payload_cmd_o[0:0]
- attribute \src "ls180.v:1116.5-1116.51"
+ attribute \src "ls180.v:1112.5-1112.51"
wire $1\main_sdphy_init_pads_out_payload_cmd_oe[0:0]
- attribute \src "ls180.v:1117.11-1117.57"
+ attribute \src "ls180.v:1113.11-1113.57"
wire width 4 $1\main_sdphy_init_pads_out_payload_data_o[3:0]
- attribute \src "ls180.v:1118.5-1118.52"
+ attribute \src "ls180.v:1114.5-1114.52"
wire $1\main_sdphy_init_pads_out_payload_data_oe[0:0]
- attribute \src "ls180.v:1368.5-1368.35"
+ attribute \src "ls180.v:1364.5-1364.35"
wire $1\main_sdphy_sdpads_cmd_i[0:0]
- attribute \src "ls180.v:1371.11-1371.42"
+ attribute \src "ls180.v:1367.11-1367.42"
wire width 4 $1\main_sdphy_sdpads_data_i[3:0]
- attribute \src "ls180.v:331.5-331.33"
+ attribute \src "ls180.v:327.5-327.33"
wire $1\main_sdram_address_re[0:0]
- attribute \src "ls180.v:330.12-330.46"
+ attribute \src "ls180.v:326.12-326.46"
wire width 13 $1\main_sdram_address_storage[12:0]
- attribute \src "ls180.v:333.5-333.34"
+ attribute \src "ls180.v:329.5-329.34"
wire $1\main_sdram_baddress_re[0:0]
- attribute \src "ls180.v:332.11-332.45"
+ attribute \src "ls180.v:328.11-328.45"
wire width 2 $1\main_sdram_baddress_storage[1:0]
- attribute \src "ls180.v:429.5-429.50"
+ attribute \src "ls180.v:425.5-425.50"
wire $1\main_sdram_bankmachine0_auto_precharge[0:0]
- attribute \src "ls180.v:451.11-451.70"
+ attribute \src "ls180.v:447.11-447.70"
wire width 3 $1\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0]
- attribute \src "ls180.v:448.11-448.68"
+ attribute \src "ls180.v:444.11-444.68"
wire width 4 $1\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0]
- attribute \src "ls180.v:450.11-450.70"
+ attribute \src "ls180.v:446.11-446.70"
wire width 3 $1\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0]
- attribute \src "ls180.v:452.11-452.73"
+ attribute \src "ls180.v:448.11-448.73"
wire width 3 $1\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0]
- attribute \src "ls180.v:475.5-475.59"
+ attribute \src "ls180.v:471.5-471.59"
wire $1\main_sdram_bankmachine0_cmd_buffer_source_first[0:0]
- attribute \src "ls180.v:476.5-476.58"
+ attribute \src "ls180.v:472.5-472.58"
wire $1\main_sdram_bankmachine0_cmd_buffer_source_last[0:0]
- attribute \src "ls180.v:478.12-478.74"
+ attribute \src "ls180.v:474.12-474.74"
wire width 22 $1\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0]
- attribute \src "ls180.v:477.5-477.64"
+ attribute \src "ls180.v:473.5-473.64"
wire $1\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0]
- attribute \src "ls180.v:473.5-473.59"
+ attribute \src "ls180.v:469.5-469.59"
wire $1\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0]
- attribute \src "ls180.v:421.12-421.57"
+ attribute \src "ls180.v:417.12-417.57"
wire width 13 $1\main_sdram_bankmachine0_cmd_payload_a[12:0]
- attribute \src "ls180.v:423.5-423.51"
+ attribute \src "ls180.v:419.5-419.51"
wire $1\main_sdram_bankmachine0_cmd_payload_cas[0:0]
- attribute \src "ls180.v:426.5-426.54"
+ attribute \src "ls180.v:422.5-422.54"
wire $1\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0]
- attribute \src "ls180.v:427.5-427.55"
+ attribute \src "ls180.v:423.5-423.55"
wire $1\main_sdram_bankmachine0_cmd_payload_is_read[0:0]
- attribute \src "ls180.v:428.5-428.56"
+ attribute \src "ls180.v:424.5-424.56"
wire $1\main_sdram_bankmachine0_cmd_payload_is_write[0:0]
- attribute \src "ls180.v:424.5-424.51"
+ attribute \src "ls180.v:420.5-420.51"
wire $1\main_sdram_bankmachine0_cmd_payload_ras[0:0]
- attribute \src "ls180.v:425.5-425.50"
+ attribute \src "ls180.v:421.5-421.50"
wire $1\main_sdram_bankmachine0_cmd_payload_we[0:0]
- attribute \src "ls180.v:420.5-420.45"
+ attribute \src "ls180.v:416.5-416.45"
wire $1\main_sdram_bankmachine0_cmd_ready[0:0]
- attribute \src "ls180.v:419.5-419.45"
+ attribute \src "ls180.v:415.5-415.45"
wire $1\main_sdram_bankmachine0_cmd_valid[0:0]
- attribute \src "ls180.v:418.5-418.47"
+ attribute \src "ls180.v:414.5-414.47"
wire $1\main_sdram_bankmachine0_refresh_gnt[0:0]
- attribute \src "ls180.v:416.5-416.51"
+ attribute \src "ls180.v:412.5-412.51"
wire $1\main_sdram_bankmachine0_req_rdata_valid[0:0]
- attribute \src "ls180.v:415.5-415.51"
+ attribute \src "ls180.v:411.5-411.51"
wire $1\main_sdram_bankmachine0_req_wdata_ready[0:0]
- attribute \src "ls180.v:479.12-479.47"
+ attribute \src "ls180.v:475.12-475.47"
wire width 13 $1\main_sdram_bankmachine0_row[12:0]
- attribute \src "ls180.v:483.5-483.45"
+ attribute \src "ls180.v:479.5-479.45"
wire $1\main_sdram_bankmachine0_row_close[0:0]
- attribute \src "ls180.v:484.5-484.54"
+ attribute \src "ls180.v:480.5-480.54"
wire $1\main_sdram_bankmachine0_row_col_n_addr_sel[0:0]
- attribute \src "ls180.v:482.5-482.44"
+ attribute \src "ls180.v:478.5-478.44"
wire $1\main_sdram_bankmachine0_row_open[0:0]
- attribute \src "ls180.v:480.5-480.46"
+ attribute \src "ls180.v:476.5-476.46"
wire $1\main_sdram_bankmachine0_row_opened[0:0]
- attribute \src "ls180.v:487.11-487.55"
+ attribute \src "ls180.v:483.11-483.55"
wire width 3 $1\main_sdram_bankmachine0_twtpcon_count[2:0]
- attribute \src "ls180.v:486.32-486.76"
+ attribute \src "ls180.v:482.32-482.76"
wire $1\main_sdram_bankmachine0_twtpcon_ready[0:0]
- attribute \src "ls180.v:511.5-511.50"
+ attribute \src "ls180.v:507.5-507.50"
wire $1\main_sdram_bankmachine1_auto_precharge[0:0]
- attribute \src "ls180.v:533.11-533.70"
+ attribute \src "ls180.v:529.11-529.70"
wire width 3 $1\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0]
- attribute \src "ls180.v:530.11-530.68"
+ attribute \src "ls180.v:526.11-526.68"
wire width 4 $1\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0]
- attribute \src "ls180.v:532.11-532.70"
+ attribute \src "ls180.v:528.11-528.70"
wire width 3 $1\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0]
- attribute \src "ls180.v:534.11-534.73"
+ attribute \src "ls180.v:530.11-530.73"
wire width 3 $1\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0]
- attribute \src "ls180.v:557.5-557.59"
+ attribute \src "ls180.v:553.5-553.59"
wire $1\main_sdram_bankmachine1_cmd_buffer_source_first[0:0]
- attribute \src "ls180.v:558.5-558.58"
+ attribute \src "ls180.v:554.5-554.58"
wire $1\main_sdram_bankmachine1_cmd_buffer_source_last[0:0]
- attribute \src "ls180.v:560.12-560.74"
+ attribute \src "ls180.v:556.12-556.74"
wire width 22 $1\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0]
- attribute \src "ls180.v:559.5-559.64"
+ attribute \src "ls180.v:555.5-555.64"
wire $1\main_sdram_bankmachine1_cmd_buffer_source_payload_we[0:0]
- attribute \src "ls180.v:555.5-555.59"
+ attribute \src "ls180.v:551.5-551.59"
wire $1\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0]
- attribute \src "ls180.v:503.12-503.57"
+ attribute \src "ls180.v:499.12-499.57"
wire width 13 $1\main_sdram_bankmachine1_cmd_payload_a[12:0]
- attribute \src "ls180.v:505.5-505.51"
+ attribute \src "ls180.v:501.5-501.51"
wire $1\main_sdram_bankmachine1_cmd_payload_cas[0:0]
- attribute \src "ls180.v:508.5-508.54"
+ attribute \src "ls180.v:504.5-504.54"
wire $1\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0]
- attribute \src "ls180.v:509.5-509.55"
+ attribute \src "ls180.v:505.5-505.55"
wire $1\main_sdram_bankmachine1_cmd_payload_is_read[0:0]
- attribute \src "ls180.v:510.5-510.56"
+ attribute \src "ls180.v:506.5-506.56"
wire $1\main_sdram_bankmachine1_cmd_payload_is_write[0:0]
- attribute \src "ls180.v:506.5-506.51"
+ attribute \src "ls180.v:502.5-502.51"
wire $1\main_sdram_bankmachine1_cmd_payload_ras[0:0]
- attribute \src "ls180.v:507.5-507.50"
+ attribute \src "ls180.v:503.5-503.50"
wire $1\main_sdram_bankmachine1_cmd_payload_we[0:0]
- attribute \src "ls180.v:502.5-502.45"
+ attribute \src "ls180.v:498.5-498.45"
wire $1\main_sdram_bankmachine1_cmd_ready[0:0]
- attribute \src "ls180.v:501.5-501.45"
+ attribute \src "ls180.v:497.5-497.45"
wire $1\main_sdram_bankmachine1_cmd_valid[0:0]
- attribute \src "ls180.v:500.5-500.47"
+ attribute \src "ls180.v:496.5-496.47"
wire $1\main_sdram_bankmachine1_refresh_gnt[0:0]
- attribute \src "ls180.v:498.5-498.51"
+ attribute \src "ls180.v:494.5-494.51"
wire $1\main_sdram_bankmachine1_req_rdata_valid[0:0]
- attribute \src "ls180.v:497.5-497.51"
+ attribute \src "ls180.v:493.5-493.51"
wire $1\main_sdram_bankmachine1_req_wdata_ready[0:0]
- attribute \src "ls180.v:561.12-561.47"
+ attribute \src "ls180.v:557.12-557.47"
wire width 13 $1\main_sdram_bankmachine1_row[12:0]
- attribute \src "ls180.v:565.5-565.45"
+ attribute \src "ls180.v:561.5-561.45"
wire $1\main_sdram_bankmachine1_row_close[0:0]
- attribute \src "ls180.v:566.5-566.54"
+ attribute \src "ls180.v:562.5-562.54"
wire $1\main_sdram_bankmachine1_row_col_n_addr_sel[0:0]
- attribute \src "ls180.v:564.5-564.44"
+ attribute \src "ls180.v:560.5-560.44"
wire $1\main_sdram_bankmachine1_row_open[0:0]
- attribute \src "ls180.v:562.5-562.46"
+ attribute \src "ls180.v:558.5-558.46"
wire $1\main_sdram_bankmachine1_row_opened[0:0]
- attribute \src "ls180.v:569.11-569.55"
+ attribute \src "ls180.v:565.11-565.55"
wire width 3 $1\main_sdram_bankmachine1_twtpcon_count[2:0]
- attribute \src "ls180.v:568.32-568.76"
+ attribute \src "ls180.v:564.32-564.76"
wire $1\main_sdram_bankmachine1_twtpcon_ready[0:0]
- attribute \src "ls180.v:593.5-593.50"
+ attribute \src "ls180.v:589.5-589.50"
wire $1\main_sdram_bankmachine2_auto_precharge[0:0]
- attribute \src "ls180.v:615.11-615.70"
+ attribute \src "ls180.v:611.11-611.70"
wire width 3 $1\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0]
- attribute \src "ls180.v:612.11-612.68"
+ attribute \src "ls180.v:608.11-608.68"
wire width 4 $1\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0]
- attribute \src "ls180.v:614.11-614.70"
+ attribute \src "ls180.v:610.11-610.70"
wire width 3 $1\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0]
- attribute \src "ls180.v:616.11-616.73"
+ attribute \src "ls180.v:612.11-612.73"
wire width 3 $1\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0]
- attribute \src "ls180.v:639.5-639.59"
+ attribute \src "ls180.v:635.5-635.59"
wire $1\main_sdram_bankmachine2_cmd_buffer_source_first[0:0]
- attribute \src "ls180.v:640.5-640.58"
+ attribute \src "ls180.v:636.5-636.58"
wire $1\main_sdram_bankmachine2_cmd_buffer_source_last[0:0]
- attribute \src "ls180.v:642.12-642.74"
+ attribute \src "ls180.v:638.12-638.74"
wire width 22 $1\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0]
- attribute \src "ls180.v:641.5-641.64"
+ attribute \src "ls180.v:637.5-637.64"
wire $1\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0]
- attribute \src "ls180.v:637.5-637.59"
+ attribute \src "ls180.v:633.5-633.59"
wire $1\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0]
- attribute \src "ls180.v:585.12-585.57"
+ attribute \src "ls180.v:581.12-581.57"
wire width 13 $1\main_sdram_bankmachine2_cmd_payload_a[12:0]
- attribute \src "ls180.v:587.5-587.51"
+ attribute \src "ls180.v:583.5-583.51"
wire $1\main_sdram_bankmachine2_cmd_payload_cas[0:0]
- attribute \src "ls180.v:590.5-590.54"
+ attribute \src "ls180.v:586.5-586.54"
wire $1\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0]
- attribute \src "ls180.v:591.5-591.55"
+ attribute \src "ls180.v:587.5-587.55"
wire $1\main_sdram_bankmachine2_cmd_payload_is_read[0:0]
- attribute \src "ls180.v:592.5-592.56"
+ attribute \src "ls180.v:588.5-588.56"
wire $1\main_sdram_bankmachine2_cmd_payload_is_write[0:0]
- attribute \src "ls180.v:588.5-588.51"
+ attribute \src "ls180.v:584.5-584.51"
wire $1\main_sdram_bankmachine2_cmd_payload_ras[0:0]
- attribute \src "ls180.v:589.5-589.50"
+ attribute \src "ls180.v:585.5-585.50"
wire $1\main_sdram_bankmachine2_cmd_payload_we[0:0]
- attribute \src "ls180.v:584.5-584.45"
+ attribute \src "ls180.v:580.5-580.45"
wire $1\main_sdram_bankmachine2_cmd_ready[0:0]
- attribute \src "ls180.v:583.5-583.45"
+ attribute \src "ls180.v:579.5-579.45"
wire $1\main_sdram_bankmachine2_cmd_valid[0:0]
- attribute \src "ls180.v:582.5-582.47"
+ attribute \src "ls180.v:578.5-578.47"
wire $1\main_sdram_bankmachine2_refresh_gnt[0:0]
- attribute \src "ls180.v:580.5-580.51"
+ attribute \src "ls180.v:576.5-576.51"
wire $1\main_sdram_bankmachine2_req_rdata_valid[0:0]
- attribute \src "ls180.v:579.5-579.51"
+ attribute \src "ls180.v:575.5-575.51"
wire $1\main_sdram_bankmachine2_req_wdata_ready[0:0]
- attribute \src "ls180.v:643.12-643.47"
+ attribute \src "ls180.v:639.12-639.47"
wire width 13 $1\main_sdram_bankmachine2_row[12:0]
- attribute \src "ls180.v:647.5-647.45"
+ attribute \src "ls180.v:643.5-643.45"
wire $1\main_sdram_bankmachine2_row_close[0:0]
- attribute \src "ls180.v:648.5-648.54"
+ attribute \src "ls180.v:644.5-644.54"
wire $1\main_sdram_bankmachine2_row_col_n_addr_sel[0:0]
- attribute \src "ls180.v:646.5-646.44"
+ attribute \src "ls180.v:642.5-642.44"
wire $1\main_sdram_bankmachine2_row_open[0:0]
- attribute \src "ls180.v:644.5-644.46"
+ attribute \src "ls180.v:640.5-640.46"
wire $1\main_sdram_bankmachine2_row_opened[0:0]
- attribute \src "ls180.v:651.11-651.55"
+ attribute \src "ls180.v:647.11-647.55"
wire width 3 $1\main_sdram_bankmachine2_twtpcon_count[2:0]
- attribute \src "ls180.v:650.32-650.76"
+ attribute \src "ls180.v:646.32-646.76"
wire $1\main_sdram_bankmachine2_twtpcon_ready[0:0]
- attribute \src "ls180.v:675.5-675.50"
+ attribute \src "ls180.v:671.5-671.50"
wire $1\main_sdram_bankmachine3_auto_precharge[0:0]
- attribute \src "ls180.v:697.11-697.70"
+ attribute \src "ls180.v:693.11-693.70"
wire width 3 $1\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0]
- attribute \src "ls180.v:694.11-694.68"
+ attribute \src "ls180.v:690.11-690.68"
wire width 4 $1\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0]
- attribute \src "ls180.v:696.11-696.70"
+ attribute \src "ls180.v:692.11-692.70"
wire width 3 $1\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0]
- attribute \src "ls180.v:698.11-698.73"
+ attribute \src "ls180.v:694.11-694.73"
wire width 3 $1\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0]
- attribute \src "ls180.v:721.5-721.59"
+ attribute \src "ls180.v:717.5-717.59"
wire $1\main_sdram_bankmachine3_cmd_buffer_source_first[0:0]
- attribute \src "ls180.v:722.5-722.58"
+ attribute \src "ls180.v:718.5-718.58"
wire $1\main_sdram_bankmachine3_cmd_buffer_source_last[0:0]
- attribute \src "ls180.v:724.12-724.74"
+ attribute \src "ls180.v:720.12-720.74"
wire width 22 $1\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0]
- attribute \src "ls180.v:723.5-723.64"
+ attribute \src "ls180.v:719.5-719.64"
wire $1\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0]
- attribute \src "ls180.v:719.5-719.59"
+ attribute \src "ls180.v:715.5-715.59"
wire $1\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0]
- attribute \src "ls180.v:667.12-667.57"
+ attribute \src "ls180.v:663.12-663.57"
wire width 13 $1\main_sdram_bankmachine3_cmd_payload_a[12:0]
- attribute \src "ls180.v:669.5-669.51"
+ attribute \src "ls180.v:665.5-665.51"
wire $1\main_sdram_bankmachine3_cmd_payload_cas[0:0]
- attribute \src "ls180.v:672.5-672.54"
+ attribute \src "ls180.v:668.5-668.54"
wire $1\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0]
- attribute \src "ls180.v:673.5-673.55"
+ attribute \src "ls180.v:669.5-669.55"
wire $1\main_sdram_bankmachine3_cmd_payload_is_read[0:0]
- attribute \src "ls180.v:674.5-674.56"
+ attribute \src "ls180.v:670.5-670.56"
wire $1\main_sdram_bankmachine3_cmd_payload_is_write[0:0]
- attribute \src "ls180.v:670.5-670.51"
+ attribute \src "ls180.v:666.5-666.51"
wire $1\main_sdram_bankmachine3_cmd_payload_ras[0:0]
- attribute \src "ls180.v:671.5-671.50"
+ attribute \src "ls180.v:667.5-667.50"
wire $1\main_sdram_bankmachine3_cmd_payload_we[0:0]
- attribute \src "ls180.v:666.5-666.45"
+ attribute \src "ls180.v:662.5-662.45"
wire $1\main_sdram_bankmachine3_cmd_ready[0:0]
- attribute \src "ls180.v:665.5-665.45"
+ attribute \src "ls180.v:661.5-661.45"
wire $1\main_sdram_bankmachine3_cmd_valid[0:0]
- attribute \src "ls180.v:664.5-664.47"
+ attribute \src "ls180.v:660.5-660.47"
wire $1\main_sdram_bankmachine3_refresh_gnt[0:0]
- attribute \src "ls180.v:662.5-662.51"
+ attribute \src "ls180.v:658.5-658.51"
wire $1\main_sdram_bankmachine3_req_rdata_valid[0:0]
- attribute \src "ls180.v:661.5-661.51"
+ attribute \src "ls180.v:657.5-657.51"
wire $1\main_sdram_bankmachine3_req_wdata_ready[0:0]
- attribute \src "ls180.v:725.12-725.47"
+ attribute \src "ls180.v:721.12-721.47"
wire width 13 $1\main_sdram_bankmachine3_row[12:0]
- attribute \src "ls180.v:729.5-729.45"
+ attribute \src "ls180.v:725.5-725.45"
wire $1\main_sdram_bankmachine3_row_close[0:0]
- attribute \src "ls180.v:730.5-730.54"
+ attribute \src "ls180.v:726.5-726.54"
wire $1\main_sdram_bankmachine3_row_col_n_addr_sel[0:0]
- attribute \src "ls180.v:728.5-728.44"
+ attribute \src "ls180.v:724.5-724.44"
wire $1\main_sdram_bankmachine3_row_open[0:0]
- attribute \src "ls180.v:726.5-726.46"
+ attribute \src "ls180.v:722.5-722.46"
wire $1\main_sdram_bankmachine3_row_opened[0:0]
- attribute \src "ls180.v:733.11-733.55"
+ attribute \src "ls180.v:729.11-729.55"
wire width 3 $1\main_sdram_bankmachine3_twtpcon_count[2:0]
- attribute \src "ls180.v:732.32-732.76"
+ attribute \src "ls180.v:728.32-728.76"
wire $1\main_sdram_bankmachine3_twtpcon_ready[0:0]
- attribute \src "ls180.v:748.5-748.49"
+ attribute \src "ls180.v:744.5-744.49"
wire $1\main_sdram_choose_cmd_cmd_payload_cas[0:0]
- attribute \src "ls180.v:749.5-749.49"
+ attribute \src "ls180.v:745.5-745.49"
wire $1\main_sdram_choose_cmd_cmd_payload_ras[0:0]
- attribute \src "ls180.v:750.5-750.48"
+ attribute \src "ls180.v:746.5-746.48"
wire $1\main_sdram_choose_cmd_cmd_payload_we[0:0]
- attribute \src "ls180.v:756.11-756.45"
+ attribute \src "ls180.v:752.11-752.45"
wire width 2 $1\main_sdram_choose_cmd_grant[1:0]
- attribute \src "ls180.v:754.11-754.46"
+ attribute \src "ls180.v:750.11-750.46"
wire width 4 $1\main_sdram_choose_cmd_valids[3:0]
- attribute \src "ls180.v:766.5-766.49"
+ attribute \src "ls180.v:762.5-762.49"
wire $1\main_sdram_choose_req_cmd_payload_cas[0:0]
- attribute \src "ls180.v:767.5-767.49"
+ attribute \src "ls180.v:763.5-763.49"
wire $1\main_sdram_choose_req_cmd_payload_ras[0:0]
- attribute \src "ls180.v:768.5-768.48"
+ attribute \src "ls180.v:764.5-764.48"
wire $1\main_sdram_choose_req_cmd_payload_we[0:0]
- attribute \src "ls180.v:763.5-763.43"
+ attribute \src "ls180.v:759.5-759.43"
wire $1\main_sdram_choose_req_cmd_ready[0:0]
- attribute \src "ls180.v:774.11-774.45"
+ attribute \src "ls180.v:770.11-770.45"
wire width 2 $1\main_sdram_choose_req_grant[1:0]
- attribute \src "ls180.v:772.11-772.46"
+ attribute \src "ls180.v:768.11-768.46"
wire width 4 $1\main_sdram_choose_req_valids[3:0]
- attribute \src "ls180.v:761.5-761.48"
+ attribute \src "ls180.v:757.5-757.48"
wire $1\main_sdram_choose_req_want_activates[0:0]
- attribute \src "ls180.v:758.5-758.44"
+ attribute \src "ls180.v:754.5-754.44"
wire $1\main_sdram_choose_req_want_reads[0:0]
- attribute \src "ls180.v:759.5-759.45"
+ attribute \src "ls180.v:755.5-755.45"
wire $1\main_sdram_choose_req_want_writes[0:0]
- attribute \src "ls180.v:387.5-387.31"
+ attribute \src "ls180.v:383.5-383.31"
wire $1\main_sdram_cmd_last[0:0]
- attribute \src "ls180.v:388.12-388.44"
+ attribute \src "ls180.v:384.12-384.44"
wire width 13 $1\main_sdram_cmd_payload_a[12:0]
- attribute \src "ls180.v:389.11-389.43"
+ attribute \src "ls180.v:385.11-385.43"
wire width 2 $1\main_sdram_cmd_payload_ba[1:0]
- attribute \src "ls180.v:390.5-390.38"
+ attribute \src "ls180.v:386.5-386.38"
wire $1\main_sdram_cmd_payload_cas[0:0]
- attribute \src "ls180.v:391.5-391.38"
+ attribute \src "ls180.v:387.5-387.38"
wire $1\main_sdram_cmd_payload_ras[0:0]
- attribute \src "ls180.v:392.5-392.37"
+ attribute \src "ls180.v:388.5-388.37"
wire $1\main_sdram_cmd_payload_we[0:0]
- attribute \src "ls180.v:386.5-386.32"
+ attribute \src "ls180.v:382.5-382.32"
wire $1\main_sdram_cmd_ready[0:0]
- attribute \src "ls180.v:385.5-385.32"
+ attribute \src "ls180.v:381.5-381.32"
wire $1\main_sdram_cmd_valid[0:0]
- attribute \src "ls180.v:325.5-325.33"
+ attribute \src "ls180.v:321.5-321.33"
wire $1\main_sdram_command_re[0:0]
- attribute \src "ls180.v:324.11-324.44"
+ attribute \src "ls180.v:320.11-320.44"
wire width 6 $1\main_sdram_command_storage[5:0]
- attribute \src "ls180.v:369.12-369.45"
+ attribute \src "ls180.v:365.12-365.45"
wire width 13 $1\main_sdram_dfi_p0_address[12:0]
- attribute \src "ls180.v:370.11-370.40"
+ attribute \src "ls180.v:366.11-366.40"
wire width 2 $1\main_sdram_dfi_p0_bank[1:0]
- attribute \src "ls180.v:371.5-371.35"
+ attribute \src "ls180.v:367.5-367.35"
wire $1\main_sdram_dfi_p0_cas_n[0:0]
- attribute \src "ls180.v:372.5-372.34"
+ attribute \src "ls180.v:368.5-368.34"
wire $1\main_sdram_dfi_p0_cs_n[0:0]
- attribute \src "ls180.v:373.5-373.35"
+ attribute \src "ls180.v:369.5-369.35"
wire $1\main_sdram_dfi_p0_ras_n[0:0]
- attribute \src "ls180.v:382.5-382.39"
+ attribute \src "ls180.v:378.5-378.39"
wire $1\main_sdram_dfi_p0_rddata_en[0:0]
- attribute \src "ls180.v:374.5-374.34"
+ attribute \src "ls180.v:370.5-370.34"
wire $1\main_sdram_dfi_p0_we_n[0:0]
- attribute \src "ls180.v:380.5-380.39"
+ attribute \src "ls180.v:376.5-376.39"
wire $1\main_sdram_dfi_p0_wrdata_en[0:0]
- attribute \src "ls180.v:793.5-793.26"
+ attribute \src "ls180.v:789.5-789.26"
wire $1\main_sdram_en0[0:0]
- attribute \src "ls180.v:796.5-796.26"
+ attribute \src "ls180.v:792.5-792.26"
wire $1\main_sdram_en1[0:0]
- attribute \src "ls180.v:366.12-366.46"
+ attribute \src "ls180.v:362.12-362.46"
wire width 16 $1\main_sdram_interface_wdata[15:0]
- attribute \src "ls180.v:367.11-367.47"
+ attribute \src "ls180.v:363.11-363.47"
wire width 2 $1\main_sdram_interface_wdata_we[1:0]
- attribute \src "ls180.v:272.5-272.36"
+ attribute \src "ls180.v:268.5-268.36"
wire $1\main_sdram_inti_p0_cas_n[0:0]
- attribute \src "ls180.v:273.5-273.35"
+ attribute \src "ls180.v:269.5-269.35"
wire $1\main_sdram_inti_p0_cs_n[0:0]
- attribute \src "ls180.v:274.5-274.36"
+ attribute \src "ls180.v:270.5-270.36"
wire $1\main_sdram_inti_p0_ras_n[0:0]
- attribute \src "ls180.v:284.12-284.45"
+ attribute \src "ls180.v:280.12-280.45"
wire width 16 $1\main_sdram_inti_p0_rddata[15:0]
- attribute \src "ls180.v:285.5-285.43"
+ attribute \src "ls180.v:281.5-281.43"
wire $1\main_sdram_inti_p0_rddata_valid[0:0]
- attribute \src "ls180.v:275.5-275.35"
+ attribute \src "ls180.v:271.5-271.35"
wire $1\main_sdram_inti_p0_we_n[0:0]
- attribute \src "ls180.v:311.5-311.38"
+ attribute \src "ls180.v:307.5-307.38"
wire $1\main_sdram_master_p0_act_n[0:0]
- attribute \src "ls180.v:302.12-302.48"
+ attribute \src "ls180.v:298.12-298.48"
wire width 13 $1\main_sdram_master_p0_address[12:0]
- attribute \src "ls180.v:303.11-303.43"
+ attribute \src "ls180.v:299.11-299.43"
wire width 2 $1\main_sdram_master_p0_bank[1:0]
- attribute \src "ls180.v:304.5-304.38"
+ attribute \src "ls180.v:300.5-300.38"
wire $1\main_sdram_master_p0_cas_n[0:0]
- attribute \src "ls180.v:308.5-308.36"
+ attribute \src "ls180.v:304.5-304.36"
wire $1\main_sdram_master_p0_cke[0:0]
- attribute \src "ls180.v:305.5-305.37"
+ attribute \src "ls180.v:301.5-301.37"
wire $1\main_sdram_master_p0_cs_n[0:0]
- attribute \src "ls180.v:309.5-309.36"
+ attribute \src "ls180.v:305.5-305.36"
wire $1\main_sdram_master_p0_odt[0:0]
- attribute \src "ls180.v:306.5-306.38"
+ attribute \src "ls180.v:302.5-302.38"
wire $1\main_sdram_master_p0_ras_n[0:0]
- attribute \src "ls180.v:315.5-315.42"
+ attribute \src "ls180.v:311.5-311.42"
wire $1\main_sdram_master_p0_rddata_en[0:0]
- attribute \src "ls180.v:310.5-310.40"
+ attribute \src "ls180.v:306.5-306.40"
wire $1\main_sdram_master_p0_reset_n[0:0]
- attribute \src "ls180.v:307.5-307.37"
+ attribute \src "ls180.v:303.5-303.37"
wire $1\main_sdram_master_p0_we_n[0:0]
- attribute \src "ls180.v:312.12-312.47"
+ attribute \src "ls180.v:308.12-308.47"
wire width 16 $1\main_sdram_master_p0_wrdata[15:0]
- attribute \src "ls180.v:313.5-313.42"
+ attribute \src "ls180.v:309.5-309.42"
wire $1\main_sdram_master_p0_wrdata_en[0:0]
- attribute \src "ls180.v:314.11-314.50"
+ attribute \src "ls180.v:310.11-310.50"
wire width 2 $1\main_sdram_master_p0_wrdata_mask[1:0]
- attribute \src "ls180.v:403.5-403.38"
+ attribute \src "ls180.v:399.5-399.38"
wire $1\main_sdram_postponer_count[0:0]
- attribute \src "ls180.v:402.5-402.38"
+ attribute \src "ls180.v:398.5-398.38"
wire $1\main_sdram_postponer_req_o[0:0]
- attribute \src "ls180.v:323.5-323.25"
+ attribute \src "ls180.v:319.5-319.25"
wire $1\main_sdram_re[0:0]
- attribute \src "ls180.v:409.5-409.38"
+ attribute \src "ls180.v:405.5-405.38"
wire $1\main_sdram_sequencer_count[0:0]
- attribute \src "ls180.v:408.11-408.46"
+ attribute \src "ls180.v:404.11-404.46"
wire width 4 $1\main_sdram_sequencer_counter[3:0]
- attribute \src "ls180.v:407.5-407.38"
+ attribute \src "ls180.v:403.5-403.38"
wire $1\main_sdram_sequencer_done1[0:0]
- attribute \src "ls180.v:404.5-404.39"
+ attribute \src "ls180.v:400.5-400.39"
wire $1\main_sdram_sequencer_start0[0:0]
- attribute \src "ls180.v:300.12-300.46"
+ attribute \src "ls180.v:296.12-296.46"
wire width 16 $1\main_sdram_slave_p0_rddata[15:0]
- attribute \src "ls180.v:301.5-301.44"
+ attribute \src "ls180.v:297.5-297.44"
wire $1\main_sdram_slave_p0_rddata_valid[0:0]
- attribute \src "ls180.v:336.12-336.37"
+ attribute \src "ls180.v:332.12-332.37"
wire width 16 $1\main_sdram_status[15:0]
- attribute \src "ls180.v:778.11-778.40"
+ attribute \src "ls180.v:774.11-774.40"
wire width 2 $1\main_sdram_steerer_sel[1:0]
- attribute \src "ls180.v:322.11-322.36"
+ attribute \src "ls180.v:318.11-318.36"
wire width 4 $1\main_sdram_storage[3:0]
- attribute \src "ls180.v:787.5-787.36"
+ attribute \src "ls180.v:783.5-783.36"
wire $1\main_sdram_tccdcon_count[0:0]
- attribute \src "ls180.v:786.32-786.63"
+ attribute \src "ls180.v:782.32-782.63"
wire $1\main_sdram_tccdcon_ready[0:0]
- attribute \src "ls180.v:795.11-795.34"
+ attribute \src "ls180.v:791.11-791.34"
wire width 5 $1\main_sdram_time0[4:0]
- attribute \src "ls180.v:798.11-798.34"
+ attribute \src "ls180.v:794.11-794.34"
wire width 4 $1\main_sdram_time1[3:0]
- attribute \src "ls180.v:400.11-400.44"
+ attribute \src "ls180.v:396.11-396.44"
wire width 10 $1\main_sdram_timer_count1[9:0]
- attribute \src "ls180.v:790.11-790.42"
+ attribute \src "ls180.v:786.11-786.42"
wire width 3 $1\main_sdram_twtrcon_count[2:0]
- attribute \src "ls180.v:789.32-789.63"
+ attribute \src "ls180.v:785.32-785.63"
wire $1\main_sdram_twtrcon_ready[0:0]
- attribute \src "ls180.v:335.5-335.32"
+ attribute \src "ls180.v:331.5-331.32"
wire $1\main_sdram_wrdata_re[0:0]
- attribute \src "ls180.v:334.12-334.45"
+ attribute \src "ls180.v:330.12-330.45"
wire width 16 $1\main_sdram_wrdata_storage[15:0]
- attribute \src "ls180.v:1003.12-1003.44"
+ attribute \src "ls180.v:999.12-999.44"
wire width 16 $1\main_spimaster11_storage[15:0]
- attribute \src "ls180.v:1004.5-1004.31"
+ attribute \src "ls180.v:1000.5-1000.31"
wire $1\main_spimaster12_re[0:0]
- attribute \src "ls180.v:1008.11-1008.42"
+ attribute \src "ls180.v:1004.11-1004.42"
wire width 8 $1\main_spimaster16_storage[7:0]
- attribute \src "ls180.v:1009.5-1009.31"
+ attribute \src "ls180.v:1005.5-1005.31"
wire $1\main_spimaster17_re[0:0]
- attribute \src "ls180.v:1065.5-1065.30"
+ attribute \src "ls180.v:1061.5-1061.30"
wire $1\main_spimaster1_re[0:0]
- attribute \src "ls180.v:1064.12-1064.45"
+ attribute \src "ls180.v:1060.12-1060.45"
wire width 16 $1\main_spimaster1_storage[15:0]
- attribute \src "ls180.v:1013.5-1013.36"
+ attribute \src "ls180.v:1009.5-1009.36"
wire $1\main_spimaster21_storage[0:0]
- attribute \src "ls180.v:1014.5-1014.31"
+ attribute \src "ls180.v:1010.5-1010.31"
wire $1\main_spimaster22_re[0:0]
- attribute \src "ls180.v:1015.5-1015.36"
+ attribute \src "ls180.v:1011.5-1011.36"
wire $1\main_spimaster23_storage[0:0]
- attribute \src "ls180.v:1016.5-1016.31"
+ attribute \src "ls180.v:1012.5-1012.31"
wire $1\main_spimaster24_re[0:0]
- attribute \src "ls180.v:1017.5-1017.39"
+ attribute \src "ls180.v:1013.5-1013.39"
wire $1\main_spimaster25_clk_enable[0:0]
- attribute \src "ls180.v:1018.5-1018.38"
+ attribute \src "ls180.v:1014.5-1014.38"
wire $1\main_spimaster26_cs_enable[0:0]
- attribute \src "ls180.v:1019.11-1019.40"
+ attribute \src "ls180.v:1015.11-1015.40"
wire width 3 $1\main_spimaster27_count[2:0]
- attribute \src "ls180.v:1785.11-1785.62"
+ attribute \src "ls180.v:1781.11-1781.62"
wire width 3 $1\main_spimaster27_count_spimaster0_next_value[2:0]
- attribute \src "ls180.v:1786.5-1786.59"
+ attribute \src "ls180.v:1782.5-1782.59"
wire $1\main_spimaster27_count_spimaster0_next_value_ce[0:0]
- attribute \src "ls180.v:1020.5-1020.39"
+ attribute \src "ls180.v:1016.5-1016.39"
wire $1\main_spimaster28_mosi_latch[0:0]
- attribute \src "ls180.v:1021.5-1021.39"
+ attribute \src "ls180.v:1017.5-1017.39"
wire $1\main_spimaster29_miso_latch[0:0]
- attribute \src "ls180.v:994.5-994.32"
+ attribute \src "ls180.v:990.5-990.32"
wire $1\main_spimaster2_done[0:0]
- attribute \src "ls180.v:1022.12-1022.48"
+ attribute \src "ls180.v:1018.12-1018.48"
wire width 16 $1\main_spimaster30_clk_divider[15:0]
- attribute \src "ls180.v:1025.11-1025.44"
+ attribute \src "ls180.v:1021.11-1021.44"
wire width 8 $1\main_spimaster33_mosi_data[7:0]
- attribute \src "ls180.v:1026.11-1026.43"
+ attribute \src "ls180.v:1022.11-1022.43"
wire width 3 $1\main_spimaster34_mosi_sel[2:0]
- attribute \src "ls180.v:1027.11-1027.44"
+ attribute \src "ls180.v:1023.11-1023.44"
wire width 8 $1\main_spimaster35_miso_data[7:0]
- attribute \src "ls180.v:995.5-995.31"
+ attribute \src "ls180.v:991.5-991.31"
wire $1\main_spimaster3_irq[0:0]
- attribute \src "ls180.v:997.11-997.38"
+ attribute \src "ls180.v:993.11-993.38"
wire width 8 $1\main_spimaster5_miso[7:0]
- attribute \src "ls180.v:1001.5-1001.33"
+ attribute \src "ls180.v:997.5-997.33"
wire $1\main_spimaster9_start[0:0]
- attribute \src "ls180.v:1058.12-1058.47"
+ attribute \src "ls180.v:1054.12-1054.47"
wire width 16 $1\main_spisdcard_clk_divider1[15:0]
- attribute \src "ls180.v:1053.5-1053.37"
+ attribute \src "ls180.v:1049.5-1049.37"
wire $1\main_spisdcard_clk_enable[0:0]
- attribute \src "ls180.v:1040.5-1040.37"
+ attribute \src "ls180.v:1036.5-1036.37"
wire $1\main_spisdcard_control_re[0:0]
- attribute \src "ls180.v:1039.12-1039.50"
+ attribute \src "ls180.v:1035.12-1035.50"
wire width 16 $1\main_spisdcard_control_storage[15:0]
- attribute \src "ls180.v:1055.11-1055.38"
+ attribute \src "ls180.v:1051.11-1051.38"
wire width 3 $1\main_spisdcard_count[2:0]
- attribute \src "ls180.v:1789.11-1789.60"
+ attribute \src "ls180.v:1785.11-1785.60"
wire width 3 $1\main_spisdcard_count_spimaster1_next_value[2:0]
- attribute \src "ls180.v:1790.5-1790.57"
+ attribute \src "ls180.v:1786.5-1786.57"
wire $1\main_spisdcard_count_spimaster1_next_value_ce[0:0]
- attribute \src "ls180.v:1054.5-1054.36"
+ attribute \src "ls180.v:1050.5-1050.36"
wire $1\main_spisdcard_cs_enable[0:0]
- attribute \src "ls180.v:1050.5-1050.32"
+ attribute \src "ls180.v:1046.5-1046.32"
wire $1\main_spisdcard_cs_re[0:0]
- attribute \src "ls180.v:1049.5-1049.37"
+ attribute \src "ls180.v:1045.5-1045.37"
wire $1\main_spisdcard_cs_storage[0:0]
- attribute \src "ls180.v:1030.5-1030.32"
+ attribute \src "ls180.v:1026.5-1026.32"
wire $1\main_spisdcard_done0[0:0]
- attribute \src "ls180.v:1031.5-1031.30"
+ attribute \src "ls180.v:1027.5-1027.30"
wire $1\main_spisdcard_irq[0:0]
- attribute \src "ls180.v:1052.5-1052.38"
+ attribute \src "ls180.v:1048.5-1048.38"
wire $1\main_spisdcard_loopback_re[0:0]
- attribute \src "ls180.v:1051.5-1051.43"
+ attribute \src "ls180.v:1047.5-1047.43"
wire $1\main_spisdcard_loopback_storage[0:0]
- attribute \src "ls180.v:1033.11-1033.37"
+ attribute \src "ls180.v:1029.11-1029.37"
wire width 8 $1\main_spisdcard_miso[7:0]
- attribute \src "ls180.v:1063.11-1063.42"
+ attribute \src "ls180.v:1059.11-1059.42"
wire width 8 $1\main_spisdcard_miso_data[7:0]
- attribute \src "ls180.v:1057.5-1057.37"
+ attribute \src "ls180.v:1053.5-1053.37"
wire $1\main_spisdcard_miso_latch[0:0]
- attribute \src "ls180.v:1061.11-1061.42"
+ attribute \src "ls180.v:1057.11-1057.42"
wire width 8 $1\main_spisdcard_mosi_data[7:0]
- attribute \src "ls180.v:1056.5-1056.37"
+ attribute \src "ls180.v:1052.5-1052.37"
wire $1\main_spisdcard_mosi_latch[0:0]
- attribute \src "ls180.v:1045.5-1045.34"
+ attribute \src "ls180.v:1041.5-1041.34"
wire $1\main_spisdcard_mosi_re[0:0]
- attribute \src "ls180.v:1062.11-1062.41"
+ attribute \src "ls180.v:1058.11-1058.41"
wire width 3 $1\main_spisdcard_mosi_sel[2:0]
- attribute \src "ls180.v:1044.11-1044.45"
+ attribute \src "ls180.v:1040.11-1040.45"
wire width 8 $1\main_spisdcard_mosi_storage[7:0]
- attribute \src "ls180.v:1037.5-1037.33"
+ attribute \src "ls180.v:1033.5-1033.33"
wire $1\main_spisdcard_start1[0:0]
- attribute \src "ls180.v:891.11-891.50"
+ attribute \src "ls180.v:887.11-887.50"
wire width 2 $1\main_uart_eventmanager_pending_w[1:0]
- attribute \src "ls180.v:893.5-893.37"
+ attribute \src "ls180.v:889.5-889.37"
wire $1\main_uart_eventmanager_re[0:0]
- attribute \src "ls180.v:887.11-887.49"
+ attribute \src "ls180.v:883.11-883.49"
wire width 2 $1\main_uart_eventmanager_status_w[1:0]
- attribute \src "ls180.v:892.11-892.48"
+ attribute \src "ls180.v:888.11-888.48"
wire width 2 $1\main_uart_eventmanager_storage[1:0]
- attribute \src "ls180.v:859.12-859.54"
+ attribute \src "ls180.v:855.12-855.54"
wire width 32 $1\main_uart_phy_phase_accumulator_rx[31:0]
- attribute \src "ls180.v:849.12-849.54"
+ attribute \src "ls180.v:845.12-845.54"
wire width 32 $1\main_uart_phy_phase_accumulator_tx[31:0]
- attribute \src "ls180.v:842.5-842.28"
+ attribute \src "ls180.v:838.5-838.28"
wire $1\main_uart_phy_re[0:0]
- attribute \src "ls180.v:863.11-863.43"
+ attribute \src "ls180.v:859.11-859.43"
wire width 4 $1\main_uart_phy_rx_bitcount[3:0]
- attribute \src "ls180.v:864.5-864.33"
+ attribute \src "ls180.v:860.5-860.33"
wire $1\main_uart_phy_rx_busy[0:0]
- attribute \src "ls180.v:861.5-861.30"
+ attribute \src "ls180.v:857.5-857.30"
wire $1\main_uart_phy_rx_r[0:0]
- attribute \src "ls180.v:862.11-862.38"
+ attribute \src "ls180.v:858.11-858.38"
wire width 8 $1\main_uart_phy_rx_reg[7:0]
- attribute \src "ls180.v:844.5-844.36"
+ attribute \src "ls180.v:840.5-840.36"
wire $1\main_uart_phy_sink_ready[0:0]
- attribute \src "ls180.v:857.11-857.51"
+ attribute \src "ls180.v:853.11-853.51"
wire width 8 $1\main_uart_phy_source_payload_data[7:0]
- attribute \src "ls180.v:853.5-853.38"
+ attribute \src "ls180.v:849.5-849.38"
wire $1\main_uart_phy_source_valid[0:0]
- attribute \src "ls180.v:841.12-841.47"
+ attribute \src "ls180.v:837.12-837.47"
wire width 32 $1\main_uart_phy_storage[31:0]
- attribute \src "ls180.v:851.11-851.43"
+ attribute \src "ls180.v:847.11-847.43"
wire width 4 $1\main_uart_phy_tx_bitcount[3:0]
- attribute \src "ls180.v:852.5-852.33"
+ attribute \src "ls180.v:848.5-848.33"
wire $1\main_uart_phy_tx_busy[0:0]
- attribute \src "ls180.v:850.11-850.38"
+ attribute \src "ls180.v:846.11-846.38"
wire width 8 $1\main_uart_phy_tx_reg[7:0]
- attribute \src "ls180.v:858.5-858.39"
+ attribute \src "ls180.v:854.5-854.39"
wire $1\main_uart_phy_uart_clk_rxen[0:0]
- attribute \src "ls180.v:848.5-848.39"
+ attribute \src "ls180.v:844.5-844.39"
wire $1\main_uart_phy_uart_clk_txen[0:0]
- attribute \src "ls180.v:882.5-882.30"
+ attribute \src "ls180.v:878.5-878.30"
wire $1\main_uart_rx_clear[0:0]
- attribute \src "ls180.v:966.11-966.43"
+ attribute \src "ls180.v:962.11-962.43"
wire width 4 $1\main_uart_rx_fifo_consume[3:0]
- attribute \src "ls180.v:963.11-963.42"
+ attribute \src "ls180.v:959.11-959.42"
wire width 5 $1\main_uart_rx_fifo_level0[4:0]
- attribute \src "ls180.v:965.11-965.43"
+ attribute \src "ls180.v:961.11-961.43"
wire width 4 $1\main_uart_rx_fifo_produce[3:0]
- attribute \src "ls180.v:956.5-956.38"
+ attribute \src "ls180.v:952.5-952.38"
wire $1\main_uart_rx_fifo_readable[0:0]
- attribute \src "ls180.v:967.11-967.46"
+ attribute \src "ls180.v:963.11-963.46"
wire width 4 $1\main_uart_rx_fifo_wrport_adr[3:0]
- attribute \src "ls180.v:883.5-883.36"
+ attribute \src "ls180.v:879.5-879.36"
wire $1\main_uart_rx_old_trigger[0:0]
- attribute \src "ls180.v:880.5-880.32"
+ attribute \src "ls180.v:876.5-876.32"
wire $1\main_uart_rx_pending[0:0]
- attribute \src "ls180.v:877.5-877.30"
+ attribute \src "ls180.v:873.5-873.30"
wire $1\main_uart_tx_clear[0:0]
- attribute \src "ls180.v:929.11-929.43"
+ attribute \src "ls180.v:925.11-925.43"
wire width 4 $1\main_uart_tx_fifo_consume[3:0]
- attribute \src "ls180.v:926.11-926.42"
+ attribute \src "ls180.v:922.11-922.42"
wire width 5 $1\main_uart_tx_fifo_level0[4:0]
- attribute \src "ls180.v:928.11-928.43"
+ attribute \src "ls180.v:924.11-924.43"
wire width 4 $1\main_uart_tx_fifo_produce[3:0]
- attribute \src "ls180.v:919.5-919.38"
+ attribute \src "ls180.v:915.5-915.38"
wire $1\main_uart_tx_fifo_readable[0:0]
- attribute \src "ls180.v:930.11-930.46"
+ attribute \src "ls180.v:926.11-926.46"
wire width 4 $1\main_uart_tx_fifo_wrport_adr[3:0]
- attribute \src "ls180.v:878.5-878.36"
+ attribute \src "ls180.v:874.5-874.36"
wire $1\main_uart_tx_old_trigger[0:0]
- attribute \src "ls180.v:875.5-875.32"
+ attribute \src "ls180.v:871.5-871.32"
wire $1\main_uart_tx_pending[0:0]
- attribute \src "ls180.v:819.5-819.29"
+ attribute \src "ls180.v:815.5-815.29"
wire $1\main_wb_sdram_ack[0:0]
- attribute \src "ls180.v:837.5-837.31"
+ attribute \src "ls180.v:833.5-833.31"
wire $1\main_wdata_consumed[0:0]
- attribute \src "ls180.v:2819.68-2819.110"
- wire $add$ls180.v:2819$22_Y
- attribute \src "ls180.v:2879.68-2879.110"
- wire $add$ls180.v:2879$33_Y
- attribute \src "ls180.v:2939.68-2939.110"
- wire $add$ls180.v:2939$44_Y
- attribute \src "ls180.v:4072.54-4072.83"
- wire $add$ls180.v:4072$537_Y
- attribute \src "ls180.v:4172.36-4172.89"
- wire width 5 $add$ls180.v:4172$583_Y
- attribute \src "ls180.v:4202.36-4202.89"
- wire width 5 $add$ls180.v:4202$594_Y
- attribute \src "ls180.v:4257.54-4257.83"
- wire width 3 $add$ls180.v:4257$607_Y
- attribute \src "ls180.v:4316.52-4316.79"
- wire width 3 $add$ls180.v:4316$615_Y
- attribute \src "ls180.v:4420.58-4420.86"
- wire width 8 $add$ls180.v:4420$643_Y
- attribute \src "ls180.v:4477.58-4477.86"
- wire width 8 $add$ls180.v:4477$646_Y
- attribute \src "ls180.v:4494.58-4494.86"
- wire width 8 $add$ls180.v:4494$648_Y
- attribute \src "ls180.v:4587.59-4587.87"
- wire width 8 $add$ls180.v:4587$665_Y
- attribute \src "ls180.v:4612.59-4612.87"
- wire width 8 $add$ls180.v:4612$668_Y
- attribute \src "ls180.v:4734.53-4734.82"
- wire width 8 $add$ls180.v:4734$685_Y
- attribute \src "ls180.v:4845.65-4845.114"
- wire width 10 $add$ls180.v:4845$699_Y
- attribute \src "ls180.v:4850.62-4850.91"
- wire width 10 $add$ls180.v:4850$702_Y
- attribute \src "ls180.v:4876.61-4876.90"
- wire width 10 $add$ls180.v:4876$705_Y
- attribute \src "ls180.v:5080.80-5080.117"
- wire width 3 $add$ls180.v:5080$890_Y
- attribute \src "ls180.v:5274.54-5274.82"
- wire width 3 $add$ls180.v:5274$965_Y
- attribute \src "ls180.v:5326.55-5326.84"
- wire width 32 $add$ls180.v:5326$975_Y
- attribute \src "ls180.v:5352.57-5352.86"
- wire width 32 $add$ls180.v:5352$983_Y
- attribute \src "ls180.v:5473.51-5473.134"
- wire width 32 $add$ls180.v:5473$999_Y
- attribute \src "ls180.v:5476.77-5476.125"
- wire width 32 $add$ls180.v:5476$1001_Y
- attribute \src "ls180.v:5569.50-5569.105"
- wire width 32 $add$ls180.v:5569$1010_Y
- attribute \src "ls180.v:5571.77-5571.111"
- wire width 32 $add$ls180.v:5571$1011_Y
- attribute \src "ls180.v:7491.36-7491.70"
- wire width 32 $add$ls180.v:7491$2403_Y
- attribute \src "ls180.v:7576.37-7576.72"
- wire width 4 $add$ls180.v:7576$2424_Y
- attribute \src "ls180.v:7593.60-7593.119"
- wire width 3 $add$ls180.v:7593$2428_Y
- attribute \src "ls180.v:7596.60-7596.119"
- wire width 3 $add$ls180.v:7596$2429_Y
- attribute \src "ls180.v:7600.59-7600.116"
- wire width 4 $add$ls180.v:7600$2434_Y
- attribute \src "ls180.v:7639.60-7639.119"
- wire width 3 $add$ls180.v:7639$2444_Y
- attribute \src "ls180.v:7642.60-7642.119"
- wire width 3 $add$ls180.v:7642$2445_Y
- attribute \src "ls180.v:7646.59-7646.116"
- wire width 4 $add$ls180.v:7646$2450_Y
- attribute \src "ls180.v:7685.60-7685.119"
- wire width 3 $add$ls180.v:7685$2460_Y
- attribute \src "ls180.v:7688.60-7688.119"
- wire width 3 $add$ls180.v:7688$2461_Y
- attribute \src "ls180.v:7692.59-7692.116"
- wire width 4 $add$ls180.v:7692$2466_Y
- attribute \src "ls180.v:7731.60-7731.119"
- wire width 3 $add$ls180.v:7731$2476_Y
- attribute \src "ls180.v:7734.60-7734.119"
- wire width 3 $add$ls180.v:7734$2477_Y
- attribute \src "ls180.v:7738.59-7738.116"
- wire width 4 $add$ls180.v:7738$2482_Y
- attribute \src "ls180.v:7968.34-7968.66"
- wire width 4 $add$ls180.v:7968$2536_Y
- attribute \src "ls180.v:7984.73-7984.131"
- wire width 33 $add$ls180.v:7984$2539_Y
- attribute \src "ls180.v:7997.34-7997.66"
- wire width 4 $add$ls180.v:7997$2543_Y
- attribute \src "ls180.v:8016.73-8016.131"
- wire width 33 $add$ls180.v:8016$2546_Y
- attribute \src "ls180.v:8042.33-8042.65"
- wire width 4 $add$ls180.v:8042$2554_Y
- attribute \src "ls180.v:8045.33-8045.65"
- wire width 4 $add$ls180.v:8045$2555_Y
- attribute \src "ls180.v:8049.33-8049.64"
- wire width 5 $add$ls180.v:8049$2560_Y
- attribute \src "ls180.v:8064.33-8064.65"
- wire width 4 $add$ls180.v:8064$2565_Y
- attribute \src "ls180.v:8067.33-8067.65"
- wire width 4 $add$ls180.v:8067$2566_Y
- attribute \src "ls180.v:8071.33-8071.64"
- wire width 5 $add$ls180.v:8071$2571_Y
- attribute \src "ls180.v:8092.35-8092.70"
- wire width 16 $add$ls180.v:8092$2573_Y
- attribute \src "ls180.v:8127.34-8127.68"
- wire width 16 $add$ls180.v:8127$2578_Y
- attribute \src "ls180.v:8163.25-8163.49"
- wire width 32 $add$ls180.v:8163$2583_Y
- attribute \src "ls180.v:8177.25-8177.49"
- wire width 32 $add$ls180.v:8177$2587_Y
- attribute \src "ls180.v:8191.31-8191.61"
- wire width 9 $add$ls180.v:8191$2592_Y
- attribute \src "ls180.v:8214.45-8214.88"
- wire width 3 $add$ls180.v:8214$2596_Y
- attribute \src "ls180.v:8260.71-8260.114"
- wire width 4 $add$ls180.v:8260$2602_Y
- attribute \src "ls180.v:8295.46-8295.90"
- wire width 3 $add$ls180.v:8295$2608_Y
- attribute \src "ls180.v:8341.72-8341.116"
- wire width 4 $add$ls180.v:8341$2614_Y
- attribute \src "ls180.v:8374.47-8374.92"
- wire $add$ls180.v:8374$2620_Y
- attribute \src "ls180.v:8402.73-8402.118"
- wire width 2 $add$ls180.v:8402$2626_Y
- attribute \src "ls180.v:8514.39-8514.75"
- wire width 4 $add$ls180.v:8514$2639_Y
- attribute \src "ls180.v:8575.37-8575.73"
- wire width 5 $add$ls180.v:8575$2643_Y
- attribute \src "ls180.v:8578.37-8578.73"
- wire width 5 $add$ls180.v:8578$2644_Y
- attribute \src "ls180.v:8582.36-8582.70"
- wire width 6 $add$ls180.v:8582$2649_Y
- attribute \src "ls180.v:8597.41-8597.80"
- wire width 2 $add$ls180.v:8597$2653_Y
- attribute \src "ls180.v:8631.67-8631.106"
- wire width 3 $add$ls180.v:8631$2659_Y
- attribute \src "ls180.v:8657.39-8657.76"
- wire width 2 $add$ls180.v:8657$2661_Y
- attribute \src "ls180.v:8661.37-8661.73"
- wire width 5 $add$ls180.v:8661$2665_Y
- attribute \src "ls180.v:8664.37-8664.73"
- wire width 5 $add$ls180.v:8664$2666_Y
- attribute \src "ls180.v:8668.36-8668.70"
- wire width 6 $add$ls180.v:8668$2671_Y
- attribute \src "ls180.v:2813.9-2813.80"
- wire $and$ls180.v:2813$17_Y
- attribute \src "ls180.v:2831.9-2831.80"
- wire $and$ls180.v:2831$24_Y
- attribute \src "ls180.v:2873.9-2873.80"
- wire $and$ls180.v:2873$28_Y
- attribute \src "ls180.v:2891.9-2891.80"
- wire $and$ls180.v:2891$35_Y
- attribute \src "ls180.v:2933.9-2933.86"
- wire $and$ls180.v:2933$39_Y
- attribute \src "ls180.v:2951.9-2951.86"
- wire $and$ls180.v:2951$46_Y
- attribute \src "ls180.v:2961.31-2961.90"
- wire $and$ls180.v:2961$48_Y
- attribute \src "ls180.v:2961.30-2961.121"
- wire $and$ls180.v:2961$49_Y
- attribute \src "ls180.v:2961.29-2961.156"
- wire $and$ls180.v:2961$50_Y
- attribute \src "ls180.v:2962.31-2962.90"
- wire $and$ls180.v:2962$51_Y
- attribute \src "ls180.v:2962.30-2962.121"
- wire $and$ls180.v:2962$52_Y
- attribute \src "ls180.v:2962.29-2962.156"
- wire $and$ls180.v:2962$53_Y
- attribute \src "ls180.v:2963.31-2963.90"
- wire $and$ls180.v:2963$54_Y
- attribute \src "ls180.v:2963.30-2963.121"
- wire $and$ls180.v:2963$55_Y
- attribute \src "ls180.v:2963.29-2963.156"
- wire $and$ls180.v:2963$56_Y
- attribute \src "ls180.v:2964.31-2964.90"
- wire $and$ls180.v:2964$57_Y
- attribute \src "ls180.v:2964.30-2964.121"
- wire $and$ls180.v:2964$58_Y
- attribute \src "ls180.v:2964.29-2964.156"
- wire $and$ls180.v:2964$59_Y
- attribute \src "ls180.v:2973.7-2973.89"
- wire $and$ls180.v:2973$62_Y
- attribute \src "ls180.v:2978.32-2978.111"
- wire $and$ls180.v:2978$63_Y
- attribute \src "ls180.v:3092.40-3092.99"
- wire $and$ls180.v:3092$70_Y
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+ wire $xor$ls180.v:5184$944_Y
+ attribute \src "ls180.v:5185.879-5185.961"
+ wire $xor$ls180.v:5185$945_Y
+ attribute \src "ls180.v:5185.620-5185.702"
+ wire $xor$ls180.v:5185$946_Y
+ attribute \src "ls180.v:5185.575-5185.703"
+ wire $xor$ls180.v:5185$947_Y
+ attribute \src "ls180.v:5185.229-5185.311"
+ wire $xor$ls180.v:5185$948_Y
+ attribute \src "ls180.v:5185.183-5185.312"
+ wire $xor$ls180.v:5185$949_Y
+ attribute \src "ls180.v:5194.879-5194.961"
+ wire $xor$ls180.v:5194$951_Y
+ attribute \src "ls180.v:5194.620-5194.702"
+ wire $xor$ls180.v:5194$952_Y
+ attribute \src "ls180.v:5194.575-5194.703"
+ wire $xor$ls180.v:5194$953_Y
+ attribute \src "ls180.v:5194.229-5194.311"
+ wire $xor$ls180.v:5194$954_Y
+ attribute \src "ls180.v:5194.183-5194.312"
+ wire $xor$ls180.v:5194$955_Y
+ attribute \src "ls180.v:5195.879-5195.961"
+ wire $xor$ls180.v:5195$956_Y
+ attribute \src "ls180.v:5195.620-5195.702"
+ wire $xor$ls180.v:5195$957_Y
+ attribute \src "ls180.v:5195.575-5195.703"
+ wire $xor$ls180.v:5195$958_Y
+ attribute \src "ls180.v:5195.229-5195.311"
+ wire $xor$ls180.v:5195$959_Y
+ attribute \src "ls180.v:5195.183-5195.312"
+ wire $xor$ls180.v:5195$960_Y
+ attribute \src "ls180.v:1745.11-1745.42"
wire width 3 \builder_bankmachine0_next_state
- attribute \src "ls180.v:1748.11-1748.37"
+ attribute \src "ls180.v:1744.11-1744.37"
wire width 3 \builder_bankmachine0_state
- attribute \src "ls180.v:1751.11-1751.42"
+ attribute \src "ls180.v:1747.11-1747.42"
wire width 3 \builder_bankmachine1_next_state
- attribute \src "ls180.v:1750.11-1750.37"
+ attribute \src "ls180.v:1746.11-1746.37"
wire width 3 \builder_bankmachine1_state
- attribute \src "ls180.v:1753.11-1753.42"
+ attribute \src "ls180.v:1749.11-1749.42"
wire width 3 \builder_bankmachine2_next_state
- attribute \src "ls180.v:1752.11-1752.37"
+ attribute \src "ls180.v:1748.11-1748.37"
wire width 3 \builder_bankmachine2_state
- attribute \src "ls180.v:1755.11-1755.42"
+ attribute \src "ls180.v:1751.11-1751.42"
wire width 3 \builder_bankmachine3_next_state
- attribute \src "ls180.v:1754.11-1754.37"
+ attribute \src "ls180.v:1750.11-1750.37"
wire width 3 \builder_bankmachine3_state
- attribute \src "ls180.v:2600.5-2600.34"
+ attribute \src "ls180.v:2596.5-2596.34"
wire \builder_comb_rhs_array_muxed0
- attribute \src "ls180.v:2601.12-2601.41"
+ attribute \src "ls180.v:2597.12-2597.41"
wire width 13 \builder_comb_rhs_array_muxed1
- attribute \src "ls180.v:2613.5-2613.35"
+ attribute \src "ls180.v:2609.5-2609.35"
wire \builder_comb_rhs_array_muxed10
- attribute \src "ls180.v:2614.5-2614.35"
+ attribute \src "ls180.v:2610.5-2610.35"
wire \builder_comb_rhs_array_muxed11
- attribute \src "ls180.v:2618.12-2618.42"
+ attribute \src "ls180.v:2614.12-2614.42"
wire width 22 \builder_comb_rhs_array_muxed12
- attribute \src "ls180.v:2619.5-2619.35"
+ attribute \src "ls180.v:2615.5-2615.35"
wire \builder_comb_rhs_array_muxed13
- attribute \src "ls180.v:2620.5-2620.35"
+ attribute \src "ls180.v:2616.5-2616.35"
wire \builder_comb_rhs_array_muxed14
- attribute \src "ls180.v:2621.12-2621.42"
+ attribute \src "ls180.v:2617.12-2617.42"
wire width 22 \builder_comb_rhs_array_muxed15
- attribute \src "ls180.v:2622.5-2622.35"
+ attribute \src "ls180.v:2618.5-2618.35"
wire \builder_comb_rhs_array_muxed16
- attribute \src "ls180.v:2623.5-2623.35"
+ attribute \src "ls180.v:2619.5-2619.35"
wire \builder_comb_rhs_array_muxed17
- attribute \src "ls180.v:2624.12-2624.42"
+ attribute \src "ls180.v:2620.12-2620.42"
wire width 22 \builder_comb_rhs_array_muxed18
- attribute \src "ls180.v:2625.5-2625.35"
+ attribute \src "ls180.v:2621.5-2621.35"
wire \builder_comb_rhs_array_muxed19
- attribute \src "ls180.v:2602.11-2602.40"
+ attribute \src "ls180.v:2598.11-2598.40"
wire width 2 \builder_comb_rhs_array_muxed2
- attribute \src "ls180.v:2626.5-2626.35"
+ attribute \src "ls180.v:2622.5-2622.35"
wire \builder_comb_rhs_array_muxed20
- attribute \src "ls180.v:2627.12-2627.42"
+ attribute \src "ls180.v:2623.12-2623.42"
wire width 22 \builder_comb_rhs_array_muxed21
- attribute \src "ls180.v:2628.5-2628.35"
+ attribute \src "ls180.v:2624.5-2624.35"
wire \builder_comb_rhs_array_muxed22
- attribute \src "ls180.v:2629.5-2629.35"
+ attribute \src "ls180.v:2625.5-2625.35"
wire \builder_comb_rhs_array_muxed23
- attribute \src "ls180.v:2630.12-2630.42"
+ attribute \src "ls180.v:2626.12-2626.42"
wire width 32 \builder_comb_rhs_array_muxed24
- attribute \src "ls180.v:2631.12-2631.42"
+ attribute \src "ls180.v:2627.12-2627.42"
wire width 32 \builder_comb_rhs_array_muxed25
- attribute \src "ls180.v:2632.11-2632.41"
+ attribute \src "ls180.v:2628.11-2628.41"
wire width 4 \builder_comb_rhs_array_muxed26
- attribute \src "ls180.v:2633.5-2633.35"
+ attribute \src "ls180.v:2629.5-2629.35"
wire \builder_comb_rhs_array_muxed27
- attribute \src "ls180.v:2634.5-2634.35"
+ attribute \src "ls180.v:2630.5-2630.35"
wire \builder_comb_rhs_array_muxed28
- attribute \src "ls180.v:2635.5-2635.35"
+ attribute \src "ls180.v:2631.5-2631.35"
wire \builder_comb_rhs_array_muxed29
- attribute \src "ls180.v:2603.5-2603.34"
+ attribute \src "ls180.v:2599.5-2599.34"
wire \builder_comb_rhs_array_muxed3
- attribute \src "ls180.v:2636.11-2636.41"
+ attribute \src "ls180.v:2632.11-2632.41"
wire width 3 \builder_comb_rhs_array_muxed30
- attribute \src "ls180.v:2637.11-2637.41"
+ attribute \src "ls180.v:2633.11-2633.41"
wire width 2 \builder_comb_rhs_array_muxed31
- attribute \src "ls180.v:2604.5-2604.34"
+ attribute \src "ls180.v:2600.5-2600.34"
wire \builder_comb_rhs_array_muxed4
- attribute \src "ls180.v:2605.5-2605.34"
+ attribute \src "ls180.v:2601.5-2601.34"
wire \builder_comb_rhs_array_muxed5
- attribute \src "ls180.v:2609.5-2609.34"
+ attribute \src "ls180.v:2605.5-2605.34"
wire \builder_comb_rhs_array_muxed6
- attribute \src "ls180.v:2610.12-2610.41"
+ attribute \src "ls180.v:2606.12-2606.41"
wire width 13 \builder_comb_rhs_array_muxed7
- attribute \src "ls180.v:2611.11-2611.40"
+ attribute \src "ls180.v:2607.11-2607.40"
wire width 2 \builder_comb_rhs_array_muxed8
- attribute \src "ls180.v:2612.5-2612.34"
+ attribute \src "ls180.v:2608.5-2608.34"
wire \builder_comb_rhs_array_muxed9
- attribute \src "ls180.v:2606.5-2606.32"
+ attribute \src "ls180.v:2602.5-2602.32"
wire \builder_comb_t_array_muxed0
- attribute \src "ls180.v:2607.5-2607.32"
+ attribute \src "ls180.v:2603.5-2603.32"
wire \builder_comb_t_array_muxed1
- attribute \src "ls180.v:2608.5-2608.32"
+ attribute \src "ls180.v:2604.5-2604.32"
wire \builder_comb_t_array_muxed2
- attribute \src "ls180.v:2615.5-2615.32"
+ attribute \src "ls180.v:2611.5-2611.32"
wire \builder_comb_t_array_muxed3
- attribute \src "ls180.v:2616.5-2616.32"
+ attribute \src "ls180.v:2612.5-2612.32"
wire \builder_comb_t_array_muxed4
- attribute \src "ls180.v:2617.5-2617.32"
+ attribute \src "ls180.v:2613.5-2613.32"
wire \builder_comb_t_array_muxed5
- attribute \src "ls180.v:1735.5-1735.34"
+ attribute \src "ls180.v:1731.5-1731.34"
wire \builder_converter0_next_state
- attribute \src "ls180.v:1734.5-1734.29"
+ attribute \src "ls180.v:1730.5-1730.29"
wire \builder_converter0_state
- attribute \src "ls180.v:1739.5-1739.34"
+ attribute \src "ls180.v:1735.5-1735.34"
wire \builder_converter1_next_state
- attribute \src "ls180.v:1738.5-1738.29"
+ attribute \src "ls180.v:1734.5-1734.29"
wire \builder_converter1_state
- attribute \src "ls180.v:1743.5-1743.34"
+ attribute \src "ls180.v:1739.5-1739.34"
wire \builder_converter2_next_state
- attribute \src "ls180.v:1742.5-1742.29"
+ attribute \src "ls180.v:1738.5-1738.29"
wire \builder_converter2_state
- attribute \src "ls180.v:1780.5-1780.33"
+ attribute \src "ls180.v:1776.5-1776.33"
wire \builder_converter_next_state
- attribute \src "ls180.v:1779.5-1779.28"
+ attribute \src "ls180.v:1775.5-1775.28"
wire \builder_converter_state
- attribute \src "ls180.v:1900.12-1900.25"
+ attribute \src "ls180.v:1896.12-1896.25"
wire width 20 \builder_count
- attribute \src "ls180.v:2588.13-2588.41"
+ attribute \src "ls180.v:2584.13-2584.41"
wire width 14 \builder_csr_interconnect_adr
- attribute \src "ls180.v:2591.12-2591.42"
+ attribute \src "ls180.v:2587.12-2587.42"
wire width 8 \builder_csr_interconnect_dat_r
- attribute \src "ls180.v:2590.12-2590.42"
+ attribute \src "ls180.v:2586.12-2586.42"
wire width 8 \builder_csr_interconnect_dat_w
- attribute \src "ls180.v:2589.6-2589.33"
+ attribute \src "ls180.v:2585.6-2585.33"
wire \builder_csr_interconnect_we
- attribute \src "ls180.v:1938.12-1938.42"
+ attribute \src "ls180.v:1934.12-1934.42"
wire width 8 \builder_csrbank0_bus_errors0_r
- attribute \src "ls180.v:1937.6-1937.37"
+ attribute \src "ls180.v:1933.6-1933.37"
wire \builder_csrbank0_bus_errors0_re
- attribute \src "ls180.v:1940.12-1940.42"
+ attribute \src "ls180.v:1936.12-1936.42"
wire width 8 \builder_csrbank0_bus_errors0_w
- attribute \src "ls180.v:1939.6-1939.37"
+ attribute \src "ls180.v:1935.6-1935.37"
wire \builder_csrbank0_bus_errors0_we
- attribute \src "ls180.v:1934.12-1934.42"
+ attribute \src "ls180.v:1930.12-1930.42"
wire width 8 \builder_csrbank0_bus_errors1_r
- attribute \src "ls180.v:1933.6-1933.37"
+ attribute \src "ls180.v:1929.6-1929.37"
wire \builder_csrbank0_bus_errors1_re
- attribute \src "ls180.v:1936.12-1936.42"
+ attribute \src "ls180.v:1932.12-1932.42"
wire width 8 \builder_csrbank0_bus_errors1_w
- attribute \src "ls180.v:1935.6-1935.37"
+ attribute \src "ls180.v:1931.6-1931.37"
wire \builder_csrbank0_bus_errors1_we
- attribute \src "ls180.v:1930.12-1930.42"
+ attribute \src "ls180.v:1926.12-1926.42"
wire width 8 \builder_csrbank0_bus_errors2_r
- attribute \src "ls180.v:1929.6-1929.37"
+ attribute \src "ls180.v:1925.6-1925.37"
wire \builder_csrbank0_bus_errors2_re
- attribute \src "ls180.v:1932.12-1932.42"
+ attribute \src "ls180.v:1928.12-1928.42"
wire width 8 \builder_csrbank0_bus_errors2_w
- attribute \src "ls180.v:1931.6-1931.37"
+ attribute \src "ls180.v:1927.6-1927.37"
wire \builder_csrbank0_bus_errors2_we
- attribute \src "ls180.v:1926.12-1926.42"
+ attribute \src "ls180.v:1922.12-1922.42"
wire width 8 \builder_csrbank0_bus_errors3_r
- attribute \src "ls180.v:1925.6-1925.37"
+ attribute \src "ls180.v:1921.6-1921.37"
wire \builder_csrbank0_bus_errors3_re
- attribute \src "ls180.v:1928.12-1928.42"
+ attribute \src "ls180.v:1924.12-1924.42"
wire width 8 \builder_csrbank0_bus_errors3_w
- attribute \src "ls180.v:1927.6-1927.37"
+ attribute \src "ls180.v:1923.6-1923.37"
wire \builder_csrbank0_bus_errors3_we
- attribute \src "ls180.v:1906.6-1906.31"
+ attribute \src "ls180.v:1902.6-1902.31"
wire \builder_csrbank0_reset0_r
- attribute \src "ls180.v:1905.6-1905.32"
+ attribute \src "ls180.v:1901.6-1901.32"
wire \builder_csrbank0_reset0_re
- attribute \src "ls180.v:1908.6-1908.31"
+ attribute \src "ls180.v:1904.6-1904.31"
wire \builder_csrbank0_reset0_w
- attribute \src "ls180.v:1907.6-1907.32"
+ attribute \src "ls180.v:1903.6-1903.32"
wire \builder_csrbank0_reset0_we
- attribute \src "ls180.v:1922.12-1922.39"
+ attribute \src "ls180.v:1918.12-1918.39"
wire width 8 \builder_csrbank0_scratch0_r
- attribute \src "ls180.v:1921.6-1921.34"
+ attribute \src "ls180.v:1917.6-1917.34"
wire \builder_csrbank0_scratch0_re
- attribute \src "ls180.v:1924.12-1924.39"
+ attribute \src "ls180.v:1920.12-1920.39"
wire width 8 \builder_csrbank0_scratch0_w
- attribute \src "ls180.v:1923.6-1923.34"
+ attribute \src "ls180.v:1919.6-1919.34"
wire \builder_csrbank0_scratch0_we
- attribute \src "ls180.v:1918.12-1918.39"
+ attribute \src "ls180.v:1914.12-1914.39"
wire width 8 \builder_csrbank0_scratch1_r
- attribute \src "ls180.v:1917.6-1917.34"
+ attribute \src "ls180.v:1913.6-1913.34"
wire \builder_csrbank0_scratch1_re
- attribute \src "ls180.v:1920.12-1920.39"
+ attribute \src "ls180.v:1916.12-1916.39"
wire width 8 \builder_csrbank0_scratch1_w
- attribute \src "ls180.v:1919.6-1919.34"
+ attribute \src "ls180.v:1915.6-1915.34"
wire \builder_csrbank0_scratch1_we
- attribute \src "ls180.v:1914.12-1914.39"
+ attribute \src "ls180.v:1910.12-1910.39"
wire width 8 \builder_csrbank0_scratch2_r
- attribute \src "ls180.v:1913.6-1913.34"
+ attribute \src "ls180.v:1909.6-1909.34"
wire \builder_csrbank0_scratch2_re
- attribute \src "ls180.v:1916.12-1916.39"
+ attribute \src "ls180.v:1912.12-1912.39"
wire width 8 \builder_csrbank0_scratch2_w
- attribute \src "ls180.v:1915.6-1915.34"
+ attribute \src "ls180.v:1911.6-1911.34"
wire \builder_csrbank0_scratch2_we
- attribute \src "ls180.v:1910.12-1910.39"
+ attribute \src "ls180.v:1906.12-1906.39"
wire width 8 \builder_csrbank0_scratch3_r
- attribute \src "ls180.v:1909.6-1909.34"
+ attribute \src "ls180.v:1905.6-1905.34"
wire \builder_csrbank0_scratch3_re
- attribute \src "ls180.v:1912.12-1912.39"
+ attribute \src "ls180.v:1908.12-1908.39"
wire width 8 \builder_csrbank0_scratch3_w
- attribute \src "ls180.v:1911.6-1911.34"
+ attribute \src "ls180.v:1907.6-1907.34"
wire \builder_csrbank0_scratch3_we
- attribute \src "ls180.v:1941.6-1941.26"
+ attribute \src "ls180.v:1937.6-1937.26"
wire \builder_csrbank0_sel
- attribute \src "ls180.v:2412.12-2412.40"
+ attribute \src "ls180.v:2408.12-2408.40"
wire width 8 \builder_csrbank10_control0_r
- attribute \src "ls180.v:2411.6-2411.35"
+ attribute \src "ls180.v:2407.6-2407.35"
wire \builder_csrbank10_control0_re
- attribute \src "ls180.v:2414.12-2414.40"
+ attribute \src "ls180.v:2410.12-2410.40"
wire width 8 \builder_csrbank10_control0_w
- attribute \src "ls180.v:2413.6-2413.35"
+ attribute \src "ls180.v:2409.6-2409.35"
wire \builder_csrbank10_control0_we
- attribute \src "ls180.v:2408.12-2408.40"
+ attribute \src "ls180.v:2404.12-2404.40"
wire width 8 \builder_csrbank10_control1_r
- attribute \src "ls180.v:2407.6-2407.35"
+ attribute \src "ls180.v:2403.6-2403.35"
wire \builder_csrbank10_control1_re
- attribute \src "ls180.v:2410.12-2410.40"
+ attribute \src "ls180.v:2406.12-2406.40"
wire width 8 \builder_csrbank10_control1_w
- attribute \src "ls180.v:2409.6-2409.35"
+ attribute \src "ls180.v:2405.6-2405.35"
wire \builder_csrbank10_control1_we
- attribute \src "ls180.v:2428.6-2428.29"
+ attribute \src "ls180.v:2424.6-2424.29"
wire \builder_csrbank10_cs0_r
- attribute \src "ls180.v:2427.6-2427.30"
+ attribute \src "ls180.v:2423.6-2423.30"
wire \builder_csrbank10_cs0_re
- attribute \src "ls180.v:2430.6-2430.29"
+ attribute \src "ls180.v:2426.6-2426.29"
wire \builder_csrbank10_cs0_w
- attribute \src "ls180.v:2429.6-2429.30"
+ attribute \src "ls180.v:2425.6-2425.30"
wire \builder_csrbank10_cs0_we
- attribute \src "ls180.v:2432.6-2432.35"
+ attribute \src "ls180.v:2428.6-2428.35"
wire \builder_csrbank10_loopback0_r
- attribute \src "ls180.v:2431.6-2431.36"
+ attribute \src "ls180.v:2427.6-2427.36"
wire \builder_csrbank10_loopback0_re
- attribute \src "ls180.v:2434.6-2434.35"
+ attribute \src "ls180.v:2430.6-2430.35"
wire \builder_csrbank10_loopback0_w
- attribute \src "ls180.v:2433.6-2433.36"
+ attribute \src "ls180.v:2429.6-2429.36"
wire \builder_csrbank10_loopback0_we
- attribute \src "ls180.v:2424.12-2424.36"
+ attribute \src "ls180.v:2420.12-2420.36"
wire width 8 \builder_csrbank10_miso_r
- attribute \src "ls180.v:2423.6-2423.31"
+ attribute \src "ls180.v:2419.6-2419.31"
wire \builder_csrbank10_miso_re
- attribute \src "ls180.v:2426.12-2426.36"
+ attribute \src "ls180.v:2422.12-2422.36"
wire width 8 \builder_csrbank10_miso_w
- attribute \src "ls180.v:2425.6-2425.31"
+ attribute \src "ls180.v:2421.6-2421.31"
wire \builder_csrbank10_miso_we
- attribute \src "ls180.v:2420.12-2420.37"
+ attribute \src "ls180.v:2416.12-2416.37"
wire width 8 \builder_csrbank10_mosi0_r
- attribute \src "ls180.v:2419.6-2419.32"
+ attribute \src "ls180.v:2415.6-2415.32"
wire \builder_csrbank10_mosi0_re
- attribute \src "ls180.v:2422.12-2422.37"
+ attribute \src "ls180.v:2418.12-2418.37"
wire width 8 \builder_csrbank10_mosi0_w
- attribute \src "ls180.v:2421.6-2421.32"
+ attribute \src "ls180.v:2417.6-2417.32"
wire \builder_csrbank10_mosi0_we
- attribute \src "ls180.v:2435.6-2435.27"
+ attribute \src "ls180.v:2431.6-2431.27"
wire \builder_csrbank10_sel
- attribute \src "ls180.v:2416.6-2416.32"
+ attribute \src "ls180.v:2412.6-2412.32"
wire \builder_csrbank10_status_r
- attribute \src "ls180.v:2415.6-2415.33"
+ attribute \src "ls180.v:2411.6-2411.33"
wire \builder_csrbank10_status_re
- attribute \src "ls180.v:2418.6-2418.32"
+ attribute \src "ls180.v:2414.6-2414.32"
wire \builder_csrbank10_status_w
- attribute \src "ls180.v:2417.6-2417.33"
+ attribute \src "ls180.v:2413.6-2413.33"
wire \builder_csrbank10_status_we
- attribute \src "ls180.v:2473.12-2473.44"
+ attribute \src "ls180.v:2469.12-2469.44"
wire width 8 \builder_csrbank11_clk_divider0_r
- attribute \src "ls180.v:2472.6-2472.39"
+ attribute \src "ls180.v:2468.6-2468.39"
wire \builder_csrbank11_clk_divider0_re
- attribute \src "ls180.v:2475.12-2475.44"
+ attribute \src "ls180.v:2471.12-2471.44"
wire width 8 \builder_csrbank11_clk_divider0_w
- attribute \src "ls180.v:2474.6-2474.39"
+ attribute \src "ls180.v:2470.6-2470.39"
wire \builder_csrbank11_clk_divider0_we
- attribute \src "ls180.v:2469.12-2469.44"
+ attribute \src "ls180.v:2465.12-2465.44"
wire width 8 \builder_csrbank11_clk_divider1_r
- attribute \src "ls180.v:2468.6-2468.39"
+ attribute \src "ls180.v:2464.6-2464.39"
wire \builder_csrbank11_clk_divider1_re
- attribute \src "ls180.v:2471.12-2471.44"
+ attribute \src "ls180.v:2467.12-2467.44"
wire width 8 \builder_csrbank11_clk_divider1_w
- attribute \src "ls180.v:2470.6-2470.39"
+ attribute \src "ls180.v:2466.6-2466.39"
wire \builder_csrbank11_clk_divider1_we
- attribute \src "ls180.v:2445.12-2445.40"
+ attribute \src "ls180.v:2441.12-2441.40"
wire width 8 \builder_csrbank11_control0_r
- attribute \src "ls180.v:2444.6-2444.35"
+ attribute \src "ls180.v:2440.6-2440.35"
wire \builder_csrbank11_control0_re
- attribute \src "ls180.v:2447.12-2447.40"
+ attribute \src "ls180.v:2443.12-2443.40"
wire width 8 \builder_csrbank11_control0_w
- attribute \src "ls180.v:2446.6-2446.35"
+ attribute \src "ls180.v:2442.6-2442.35"
wire \builder_csrbank11_control0_we
- attribute \src "ls180.v:2441.12-2441.40"
+ attribute \src "ls180.v:2437.12-2437.40"
wire width 8 \builder_csrbank11_control1_r
- attribute \src "ls180.v:2440.6-2440.35"
+ attribute \src "ls180.v:2436.6-2436.35"
wire \builder_csrbank11_control1_re
- attribute \src "ls180.v:2443.12-2443.40"
+ attribute \src "ls180.v:2439.12-2439.40"
wire width 8 \builder_csrbank11_control1_w
- attribute \src "ls180.v:2442.6-2442.35"
+ attribute \src "ls180.v:2438.6-2438.35"
wire \builder_csrbank11_control1_we
- attribute \src "ls180.v:2461.6-2461.29"
+ attribute \src "ls180.v:2457.6-2457.29"
wire \builder_csrbank11_cs0_r
- attribute \src "ls180.v:2460.6-2460.30"
+ attribute \src "ls180.v:2456.6-2456.30"
wire \builder_csrbank11_cs0_re
- attribute \src "ls180.v:2463.6-2463.29"
+ attribute \src "ls180.v:2459.6-2459.29"
wire \builder_csrbank11_cs0_w
- attribute \src "ls180.v:2462.6-2462.30"
+ attribute \src "ls180.v:2458.6-2458.30"
wire \builder_csrbank11_cs0_we
- attribute \src "ls180.v:2465.6-2465.35"
+ attribute \src "ls180.v:2461.6-2461.35"
wire \builder_csrbank11_loopback0_r
- attribute \src "ls180.v:2464.6-2464.36"
+ attribute \src "ls180.v:2460.6-2460.36"
wire \builder_csrbank11_loopback0_re
- attribute \src "ls180.v:2467.6-2467.35"
+ attribute \src "ls180.v:2463.6-2463.35"
wire \builder_csrbank11_loopback0_w
- attribute \src "ls180.v:2466.6-2466.36"
+ attribute \src "ls180.v:2462.6-2462.36"
wire \builder_csrbank11_loopback0_we
- attribute \src "ls180.v:2457.12-2457.36"
+ attribute \src "ls180.v:2453.12-2453.36"
wire width 8 \builder_csrbank11_miso_r
- attribute \src "ls180.v:2456.6-2456.31"
+ attribute \src "ls180.v:2452.6-2452.31"
wire \builder_csrbank11_miso_re
- attribute \src "ls180.v:2459.12-2459.36"
+ attribute \src "ls180.v:2455.12-2455.36"
wire width 8 \builder_csrbank11_miso_w
- attribute \src "ls180.v:2458.6-2458.31"
+ attribute \src "ls180.v:2454.6-2454.31"
wire \builder_csrbank11_miso_we
- attribute \src "ls180.v:2453.12-2453.37"
+ attribute \src "ls180.v:2449.12-2449.37"
wire width 8 \builder_csrbank11_mosi0_r
- attribute \src "ls180.v:2452.6-2452.32"
+ attribute \src "ls180.v:2448.6-2448.32"
wire \builder_csrbank11_mosi0_re
- attribute \src "ls180.v:2455.12-2455.37"
+ attribute \src "ls180.v:2451.12-2451.37"
wire width 8 \builder_csrbank11_mosi0_w
- attribute \src "ls180.v:2454.6-2454.32"
+ attribute \src "ls180.v:2450.6-2450.32"
wire \builder_csrbank11_mosi0_we
- attribute \src "ls180.v:2476.6-2476.27"
+ attribute \src "ls180.v:2472.6-2472.27"
wire \builder_csrbank11_sel
- attribute \src "ls180.v:2449.6-2449.32"
+ attribute \src "ls180.v:2445.6-2445.32"
wire \builder_csrbank11_status_r
- attribute \src "ls180.v:2448.6-2448.33"
+ attribute \src "ls180.v:2444.6-2444.33"
wire \builder_csrbank11_status_re
- attribute \src "ls180.v:2451.6-2451.32"
+ attribute \src "ls180.v:2447.6-2447.32"
wire \builder_csrbank11_status_w
- attribute \src "ls180.v:2450.6-2450.33"
+ attribute \src "ls180.v:2446.6-2446.33"
wire \builder_csrbank11_status_we
- attribute \src "ls180.v:2514.6-2514.29"
+ attribute \src "ls180.v:2510.6-2510.29"
wire \builder_csrbank12_en0_r
- attribute \src "ls180.v:2513.6-2513.30"
+ attribute \src "ls180.v:2509.6-2509.30"
wire \builder_csrbank12_en0_re
- attribute \src "ls180.v:2516.6-2516.29"
+ attribute \src "ls180.v:2512.6-2512.29"
wire \builder_csrbank12_en0_w
- attribute \src "ls180.v:2515.6-2515.30"
+ attribute \src "ls180.v:2511.6-2511.30"
wire \builder_csrbank12_en0_we
- attribute \src "ls180.v:2538.6-2538.36"
+ attribute \src "ls180.v:2534.6-2534.36"
wire \builder_csrbank12_ev_enable0_r
- attribute \src "ls180.v:2537.6-2537.37"
+ attribute \src "ls180.v:2533.6-2533.37"
wire \builder_csrbank12_ev_enable0_re
- attribute \src "ls180.v:2540.6-2540.36"
+ attribute \src "ls180.v:2536.6-2536.36"
wire \builder_csrbank12_ev_enable0_w
- attribute \src "ls180.v:2539.6-2539.37"
+ attribute \src "ls180.v:2535.6-2535.37"
wire \builder_csrbank12_ev_enable0_we
- attribute \src "ls180.v:2494.12-2494.37"
+ attribute \src "ls180.v:2490.12-2490.37"
wire width 8 \builder_csrbank12_load0_r
- attribute \src "ls180.v:2493.6-2493.32"
+ attribute \src "ls180.v:2489.6-2489.32"
wire \builder_csrbank12_load0_re
- attribute \src "ls180.v:2496.12-2496.37"
+ attribute \src "ls180.v:2492.12-2492.37"
wire width 8 \builder_csrbank12_load0_w
- attribute \src "ls180.v:2495.6-2495.32"
+ attribute \src "ls180.v:2491.6-2491.32"
wire \builder_csrbank12_load0_we
- attribute \src "ls180.v:2490.12-2490.37"
+ attribute \src "ls180.v:2486.12-2486.37"
wire width 8 \builder_csrbank12_load1_r
- attribute \src "ls180.v:2489.6-2489.32"
+ attribute \src "ls180.v:2485.6-2485.32"
wire \builder_csrbank12_load1_re
- attribute \src "ls180.v:2492.12-2492.37"
+ attribute \src "ls180.v:2488.12-2488.37"
wire width 8 \builder_csrbank12_load1_w
- attribute \src "ls180.v:2491.6-2491.32"
+ attribute \src "ls180.v:2487.6-2487.32"
wire \builder_csrbank12_load1_we
- attribute \src "ls180.v:2486.12-2486.37"
+ attribute \src "ls180.v:2482.12-2482.37"
wire width 8 \builder_csrbank12_load2_r
- attribute \src "ls180.v:2485.6-2485.32"
+ attribute \src "ls180.v:2481.6-2481.32"
wire \builder_csrbank12_load2_re
- attribute \src "ls180.v:2488.12-2488.37"
+ attribute \src "ls180.v:2484.12-2484.37"
wire width 8 \builder_csrbank12_load2_w
- attribute \src "ls180.v:2487.6-2487.32"
+ attribute \src "ls180.v:2483.6-2483.32"
wire \builder_csrbank12_load2_we
- attribute \src "ls180.v:2482.12-2482.37"
+ attribute \src "ls180.v:2478.12-2478.37"
wire width 8 \builder_csrbank12_load3_r
- attribute \src "ls180.v:2481.6-2481.32"
+ attribute \src "ls180.v:2477.6-2477.32"
wire \builder_csrbank12_load3_re
- attribute \src "ls180.v:2484.12-2484.37"
+ attribute \src "ls180.v:2480.12-2480.37"
wire width 8 \builder_csrbank12_load3_w
- attribute \src "ls180.v:2483.6-2483.32"
+ attribute \src "ls180.v:2479.6-2479.32"
wire \builder_csrbank12_load3_we
- attribute \src "ls180.v:2510.12-2510.39"
+ attribute \src "ls180.v:2506.12-2506.39"
wire width 8 \builder_csrbank12_reload0_r
- attribute \src "ls180.v:2509.6-2509.34"
+ attribute \src "ls180.v:2505.6-2505.34"
wire \builder_csrbank12_reload0_re
- attribute \src "ls180.v:2512.12-2512.39"
+ attribute \src "ls180.v:2508.12-2508.39"
wire width 8 \builder_csrbank12_reload0_w
- attribute \src "ls180.v:2511.6-2511.34"
+ attribute \src "ls180.v:2507.6-2507.34"
wire \builder_csrbank12_reload0_we
- attribute \src "ls180.v:2506.12-2506.39"
+ attribute \src "ls180.v:2502.12-2502.39"
wire width 8 \builder_csrbank12_reload1_r
- attribute \src "ls180.v:2505.6-2505.34"
+ attribute \src "ls180.v:2501.6-2501.34"
wire \builder_csrbank12_reload1_re
- attribute \src "ls180.v:2508.12-2508.39"
+ attribute \src "ls180.v:2504.12-2504.39"
wire width 8 \builder_csrbank12_reload1_w
- attribute \src "ls180.v:2507.6-2507.34"
+ attribute \src "ls180.v:2503.6-2503.34"
wire \builder_csrbank12_reload1_we
- attribute \src "ls180.v:2502.12-2502.39"
+ attribute \src "ls180.v:2498.12-2498.39"
wire width 8 \builder_csrbank12_reload2_r
- attribute \src "ls180.v:2501.6-2501.34"
+ attribute \src "ls180.v:2497.6-2497.34"
wire \builder_csrbank12_reload2_re
- attribute \src "ls180.v:2504.12-2504.39"
+ attribute \src "ls180.v:2500.12-2500.39"
wire width 8 \builder_csrbank12_reload2_w
- attribute \src "ls180.v:2503.6-2503.34"
+ attribute \src "ls180.v:2499.6-2499.34"
wire \builder_csrbank12_reload2_we
- attribute \src "ls180.v:2498.12-2498.39"
+ attribute \src "ls180.v:2494.12-2494.39"
wire width 8 \builder_csrbank12_reload3_r
- attribute \src "ls180.v:2497.6-2497.34"
+ attribute \src "ls180.v:2493.6-2493.34"
wire \builder_csrbank12_reload3_re
- attribute \src "ls180.v:2500.12-2500.39"
+ attribute \src "ls180.v:2496.12-2496.39"
wire width 8 \builder_csrbank12_reload3_w
- attribute \src "ls180.v:2499.6-2499.34"
+ attribute \src "ls180.v:2495.6-2495.34"
wire \builder_csrbank12_reload3_we
- attribute \src "ls180.v:2541.6-2541.27"
+ attribute \src "ls180.v:2537.6-2537.27"
wire \builder_csrbank12_sel
- attribute \src "ls180.v:2518.6-2518.39"
+ attribute \src "ls180.v:2514.6-2514.39"
wire \builder_csrbank12_update_value0_r
- attribute \src "ls180.v:2517.6-2517.40"
+ attribute \src "ls180.v:2513.6-2513.40"
wire \builder_csrbank12_update_value0_re
- attribute \src "ls180.v:2520.6-2520.39"
+ attribute \src "ls180.v:2516.6-2516.39"
wire \builder_csrbank12_update_value0_w
- attribute \src "ls180.v:2519.6-2519.40"
+ attribute \src "ls180.v:2515.6-2515.40"
wire \builder_csrbank12_update_value0_we
- attribute \src "ls180.v:2534.12-2534.38"
+ attribute \src "ls180.v:2530.12-2530.38"
wire width 8 \builder_csrbank12_value0_r
- attribute \src "ls180.v:2533.6-2533.33"
+ attribute \src "ls180.v:2529.6-2529.33"
wire \builder_csrbank12_value0_re
- attribute \src "ls180.v:2536.12-2536.38"
+ attribute \src "ls180.v:2532.12-2532.38"
wire width 8 \builder_csrbank12_value0_w
- attribute \src "ls180.v:2535.6-2535.33"
+ attribute \src "ls180.v:2531.6-2531.33"
wire \builder_csrbank12_value0_we
- attribute \src "ls180.v:2530.12-2530.38"
+ attribute \src "ls180.v:2526.12-2526.38"
wire width 8 \builder_csrbank12_value1_r
- attribute \src "ls180.v:2529.6-2529.33"
+ attribute \src "ls180.v:2525.6-2525.33"
wire \builder_csrbank12_value1_re
- attribute \src "ls180.v:2532.12-2532.38"
+ attribute \src "ls180.v:2528.12-2528.38"
wire width 8 \builder_csrbank12_value1_w
- attribute \src "ls180.v:2531.6-2531.33"
+ attribute \src "ls180.v:2527.6-2527.33"
wire \builder_csrbank12_value1_we
- attribute \src "ls180.v:2526.12-2526.38"
+ attribute \src "ls180.v:2522.12-2522.38"
wire width 8 \builder_csrbank12_value2_r
- attribute \src "ls180.v:2525.6-2525.33"
+ attribute \src "ls180.v:2521.6-2521.33"
wire \builder_csrbank12_value2_re
- attribute \src "ls180.v:2528.12-2528.38"
+ attribute \src "ls180.v:2524.12-2524.38"
wire width 8 \builder_csrbank12_value2_w
- attribute \src "ls180.v:2527.6-2527.33"
+ attribute \src "ls180.v:2523.6-2523.33"
wire \builder_csrbank12_value2_we
- attribute \src "ls180.v:2522.12-2522.38"
+ attribute \src "ls180.v:2518.12-2518.38"
wire width 8 \builder_csrbank12_value3_r
- attribute \src "ls180.v:2521.6-2521.33"
+ attribute \src "ls180.v:2517.6-2517.33"
wire \builder_csrbank12_value3_re
- attribute \src "ls180.v:2524.12-2524.38"
+ attribute \src "ls180.v:2520.12-2520.38"
wire width 8 \builder_csrbank12_value3_w
- attribute \src "ls180.v:2523.6-2523.33"
+ attribute \src "ls180.v:2519.6-2519.33"
wire \builder_csrbank12_value3_we
- attribute \src "ls180.v:2555.12-2555.42"
+ attribute \src "ls180.v:2551.12-2551.42"
wire width 2 \builder_csrbank13_ev_enable0_r
- attribute \src "ls180.v:2554.6-2554.37"
+ attribute \src "ls180.v:2550.6-2550.37"
wire \builder_csrbank13_ev_enable0_re
- attribute \src "ls180.v:2557.12-2557.42"
+ attribute \src "ls180.v:2553.12-2553.42"
wire width 2 \builder_csrbank13_ev_enable0_w
- attribute \src "ls180.v:2556.6-2556.37"
+ attribute \src "ls180.v:2552.6-2552.37"
wire \builder_csrbank13_ev_enable0_we
- attribute \src "ls180.v:2551.6-2551.33"
+ attribute \src "ls180.v:2547.6-2547.33"
wire \builder_csrbank13_rxempty_r
- attribute \src "ls180.v:2550.6-2550.34"
+ attribute \src "ls180.v:2546.6-2546.34"
wire \builder_csrbank13_rxempty_re
- attribute \src "ls180.v:2553.6-2553.33"
+ attribute \src "ls180.v:2549.6-2549.33"
wire \builder_csrbank13_rxempty_w
- attribute \src "ls180.v:2552.6-2552.34"
+ attribute \src "ls180.v:2548.6-2548.34"
wire \builder_csrbank13_rxempty_we
- attribute \src "ls180.v:2563.6-2563.32"
+ attribute \src "ls180.v:2559.6-2559.32"
wire \builder_csrbank13_rxfull_r
- attribute \src "ls180.v:2562.6-2562.33"
+ attribute \src "ls180.v:2558.6-2558.33"
wire \builder_csrbank13_rxfull_re
- attribute \src "ls180.v:2565.6-2565.32"
+ attribute \src "ls180.v:2561.6-2561.32"
wire \builder_csrbank13_rxfull_w
- attribute \src "ls180.v:2564.6-2564.33"
+ attribute \src "ls180.v:2560.6-2560.33"
wire \builder_csrbank13_rxfull_we
- attribute \src "ls180.v:2566.6-2566.27"
+ attribute \src "ls180.v:2562.6-2562.27"
wire \builder_csrbank13_sel
- attribute \src "ls180.v:2559.6-2559.33"
+ attribute \src "ls180.v:2555.6-2555.33"
wire \builder_csrbank13_txempty_r
- attribute \src "ls180.v:2558.6-2558.34"
+ attribute \src "ls180.v:2554.6-2554.34"
wire \builder_csrbank13_txempty_re
- attribute \src "ls180.v:2561.6-2561.33"
+ attribute \src "ls180.v:2557.6-2557.33"
wire \builder_csrbank13_txempty_w
- attribute \src "ls180.v:2560.6-2560.34"
+ attribute \src "ls180.v:2556.6-2556.34"
wire \builder_csrbank13_txempty_we
- attribute \src "ls180.v:2547.6-2547.32"
+ attribute \src "ls180.v:2543.6-2543.32"
wire \builder_csrbank13_txfull_r
- attribute \src "ls180.v:2546.6-2546.33"
+ attribute \src "ls180.v:2542.6-2542.33"
wire \builder_csrbank13_txfull_re
- attribute \src "ls180.v:2549.6-2549.32"
+ attribute \src "ls180.v:2545.6-2545.32"
wire \builder_csrbank13_txfull_w
- attribute \src "ls180.v:2548.6-2548.33"
+ attribute \src "ls180.v:2544.6-2544.33"
wire \builder_csrbank13_txfull_we
- attribute \src "ls180.v:2587.6-2587.27"
+ attribute \src "ls180.v:2583.6-2583.27"
wire \builder_csrbank14_sel
- attribute \src "ls180.v:2584.12-2584.44"
+ attribute \src "ls180.v:2580.12-2580.44"
wire width 8 \builder_csrbank14_tuning_word0_r
- attribute \src "ls180.v:2583.6-2583.39"
+ attribute \src "ls180.v:2579.6-2579.39"
wire \builder_csrbank14_tuning_word0_re
- attribute \src "ls180.v:2586.12-2586.44"
+ attribute \src "ls180.v:2582.12-2582.44"
wire width 8 \builder_csrbank14_tuning_word0_w
- attribute \src "ls180.v:2585.6-2585.39"
+ attribute \src "ls180.v:2581.6-2581.39"
wire \builder_csrbank14_tuning_word0_we
- attribute \src "ls180.v:2580.12-2580.44"
+ attribute \src "ls180.v:2576.12-2576.44"
wire width 8 \builder_csrbank14_tuning_word1_r
- attribute \src "ls180.v:2579.6-2579.39"
+ attribute \src "ls180.v:2575.6-2575.39"
wire \builder_csrbank14_tuning_word1_re
- attribute \src "ls180.v:2582.12-2582.44"
+ attribute \src "ls180.v:2578.12-2578.44"
wire width 8 \builder_csrbank14_tuning_word1_w
- attribute \src "ls180.v:2581.6-2581.39"
+ attribute \src "ls180.v:2577.6-2577.39"
wire \builder_csrbank14_tuning_word1_we
- attribute \src "ls180.v:2576.12-2576.44"
+ attribute \src "ls180.v:2572.12-2572.44"
wire width 8 \builder_csrbank14_tuning_word2_r
- attribute \src "ls180.v:2575.6-2575.39"
+ attribute \src "ls180.v:2571.6-2571.39"
wire \builder_csrbank14_tuning_word2_re
- attribute \src "ls180.v:2578.12-2578.44"
+ attribute \src "ls180.v:2574.12-2574.44"
wire width 8 \builder_csrbank14_tuning_word2_w
- attribute \src "ls180.v:2577.6-2577.39"
+ attribute \src "ls180.v:2573.6-2573.39"
wire \builder_csrbank14_tuning_word2_we
- attribute \src "ls180.v:2572.12-2572.44"
+ attribute \src "ls180.v:2568.12-2568.44"
wire width 8 \builder_csrbank14_tuning_word3_r
- attribute \src "ls180.v:2571.6-2571.39"
+ attribute \src "ls180.v:2567.6-2567.39"
wire \builder_csrbank14_tuning_word3_re
- attribute \src "ls180.v:2574.12-2574.44"
+ attribute \src "ls180.v:2570.12-2570.44"
wire width 8 \builder_csrbank14_tuning_word3_w
- attribute \src "ls180.v:2573.6-2573.39"
+ attribute \src "ls180.v:2569.6-2569.39"
wire \builder_csrbank14_tuning_word3_we
- attribute \src "ls180.v:1959.12-1959.34"
+ attribute \src "ls180.v:1955.12-1955.34"
wire width 8 \builder_csrbank1_in0_r
- attribute \src "ls180.v:1958.6-1958.29"
+ attribute \src "ls180.v:1954.6-1954.29"
wire \builder_csrbank1_in0_re
- attribute \src "ls180.v:1961.12-1961.34"
+ attribute \src "ls180.v:1957.12-1957.34"
wire width 8 \builder_csrbank1_in0_w
- attribute \src "ls180.v:1960.6-1960.29"
+ attribute \src "ls180.v:1956.6-1956.29"
wire \builder_csrbank1_in0_we
- attribute \src "ls180.v:1955.12-1955.34"
+ attribute \src "ls180.v:1951.12-1951.34"
wire width 8 \builder_csrbank1_in1_r
- attribute \src "ls180.v:1954.6-1954.29"
+ attribute \src "ls180.v:1950.6-1950.29"
wire \builder_csrbank1_in1_re
- attribute \src "ls180.v:1957.12-1957.34"
+ attribute \src "ls180.v:1953.12-1953.34"
wire width 8 \builder_csrbank1_in1_w
- attribute \src "ls180.v:1956.6-1956.29"
+ attribute \src "ls180.v:1952.6-1952.29"
wire \builder_csrbank1_in1_we
- attribute \src "ls180.v:1951.12-1951.34"
+ attribute \src "ls180.v:1947.12-1947.34"
wire width 8 \builder_csrbank1_oe0_r
- attribute \src "ls180.v:1950.6-1950.29"
+ attribute \src "ls180.v:1946.6-1946.29"
wire \builder_csrbank1_oe0_re
- attribute \src "ls180.v:1953.12-1953.34"
+ attribute \src "ls180.v:1949.12-1949.34"
wire width 8 \builder_csrbank1_oe0_w
- attribute \src "ls180.v:1952.6-1952.29"
+ attribute \src "ls180.v:1948.6-1948.29"
wire \builder_csrbank1_oe0_we
- attribute \src "ls180.v:1947.12-1947.34"
+ attribute \src "ls180.v:1943.12-1943.34"
wire width 8 \builder_csrbank1_oe1_r
- attribute \src "ls180.v:1946.6-1946.29"
+ attribute \src "ls180.v:1942.6-1942.29"
wire \builder_csrbank1_oe1_re
- attribute \src "ls180.v:1949.12-1949.34"
+ attribute \src "ls180.v:1945.12-1945.34"
wire width 8 \builder_csrbank1_oe1_w
- attribute \src "ls180.v:1948.6-1948.29"
+ attribute \src "ls180.v:1944.6-1944.29"
wire \builder_csrbank1_oe1_we
- attribute \src "ls180.v:1967.12-1967.35"
+ attribute \src "ls180.v:1963.12-1963.35"
wire width 8 \builder_csrbank1_out0_r
- attribute \src "ls180.v:1966.6-1966.30"
+ attribute \src "ls180.v:1962.6-1962.30"
wire \builder_csrbank1_out0_re
- attribute \src "ls180.v:1969.12-1969.35"
+ attribute \src "ls180.v:1965.12-1965.35"
wire width 8 \builder_csrbank1_out0_w
- attribute \src "ls180.v:1968.6-1968.30"
+ attribute \src "ls180.v:1964.6-1964.30"
wire \builder_csrbank1_out0_we
- attribute \src "ls180.v:1963.12-1963.35"
+ attribute \src "ls180.v:1959.12-1959.35"
wire width 8 \builder_csrbank1_out1_r
- attribute \src "ls180.v:1962.6-1962.30"
+ attribute \src "ls180.v:1958.6-1958.30"
wire \builder_csrbank1_out1_re
- attribute \src "ls180.v:1965.12-1965.35"
+ attribute \src "ls180.v:1961.12-1961.35"
wire width 8 \builder_csrbank1_out1_w
- attribute \src "ls180.v:1964.6-1964.30"
+ attribute \src "ls180.v:1960.6-1960.30"
wire \builder_csrbank1_out1_we
- attribute \src "ls180.v:1970.6-1970.26"
+ attribute \src "ls180.v:1966.6-1966.26"
wire \builder_csrbank1_sel
- attribute \src "ls180.v:1980.6-1980.26"
+ attribute \src "ls180.v:1976.6-1976.26"
wire \builder_csrbank2_r_r
- attribute \src "ls180.v:1979.6-1979.27"
+ attribute \src "ls180.v:1975.6-1975.27"
wire \builder_csrbank2_r_re
- attribute \src "ls180.v:1982.6-1982.26"
+ attribute \src "ls180.v:1978.6-1978.26"
wire \builder_csrbank2_r_w
- attribute \src "ls180.v:1981.6-1981.27"
+ attribute \src "ls180.v:1977.6-1977.27"
wire \builder_csrbank2_r_we
- attribute \src "ls180.v:1983.6-1983.26"
+ attribute \src "ls180.v:1979.6-1979.26"
wire \builder_csrbank2_sel
- attribute \src "ls180.v:1976.12-1976.33"
+ attribute \src "ls180.v:1972.12-1972.33"
wire width 3 \builder_csrbank2_w0_r
- attribute \src "ls180.v:1975.6-1975.28"
+ attribute \src "ls180.v:1971.6-1971.28"
wire \builder_csrbank2_w0_re
- attribute \src "ls180.v:1978.12-1978.33"
+ attribute \src "ls180.v:1974.12-1974.33"
wire width 3 \builder_csrbank2_w0_w
- attribute \src "ls180.v:1977.6-1977.28"
+ attribute \src "ls180.v:1973.6-1973.28"
wire \builder_csrbank2_w0_we
- attribute \src "ls180.v:1989.6-1989.32"
+ attribute \src "ls180.v:1985.6-1985.32"
wire \builder_csrbank3_enable0_r
- attribute \src "ls180.v:1988.6-1988.33"
+ attribute \src "ls180.v:1984.6-1984.33"
wire \builder_csrbank3_enable0_re
- attribute \src "ls180.v:1991.6-1991.32"
+ attribute \src "ls180.v:1987.6-1987.32"
wire \builder_csrbank3_enable0_w
- attribute \src "ls180.v:1990.6-1990.33"
+ attribute \src "ls180.v:1986.6-1986.33"
wire \builder_csrbank3_enable0_we
- attribute \src "ls180.v:2021.12-2021.38"
+ attribute \src "ls180.v:2017.12-2017.38"
wire width 8 \builder_csrbank3_period0_r
- attribute \src "ls180.v:2020.6-2020.33"
+ attribute \src "ls180.v:2016.6-2016.33"
wire \builder_csrbank3_period0_re
- attribute \src "ls180.v:2023.12-2023.38"
+ attribute \src "ls180.v:2019.12-2019.38"
wire width 8 \builder_csrbank3_period0_w
- attribute \src "ls180.v:2022.6-2022.33"
+ attribute \src "ls180.v:2018.6-2018.33"
wire \builder_csrbank3_period0_we
- attribute \src "ls180.v:2017.12-2017.38"
+ attribute \src "ls180.v:2013.12-2013.38"
wire width 8 \builder_csrbank3_period1_r
- attribute \src "ls180.v:2016.6-2016.33"
+ attribute \src "ls180.v:2012.6-2012.33"
wire \builder_csrbank3_period1_re
- attribute \src "ls180.v:2019.12-2019.38"
+ attribute \src "ls180.v:2015.12-2015.38"
wire width 8 \builder_csrbank3_period1_w
- attribute \src "ls180.v:2018.6-2018.33"
+ attribute \src "ls180.v:2014.6-2014.33"
wire \builder_csrbank3_period1_we
- attribute \src "ls180.v:2013.12-2013.38"
+ attribute \src "ls180.v:2009.12-2009.38"
wire width 8 \builder_csrbank3_period2_r
- attribute \src "ls180.v:2012.6-2012.33"
+ attribute \src "ls180.v:2008.6-2008.33"
wire \builder_csrbank3_period2_re
- attribute \src "ls180.v:2015.12-2015.38"
+ attribute \src "ls180.v:2011.12-2011.38"
wire width 8 \builder_csrbank3_period2_w
- attribute \src "ls180.v:2014.6-2014.33"
+ attribute \src "ls180.v:2010.6-2010.33"
wire \builder_csrbank3_period2_we
- attribute \src "ls180.v:2009.12-2009.38"
+ attribute \src "ls180.v:2005.12-2005.38"
wire width 8 \builder_csrbank3_period3_r
- attribute \src "ls180.v:2008.6-2008.33"
+ attribute \src "ls180.v:2004.6-2004.33"
wire \builder_csrbank3_period3_re
- attribute \src "ls180.v:2011.12-2011.38"
+ attribute \src "ls180.v:2007.12-2007.38"
wire width 8 \builder_csrbank3_period3_w
- attribute \src "ls180.v:2010.6-2010.33"
+ attribute \src "ls180.v:2006.6-2006.33"
wire \builder_csrbank3_period3_we
- attribute \src "ls180.v:2024.6-2024.26"
+ attribute \src "ls180.v:2020.6-2020.26"
wire \builder_csrbank3_sel
- attribute \src "ls180.v:2005.12-2005.37"
+ attribute \src "ls180.v:2001.12-2001.37"
wire width 8 \builder_csrbank3_width0_r
- attribute \src "ls180.v:2004.6-2004.32"
+ attribute \src "ls180.v:2000.6-2000.32"
wire \builder_csrbank3_width0_re
- attribute \src "ls180.v:2007.12-2007.37"
+ attribute \src "ls180.v:2003.12-2003.37"
wire width 8 \builder_csrbank3_width0_w
- attribute \src "ls180.v:2006.6-2006.32"
+ attribute \src "ls180.v:2002.6-2002.32"
wire \builder_csrbank3_width0_we
- attribute \src "ls180.v:2001.12-2001.37"
+ attribute \src "ls180.v:1997.12-1997.37"
wire width 8 \builder_csrbank3_width1_r
- attribute \src "ls180.v:2000.6-2000.32"
+ attribute \src "ls180.v:1996.6-1996.32"
wire \builder_csrbank3_width1_re
- attribute \src "ls180.v:2003.12-2003.37"
+ attribute \src "ls180.v:1999.12-1999.37"
wire width 8 \builder_csrbank3_width1_w
- attribute \src "ls180.v:2002.6-2002.32"
+ attribute \src "ls180.v:1998.6-1998.32"
wire \builder_csrbank3_width1_we
- attribute \src "ls180.v:1997.12-1997.37"
+ attribute \src "ls180.v:1993.12-1993.37"
wire width 8 \builder_csrbank3_width2_r
- attribute \src "ls180.v:1996.6-1996.32"
+ attribute \src "ls180.v:1992.6-1992.32"
wire \builder_csrbank3_width2_re
- attribute \src "ls180.v:1999.12-1999.37"
+ attribute \src "ls180.v:1995.12-1995.37"
wire width 8 \builder_csrbank3_width2_w
- attribute \src "ls180.v:1998.6-1998.32"
+ attribute \src "ls180.v:1994.6-1994.32"
wire \builder_csrbank3_width2_we
- attribute \src "ls180.v:1993.12-1993.37"
+ attribute \src "ls180.v:1989.12-1989.37"
wire width 8 \builder_csrbank3_width3_r
- attribute \src "ls180.v:1992.6-1992.32"
+ attribute \src "ls180.v:1988.6-1988.32"
wire \builder_csrbank3_width3_re
- attribute \src "ls180.v:1995.12-1995.37"
+ attribute \src "ls180.v:1991.12-1991.37"
wire width 8 \builder_csrbank3_width3_w
- attribute \src "ls180.v:1994.6-1994.32"
+ attribute \src "ls180.v:1990.6-1990.32"
wire \builder_csrbank3_width3_we
- attribute \src "ls180.v:2030.6-2030.32"
+ attribute \src "ls180.v:2026.6-2026.32"
wire \builder_csrbank4_enable0_r
- attribute \src "ls180.v:2029.6-2029.33"
+ attribute \src "ls180.v:2025.6-2025.33"
wire \builder_csrbank4_enable0_re
- attribute \src "ls180.v:2032.6-2032.32"
+ attribute \src "ls180.v:2028.6-2028.32"
wire \builder_csrbank4_enable0_w
- attribute \src "ls180.v:2031.6-2031.33"
+ attribute \src "ls180.v:2027.6-2027.33"
wire \builder_csrbank4_enable0_we
- attribute \src "ls180.v:2062.12-2062.38"
+ attribute \src "ls180.v:2058.12-2058.38"
wire width 8 \builder_csrbank4_period0_r
- attribute \src "ls180.v:2061.6-2061.33"
+ attribute \src "ls180.v:2057.6-2057.33"
wire \builder_csrbank4_period0_re
- attribute \src "ls180.v:2064.12-2064.38"
+ attribute \src "ls180.v:2060.12-2060.38"
wire width 8 \builder_csrbank4_period0_w
- attribute \src "ls180.v:2063.6-2063.33"
+ attribute \src "ls180.v:2059.6-2059.33"
wire \builder_csrbank4_period0_we
- attribute \src "ls180.v:2058.12-2058.38"
+ attribute \src "ls180.v:2054.12-2054.38"
wire width 8 \builder_csrbank4_period1_r
- attribute \src "ls180.v:2057.6-2057.33"
+ attribute \src "ls180.v:2053.6-2053.33"
wire \builder_csrbank4_period1_re
- attribute \src "ls180.v:2060.12-2060.38"
+ attribute \src "ls180.v:2056.12-2056.38"
wire width 8 \builder_csrbank4_period1_w
- attribute \src "ls180.v:2059.6-2059.33"
+ attribute \src "ls180.v:2055.6-2055.33"
wire \builder_csrbank4_period1_we
- attribute \src "ls180.v:2054.12-2054.38"
+ attribute \src "ls180.v:2050.12-2050.38"
wire width 8 \builder_csrbank4_period2_r
- attribute \src "ls180.v:2053.6-2053.33"
+ attribute \src "ls180.v:2049.6-2049.33"
wire \builder_csrbank4_period2_re
- attribute \src "ls180.v:2056.12-2056.38"
+ attribute \src "ls180.v:2052.12-2052.38"
wire width 8 \builder_csrbank4_period2_w
- attribute \src "ls180.v:2055.6-2055.33"
+ attribute \src "ls180.v:2051.6-2051.33"
wire \builder_csrbank4_period2_we
- attribute \src "ls180.v:2050.12-2050.38"
+ attribute \src "ls180.v:2046.12-2046.38"
wire width 8 \builder_csrbank4_period3_r
- attribute \src "ls180.v:2049.6-2049.33"
+ attribute \src "ls180.v:2045.6-2045.33"
wire \builder_csrbank4_period3_re
- attribute \src "ls180.v:2052.12-2052.38"
+ attribute \src "ls180.v:2048.12-2048.38"
wire width 8 \builder_csrbank4_period3_w
- attribute \src "ls180.v:2051.6-2051.33"
+ attribute \src "ls180.v:2047.6-2047.33"
wire \builder_csrbank4_period3_we
- attribute \src "ls180.v:2065.6-2065.26"
+ attribute \src "ls180.v:2061.6-2061.26"
wire \builder_csrbank4_sel
- attribute \src "ls180.v:2046.12-2046.37"
+ attribute \src "ls180.v:2042.12-2042.37"
wire width 8 \builder_csrbank4_width0_r
- attribute \src "ls180.v:2045.6-2045.32"
+ attribute \src "ls180.v:2041.6-2041.32"
wire \builder_csrbank4_width0_re
- attribute \src "ls180.v:2048.12-2048.37"
+ attribute \src "ls180.v:2044.12-2044.37"
wire width 8 \builder_csrbank4_width0_w
- attribute \src "ls180.v:2047.6-2047.32"
+ attribute \src "ls180.v:2043.6-2043.32"
wire \builder_csrbank4_width0_we
- attribute \src "ls180.v:2042.12-2042.37"
+ attribute \src "ls180.v:2038.12-2038.37"
wire width 8 \builder_csrbank4_width1_r
- attribute \src "ls180.v:2041.6-2041.32"
+ attribute \src "ls180.v:2037.6-2037.32"
wire \builder_csrbank4_width1_re
- attribute \src "ls180.v:2044.12-2044.37"
+ attribute \src "ls180.v:2040.12-2040.37"
wire width 8 \builder_csrbank4_width1_w
- attribute \src "ls180.v:2043.6-2043.32"
+ attribute \src "ls180.v:2039.6-2039.32"
wire \builder_csrbank4_width1_we
- attribute \src "ls180.v:2038.12-2038.37"
+ attribute \src "ls180.v:2034.12-2034.37"
wire width 8 \builder_csrbank4_width2_r
- attribute \src "ls180.v:2037.6-2037.32"
+ attribute \src "ls180.v:2033.6-2033.32"
wire \builder_csrbank4_width2_re
- attribute \src "ls180.v:2040.12-2040.37"
+ attribute \src "ls180.v:2036.12-2036.37"
wire width 8 \builder_csrbank4_width2_w
- attribute \src "ls180.v:2039.6-2039.32"
+ attribute \src "ls180.v:2035.6-2035.32"
wire \builder_csrbank4_width2_we
- attribute \src "ls180.v:2034.12-2034.37"
+ attribute \src "ls180.v:2030.12-2030.37"
wire width 8 \builder_csrbank4_width3_r
- attribute \src "ls180.v:2033.6-2033.32"
+ attribute \src "ls180.v:2029.6-2029.32"
wire \builder_csrbank4_width3_re
- attribute \src "ls180.v:2036.12-2036.37"
+ attribute \src "ls180.v:2032.12-2032.37"
wire width 8 \builder_csrbank4_width3_w
- attribute \src "ls180.v:2035.6-2035.32"
+ attribute \src "ls180.v:2031.6-2031.32"
wire \builder_csrbank4_width3_we
- attribute \src "ls180.v:2099.12-2099.40"
+ attribute \src "ls180.v:2095.12-2095.40"
wire width 8 \builder_csrbank5_dma_base0_r
- attribute \src "ls180.v:2098.6-2098.35"
+ attribute \src "ls180.v:2094.6-2094.35"
wire \builder_csrbank5_dma_base0_re
- attribute \src "ls180.v:2101.12-2101.40"
+ attribute \src "ls180.v:2097.12-2097.40"
wire width 8 \builder_csrbank5_dma_base0_w
- attribute \src "ls180.v:2100.6-2100.35"
+ attribute \src "ls180.v:2096.6-2096.35"
wire \builder_csrbank5_dma_base0_we
- attribute \src "ls180.v:2095.12-2095.40"
+ attribute \src "ls180.v:2091.12-2091.40"
wire width 8 \builder_csrbank5_dma_base1_r
- attribute \src "ls180.v:2094.6-2094.35"
+ attribute \src "ls180.v:2090.6-2090.35"
wire \builder_csrbank5_dma_base1_re
- attribute \src "ls180.v:2097.12-2097.40"
+ attribute \src "ls180.v:2093.12-2093.40"
wire width 8 \builder_csrbank5_dma_base1_w
- attribute \src "ls180.v:2096.6-2096.35"
+ attribute \src "ls180.v:2092.6-2092.35"
wire \builder_csrbank5_dma_base1_we
- attribute \src "ls180.v:2091.12-2091.40"
+ attribute \src "ls180.v:2087.12-2087.40"
wire width 8 \builder_csrbank5_dma_base2_r
- attribute \src "ls180.v:2090.6-2090.35"
+ attribute \src "ls180.v:2086.6-2086.35"
wire \builder_csrbank5_dma_base2_re
- attribute \src "ls180.v:2093.12-2093.40"
+ attribute \src "ls180.v:2089.12-2089.40"
wire width 8 \builder_csrbank5_dma_base2_w
- attribute \src "ls180.v:2092.6-2092.35"
+ attribute \src "ls180.v:2088.6-2088.35"
wire \builder_csrbank5_dma_base2_we
- attribute \src "ls180.v:2087.12-2087.40"
+ attribute \src "ls180.v:2083.12-2083.40"
wire width 8 \builder_csrbank5_dma_base3_r
- attribute \src "ls180.v:2086.6-2086.35"
+ attribute \src "ls180.v:2082.6-2082.35"
wire \builder_csrbank5_dma_base3_re
- attribute \src "ls180.v:2089.12-2089.40"
+ attribute \src "ls180.v:2085.12-2085.40"
wire width 8 \builder_csrbank5_dma_base3_w
- attribute \src "ls180.v:2088.6-2088.35"
+ attribute \src "ls180.v:2084.6-2084.35"
wire \builder_csrbank5_dma_base3_we
- attribute \src "ls180.v:2083.12-2083.40"
+ attribute \src "ls180.v:2079.12-2079.40"
wire width 8 \builder_csrbank5_dma_base4_r
- attribute \src "ls180.v:2082.6-2082.35"
+ attribute \src "ls180.v:2078.6-2078.35"
wire \builder_csrbank5_dma_base4_re
- attribute \src "ls180.v:2085.12-2085.40"
+ attribute \src "ls180.v:2081.12-2081.40"
wire width 8 \builder_csrbank5_dma_base4_w
- attribute \src "ls180.v:2084.6-2084.35"
+ attribute \src "ls180.v:2080.6-2080.35"
wire \builder_csrbank5_dma_base4_we
- attribute \src "ls180.v:2079.12-2079.40"
+ attribute \src "ls180.v:2075.12-2075.40"
wire width 8 \builder_csrbank5_dma_base5_r
- attribute \src "ls180.v:2078.6-2078.35"
+ attribute \src "ls180.v:2074.6-2074.35"
wire \builder_csrbank5_dma_base5_re
- attribute \src "ls180.v:2081.12-2081.40"
+ attribute \src "ls180.v:2077.12-2077.40"
wire width 8 \builder_csrbank5_dma_base5_w
- attribute \src "ls180.v:2080.6-2080.35"
+ attribute \src "ls180.v:2076.6-2076.35"
wire \builder_csrbank5_dma_base5_we
- attribute \src "ls180.v:2075.12-2075.40"
+ attribute \src "ls180.v:2071.12-2071.40"
wire width 8 \builder_csrbank5_dma_base6_r
- attribute \src "ls180.v:2074.6-2074.35"
+ attribute \src "ls180.v:2070.6-2070.35"
wire \builder_csrbank5_dma_base6_re
- attribute \src "ls180.v:2077.12-2077.40"
+ attribute \src "ls180.v:2073.12-2073.40"
wire width 8 \builder_csrbank5_dma_base6_w
- attribute \src "ls180.v:2076.6-2076.35"
+ attribute \src "ls180.v:2072.6-2072.35"
wire \builder_csrbank5_dma_base6_we
- attribute \src "ls180.v:2071.12-2071.40"
+ attribute \src "ls180.v:2067.12-2067.40"
wire width 8 \builder_csrbank5_dma_base7_r
- attribute \src "ls180.v:2070.6-2070.35"
+ attribute \src "ls180.v:2066.6-2066.35"
wire \builder_csrbank5_dma_base7_re
- attribute \src "ls180.v:2073.12-2073.40"
+ attribute \src "ls180.v:2069.12-2069.40"
wire width 8 \builder_csrbank5_dma_base7_w
- attribute \src "ls180.v:2072.6-2072.35"
+ attribute \src "ls180.v:2068.6-2068.35"
wire \builder_csrbank5_dma_base7_we
- attribute \src "ls180.v:2123.6-2123.33"
+ attribute \src "ls180.v:2119.6-2119.33"
wire \builder_csrbank5_dma_done_r
- attribute \src "ls180.v:2122.6-2122.34"
+ attribute \src "ls180.v:2118.6-2118.34"
wire \builder_csrbank5_dma_done_re
- attribute \src "ls180.v:2125.6-2125.33"
+ attribute \src "ls180.v:2121.6-2121.33"
wire \builder_csrbank5_dma_done_w
- attribute \src "ls180.v:2124.6-2124.34"
+ attribute \src "ls180.v:2120.6-2120.34"
wire \builder_csrbank5_dma_done_we
- attribute \src "ls180.v:2119.6-2119.36"
+ attribute \src "ls180.v:2115.6-2115.36"
wire \builder_csrbank5_dma_enable0_r
- attribute \src "ls180.v:2118.6-2118.37"
+ attribute \src "ls180.v:2114.6-2114.37"
wire \builder_csrbank5_dma_enable0_re
- attribute \src "ls180.v:2121.6-2121.36"
+ attribute \src "ls180.v:2117.6-2117.36"
wire \builder_csrbank5_dma_enable0_w
- attribute \src "ls180.v:2120.6-2120.37"
+ attribute \src "ls180.v:2116.6-2116.37"
wire \builder_csrbank5_dma_enable0_we
- attribute \src "ls180.v:2115.12-2115.42"
+ attribute \src "ls180.v:2111.12-2111.42"
wire width 8 \builder_csrbank5_dma_length0_r
- attribute \src "ls180.v:2114.6-2114.37"
+ attribute \src "ls180.v:2110.6-2110.37"
wire \builder_csrbank5_dma_length0_re
- attribute \src "ls180.v:2117.12-2117.42"
+ attribute \src "ls180.v:2113.12-2113.42"
wire width 8 \builder_csrbank5_dma_length0_w
- attribute \src "ls180.v:2116.6-2116.37"
+ attribute \src "ls180.v:2112.6-2112.37"
wire \builder_csrbank5_dma_length0_we
- attribute \src "ls180.v:2111.12-2111.42"
+ attribute \src "ls180.v:2107.12-2107.42"
wire width 8 \builder_csrbank5_dma_length1_r
- attribute \src "ls180.v:2110.6-2110.37"
+ attribute \src "ls180.v:2106.6-2106.37"
wire \builder_csrbank5_dma_length1_re
- attribute \src "ls180.v:2113.12-2113.42"
+ attribute \src "ls180.v:2109.12-2109.42"
wire width 8 \builder_csrbank5_dma_length1_w
- attribute \src "ls180.v:2112.6-2112.37"
+ attribute \src "ls180.v:2108.6-2108.37"
wire \builder_csrbank5_dma_length1_we
- attribute \src "ls180.v:2107.12-2107.42"
+ attribute \src "ls180.v:2103.12-2103.42"
wire width 8 \builder_csrbank5_dma_length2_r
- attribute \src "ls180.v:2106.6-2106.37"
+ attribute \src "ls180.v:2102.6-2102.37"
wire \builder_csrbank5_dma_length2_re
- attribute \src "ls180.v:2109.12-2109.42"
+ attribute \src "ls180.v:2105.12-2105.42"
wire width 8 \builder_csrbank5_dma_length2_w
- attribute \src "ls180.v:2108.6-2108.37"
+ attribute \src "ls180.v:2104.6-2104.37"
wire \builder_csrbank5_dma_length2_we
- attribute \src "ls180.v:2103.12-2103.42"
+ attribute \src "ls180.v:2099.12-2099.42"
wire width 8 \builder_csrbank5_dma_length3_r
- attribute \src "ls180.v:2102.6-2102.37"
+ attribute \src "ls180.v:2098.6-2098.37"
wire \builder_csrbank5_dma_length3_re
- attribute \src "ls180.v:2105.12-2105.42"
+ attribute \src "ls180.v:2101.12-2101.42"
wire width 8 \builder_csrbank5_dma_length3_w
- attribute \src "ls180.v:2104.6-2104.37"
+ attribute \src "ls180.v:2100.6-2100.37"
wire \builder_csrbank5_dma_length3_we
- attribute \src "ls180.v:2127.6-2127.34"
+ attribute \src "ls180.v:2123.6-2123.34"
wire \builder_csrbank5_dma_loop0_r
- attribute \src "ls180.v:2126.6-2126.35"
+ attribute \src "ls180.v:2122.6-2122.35"
wire \builder_csrbank5_dma_loop0_re
- attribute \src "ls180.v:2129.6-2129.34"
+ attribute \src "ls180.v:2125.6-2125.34"
wire \builder_csrbank5_dma_loop0_w
- attribute \src "ls180.v:2128.6-2128.35"
+ attribute \src "ls180.v:2124.6-2124.35"
wire \builder_csrbank5_dma_loop0_we
- attribute \src "ls180.v:2130.6-2130.26"
+ attribute \src "ls180.v:2126.6-2126.26"
wire \builder_csrbank5_sel
- attribute \src "ls180.v:2260.12-2260.43"
+ attribute \src "ls180.v:2256.12-2256.43"
wire width 8 \builder_csrbank6_block_count0_r
- attribute \src "ls180.v:2259.6-2259.38"
+ attribute \src "ls180.v:2255.6-2255.38"
wire \builder_csrbank6_block_count0_re
- attribute \src "ls180.v:2262.12-2262.43"
+ attribute \src "ls180.v:2258.12-2258.43"
wire width 8 \builder_csrbank6_block_count0_w
- attribute \src "ls180.v:2261.6-2261.38"
+ attribute \src "ls180.v:2257.6-2257.38"
wire \builder_csrbank6_block_count0_we
- attribute \src "ls180.v:2256.12-2256.43"
+ attribute \src "ls180.v:2252.12-2252.43"
wire width 8 \builder_csrbank6_block_count1_r
- attribute \src "ls180.v:2255.6-2255.38"
+ attribute \src "ls180.v:2251.6-2251.38"
wire \builder_csrbank6_block_count1_re
- attribute \src "ls180.v:2258.12-2258.43"
+ attribute \src "ls180.v:2254.12-2254.43"
wire width 8 \builder_csrbank6_block_count1_w
- attribute \src "ls180.v:2257.6-2257.38"
+ attribute \src "ls180.v:2253.6-2253.38"
wire \builder_csrbank6_block_count1_we
- attribute \src "ls180.v:2252.12-2252.43"
+ attribute \src "ls180.v:2248.12-2248.43"
wire width 8 \builder_csrbank6_block_count2_r
- attribute \src "ls180.v:2251.6-2251.38"
+ attribute \src "ls180.v:2247.6-2247.38"
wire \builder_csrbank6_block_count2_re
- attribute \src "ls180.v:2254.12-2254.43"
+ attribute \src "ls180.v:2250.12-2250.43"
wire width 8 \builder_csrbank6_block_count2_w
- attribute \src "ls180.v:2253.6-2253.38"
+ attribute \src "ls180.v:2249.6-2249.38"
wire \builder_csrbank6_block_count2_we
- attribute \src "ls180.v:2248.12-2248.43"
+ attribute \src "ls180.v:2244.12-2244.43"
wire width 8 \builder_csrbank6_block_count3_r
- attribute \src "ls180.v:2247.6-2247.38"
+ attribute \src "ls180.v:2243.6-2243.38"
wire \builder_csrbank6_block_count3_re
- attribute \src "ls180.v:2250.12-2250.43"
+ attribute \src "ls180.v:2246.12-2246.43"
wire width 8 \builder_csrbank6_block_count3_w
- attribute \src "ls180.v:2249.6-2249.38"
+ attribute \src "ls180.v:2245.6-2245.38"
wire \builder_csrbank6_block_count3_we
- attribute \src "ls180.v:2244.12-2244.44"
+ attribute \src "ls180.v:2240.12-2240.44"
wire width 8 \builder_csrbank6_block_length0_r
- attribute \src "ls180.v:2243.6-2243.39"
+ attribute \src "ls180.v:2239.6-2239.39"
wire \builder_csrbank6_block_length0_re
- attribute \src "ls180.v:2246.12-2246.44"
+ attribute \src "ls180.v:2242.12-2242.44"
wire width 8 \builder_csrbank6_block_length0_w
- attribute \src "ls180.v:2245.6-2245.39"
+ attribute \src "ls180.v:2241.6-2241.39"
wire \builder_csrbank6_block_length0_we
- attribute \src "ls180.v:2240.12-2240.44"
+ attribute \src "ls180.v:2236.12-2236.44"
wire width 2 \builder_csrbank6_block_length1_r
- attribute \src "ls180.v:2239.6-2239.39"
+ attribute \src "ls180.v:2235.6-2235.39"
wire \builder_csrbank6_block_length1_re
- attribute \src "ls180.v:2242.12-2242.44"
+ attribute \src "ls180.v:2238.12-2238.44"
wire width 2 \builder_csrbank6_block_length1_w
- attribute \src "ls180.v:2241.6-2241.39"
+ attribute \src "ls180.v:2237.6-2237.39"
wire \builder_csrbank6_block_length1_we
- attribute \src "ls180.v:2148.12-2148.44"
+ attribute \src "ls180.v:2144.12-2144.44"
wire width 8 \builder_csrbank6_cmd_argument0_r
- attribute \src "ls180.v:2147.6-2147.39"
+ attribute \src "ls180.v:2143.6-2143.39"
wire \builder_csrbank6_cmd_argument0_re
- attribute \src "ls180.v:2150.12-2150.44"
+ attribute \src "ls180.v:2146.12-2146.44"
wire width 8 \builder_csrbank6_cmd_argument0_w
- attribute \src "ls180.v:2149.6-2149.39"
+ attribute \src "ls180.v:2145.6-2145.39"
wire \builder_csrbank6_cmd_argument0_we
- attribute \src "ls180.v:2144.12-2144.44"
+ attribute \src "ls180.v:2140.12-2140.44"
wire width 8 \builder_csrbank6_cmd_argument1_r
- attribute \src "ls180.v:2143.6-2143.39"
+ attribute \src "ls180.v:2139.6-2139.39"
wire \builder_csrbank6_cmd_argument1_re
- attribute \src "ls180.v:2146.12-2146.44"
+ attribute \src "ls180.v:2142.12-2142.44"
wire width 8 \builder_csrbank6_cmd_argument1_w
- attribute \src "ls180.v:2145.6-2145.39"
+ attribute \src "ls180.v:2141.6-2141.39"
wire \builder_csrbank6_cmd_argument1_we
- attribute \src "ls180.v:2140.12-2140.44"
+ attribute \src "ls180.v:2136.12-2136.44"
wire width 8 \builder_csrbank6_cmd_argument2_r
- attribute \src "ls180.v:2139.6-2139.39"
+ attribute \src "ls180.v:2135.6-2135.39"
wire \builder_csrbank6_cmd_argument2_re
- attribute \src "ls180.v:2142.12-2142.44"
+ attribute \src "ls180.v:2138.12-2138.44"
wire width 8 \builder_csrbank6_cmd_argument2_w
- attribute \src "ls180.v:2141.6-2141.39"
+ attribute \src "ls180.v:2137.6-2137.39"
wire \builder_csrbank6_cmd_argument2_we
- attribute \src "ls180.v:2136.12-2136.44"
+ attribute \src "ls180.v:2132.12-2132.44"
wire width 8 \builder_csrbank6_cmd_argument3_r
- attribute \src "ls180.v:2135.6-2135.39"
+ attribute \src "ls180.v:2131.6-2131.39"
wire \builder_csrbank6_cmd_argument3_re
- attribute \src "ls180.v:2138.12-2138.44"
+ attribute \src "ls180.v:2134.12-2134.44"
wire width 8 \builder_csrbank6_cmd_argument3_w
- attribute \src "ls180.v:2137.6-2137.39"
+ attribute \src "ls180.v:2133.6-2133.39"
wire \builder_csrbank6_cmd_argument3_we
- attribute \src "ls180.v:2164.12-2164.43"
+ attribute \src "ls180.v:2160.12-2160.43"
wire width 8 \builder_csrbank6_cmd_command0_r
- attribute \src "ls180.v:2163.6-2163.38"
+ attribute \src "ls180.v:2159.6-2159.38"
wire \builder_csrbank6_cmd_command0_re
- attribute \src "ls180.v:2166.12-2166.43"
+ attribute \src "ls180.v:2162.12-2162.43"
wire width 8 \builder_csrbank6_cmd_command0_w
- attribute \src "ls180.v:2165.6-2165.38"
+ attribute \src "ls180.v:2161.6-2161.38"
wire \builder_csrbank6_cmd_command0_we
- attribute \src "ls180.v:2160.12-2160.43"
+ attribute \src "ls180.v:2156.12-2156.43"
wire width 8 \builder_csrbank6_cmd_command1_r
- attribute \src "ls180.v:2159.6-2159.38"
+ attribute \src "ls180.v:2155.6-2155.38"
wire \builder_csrbank6_cmd_command1_re
- attribute \src "ls180.v:2162.12-2162.43"
+ attribute \src "ls180.v:2158.12-2158.43"
wire width 8 \builder_csrbank6_cmd_command1_w
- attribute \src "ls180.v:2161.6-2161.38"
+ attribute \src "ls180.v:2157.6-2157.38"
wire \builder_csrbank6_cmd_command1_we
- attribute \src "ls180.v:2156.12-2156.43"
+ attribute \src "ls180.v:2152.12-2152.43"
wire width 8 \builder_csrbank6_cmd_command2_r
- attribute \src "ls180.v:2155.6-2155.38"
+ attribute \src "ls180.v:2151.6-2151.38"
wire \builder_csrbank6_cmd_command2_re
- attribute \src "ls180.v:2158.12-2158.43"
+ attribute \src "ls180.v:2154.12-2154.43"
wire width 8 \builder_csrbank6_cmd_command2_w
- attribute \src "ls180.v:2157.6-2157.38"
+ attribute \src "ls180.v:2153.6-2153.38"
wire \builder_csrbank6_cmd_command2_we
- attribute \src "ls180.v:2152.12-2152.43"
+ attribute \src "ls180.v:2148.12-2148.43"
wire width 8 \builder_csrbank6_cmd_command3_r
- attribute \src "ls180.v:2151.6-2151.38"
+ attribute \src "ls180.v:2147.6-2147.38"
wire \builder_csrbank6_cmd_command3_re
- attribute \src "ls180.v:2154.12-2154.43"
+ attribute \src "ls180.v:2150.12-2150.43"
wire width 8 \builder_csrbank6_cmd_command3_w
- attribute \src "ls180.v:2153.6-2153.38"
+ attribute \src "ls180.v:2149.6-2149.38"
wire \builder_csrbank6_cmd_command3_we
- attribute \src "ls180.v:2232.12-2232.40"
+ attribute \src "ls180.v:2228.12-2228.40"
wire width 4 \builder_csrbank6_cmd_event_r
- attribute \src "ls180.v:2231.6-2231.35"
+ attribute \src "ls180.v:2227.6-2227.35"
wire \builder_csrbank6_cmd_event_re
- attribute \src "ls180.v:2234.12-2234.40"
+ attribute \src "ls180.v:2230.12-2230.40"
wire width 4 \builder_csrbank6_cmd_event_w
- attribute \src "ls180.v:2233.6-2233.35"
+ attribute \src "ls180.v:2229.6-2229.35"
wire \builder_csrbank6_cmd_event_we
- attribute \src "ls180.v:2228.12-2228.44"
+ attribute \src "ls180.v:2224.12-2224.44"
wire width 8 \builder_csrbank6_cmd_response0_r
- attribute \src "ls180.v:2227.6-2227.39"
+ attribute \src "ls180.v:2223.6-2223.39"
wire \builder_csrbank6_cmd_response0_re
- attribute \src "ls180.v:2230.12-2230.44"
+ attribute \src "ls180.v:2226.12-2226.44"
wire width 8 \builder_csrbank6_cmd_response0_w
- attribute \src "ls180.v:2229.6-2229.39"
+ attribute \src "ls180.v:2225.6-2225.39"
wire \builder_csrbank6_cmd_response0_we
- attribute \src "ls180.v:2188.12-2188.45"
+ attribute \src "ls180.v:2184.12-2184.45"
wire width 8 \builder_csrbank6_cmd_response10_r
- attribute \src "ls180.v:2187.6-2187.40"
+ attribute \src "ls180.v:2183.6-2183.40"
wire \builder_csrbank6_cmd_response10_re
- attribute \src "ls180.v:2190.12-2190.45"
+ attribute \src "ls180.v:2186.12-2186.45"
wire width 8 \builder_csrbank6_cmd_response10_w
- attribute \src "ls180.v:2189.6-2189.40"
+ attribute \src "ls180.v:2185.6-2185.40"
wire \builder_csrbank6_cmd_response10_we
- attribute \src "ls180.v:2184.12-2184.45"
+ attribute \src "ls180.v:2180.12-2180.45"
wire width 8 \builder_csrbank6_cmd_response11_r
- attribute \src "ls180.v:2183.6-2183.40"
+ attribute \src "ls180.v:2179.6-2179.40"
wire \builder_csrbank6_cmd_response11_re
- attribute \src "ls180.v:2186.12-2186.45"
+ attribute \src "ls180.v:2182.12-2182.45"
wire width 8 \builder_csrbank6_cmd_response11_w
- attribute \src "ls180.v:2185.6-2185.40"
+ attribute \src "ls180.v:2181.6-2181.40"
wire \builder_csrbank6_cmd_response11_we
- attribute \src "ls180.v:2180.12-2180.45"
+ attribute \src "ls180.v:2176.12-2176.45"
wire width 8 \builder_csrbank6_cmd_response12_r
- attribute \src "ls180.v:2179.6-2179.40"
+ attribute \src "ls180.v:2175.6-2175.40"
wire \builder_csrbank6_cmd_response12_re
- attribute \src "ls180.v:2182.12-2182.45"
+ attribute \src "ls180.v:2178.12-2178.45"
wire width 8 \builder_csrbank6_cmd_response12_w
- attribute \src "ls180.v:2181.6-2181.40"
+ attribute \src "ls180.v:2177.6-2177.40"
wire \builder_csrbank6_cmd_response12_we
- attribute \src "ls180.v:2176.12-2176.45"
+ attribute \src "ls180.v:2172.12-2172.45"
wire width 8 \builder_csrbank6_cmd_response13_r
- attribute \src "ls180.v:2175.6-2175.40"
+ attribute \src "ls180.v:2171.6-2171.40"
wire \builder_csrbank6_cmd_response13_re
- attribute \src "ls180.v:2178.12-2178.45"
+ attribute \src "ls180.v:2174.12-2174.45"
wire width 8 \builder_csrbank6_cmd_response13_w
- attribute \src "ls180.v:2177.6-2177.40"
+ attribute \src "ls180.v:2173.6-2173.40"
wire \builder_csrbank6_cmd_response13_we
- attribute \src "ls180.v:2172.12-2172.45"
+ attribute \src "ls180.v:2168.12-2168.45"
wire width 8 \builder_csrbank6_cmd_response14_r
- attribute \src "ls180.v:2171.6-2171.40"
+ attribute \src "ls180.v:2167.6-2167.40"
wire \builder_csrbank6_cmd_response14_re
- attribute \src "ls180.v:2174.12-2174.45"
+ attribute \src "ls180.v:2170.12-2170.45"
wire width 8 \builder_csrbank6_cmd_response14_w
- attribute \src "ls180.v:2173.6-2173.40"
+ attribute \src "ls180.v:2169.6-2169.40"
wire \builder_csrbank6_cmd_response14_we
- attribute \src "ls180.v:2168.12-2168.45"
+ attribute \src "ls180.v:2164.12-2164.45"
wire width 8 \builder_csrbank6_cmd_response15_r
- attribute \src "ls180.v:2167.6-2167.40"
+ attribute \src "ls180.v:2163.6-2163.40"
wire \builder_csrbank6_cmd_response15_re
- attribute \src "ls180.v:2170.12-2170.45"
+ attribute \src "ls180.v:2166.12-2166.45"
wire width 8 \builder_csrbank6_cmd_response15_w
- attribute \src "ls180.v:2169.6-2169.40"
+ attribute \src "ls180.v:2165.6-2165.40"
wire \builder_csrbank6_cmd_response15_we
- attribute \src "ls180.v:2224.12-2224.44"
+ attribute \src "ls180.v:2220.12-2220.44"
wire width 8 \builder_csrbank6_cmd_response1_r
- attribute \src "ls180.v:2223.6-2223.39"
+ attribute \src "ls180.v:2219.6-2219.39"
wire \builder_csrbank6_cmd_response1_re
- attribute \src "ls180.v:2226.12-2226.44"
+ attribute \src "ls180.v:2222.12-2222.44"
wire width 8 \builder_csrbank6_cmd_response1_w
- attribute \src "ls180.v:2225.6-2225.39"
+ attribute \src "ls180.v:2221.6-2221.39"
wire \builder_csrbank6_cmd_response1_we
- attribute \src "ls180.v:2220.12-2220.44"
+ attribute \src "ls180.v:2216.12-2216.44"
wire width 8 \builder_csrbank6_cmd_response2_r
- attribute \src "ls180.v:2219.6-2219.39"
+ attribute \src "ls180.v:2215.6-2215.39"
wire \builder_csrbank6_cmd_response2_re
- attribute \src "ls180.v:2222.12-2222.44"
+ attribute \src "ls180.v:2218.12-2218.44"
wire width 8 \builder_csrbank6_cmd_response2_w
- attribute \src "ls180.v:2221.6-2221.39"
+ attribute \src "ls180.v:2217.6-2217.39"
wire \builder_csrbank6_cmd_response2_we
- attribute \src "ls180.v:2216.12-2216.44"
+ attribute \src "ls180.v:2212.12-2212.44"
wire width 8 \builder_csrbank6_cmd_response3_r
- attribute \src "ls180.v:2215.6-2215.39"
+ attribute \src "ls180.v:2211.6-2211.39"
wire \builder_csrbank6_cmd_response3_re
- attribute \src "ls180.v:2218.12-2218.44"
+ attribute \src "ls180.v:2214.12-2214.44"
wire width 8 \builder_csrbank6_cmd_response3_w
- attribute \src "ls180.v:2217.6-2217.39"
+ attribute \src "ls180.v:2213.6-2213.39"
wire \builder_csrbank6_cmd_response3_we
- attribute \src "ls180.v:2212.12-2212.44"
+ attribute \src "ls180.v:2208.12-2208.44"
wire width 8 \builder_csrbank6_cmd_response4_r
- attribute \src "ls180.v:2211.6-2211.39"
+ attribute \src "ls180.v:2207.6-2207.39"
wire \builder_csrbank6_cmd_response4_re
- attribute \src "ls180.v:2214.12-2214.44"
+ attribute \src "ls180.v:2210.12-2210.44"
wire width 8 \builder_csrbank6_cmd_response4_w
- attribute \src "ls180.v:2213.6-2213.39"
+ attribute \src "ls180.v:2209.6-2209.39"
wire \builder_csrbank6_cmd_response4_we
- attribute \src "ls180.v:2208.12-2208.44"
+ attribute \src "ls180.v:2204.12-2204.44"
wire width 8 \builder_csrbank6_cmd_response5_r
- attribute \src "ls180.v:2207.6-2207.39"
+ attribute \src "ls180.v:2203.6-2203.39"
wire \builder_csrbank6_cmd_response5_re
- attribute \src "ls180.v:2210.12-2210.44"
+ attribute \src "ls180.v:2206.12-2206.44"
wire width 8 \builder_csrbank6_cmd_response5_w
- attribute \src "ls180.v:2209.6-2209.39"
+ attribute \src "ls180.v:2205.6-2205.39"
wire \builder_csrbank6_cmd_response5_we
- attribute \src "ls180.v:2204.12-2204.44"
+ attribute \src "ls180.v:2200.12-2200.44"
wire width 8 \builder_csrbank6_cmd_response6_r
- attribute \src "ls180.v:2203.6-2203.39"
+ attribute \src "ls180.v:2199.6-2199.39"
wire \builder_csrbank6_cmd_response6_re
- attribute \src "ls180.v:2206.12-2206.44"
+ attribute \src "ls180.v:2202.12-2202.44"
wire width 8 \builder_csrbank6_cmd_response6_w
- attribute \src "ls180.v:2205.6-2205.39"
+ attribute \src "ls180.v:2201.6-2201.39"
wire \builder_csrbank6_cmd_response6_we
- attribute \src "ls180.v:2200.12-2200.44"
+ attribute \src "ls180.v:2196.12-2196.44"
wire width 8 \builder_csrbank6_cmd_response7_r
- attribute \src "ls180.v:2199.6-2199.39"
+ attribute \src "ls180.v:2195.6-2195.39"
wire \builder_csrbank6_cmd_response7_re
- attribute \src "ls180.v:2202.12-2202.44"
+ attribute \src "ls180.v:2198.12-2198.44"
wire width 8 \builder_csrbank6_cmd_response7_w
- attribute \src "ls180.v:2201.6-2201.39"
+ attribute \src "ls180.v:2197.6-2197.39"
wire \builder_csrbank6_cmd_response7_we
- attribute \src "ls180.v:2196.12-2196.44"
+ attribute \src "ls180.v:2192.12-2192.44"
wire width 8 \builder_csrbank6_cmd_response8_r
- attribute \src "ls180.v:2195.6-2195.39"
+ attribute \src "ls180.v:2191.6-2191.39"
wire \builder_csrbank6_cmd_response8_re
- attribute \src "ls180.v:2198.12-2198.44"
+ attribute \src "ls180.v:2194.12-2194.44"
wire width 8 \builder_csrbank6_cmd_response8_w
- attribute \src "ls180.v:2197.6-2197.39"
+ attribute \src "ls180.v:2193.6-2193.39"
wire \builder_csrbank6_cmd_response8_we
- attribute \src "ls180.v:2192.12-2192.44"
+ attribute \src "ls180.v:2188.12-2188.44"
wire width 8 \builder_csrbank6_cmd_response9_r
- attribute \src "ls180.v:2191.6-2191.39"
+ attribute \src "ls180.v:2187.6-2187.39"
wire \builder_csrbank6_cmd_response9_re
- attribute \src "ls180.v:2194.12-2194.44"
+ attribute \src "ls180.v:2190.12-2190.44"
wire width 8 \builder_csrbank6_cmd_response9_w
- attribute \src "ls180.v:2193.6-2193.39"
+ attribute \src "ls180.v:2189.6-2189.39"
wire \builder_csrbank6_cmd_response9_we
- attribute \src "ls180.v:2236.12-2236.41"
+ attribute \src "ls180.v:2232.12-2232.41"
wire width 4 \builder_csrbank6_data_event_r
- attribute \src "ls180.v:2235.6-2235.36"
+ attribute \src "ls180.v:2231.6-2231.36"
wire \builder_csrbank6_data_event_re
- attribute \src "ls180.v:2238.12-2238.41"
+ attribute \src "ls180.v:2234.12-2234.41"
wire width 4 \builder_csrbank6_data_event_w
- attribute \src "ls180.v:2237.6-2237.36"
+ attribute \src "ls180.v:2233.6-2233.36"
wire \builder_csrbank6_data_event_we
- attribute \src "ls180.v:2263.6-2263.26"
+ attribute \src "ls180.v:2259.6-2259.26"
wire \builder_csrbank6_sel
- attribute \src "ls180.v:2297.12-2297.40"
+ attribute \src "ls180.v:2293.12-2293.40"
wire width 8 \builder_csrbank7_dma_base0_r
- attribute \src "ls180.v:2296.6-2296.35"
+ attribute \src "ls180.v:2292.6-2292.35"
wire \builder_csrbank7_dma_base0_re
- attribute \src "ls180.v:2299.12-2299.40"
+ attribute \src "ls180.v:2295.12-2295.40"
wire width 8 \builder_csrbank7_dma_base0_w
- attribute \src "ls180.v:2298.6-2298.35"
+ attribute \src "ls180.v:2294.6-2294.35"
wire \builder_csrbank7_dma_base0_we
- attribute \src "ls180.v:2293.12-2293.40"
+ attribute \src "ls180.v:2289.12-2289.40"
wire width 8 \builder_csrbank7_dma_base1_r
- attribute \src "ls180.v:2292.6-2292.35"
+ attribute \src "ls180.v:2288.6-2288.35"
wire \builder_csrbank7_dma_base1_re
- attribute \src "ls180.v:2295.12-2295.40"
+ attribute \src "ls180.v:2291.12-2291.40"
wire width 8 \builder_csrbank7_dma_base1_w
- attribute \src "ls180.v:2294.6-2294.35"
+ attribute \src "ls180.v:2290.6-2290.35"
wire \builder_csrbank7_dma_base1_we
- attribute \src "ls180.v:2289.12-2289.40"
+ attribute \src "ls180.v:2285.12-2285.40"
wire width 8 \builder_csrbank7_dma_base2_r
- attribute \src "ls180.v:2288.6-2288.35"
+ attribute \src "ls180.v:2284.6-2284.35"
wire \builder_csrbank7_dma_base2_re
- attribute \src "ls180.v:2291.12-2291.40"
+ attribute \src "ls180.v:2287.12-2287.40"
wire width 8 \builder_csrbank7_dma_base2_w
- attribute \src "ls180.v:2290.6-2290.35"
+ attribute \src "ls180.v:2286.6-2286.35"
wire \builder_csrbank7_dma_base2_we
- attribute \src "ls180.v:2285.12-2285.40"
+ attribute \src "ls180.v:2281.12-2281.40"
wire width 8 \builder_csrbank7_dma_base3_r
- attribute \src "ls180.v:2284.6-2284.35"
+ attribute \src "ls180.v:2280.6-2280.35"
wire \builder_csrbank7_dma_base3_re
- attribute \src "ls180.v:2287.12-2287.40"
+ attribute \src "ls180.v:2283.12-2283.40"
wire width 8 \builder_csrbank7_dma_base3_w
- attribute \src "ls180.v:2286.6-2286.35"
+ attribute \src "ls180.v:2282.6-2282.35"
wire \builder_csrbank7_dma_base3_we
- attribute \src "ls180.v:2281.12-2281.40"
+ attribute \src "ls180.v:2277.12-2277.40"
wire width 8 \builder_csrbank7_dma_base4_r
- attribute \src "ls180.v:2280.6-2280.35"
+ attribute \src "ls180.v:2276.6-2276.35"
wire \builder_csrbank7_dma_base4_re
- attribute \src "ls180.v:2283.12-2283.40"
+ attribute \src "ls180.v:2279.12-2279.40"
wire width 8 \builder_csrbank7_dma_base4_w
- attribute \src "ls180.v:2282.6-2282.35"
+ attribute \src "ls180.v:2278.6-2278.35"
wire \builder_csrbank7_dma_base4_we
- attribute \src "ls180.v:2277.12-2277.40"
+ attribute \src "ls180.v:2273.12-2273.40"
wire width 8 \builder_csrbank7_dma_base5_r
- attribute \src "ls180.v:2276.6-2276.35"
+ attribute \src "ls180.v:2272.6-2272.35"
wire \builder_csrbank7_dma_base5_re
- attribute \src "ls180.v:2279.12-2279.40"
+ attribute \src "ls180.v:2275.12-2275.40"
wire width 8 \builder_csrbank7_dma_base5_w
- attribute \src "ls180.v:2278.6-2278.35"
+ attribute \src "ls180.v:2274.6-2274.35"
wire \builder_csrbank7_dma_base5_we
- attribute \src "ls180.v:2273.12-2273.40"
+ attribute \src "ls180.v:2269.12-2269.40"
wire width 8 \builder_csrbank7_dma_base6_r
- attribute \src "ls180.v:2272.6-2272.35"
+ attribute \src "ls180.v:2268.6-2268.35"
wire \builder_csrbank7_dma_base6_re
- attribute \src "ls180.v:2275.12-2275.40"
+ attribute \src "ls180.v:2271.12-2271.40"
wire width 8 \builder_csrbank7_dma_base6_w
- attribute \src "ls180.v:2274.6-2274.35"
+ attribute \src "ls180.v:2270.6-2270.35"
wire \builder_csrbank7_dma_base6_we
- attribute \src "ls180.v:2269.12-2269.40"
+ attribute \src "ls180.v:2265.12-2265.40"
wire width 8 \builder_csrbank7_dma_base7_r
- attribute \src "ls180.v:2268.6-2268.35"
+ attribute \src "ls180.v:2264.6-2264.35"
wire \builder_csrbank7_dma_base7_re
- attribute \src "ls180.v:2271.12-2271.40"
+ attribute \src "ls180.v:2267.12-2267.40"
wire width 8 \builder_csrbank7_dma_base7_w
- attribute \src "ls180.v:2270.6-2270.35"
+ attribute \src "ls180.v:2266.6-2266.35"
wire \builder_csrbank7_dma_base7_we
- attribute \src "ls180.v:2321.6-2321.33"
+ attribute \src "ls180.v:2317.6-2317.33"
wire \builder_csrbank7_dma_done_r
- attribute \src "ls180.v:2320.6-2320.34"
+ attribute \src "ls180.v:2316.6-2316.34"
wire \builder_csrbank7_dma_done_re
- attribute \src "ls180.v:2323.6-2323.33"
+ attribute \src "ls180.v:2319.6-2319.33"
wire \builder_csrbank7_dma_done_w
- attribute \src "ls180.v:2322.6-2322.34"
+ attribute \src "ls180.v:2318.6-2318.34"
wire \builder_csrbank7_dma_done_we
- attribute \src "ls180.v:2317.6-2317.36"
+ attribute \src "ls180.v:2313.6-2313.36"
wire \builder_csrbank7_dma_enable0_r
- attribute \src "ls180.v:2316.6-2316.37"
+ attribute \src "ls180.v:2312.6-2312.37"
wire \builder_csrbank7_dma_enable0_re
- attribute \src "ls180.v:2319.6-2319.36"
+ attribute \src "ls180.v:2315.6-2315.36"
wire \builder_csrbank7_dma_enable0_w
- attribute \src "ls180.v:2318.6-2318.37"
+ attribute \src "ls180.v:2314.6-2314.37"
wire \builder_csrbank7_dma_enable0_we
- attribute \src "ls180.v:2313.12-2313.42"
+ attribute \src "ls180.v:2309.12-2309.42"
wire width 8 \builder_csrbank7_dma_length0_r
- attribute \src "ls180.v:2312.6-2312.37"
+ attribute \src "ls180.v:2308.6-2308.37"
wire \builder_csrbank7_dma_length0_re
- attribute \src "ls180.v:2315.12-2315.42"
+ attribute \src "ls180.v:2311.12-2311.42"
wire width 8 \builder_csrbank7_dma_length0_w
- attribute \src "ls180.v:2314.6-2314.37"
+ attribute \src "ls180.v:2310.6-2310.37"
wire \builder_csrbank7_dma_length0_we
- attribute \src "ls180.v:2309.12-2309.42"
+ attribute \src "ls180.v:2305.12-2305.42"
wire width 8 \builder_csrbank7_dma_length1_r
- attribute \src "ls180.v:2308.6-2308.37"
+ attribute \src "ls180.v:2304.6-2304.37"
wire \builder_csrbank7_dma_length1_re
- attribute \src "ls180.v:2311.12-2311.42"
+ attribute \src "ls180.v:2307.12-2307.42"
wire width 8 \builder_csrbank7_dma_length1_w
- attribute \src "ls180.v:2310.6-2310.37"
+ attribute \src "ls180.v:2306.6-2306.37"
wire \builder_csrbank7_dma_length1_we
- attribute \src "ls180.v:2305.12-2305.42"
+ attribute \src "ls180.v:2301.12-2301.42"
wire width 8 \builder_csrbank7_dma_length2_r
- attribute \src "ls180.v:2304.6-2304.37"
+ attribute \src "ls180.v:2300.6-2300.37"
wire \builder_csrbank7_dma_length2_re
- attribute \src "ls180.v:2307.12-2307.42"
+ attribute \src "ls180.v:2303.12-2303.42"
wire width 8 \builder_csrbank7_dma_length2_w
- attribute \src "ls180.v:2306.6-2306.37"
+ attribute \src "ls180.v:2302.6-2302.37"
wire \builder_csrbank7_dma_length2_we
- attribute \src "ls180.v:2301.12-2301.42"
+ attribute \src "ls180.v:2297.12-2297.42"
wire width 8 \builder_csrbank7_dma_length3_r
- attribute \src "ls180.v:2300.6-2300.37"
+ attribute \src "ls180.v:2296.6-2296.37"
wire \builder_csrbank7_dma_length3_re
- attribute \src "ls180.v:2303.12-2303.42"
+ attribute \src "ls180.v:2299.12-2299.42"
wire width 8 \builder_csrbank7_dma_length3_w
- attribute \src "ls180.v:2302.6-2302.37"
+ attribute \src "ls180.v:2298.6-2298.37"
wire \builder_csrbank7_dma_length3_we
- attribute \src "ls180.v:2325.6-2325.34"
+ attribute \src "ls180.v:2321.6-2321.34"
wire \builder_csrbank7_dma_loop0_r
- attribute \src "ls180.v:2324.6-2324.35"
+ attribute \src "ls180.v:2320.6-2320.35"
wire \builder_csrbank7_dma_loop0_re
- attribute \src "ls180.v:2327.6-2327.34"
+ attribute \src "ls180.v:2323.6-2323.34"
wire \builder_csrbank7_dma_loop0_w
- attribute \src "ls180.v:2326.6-2326.35"
+ attribute \src "ls180.v:2322.6-2322.35"
wire \builder_csrbank7_dma_loop0_we
- attribute \src "ls180.v:2341.12-2341.42"
+ attribute \src "ls180.v:2337.12-2337.42"
wire width 8 \builder_csrbank7_dma_offset0_r
- attribute \src "ls180.v:2340.6-2340.37"
+ attribute \src "ls180.v:2336.6-2336.37"
wire \builder_csrbank7_dma_offset0_re
- attribute \src "ls180.v:2343.12-2343.42"
+ attribute \src "ls180.v:2339.12-2339.42"
wire width 8 \builder_csrbank7_dma_offset0_w
- attribute \src "ls180.v:2342.6-2342.37"
+ attribute \src "ls180.v:2338.6-2338.37"
wire \builder_csrbank7_dma_offset0_we
- attribute \src "ls180.v:2337.12-2337.42"
+ attribute \src "ls180.v:2333.12-2333.42"
wire width 8 \builder_csrbank7_dma_offset1_r
- attribute \src "ls180.v:2336.6-2336.37"
+ attribute \src "ls180.v:2332.6-2332.37"
wire \builder_csrbank7_dma_offset1_re
- attribute \src "ls180.v:2339.12-2339.42"
+ attribute \src "ls180.v:2335.12-2335.42"
wire width 8 \builder_csrbank7_dma_offset1_w
- attribute \src "ls180.v:2338.6-2338.37"
+ attribute \src "ls180.v:2334.6-2334.37"
wire \builder_csrbank7_dma_offset1_we
- attribute \src "ls180.v:2333.12-2333.42"
+ attribute \src "ls180.v:2329.12-2329.42"
wire width 8 \builder_csrbank7_dma_offset2_r
- attribute \src "ls180.v:2332.6-2332.37"
+ attribute \src "ls180.v:2328.6-2328.37"
wire \builder_csrbank7_dma_offset2_re
- attribute \src "ls180.v:2335.12-2335.42"
+ attribute \src "ls180.v:2331.12-2331.42"
wire width 8 \builder_csrbank7_dma_offset2_w
- attribute \src "ls180.v:2334.6-2334.37"
+ attribute \src "ls180.v:2330.6-2330.37"
wire \builder_csrbank7_dma_offset2_we
- attribute \src "ls180.v:2329.12-2329.42"
+ attribute \src "ls180.v:2325.12-2325.42"
wire width 8 \builder_csrbank7_dma_offset3_r
- attribute \src "ls180.v:2328.6-2328.37"
+ attribute \src "ls180.v:2324.6-2324.37"
wire \builder_csrbank7_dma_offset3_re
- attribute \src "ls180.v:2331.12-2331.42"
+ attribute \src "ls180.v:2327.12-2327.42"
wire width 8 \builder_csrbank7_dma_offset3_w
- attribute \src "ls180.v:2330.6-2330.37"
+ attribute \src "ls180.v:2326.6-2326.37"
wire \builder_csrbank7_dma_offset3_we
- attribute \src "ls180.v:2344.6-2344.26"
+ attribute \src "ls180.v:2340.6-2340.26"
wire \builder_csrbank7_sel
- attribute \src "ls180.v:2350.6-2350.36"
+ attribute \src "ls180.v:2346.6-2346.36"
wire \builder_csrbank8_card_detect_r
- attribute \src "ls180.v:2349.6-2349.37"
+ attribute \src "ls180.v:2345.6-2345.37"
wire \builder_csrbank8_card_detect_re
- attribute \src "ls180.v:2352.6-2352.36"
+ attribute \src "ls180.v:2348.6-2348.36"
wire \builder_csrbank8_card_detect_w
- attribute \src "ls180.v:2351.6-2351.37"
+ attribute \src "ls180.v:2347.6-2347.37"
wire \builder_csrbank8_card_detect_we
- attribute \src "ls180.v:2358.12-2358.47"
+ attribute \src "ls180.v:2354.12-2354.47"
wire width 8 \builder_csrbank8_clocker_divider0_r
- attribute \src "ls180.v:2357.6-2357.42"
+ attribute \src "ls180.v:2353.6-2353.42"
wire \builder_csrbank8_clocker_divider0_re
- attribute \src "ls180.v:2360.12-2360.47"
+ attribute \src "ls180.v:2356.12-2356.47"
wire width 8 \builder_csrbank8_clocker_divider0_w
- attribute \src "ls180.v:2359.6-2359.42"
+ attribute \src "ls180.v:2355.6-2355.42"
wire \builder_csrbank8_clocker_divider0_we
- attribute \src "ls180.v:2354.6-2354.41"
+ attribute \src "ls180.v:2350.6-2350.41"
wire \builder_csrbank8_clocker_divider1_r
- attribute \src "ls180.v:2353.6-2353.42"
+ attribute \src "ls180.v:2349.6-2349.42"
wire \builder_csrbank8_clocker_divider1_re
- attribute \src "ls180.v:2356.6-2356.41"
+ attribute \src "ls180.v:2352.6-2352.41"
wire \builder_csrbank8_clocker_divider1_w
- attribute \src "ls180.v:2355.6-2355.42"
+ attribute \src "ls180.v:2351.6-2351.42"
wire \builder_csrbank8_clocker_divider1_we
- attribute \src "ls180.v:2361.6-2361.26"
+ attribute \src "ls180.v:2357.6-2357.26"
wire \builder_csrbank8_sel
- attribute \src "ls180.v:2367.12-2367.44"
+ attribute \src "ls180.v:2363.12-2363.44"
wire width 4 \builder_csrbank9_dfii_control0_r
- attribute \src "ls180.v:2366.6-2366.39"
+ attribute \src "ls180.v:2362.6-2362.39"
wire \builder_csrbank9_dfii_control0_re
- attribute \src "ls180.v:2369.12-2369.44"
+ attribute \src "ls180.v:2365.12-2365.44"
wire width 4 \builder_csrbank9_dfii_control0_w
- attribute \src "ls180.v:2368.6-2368.39"
+ attribute \src "ls180.v:2364.6-2364.39"
wire \builder_csrbank9_dfii_control0_we
- attribute \src "ls180.v:2379.12-2379.48"
+ attribute \src "ls180.v:2375.12-2375.48"
wire width 8 \builder_csrbank9_dfii_pi0_address0_r
- attribute \src "ls180.v:2378.6-2378.43"
+ attribute \src "ls180.v:2374.6-2374.43"
wire \builder_csrbank9_dfii_pi0_address0_re
- attribute \src "ls180.v:2381.12-2381.48"
+ attribute \src "ls180.v:2377.12-2377.48"
wire width 8 \builder_csrbank9_dfii_pi0_address0_w
- attribute \src "ls180.v:2380.6-2380.43"
+ attribute \src "ls180.v:2376.6-2376.43"
wire \builder_csrbank9_dfii_pi0_address0_we
- attribute \src "ls180.v:2375.12-2375.48"
+ attribute \src "ls180.v:2371.12-2371.48"
wire width 5 \builder_csrbank9_dfii_pi0_address1_r
- attribute \src "ls180.v:2374.6-2374.43"
+ attribute \src "ls180.v:2370.6-2370.43"
wire \builder_csrbank9_dfii_pi0_address1_re
- attribute \src "ls180.v:2377.12-2377.48"
+ attribute \src "ls180.v:2373.12-2373.48"
wire width 5 \builder_csrbank9_dfii_pi0_address1_w
- attribute \src "ls180.v:2376.6-2376.43"
+ attribute \src "ls180.v:2372.6-2372.43"
wire \builder_csrbank9_dfii_pi0_address1_we
- attribute \src "ls180.v:2383.12-2383.49"
+ attribute \src "ls180.v:2379.12-2379.49"
wire width 2 \builder_csrbank9_dfii_pi0_baddress0_r
- attribute \src "ls180.v:2382.6-2382.44"
+ attribute \src "ls180.v:2378.6-2378.44"
wire \builder_csrbank9_dfii_pi0_baddress0_re
- attribute \src "ls180.v:2385.12-2385.49"
+ attribute \src "ls180.v:2381.12-2381.49"
wire width 2 \builder_csrbank9_dfii_pi0_baddress0_w
- attribute \src "ls180.v:2384.6-2384.44"
+ attribute \src "ls180.v:2380.6-2380.44"
wire \builder_csrbank9_dfii_pi0_baddress0_we
- attribute \src "ls180.v:2371.12-2371.48"
+ attribute \src "ls180.v:2367.12-2367.48"
wire width 6 \builder_csrbank9_dfii_pi0_command0_r
- attribute \src "ls180.v:2370.6-2370.43"
+ attribute \src "ls180.v:2366.6-2366.43"
wire \builder_csrbank9_dfii_pi0_command0_re
- attribute \src "ls180.v:2373.12-2373.48"
+ attribute \src "ls180.v:2369.12-2369.48"
wire width 6 \builder_csrbank9_dfii_pi0_command0_w
- attribute \src "ls180.v:2372.6-2372.43"
+ attribute \src "ls180.v:2368.6-2368.43"
wire \builder_csrbank9_dfii_pi0_command0_we
- attribute \src "ls180.v:2399.12-2399.47"
+ attribute \src "ls180.v:2395.12-2395.47"
wire width 8 \builder_csrbank9_dfii_pi0_rddata0_r
- attribute \src "ls180.v:2398.6-2398.42"
+ attribute \src "ls180.v:2394.6-2394.42"
wire \builder_csrbank9_dfii_pi0_rddata0_re
- attribute \src "ls180.v:2401.12-2401.47"
+ attribute \src "ls180.v:2397.12-2397.47"
wire width 8 \builder_csrbank9_dfii_pi0_rddata0_w
- attribute \src "ls180.v:2400.6-2400.42"
+ attribute \src "ls180.v:2396.6-2396.42"
wire \builder_csrbank9_dfii_pi0_rddata0_we
- attribute \src "ls180.v:2395.12-2395.47"
+ attribute \src "ls180.v:2391.12-2391.47"
wire width 8 \builder_csrbank9_dfii_pi0_rddata1_r
- attribute \src "ls180.v:2394.6-2394.42"
+ attribute \src "ls180.v:2390.6-2390.42"
wire \builder_csrbank9_dfii_pi0_rddata1_re
- attribute \src "ls180.v:2397.12-2397.47"
+ attribute \src "ls180.v:2393.12-2393.47"
wire width 8 \builder_csrbank9_dfii_pi0_rddata1_w
- attribute \src "ls180.v:2396.6-2396.42"
+ attribute \src "ls180.v:2392.6-2392.42"
wire \builder_csrbank9_dfii_pi0_rddata1_we
- attribute \src "ls180.v:2391.12-2391.47"
+ attribute \src "ls180.v:2387.12-2387.47"
wire width 8 \builder_csrbank9_dfii_pi0_wrdata0_r
- attribute \src "ls180.v:2390.6-2390.42"
+ attribute \src "ls180.v:2386.6-2386.42"
wire \builder_csrbank9_dfii_pi0_wrdata0_re
- attribute \src "ls180.v:2393.12-2393.47"
+ attribute \src "ls180.v:2389.12-2389.47"
wire width 8 \builder_csrbank9_dfii_pi0_wrdata0_w
- attribute \src "ls180.v:2392.6-2392.42"
+ attribute \src "ls180.v:2388.6-2388.42"
wire \builder_csrbank9_dfii_pi0_wrdata0_we
- attribute \src "ls180.v:2387.12-2387.47"
+ attribute \src "ls180.v:2383.12-2383.47"
wire width 8 \builder_csrbank9_dfii_pi0_wrdata1_r
- attribute \src "ls180.v:2386.6-2386.42"
+ attribute \src "ls180.v:2382.6-2382.42"
wire \builder_csrbank9_dfii_pi0_wrdata1_re
- attribute \src "ls180.v:2389.12-2389.47"
+ attribute \src "ls180.v:2385.12-2385.47"
wire width 8 \builder_csrbank9_dfii_pi0_wrdata1_w
- attribute \src "ls180.v:2388.6-2388.42"
+ attribute \src "ls180.v:2384.6-2384.42"
wire \builder_csrbank9_dfii_pi0_wrdata1_we
- attribute \src "ls180.v:2402.6-2402.26"
+ attribute \src "ls180.v:2398.6-2398.26"
wire \builder_csrbank9_sel
- attribute \src "ls180.v:1899.6-1899.18"
+ attribute \src "ls180.v:1895.6-1895.18"
wire \builder_done
- attribute \src "ls180.v:1897.5-1897.18"
+ attribute \src "ls180.v:1893.5-1893.18"
wire \builder_error
- attribute \src "ls180.v:1894.11-1894.24"
+ attribute \src "ls180.v:1890.11-1890.24"
wire width 3 \builder_grant
- attribute \src "ls180.v:1901.13-1901.44"
+ attribute \src "ls180.v:1897.13-1897.44"
wire width 14 \builder_interface0_bank_bus_adr
- attribute \src "ls180.v:1904.11-1904.44"
+ attribute \src "ls180.v:1900.11-1900.44"
wire width 8 \builder_interface0_bank_bus_dat_r
- attribute \src "ls180.v:1903.12-1903.45"
+ attribute \src "ls180.v:1899.12-1899.45"
wire width 8 \builder_interface0_bank_bus_dat_w
- attribute \src "ls180.v:1902.6-1902.36"
+ attribute \src "ls180.v:1898.6-1898.36"
wire \builder_interface0_bank_bus_we
- attribute \src "ls180.v:2403.13-2403.45"
+ attribute \src "ls180.v:2399.13-2399.45"
wire width 14 \builder_interface10_bank_bus_adr
- attribute \src "ls180.v:2406.11-2406.45"
+ attribute \src "ls180.v:2402.11-2402.45"
wire width 8 \builder_interface10_bank_bus_dat_r
- attribute \src "ls180.v:2405.12-2405.46"
+ attribute \src "ls180.v:2401.12-2401.46"
wire width 8 \builder_interface10_bank_bus_dat_w
- attribute \src "ls180.v:2404.6-2404.37"
+ attribute \src "ls180.v:2400.6-2400.37"
wire \builder_interface10_bank_bus_we
- attribute \src "ls180.v:2436.13-2436.45"
+ attribute \src "ls180.v:2432.13-2432.45"
wire width 14 \builder_interface11_bank_bus_adr
- attribute \src "ls180.v:2439.11-2439.45"
+ attribute \src "ls180.v:2435.11-2435.45"
wire width 8 \builder_interface11_bank_bus_dat_r
- attribute \src "ls180.v:2438.12-2438.46"
+ attribute \src "ls180.v:2434.12-2434.46"
wire width 8 \builder_interface11_bank_bus_dat_w
- attribute \src "ls180.v:2437.6-2437.37"
+ attribute \src "ls180.v:2433.6-2433.37"
wire \builder_interface11_bank_bus_we
- attribute \src "ls180.v:2477.13-2477.45"
+ attribute \src "ls180.v:2473.13-2473.45"
wire width 14 \builder_interface12_bank_bus_adr
- attribute \src "ls180.v:2480.11-2480.45"
+ attribute \src "ls180.v:2476.11-2476.45"
wire width 8 \builder_interface12_bank_bus_dat_r
- attribute \src "ls180.v:2479.12-2479.46"
+ attribute \src "ls180.v:2475.12-2475.46"
wire width 8 \builder_interface12_bank_bus_dat_w
- attribute \src "ls180.v:2478.6-2478.37"
+ attribute \src "ls180.v:2474.6-2474.37"
wire \builder_interface12_bank_bus_we
- attribute \src "ls180.v:2542.13-2542.45"
+ attribute \src "ls180.v:2538.13-2538.45"
wire width 14 \builder_interface13_bank_bus_adr
- attribute \src "ls180.v:2545.11-2545.45"
+ attribute \src "ls180.v:2541.11-2541.45"
wire width 8 \builder_interface13_bank_bus_dat_r
- attribute \src "ls180.v:2544.12-2544.46"
+ attribute \src "ls180.v:2540.12-2540.46"
wire width 8 \builder_interface13_bank_bus_dat_w
- attribute \src "ls180.v:2543.6-2543.37"
+ attribute \src "ls180.v:2539.6-2539.37"
wire \builder_interface13_bank_bus_we
- attribute \src "ls180.v:2567.13-2567.45"
+ attribute \src "ls180.v:2563.13-2563.45"
wire width 14 \builder_interface14_bank_bus_adr
- attribute \src "ls180.v:2570.11-2570.45"
+ attribute \src "ls180.v:2566.11-2566.45"
wire width 8 \builder_interface14_bank_bus_dat_r
- attribute \src "ls180.v:2569.12-2569.46"
+ attribute \src "ls180.v:2565.12-2565.46"
wire width 8 \builder_interface14_bank_bus_dat_w
- attribute \src "ls180.v:2568.6-2568.37"
+ attribute \src "ls180.v:2564.6-2564.37"
wire \builder_interface14_bank_bus_we
- attribute \src "ls180.v:1942.13-1942.44"
+ attribute \src "ls180.v:1938.13-1938.44"
wire width 14 \builder_interface1_bank_bus_adr
- attribute \src "ls180.v:1945.11-1945.44"
+ attribute \src "ls180.v:1941.11-1941.44"
wire width 8 \builder_interface1_bank_bus_dat_r
- attribute \src "ls180.v:1944.12-1944.45"
+ attribute \src "ls180.v:1940.12-1940.45"
wire width 8 \builder_interface1_bank_bus_dat_w
- attribute \src "ls180.v:1943.6-1943.36"
+ attribute \src "ls180.v:1939.6-1939.36"
wire \builder_interface1_bank_bus_we
- attribute \src "ls180.v:1971.13-1971.44"
+ attribute \src "ls180.v:1967.13-1967.44"
wire width 14 \builder_interface2_bank_bus_adr
- attribute \src "ls180.v:1974.11-1974.44"
+ attribute \src "ls180.v:1970.11-1970.44"
wire width 8 \builder_interface2_bank_bus_dat_r
- attribute \src "ls180.v:1973.12-1973.45"
+ attribute \src "ls180.v:1969.12-1969.45"
wire width 8 \builder_interface2_bank_bus_dat_w
- attribute \src "ls180.v:1972.6-1972.36"
+ attribute \src "ls180.v:1968.6-1968.36"
wire \builder_interface2_bank_bus_we
- attribute \src "ls180.v:1984.13-1984.44"
+ attribute \src "ls180.v:1980.13-1980.44"
wire width 14 \builder_interface3_bank_bus_adr
- attribute \src "ls180.v:1987.11-1987.44"
+ attribute \src "ls180.v:1983.11-1983.44"
wire width 8 \builder_interface3_bank_bus_dat_r
- attribute \src "ls180.v:1986.12-1986.45"
+ attribute \src "ls180.v:1982.12-1982.45"
wire width 8 \builder_interface3_bank_bus_dat_w
- attribute \src "ls180.v:1985.6-1985.36"
+ attribute \src "ls180.v:1981.6-1981.36"
wire \builder_interface3_bank_bus_we
- attribute \src "ls180.v:2025.13-2025.44"
+ attribute \src "ls180.v:2021.13-2021.44"
wire width 14 \builder_interface4_bank_bus_adr
- attribute \src "ls180.v:2028.11-2028.44"
+ attribute \src "ls180.v:2024.11-2024.44"
wire width 8 \builder_interface4_bank_bus_dat_r
- attribute \src "ls180.v:2027.12-2027.45"
+ attribute \src "ls180.v:2023.12-2023.45"
wire width 8 \builder_interface4_bank_bus_dat_w
- attribute \src "ls180.v:2026.6-2026.36"
+ attribute \src "ls180.v:2022.6-2022.36"
wire \builder_interface4_bank_bus_we
- attribute \src "ls180.v:2066.13-2066.44"
+ attribute \src "ls180.v:2062.13-2062.44"
wire width 14 \builder_interface5_bank_bus_adr
- attribute \src "ls180.v:2069.11-2069.44"
+ attribute \src "ls180.v:2065.11-2065.44"
wire width 8 \builder_interface5_bank_bus_dat_r
- attribute \src "ls180.v:2068.12-2068.45"
+ attribute \src "ls180.v:2064.12-2064.45"
wire width 8 \builder_interface5_bank_bus_dat_w
- attribute \src "ls180.v:2067.6-2067.36"
+ attribute \src "ls180.v:2063.6-2063.36"
wire \builder_interface5_bank_bus_we
- attribute \src "ls180.v:2131.13-2131.44"
+ attribute \src "ls180.v:2127.13-2127.44"
wire width 14 \builder_interface6_bank_bus_adr
- attribute \src "ls180.v:2134.11-2134.44"
+ attribute \src "ls180.v:2130.11-2130.44"
wire width 8 \builder_interface6_bank_bus_dat_r
- attribute \src "ls180.v:2133.12-2133.45"
+ attribute \src "ls180.v:2129.12-2129.45"
wire width 8 \builder_interface6_bank_bus_dat_w
- attribute \src "ls180.v:2132.6-2132.36"
+ attribute \src "ls180.v:2128.6-2128.36"
wire \builder_interface6_bank_bus_we
- attribute \src "ls180.v:2264.13-2264.44"
+ attribute \src "ls180.v:2260.13-2260.44"
wire width 14 \builder_interface7_bank_bus_adr
- attribute \src "ls180.v:2267.11-2267.44"
+ attribute \src "ls180.v:2263.11-2263.44"
wire width 8 \builder_interface7_bank_bus_dat_r
- attribute \src "ls180.v:2266.12-2266.45"
+ attribute \src "ls180.v:2262.12-2262.45"
wire width 8 \builder_interface7_bank_bus_dat_w
- attribute \src "ls180.v:2265.6-2265.36"
+ attribute \src "ls180.v:2261.6-2261.36"
wire \builder_interface7_bank_bus_we
- attribute \src "ls180.v:2345.13-2345.44"
+ attribute \src "ls180.v:2341.13-2341.44"
wire width 14 \builder_interface8_bank_bus_adr
- attribute \src "ls180.v:2348.11-2348.44"
+ attribute \src "ls180.v:2344.11-2344.44"
wire width 8 \builder_interface8_bank_bus_dat_r
- attribute \src "ls180.v:2347.12-2347.45"
+ attribute \src "ls180.v:2343.12-2343.45"
wire width 8 \builder_interface8_bank_bus_dat_w
- attribute \src "ls180.v:2346.6-2346.36"
+ attribute \src "ls180.v:2342.6-2342.36"
wire \builder_interface8_bank_bus_we
- attribute \src "ls180.v:2362.13-2362.44"
+ attribute \src "ls180.v:2358.13-2358.44"
wire width 14 \builder_interface9_bank_bus_adr
- attribute \src "ls180.v:2365.11-2365.44"
+ attribute \src "ls180.v:2361.11-2361.44"
wire width 8 \builder_interface9_bank_bus_dat_r
- attribute \src "ls180.v:2364.12-2364.45"
+ attribute \src "ls180.v:2360.12-2360.45"
wire width 8 \builder_interface9_bank_bus_dat_w
- attribute \src "ls180.v:2363.6-2363.36"
+ attribute \src "ls180.v:2359.6-2359.36"
wire \builder_interface9_bank_bus_we
- attribute \src "ls180.v:1867.12-1867.35"
+ attribute \src "ls180.v:1863.12-1863.35"
wire width 14 \builder_libresocsim_adr
- attribute \src "ls180.v:2596.12-2596.47"
+ attribute \src "ls180.v:2592.12-2592.47"
wire width 14 \builder_libresocsim_adr_next_value1
- attribute \src "ls180.v:2597.5-2597.43"
+ attribute \src "ls180.v:2593.5-2593.43"
wire \builder_libresocsim_adr_next_value_ce1
- attribute \src "ls180.v:1870.12-1870.37"
+ attribute \src "ls180.v:1866.12-1866.37"
wire width 8 \builder_libresocsim_dat_r
- attribute \src "ls180.v:1869.11-1869.36"
+ attribute \src "ls180.v:1865.11-1865.36"
wire width 8 \builder_libresocsim_dat_w
- attribute \src "ls180.v:2594.11-2594.48"
+ attribute \src "ls180.v:2590.11-2590.48"
wire width 8 \builder_libresocsim_dat_w_next_value0
- attribute \src "ls180.v:2595.5-2595.45"
+ attribute \src "ls180.v:2591.5-2591.45"
wire \builder_libresocsim_dat_w_next_value_ce0
- attribute \src "ls180.v:1868.5-1868.27"
+ attribute \src "ls180.v:1864.5-1864.27"
wire \builder_libresocsim_we
- attribute \src "ls180.v:2598.5-2598.39"
+ attribute \src "ls180.v:2594.5-2594.39"
wire \builder_libresocsim_we_next_value2
- attribute \src "ls180.v:2599.5-2599.42"
+ attribute \src "ls180.v:2595.5-2595.42"
wire \builder_libresocsim_we_next_value_ce2
- attribute \src "ls180.v:1877.5-1877.37"
+ attribute \src "ls180.v:1873.5-1873.37"
wire \builder_libresocsim_wishbone_ack
- attribute \src "ls180.v:1871.13-1871.45"
+ attribute \src "ls180.v:1867.13-1867.45"
wire width 30 \builder_libresocsim_wishbone_adr
- attribute \src "ls180.v:1880.12-1880.44"
+ attribute \src "ls180.v:1876.12-1876.44"
wire width 2 \builder_libresocsim_wishbone_bte
- attribute \src "ls180.v:1879.12-1879.44"
+ attribute \src "ls180.v:1875.12-1875.44"
wire width 3 \builder_libresocsim_wishbone_cti
- attribute \src "ls180.v:1875.6-1875.38"
+ attribute \src "ls180.v:1871.6-1871.38"
wire \builder_libresocsim_wishbone_cyc
- attribute \src "ls180.v:1873.12-1873.46"
+ attribute \src "ls180.v:1869.12-1869.46"
wire width 32 \builder_libresocsim_wishbone_dat_r
- attribute \src "ls180.v:1872.13-1872.47"
+ attribute \src "ls180.v:1868.13-1868.47"
wire width 32 \builder_libresocsim_wishbone_dat_w
- attribute \src "ls180.v:1881.5-1881.37"
+ attribute \src "ls180.v:1877.5-1877.37"
wire \builder_libresocsim_wishbone_err
- attribute \src "ls180.v:1874.12-1874.44"
+ attribute \src "ls180.v:1870.12-1870.44"
wire width 4 \builder_libresocsim_wishbone_sel
- attribute \src "ls180.v:1876.6-1876.38"
+ attribute \src "ls180.v:1872.6-1872.38"
wire \builder_libresocsim_wishbone_stb
- attribute \src "ls180.v:1878.6-1878.37"
+ attribute \src "ls180.v:1874.6-1874.37"
wire \builder_libresocsim_wishbone_we
- attribute \src "ls180.v:1770.5-1770.20"
+ attribute \src "ls180.v:1766.5-1766.20"
wire \builder_locked0
- attribute \src "ls180.v:1771.5-1771.20"
+ attribute \src "ls180.v:1767.5-1767.20"
wire \builder_locked1
- attribute \src "ls180.v:1772.5-1772.20"
+ attribute \src "ls180.v:1768.5-1768.20"
wire \builder_locked2
- attribute \src "ls180.v:1773.5-1773.20"
+ attribute \src "ls180.v:1769.5-1769.20"
wire \builder_locked3
- attribute \src "ls180.v:1757.11-1757.41"
+ attribute \src "ls180.v:1753.11-1753.41"
wire width 3 \builder_multiplexer_next_state
- attribute \src "ls180.v:1756.11-1756.36"
+ attribute \src "ls180.v:1752.11-1752.36"
wire width 3 \builder_multiplexer_state
attribute \no_retiming "true"
- attribute \src "ls180.v:2703.32-2703.59"
+ attribute \src "ls180.v:2699.32-2699.59"
wire \builder_multiregimpl0_regs0
attribute \no_retiming "true"
- attribute \src "ls180.v:2704.32-2704.59"
+ attribute \src "ls180.v:2700.32-2700.59"
wire \builder_multiregimpl0_regs1
attribute \no_retiming "true"
- attribute \src "ls180.v:2723.32-2723.60"
+ attribute \src "ls180.v:2719.32-2719.60"
wire \builder_multiregimpl10_regs0
attribute \no_retiming "true"
- attribute \src "ls180.v:2724.32-2724.60"
+ attribute \src "ls180.v:2720.32-2720.60"
wire \builder_multiregimpl10_regs1
attribute \no_retiming "true"
- attribute \src "ls180.v:2725.32-2725.60"
+ attribute \src "ls180.v:2721.32-2721.60"
wire \builder_multiregimpl11_regs0
attribute \no_retiming "true"
- attribute \src "ls180.v:2726.32-2726.60"
+ attribute \src "ls180.v:2722.32-2722.60"
wire \builder_multiregimpl11_regs1
attribute \no_retiming "true"
- attribute \src "ls180.v:2727.32-2727.60"
+ attribute \src "ls180.v:2723.32-2723.60"
wire \builder_multiregimpl12_regs0
attribute \no_retiming "true"
- attribute \src "ls180.v:2728.32-2728.60"
+ attribute \src "ls180.v:2724.32-2724.60"
wire \builder_multiregimpl12_regs1
attribute \no_retiming "true"
- attribute \src "ls180.v:2729.32-2729.60"
+ attribute \src "ls180.v:2725.32-2725.60"
wire \builder_multiregimpl13_regs0
attribute \no_retiming "true"
- attribute \src "ls180.v:2730.32-2730.60"
+ attribute \src "ls180.v:2726.32-2726.60"
wire \builder_multiregimpl13_regs1
attribute \no_retiming "true"
- attribute \src "ls180.v:2731.32-2731.60"
+ attribute \src "ls180.v:2727.32-2727.60"
wire \builder_multiregimpl14_regs0
attribute \no_retiming "true"
- attribute \src "ls180.v:2732.32-2732.60"
+ attribute \src "ls180.v:2728.32-2728.60"
wire \builder_multiregimpl14_regs1
attribute \no_retiming "true"
- attribute \src "ls180.v:2733.32-2733.60"
+ attribute \src "ls180.v:2729.32-2729.60"
wire \builder_multiregimpl15_regs0
attribute \no_retiming "true"
- attribute \src "ls180.v:2734.32-2734.60"
+ attribute \src "ls180.v:2730.32-2730.60"
wire \builder_multiregimpl15_regs1
attribute \no_retiming "true"
- attribute \src "ls180.v:2735.32-2735.60"
+ attribute \src "ls180.v:2731.32-2731.60"
wire \builder_multiregimpl16_regs0
attribute \no_retiming "true"
- attribute \src "ls180.v:2736.32-2736.60"
+ attribute \src "ls180.v:2732.32-2732.60"
wire \builder_multiregimpl16_regs1
attribute \no_retiming "true"
- attribute \src "ls180.v:2705.32-2705.59"
+ attribute \src "ls180.v:2701.32-2701.59"
wire \builder_multiregimpl1_regs0
attribute \no_retiming "true"
- attribute \src "ls180.v:2706.32-2706.59"
+ attribute \src "ls180.v:2702.32-2702.59"
wire \builder_multiregimpl1_regs1
attribute \no_retiming "true"
- attribute \src "ls180.v:2707.32-2707.59"
+ attribute \src "ls180.v:2703.32-2703.59"
wire \builder_multiregimpl2_regs0
attribute \no_retiming "true"
- attribute \src "ls180.v:2708.32-2708.59"
+ attribute \src "ls180.v:2704.32-2704.59"
wire \builder_multiregimpl2_regs1
attribute \no_retiming "true"
- attribute \src "ls180.v:2709.32-2709.59"
+ attribute \src "ls180.v:2705.32-2705.59"
wire \builder_multiregimpl3_regs0
attribute \no_retiming "true"
- attribute \src "ls180.v:2710.32-2710.59"
+ attribute \src "ls180.v:2706.32-2706.59"
wire \builder_multiregimpl3_regs1
attribute \no_retiming "true"
- attribute \src "ls180.v:2711.32-2711.59"
+ attribute \src "ls180.v:2707.32-2707.59"
wire \builder_multiregimpl4_regs0
attribute \no_retiming "true"
- attribute \src "ls180.v:2712.32-2712.59"
+ attribute \src "ls180.v:2708.32-2708.59"
wire \builder_multiregimpl4_regs1
attribute \no_retiming "true"
- attribute \src "ls180.v:2713.32-2713.59"
+ attribute \src "ls180.v:2709.32-2709.59"
wire \builder_multiregimpl5_regs0
attribute \no_retiming "true"
- attribute \src "ls180.v:2714.32-2714.59"
+ attribute \src "ls180.v:2710.32-2710.59"
wire \builder_multiregimpl5_regs1
attribute \no_retiming "true"
- attribute \src "ls180.v:2715.32-2715.59"
+ attribute \src "ls180.v:2711.32-2711.59"
wire \builder_multiregimpl6_regs0
attribute \no_retiming "true"
- attribute \src "ls180.v:2716.32-2716.59"
+ attribute \src "ls180.v:2712.32-2712.59"
wire \builder_multiregimpl6_regs1
attribute \no_retiming "true"
- attribute \src "ls180.v:2717.32-2717.59"
+ attribute \src "ls180.v:2713.32-2713.59"
wire \builder_multiregimpl7_regs0
attribute \no_retiming "true"
- attribute \src "ls180.v:2718.32-2718.59"
+ attribute \src "ls180.v:2714.32-2714.59"
wire \builder_multiregimpl7_regs1
attribute \no_retiming "true"
- attribute \src "ls180.v:2719.32-2719.59"
+ attribute \src "ls180.v:2715.32-2715.59"
wire \builder_multiregimpl8_regs0
attribute \no_retiming "true"
- attribute \src "ls180.v:2720.32-2720.59"
+ attribute \src "ls180.v:2716.32-2716.59"
wire \builder_multiregimpl8_regs1
attribute \no_retiming "true"
- attribute \src "ls180.v:2721.32-2721.59"
+ attribute \src "ls180.v:2717.32-2717.59"
wire \builder_multiregimpl9_regs0
attribute \no_retiming "true"
- attribute \src "ls180.v:2722.32-2722.59"
+ attribute \src "ls180.v:2718.32-2718.59"
wire \builder_multiregimpl9_regs1
- attribute \src "ls180.v:1775.5-1775.36"
+ attribute \src "ls180.v:1771.5-1771.36"
wire \builder_new_master_rdata_valid0
- attribute \src "ls180.v:1776.5-1776.36"
+ attribute \src "ls180.v:1772.5-1772.36"
wire \builder_new_master_rdata_valid1
- attribute \src "ls180.v:1777.5-1777.36"
+ attribute \src "ls180.v:1773.5-1773.36"
wire \builder_new_master_rdata_valid2
- attribute \src "ls180.v:1778.5-1778.36"
+ attribute \src "ls180.v:1774.5-1774.36"
wire \builder_new_master_rdata_valid3
- attribute \src "ls180.v:1774.5-1774.35"
+ attribute \src "ls180.v:1770.5-1770.35"
wire \builder_new_master_wdata_ready
- attribute \src "ls180.v:2593.11-2593.29"
+ attribute \src "ls180.v:2589.11-2589.29"
wire width 2 \builder_next_state
- attribute \src "ls180.v:1747.11-1747.39"
+ attribute \src "ls180.v:1743.11-1743.39"
wire width 2 \builder_refresher_next_state
- attribute \src "ls180.v:1746.11-1746.34"
+ attribute \src "ls180.v:1742.11-1742.34"
wire width 2 \builder_refresher_state
- attribute \src "ls180.v:1893.12-1893.27"
+ attribute \src "ls180.v:1889.12-1889.27"
wire width 5 \builder_request
- attribute \src "ls180.v:1760.6-1760.28"
+ attribute \src "ls180.v:1756.6-1756.28"
wire \builder_roundrobin0_ce
- attribute \src "ls180.v:1759.6-1759.31"
+ attribute \src "ls180.v:1755.6-1755.31"
wire \builder_roundrobin0_grant
- attribute \src "ls180.v:1758.6-1758.33"
+ attribute \src "ls180.v:1754.6-1754.33"
wire \builder_roundrobin0_request
- attribute \src "ls180.v:1763.6-1763.28"
+ attribute \src "ls180.v:1759.6-1759.28"
wire \builder_roundrobin1_ce
- attribute \src "ls180.v:1762.6-1762.31"
+ attribute \src "ls180.v:1758.6-1758.31"
wire \builder_roundrobin1_grant
- attribute \src "ls180.v:1761.6-1761.33"
+ attribute \src "ls180.v:1757.6-1757.33"
wire \builder_roundrobin1_request
- attribute \src "ls180.v:1766.6-1766.28"
+ attribute \src "ls180.v:1762.6-1762.28"
wire \builder_roundrobin2_ce
- attribute \src "ls180.v:1765.6-1765.31"
+ attribute \src "ls180.v:1761.6-1761.31"
wire \builder_roundrobin2_grant
- attribute \src "ls180.v:1764.6-1764.33"
+ attribute \src "ls180.v:1760.6-1760.33"
wire \builder_roundrobin2_request
- attribute \src "ls180.v:1769.6-1769.28"
+ attribute \src "ls180.v:1765.6-1765.28"
wire \builder_roundrobin3_ce
- attribute \src "ls180.v:1768.6-1768.31"
+ attribute \src "ls180.v:1764.6-1764.31"
wire \builder_roundrobin3_grant
- attribute \src "ls180.v:1767.6-1767.33"
+ attribute \src "ls180.v:1763.6-1763.33"
wire \builder_roundrobin3_request
- attribute \src "ls180.v:1856.11-1856.44"
+ attribute \src "ls180.v:1852.11-1852.44"
wire width 2 \builder_sdblock2memdma_next_state
- attribute \src "ls180.v:1855.11-1855.39"
+ attribute \src "ls180.v:1851.11-1851.39"
wire width 2 \builder_sdblock2memdma_state
- attribute \src "ls180.v:1824.5-1824.50"
+ attribute \src "ls180.v:1820.5-1820.50"
wire \builder_sdcore_crcupstreaminserter_next_state
- attribute \src "ls180.v:1823.5-1823.45"
+ attribute \src "ls180.v:1819.5-1819.45"
wire \builder_sdcore_crcupstreaminserter_state
- attribute \src "ls180.v:1836.11-1836.40"
+ attribute \src "ls180.v:1832.11-1832.40"
wire width 3 \builder_sdcore_fsm_next_state
- attribute \src "ls180.v:1835.11-1835.35"
+ attribute \src "ls180.v:1831.11-1831.35"
wire width 3 \builder_sdcore_fsm_state
- attribute \src "ls180.v:1860.5-1860.42"
+ attribute \src "ls180.v:1856.5-1856.42"
wire \builder_sdmem2blockdma_fsm_next_state
- attribute \src "ls180.v:1859.5-1859.37"
+ attribute \src "ls180.v:1855.5-1855.37"
wire \builder_sdmem2blockdma_fsm_state
- attribute \src "ls180.v:1864.11-1864.58"
+ attribute \src "ls180.v:1860.11-1860.58"
wire width 2 \builder_sdmem2blockdma_resetinserter_next_state
- attribute \src "ls180.v:1863.11-1863.53"
+ attribute \src "ls180.v:1859.11-1859.53"
wire width 2 \builder_sdmem2blockdma_resetinserter_state
- attribute \src "ls180.v:1812.11-1812.39"
+ attribute \src "ls180.v:1808.11-1808.39"
wire width 3 \builder_sdphy_fsm_next_state
- attribute \src "ls180.v:1811.11-1811.34"
+ attribute \src "ls180.v:1807.11-1807.34"
wire width 3 \builder_sdphy_fsm_state
- attribute \src "ls180.v:1800.11-1800.45"
+ attribute \src "ls180.v:1796.11-1796.45"
wire width 3 \builder_sdphy_sdphycmdr_next_state
- attribute \src "ls180.v:1799.11-1799.40"
+ attribute \src "ls180.v:1795.11-1795.40"
wire width 3 \builder_sdphy_sdphycmdr_state
- attribute \src "ls180.v:1796.11-1796.45"
+ attribute \src "ls180.v:1792.11-1792.45"
wire width 2 \builder_sdphy_sdphycmdw_next_state
- attribute \src "ls180.v:1795.11-1795.40"
+ attribute \src "ls180.v:1791.11-1791.40"
wire width 2 \builder_sdphy_sdphycmdw_state
- attribute \src "ls180.v:1808.5-1808.39"
+ attribute \src "ls180.v:1804.5-1804.39"
wire \builder_sdphy_sdphycrcr_next_state
- attribute \src "ls180.v:1807.5-1807.34"
+ attribute \src "ls180.v:1803.5-1803.34"
wire \builder_sdphy_sdphycrcr_state
- attribute \src "ls180.v:1816.11-1816.46"
+ attribute \src "ls180.v:1812.11-1812.46"
wire width 3 \builder_sdphy_sdphydatar_next_state
- attribute \src "ls180.v:1815.11-1815.41"
+ attribute \src "ls180.v:1811.11-1811.41"
wire width 3 \builder_sdphy_sdphydatar_state
- attribute \src "ls180.v:1792.5-1792.39"
+ attribute \src "ls180.v:1788.5-1788.39"
wire \builder_sdphy_sdphyinit_next_state
- attribute \src "ls180.v:1791.5-1791.34"
+ attribute \src "ls180.v:1787.5-1787.34"
wire \builder_sdphy_sdphyinit_state
- attribute \src "ls180.v:1888.5-1888.23"
+ attribute \src "ls180.v:1884.5-1884.23"
wire \builder_shared_ack
- attribute \src "ls180.v:1882.13-1882.31"
+ attribute \src "ls180.v:1878.13-1878.31"
wire width 30 \builder_shared_adr
- attribute \src "ls180.v:1891.12-1891.30"
+ attribute \src "ls180.v:1887.12-1887.30"
wire width 2 \builder_shared_bte
- attribute \src "ls180.v:1890.12-1890.30"
+ attribute \src "ls180.v:1886.12-1886.30"
wire width 3 \builder_shared_cti
- attribute \src "ls180.v:1886.6-1886.24"
+ attribute \src "ls180.v:1882.6-1882.24"
wire \builder_shared_cyc
- attribute \src "ls180.v:1884.12-1884.32"
+ attribute \src "ls180.v:1880.12-1880.32"
wire width 32 \builder_shared_dat_r
- attribute \src "ls180.v:1883.13-1883.33"
+ attribute \src "ls180.v:1879.13-1879.33"
wire width 32 \builder_shared_dat_w
- attribute \src "ls180.v:1892.6-1892.24"
+ attribute \src "ls180.v:1888.6-1888.24"
wire \builder_shared_err
- attribute \src "ls180.v:1885.12-1885.30"
+ attribute \src "ls180.v:1881.12-1881.30"
wire width 4 \builder_shared_sel
- attribute \src "ls180.v:1887.6-1887.24"
+ attribute \src "ls180.v:1883.6-1883.24"
wire \builder_shared_stb
- attribute \src "ls180.v:1889.6-1889.23"
+ attribute \src "ls180.v:1885.6-1885.23"
wire \builder_shared_we
- attribute \src "ls180.v:1895.11-1895.28"
+ attribute \src "ls180.v:1891.11-1891.28"
wire width 5 \builder_slave_sel
- attribute \src "ls180.v:1896.11-1896.30"
+ attribute \src "ls180.v:1892.11-1892.30"
wire width 5 \builder_slave_sel_r
- attribute \src "ls180.v:1784.11-1784.40"
+ attribute \src "ls180.v:1780.11-1780.40"
wire width 2 \builder_spimaster0_next_state
- attribute \src "ls180.v:1783.11-1783.35"
+ attribute \src "ls180.v:1779.11-1779.35"
wire width 2 \builder_spimaster0_state
- attribute \src "ls180.v:1788.11-1788.40"
+ attribute \src "ls180.v:1784.11-1784.40"
wire width 2 \builder_spimaster1_next_state
- attribute \src "ls180.v:1787.11-1787.35"
+ attribute \src "ls180.v:1783.11-1783.35"
wire width 2 \builder_spimaster1_state
- attribute \src "ls180.v:2592.11-2592.24"
+ attribute \src "ls180.v:2588.11-2588.24"
wire width 2 \builder_state
- attribute \src "ls180.v:2645.5-2645.32"
+ attribute \src "ls180.v:2641.5-2641.32"
wire \builder_sync_f_array_muxed0
- attribute \src "ls180.v:2646.5-2646.32"
+ attribute \src "ls180.v:2642.5-2642.32"
wire \builder_sync_f_array_muxed1
- attribute \src "ls180.v:2638.11-2638.40"
+ attribute \src "ls180.v:2634.11-2634.40"
wire width 2 \builder_sync_rhs_array_muxed0
- attribute \src "ls180.v:2639.12-2639.41"
+ attribute \src "ls180.v:2635.12-2635.41"
wire width 13 \builder_sync_rhs_array_muxed1
- attribute \src "ls180.v:2640.5-2640.34"
+ attribute \src "ls180.v:2636.5-2636.34"
wire \builder_sync_rhs_array_muxed2
- attribute \src "ls180.v:2641.5-2641.34"
+ attribute \src "ls180.v:2637.5-2637.34"
wire \builder_sync_rhs_array_muxed3
- attribute \src "ls180.v:2642.5-2642.34"
+ attribute \src "ls180.v:2638.5-2638.34"
wire \builder_sync_rhs_array_muxed4
- attribute \src "ls180.v:2643.5-2643.34"
+ attribute \src "ls180.v:2639.5-2639.34"
wire \builder_sync_rhs_array_muxed5
- attribute \src "ls180.v:2644.5-2644.34"
+ attribute \src "ls180.v:2640.5-2640.34"
wire \builder_sync_rhs_array_muxed6
- attribute \src "ls180.v:1898.6-1898.18"
+ attribute \src "ls180.v:1894.6-1894.18"
wire \builder_wait
- attribute \src "ls180.v:31.19-31.23"
- wire width 3 input 27 \eint
- attribute \src "ls180.v:150.12-150.18"
+ attribute \src "ls180.v:30.19-30.23"
+ wire width 3 input 26 \eint
+ attribute \src "ls180.v:145.12-145.18"
wire width 3 \eint_1
- attribute \src "ls180.v:36.20-36.26"
- wire width 16 input 32 \gpio_i
- attribute \src "ls180.v:37.21-37.27"
- wire width 16 output 33 \gpio_o
- attribute \src "ls180.v:38.21-38.28"
- wire width 16 output 34 \gpio_oe
- attribute \src "ls180.v:6.14-6.21"
- wire output 2 \i2c_scl
- attribute \src "ls180.v:7.13-7.22"
- wire input 3 \i2c_sda_i
- attribute \src "ls180.v:8.14-8.23"
- wire output 4 \i2c_sda_o
- attribute \src "ls180.v:9.14-9.24"
- wire output 5 \i2c_sda_oe
+ attribute \src "ls180.v:25.20-25.26"
+ wire width 16 input 21 \gpio_i
+ attribute \src "ls180.v:26.21-26.27"
+ wire width 16 output 22 \gpio_o
+ attribute \src "ls180.v:27.21-27.28"
+ wire width 16 output 23 \gpio_oe
+ attribute \src "ls180.v:5.14-5.21"
+ wire output 1 \i2c_scl
+ attribute \src "ls180.v:6.13-6.22"
+ wire input 2 \i2c_sda_i
+ attribute \src "ls180.v:7.14-7.23"
+ wire output 3 \i2c_sda_o
+ attribute \src "ls180.v:8.14-8.24"
+ wire output 4 \i2c_sda_oe
attribute \src "ls180.v:49.13-49.21"
wire input 45 \jtag_tck
attribute \src "ls180.v:50.13-50.21"
wire output 47 \jtag_tdo
attribute \src "ls180.v:48.13-48.21"
wire input 44 \jtag_tms
- attribute \src "ls180.v:838.6-838.18"
+ attribute \src "ls180.v:834.6-834.18"
wire \main_ack_cmd
- attribute \src "ls180.v:840.6-840.20"
+ attribute \src "ls180.v:836.6-836.20"
wire \main_ack_rdata
- attribute \src "ls180.v:839.6-839.20"
+ attribute \src "ls180.v:835.6-835.20"
wire \main_ack_wdata
- attribute \src "ls180.v:836.5-836.22"
+ attribute \src "ls180.v:832.5-832.22"
wire \main_cmd_consumed
- attribute \src "ls180.v:833.5-833.27"
+ attribute \src "ls180.v:829.5-829.27"
wire \main_converter_counter
- attribute \src "ls180.v:1781.5-1781.48"
+ attribute \src "ls180.v:1777.5-1777.48"
wire \main_converter_counter_converter_next_value
- attribute \src "ls180.v:1782.5-1782.51"
+ attribute \src "ls180.v:1778.5-1778.51"
wire \main_converter_counter_converter_next_value_ce
- attribute \src "ls180.v:835.12-835.32"
+ attribute \src "ls180.v:831.12-831.32"
wire width 32 \main_converter_dat_r
- attribute \src "ls180.v:834.6-834.26"
+ attribute \src "ls180.v:830.6-830.26"
wire \main_converter_reset
- attribute \src "ls180.v:832.5-832.24"
+ attribute \src "ls180.v:828.5-828.24"
wire \main_converter_skip
- attribute \src "ls180.v:262.6-262.23"
+ attribute \src "ls180.v:258.6-258.23"
wire \main_dfi_p0_act_n
- attribute \src "ls180.v:253.13-253.32"
+ attribute \src "ls180.v:249.13-249.32"
wire width 13 \main_dfi_p0_address
- attribute \src "ls180.v:254.12-254.28"
+ attribute \src "ls180.v:250.12-250.28"
wire width 2 \main_dfi_p0_bank
- attribute \src "ls180.v:255.6-255.23"
+ attribute \src "ls180.v:251.6-251.23"
wire \main_dfi_p0_cas_n
- attribute \src "ls180.v:259.6-259.21"
+ attribute \src "ls180.v:255.6-255.21"
wire \main_dfi_p0_cke
- attribute \src "ls180.v:256.6-256.22"
+ attribute \src "ls180.v:252.6-252.22"
wire \main_dfi_p0_cs_n
- attribute \src "ls180.v:260.6-260.21"
+ attribute \src "ls180.v:256.6-256.21"
wire \main_dfi_p0_odt
- attribute \src "ls180.v:257.6-257.23"
+ attribute \src "ls180.v:253.6-253.23"
wire \main_dfi_p0_ras_n
- attribute \src "ls180.v:267.12-267.30"
+ attribute \src "ls180.v:263.12-263.30"
wire width 16 \main_dfi_p0_rddata
- attribute \src "ls180.v:266.6-266.27"
+ attribute \src "ls180.v:262.6-262.27"
wire \main_dfi_p0_rddata_en
- attribute \src "ls180.v:268.5-268.29"
+ attribute \src "ls180.v:264.5-264.29"
wire \main_dfi_p0_rddata_valid
- attribute \src "ls180.v:261.6-261.25"
+ attribute \src "ls180.v:257.6-257.25"
wire \main_dfi_p0_reset_n
- attribute \src "ls180.v:258.6-258.22"
+ attribute \src "ls180.v:254.6-254.22"
wire \main_dfi_p0_we_n
- attribute \src "ls180.v:263.13-263.31"
+ attribute \src "ls180.v:259.13-259.31"
wire width 16 \main_dfi_p0_wrdata
- attribute \src "ls180.v:264.6-264.27"
+ attribute \src "ls180.v:260.6-260.27"
wire \main_dfi_p0_wrdata_en
- attribute \src "ls180.v:265.12-265.35"
+ attribute \src "ls180.v:261.12-261.35"
wire width 2 \main_dfi_p0_wrdata_mask
- attribute \src "ls180.v:1067.12-1067.22"
+ attribute \src "ls180.v:1063.12-1063.22"
wire width 24 \main_dummy
- attribute \src "ls180.v:984.5-984.20"
+ attribute \src "ls180.v:980.5-980.20"
wire \main_gpio_oe_re
- attribute \src "ls180.v:983.12-983.32"
+ attribute \src "ls180.v:979.12-979.32"
wire width 16 \main_gpio_oe_storage
- attribute \src "ls180.v:988.5-988.21"
+ attribute \src "ls180.v:984.5-984.21"
wire \main_gpio_out_re
- attribute \src "ls180.v:987.12-987.33"
+ attribute \src "ls180.v:983.12-983.33"
wire width 16 \main_gpio_out_storage
- attribute \src "ls180.v:989.13-989.29"
+ attribute \src "ls180.v:985.13-985.29"
wire width 16 \main_gpio_pads_i
- attribute \src "ls180.v:990.13-990.29"
+ attribute \src "ls180.v:986.13-986.29"
wire width 16 \main_gpio_pads_o
- attribute \src "ls180.v:991.13-991.30"
+ attribute \src "ls180.v:987.13-987.30"
wire width 16 \main_gpio_pads_oe
- attribute \src "ls180.v:985.12-985.28"
+ attribute \src "ls180.v:981.12-981.28"
wire width 16 \main_gpio_status
- attribute \src "ls180.v:986.6-986.18"
+ attribute \src "ls180.v:982.6-982.18"
wire \main_gpio_we
- attribute \src "ls180.v:1089.6-1089.17"
+ attribute \src "ls180.v:1085.6-1085.17"
wire \main_i2c_oe
- attribute \src "ls180.v:1092.5-1092.16"
+ attribute \src "ls180.v:1088.5-1088.16"
wire \main_i2c_re
- attribute \src "ls180.v:1088.6-1088.18"
+ attribute \src "ls180.v:1084.6-1084.18"
wire \main_i2c_scl
- attribute \src "ls180.v:1090.6-1090.19"
+ attribute \src "ls180.v:1086.6-1086.19"
wire \main_i2c_sda0
- attribute \src "ls180.v:1093.6-1093.19"
+ attribute \src "ls180.v:1089.6-1089.19"
wire \main_i2c_sda1
- attribute \src "ls180.v:1094.6-1094.21"
+ attribute \src "ls180.v:1090.6-1090.21"
wire \main_i2c_status
- attribute \src "ls180.v:1091.11-1091.27"
+ attribute \src "ls180.v:1087.11-1087.27"
wire width 3 \main_i2c_storage
- attribute \src "ls180.v:1095.6-1095.17"
+ attribute \src "ls180.v:1091.6-1091.17"
wire \main_i2c_we
- attribute \src "ls180.v:252.5-252.17"
+ attribute \src "ls180.v:248.5-248.17"
wire \main_int_rst
- attribute \src "ls180.v:1555.6-1555.29"
+ attribute \src "ls180.v:1551.6-1551.29"
wire \main_interface0_bus_ack
- attribute \src "ls180.v:1549.13-1549.36"
+ attribute \src "ls180.v:1545.13-1545.36"
wire width 32 \main_interface0_bus_adr
- attribute \src "ls180.v:1558.11-1558.34"
+ attribute \src "ls180.v:1554.11-1554.34"
wire width 2 \main_interface0_bus_bte
- attribute \src "ls180.v:1557.11-1557.34"
+ attribute \src "ls180.v:1553.11-1553.34"
wire width 3 \main_interface0_bus_cti
- attribute \src "ls180.v:1553.6-1553.29"
+ attribute \src "ls180.v:1549.6-1549.29"
wire \main_interface0_bus_cyc
- attribute \src "ls180.v:1551.13-1551.38"
+ attribute \src "ls180.v:1547.13-1547.38"
wire width 32 \main_interface0_bus_dat_r
- attribute \src "ls180.v:1550.13-1550.38"
+ attribute \src "ls180.v:1546.13-1546.38"
wire width 32 \main_interface0_bus_dat_w
- attribute \src "ls180.v:1559.6-1559.29"
+ attribute \src "ls180.v:1555.6-1555.29"
wire \main_interface0_bus_err
- attribute \src "ls180.v:1552.12-1552.35"
+ attribute \src "ls180.v:1548.12-1548.35"
wire width 4 \main_interface0_bus_sel
- attribute \src "ls180.v:1554.6-1554.29"
+ attribute \src "ls180.v:1550.6-1550.29"
wire \main_interface0_bus_stb
- attribute \src "ls180.v:1556.6-1556.28"
+ attribute \src "ls180.v:1552.6-1552.28"
wire \main_interface0_bus_we
- attribute \src "ls180.v:1646.6-1646.29"
+ attribute \src "ls180.v:1642.6-1642.29"
wire \main_interface1_bus_ack
- attribute \src "ls180.v:1640.12-1640.35"
+ attribute \src "ls180.v:1636.12-1636.35"
wire width 32 \main_interface1_bus_adr
- attribute \src "ls180.v:1649.11-1649.34"
+ attribute \src "ls180.v:1645.11-1645.34"
wire width 2 \main_interface1_bus_bte
- attribute \src "ls180.v:1648.11-1648.34"
+ attribute \src "ls180.v:1644.11-1644.34"
wire width 3 \main_interface1_bus_cti
- attribute \src "ls180.v:1644.5-1644.28"
+ attribute \src "ls180.v:1640.5-1640.28"
wire \main_interface1_bus_cyc
- attribute \src "ls180.v:1642.13-1642.38"
+ attribute \src "ls180.v:1638.13-1638.38"
wire width 32 \main_interface1_bus_dat_r
- attribute \src "ls180.v:1641.12-1641.37"
+ attribute \src "ls180.v:1637.12-1637.37"
wire width 32 \main_interface1_bus_dat_w
- attribute \src "ls180.v:1650.6-1650.29"
+ attribute \src "ls180.v:1646.6-1646.29"
wire \main_interface1_bus_err
- attribute \src "ls180.v:1643.11-1643.34"
+ attribute \src "ls180.v:1639.11-1639.34"
wire width 4 \main_interface1_bus_sel
- attribute \src "ls180.v:1645.5-1645.28"
+ attribute \src "ls180.v:1641.5-1641.28"
wire \main_interface1_bus_stb
- attribute \src "ls180.v:1647.5-1647.27"
+ attribute \src "ls180.v:1643.5-1643.27"
wire \main_interface1_bus_we
- attribute \src "ls180.v:218.12-218.32"
+ attribute \src "ls180.v:214.12-214.32"
wire width 7 \main_libresocsim_adr
attribute \src "ls180.v:62.6-62.32"
wire \main_libresocsim_bus_error
wire width 32 \main_libresocsim_bus_errors_status
attribute \src "ls180.v:60.6-60.36"
wire \main_libresocsim_bus_errors_we
- attribute \src "ls180.v:174.5-174.40"
+ attribute \src "ls180.v:170.5-170.40"
wire \main_libresocsim_converter0_counter
- attribute \src "ls180.v:1736.5-1736.62"
+ attribute \src "ls180.v:1732.5-1732.62"
wire \main_libresocsim_converter0_counter_converter0_next_value
- attribute \src "ls180.v:1737.5-1737.65"
+ attribute \src "ls180.v:1733.5-1733.65"
wire \main_libresocsim_converter0_counter_converter0_next_value_ce
- attribute \src "ls180.v:176.12-176.45"
+ attribute \src "ls180.v:172.12-172.45"
wire width 64 \main_libresocsim_converter0_dat_r
- attribute \src "ls180.v:175.6-175.39"
+ attribute \src "ls180.v:171.6-171.39"
wire \main_libresocsim_converter0_reset
- attribute \src "ls180.v:173.5-173.37"
+ attribute \src "ls180.v:169.5-169.37"
wire \main_libresocsim_converter0_skip
- attribute \src "ls180.v:189.5-189.40"
+ attribute \src "ls180.v:185.5-185.40"
wire \main_libresocsim_converter1_counter
- attribute \src "ls180.v:1740.5-1740.62"
+ attribute \src "ls180.v:1736.5-1736.62"
wire \main_libresocsim_converter1_counter_converter1_next_value
- attribute \src "ls180.v:1741.5-1741.65"
+ attribute \src "ls180.v:1737.5-1737.65"
wire \main_libresocsim_converter1_counter_converter1_next_value_ce
- attribute \src "ls180.v:191.12-191.45"
+ attribute \src "ls180.v:187.12-187.45"
wire width 64 \main_libresocsim_converter1_dat_r
- attribute \src "ls180.v:190.6-190.39"
+ attribute \src "ls180.v:186.6-186.39"
wire \main_libresocsim_converter1_reset
- attribute \src "ls180.v:188.5-188.37"
+ attribute \src "ls180.v:184.5-184.37"
wire \main_libresocsim_converter1_skip
- attribute \src "ls180.v:204.5-204.40"
+ attribute \src "ls180.v:200.5-200.40"
wire \main_libresocsim_converter2_counter
- attribute \src "ls180.v:1744.5-1744.62"
+ attribute \src "ls180.v:1740.5-1740.62"
wire \main_libresocsim_converter2_counter_converter2_next_value
- attribute \src "ls180.v:1745.5-1745.65"
+ attribute \src "ls180.v:1741.5-1741.65"
wire \main_libresocsim_converter2_counter_converter2_next_value_ce
- attribute \src "ls180.v:206.12-206.45"
+ attribute \src "ls180.v:202.12-202.45"
wire width 64 \main_libresocsim_converter2_dat_r
- attribute \src "ls180.v:205.6-205.39"
+ attribute \src "ls180.v:201.6-201.39"
wire \main_libresocsim_converter2_reset
- attribute \src "ls180.v:203.5-203.37"
+ attribute \src "ls180.v:199.5-199.37"
wire \main_libresocsim_converter2_skip
- attribute \src "ls180.v:219.13-219.35"
+ attribute \src "ls180.v:215.13-215.35"
wire width 32 \main_libresocsim_dat_r
- attribute \src "ls180.v:221.13-221.35"
+ attribute \src "ls180.v:217.13-217.35"
wire width 32 \main_libresocsim_dat_w
- attribute \src "ls180.v:227.5-227.27"
+ attribute \src "ls180.v:223.5-223.27"
wire \main_libresocsim_en_re
- attribute \src "ls180.v:226.5-226.32"
+ attribute \src "ls180.v:222.5-222.32"
wire \main_libresocsim_en_storage
- attribute \src "ls180.v:243.6-243.45"
+ attribute \src "ls180.v:239.6-239.45"
wire \main_libresocsim_eventmanager_pending_r
- attribute \src "ls180.v:242.6-242.46"
+ attribute \src "ls180.v:238.6-238.46"
wire \main_libresocsim_eventmanager_pending_re
- attribute \src "ls180.v:245.6-245.45"
+ attribute \src "ls180.v:241.6-241.45"
wire \main_libresocsim_eventmanager_pending_w
- attribute \src "ls180.v:244.6-244.46"
+ attribute \src "ls180.v:240.6-240.46"
wire \main_libresocsim_eventmanager_pending_we
- attribute \src "ls180.v:247.5-247.37"
+ attribute \src "ls180.v:243.5-243.37"
wire \main_libresocsim_eventmanager_re
- attribute \src "ls180.v:239.6-239.44"
+ attribute \src "ls180.v:235.6-235.44"
wire \main_libresocsim_eventmanager_status_r
- attribute \src "ls180.v:238.6-238.45"
+ attribute \src "ls180.v:234.6-234.45"
wire \main_libresocsim_eventmanager_status_re
- attribute \src "ls180.v:241.6-241.44"
+ attribute \src "ls180.v:237.6-237.44"
wire \main_libresocsim_eventmanager_status_w
- attribute \src "ls180.v:240.6-240.45"
+ attribute \src "ls180.v:236.6-236.45"
wire \main_libresocsim_eventmanager_status_we
- attribute \src "ls180.v:246.5-246.42"
+ attribute \src "ls180.v:242.5-242.42"
wire \main_libresocsim_eventmanager_storage
- attribute \src "ls180.v:168.6-168.57"
+ attribute \src "ls180.v:164.6-164.57"
wire \main_libresocsim_interface0_converted_interface_ack
- attribute \src "ls180.v:162.12-162.63"
+ attribute \src "ls180.v:158.12-158.63"
wire width 30 \main_libresocsim_interface0_converted_interface_adr
- attribute \src "ls180.v:171.11-171.62"
+ attribute \src "ls180.v:167.11-167.62"
wire width 2 \main_libresocsim_interface0_converted_interface_bte
- attribute \src "ls180.v:170.11-170.62"
+ attribute \src "ls180.v:166.11-166.62"
wire width 3 \main_libresocsim_interface0_converted_interface_cti
- attribute \src "ls180.v:166.5-166.56"
+ attribute \src "ls180.v:162.5-162.56"
wire \main_libresocsim_interface0_converted_interface_cyc
- attribute \src "ls180.v:164.13-164.66"
+ attribute \src "ls180.v:160.13-160.66"
wire width 32 \main_libresocsim_interface0_converted_interface_dat_r
- attribute \src "ls180.v:163.12-163.65"
+ attribute \src "ls180.v:159.12-159.65"
wire width 32 \main_libresocsim_interface0_converted_interface_dat_w
- attribute \src "ls180.v:172.6-172.57"
+ attribute \src "ls180.v:168.6-168.57"
wire \main_libresocsim_interface0_converted_interface_err
- attribute \src "ls180.v:165.11-165.62"
+ attribute \src "ls180.v:161.11-161.62"
wire width 4 \main_libresocsim_interface0_converted_interface_sel
- attribute \src "ls180.v:167.5-167.56"
+ attribute \src "ls180.v:163.5-163.56"
wire \main_libresocsim_interface0_converted_interface_stb
- attribute \src "ls180.v:169.5-169.55"
+ attribute \src "ls180.v:165.5-165.55"
wire \main_libresocsim_interface0_converted_interface_we
- attribute \src "ls180.v:183.6-183.57"
+ attribute \src "ls180.v:179.6-179.57"
wire \main_libresocsim_interface1_converted_interface_ack
- attribute \src "ls180.v:177.12-177.63"
+ attribute \src "ls180.v:173.12-173.63"
wire width 30 \main_libresocsim_interface1_converted_interface_adr
- attribute \src "ls180.v:186.11-186.62"
+ attribute \src "ls180.v:182.11-182.62"
wire width 2 \main_libresocsim_interface1_converted_interface_bte
- attribute \src "ls180.v:185.11-185.62"
+ attribute \src "ls180.v:181.11-181.62"
wire width 3 \main_libresocsim_interface1_converted_interface_cti
- attribute \src "ls180.v:181.5-181.56"
+ attribute \src "ls180.v:177.5-177.56"
wire \main_libresocsim_interface1_converted_interface_cyc
- attribute \src "ls180.v:179.13-179.66"
+ attribute \src "ls180.v:175.13-175.66"
wire width 32 \main_libresocsim_interface1_converted_interface_dat_r
- attribute \src "ls180.v:178.12-178.65"
+ attribute \src "ls180.v:174.12-174.65"
wire width 32 \main_libresocsim_interface1_converted_interface_dat_w
- attribute \src "ls180.v:187.6-187.57"
+ attribute \src "ls180.v:183.6-183.57"
wire \main_libresocsim_interface1_converted_interface_err
- attribute \src "ls180.v:180.11-180.62"
+ attribute \src "ls180.v:176.11-176.62"
wire width 4 \main_libresocsim_interface1_converted_interface_sel
- attribute \src "ls180.v:182.5-182.56"
+ attribute \src "ls180.v:178.5-178.56"
wire \main_libresocsim_interface1_converted_interface_stb
- attribute \src "ls180.v:184.5-184.55"
+ attribute \src "ls180.v:180.5-180.55"
wire \main_libresocsim_interface1_converted_interface_we
- attribute \src "ls180.v:198.6-198.57"
+ attribute \src "ls180.v:194.6-194.57"
wire \main_libresocsim_interface2_converted_interface_ack
- attribute \src "ls180.v:192.12-192.63"
+ attribute \src "ls180.v:188.12-188.63"
wire width 30 \main_libresocsim_interface2_converted_interface_adr
- attribute \src "ls180.v:201.11-201.62"
+ attribute \src "ls180.v:197.11-197.62"
wire width 2 \main_libresocsim_interface2_converted_interface_bte
- attribute \src "ls180.v:200.11-200.62"
+ attribute \src "ls180.v:196.11-196.62"
wire width 3 \main_libresocsim_interface2_converted_interface_cti
- attribute \src "ls180.v:196.5-196.56"
+ attribute \src "ls180.v:192.5-192.56"
wire \main_libresocsim_interface2_converted_interface_cyc
- attribute \src "ls180.v:194.13-194.66"
+ attribute \src "ls180.v:190.13-190.66"
wire width 32 \main_libresocsim_interface2_converted_interface_dat_r
- attribute \src "ls180.v:193.12-193.65"
+ attribute \src "ls180.v:189.12-189.65"
wire width 32 \main_libresocsim_interface2_converted_interface_dat_w
- attribute \src "ls180.v:202.6-202.57"
+ attribute \src "ls180.v:198.6-198.57"
wire \main_libresocsim_interface2_converted_interface_err
- attribute \src "ls180.v:195.11-195.62"
+ attribute \src "ls180.v:191.11-191.62"
wire width 4 \main_libresocsim_interface2_converted_interface_sel
- attribute \src "ls180.v:197.5-197.56"
+ attribute \src "ls180.v:193.5-193.56"
wire \main_libresocsim_interface2_converted_interface_stb
- attribute \src "ls180.v:199.5-199.55"
+ attribute \src "ls180.v:195.5-195.55"
wire \main_libresocsim_interface2_converted_interface_we
- attribute \src "ls180.v:232.6-232.26"
+ attribute \src "ls180.v:228.6-228.26"
wire \main_libresocsim_irq
- attribute \src "ls180.v:123.6-123.32"
+ attribute \src "ls180.v:119.6-119.32"
wire \main_libresocsim_libresoc0
- attribute \src "ls180.v:124.6-124.32"
+ attribute \src "ls180.v:120.6-120.32"
wire \main_libresocsim_libresoc1
- attribute \src "ls180.v:125.13-125.39"
+ attribute \src "ls180.v:121.13-121.39"
wire width 64 \main_libresocsim_libresoc2
- attribute \src "ls180.v:127.12-127.45"
+ attribute \src "ls180.v:123.12-123.45"
wire width 2 \main_libresocsim_libresoc_clk_sel
- attribute \src "ls180.v:155.13-155.67"
+ attribute \src "ls180.v:142.13-142.67"
wire width 16 \main_libresocsim_libresoc_constraintmanager_obj_gpio_i
- attribute \src "ls180.v:156.13-156.67"
+ attribute \src "ls180.v:143.13-143.67"
wire width 16 \main_libresocsim_libresoc_constraintmanager_obj_gpio_o
- attribute \src "ls180.v:157.13-157.68"
+ attribute \src "ls180.v:144.13-144.68"
wire width 16 \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe
- attribute \src "ls180.v:130.6-130.61"
+ attribute \src "ls180.v:125.6-125.61"
wire \main_libresocsim_libresoc_constraintmanager_obj_i2c_scl
- attribute \src "ls180.v:131.6-131.63"
+ attribute \src "ls180.v:126.6-126.63"
wire \main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_i
- attribute \src "ls180.v:132.6-132.63"
+ attribute \src "ls180.v:127.6-127.63"
wire \main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_o
- attribute \src "ls180.v:133.6-133.64"
+ attribute \src "ls180.v:128.6-128.64"
wire \main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_oe
attribute \src "ls180.v:134.6-134.64"
wire \main_libresocsim_libresoc_constraintmanager_obj_sdcard_clk
wire \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_o
attribute \src "ls180.v:137.6-137.67"
wire \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_oe
- attribute \src "ls180.v:138.13-138.68"
+ attribute \src "ls180.v:146.13-146.68"
wire width 13 \main_libresocsim_libresoc_constraintmanager_obj_sdram_a
- attribute \src "ls180.v:147.12-147.68"
+ attribute \src "ls180.v:155.12-155.68"
wire width 2 \main_libresocsim_libresoc_constraintmanager_obj_sdram_ba
- attribute \src "ls180.v:144.6-144.65"
+ attribute \src "ls180.v:152.6-152.65"
wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_cas_n
- attribute \src "ls180.v:146.6-146.63"
+ attribute \src "ls180.v:154.6-154.63"
wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_cke
- attribute \src "ls180.v:145.6-145.64"
+ attribute \src "ls180.v:153.6-153.64"
wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_cs_n
- attribute \src "ls180.v:148.12-148.68"
+ attribute \src "ls180.v:156.12-156.68"
wire width 2 \main_libresocsim_libresoc_constraintmanager_obj_sdram_dm
- attribute \src "ls180.v:139.13-139.71"
+ attribute \src "ls180.v:147.13-147.71"
wire width 16 \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i
- attribute \src "ls180.v:140.13-140.71"
+ attribute \src "ls180.v:148.13-148.71"
wire width 16 \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o
- attribute \src "ls180.v:141.6-141.65"
+ attribute \src "ls180.v:149.6-149.65"
wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe
- attribute \src "ls180.v:143.6-143.65"
+ attribute \src "ls180.v:151.6-151.65"
wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_ras_n
- attribute \src "ls180.v:142.6-142.64"
+ attribute \src "ls180.v:150.6-150.64"
wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_we_n
- attribute \src "ls180.v:151.6-151.67"
+ attribute \src "ls180.v:138.6-138.67"
wire \main_libresocsim_libresoc_constraintmanager_obj_spimaster_clk
- attribute \src "ls180.v:153.6-153.68"
+ attribute \src "ls180.v:140.6-140.68"
wire \main_libresocsim_libresoc_constraintmanager_obj_spimaster_cs_n
- attribute \src "ls180.v:154.6-154.68"
+ attribute \src "ls180.v:141.6-141.68"
wire \main_libresocsim_libresoc_constraintmanager_obj_spimaster_miso
- attribute \src "ls180.v:152.6-152.68"
+ attribute \src "ls180.v:139.6-139.68"
wire \main_libresocsim_libresoc_constraintmanager_obj_spimaster_mosi
- attribute \src "ls180.v:158.6-158.67"
+ attribute \src "ls180.v:130.6-130.67"
wire \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_clk
- attribute \src "ls180.v:160.6-160.68"
+ attribute \src "ls180.v:132.6-132.68"
wire \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_cs_n
- attribute \src "ls180.v:161.6-161.68"
+ attribute \src "ls180.v:133.6-133.68"
wire \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_miso
- attribute \src "ls180.v:159.6-159.68"
+ attribute \src "ls180.v:131.6-131.68"
wire \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_mosi
attribute \src "ls180.v:72.5-72.39"
wire \main_libresocsim_libresoc_dbus_ack
attribute \src "ls180.v:66.13-66.47"
wire width 29 \main_libresocsim_libresoc_dbus_adr
- attribute \src "ls180.v:75.12-75.46"
- wire width 2 \main_libresocsim_libresoc_dbus_bte
- attribute \src "ls180.v:74.12-74.46"
- wire width 3 \main_libresocsim_libresoc_dbus_cti
attribute \src "ls180.v:70.6-70.40"
wire \main_libresocsim_libresoc_dbus_cyc
attribute \src "ls180.v:68.13-68.49"
wire width 64 \main_libresocsim_libresoc_dbus_dat_r
attribute \src "ls180.v:67.13-67.49"
wire width 64 \main_libresocsim_libresoc_dbus_dat_w
- attribute \src "ls180.v:76.5-76.39"
+ attribute \src "ls180.v:74.5-74.39"
wire \main_libresocsim_libresoc_dbus_err
attribute \src "ls180.v:69.12-69.46"
wire width 8 \main_libresocsim_libresoc_dbus_sel
wire \main_libresocsim_libresoc_dbus_stb
attribute \src "ls180.v:73.6-73.39"
wire \main_libresocsim_libresoc_dbus_we
- attribute \src "ls180.v:83.5-83.39"
+ attribute \src "ls180.v:81.5-81.39"
wire \main_libresocsim_libresoc_ibus_ack
- attribute \src "ls180.v:77.13-77.47"
+ attribute \src "ls180.v:75.13-75.47"
wire width 29 \main_libresocsim_libresoc_ibus_adr
- attribute \src "ls180.v:86.12-86.46"
- wire width 2 \main_libresocsim_libresoc_ibus_bte
- attribute \src "ls180.v:85.12-85.46"
- wire width 3 \main_libresocsim_libresoc_ibus_cti
- attribute \src "ls180.v:81.6-81.40"
+ attribute \src "ls180.v:79.6-79.40"
wire \main_libresocsim_libresoc_ibus_cyc
- attribute \src "ls180.v:79.13-79.49"
+ attribute \src "ls180.v:77.13-77.49"
wire width 64 \main_libresocsim_libresoc_ibus_dat_r
- attribute \src "ls180.v:78.13-78.49"
+ attribute \src "ls180.v:76.13-76.49"
wire width 64 \main_libresocsim_libresoc_ibus_dat_w
- attribute \src "ls180.v:87.5-87.39"
+ attribute \src "ls180.v:83.5-83.39"
wire \main_libresocsim_libresoc_ibus_err
- attribute \src "ls180.v:80.12-80.46"
+ attribute \src "ls180.v:78.12-78.46"
wire width 8 \main_libresocsim_libresoc_ibus_sel
- attribute \src "ls180.v:82.6-82.40"
+ attribute \src "ls180.v:80.6-80.40"
wire \main_libresocsim_libresoc_ibus_stb
- attribute \src "ls180.v:84.6-84.39"
+ attribute \src "ls180.v:82.6-82.39"
wire \main_libresocsim_libresoc_ibus_we
attribute \src "ls180.v:65.12-65.47"
wire width 16 \main_libresocsim_libresoc_interrupt
- attribute \src "ls180.v:119.6-119.40"
+ attribute \src "ls180.v:115.6-115.40"
wire \main_libresocsim_libresoc_jtag_tck
- attribute \src "ls180.v:121.6-121.40"
+ attribute \src "ls180.v:117.6-117.40"
wire \main_libresocsim_libresoc_jtag_tdi
- attribute \src "ls180.v:122.6-122.40"
+ attribute \src "ls180.v:118.6-118.40"
wire \main_libresocsim_libresoc_jtag_tdo
- attribute \src "ls180.v:120.6-120.40"
+ attribute \src "ls180.v:116.6-116.40"
wire \main_libresocsim_libresoc_jtag_tms
- attribute \src "ls180.v:116.5-116.42"
+ attribute \src "ls180.v:112.5-112.42"
wire \main_libresocsim_libresoc_jtag_wb_ack
- attribute \src "ls180.v:110.13-110.50"
+ attribute \src "ls180.v:106.13-106.50"
wire width 29 \main_libresocsim_libresoc_jtag_wb_adr
- attribute \src "ls180.v:114.6-114.43"
+ attribute \src "ls180.v:110.6-110.43"
wire \main_libresocsim_libresoc_jtag_wb_cyc
- attribute \src "ls180.v:112.13-112.52"
+ attribute \src "ls180.v:108.13-108.52"
wire width 64 \main_libresocsim_libresoc_jtag_wb_dat_r
- attribute \src "ls180.v:111.13-111.52"
+ attribute \src "ls180.v:107.13-107.52"
wire width 64 \main_libresocsim_libresoc_jtag_wb_dat_w
- attribute \src "ls180.v:118.5-118.42"
+ attribute \src "ls180.v:114.5-114.42"
wire \main_libresocsim_libresoc_jtag_wb_err
- attribute \src "ls180.v:113.12-113.49"
+ attribute \src "ls180.v:109.12-109.49"
wire width 8 \main_libresocsim_libresoc_jtag_wb_sel
- attribute \src "ls180.v:115.6-115.43"
+ attribute \src "ls180.v:111.6-111.43"
wire \main_libresocsim_libresoc_jtag_wb_stb
- attribute \src "ls180.v:117.6-117.42"
+ attribute \src "ls180.v:113.6-113.42"
wire \main_libresocsim_libresoc_jtag_wb_we
- attribute \src "ls180.v:126.6-126.40"
+ attribute \src "ls180.v:122.6-122.40"
wire \main_libresocsim_libresoc_pll_18_o
- attribute \src "ls180.v:128.6-128.41"
+ attribute \src "ls180.v:124.6-124.41"
wire \main_libresocsim_libresoc_pll_lck_o
attribute \src "ls180.v:64.6-64.37"
wire \main_libresocsim_libresoc_reset
- attribute \src "ls180.v:94.6-94.44"
+ attribute \src "ls180.v:90.6-90.44"
wire \main_libresocsim_libresoc_xics_icp_ack
- attribute \src "ls180.v:88.13-88.51"
+ attribute \src "ls180.v:84.13-84.51"
wire width 30 \main_libresocsim_libresoc_xics_icp_adr
- attribute \src "ls180.v:97.12-97.50"
+ attribute \src "ls180.v:93.12-93.50"
wire width 2 \main_libresocsim_libresoc_xics_icp_bte
- attribute \src "ls180.v:96.12-96.50"
+ attribute \src "ls180.v:92.12-92.50"
wire width 3 \main_libresocsim_libresoc_xics_icp_cti
- attribute \src "ls180.v:92.6-92.44"
+ attribute \src "ls180.v:88.6-88.44"
wire \main_libresocsim_libresoc_xics_icp_cyc
- attribute \src "ls180.v:90.13-90.53"
+ attribute \src "ls180.v:86.13-86.53"
wire width 32 \main_libresocsim_libresoc_xics_icp_dat_r
- attribute \src "ls180.v:89.13-89.53"
+ attribute \src "ls180.v:85.13-85.53"
wire width 32 \main_libresocsim_libresoc_xics_icp_dat_w
- attribute \src "ls180.v:98.6-98.44"
+ attribute \src "ls180.v:94.6-94.44"
wire \main_libresocsim_libresoc_xics_icp_err
- attribute \src "ls180.v:91.12-91.50"
+ attribute \src "ls180.v:87.12-87.50"
wire width 4 \main_libresocsim_libresoc_xics_icp_sel
- attribute \src "ls180.v:93.6-93.44"
+ attribute \src "ls180.v:89.6-89.44"
wire \main_libresocsim_libresoc_xics_icp_stb
- attribute \src "ls180.v:95.6-95.43"
+ attribute \src "ls180.v:91.6-91.43"
wire \main_libresocsim_libresoc_xics_icp_we
- attribute \src "ls180.v:105.6-105.44"
+ attribute \src "ls180.v:101.6-101.44"
wire \main_libresocsim_libresoc_xics_ics_ack
- attribute \src "ls180.v:99.13-99.51"
+ attribute \src "ls180.v:95.13-95.51"
wire width 30 \main_libresocsim_libresoc_xics_ics_adr
- attribute \src "ls180.v:108.12-108.50"
+ attribute \src "ls180.v:104.12-104.50"
wire width 2 \main_libresocsim_libresoc_xics_ics_bte
- attribute \src "ls180.v:107.12-107.50"
+ attribute \src "ls180.v:103.12-103.50"
wire width 3 \main_libresocsim_libresoc_xics_ics_cti
- attribute \src "ls180.v:103.6-103.44"
+ attribute \src "ls180.v:99.6-99.44"
wire \main_libresocsim_libresoc_xics_ics_cyc
- attribute \src "ls180.v:101.13-101.53"
+ attribute \src "ls180.v:97.13-97.53"
wire width 32 \main_libresocsim_libresoc_xics_ics_dat_r
- attribute \src "ls180.v:100.13-100.53"
+ attribute \src "ls180.v:96.13-96.53"
wire width 32 \main_libresocsim_libresoc_xics_ics_dat_w
- attribute \src "ls180.v:109.6-109.44"
+ attribute \src "ls180.v:105.6-105.44"
wire \main_libresocsim_libresoc_xics_ics_err
- attribute \src "ls180.v:102.12-102.50"
+ attribute \src "ls180.v:98.12-98.50"
wire width 4 \main_libresocsim_libresoc_xics_ics_sel
- attribute \src "ls180.v:104.6-104.44"
+ attribute \src "ls180.v:100.6-100.44"
wire \main_libresocsim_libresoc_xics_ics_stb
- attribute \src "ls180.v:106.6-106.43"
+ attribute \src "ls180.v:102.6-102.43"
wire \main_libresocsim_libresoc_xics_ics_we
- attribute \src "ls180.v:223.5-223.29"
+ attribute \src "ls180.v:219.5-219.29"
wire \main_libresocsim_load_re
- attribute \src "ls180.v:222.12-222.41"
+ attribute \src "ls180.v:218.12-218.41"
wire width 32 \main_libresocsim_load_storage
- attribute \src "ls180.v:213.5-213.33"
+ attribute \src "ls180.v:209.5-209.33"
wire \main_libresocsim_ram_bus_ack
- attribute \src "ls180.v:207.13-207.41"
+ attribute \src "ls180.v:203.13-203.41"
wire width 30 \main_libresocsim_ram_bus_adr
- attribute \src "ls180.v:216.12-216.40"
+ attribute \src "ls180.v:212.12-212.40"
wire width 2 \main_libresocsim_ram_bus_bte
- attribute \src "ls180.v:215.12-215.40"
+ attribute \src "ls180.v:211.12-211.40"
wire width 3 \main_libresocsim_ram_bus_cti
- attribute \src "ls180.v:211.6-211.34"
+ attribute \src "ls180.v:207.6-207.34"
wire \main_libresocsim_ram_bus_cyc
- attribute \src "ls180.v:209.13-209.43"
+ attribute \src "ls180.v:205.13-205.43"
wire width 32 \main_libresocsim_ram_bus_dat_r
- attribute \src "ls180.v:208.13-208.43"
+ attribute \src "ls180.v:204.13-204.43"
wire width 32 \main_libresocsim_ram_bus_dat_w
- attribute \src "ls180.v:217.5-217.33"
+ attribute \src "ls180.v:213.5-213.33"
wire \main_libresocsim_ram_bus_err
- attribute \src "ls180.v:210.12-210.40"
+ attribute \src "ls180.v:206.12-206.40"
wire width 4 \main_libresocsim_ram_bus_sel
- attribute \src "ls180.v:212.6-212.34"
+ attribute \src "ls180.v:208.6-208.34"
wire \main_libresocsim_ram_bus_stb
- attribute \src "ls180.v:214.6-214.33"
+ attribute \src "ls180.v:210.6-210.33"
wire \main_libresocsim_ram_bus_we
- attribute \src "ls180.v:225.5-225.31"
+ attribute \src "ls180.v:221.5-221.31"
wire \main_libresocsim_reload_re
- attribute \src "ls180.v:224.12-224.43"
+ attribute \src "ls180.v:220.12-220.43"
wire width 32 \main_libresocsim_reload_storage
attribute \src "ls180.v:61.6-61.28"
wire \main_libresocsim_reset
wire \main_libresocsim_scratch_re
attribute \src "ls180.v:57.12-57.44"
wire width 32 \main_libresocsim_scratch_storage
- attribute \src "ls180.v:229.5-229.37"
+ attribute \src "ls180.v:225.5-225.37"
wire \main_libresocsim_update_value_re
- attribute \src "ls180.v:228.5-228.42"
+ attribute \src "ls180.v:224.5-224.42"
wire \main_libresocsim_update_value_storage
- attribute \src "ls180.v:248.12-248.34"
+ attribute \src "ls180.v:244.12-244.34"
wire width 32 \main_libresocsim_value
- attribute \src "ls180.v:230.12-230.41"
+ attribute \src "ls180.v:226.12-226.41"
wire width 32 \main_libresocsim_value_status
- attribute \src "ls180.v:231.6-231.31"
+ attribute \src "ls180.v:227.6-227.31"
wire \main_libresocsim_value_we
- attribute \src "ls180.v:220.11-220.30"
+ attribute \src "ls180.v:216.11-216.30"
wire width 4 \main_libresocsim_we
- attribute \src "ls180.v:236.5-236.32"
+ attribute \src "ls180.v:232.5-232.32"
wire \main_libresocsim_zero_clear
- attribute \src "ls180.v:237.5-237.38"
+ attribute \src "ls180.v:233.5-233.38"
wire \main_libresocsim_zero_old_trigger
- attribute \src "ls180.v:234.5-234.34"
+ attribute \src "ls180.v:230.5-230.34"
wire \main_libresocsim_zero_pending
- attribute \src "ls180.v:233.6-233.34"
+ attribute \src "ls180.v:229.6-229.34"
wire \main_libresocsim_zero_status
- attribute \src "ls180.v:235.6-235.35"
+ attribute \src "ls180.v:231.6-231.35"
wire \main_libresocsim_zero_trigger
- attribute \src "ls180.v:830.6-830.26"
+ attribute \src "ls180.v:826.6-826.26"
wire \main_litedram_wb_ack
- attribute \src "ls180.v:824.12-824.32"
+ attribute \src "ls180.v:820.12-820.32"
wire width 30 \main_litedram_wb_adr
- attribute \src "ls180.v:828.5-828.25"
+ attribute \src "ls180.v:824.5-824.25"
wire \main_litedram_wb_cyc
- attribute \src "ls180.v:826.13-826.35"
+ attribute \src "ls180.v:822.13-822.35"
wire width 16 \main_litedram_wb_dat_r
- attribute \src "ls180.v:825.12-825.34"
+ attribute \src "ls180.v:821.12-821.34"
wire width 16 \main_litedram_wb_dat_w
- attribute \src "ls180.v:827.11-827.31"
+ attribute \src "ls180.v:823.11-823.31"
wire width 2 \main_litedram_wb_sel
- attribute \src "ls180.v:829.5-829.25"
+ attribute \src "ls180.v:825.5-825.25"
wire \main_litedram_wb_stb
- attribute \src "ls180.v:831.5-831.24"
+ attribute \src "ls180.v:827.5-827.24"
wire \main_litedram_wb_we
- attribute \src "ls180.v:1066.13-1066.20"
+ attribute \src "ls180.v:1062.13-1062.20"
wire width 24 \main_nc
- attribute \src "ls180.v:803.6-803.24"
+ attribute \src "ls180.v:799.6-799.24"
wire \main_port_cmd_last
- attribute \src "ls180.v:805.13-805.39"
+ attribute \src "ls180.v:801.13-801.39"
wire width 24 \main_port_cmd_payload_addr
- attribute \src "ls180.v:804.6-804.30"
+ attribute \src "ls180.v:800.6-800.30"
wire \main_port_cmd_payload_we
- attribute \src "ls180.v:802.6-802.25"
+ attribute \src "ls180.v:798.6-798.25"
wire \main_port_cmd_ready
- attribute \src "ls180.v:801.6-801.25"
+ attribute \src "ls180.v:797.6-797.25"
wire \main_port_cmd_valid
- attribute \src "ls180.v:800.6-800.21"
+ attribute \src "ls180.v:796.6-796.21"
wire \main_port_flush
- attribute \src "ls180.v:812.13-812.41"
+ attribute \src "ls180.v:808.13-808.41"
wire width 16 \main_port_rdata_payload_data
- attribute \src "ls180.v:811.6-811.27"
+ attribute \src "ls180.v:807.6-807.27"
wire \main_port_rdata_ready
- attribute \src "ls180.v:810.6-810.27"
+ attribute \src "ls180.v:806.6-806.27"
wire \main_port_rdata_valid
- attribute \src "ls180.v:808.13-808.41"
+ attribute \src "ls180.v:804.13-804.41"
wire width 16 \main_port_wdata_payload_data
- attribute \src "ls180.v:809.12-809.38"
+ attribute \src "ls180.v:805.12-805.38"
wire width 2 \main_port_wdata_payload_we
- attribute \src "ls180.v:807.6-807.27"
+ attribute \src "ls180.v:803.6-803.27"
wire \main_port_wdata_ready
- attribute \src "ls180.v:806.6-806.27"
+ attribute \src "ls180.v:802.6-802.27"
wire \main_port_wdata_valid
- attribute \src "ls180.v:1071.12-1071.29"
+ attribute \src "ls180.v:1067.12-1067.29"
wire width 32 \main_pwm0_counter
- attribute \src "ls180.v:1068.6-1068.22"
+ attribute \src "ls180.v:1064.6-1064.22"
wire \main_pwm0_enable
- attribute \src "ls180.v:1073.5-1073.24"
+ attribute \src "ls180.v:1069.5-1069.24"
wire \main_pwm0_enable_re
- attribute \src "ls180.v:1072.5-1072.29"
+ attribute \src "ls180.v:1068.5-1068.29"
wire \main_pwm0_enable_storage
- attribute \src "ls180.v:1070.13-1070.29"
+ attribute \src "ls180.v:1066.13-1066.29"
wire width 32 \main_pwm0_period
- attribute \src "ls180.v:1077.5-1077.24"
+ attribute \src "ls180.v:1073.5-1073.24"
wire \main_pwm0_period_re
- attribute \src "ls180.v:1076.12-1076.36"
+ attribute \src "ls180.v:1072.12-1072.36"
wire width 32 \main_pwm0_period_storage
- attribute \src "ls180.v:1069.13-1069.28"
+ attribute \src "ls180.v:1065.13-1065.28"
wire width 32 \main_pwm0_width
- attribute \src "ls180.v:1075.5-1075.23"
+ attribute \src "ls180.v:1071.5-1071.23"
wire \main_pwm0_width_re
- attribute \src "ls180.v:1074.12-1074.35"
+ attribute \src "ls180.v:1070.12-1070.35"
wire width 32 \main_pwm0_width_storage
- attribute \src "ls180.v:1081.12-1081.29"
+ attribute \src "ls180.v:1077.12-1077.29"
wire width 32 \main_pwm1_counter
- attribute \src "ls180.v:1078.6-1078.22"
+ attribute \src "ls180.v:1074.6-1074.22"
wire \main_pwm1_enable
- attribute \src "ls180.v:1083.5-1083.24"
+ attribute \src "ls180.v:1079.5-1079.24"
wire \main_pwm1_enable_re
- attribute \src "ls180.v:1082.5-1082.29"
+ attribute \src "ls180.v:1078.5-1078.29"
wire \main_pwm1_enable_storage
- attribute \src "ls180.v:1080.13-1080.29"
+ attribute \src "ls180.v:1076.13-1076.29"
wire width 32 \main_pwm1_period
- attribute \src "ls180.v:1087.5-1087.24"
+ attribute \src "ls180.v:1083.5-1083.24"
wire \main_pwm1_period_re
- attribute \src "ls180.v:1086.12-1086.36"
+ attribute \src "ls180.v:1082.12-1082.36"
wire width 32 \main_pwm1_period_storage
- attribute \src "ls180.v:1079.13-1079.28"
+ attribute \src "ls180.v:1075.13-1075.28"
wire width 32 \main_pwm1_width
- attribute \src "ls180.v:1085.5-1085.23"
+ attribute \src "ls180.v:1081.5-1081.23"
wire \main_pwm1_width_re
- attribute \src "ls180.v:1084.12-1084.35"
+ attribute \src "ls180.v:1080.12-1080.35"
wire width 32 \main_pwm1_width_storage
- attribute \src "ls180.v:269.11-269.25"
+ attribute \src "ls180.v:265.11-265.25"
wire width 3 \main_rddata_en
- attribute \src "ls180.v:1609.11-1609.43"
+ attribute \src "ls180.v:1605.11-1605.43"
wire width 2 \main_sdblock2mem_converter_demux
- attribute \src "ls180.v:1610.6-1610.42"
+ attribute \src "ls180.v:1606.6-1606.42"
wire \main_sdblock2mem_converter_load_part
- attribute \src "ls180.v:1600.6-1600.43"
+ attribute \src "ls180.v:1596.6-1596.43"
wire \main_sdblock2mem_converter_sink_first
- attribute \src "ls180.v:1601.6-1601.42"
+ attribute \src "ls180.v:1597.6-1597.42"
wire \main_sdblock2mem_converter_sink_last
- attribute \src "ls180.v:1602.12-1602.56"
+ attribute \src "ls180.v:1598.12-1598.56"
wire width 8 \main_sdblock2mem_converter_sink_payload_data
- attribute \src "ls180.v:1599.6-1599.43"
+ attribute \src "ls180.v:1595.6-1595.43"
wire \main_sdblock2mem_converter_sink_ready
- attribute \src "ls180.v:1598.6-1598.43"
+ attribute \src "ls180.v:1594.6-1594.43"
wire \main_sdblock2mem_converter_sink_valid
- attribute \src "ls180.v:1605.5-1605.44"
+ attribute \src "ls180.v:1601.5-1601.44"
wire \main_sdblock2mem_converter_source_first
- attribute \src "ls180.v:1606.5-1606.43"
+ attribute \src "ls180.v:1602.5-1602.43"
wire \main_sdblock2mem_converter_source_last
- attribute \src "ls180.v:1607.12-1607.58"
+ attribute \src "ls180.v:1603.12-1603.58"
wire width 32 \main_sdblock2mem_converter_source_payload_data
- attribute \src "ls180.v:1608.11-1608.70"
+ attribute \src "ls180.v:1604.11-1604.70"
wire width 3 \main_sdblock2mem_converter_source_payload_valid_token_count
- attribute \src "ls180.v:1604.6-1604.45"
+ attribute \src "ls180.v:1600.6-1600.45"
wire \main_sdblock2mem_converter_source_ready
- attribute \src "ls180.v:1603.6-1603.45"
+ attribute \src "ls180.v:1599.6-1599.45"
wire \main_sdblock2mem_converter_source_valid
- attribute \src "ls180.v:1611.5-1611.42"
+ attribute \src "ls180.v:1607.5-1607.42"
wire \main_sdblock2mem_converter_strobe_all
- attribute \src "ls180.v:1584.11-1584.40"
+ attribute \src "ls180.v:1580.11-1580.40"
wire width 5 \main_sdblock2mem_fifo_consume
- attribute \src "ls180.v:1589.6-1589.35"
+ attribute \src "ls180.v:1585.6-1585.35"
wire \main_sdblock2mem_fifo_do_read
- attribute \src "ls180.v:1593.6-1593.41"
+ attribute \src "ls180.v:1589.6-1589.41"
wire \main_sdblock2mem_fifo_fifo_in_first
- attribute \src "ls180.v:1594.6-1594.40"
+ attribute \src "ls180.v:1590.6-1590.40"
wire \main_sdblock2mem_fifo_fifo_in_last
- attribute \src "ls180.v:1592.12-1592.54"
+ attribute \src "ls180.v:1588.12-1588.54"
wire width 8 \main_sdblock2mem_fifo_fifo_in_payload_data
- attribute \src "ls180.v:1596.6-1596.42"
+ attribute \src "ls180.v:1592.6-1592.42"
wire \main_sdblock2mem_fifo_fifo_out_first
- attribute \src "ls180.v:1597.6-1597.41"
+ attribute \src "ls180.v:1593.6-1593.41"
wire \main_sdblock2mem_fifo_fifo_out_last
- attribute \src "ls180.v:1595.12-1595.55"
+ attribute \src "ls180.v:1591.12-1591.55"
wire width 8 \main_sdblock2mem_fifo_fifo_out_payload_data
- attribute \src "ls180.v:1581.11-1581.38"
+ attribute \src "ls180.v:1577.11-1577.38"
wire width 6 \main_sdblock2mem_fifo_level
- attribute \src "ls180.v:1583.11-1583.40"
+ attribute \src "ls180.v:1579.11-1579.40"
wire width 5 \main_sdblock2mem_fifo_produce
- attribute \src "ls180.v:1590.12-1590.44"
+ attribute \src "ls180.v:1586.12-1586.44"
wire width 5 \main_sdblock2mem_fifo_rdport_adr
- attribute \src "ls180.v:1591.12-1591.46"
+ attribute \src "ls180.v:1587.12-1587.46"
wire width 10 \main_sdblock2mem_fifo_rdport_dat_r
- attribute \src "ls180.v:1582.5-1582.34"
+ attribute \src "ls180.v:1578.5-1578.34"
wire \main_sdblock2mem_fifo_replace
- attribute \src "ls180.v:1567.6-1567.38"
+ attribute \src "ls180.v:1563.6-1563.38"
wire \main_sdblock2mem_fifo_sink_first
- attribute \src "ls180.v:1568.6-1568.37"
+ attribute \src "ls180.v:1564.6-1564.37"
wire \main_sdblock2mem_fifo_sink_last
- attribute \src "ls180.v:1569.12-1569.51"
+ attribute \src "ls180.v:1565.12-1565.51"
wire width 8 \main_sdblock2mem_fifo_sink_payload_data
- attribute \src "ls180.v:1566.6-1566.38"
+ attribute \src "ls180.v:1562.6-1562.38"
wire \main_sdblock2mem_fifo_sink_ready
- attribute \src "ls180.v:1565.6-1565.38"
+ attribute \src "ls180.v:1561.6-1561.38"
wire \main_sdblock2mem_fifo_sink_valid
- attribute \src "ls180.v:1572.6-1572.40"
+ attribute \src "ls180.v:1568.6-1568.40"
wire \main_sdblock2mem_fifo_source_first
- attribute \src "ls180.v:1573.6-1573.39"
+ attribute \src "ls180.v:1569.6-1569.39"
wire \main_sdblock2mem_fifo_source_last
- attribute \src "ls180.v:1574.12-1574.53"
+ attribute \src "ls180.v:1570.12-1570.53"
wire width 8 \main_sdblock2mem_fifo_source_payload_data
- attribute \src "ls180.v:1571.6-1571.40"
+ attribute \src "ls180.v:1567.6-1567.40"
wire \main_sdblock2mem_fifo_source_ready
- attribute \src "ls180.v:1570.6-1570.40"
+ attribute \src "ls180.v:1566.6-1566.40"
wire \main_sdblock2mem_fifo_source_valid
- attribute \src "ls180.v:1579.12-1579.46"
+ attribute \src "ls180.v:1575.12-1575.46"
wire width 10 \main_sdblock2mem_fifo_syncfifo_din
- attribute \src "ls180.v:1580.12-1580.47"
+ attribute \src "ls180.v:1576.12-1576.47"
wire width 10 \main_sdblock2mem_fifo_syncfifo_dout
- attribute \src "ls180.v:1577.6-1577.39"
+ attribute \src "ls180.v:1573.6-1573.39"
wire \main_sdblock2mem_fifo_syncfifo_re
- attribute \src "ls180.v:1578.6-1578.45"
+ attribute \src "ls180.v:1574.6-1574.45"
wire \main_sdblock2mem_fifo_syncfifo_readable
- attribute \src "ls180.v:1575.6-1575.39"
+ attribute \src "ls180.v:1571.6-1571.39"
wire \main_sdblock2mem_fifo_syncfifo_we
- attribute \src "ls180.v:1576.6-1576.45"
+ attribute \src "ls180.v:1572.6-1572.45"
wire \main_sdblock2mem_fifo_syncfifo_writable
- attribute \src "ls180.v:1585.11-1585.43"
+ attribute \src "ls180.v:1581.11-1581.43"
wire width 5 \main_sdblock2mem_fifo_wrport_adr
- attribute \src "ls180.v:1586.12-1586.46"
+ attribute \src "ls180.v:1582.12-1582.46"
wire width 10 \main_sdblock2mem_fifo_wrport_dat_r
- attribute \src "ls180.v:1588.12-1588.46"
+ attribute \src "ls180.v:1584.12-1584.46"
wire width 10 \main_sdblock2mem_fifo_wrport_dat_w
- attribute \src "ls180.v:1587.6-1587.37"
+ attribute \src "ls180.v:1583.6-1583.37"
wire \main_sdblock2mem_fifo_wrport_we
- attribute \src "ls180.v:1562.6-1562.38"
+ attribute \src "ls180.v:1558.6-1558.38"
wire \main_sdblock2mem_sink_sink_first
- attribute \src "ls180.v:1563.6-1563.37"
+ attribute \src "ls180.v:1559.6-1559.37"
wire \main_sdblock2mem_sink_sink_last
- attribute \src "ls180.v:1619.12-1619.54"
+ attribute \src "ls180.v:1615.12-1615.54"
wire width 32 \main_sdblock2mem_sink_sink_payload_address
- attribute \src "ls180.v:1564.12-1564.52"
+ attribute \src "ls180.v:1560.12-1560.52"
wire width 8 \main_sdblock2mem_sink_sink_payload_data0
- attribute \src "ls180.v:1620.12-1620.52"
+ attribute \src "ls180.v:1616.12-1616.52"
wire width 32 \main_sdblock2mem_sink_sink_payload_data1
- attribute \src "ls180.v:1561.6-1561.39"
+ attribute \src "ls180.v:1557.6-1557.39"
wire \main_sdblock2mem_sink_sink_ready0
- attribute \src "ls180.v:1618.6-1618.39"
+ attribute \src "ls180.v:1614.6-1614.39"
wire \main_sdblock2mem_sink_sink_ready1
- attribute \src "ls180.v:1560.6-1560.39"
+ attribute \src "ls180.v:1556.6-1556.39"
wire \main_sdblock2mem_sink_sink_valid0
- attribute \src "ls180.v:1617.5-1617.38"
+ attribute \src "ls180.v:1613.5-1613.38"
wire \main_sdblock2mem_sink_sink_valid1
- attribute \src "ls180.v:1614.6-1614.42"
+ attribute \src "ls180.v:1610.6-1610.42"
wire \main_sdblock2mem_source_source_first
- attribute \src "ls180.v:1615.6-1615.41"
+ attribute \src "ls180.v:1611.6-1611.41"
wire \main_sdblock2mem_source_source_last
- attribute \src "ls180.v:1616.13-1616.56"
+ attribute \src "ls180.v:1612.13-1612.56"
wire width 32 \main_sdblock2mem_source_source_payload_data
- attribute \src "ls180.v:1613.6-1613.42"
+ attribute \src "ls180.v:1609.6-1609.42"
wire \main_sdblock2mem_source_source_ready
- attribute \src "ls180.v:1612.6-1612.42"
+ attribute \src "ls180.v:1608.6-1608.42"
wire \main_sdblock2mem_source_source_valid
- attribute \src "ls180.v:1636.13-1636.52"
+ attribute \src "ls180.v:1632.13-1632.52"
wire width 32 \main_sdblock2mem_wishbonedmawriter_base
- attribute \src "ls180.v:1627.5-1627.47"
+ attribute \src "ls180.v:1623.5-1623.47"
wire \main_sdblock2mem_wishbonedmawriter_base_re
- attribute \src "ls180.v:1626.12-1626.59"
+ attribute \src "ls180.v:1622.12-1622.59"
wire width 64 \main_sdblock2mem_wishbonedmawriter_base_storage
- attribute \src "ls180.v:1631.5-1631.49"
+ attribute \src "ls180.v:1627.5-1627.49"
wire \main_sdblock2mem_wishbonedmawriter_enable_re
- attribute \src "ls180.v:1630.5-1630.54"
+ attribute \src "ls180.v:1626.5-1626.54"
wire \main_sdblock2mem_wishbonedmawriter_enable_storage
- attribute \src "ls180.v:1638.13-1638.54"
+ attribute \src "ls180.v:1634.13-1634.54"
wire width 32 \main_sdblock2mem_wishbonedmawriter_length
- attribute \src "ls180.v:1629.5-1629.49"
+ attribute \src "ls180.v:1625.5-1625.49"
wire \main_sdblock2mem_wishbonedmawriter_length_re
- attribute \src "ls180.v:1628.12-1628.61"
+ attribute \src "ls180.v:1624.12-1624.61"
wire width 32 \main_sdblock2mem_wishbonedmawriter_length_storage
- attribute \src "ls180.v:1635.5-1635.47"
+ attribute \src "ls180.v:1631.5-1631.47"
wire \main_sdblock2mem_wishbonedmawriter_loop_re
- attribute \src "ls180.v:1634.5-1634.52"
+ attribute \src "ls180.v:1630.5-1630.52"
wire \main_sdblock2mem_wishbonedmawriter_loop_storage
- attribute \src "ls180.v:1637.12-1637.53"
+ attribute \src "ls180.v:1633.12-1633.53"
wire width 32 \main_sdblock2mem_wishbonedmawriter_offset
- attribute \src "ls180.v:1857.12-1857.79"
+ attribute \src "ls180.v:1853.12-1853.79"
wire width 32 \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value
- attribute \src "ls180.v:1858.5-1858.75"
+ attribute \src "ls180.v:1854.5-1854.75"
wire \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce
- attribute \src "ls180.v:1639.6-1639.46"
+ attribute \src "ls180.v:1635.6-1635.46"
wire \main_sdblock2mem_wishbonedmawriter_reset
- attribute \src "ls180.v:1623.6-1623.51"
+ attribute \src "ls180.v:1619.6-1619.51"
wire \main_sdblock2mem_wishbonedmawriter_sink_first
- attribute \src "ls180.v:1624.6-1624.50"
+ attribute \src "ls180.v:1620.6-1620.50"
wire \main_sdblock2mem_wishbonedmawriter_sink_last
- attribute \src "ls180.v:1625.13-1625.65"
+ attribute \src "ls180.v:1621.13-1621.65"
wire width 32 \main_sdblock2mem_wishbonedmawriter_sink_payload_data
- attribute \src "ls180.v:1622.5-1622.50"
+ attribute \src "ls180.v:1618.5-1618.50"
wire \main_sdblock2mem_wishbonedmawriter_sink_ready
- attribute \src "ls180.v:1621.6-1621.51"
+ attribute \src "ls180.v:1617.6-1617.51"
wire \main_sdblock2mem_wishbonedmawriter_sink_valid
- attribute \src "ls180.v:1632.5-1632.46"
+ attribute \src "ls180.v:1628.5-1628.46"
wire \main_sdblock2mem_wishbonedmawriter_status
- attribute \src "ls180.v:1633.6-1633.43"
+ attribute \src "ls180.v:1629.6-1629.43"
wire \main_sdblock2mem_wishbonedmawriter_we
- attribute \src "ls180.v:1401.5-1401.31"
+ attribute \src "ls180.v:1397.5-1397.31"
wire \main_sdcore_block_count_re
- attribute \src "ls180.v:1400.12-1400.43"
+ attribute \src "ls180.v:1396.12-1396.43"
wire width 32 \main_sdcore_block_count_storage
- attribute \src "ls180.v:1399.5-1399.32"
+ attribute \src "ls180.v:1395.5-1395.32"
wire \main_sdcore_block_length_re
- attribute \src "ls180.v:1398.11-1398.43"
+ attribute \src "ls180.v:1394.11-1394.43"
wire width 10 \main_sdcore_block_length_storage
- attribute \src "ls180.v:1385.5-1385.32"
+ attribute \src "ls180.v:1381.5-1381.32"
wire \main_sdcore_cmd_argument_re
- attribute \src "ls180.v:1384.12-1384.44"
+ attribute \src "ls180.v:1380.12-1380.44"
wire width 32 \main_sdcore_cmd_argument_storage
- attribute \src "ls180.v:1387.5-1387.31"
+ attribute \src "ls180.v:1383.5-1383.31"
wire \main_sdcore_cmd_command_re
- attribute \src "ls180.v:1386.12-1386.43"
+ attribute \src "ls180.v:1382.12-1382.43"
wire width 32 \main_sdcore_cmd_command_storage
- attribute \src "ls180.v:1540.11-1540.32"
+ attribute \src "ls180.v:1536.11-1536.32"
wire width 3 \main_sdcore_cmd_count
- attribute \src "ls180.v:1841.11-1841.55"
+ attribute \src "ls180.v:1837.11-1837.55"
wire width 3 \main_sdcore_cmd_count_sdcore_fsm_next_value2
- attribute \src "ls180.v:1842.5-1842.52"
+ attribute \src "ls180.v:1838.5-1838.52"
wire \main_sdcore_cmd_count_sdcore_fsm_next_value_ce2
- attribute \src "ls180.v:1541.5-1541.25"
+ attribute \src "ls180.v:1537.5-1537.25"
wire \main_sdcore_cmd_done
- attribute \src "ls180.v:1837.5-1837.48"
+ attribute \src "ls180.v:1833.5-1833.48"
wire \main_sdcore_cmd_done_sdcore_fsm_next_value0
- attribute \src "ls180.v:1838.5-1838.51"
+ attribute \src "ls180.v:1834.5-1834.51"
wire \main_sdcore_cmd_done_sdcore_fsm_next_value_ce0
- attribute \src "ls180.v:1542.5-1542.26"
+ attribute \src "ls180.v:1538.5-1538.26"
wire \main_sdcore_cmd_error
- attribute \src "ls180.v:1845.5-1845.49"
+ attribute \src "ls180.v:1841.5-1841.49"
wire \main_sdcore_cmd_error_sdcore_fsm_next_value4
- attribute \src "ls180.v:1846.5-1846.52"
+ attribute \src "ls180.v:1842.5-1842.52"
wire \main_sdcore_cmd_error_sdcore_fsm_next_value_ce4
- attribute \src "ls180.v:1394.12-1394.40"
+ attribute \src "ls180.v:1390.12-1390.40"
wire width 4 \main_sdcore_cmd_event_status
- attribute \src "ls180.v:1395.6-1395.30"
+ attribute \src "ls180.v:1391.6-1391.30"
wire \main_sdcore_cmd_event_we
- attribute \src "ls180.v:1392.13-1392.44"
+ attribute \src "ls180.v:1388.13-1388.44"
wire width 128 \main_sdcore_cmd_response_status
- attribute \src "ls180.v:1853.13-1853.67"
+ attribute \src "ls180.v:1849.13-1849.67"
wire width 128 \main_sdcore_cmd_response_status_sdcore_fsm_next_value8
- attribute \src "ls180.v:1854.5-1854.62"
+ attribute \src "ls180.v:1850.5-1850.62"
wire \main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8
- attribute \src "ls180.v:1393.6-1393.33"
+ attribute \src "ls180.v:1389.6-1389.33"
wire \main_sdcore_cmd_response_we
- attribute \src "ls180.v:1389.6-1389.28"
+ attribute \src "ls180.v:1385.6-1385.28"
wire \main_sdcore_cmd_send_r
- attribute \src "ls180.v:1388.6-1388.29"
+ attribute \src "ls180.v:1384.6-1384.29"
wire \main_sdcore_cmd_send_re
- attribute \src "ls180.v:1391.5-1391.27"
+ attribute \src "ls180.v:1387.5-1387.27"
wire \main_sdcore_cmd_send_w
- attribute \src "ls180.v:1390.6-1390.29"
+ attribute \src "ls180.v:1386.6-1386.29"
wire \main_sdcore_cmd_send_we
- attribute \src "ls180.v:1543.5-1543.28"
+ attribute \src "ls180.v:1539.5-1539.28"
wire \main_sdcore_cmd_timeout
- attribute \src "ls180.v:1847.5-1847.51"
+ attribute \src "ls180.v:1843.5-1843.51"
wire \main_sdcore_cmd_timeout_sdcore_fsm_next_value5
- attribute \src "ls180.v:1848.5-1848.54"
+ attribute \src "ls180.v:1844.5-1844.54"
wire \main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5
- attribute \src "ls180.v:1539.12-1539.32"
+ attribute \src "ls180.v:1535.12-1535.32"
wire width 2 \main_sdcore_cmd_type
- attribute \src "ls180.v:1501.11-1501.40"
+ attribute \src "ls180.v:1497.11-1497.40"
wire width 4 \main_sdcore_crc16_checker_cnt
- attribute \src "ls180.v:1507.5-1507.39"
+ attribute \src "ls180.v:1503.5-1503.39"
wire \main_sdcore_crc16_checker_crc0_clr
- attribute \src "ls180.v:1506.12-1506.46"
+ attribute \src "ls180.v:1502.12-1502.46"
wire width 16 \main_sdcore_crc16_checker_crc0_crc
- attribute \src "ls180.v:1502.12-1502.50"
+ attribute \src "ls180.v:1498.12-1498.50"
wire width 16 \main_sdcore_crc16_checker_crc0_crcreg0
- attribute \src "ls180.v:1503.13-1503.51"
+ attribute \src "ls180.v:1499.13-1499.51"
wire width 16 \main_sdcore_crc16_checker_crc0_crcreg1
- attribute \src "ls180.v:1504.13-1504.51"
+ attribute \src "ls180.v:1500.13-1500.51"
wire width 16 \main_sdcore_crc16_checker_crc0_crcreg2
- attribute \src "ls180.v:1508.6-1508.43"
+ attribute \src "ls180.v:1504.6-1504.43"
wire \main_sdcore_crc16_checker_crc0_enable
- attribute \src "ls180.v:1505.12-1505.46"
+ attribute \src "ls180.v:1501.12-1501.46"
wire width 2 \main_sdcore_crc16_checker_crc0_val
- attribute \src "ls180.v:1514.5-1514.39"
+ attribute \src "ls180.v:1510.5-1510.39"
wire \main_sdcore_crc16_checker_crc1_clr
- attribute \src "ls180.v:1513.12-1513.46"
+ attribute \src "ls180.v:1509.12-1509.46"
wire width 16 \main_sdcore_crc16_checker_crc1_crc
- attribute \src "ls180.v:1509.12-1509.50"
+ attribute \src "ls180.v:1505.12-1505.50"
wire width 16 \main_sdcore_crc16_checker_crc1_crcreg0
- attribute \src "ls180.v:1510.13-1510.51"
+ attribute \src "ls180.v:1506.13-1506.51"
wire width 16 \main_sdcore_crc16_checker_crc1_crcreg1
- attribute \src "ls180.v:1511.13-1511.51"
+ attribute \src "ls180.v:1507.13-1507.51"
wire width 16 \main_sdcore_crc16_checker_crc1_crcreg2
- attribute \src "ls180.v:1515.6-1515.43"
+ attribute \src "ls180.v:1511.6-1511.43"
wire \main_sdcore_crc16_checker_crc1_enable
- attribute \src "ls180.v:1512.12-1512.46"
+ attribute \src "ls180.v:1508.12-1508.46"
wire width 2 \main_sdcore_crc16_checker_crc1_val
- attribute \src "ls180.v:1521.5-1521.39"
+ attribute \src "ls180.v:1517.5-1517.39"
wire \main_sdcore_crc16_checker_crc2_clr
- attribute \src "ls180.v:1520.12-1520.46"
+ attribute \src "ls180.v:1516.12-1516.46"
wire width 16 \main_sdcore_crc16_checker_crc2_crc
- attribute \src "ls180.v:1516.12-1516.50"
+ attribute \src "ls180.v:1512.12-1512.50"
wire width 16 \main_sdcore_crc16_checker_crc2_crcreg0
- attribute \src "ls180.v:1517.13-1517.51"
+ attribute \src "ls180.v:1513.13-1513.51"
wire width 16 \main_sdcore_crc16_checker_crc2_crcreg1
- attribute \src "ls180.v:1518.13-1518.51"
+ attribute \src "ls180.v:1514.13-1514.51"
wire width 16 \main_sdcore_crc16_checker_crc2_crcreg2
- attribute \src "ls180.v:1522.6-1522.43"
+ attribute \src "ls180.v:1518.6-1518.43"
wire \main_sdcore_crc16_checker_crc2_enable
- attribute \src "ls180.v:1519.12-1519.46"
+ attribute \src "ls180.v:1515.12-1515.46"
wire width 2 \main_sdcore_crc16_checker_crc2_val
- attribute \src "ls180.v:1528.5-1528.39"
+ attribute \src "ls180.v:1524.5-1524.39"
wire \main_sdcore_crc16_checker_crc3_clr
- attribute \src "ls180.v:1527.12-1527.46"
+ attribute \src "ls180.v:1523.12-1523.46"
wire width 16 \main_sdcore_crc16_checker_crc3_crc
- attribute \src "ls180.v:1523.12-1523.50"
+ attribute \src "ls180.v:1519.12-1519.50"
wire width 16 \main_sdcore_crc16_checker_crc3_crcreg0
- attribute \src "ls180.v:1524.13-1524.51"
+ attribute \src "ls180.v:1520.13-1520.51"
wire width 16 \main_sdcore_crc16_checker_crc3_crcreg1
- attribute \src "ls180.v:1525.13-1525.51"
+ attribute \src "ls180.v:1521.13-1521.51"
wire width 16 \main_sdcore_crc16_checker_crc3_crcreg2
- attribute \src "ls180.v:1529.6-1529.43"
+ attribute \src "ls180.v:1525.6-1525.43"
wire \main_sdcore_crc16_checker_crc3_enable
- attribute \src "ls180.v:1526.12-1526.46"
+ attribute \src "ls180.v:1522.12-1522.46"
wire width 2 \main_sdcore_crc16_checker_crc3_val
- attribute \src "ls180.v:1530.12-1530.45"
+ attribute \src "ls180.v:1526.12-1526.45"
wire width 16 \main_sdcore_crc16_checker_crctmp0
- attribute \src "ls180.v:1531.12-1531.45"
+ attribute \src "ls180.v:1527.12-1527.45"
wire width 16 \main_sdcore_crc16_checker_crctmp1
- attribute \src "ls180.v:1532.12-1532.45"
+ attribute \src "ls180.v:1528.12-1528.45"
wire width 16 \main_sdcore_crc16_checker_crctmp2
- attribute \src "ls180.v:1533.12-1533.45"
+ attribute \src "ls180.v:1529.12-1529.45"
wire width 16 \main_sdcore_crc16_checker_crctmp3
- attribute \src "ls180.v:1535.12-1535.43"
+ attribute \src "ls180.v:1531.12-1531.43"
wire width 16 \main_sdcore_crc16_checker_fifo0
- attribute \src "ls180.v:1536.12-1536.43"
+ attribute \src "ls180.v:1532.12-1532.43"
wire width 16 \main_sdcore_crc16_checker_fifo1
- attribute \src "ls180.v:1537.12-1537.43"
+ attribute \src "ls180.v:1533.12-1533.43"
wire width 16 \main_sdcore_crc16_checker_fifo2
- attribute \src "ls180.v:1538.12-1538.43"
+ attribute \src "ls180.v:1534.12-1534.43"
wire width 16 \main_sdcore_crc16_checker_fifo3
- attribute \src "ls180.v:1492.5-1492.41"
+ attribute \src "ls180.v:1488.5-1488.41"
wire \main_sdcore_crc16_checker_sink_first
- attribute \src "ls180.v:1493.5-1493.40"
+ attribute \src "ls180.v:1489.5-1489.40"
wire \main_sdcore_crc16_checker_sink_last
- attribute \src "ls180.v:1494.11-1494.54"
+ attribute \src "ls180.v:1490.11-1490.54"
wire width 8 \main_sdcore_crc16_checker_sink_payload_data
- attribute \src "ls180.v:1491.5-1491.41"
+ attribute \src "ls180.v:1487.5-1487.41"
wire \main_sdcore_crc16_checker_sink_ready
- attribute \src "ls180.v:1490.5-1490.41"
+ attribute \src "ls180.v:1486.5-1486.41"
wire \main_sdcore_crc16_checker_sink_valid
- attribute \src "ls180.v:1497.5-1497.43"
+ attribute \src "ls180.v:1493.5-1493.43"
wire \main_sdcore_crc16_checker_source_first
- attribute \src "ls180.v:1498.6-1498.43"
+ attribute \src "ls180.v:1494.6-1494.43"
wire \main_sdcore_crc16_checker_source_last
- attribute \src "ls180.v:1499.12-1499.57"
+ attribute \src "ls180.v:1495.12-1495.57"
wire width 8 \main_sdcore_crc16_checker_source_payload_data
- attribute \src "ls180.v:1496.6-1496.44"
+ attribute \src "ls180.v:1492.6-1492.44"
wire \main_sdcore_crc16_checker_source_ready
- attribute \src "ls180.v:1495.5-1495.43"
+ attribute \src "ls180.v:1491.5-1491.43"
wire \main_sdcore_crc16_checker_source_valid
- attribute \src "ls180.v:1500.11-1500.40"
+ attribute \src "ls180.v:1496.11-1496.40"
wire width 8 \main_sdcore_crc16_checker_val
- attribute \src "ls180.v:1534.5-1534.36"
+ attribute \src "ls180.v:1530.5-1530.36"
wire \main_sdcore_crc16_checker_valid
- attribute \src "ls180.v:1457.11-1457.41"
+ attribute \src "ls180.v:1453.11-1453.41"
wire width 3 \main_sdcore_crc16_inserter_cnt
- attribute \src "ls180.v:1833.11-1833.80"
+ attribute \src "ls180.v:1829.11-1829.80"
wire width 3 \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4
- attribute \src "ls180.v:1834.5-1834.77"
+ attribute \src "ls180.v:1830.5-1830.77"
wire \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4
- attribute \src "ls180.v:1463.6-1463.41"
+ attribute \src "ls180.v:1459.6-1459.41"
wire \main_sdcore_crc16_inserter_crc0_clr
- attribute \src "ls180.v:1462.12-1462.47"
+ attribute \src "ls180.v:1458.12-1458.47"
wire width 16 \main_sdcore_crc16_inserter_crc0_crc
- attribute \src "ls180.v:1458.12-1458.51"
+ attribute \src "ls180.v:1454.12-1454.51"
wire width 16 \main_sdcore_crc16_inserter_crc0_crcreg0
- attribute \src "ls180.v:1459.13-1459.52"
+ attribute \src "ls180.v:1455.13-1455.52"
wire width 16 \main_sdcore_crc16_inserter_crc0_crcreg1
- attribute \src "ls180.v:1460.13-1460.52"
+ attribute \src "ls180.v:1456.13-1456.52"
wire width 16 \main_sdcore_crc16_inserter_crc0_crcreg2
- attribute \src "ls180.v:1464.6-1464.44"
+ attribute \src "ls180.v:1460.6-1460.44"
wire \main_sdcore_crc16_inserter_crc0_enable
- attribute \src "ls180.v:1461.12-1461.47"
+ attribute \src "ls180.v:1457.12-1457.47"
wire width 2 \main_sdcore_crc16_inserter_crc0_val
- attribute \src "ls180.v:1470.6-1470.41"
+ attribute \src "ls180.v:1466.6-1466.41"
wire \main_sdcore_crc16_inserter_crc1_clr
- attribute \src "ls180.v:1469.12-1469.47"
+ attribute \src "ls180.v:1465.12-1465.47"
wire width 16 \main_sdcore_crc16_inserter_crc1_crc
- attribute \src "ls180.v:1465.12-1465.51"
+ attribute \src "ls180.v:1461.12-1461.51"
wire width 16 \main_sdcore_crc16_inserter_crc1_crcreg0
- attribute \src "ls180.v:1466.13-1466.52"
+ attribute \src "ls180.v:1462.13-1462.52"
wire width 16 \main_sdcore_crc16_inserter_crc1_crcreg1
- attribute \src "ls180.v:1467.13-1467.52"
+ attribute \src "ls180.v:1463.13-1463.52"
wire width 16 \main_sdcore_crc16_inserter_crc1_crcreg2
- attribute \src "ls180.v:1471.6-1471.44"
+ attribute \src "ls180.v:1467.6-1467.44"
wire \main_sdcore_crc16_inserter_crc1_enable
- attribute \src "ls180.v:1468.12-1468.47"
+ attribute \src "ls180.v:1464.12-1464.47"
wire width 2 \main_sdcore_crc16_inserter_crc1_val
- attribute \src "ls180.v:1477.6-1477.41"
+ attribute \src "ls180.v:1473.6-1473.41"
wire \main_sdcore_crc16_inserter_crc2_clr
- attribute \src "ls180.v:1476.12-1476.47"
+ attribute \src "ls180.v:1472.12-1472.47"
wire width 16 \main_sdcore_crc16_inserter_crc2_crc
- attribute \src "ls180.v:1472.12-1472.51"
+ attribute \src "ls180.v:1468.12-1468.51"
wire width 16 \main_sdcore_crc16_inserter_crc2_crcreg0
- attribute \src "ls180.v:1473.13-1473.52"
+ attribute \src "ls180.v:1469.13-1469.52"
wire width 16 \main_sdcore_crc16_inserter_crc2_crcreg1
- attribute \src "ls180.v:1474.13-1474.52"
+ attribute \src "ls180.v:1470.13-1470.52"
wire width 16 \main_sdcore_crc16_inserter_crc2_crcreg2
- attribute \src "ls180.v:1478.6-1478.44"
+ attribute \src "ls180.v:1474.6-1474.44"
wire \main_sdcore_crc16_inserter_crc2_enable
- attribute \src "ls180.v:1475.12-1475.47"
+ attribute \src "ls180.v:1471.12-1471.47"
wire width 2 \main_sdcore_crc16_inserter_crc2_val
- attribute \src "ls180.v:1484.6-1484.41"
+ attribute \src "ls180.v:1480.6-1480.41"
wire \main_sdcore_crc16_inserter_crc3_clr
- attribute \src "ls180.v:1483.12-1483.47"
+ attribute \src "ls180.v:1479.12-1479.47"
wire width 16 \main_sdcore_crc16_inserter_crc3_crc
- attribute \src "ls180.v:1479.12-1479.51"
+ attribute \src "ls180.v:1475.12-1475.51"
wire width 16 \main_sdcore_crc16_inserter_crc3_crcreg0
- attribute \src "ls180.v:1480.13-1480.52"
+ attribute \src "ls180.v:1476.13-1476.52"
wire width 16 \main_sdcore_crc16_inserter_crc3_crcreg1
- attribute \src "ls180.v:1481.13-1481.52"
+ attribute \src "ls180.v:1477.13-1477.52"
wire width 16 \main_sdcore_crc16_inserter_crc3_crcreg2
- attribute \src "ls180.v:1485.6-1485.44"
+ attribute \src "ls180.v:1481.6-1481.44"
wire \main_sdcore_crc16_inserter_crc3_enable
- attribute \src "ls180.v:1482.12-1482.47"
+ attribute \src "ls180.v:1478.12-1478.47"
wire width 2 \main_sdcore_crc16_inserter_crc3_val
- attribute \src "ls180.v:1486.12-1486.46"
+ attribute \src "ls180.v:1482.12-1482.46"
wire width 16 \main_sdcore_crc16_inserter_crctmp0
- attribute \src "ls180.v:1825.12-1825.85"
+ attribute \src "ls180.v:1821.12-1821.85"
wire width 16 \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0
- attribute \src "ls180.v:1826.5-1826.81"
+ attribute \src "ls180.v:1822.5-1822.81"
wire \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0
- attribute \src "ls180.v:1487.12-1487.46"
+ attribute \src "ls180.v:1483.12-1483.46"
wire width 16 \main_sdcore_crc16_inserter_crctmp1
- attribute \src "ls180.v:1827.12-1827.85"
+ attribute \src "ls180.v:1823.12-1823.85"
wire width 16 \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1
- attribute \src "ls180.v:1828.5-1828.81"
+ attribute \src "ls180.v:1824.5-1824.81"
wire \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1
- attribute \src "ls180.v:1488.12-1488.46"
+ attribute \src "ls180.v:1484.12-1484.46"
wire width 16 \main_sdcore_crc16_inserter_crctmp2
- attribute \src "ls180.v:1829.12-1829.85"
+ attribute \src "ls180.v:1825.12-1825.85"
wire width 16 \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2
- attribute \src "ls180.v:1830.5-1830.81"
+ attribute \src "ls180.v:1826.5-1826.81"
wire \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2
- attribute \src "ls180.v:1489.12-1489.46"
+ attribute \src "ls180.v:1485.12-1485.46"
wire width 16 \main_sdcore_crc16_inserter_crctmp3
- attribute \src "ls180.v:1831.12-1831.85"
+ attribute \src "ls180.v:1827.12-1827.85"
wire width 16 \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3
- attribute \src "ls180.v:1832.5-1832.81"
+ attribute \src "ls180.v:1828.5-1828.81"
wire \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3
- attribute \src "ls180.v:1449.6-1449.43"
+ attribute \src "ls180.v:1445.6-1445.43"
wire \main_sdcore_crc16_inserter_sink_first
- attribute \src "ls180.v:1450.6-1450.42"
+ attribute \src "ls180.v:1446.6-1446.42"
wire \main_sdcore_crc16_inserter_sink_last
- attribute \src "ls180.v:1451.12-1451.56"
+ attribute \src "ls180.v:1447.12-1447.56"
wire width 8 \main_sdcore_crc16_inserter_sink_payload_data
- attribute \src "ls180.v:1448.5-1448.42"
+ attribute \src "ls180.v:1444.5-1444.42"
wire \main_sdcore_crc16_inserter_sink_ready
- attribute \src "ls180.v:1447.6-1447.43"
+ attribute \src "ls180.v:1443.6-1443.43"
wire \main_sdcore_crc16_inserter_sink_valid
- attribute \src "ls180.v:1454.5-1454.44"
+ attribute \src "ls180.v:1450.5-1450.44"
wire \main_sdcore_crc16_inserter_source_first
- attribute \src "ls180.v:1455.5-1455.43"
+ attribute \src "ls180.v:1451.5-1451.43"
wire \main_sdcore_crc16_inserter_source_last
- attribute \src "ls180.v:1456.11-1456.57"
+ attribute \src "ls180.v:1452.11-1452.57"
wire width 8 \main_sdcore_crc16_inserter_source_payload_data
- attribute \src "ls180.v:1453.5-1453.44"
+ attribute \src "ls180.v:1449.5-1449.44"
wire \main_sdcore_crc16_inserter_source_ready
- attribute \src "ls180.v:1452.5-1452.44"
+ attribute \src "ls180.v:1448.5-1448.44"
wire \main_sdcore_crc16_inserter_source_valid
- attribute \src "ls180.v:1445.6-1445.35"
+ attribute \src "ls180.v:1441.6-1441.35"
wire \main_sdcore_crc7_inserter_clr
- attribute \src "ls180.v:1444.11-1444.40"
+ attribute \src "ls180.v:1440.11-1440.40"
wire width 7 \main_sdcore_crc7_inserter_crc
- attribute \src "ls180.v:1402.11-1402.44"
+ attribute \src "ls180.v:1398.11-1398.44"
wire width 7 \main_sdcore_crc7_inserter_crcreg0
- attribute \src "ls180.v:1403.12-1403.45"
+ attribute \src "ls180.v:1399.12-1399.45"
wire width 7 \main_sdcore_crc7_inserter_crcreg1
- attribute \src "ls180.v:1412.12-1412.46"
+ attribute \src "ls180.v:1408.12-1408.46"
wire width 7 \main_sdcore_crc7_inserter_crcreg10
- attribute \src "ls180.v:1413.12-1413.46"
+ attribute \src "ls180.v:1409.12-1409.46"
wire width 7 \main_sdcore_crc7_inserter_crcreg11
- attribute \src "ls180.v:1414.12-1414.46"
+ attribute \src "ls180.v:1410.12-1410.46"
wire width 7 \main_sdcore_crc7_inserter_crcreg12
- attribute \src "ls180.v:1415.12-1415.46"
+ attribute \src "ls180.v:1411.12-1411.46"
wire width 7 \main_sdcore_crc7_inserter_crcreg13
- attribute \src "ls180.v:1416.12-1416.46"
+ attribute \src "ls180.v:1412.12-1412.46"
wire width 7 \main_sdcore_crc7_inserter_crcreg14
- attribute \src "ls180.v:1417.12-1417.46"
+ attribute \src "ls180.v:1413.12-1413.46"
wire width 7 \main_sdcore_crc7_inserter_crcreg15
- attribute \src "ls180.v:1418.12-1418.46"
+ attribute \src "ls180.v:1414.12-1414.46"
wire width 7 \main_sdcore_crc7_inserter_crcreg16
- attribute \src "ls180.v:1419.12-1419.46"
+ attribute \src "ls180.v:1415.12-1415.46"
wire width 7 \main_sdcore_crc7_inserter_crcreg17
- attribute \src "ls180.v:1420.12-1420.46"
+ attribute \src "ls180.v:1416.12-1416.46"
wire width 7 \main_sdcore_crc7_inserter_crcreg18
- attribute \src "ls180.v:1421.12-1421.46"
+ attribute \src "ls180.v:1417.12-1417.46"
wire width 7 \main_sdcore_crc7_inserter_crcreg19
- attribute \src "ls180.v:1404.12-1404.45"
+ attribute \src "ls180.v:1400.12-1400.45"
wire width 7 \main_sdcore_crc7_inserter_crcreg2
- attribute \src "ls180.v:1422.12-1422.46"
+ attribute \src "ls180.v:1418.12-1418.46"
wire width 7 \main_sdcore_crc7_inserter_crcreg20
- attribute \src "ls180.v:1423.12-1423.46"
+ attribute \src "ls180.v:1419.12-1419.46"
wire width 7 \main_sdcore_crc7_inserter_crcreg21
- attribute \src "ls180.v:1424.12-1424.46"
+ attribute \src "ls180.v:1420.12-1420.46"
wire width 7 \main_sdcore_crc7_inserter_crcreg22
- attribute \src "ls180.v:1425.12-1425.46"
+ attribute \src "ls180.v:1421.12-1421.46"
wire width 7 \main_sdcore_crc7_inserter_crcreg23
- attribute \src "ls180.v:1426.12-1426.46"
+ attribute \src "ls180.v:1422.12-1422.46"
wire width 7 \main_sdcore_crc7_inserter_crcreg24
- attribute \src "ls180.v:1427.12-1427.46"
+ attribute \src "ls180.v:1423.12-1423.46"
wire width 7 \main_sdcore_crc7_inserter_crcreg25
- attribute \src "ls180.v:1428.12-1428.46"
+ attribute \src "ls180.v:1424.12-1424.46"
wire width 7 \main_sdcore_crc7_inserter_crcreg26
- attribute \src "ls180.v:1429.12-1429.46"
+ attribute \src "ls180.v:1425.12-1425.46"
wire width 7 \main_sdcore_crc7_inserter_crcreg27
- attribute \src "ls180.v:1430.12-1430.46"
+ attribute \src "ls180.v:1426.12-1426.46"
wire width 7 \main_sdcore_crc7_inserter_crcreg28
- attribute \src "ls180.v:1431.12-1431.46"
+ attribute \src "ls180.v:1427.12-1427.46"
wire width 7 \main_sdcore_crc7_inserter_crcreg29
- attribute \src "ls180.v:1405.12-1405.45"
+ attribute \src "ls180.v:1401.12-1401.45"
wire width 7 \main_sdcore_crc7_inserter_crcreg3
- attribute \src "ls180.v:1432.12-1432.46"
+ attribute \src "ls180.v:1428.12-1428.46"
wire width 7 \main_sdcore_crc7_inserter_crcreg30
- attribute \src "ls180.v:1433.12-1433.46"
+ attribute \src "ls180.v:1429.12-1429.46"
wire width 7 \main_sdcore_crc7_inserter_crcreg31
- attribute \src "ls180.v:1434.12-1434.46"
+ attribute \src "ls180.v:1430.12-1430.46"
wire width 7 \main_sdcore_crc7_inserter_crcreg32
- attribute \src "ls180.v:1435.12-1435.46"
+ attribute \src "ls180.v:1431.12-1431.46"
wire width 7 \main_sdcore_crc7_inserter_crcreg33
- attribute \src "ls180.v:1436.12-1436.46"
+ attribute \src "ls180.v:1432.12-1432.46"
wire width 7 \main_sdcore_crc7_inserter_crcreg34
- attribute \src "ls180.v:1437.12-1437.46"
+ attribute \src "ls180.v:1433.12-1433.46"
wire width 7 \main_sdcore_crc7_inserter_crcreg35
- attribute \src "ls180.v:1438.12-1438.46"
+ attribute \src "ls180.v:1434.12-1434.46"
wire width 7 \main_sdcore_crc7_inserter_crcreg36
- attribute \src "ls180.v:1439.12-1439.46"
+ attribute \src "ls180.v:1435.12-1435.46"
wire width 7 \main_sdcore_crc7_inserter_crcreg37
- attribute \src "ls180.v:1440.12-1440.46"
+ attribute \src "ls180.v:1436.12-1436.46"
wire width 7 \main_sdcore_crc7_inserter_crcreg38
- attribute \src "ls180.v:1441.12-1441.46"
+ attribute \src "ls180.v:1437.12-1437.46"
wire width 7 \main_sdcore_crc7_inserter_crcreg39
- attribute \src "ls180.v:1406.12-1406.45"
+ attribute \src "ls180.v:1402.12-1402.45"
wire width 7 \main_sdcore_crc7_inserter_crcreg4
- attribute \src "ls180.v:1442.12-1442.46"
+ attribute \src "ls180.v:1438.12-1438.46"
wire width 7 \main_sdcore_crc7_inserter_crcreg40
- attribute \src "ls180.v:1407.12-1407.45"
+ attribute \src "ls180.v:1403.12-1403.45"
wire width 7 \main_sdcore_crc7_inserter_crcreg5
- attribute \src "ls180.v:1408.12-1408.45"
+ attribute \src "ls180.v:1404.12-1404.45"
wire width 7 \main_sdcore_crc7_inserter_crcreg6
- attribute \src "ls180.v:1409.12-1409.45"
+ attribute \src "ls180.v:1405.12-1405.45"
wire width 7 \main_sdcore_crc7_inserter_crcreg7
- attribute \src "ls180.v:1410.12-1410.45"
+ attribute \src "ls180.v:1406.12-1406.45"
wire width 7 \main_sdcore_crc7_inserter_crcreg8
- attribute \src "ls180.v:1411.12-1411.45"
+ attribute \src "ls180.v:1407.12-1407.45"
wire width 7 \main_sdcore_crc7_inserter_crcreg9
- attribute \src "ls180.v:1446.6-1446.38"
+ attribute \src "ls180.v:1442.6-1442.38"
wire \main_sdcore_crc7_inserter_enable
- attribute \src "ls180.v:1443.13-1443.42"
+ attribute \src "ls180.v:1439.13-1439.42"
wire width 40 \main_sdcore_crc7_inserter_val
- attribute \src "ls180.v:1545.12-1545.34"
+ attribute \src "ls180.v:1541.12-1541.34"
wire width 32 \main_sdcore_data_count
- attribute \src "ls180.v:1843.12-1843.57"
+ attribute \src "ls180.v:1839.12-1839.57"
wire width 32 \main_sdcore_data_count_sdcore_fsm_next_value3
- attribute \src "ls180.v:1844.5-1844.53"
+ attribute \src "ls180.v:1840.5-1840.53"
wire \main_sdcore_data_count_sdcore_fsm_next_value_ce3
- attribute \src "ls180.v:1546.5-1546.26"
+ attribute \src "ls180.v:1542.5-1542.26"
wire \main_sdcore_data_done
- attribute \src "ls180.v:1839.5-1839.49"
+ attribute \src "ls180.v:1835.5-1835.49"
wire \main_sdcore_data_done_sdcore_fsm_next_value1
- attribute \src "ls180.v:1840.5-1840.52"
+ attribute \src "ls180.v:1836.5-1836.52"
wire \main_sdcore_data_done_sdcore_fsm_next_value_ce1
- attribute \src "ls180.v:1547.5-1547.27"
+ attribute \src "ls180.v:1543.5-1543.27"
wire \main_sdcore_data_error
- attribute \src "ls180.v:1849.5-1849.50"
+ attribute \src "ls180.v:1845.5-1845.50"
wire \main_sdcore_data_error_sdcore_fsm_next_value6
- attribute \src "ls180.v:1850.5-1850.53"
+ attribute \src "ls180.v:1846.5-1846.53"
wire \main_sdcore_data_error_sdcore_fsm_next_value_ce6
- attribute \src "ls180.v:1396.12-1396.41"
+ attribute \src "ls180.v:1392.12-1392.41"
wire width 4 \main_sdcore_data_event_status
- attribute \src "ls180.v:1397.6-1397.31"
+ attribute \src "ls180.v:1393.6-1393.31"
wire \main_sdcore_data_event_we
- attribute \src "ls180.v:1548.5-1548.29"
+ attribute \src "ls180.v:1544.5-1544.29"
wire \main_sdcore_data_timeout
- attribute \src "ls180.v:1851.5-1851.52"
+ attribute \src "ls180.v:1847.5-1847.52"
wire \main_sdcore_data_timeout_sdcore_fsm_next_value7
- attribute \src "ls180.v:1852.5-1852.55"
+ attribute \src "ls180.v:1848.5-1848.55"
wire \main_sdcore_data_timeout_sdcore_fsm_next_value_ce7
- attribute \src "ls180.v:1544.12-1544.33"
+ attribute \src "ls180.v:1540.12-1540.33"
wire width 2 \main_sdcore_data_type
- attribute \src "ls180.v:1376.6-1376.33"
+ attribute \src "ls180.v:1372.6-1372.33"
wire \main_sdcore_sink_sink_first
- attribute \src "ls180.v:1377.6-1377.32"
+ attribute \src "ls180.v:1373.6-1373.32"
wire \main_sdcore_sink_sink_last
- attribute \src "ls180.v:1378.12-1378.46"
+ attribute \src "ls180.v:1374.12-1374.46"
wire width 8 \main_sdcore_sink_sink_payload_data
- attribute \src "ls180.v:1375.6-1375.33"
+ attribute \src "ls180.v:1371.6-1371.33"
wire \main_sdcore_sink_sink_ready
- attribute \src "ls180.v:1374.6-1374.33"
+ attribute \src "ls180.v:1370.6-1370.33"
wire \main_sdcore_sink_sink_valid
- attribute \src "ls180.v:1381.6-1381.37"
+ attribute \src "ls180.v:1377.6-1377.37"
wire \main_sdcore_source_source_first
- attribute \src "ls180.v:1382.6-1382.36"
+ attribute \src "ls180.v:1378.6-1378.36"
wire \main_sdcore_source_source_last
- attribute \src "ls180.v:1383.12-1383.50"
+ attribute \src "ls180.v:1379.12-1379.50"
wire width 8 \main_sdcore_source_source_payload_data
- attribute \src "ls180.v:1380.6-1380.37"
+ attribute \src "ls180.v:1376.6-1376.37"
wire \main_sdcore_source_source_ready
- attribute \src "ls180.v:1379.6-1379.37"
+ attribute \src "ls180.v:1375.6-1375.37"
wire \main_sdcore_source_source_valid
- attribute \src "ls180.v:1694.6-1694.38"
+ attribute \src "ls180.v:1690.6-1690.38"
wire \main_sdmem2block_converter_first
- attribute \src "ls180.v:1695.6-1695.37"
+ attribute \src "ls180.v:1691.6-1691.37"
wire \main_sdmem2block_converter_last
- attribute \src "ls180.v:1693.11-1693.41"
+ attribute \src "ls180.v:1689.11-1689.41"
wire width 2 \main_sdmem2block_converter_mux
- attribute \src "ls180.v:1684.6-1684.43"
+ attribute \src "ls180.v:1680.6-1680.43"
wire \main_sdmem2block_converter_sink_first
- attribute \src "ls180.v:1685.6-1685.42"
+ attribute \src "ls180.v:1681.6-1681.42"
wire \main_sdmem2block_converter_sink_last
- attribute \src "ls180.v:1686.13-1686.57"
+ attribute \src "ls180.v:1682.13-1682.57"
wire width 32 \main_sdmem2block_converter_sink_payload_data
- attribute \src "ls180.v:1683.6-1683.43"
+ attribute \src "ls180.v:1679.6-1679.43"
wire \main_sdmem2block_converter_sink_ready
- attribute \src "ls180.v:1682.6-1682.43"
+ attribute \src "ls180.v:1678.6-1678.43"
wire \main_sdmem2block_converter_sink_valid
- attribute \src "ls180.v:1689.6-1689.45"
+ attribute \src "ls180.v:1685.6-1685.45"
wire \main_sdmem2block_converter_source_first
- attribute \src "ls180.v:1690.6-1690.44"
+ attribute \src "ls180.v:1686.6-1686.44"
wire \main_sdmem2block_converter_source_last
- attribute \src "ls180.v:1691.11-1691.57"
+ attribute \src "ls180.v:1687.11-1687.57"
wire width 8 \main_sdmem2block_converter_source_payload_data
- attribute \src "ls180.v:1692.6-1692.65"
+ attribute \src "ls180.v:1688.6-1688.65"
wire \main_sdmem2block_converter_source_payload_valid_token_count
- attribute \src "ls180.v:1688.6-1688.45"
+ attribute \src "ls180.v:1684.6-1684.45"
wire \main_sdmem2block_converter_source_ready
- attribute \src "ls180.v:1687.6-1687.45"
+ attribute \src "ls180.v:1683.6-1683.45"
wire \main_sdmem2block_converter_source_valid
- attribute \src "ls180.v:1678.13-1678.38"
+ attribute \src "ls180.v:1674.13-1674.38"
wire width 32 \main_sdmem2block_dma_base
- attribute \src "ls180.v:1667.5-1667.33"
+ attribute \src "ls180.v:1663.5-1663.33"
wire \main_sdmem2block_dma_base_re
- attribute \src "ls180.v:1666.12-1666.45"
+ attribute \src "ls180.v:1662.12-1662.45"
wire width 64 \main_sdmem2block_dma_base_storage
- attribute \src "ls180.v:1665.12-1665.37"
+ attribute \src "ls180.v:1661.12-1661.37"
wire width 32 \main_sdmem2block_dma_data
- attribute \src "ls180.v:1861.12-1861.67"
+ attribute \src "ls180.v:1857.12-1857.67"
wire width 32 \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value
- attribute \src "ls180.v:1862.5-1862.63"
+ attribute \src "ls180.v:1858.5-1858.63"
wire \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce
- attribute \src "ls180.v:1672.5-1672.37"
+ attribute \src "ls180.v:1668.5-1668.37"
wire \main_sdmem2block_dma_done_status
- attribute \src "ls180.v:1673.6-1673.34"
+ attribute \src "ls180.v:1669.6-1669.34"
wire \main_sdmem2block_dma_done_we
- attribute \src "ls180.v:1671.5-1671.35"
+ attribute \src "ls180.v:1667.5-1667.35"
wire \main_sdmem2block_dma_enable_re
- attribute \src "ls180.v:1670.5-1670.40"
+ attribute \src "ls180.v:1666.5-1666.40"
wire \main_sdmem2block_dma_enable_storage
- attribute \src "ls180.v:1680.13-1680.40"
+ attribute \src "ls180.v:1676.13-1676.40"
wire width 32 \main_sdmem2block_dma_length
- attribute \src "ls180.v:1669.5-1669.35"
+ attribute \src "ls180.v:1665.5-1665.35"
wire \main_sdmem2block_dma_length_re
- attribute \src "ls180.v:1668.12-1668.47"
+ attribute \src "ls180.v:1664.12-1664.47"
wire width 32 \main_sdmem2block_dma_length_storage
- attribute \src "ls180.v:1675.5-1675.33"
+ attribute \src "ls180.v:1671.5-1671.33"
wire \main_sdmem2block_dma_loop_re
- attribute \src "ls180.v:1674.5-1674.38"
+ attribute \src "ls180.v:1670.5-1670.38"
wire \main_sdmem2block_dma_loop_storage
- attribute \src "ls180.v:1679.12-1679.39"
+ attribute \src "ls180.v:1675.12-1675.39"
wire width 32 \main_sdmem2block_dma_offset
- attribute \src "ls180.v:1865.12-1865.79"
+ attribute \src "ls180.v:1861.12-1861.79"
wire width 32 \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value
- attribute \src "ls180.v:1866.5-1866.75"
+ attribute \src "ls180.v:1862.5-1862.75"
wire \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce
- attribute \src "ls180.v:1676.13-1676.47"
+ attribute \src "ls180.v:1672.13-1672.47"
wire width 32 \main_sdmem2block_dma_offset_status
- attribute \src "ls180.v:1677.6-1677.36"
+ attribute \src "ls180.v:1673.6-1673.36"
wire \main_sdmem2block_dma_offset_we
- attribute \src "ls180.v:1681.6-1681.32"
+ attribute \src "ls180.v:1677.6-1677.32"
wire \main_sdmem2block_dma_reset
- attribute \src "ls180.v:1658.5-1658.35"
+ attribute \src "ls180.v:1654.5-1654.35"
wire \main_sdmem2block_dma_sink_last
- attribute \src "ls180.v:1659.12-1659.53"
+ attribute \src "ls180.v:1655.12-1655.53"
wire width 32 \main_sdmem2block_dma_sink_payload_address
- attribute \src "ls180.v:1657.5-1657.36"
+ attribute \src "ls180.v:1653.5-1653.36"
wire \main_sdmem2block_dma_sink_ready
- attribute \src "ls180.v:1656.5-1656.36"
+ attribute \src "ls180.v:1652.5-1652.36"
wire \main_sdmem2block_dma_sink_valid
- attribute \src "ls180.v:1662.5-1662.38"
+ attribute \src "ls180.v:1658.5-1658.38"
wire \main_sdmem2block_dma_source_first
- attribute \src "ls180.v:1663.5-1663.37"
+ attribute \src "ls180.v:1659.5-1659.37"
wire \main_sdmem2block_dma_source_last
- attribute \src "ls180.v:1664.12-1664.52"
+ attribute \src "ls180.v:1660.12-1660.52"
wire width 32 \main_sdmem2block_dma_source_payload_data
- attribute \src "ls180.v:1661.6-1661.39"
+ attribute \src "ls180.v:1657.6-1657.39"
wire \main_sdmem2block_dma_source_ready
- attribute \src "ls180.v:1660.5-1660.38"
+ attribute \src "ls180.v:1656.5-1656.38"
wire \main_sdmem2block_dma_source_valid
- attribute \src "ls180.v:1720.11-1720.40"
+ attribute \src "ls180.v:1716.11-1716.40"
wire width 5 \main_sdmem2block_fifo_consume
- attribute \src "ls180.v:1725.6-1725.35"
+ attribute \src "ls180.v:1721.6-1721.35"
wire \main_sdmem2block_fifo_do_read
- attribute \src "ls180.v:1729.6-1729.41"
+ attribute \src "ls180.v:1725.6-1725.41"
wire \main_sdmem2block_fifo_fifo_in_first
- attribute \src "ls180.v:1730.6-1730.40"
+ attribute \src "ls180.v:1726.6-1726.40"
wire \main_sdmem2block_fifo_fifo_in_last
- attribute \src "ls180.v:1728.12-1728.54"
+ attribute \src "ls180.v:1724.12-1724.54"
wire width 8 \main_sdmem2block_fifo_fifo_in_payload_data
- attribute \src "ls180.v:1732.6-1732.42"
+ attribute \src "ls180.v:1728.6-1728.42"
wire \main_sdmem2block_fifo_fifo_out_first
- attribute \src "ls180.v:1733.6-1733.41"
+ attribute \src "ls180.v:1729.6-1729.41"
wire \main_sdmem2block_fifo_fifo_out_last
- attribute \src "ls180.v:1731.12-1731.55"
+ attribute \src "ls180.v:1727.12-1727.55"
wire width 8 \main_sdmem2block_fifo_fifo_out_payload_data
- attribute \src "ls180.v:1717.11-1717.38"
+ attribute \src "ls180.v:1713.11-1713.38"
wire width 6 \main_sdmem2block_fifo_level
- attribute \src "ls180.v:1719.11-1719.40"
+ attribute \src "ls180.v:1715.11-1715.40"
wire width 5 \main_sdmem2block_fifo_produce
- attribute \src "ls180.v:1726.12-1726.44"
+ attribute \src "ls180.v:1722.12-1722.44"
wire width 5 \main_sdmem2block_fifo_rdport_adr
- attribute \src "ls180.v:1727.12-1727.46"
+ attribute \src "ls180.v:1723.12-1723.46"
wire width 10 \main_sdmem2block_fifo_rdport_dat_r
- attribute \src "ls180.v:1718.5-1718.34"
+ attribute \src "ls180.v:1714.5-1714.34"
wire \main_sdmem2block_fifo_replace
- attribute \src "ls180.v:1703.6-1703.38"
+ attribute \src "ls180.v:1699.6-1699.38"
wire \main_sdmem2block_fifo_sink_first
- attribute \src "ls180.v:1704.6-1704.37"
+ attribute \src "ls180.v:1700.6-1700.37"
wire \main_sdmem2block_fifo_sink_last
- attribute \src "ls180.v:1705.12-1705.51"
+ attribute \src "ls180.v:1701.12-1701.51"
wire width 8 \main_sdmem2block_fifo_sink_payload_data
- attribute \src "ls180.v:1702.6-1702.38"
+ attribute \src "ls180.v:1698.6-1698.38"
wire \main_sdmem2block_fifo_sink_ready
- attribute \src "ls180.v:1701.6-1701.38"
+ attribute \src "ls180.v:1697.6-1697.38"
wire \main_sdmem2block_fifo_sink_valid
- attribute \src "ls180.v:1708.6-1708.40"
+ attribute \src "ls180.v:1704.6-1704.40"
wire \main_sdmem2block_fifo_source_first
- attribute \src "ls180.v:1709.6-1709.39"
+ attribute \src "ls180.v:1705.6-1705.39"
wire \main_sdmem2block_fifo_source_last
- attribute \src "ls180.v:1710.12-1710.53"
+ attribute \src "ls180.v:1706.12-1706.53"
wire width 8 \main_sdmem2block_fifo_source_payload_data
- attribute \src "ls180.v:1707.6-1707.40"
+ attribute \src "ls180.v:1703.6-1703.40"
wire \main_sdmem2block_fifo_source_ready
- attribute \src "ls180.v:1706.6-1706.40"
+ attribute \src "ls180.v:1702.6-1702.40"
wire \main_sdmem2block_fifo_source_valid
- attribute \src "ls180.v:1715.12-1715.46"
+ attribute \src "ls180.v:1711.12-1711.46"
wire width 10 \main_sdmem2block_fifo_syncfifo_din
- attribute \src "ls180.v:1716.12-1716.47"
+ attribute \src "ls180.v:1712.12-1712.47"
wire width 10 \main_sdmem2block_fifo_syncfifo_dout
- attribute \src "ls180.v:1713.6-1713.39"
+ attribute \src "ls180.v:1709.6-1709.39"
wire \main_sdmem2block_fifo_syncfifo_re
- attribute \src "ls180.v:1714.6-1714.45"
+ attribute \src "ls180.v:1710.6-1710.45"
wire \main_sdmem2block_fifo_syncfifo_readable
- attribute \src "ls180.v:1711.6-1711.39"
+ attribute \src "ls180.v:1707.6-1707.39"
wire \main_sdmem2block_fifo_syncfifo_we
- attribute \src "ls180.v:1712.6-1712.45"
+ attribute \src "ls180.v:1708.6-1708.45"
wire \main_sdmem2block_fifo_syncfifo_writable
- attribute \src "ls180.v:1721.11-1721.43"
+ attribute \src "ls180.v:1717.11-1717.43"
wire width 5 \main_sdmem2block_fifo_wrport_adr
- attribute \src "ls180.v:1722.12-1722.46"
+ attribute \src "ls180.v:1718.12-1718.46"
wire width 10 \main_sdmem2block_fifo_wrport_dat_r
- attribute \src "ls180.v:1724.12-1724.46"
+ attribute \src "ls180.v:1720.12-1720.46"
wire width 10 \main_sdmem2block_fifo_wrport_dat_w
- attribute \src "ls180.v:1723.6-1723.37"
+ attribute \src "ls180.v:1719.6-1719.37"
wire \main_sdmem2block_fifo_wrport_we
- attribute \src "ls180.v:1653.6-1653.43"
+ attribute \src "ls180.v:1649.6-1649.43"
wire \main_sdmem2block_source_source_first0
- attribute \src "ls180.v:1698.6-1698.43"
+ attribute \src "ls180.v:1694.6-1694.43"
wire \main_sdmem2block_source_source_first1
- attribute \src "ls180.v:1654.6-1654.42"
+ attribute \src "ls180.v:1650.6-1650.42"
wire \main_sdmem2block_source_source_last0
- attribute \src "ls180.v:1699.6-1699.42"
+ attribute \src "ls180.v:1695.6-1695.42"
wire \main_sdmem2block_source_source_last1
- attribute \src "ls180.v:1655.12-1655.56"
+ attribute \src "ls180.v:1651.12-1651.56"
wire width 8 \main_sdmem2block_source_source_payload_data0
- attribute \src "ls180.v:1700.12-1700.56"
+ attribute \src "ls180.v:1696.12-1696.56"
wire width 8 \main_sdmem2block_source_source_payload_data1
- attribute \src "ls180.v:1652.6-1652.43"
+ attribute \src "ls180.v:1648.6-1648.43"
wire \main_sdmem2block_source_source_ready0
- attribute \src "ls180.v:1697.6-1697.43"
+ attribute \src "ls180.v:1693.6-1693.43"
wire \main_sdmem2block_source_source_ready1
- attribute \src "ls180.v:1651.6-1651.43"
+ attribute \src "ls180.v:1647.6-1647.43"
wire \main_sdmem2block_source_source_valid0
- attribute \src "ls180.v:1696.6-1696.43"
+ attribute \src "ls180.v:1692.6-1692.43"
wire \main_sdmem2block_source_source_valid1
- attribute \src "ls180.v:1102.6-1102.27"
+ attribute \src "ls180.v:1098.6-1098.27"
wire \main_sdphy_clocker_ce
- attribute \src "ls180.v:1101.5-1101.28"
+ attribute \src "ls180.v:1097.5-1097.28"
wire \main_sdphy_clocker_clk0
- attribute \src "ls180.v:1104.5-1104.28"
+ attribute \src "ls180.v:1100.5-1100.28"
wire \main_sdphy_clocker_clk1
- attribute \src "ls180.v:1105.5-1105.29"
+ attribute \src "ls180.v:1101.5-1101.29"
wire \main_sdphy_clocker_clk_d
- attribute \src "ls180.v:1103.11-1103.34"
+ attribute \src "ls180.v:1099.11-1099.34"
wire width 9 \main_sdphy_clocker_clks
- attribute \src "ls180.v:1099.5-1099.26"
+ attribute \src "ls180.v:1095.5-1095.26"
wire \main_sdphy_clocker_re
- attribute \src "ls180.v:1100.6-1100.29"
+ attribute \src "ls180.v:1096.6-1096.29"
wire \main_sdphy_clocker_stop
- attribute \src "ls180.v:1098.11-1098.37"
+ attribute \src "ls180.v:1094.11-1094.37"
wire width 9 \main_sdphy_clocker_storage
- attribute \src "ls180.v:1202.6-1202.41"
+ attribute \src "ls180.v:1198.6-1198.41"
wire \main_sdphy_cmdr_cmdr_buf_sink_first
- attribute \src "ls180.v:1203.6-1203.40"
+ attribute \src "ls180.v:1199.6-1199.40"
wire \main_sdphy_cmdr_cmdr_buf_sink_last
- attribute \src "ls180.v:1204.12-1204.54"
+ attribute \src "ls180.v:1200.12-1200.54"
wire width 8 \main_sdphy_cmdr_cmdr_buf_sink_payload_data
- attribute \src "ls180.v:1201.6-1201.41"
+ attribute \src "ls180.v:1197.6-1197.41"
wire \main_sdphy_cmdr_cmdr_buf_sink_ready
- attribute \src "ls180.v:1200.6-1200.41"
+ attribute \src "ls180.v:1196.6-1196.41"
wire \main_sdphy_cmdr_cmdr_buf_sink_valid
- attribute \src "ls180.v:1207.5-1207.42"
+ attribute \src "ls180.v:1203.5-1203.42"
wire \main_sdphy_cmdr_cmdr_buf_source_first
- attribute \src "ls180.v:1208.5-1208.41"
+ attribute \src "ls180.v:1204.5-1204.41"
wire \main_sdphy_cmdr_cmdr_buf_source_last
- attribute \src "ls180.v:1209.11-1209.55"
+ attribute \src "ls180.v:1205.11-1205.55"
wire width 8 \main_sdphy_cmdr_cmdr_buf_source_payload_data
- attribute \src "ls180.v:1206.6-1206.43"
+ attribute \src "ls180.v:1202.6-1202.43"
wire \main_sdphy_cmdr_cmdr_buf_source_ready
- attribute \src "ls180.v:1205.5-1205.42"
+ attribute \src "ls180.v:1201.5-1201.42"
wire \main_sdphy_cmdr_cmdr_buf_source_valid
- attribute \src "ls180.v:1192.11-1192.47"
+ attribute \src "ls180.v:1188.11-1188.47"
wire width 3 \main_sdphy_cmdr_cmdr_converter_demux
- attribute \src "ls180.v:1193.6-1193.46"
+ attribute \src "ls180.v:1189.6-1189.46"
wire \main_sdphy_cmdr_cmdr_converter_load_part
- attribute \src "ls180.v:1183.5-1183.46"
+ attribute \src "ls180.v:1179.5-1179.46"
wire \main_sdphy_cmdr_cmdr_converter_sink_first
- attribute \src "ls180.v:1184.5-1184.45"
+ attribute \src "ls180.v:1180.5-1180.45"
wire \main_sdphy_cmdr_cmdr_converter_sink_last
- attribute \src "ls180.v:1185.6-1185.54"
+ attribute \src "ls180.v:1181.6-1181.54"
wire \main_sdphy_cmdr_cmdr_converter_sink_payload_data
- attribute \src "ls180.v:1182.6-1182.47"
+ attribute \src "ls180.v:1178.6-1178.47"
wire \main_sdphy_cmdr_cmdr_converter_sink_ready
- attribute \src "ls180.v:1181.6-1181.47"
+ attribute \src "ls180.v:1177.6-1177.47"
wire \main_sdphy_cmdr_cmdr_converter_sink_valid
- attribute \src "ls180.v:1188.5-1188.48"
+ attribute \src "ls180.v:1184.5-1184.48"
wire \main_sdphy_cmdr_cmdr_converter_source_first
- attribute \src "ls180.v:1189.5-1189.47"
+ attribute \src "ls180.v:1185.5-1185.47"
wire \main_sdphy_cmdr_cmdr_converter_source_last
- attribute \src "ls180.v:1190.11-1190.61"
+ attribute \src "ls180.v:1186.11-1186.61"
wire width 8 \main_sdphy_cmdr_cmdr_converter_source_payload_data
- attribute \src "ls180.v:1191.11-1191.74"
+ attribute \src "ls180.v:1187.11-1187.74"
wire width 4 \main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count
- attribute \src "ls180.v:1187.6-1187.49"
+ attribute \src "ls180.v:1183.6-1183.49"
wire \main_sdphy_cmdr_cmdr_converter_source_ready
- attribute \src "ls180.v:1186.6-1186.49"
+ attribute \src "ls180.v:1182.6-1182.49"
wire \main_sdphy_cmdr_cmdr_converter_source_valid
- attribute \src "ls180.v:1194.5-1194.46"
+ attribute \src "ls180.v:1190.5-1190.46"
wire \main_sdphy_cmdr_cmdr_converter_strobe_all
- attribute \src "ls180.v:1165.6-1165.40"
+ attribute \src "ls180.v:1161.6-1161.40"
wire \main_sdphy_cmdr_cmdr_pads_in_first
- attribute \src "ls180.v:1166.6-1166.39"
+ attribute \src "ls180.v:1162.6-1162.39"
wire \main_sdphy_cmdr_cmdr_pads_in_last
- attribute \src "ls180.v:1167.6-1167.46"
+ attribute \src "ls180.v:1163.6-1163.46"
wire \main_sdphy_cmdr_cmdr_pads_in_payload_clk
- attribute \src "ls180.v:1168.6-1168.48"
+ attribute \src "ls180.v:1164.6-1164.48"
wire \main_sdphy_cmdr_cmdr_pads_in_payload_cmd_i
- attribute \src "ls180.v:1169.6-1169.48"
+ attribute \src "ls180.v:1165.6-1165.48"
wire \main_sdphy_cmdr_cmdr_pads_in_payload_cmd_o
- attribute \src "ls180.v:1170.6-1170.49"
+ attribute \src "ls180.v:1166.6-1166.49"
wire \main_sdphy_cmdr_cmdr_pads_in_payload_cmd_oe
- attribute \src "ls180.v:1171.12-1171.55"
+ attribute \src "ls180.v:1167.12-1167.55"
wire width 4 \main_sdphy_cmdr_cmdr_pads_in_payload_data_i
- attribute \src "ls180.v:1172.12-1172.55"
+ attribute \src "ls180.v:1168.12-1168.55"
wire width 4 \main_sdphy_cmdr_cmdr_pads_in_payload_data_o
- attribute \src "ls180.v:1173.6-1173.50"
+ attribute \src "ls180.v:1169.6-1169.50"
wire \main_sdphy_cmdr_cmdr_pads_in_payload_data_oe
- attribute \src "ls180.v:1164.5-1164.39"
+ attribute \src "ls180.v:1160.5-1160.39"
wire \main_sdphy_cmdr_cmdr_pads_in_ready
- attribute \src "ls180.v:1163.6-1163.40"
+ attribute \src "ls180.v:1159.6-1159.40"
wire \main_sdphy_cmdr_cmdr_pads_in_valid
- attribute \src "ls180.v:1210.5-1210.31"
+ attribute \src "ls180.v:1206.5-1206.31"
wire \main_sdphy_cmdr_cmdr_reset
- attribute \src "ls180.v:1805.5-1805.59"
+ attribute \src "ls180.v:1801.5-1801.59"
wire \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2
- attribute \src "ls180.v:1806.5-1806.62"
+ attribute \src "ls180.v:1802.5-1802.62"
wire \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2
- attribute \src "ls180.v:1180.5-1180.29"
+ attribute \src "ls180.v:1176.5-1176.29"
wire \main_sdphy_cmdr_cmdr_run
- attribute \src "ls180.v:1176.6-1176.47"
+ attribute \src "ls180.v:1172.6-1172.47"
wire \main_sdphy_cmdr_cmdr_source_source_first0
- attribute \src "ls180.v:1197.6-1197.47"
+ attribute \src "ls180.v:1193.6-1193.47"
wire \main_sdphy_cmdr_cmdr_source_source_first1
- attribute \src "ls180.v:1177.6-1177.46"
+ attribute \src "ls180.v:1173.6-1173.46"
wire \main_sdphy_cmdr_cmdr_source_source_last0
- attribute \src "ls180.v:1198.6-1198.46"
+ attribute \src "ls180.v:1194.6-1194.46"
wire \main_sdphy_cmdr_cmdr_source_source_last1
- attribute \src "ls180.v:1178.12-1178.60"
+ attribute \src "ls180.v:1174.12-1174.60"
wire width 8 \main_sdphy_cmdr_cmdr_source_source_payload_data0
- attribute \src "ls180.v:1199.12-1199.60"
+ attribute \src "ls180.v:1195.12-1195.60"
wire width 8 \main_sdphy_cmdr_cmdr_source_source_payload_data1
- attribute \src "ls180.v:1175.5-1175.46"
+ attribute \src "ls180.v:1171.5-1171.46"
wire \main_sdphy_cmdr_cmdr_source_source_ready0
- attribute \src "ls180.v:1196.6-1196.47"
+ attribute \src "ls180.v:1192.6-1192.47"
wire \main_sdphy_cmdr_cmdr_source_source_ready1
- attribute \src "ls180.v:1174.6-1174.47"
+ attribute \src "ls180.v:1170.6-1170.47"
wire \main_sdphy_cmdr_cmdr_source_source_valid0
- attribute \src "ls180.v:1195.6-1195.47"
+ attribute \src "ls180.v:1191.6-1191.47"
wire \main_sdphy_cmdr_cmdr_source_source_valid1
- attribute \src "ls180.v:1179.6-1179.32"
+ attribute \src "ls180.v:1175.6-1175.32"
wire \main_sdphy_cmdr_cmdr_start
- attribute \src "ls180.v:1162.11-1162.32"
+ attribute \src "ls180.v:1158.11-1158.32"
wire width 8 \main_sdphy_cmdr_count
- attribute \src "ls180.v:1801.11-1801.60"
+ attribute \src "ls180.v:1797.11-1797.60"
wire width 8 \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0
- attribute \src "ls180.v:1802.5-1802.57"
+ attribute \src "ls180.v:1798.5-1798.57"
wire \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0
- attribute \src "ls180.v:1137.5-1137.42"
+ attribute \src "ls180.v:1133.5-1133.42"
wire \main_sdphy_cmdr_pads_in_pads_in_first
- attribute \src "ls180.v:1138.5-1138.41"
+ attribute \src "ls180.v:1134.5-1134.41"
wire \main_sdphy_cmdr_pads_in_pads_in_last
- attribute \src "ls180.v:1139.5-1139.48"
+ attribute \src "ls180.v:1135.5-1135.48"
wire \main_sdphy_cmdr_pads_in_pads_in_payload_clk
- attribute \src "ls180.v:1140.6-1140.51"
+ attribute \src "ls180.v:1136.6-1136.51"
wire \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_i
- attribute \src "ls180.v:1141.5-1141.50"
+ attribute \src "ls180.v:1137.5-1137.50"
wire \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_o
- attribute \src "ls180.v:1142.5-1142.51"
+ attribute \src "ls180.v:1138.5-1138.51"
wire \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_oe
- attribute \src "ls180.v:1143.12-1143.58"
+ attribute \src "ls180.v:1139.12-1139.58"
wire width 4 \main_sdphy_cmdr_pads_in_pads_in_payload_data_i
- attribute \src "ls180.v:1144.11-1144.57"
+ attribute \src "ls180.v:1140.11-1140.57"
wire width 4 \main_sdphy_cmdr_pads_in_pads_in_payload_data_o
- attribute \src "ls180.v:1145.5-1145.52"
+ attribute \src "ls180.v:1141.5-1141.52"
wire \main_sdphy_cmdr_pads_in_pads_in_payload_data_oe
- attribute \src "ls180.v:1136.6-1136.43"
+ attribute \src "ls180.v:1132.6-1132.43"
wire \main_sdphy_cmdr_pads_in_pads_in_ready
- attribute \src "ls180.v:1135.6-1135.43"
+ attribute \src "ls180.v:1131.6-1131.43"
wire \main_sdphy_cmdr_pads_in_pads_in_valid
- attribute \src "ls180.v:1147.5-1147.41"
+ attribute \src "ls180.v:1143.5-1143.41"
wire \main_sdphy_cmdr_pads_out_payload_clk
- attribute \src "ls180.v:1148.5-1148.43"
+ attribute \src "ls180.v:1144.5-1144.43"
wire \main_sdphy_cmdr_pads_out_payload_cmd_o
- attribute \src "ls180.v:1149.5-1149.44"
+ attribute \src "ls180.v:1145.5-1145.44"
wire \main_sdphy_cmdr_pads_out_payload_cmd_oe
- attribute \src "ls180.v:1150.11-1150.50"
+ attribute \src "ls180.v:1146.11-1146.50"
wire width 4 \main_sdphy_cmdr_pads_out_payload_data_o
- attribute \src "ls180.v:1151.5-1151.45"
+ attribute \src "ls180.v:1147.5-1147.45"
wire \main_sdphy_cmdr_pads_out_payload_data_oe
- attribute \src "ls180.v:1146.6-1146.36"
+ attribute \src "ls180.v:1142.6-1142.36"
wire \main_sdphy_cmdr_pads_out_ready
- attribute \src "ls180.v:1154.5-1154.30"
+ attribute \src "ls180.v:1150.5-1150.30"
wire \main_sdphy_cmdr_sink_last
- attribute \src "ls180.v:1155.11-1155.46"
+ attribute \src "ls180.v:1151.11-1151.46"
wire width 8 \main_sdphy_cmdr_sink_payload_length
- attribute \src "ls180.v:1153.5-1153.31"
+ attribute \src "ls180.v:1149.5-1149.31"
wire \main_sdphy_cmdr_sink_ready
- attribute \src "ls180.v:1152.5-1152.31"
+ attribute \src "ls180.v:1148.5-1148.31"
wire \main_sdphy_cmdr_sink_valid
- attribute \src "ls180.v:1158.5-1158.32"
+ attribute \src "ls180.v:1154.5-1154.32"
wire \main_sdphy_cmdr_source_last
- attribute \src "ls180.v:1159.11-1159.46"
+ attribute \src "ls180.v:1155.11-1155.46"
wire width 8 \main_sdphy_cmdr_source_payload_data
- attribute \src "ls180.v:1160.11-1160.48"
+ attribute \src "ls180.v:1156.11-1156.48"
wire width 3 \main_sdphy_cmdr_source_payload_status
- attribute \src "ls180.v:1157.5-1157.33"
+ attribute \src "ls180.v:1153.5-1153.33"
wire \main_sdphy_cmdr_source_ready
- attribute \src "ls180.v:1156.5-1156.33"
+ attribute \src "ls180.v:1152.5-1152.33"
wire \main_sdphy_cmdr_source_valid
- attribute \src "ls180.v:1161.12-1161.35"
+ attribute \src "ls180.v:1157.12-1157.35"
wire width 32 \main_sdphy_cmdr_timeout
- attribute \src "ls180.v:1803.12-1803.63"
+ attribute \src "ls180.v:1799.12-1799.63"
wire width 32 \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1
- attribute \src "ls180.v:1804.5-1804.59"
+ attribute \src "ls180.v:1800.5-1800.59"
wire \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1
- attribute \src "ls180.v:1134.11-1134.32"
+ attribute \src "ls180.v:1130.11-1130.32"
wire width 8 \main_sdphy_cmdw_count
- attribute \src "ls180.v:1797.11-1797.59"
+ attribute \src "ls180.v:1793.11-1793.59"
wire width 8 \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value
- attribute \src "ls180.v:1798.5-1798.56"
+ attribute \src "ls180.v:1794.5-1794.56"
wire \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce
- attribute \src "ls180.v:1133.5-1133.25"
+ attribute \src "ls180.v:1129.5-1129.25"
wire \main_sdphy_cmdw_done
- attribute \src "ls180.v:1121.6-1121.43"
+ attribute \src "ls180.v:1117.6-1117.43"
wire \main_sdphy_cmdw_pads_in_payload_cmd_i
- attribute \src "ls180.v:1122.12-1122.50"
+ attribute \src "ls180.v:1118.12-1118.50"
wire width 4 \main_sdphy_cmdw_pads_in_payload_data_i
- attribute \src "ls180.v:1120.6-1120.35"
+ attribute \src "ls180.v:1116.6-1116.35"
wire \main_sdphy_cmdw_pads_in_valid
- attribute \src "ls180.v:1124.5-1124.41"
+ attribute \src "ls180.v:1120.5-1120.41"
wire \main_sdphy_cmdw_pads_out_payload_clk
- attribute \src "ls180.v:1125.5-1125.43"
+ attribute \src "ls180.v:1121.5-1121.43"
wire \main_sdphy_cmdw_pads_out_payload_cmd_o
- attribute \src "ls180.v:1126.5-1126.44"
+ attribute \src "ls180.v:1122.5-1122.44"
wire \main_sdphy_cmdw_pads_out_payload_cmd_oe
- attribute \src "ls180.v:1127.11-1127.50"
+ attribute \src "ls180.v:1123.11-1123.50"
wire width 4 \main_sdphy_cmdw_pads_out_payload_data_o
- attribute \src "ls180.v:1128.5-1128.45"
+ attribute \src "ls180.v:1124.5-1124.45"
wire \main_sdphy_cmdw_pads_out_payload_data_oe
- attribute \src "ls180.v:1123.6-1123.36"
+ attribute \src "ls180.v:1119.6-1119.36"
wire \main_sdphy_cmdw_pads_out_ready
- attribute \src "ls180.v:1131.5-1131.30"
+ attribute \src "ls180.v:1127.5-1127.30"
wire \main_sdphy_cmdw_sink_last
- attribute \src "ls180.v:1132.11-1132.44"
+ attribute \src "ls180.v:1128.11-1128.44"
wire width 8 \main_sdphy_cmdw_sink_payload_data
- attribute \src "ls180.v:1130.5-1130.31"
+ attribute \src "ls180.v:1126.5-1126.31"
wire \main_sdphy_cmdw_sink_ready
- attribute \src "ls180.v:1129.5-1129.31"
+ attribute \src "ls180.v:1125.5-1125.31"
wire \main_sdphy_cmdw_sink_valid
- attribute \src "ls180.v:1318.11-1318.33"
+ attribute \src "ls180.v:1314.11-1314.33"
wire width 10 \main_sdphy_datar_count
- attribute \src "ls180.v:1817.11-1817.62"
+ attribute \src "ls180.v:1813.11-1813.62"
wire width 10 \main_sdphy_datar_count_sdphy_sdphydatar_next_value0
- attribute \src "ls180.v:1818.5-1818.59"
+ attribute \src "ls180.v:1814.5-1814.59"
wire \main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0
- attribute \src "ls180.v:1358.6-1358.43"
+ attribute \src "ls180.v:1354.6-1354.43"
wire \main_sdphy_datar_datar_buf_sink_first
- attribute \src "ls180.v:1359.6-1359.42"
+ attribute \src "ls180.v:1355.6-1355.42"
wire \main_sdphy_datar_datar_buf_sink_last
- attribute \src "ls180.v:1360.12-1360.56"
+ attribute \src "ls180.v:1356.12-1356.56"
wire width 8 \main_sdphy_datar_datar_buf_sink_payload_data
- attribute \src "ls180.v:1357.6-1357.43"
+ attribute \src "ls180.v:1353.6-1353.43"
wire \main_sdphy_datar_datar_buf_sink_ready
- attribute \src "ls180.v:1356.6-1356.43"
+ attribute \src "ls180.v:1352.6-1352.43"
wire \main_sdphy_datar_datar_buf_sink_valid
- attribute \src "ls180.v:1363.5-1363.44"
+ attribute \src "ls180.v:1359.5-1359.44"
wire \main_sdphy_datar_datar_buf_source_first
- attribute \src "ls180.v:1364.5-1364.43"
+ attribute \src "ls180.v:1360.5-1360.43"
wire \main_sdphy_datar_datar_buf_source_last
- attribute \src "ls180.v:1365.11-1365.57"
+ attribute \src "ls180.v:1361.11-1361.57"
wire width 8 \main_sdphy_datar_datar_buf_source_payload_data
- attribute \src "ls180.v:1362.6-1362.45"
+ attribute \src "ls180.v:1358.6-1358.45"
wire \main_sdphy_datar_datar_buf_source_ready
- attribute \src "ls180.v:1361.5-1361.44"
+ attribute \src "ls180.v:1357.5-1357.44"
wire \main_sdphy_datar_datar_buf_source_valid
- attribute \src "ls180.v:1348.5-1348.43"
+ attribute \src "ls180.v:1344.5-1344.43"
wire \main_sdphy_datar_datar_converter_demux
- attribute \src "ls180.v:1349.6-1349.48"
+ attribute \src "ls180.v:1345.6-1345.48"
wire \main_sdphy_datar_datar_converter_load_part
- attribute \src "ls180.v:1339.5-1339.48"
+ attribute \src "ls180.v:1335.5-1335.48"
wire \main_sdphy_datar_datar_converter_sink_first
- attribute \src "ls180.v:1340.5-1340.47"
+ attribute \src "ls180.v:1336.5-1336.47"
wire \main_sdphy_datar_datar_converter_sink_last
- attribute \src "ls180.v:1341.12-1341.62"
+ attribute \src "ls180.v:1337.12-1337.62"
wire width 4 \main_sdphy_datar_datar_converter_sink_payload_data
- attribute \src "ls180.v:1338.6-1338.49"
+ attribute \src "ls180.v:1334.6-1334.49"
wire \main_sdphy_datar_datar_converter_sink_ready
- attribute \src "ls180.v:1337.6-1337.49"
+ attribute \src "ls180.v:1333.6-1333.49"
wire \main_sdphy_datar_datar_converter_sink_valid
- attribute \src "ls180.v:1344.5-1344.50"
+ attribute \src "ls180.v:1340.5-1340.50"
wire \main_sdphy_datar_datar_converter_source_first
- attribute \src "ls180.v:1345.5-1345.49"
+ attribute \src "ls180.v:1341.5-1341.49"
wire \main_sdphy_datar_datar_converter_source_last
- attribute \src "ls180.v:1346.11-1346.63"
+ attribute \src "ls180.v:1342.11-1342.63"
wire width 8 \main_sdphy_datar_datar_converter_source_payload_data
- attribute \src "ls180.v:1347.11-1347.76"
+ attribute \src "ls180.v:1343.11-1343.76"
wire width 2 \main_sdphy_datar_datar_converter_source_payload_valid_token_count
- attribute \src "ls180.v:1343.6-1343.51"
+ attribute \src "ls180.v:1339.6-1339.51"
wire \main_sdphy_datar_datar_converter_source_ready
- attribute \src "ls180.v:1342.6-1342.51"
+ attribute \src "ls180.v:1338.6-1338.51"
wire \main_sdphy_datar_datar_converter_source_valid
- attribute \src "ls180.v:1350.5-1350.48"
+ attribute \src "ls180.v:1346.5-1346.48"
wire \main_sdphy_datar_datar_converter_strobe_all
- attribute \src "ls180.v:1321.6-1321.42"
+ attribute \src "ls180.v:1317.6-1317.42"
wire \main_sdphy_datar_datar_pads_in_first
- attribute \src "ls180.v:1322.6-1322.41"
+ attribute \src "ls180.v:1318.6-1318.41"
wire \main_sdphy_datar_datar_pads_in_last
- attribute \src "ls180.v:1323.6-1323.48"
+ attribute \src "ls180.v:1319.6-1319.48"
wire \main_sdphy_datar_datar_pads_in_payload_clk
- attribute \src "ls180.v:1324.6-1324.50"
+ attribute \src "ls180.v:1320.6-1320.50"
wire \main_sdphy_datar_datar_pads_in_payload_cmd_i
- attribute \src "ls180.v:1325.6-1325.50"
+ attribute \src "ls180.v:1321.6-1321.50"
wire \main_sdphy_datar_datar_pads_in_payload_cmd_o
- attribute \src "ls180.v:1326.6-1326.51"
+ attribute \src "ls180.v:1322.6-1322.51"
wire \main_sdphy_datar_datar_pads_in_payload_cmd_oe
- attribute \src "ls180.v:1327.12-1327.57"
+ attribute \src "ls180.v:1323.12-1323.57"
wire width 4 \main_sdphy_datar_datar_pads_in_payload_data_i
- attribute \src "ls180.v:1328.12-1328.57"
+ attribute \src "ls180.v:1324.12-1324.57"
wire width 4 \main_sdphy_datar_datar_pads_in_payload_data_o
- attribute \src "ls180.v:1329.6-1329.52"
+ attribute \src "ls180.v:1325.6-1325.52"
wire \main_sdphy_datar_datar_pads_in_payload_data_oe
- attribute \src "ls180.v:1320.5-1320.41"
+ attribute \src "ls180.v:1316.5-1316.41"
wire \main_sdphy_datar_datar_pads_in_ready
- attribute \src "ls180.v:1319.6-1319.42"
+ attribute \src "ls180.v:1315.6-1315.42"
wire \main_sdphy_datar_datar_pads_in_valid
- attribute \src "ls180.v:1366.5-1366.33"
+ attribute \src "ls180.v:1362.5-1362.33"
wire \main_sdphy_datar_datar_reset
- attribute \src "ls180.v:1821.5-1821.62"
+ attribute \src "ls180.v:1817.5-1817.62"
wire \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2
- attribute \src "ls180.v:1822.5-1822.65"
+ attribute \src "ls180.v:1818.5-1818.65"
wire \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2
- attribute \src "ls180.v:1336.5-1336.31"
+ attribute \src "ls180.v:1332.5-1332.31"
wire \main_sdphy_datar_datar_run
- attribute \src "ls180.v:1332.6-1332.49"
+ attribute \src "ls180.v:1328.6-1328.49"
wire \main_sdphy_datar_datar_source_source_first0
- attribute \src "ls180.v:1353.6-1353.49"
+ attribute \src "ls180.v:1349.6-1349.49"
wire \main_sdphy_datar_datar_source_source_first1
- attribute \src "ls180.v:1333.6-1333.48"
+ attribute \src "ls180.v:1329.6-1329.48"
wire \main_sdphy_datar_datar_source_source_last0
- attribute \src "ls180.v:1354.6-1354.48"
+ attribute \src "ls180.v:1350.6-1350.48"
wire \main_sdphy_datar_datar_source_source_last1
- attribute \src "ls180.v:1334.12-1334.62"
+ attribute \src "ls180.v:1330.12-1330.62"
wire width 8 \main_sdphy_datar_datar_source_source_payload_data0
- attribute \src "ls180.v:1355.12-1355.62"
+ attribute \src "ls180.v:1351.12-1351.62"
wire width 8 \main_sdphy_datar_datar_source_source_payload_data1
- attribute \src "ls180.v:1331.5-1331.48"
+ attribute \src "ls180.v:1327.5-1327.48"
wire \main_sdphy_datar_datar_source_source_ready0
- attribute \src "ls180.v:1352.6-1352.49"
+ attribute \src "ls180.v:1348.6-1348.49"
wire \main_sdphy_datar_datar_source_source_ready1
- attribute \src "ls180.v:1330.6-1330.49"
+ attribute \src "ls180.v:1326.6-1326.49"
wire \main_sdphy_datar_datar_source_source_valid0
- attribute \src "ls180.v:1351.6-1351.49"
+ attribute \src "ls180.v:1347.6-1347.49"
wire \main_sdphy_datar_datar_source_source_valid1
- attribute \src "ls180.v:1335.6-1335.34"
+ attribute \src "ls180.v:1331.6-1331.34"
wire \main_sdphy_datar_datar_start
- attribute \src "ls180.v:1291.5-1291.43"
+ attribute \src "ls180.v:1287.5-1287.43"
wire \main_sdphy_datar_pads_in_pads_in_first
- attribute \src "ls180.v:1292.5-1292.42"
+ attribute \src "ls180.v:1288.5-1288.42"
wire \main_sdphy_datar_pads_in_pads_in_last
- attribute \src "ls180.v:1293.5-1293.49"
+ attribute \src "ls180.v:1289.5-1289.49"
wire \main_sdphy_datar_pads_in_pads_in_payload_clk
- attribute \src "ls180.v:1294.6-1294.52"
+ attribute \src "ls180.v:1290.6-1290.52"
wire \main_sdphy_datar_pads_in_pads_in_payload_cmd_i
- attribute \src "ls180.v:1295.5-1295.51"
+ attribute \src "ls180.v:1291.5-1291.51"
wire \main_sdphy_datar_pads_in_pads_in_payload_cmd_o
- attribute \src "ls180.v:1296.5-1296.52"
+ attribute \src "ls180.v:1292.5-1292.52"
wire \main_sdphy_datar_pads_in_pads_in_payload_cmd_oe
- attribute \src "ls180.v:1297.12-1297.59"
+ attribute \src "ls180.v:1293.12-1293.59"
wire width 4 \main_sdphy_datar_pads_in_pads_in_payload_data_i
- attribute \src "ls180.v:1298.11-1298.58"
+ attribute \src "ls180.v:1294.11-1294.58"
wire width 4 \main_sdphy_datar_pads_in_pads_in_payload_data_o
- attribute \src "ls180.v:1299.5-1299.53"
+ attribute \src "ls180.v:1295.5-1295.53"
wire \main_sdphy_datar_pads_in_pads_in_payload_data_oe
- attribute \src "ls180.v:1290.6-1290.44"
+ attribute \src "ls180.v:1286.6-1286.44"
wire \main_sdphy_datar_pads_in_pads_in_ready
- attribute \src "ls180.v:1289.6-1289.44"
+ attribute \src "ls180.v:1285.6-1285.44"
wire \main_sdphy_datar_pads_in_pads_in_valid
- attribute \src "ls180.v:1301.5-1301.42"
+ attribute \src "ls180.v:1297.5-1297.42"
wire \main_sdphy_datar_pads_out_payload_clk
- attribute \src "ls180.v:1302.5-1302.44"
+ attribute \src "ls180.v:1298.5-1298.44"
wire \main_sdphy_datar_pads_out_payload_cmd_o
- attribute \src "ls180.v:1303.5-1303.45"
+ attribute \src "ls180.v:1299.5-1299.45"
wire \main_sdphy_datar_pads_out_payload_cmd_oe
- attribute \src "ls180.v:1304.11-1304.51"
+ attribute \src "ls180.v:1300.11-1300.51"
wire width 4 \main_sdphy_datar_pads_out_payload_data_o
- attribute \src "ls180.v:1305.5-1305.46"
+ attribute \src "ls180.v:1301.5-1301.46"
wire \main_sdphy_datar_pads_out_payload_data_oe
- attribute \src "ls180.v:1300.6-1300.37"
+ attribute \src "ls180.v:1296.6-1296.37"
wire \main_sdphy_datar_pads_out_ready
- attribute \src "ls180.v:1308.5-1308.31"
+ attribute \src "ls180.v:1304.5-1304.31"
wire \main_sdphy_datar_sink_last
- attribute \src "ls180.v:1309.11-1309.53"
+ attribute \src "ls180.v:1305.11-1305.53"
wire width 10 \main_sdphy_datar_sink_payload_block_length
- attribute \src "ls180.v:1307.5-1307.32"
+ attribute \src "ls180.v:1303.5-1303.32"
wire \main_sdphy_datar_sink_ready
- attribute \src "ls180.v:1306.5-1306.32"
+ attribute \src "ls180.v:1302.5-1302.32"
wire \main_sdphy_datar_sink_valid
- attribute \src "ls180.v:1312.5-1312.34"
+ attribute \src "ls180.v:1308.5-1308.34"
wire \main_sdphy_datar_source_first
- attribute \src "ls180.v:1313.5-1313.33"
+ attribute \src "ls180.v:1309.5-1309.33"
wire \main_sdphy_datar_source_last
- attribute \src "ls180.v:1314.11-1314.47"
+ attribute \src "ls180.v:1310.11-1310.47"
wire width 8 \main_sdphy_datar_source_payload_data
- attribute \src "ls180.v:1315.11-1315.49"
+ attribute \src "ls180.v:1311.11-1311.49"
wire width 3 \main_sdphy_datar_source_payload_status
- attribute \src "ls180.v:1311.5-1311.34"
+ attribute \src "ls180.v:1307.5-1307.34"
wire \main_sdphy_datar_source_ready
- attribute \src "ls180.v:1310.5-1310.34"
+ attribute \src "ls180.v:1306.5-1306.34"
wire \main_sdphy_datar_source_valid
- attribute \src "ls180.v:1316.5-1316.26"
+ attribute \src "ls180.v:1312.5-1312.26"
wire \main_sdphy_datar_stop
- attribute \src "ls180.v:1317.12-1317.36"
+ attribute \src "ls180.v:1313.12-1313.36"
wire width 32 \main_sdphy_datar_timeout
- attribute \src "ls180.v:1819.12-1819.65"
+ attribute \src "ls180.v:1815.12-1815.65"
wire width 32 \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1
- attribute \src "ls180.v:1820.5-1820.61"
+ attribute \src "ls180.v:1816.5-1816.61"
wire \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1
- attribute \src "ls180.v:1226.11-1226.33"
+ attribute \src "ls180.v:1222.11-1222.33"
wire width 8 \main_sdphy_dataw_count
- attribute \src "ls180.v:1813.11-1813.54"
+ attribute \src "ls180.v:1809.11-1809.54"
wire width 8 \main_sdphy_dataw_count_sdphy_fsm_next_value
- attribute \src "ls180.v:1814.5-1814.51"
+ attribute \src "ls180.v:1810.5-1810.51"
wire \main_sdphy_dataw_count_sdphy_fsm_next_value_ce
- attribute \src "ls180.v:1280.6-1280.42"
+ attribute \src "ls180.v:1276.6-1276.42"
wire \main_sdphy_dataw_crcr_buf_sink_first
- attribute \src "ls180.v:1281.6-1281.41"
+ attribute \src "ls180.v:1277.6-1277.41"
wire \main_sdphy_dataw_crcr_buf_sink_last
- attribute \src "ls180.v:1282.12-1282.55"
+ attribute \src "ls180.v:1278.12-1278.55"
wire width 8 \main_sdphy_dataw_crcr_buf_sink_payload_data
- attribute \src "ls180.v:1279.6-1279.42"
+ attribute \src "ls180.v:1275.6-1275.42"
wire \main_sdphy_dataw_crcr_buf_sink_ready
- attribute \src "ls180.v:1278.6-1278.42"
+ attribute \src "ls180.v:1274.6-1274.42"
wire \main_sdphy_dataw_crcr_buf_sink_valid
- attribute \src "ls180.v:1285.5-1285.43"
+ attribute \src "ls180.v:1281.5-1281.43"
wire \main_sdphy_dataw_crcr_buf_source_first
- attribute \src "ls180.v:1286.5-1286.42"
+ attribute \src "ls180.v:1282.5-1282.42"
wire \main_sdphy_dataw_crcr_buf_source_last
- attribute \src "ls180.v:1287.11-1287.56"
+ attribute \src "ls180.v:1283.11-1283.56"
wire width 8 \main_sdphy_dataw_crcr_buf_source_payload_data
- attribute \src "ls180.v:1284.6-1284.44"
+ attribute \src "ls180.v:1280.6-1280.44"
wire \main_sdphy_dataw_crcr_buf_source_ready
- attribute \src "ls180.v:1283.5-1283.43"
+ attribute \src "ls180.v:1279.5-1279.43"
wire \main_sdphy_dataw_crcr_buf_source_valid
- attribute \src "ls180.v:1270.11-1270.48"
+ attribute \src "ls180.v:1266.11-1266.48"
wire width 3 \main_sdphy_dataw_crcr_converter_demux
- attribute \src "ls180.v:1271.6-1271.47"
+ attribute \src "ls180.v:1267.6-1267.47"
wire \main_sdphy_dataw_crcr_converter_load_part
- attribute \src "ls180.v:1261.5-1261.47"
+ attribute \src "ls180.v:1257.5-1257.47"
wire \main_sdphy_dataw_crcr_converter_sink_first
- attribute \src "ls180.v:1262.5-1262.46"
+ attribute \src "ls180.v:1258.5-1258.46"
wire \main_sdphy_dataw_crcr_converter_sink_last
- attribute \src "ls180.v:1263.6-1263.55"
+ attribute \src "ls180.v:1259.6-1259.55"
wire \main_sdphy_dataw_crcr_converter_sink_payload_data
- attribute \src "ls180.v:1260.6-1260.48"
+ attribute \src "ls180.v:1256.6-1256.48"
wire \main_sdphy_dataw_crcr_converter_sink_ready
- attribute \src "ls180.v:1259.6-1259.48"
+ attribute \src "ls180.v:1255.6-1255.48"
wire \main_sdphy_dataw_crcr_converter_sink_valid
- attribute \src "ls180.v:1266.5-1266.49"
+ attribute \src "ls180.v:1262.5-1262.49"
wire \main_sdphy_dataw_crcr_converter_source_first
- attribute \src "ls180.v:1267.5-1267.48"
+ attribute \src "ls180.v:1263.5-1263.48"
wire \main_sdphy_dataw_crcr_converter_source_last
- attribute \src "ls180.v:1268.11-1268.62"
+ attribute \src "ls180.v:1264.11-1264.62"
wire width 8 \main_sdphy_dataw_crcr_converter_source_payload_data
- attribute \src "ls180.v:1269.11-1269.75"
+ attribute \src "ls180.v:1265.11-1265.75"
wire width 4 \main_sdphy_dataw_crcr_converter_source_payload_valid_token_count
- attribute \src "ls180.v:1265.6-1265.50"
+ attribute \src "ls180.v:1261.6-1261.50"
wire \main_sdphy_dataw_crcr_converter_source_ready
- attribute \src "ls180.v:1264.6-1264.50"
+ attribute \src "ls180.v:1260.6-1260.50"
wire \main_sdphy_dataw_crcr_converter_source_valid
- attribute \src "ls180.v:1272.5-1272.47"
+ attribute \src "ls180.v:1268.5-1268.47"
wire \main_sdphy_dataw_crcr_converter_strobe_all
- attribute \src "ls180.v:1243.6-1243.41"
+ attribute \src "ls180.v:1239.6-1239.41"
wire \main_sdphy_dataw_crcr_pads_in_first
- attribute \src "ls180.v:1244.6-1244.40"
+ attribute \src "ls180.v:1240.6-1240.40"
wire \main_sdphy_dataw_crcr_pads_in_last
- attribute \src "ls180.v:1245.6-1245.47"
+ attribute \src "ls180.v:1241.6-1241.47"
wire \main_sdphy_dataw_crcr_pads_in_payload_clk
- attribute \src "ls180.v:1246.6-1246.49"
+ attribute \src "ls180.v:1242.6-1242.49"
wire \main_sdphy_dataw_crcr_pads_in_payload_cmd_i
- attribute \src "ls180.v:1247.6-1247.49"
+ attribute \src "ls180.v:1243.6-1243.49"
wire \main_sdphy_dataw_crcr_pads_in_payload_cmd_o
- attribute \src "ls180.v:1248.6-1248.50"
+ attribute \src "ls180.v:1244.6-1244.50"
wire \main_sdphy_dataw_crcr_pads_in_payload_cmd_oe
- attribute \src "ls180.v:1249.12-1249.56"
+ attribute \src "ls180.v:1245.12-1245.56"
wire width 4 \main_sdphy_dataw_crcr_pads_in_payload_data_i
- attribute \src "ls180.v:1250.12-1250.56"
+ attribute \src "ls180.v:1246.12-1246.56"
wire width 4 \main_sdphy_dataw_crcr_pads_in_payload_data_o
- attribute \src "ls180.v:1251.6-1251.51"
+ attribute \src "ls180.v:1247.6-1247.51"
wire \main_sdphy_dataw_crcr_pads_in_payload_data_oe
- attribute \src "ls180.v:1242.5-1242.40"
+ attribute \src "ls180.v:1238.5-1238.40"
wire \main_sdphy_dataw_crcr_pads_in_ready
- attribute \src "ls180.v:1241.6-1241.41"
+ attribute \src "ls180.v:1237.6-1237.41"
wire \main_sdphy_dataw_crcr_pads_in_valid
- attribute \src "ls180.v:1288.5-1288.32"
+ attribute \src "ls180.v:1284.5-1284.32"
wire \main_sdphy_dataw_crcr_reset
- attribute \src "ls180.v:1809.5-1809.59"
+ attribute \src "ls180.v:1805.5-1805.59"
wire \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value
- attribute \src "ls180.v:1810.5-1810.62"
+ attribute \src "ls180.v:1806.5-1806.62"
wire \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce
- attribute \src "ls180.v:1258.5-1258.30"
+ attribute \src "ls180.v:1254.5-1254.30"
wire \main_sdphy_dataw_crcr_run
- attribute \src "ls180.v:1254.6-1254.48"
+ attribute \src "ls180.v:1250.6-1250.48"
wire \main_sdphy_dataw_crcr_source_source_first0
- attribute \src "ls180.v:1275.6-1275.48"
+ attribute \src "ls180.v:1271.6-1271.48"
wire \main_sdphy_dataw_crcr_source_source_first1
- attribute \src "ls180.v:1255.6-1255.47"
+ attribute \src "ls180.v:1251.6-1251.47"
wire \main_sdphy_dataw_crcr_source_source_last0
- attribute \src "ls180.v:1276.6-1276.47"
+ attribute \src "ls180.v:1272.6-1272.47"
wire \main_sdphy_dataw_crcr_source_source_last1
- attribute \src "ls180.v:1256.12-1256.61"
+ attribute \src "ls180.v:1252.12-1252.61"
wire width 8 \main_sdphy_dataw_crcr_source_source_payload_data0
- attribute \src "ls180.v:1277.12-1277.61"
+ attribute \src "ls180.v:1273.12-1273.61"
wire width 8 \main_sdphy_dataw_crcr_source_source_payload_data1
- attribute \src "ls180.v:1253.5-1253.47"
+ attribute \src "ls180.v:1249.5-1249.47"
wire \main_sdphy_dataw_crcr_source_source_ready0
- attribute \src "ls180.v:1274.6-1274.48"
+ attribute \src "ls180.v:1270.6-1270.48"
wire \main_sdphy_dataw_crcr_source_source_ready1
- attribute \src "ls180.v:1252.6-1252.48"
+ attribute \src "ls180.v:1248.6-1248.48"
wire \main_sdphy_dataw_crcr_source_source_valid0
- attribute \src "ls180.v:1273.6-1273.48"
+ attribute \src "ls180.v:1269.6-1269.48"
wire \main_sdphy_dataw_crcr_source_source_valid1
- attribute \src "ls180.v:1257.6-1257.33"
+ attribute \src "ls180.v:1253.6-1253.33"
wire \main_sdphy_dataw_crcr_start
- attribute \src "ls180.v:1240.5-1240.27"
+ attribute \src "ls180.v:1236.5-1236.27"
wire \main_sdphy_dataw_error
- attribute \src "ls180.v:1229.5-1229.43"
+ attribute \src "ls180.v:1225.5-1225.43"
wire \main_sdphy_dataw_pads_in_pads_in_first
- attribute \src "ls180.v:1230.5-1230.42"
+ attribute \src "ls180.v:1226.5-1226.42"
wire \main_sdphy_dataw_pads_in_pads_in_last
- attribute \src "ls180.v:1231.5-1231.49"
+ attribute \src "ls180.v:1227.5-1227.49"
wire \main_sdphy_dataw_pads_in_pads_in_payload_clk
- attribute \src "ls180.v:1232.5-1232.51"
+ attribute \src "ls180.v:1228.5-1228.51"
wire \main_sdphy_dataw_pads_in_pads_in_payload_cmd_i
- attribute \src "ls180.v:1233.5-1233.51"
+ attribute \src "ls180.v:1229.5-1229.51"
wire \main_sdphy_dataw_pads_in_pads_in_payload_cmd_o
- attribute \src "ls180.v:1234.5-1234.52"
+ attribute \src "ls180.v:1230.5-1230.52"
wire \main_sdphy_dataw_pads_in_pads_in_payload_cmd_oe
- attribute \src "ls180.v:1235.11-1235.58"
+ attribute \src "ls180.v:1231.11-1231.58"
wire width 4 \main_sdphy_dataw_pads_in_pads_in_payload_data_i
- attribute \src "ls180.v:1236.11-1236.58"
+ attribute \src "ls180.v:1232.11-1232.58"
wire width 4 \main_sdphy_dataw_pads_in_pads_in_payload_data_o
- attribute \src "ls180.v:1237.5-1237.53"
+ attribute \src "ls180.v:1233.5-1233.53"
wire \main_sdphy_dataw_pads_in_pads_in_payload_data_oe
- attribute \src "ls180.v:1228.6-1228.44"
+ attribute \src "ls180.v:1224.6-1224.44"
wire \main_sdphy_dataw_pads_in_pads_in_ready
- attribute \src "ls180.v:1227.5-1227.43"
+ attribute \src "ls180.v:1223.5-1223.43"
wire \main_sdphy_dataw_pads_in_pads_in_valid
- attribute \src "ls180.v:1212.6-1212.44"
+ attribute \src "ls180.v:1208.6-1208.44"
wire \main_sdphy_dataw_pads_in_payload_cmd_i
- attribute \src "ls180.v:1213.12-1213.51"
+ attribute \src "ls180.v:1209.12-1209.51"
wire width 4 \main_sdphy_dataw_pads_in_payload_data_i
- attribute \src "ls180.v:1211.6-1211.36"
+ attribute \src "ls180.v:1207.6-1207.36"
wire \main_sdphy_dataw_pads_in_valid
- attribute \src "ls180.v:1215.5-1215.42"
+ attribute \src "ls180.v:1211.5-1211.42"
wire \main_sdphy_dataw_pads_out_payload_clk
- attribute \src "ls180.v:1216.5-1216.44"
+ attribute \src "ls180.v:1212.5-1212.44"
wire \main_sdphy_dataw_pads_out_payload_cmd_o
- attribute \src "ls180.v:1217.5-1217.45"
+ attribute \src "ls180.v:1213.5-1213.45"
wire \main_sdphy_dataw_pads_out_payload_cmd_oe
- attribute \src "ls180.v:1218.11-1218.51"
+ attribute \src "ls180.v:1214.11-1214.51"
wire width 4 \main_sdphy_dataw_pads_out_payload_data_o
- attribute \src "ls180.v:1219.5-1219.46"
+ attribute \src "ls180.v:1215.5-1215.46"
wire \main_sdphy_dataw_pads_out_payload_data_oe
- attribute \src "ls180.v:1214.6-1214.37"
+ attribute \src "ls180.v:1210.6-1210.37"
wire \main_sdphy_dataw_pads_out_ready
- attribute \src "ls180.v:1222.5-1222.32"
+ attribute \src "ls180.v:1218.5-1218.32"
wire \main_sdphy_dataw_sink_first
- attribute \src "ls180.v:1223.5-1223.31"
+ attribute \src "ls180.v:1219.5-1219.31"
wire \main_sdphy_dataw_sink_last
- attribute \src "ls180.v:1224.11-1224.45"
+ attribute \src "ls180.v:1220.11-1220.45"
wire width 8 \main_sdphy_dataw_sink_payload_data
- attribute \src "ls180.v:1221.5-1221.32"
+ attribute \src "ls180.v:1217.5-1217.32"
wire \main_sdphy_dataw_sink_ready
- attribute \src "ls180.v:1220.5-1220.32"
+ attribute \src "ls180.v:1216.5-1216.32"
wire \main_sdphy_dataw_sink_valid
- attribute \src "ls180.v:1238.5-1238.27"
+ attribute \src "ls180.v:1234.5-1234.27"
wire \main_sdphy_dataw_start
- attribute \src "ls180.v:1225.5-1225.26"
+ attribute \src "ls180.v:1221.5-1221.26"
wire \main_sdphy_dataw_stop
- attribute \src "ls180.v:1239.5-1239.27"
+ attribute \src "ls180.v:1235.5-1235.27"
wire \main_sdphy_dataw_valid
- attribute \src "ls180.v:1119.11-1119.32"
+ attribute \src "ls180.v:1115.11-1115.32"
wire width 8 \main_sdphy_init_count
- attribute \src "ls180.v:1793.11-1793.59"
+ attribute \src "ls180.v:1789.11-1789.59"
wire width 8 \main_sdphy_init_count_sdphy_sdphyinit_next_value
- attribute \src "ls180.v:1794.5-1794.56"
+ attribute \src "ls180.v:1790.5-1790.56"
wire \main_sdphy_init_count_sdphy_sdphyinit_next_value_ce
- attribute \src "ls180.v:1107.6-1107.34"
+ attribute \src "ls180.v:1103.6-1103.34"
wire \main_sdphy_init_initialize_r
- attribute \src "ls180.v:1106.6-1106.35"
+ attribute \src "ls180.v:1102.6-1102.35"
wire \main_sdphy_init_initialize_re
- attribute \src "ls180.v:1109.5-1109.33"
+ attribute \src "ls180.v:1105.5-1105.33"
wire \main_sdphy_init_initialize_w
- attribute \src "ls180.v:1108.6-1108.35"
+ attribute \src "ls180.v:1104.6-1104.35"
wire \main_sdphy_init_initialize_we
- attribute \src "ls180.v:1111.6-1111.43"
+ attribute \src "ls180.v:1107.6-1107.43"
wire \main_sdphy_init_pads_in_payload_cmd_i
- attribute \src "ls180.v:1112.12-1112.50"
+ attribute \src "ls180.v:1108.12-1108.50"
wire width 4 \main_sdphy_init_pads_in_payload_data_i
- attribute \src "ls180.v:1110.6-1110.35"
+ attribute \src "ls180.v:1106.6-1106.35"
wire \main_sdphy_init_pads_in_valid
- attribute \src "ls180.v:1114.5-1114.41"
+ attribute \src "ls180.v:1110.5-1110.41"
wire \main_sdphy_init_pads_out_payload_clk
- attribute \src "ls180.v:1115.5-1115.43"
+ attribute \src "ls180.v:1111.5-1111.43"
wire \main_sdphy_init_pads_out_payload_cmd_o
- attribute \src "ls180.v:1116.5-1116.44"
+ attribute \src "ls180.v:1112.5-1112.44"
wire \main_sdphy_init_pads_out_payload_cmd_oe
- attribute \src "ls180.v:1117.11-1117.50"
+ attribute \src "ls180.v:1113.11-1113.50"
wire width 4 \main_sdphy_init_pads_out_payload_data_o
- attribute \src "ls180.v:1118.5-1118.45"
+ attribute \src "ls180.v:1114.5-1114.45"
wire \main_sdphy_init_pads_out_payload_data_oe
- attribute \src "ls180.v:1113.6-1113.36"
+ attribute \src "ls180.v:1109.6-1109.36"
wire \main_sdphy_init_pads_out_ready
- attribute \src "ls180.v:1367.6-1367.27"
+ attribute \src "ls180.v:1363.6-1363.27"
wire \main_sdphy_sdpads_clk
- attribute \src "ls180.v:1368.5-1368.28"
+ attribute \src "ls180.v:1364.5-1364.28"
wire \main_sdphy_sdpads_cmd_i
- attribute \src "ls180.v:1369.6-1369.29"
+ attribute \src "ls180.v:1365.6-1365.29"
wire \main_sdphy_sdpads_cmd_o
- attribute \src "ls180.v:1370.6-1370.30"
+ attribute \src "ls180.v:1366.6-1366.30"
wire \main_sdphy_sdpads_cmd_oe
- attribute \src "ls180.v:1371.11-1371.35"
+ attribute \src "ls180.v:1367.11-1367.35"
wire width 4 \main_sdphy_sdpads_data_i
- attribute \src "ls180.v:1372.12-1372.36"
+ attribute \src "ls180.v:1368.12-1368.36"
wire width 4 \main_sdphy_sdpads_data_o
- attribute \src "ls180.v:1373.6-1373.31"
+ attribute \src "ls180.v:1369.6-1369.31"
wire \main_sdphy_sdpads_data_oe
- attribute \src "ls180.v:1096.6-1096.23"
+ attribute \src "ls180.v:1092.6-1092.23"
wire \main_sdphy_status
- attribute \src "ls180.v:1097.6-1097.19"
+ attribute \src "ls180.v:1093.6-1093.19"
wire \main_sdphy_we
- attribute \src "ls180.v:331.5-331.26"
+ attribute \src "ls180.v:327.5-327.26"
wire \main_sdram_address_re
- attribute \src "ls180.v:330.12-330.38"
+ attribute \src "ls180.v:326.12-326.38"
wire width 13 \main_sdram_address_storage
- attribute \src "ls180.v:333.5-333.27"
+ attribute \src "ls180.v:329.5-329.27"
wire \main_sdram_baddress_re
- attribute \src "ls180.v:332.11-332.38"
+ attribute \src "ls180.v:328.11-328.38"
wire width 2 \main_sdram_baddress_storage
- attribute \src "ls180.v:429.5-429.43"
+ attribute \src "ls180.v:425.5-425.43"
wire \main_sdram_bankmachine0_auto_precharge
- attribute \src "ls180.v:451.11-451.63"
+ attribute \src "ls180.v:447.11-447.63"
wire width 3 \main_sdram_bankmachine0_cmd_buffer_lookahead_consume
- attribute \src "ls180.v:456.6-456.58"
+ attribute \src "ls180.v:452.6-452.58"
wire \main_sdram_bankmachine0_cmd_buffer_lookahead_do_read
- attribute \src "ls180.v:461.6-461.64"
+ attribute \src "ls180.v:457.6-457.64"
wire \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_first
- attribute \src "ls180.v:462.6-462.63"
+ attribute \src "ls180.v:458.6-458.63"
wire \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_last
- attribute \src "ls180.v:460.13-460.78"
+ attribute \src "ls180.v:456.13-456.78"
wire width 22 \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr
- attribute \src "ls180.v:459.6-459.69"
+ attribute \src "ls180.v:455.6-455.69"
wire \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we
- attribute \src "ls180.v:465.6-465.65"
+ attribute \src "ls180.v:461.6-461.65"
wire \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first
- attribute \src "ls180.v:466.6-466.64"
+ attribute \src "ls180.v:462.6-462.64"
wire \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last
- attribute \src "ls180.v:464.13-464.79"
+ attribute \src "ls180.v:460.13-460.79"
wire width 22 \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr
- attribute \src "ls180.v:463.6-463.70"
+ attribute \src "ls180.v:459.6-459.70"
wire \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we
- attribute \src "ls180.v:448.11-448.61"
+ attribute \src "ls180.v:444.11-444.61"
wire width 4 \main_sdram_bankmachine0_cmd_buffer_lookahead_level
- attribute \src "ls180.v:450.11-450.63"
+ attribute \src "ls180.v:446.11-446.63"
wire width 3 \main_sdram_bankmachine0_cmd_buffer_lookahead_produce
- attribute \src "ls180.v:457.12-457.67"
+ attribute \src "ls180.v:453.12-453.67"
wire width 3 \main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_adr
- attribute \src "ls180.v:458.13-458.70"
+ attribute \src "ls180.v:454.13-454.70"
wire width 25 \main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r
- attribute \src "ls180.v:449.5-449.57"
+ attribute \src "ls180.v:445.5-445.57"
wire \main_sdram_bankmachine0_cmd_buffer_lookahead_replace
- attribute \src "ls180.v:432.5-432.60"
+ attribute \src "ls180.v:428.5-428.60"
wire \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first
- attribute \src "ls180.v:433.5-433.59"
+ attribute \src "ls180.v:429.5-429.59"
wire \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last
- attribute \src "ls180.v:435.13-435.75"
+ attribute \src "ls180.v:431.13-431.75"
wire width 22 \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_addr
- attribute \src "ls180.v:434.6-434.66"
+ attribute \src "ls180.v:430.6-430.66"
wire \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_we
- attribute \src "ls180.v:431.6-431.61"
+ attribute \src "ls180.v:427.6-427.61"
wire \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_ready
- attribute \src "ls180.v:430.6-430.61"
+ attribute \src "ls180.v:426.6-426.61"
wire \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_valid
- attribute \src "ls180.v:438.6-438.63"
+ attribute \src "ls180.v:434.6-434.63"
wire \main_sdram_bankmachine0_cmd_buffer_lookahead_source_first
- attribute \src "ls180.v:439.6-439.62"
+ attribute \src "ls180.v:435.6-435.62"
wire \main_sdram_bankmachine0_cmd_buffer_lookahead_source_last
- attribute \src "ls180.v:441.13-441.77"
+ attribute \src "ls180.v:437.13-437.77"
wire width 22 \main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr
- attribute \src "ls180.v:440.6-440.68"
+ attribute \src "ls180.v:436.6-436.68"
wire \main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_we
- attribute \src "ls180.v:437.6-437.63"
+ attribute \src "ls180.v:433.6-433.63"
wire \main_sdram_bankmachine0_cmd_buffer_lookahead_source_ready
- attribute \src "ls180.v:436.6-436.63"
+ attribute \src "ls180.v:432.6-432.63"
wire \main_sdram_bankmachine0_cmd_buffer_lookahead_source_valid
- attribute \src "ls180.v:446.13-446.71"
+ attribute \src "ls180.v:442.13-442.71"
wire width 25 \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_din
- attribute \src "ls180.v:447.13-447.72"
+ attribute \src "ls180.v:443.13-443.72"
wire width 25 \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout
- attribute \src "ls180.v:444.6-444.63"
+ attribute \src "ls180.v:440.6-440.63"
wire \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_re
- attribute \src "ls180.v:445.6-445.69"
+ attribute \src "ls180.v:441.6-441.69"
wire \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable
- attribute \src "ls180.v:442.6-442.63"
+ attribute \src "ls180.v:438.6-438.63"
wire \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we
- attribute \src "ls180.v:443.6-443.69"
+ attribute \src "ls180.v:439.6-439.69"
wire \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable
- attribute \src "ls180.v:452.11-452.66"
+ attribute \src "ls180.v:448.11-448.66"
wire width 3 \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr
- attribute \src "ls180.v:453.13-453.70"
+ attribute \src "ls180.v:449.13-449.70"
wire width 25 \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_r
- attribute \src "ls180.v:455.13-455.70"
+ attribute \src "ls180.v:451.13-451.70"
wire width 25 \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w
- attribute \src "ls180.v:454.6-454.60"
+ attribute \src "ls180.v:450.6-450.60"
wire \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_we
- attribute \src "ls180.v:469.6-469.51"
+ attribute \src "ls180.v:465.6-465.51"
wire \main_sdram_bankmachine0_cmd_buffer_sink_first
- attribute \src "ls180.v:470.6-470.50"
+ attribute \src "ls180.v:466.6-466.50"
wire \main_sdram_bankmachine0_cmd_buffer_sink_last
- attribute \src "ls180.v:472.13-472.65"
+ attribute \src "ls180.v:468.13-468.65"
wire width 22 \main_sdram_bankmachine0_cmd_buffer_sink_payload_addr
- attribute \src "ls180.v:471.6-471.56"
+ attribute \src "ls180.v:467.6-467.56"
wire \main_sdram_bankmachine0_cmd_buffer_sink_payload_we
- attribute \src "ls180.v:468.6-468.51"
+ attribute \src "ls180.v:464.6-464.51"
wire \main_sdram_bankmachine0_cmd_buffer_sink_ready
- attribute \src "ls180.v:467.6-467.51"
+ attribute \src "ls180.v:463.6-463.51"
wire \main_sdram_bankmachine0_cmd_buffer_sink_valid
- attribute \src "ls180.v:475.5-475.52"
+ attribute \src "ls180.v:471.5-471.52"
wire \main_sdram_bankmachine0_cmd_buffer_source_first
- attribute \src "ls180.v:476.5-476.51"
+ attribute \src "ls180.v:472.5-472.51"
wire \main_sdram_bankmachine0_cmd_buffer_source_last
- attribute \src "ls180.v:478.12-478.66"
+ attribute \src "ls180.v:474.12-474.66"
wire width 22 \main_sdram_bankmachine0_cmd_buffer_source_payload_addr
- attribute \src "ls180.v:477.5-477.57"
+ attribute \src "ls180.v:473.5-473.57"
wire \main_sdram_bankmachine0_cmd_buffer_source_payload_we
- attribute \src "ls180.v:474.6-474.53"
+ attribute \src "ls180.v:470.6-470.53"
wire \main_sdram_bankmachine0_cmd_buffer_source_ready
- attribute \src "ls180.v:473.5-473.52"
+ attribute \src "ls180.v:469.5-469.52"
wire \main_sdram_bankmachine0_cmd_buffer_source_valid
- attribute \src "ls180.v:421.12-421.49"
+ attribute \src "ls180.v:417.12-417.49"
wire width 13 \main_sdram_bankmachine0_cmd_payload_a
- attribute \src "ls180.v:422.12-422.50"
+ attribute \src "ls180.v:418.12-418.50"
wire width 2 \main_sdram_bankmachine0_cmd_payload_ba
- attribute \src "ls180.v:423.5-423.44"
+ attribute \src "ls180.v:419.5-419.44"
wire \main_sdram_bankmachine0_cmd_payload_cas
- attribute \src "ls180.v:426.5-426.47"
+ attribute \src "ls180.v:422.5-422.47"
wire \main_sdram_bankmachine0_cmd_payload_is_cmd
- attribute \src "ls180.v:427.5-427.48"
+ attribute \src "ls180.v:423.5-423.48"
wire \main_sdram_bankmachine0_cmd_payload_is_read
- attribute \src "ls180.v:428.5-428.49"
+ attribute \src "ls180.v:424.5-424.49"
wire \main_sdram_bankmachine0_cmd_payload_is_write
- attribute \src "ls180.v:424.5-424.44"
+ attribute \src "ls180.v:420.5-420.44"
wire \main_sdram_bankmachine0_cmd_payload_ras
- attribute \src "ls180.v:425.5-425.43"
+ attribute \src "ls180.v:421.5-421.43"
wire \main_sdram_bankmachine0_cmd_payload_we
- attribute \src "ls180.v:420.5-420.38"
+ attribute \src "ls180.v:416.5-416.38"
wire \main_sdram_bankmachine0_cmd_ready
- attribute \src "ls180.v:419.5-419.38"
+ attribute \src "ls180.v:415.5-415.38"
wire \main_sdram_bankmachine0_cmd_valid
- attribute \src "ls180.v:418.5-418.40"
+ attribute \src "ls180.v:414.5-414.40"
wire \main_sdram_bankmachine0_refresh_gnt
- attribute \src "ls180.v:417.6-417.41"
+ attribute \src "ls180.v:413.6-413.41"
wire \main_sdram_bankmachine0_refresh_req
- attribute \src "ls180.v:413.13-413.45"
+ attribute \src "ls180.v:409.13-409.45"
wire width 22 \main_sdram_bankmachine0_req_addr
- attribute \src "ls180.v:414.6-414.38"
+ attribute \src "ls180.v:410.6-410.38"
wire \main_sdram_bankmachine0_req_lock
- attribute \src "ls180.v:416.5-416.44"
+ attribute \src "ls180.v:412.5-412.44"
wire \main_sdram_bankmachine0_req_rdata_valid
- attribute \src "ls180.v:411.6-411.39"
+ attribute \src "ls180.v:407.6-407.39"
wire \main_sdram_bankmachine0_req_ready
- attribute \src "ls180.v:410.6-410.39"
+ attribute \src "ls180.v:406.6-406.39"
wire \main_sdram_bankmachine0_req_valid
- attribute \src "ls180.v:415.5-415.44"
+ attribute \src "ls180.v:411.5-411.44"
wire \main_sdram_bankmachine0_req_wdata_ready
- attribute \src "ls180.v:412.6-412.36"
+ attribute \src "ls180.v:408.6-408.36"
wire \main_sdram_bankmachine0_req_we
- attribute \src "ls180.v:479.12-479.39"
+ attribute \src "ls180.v:475.12-475.39"
wire width 13 \main_sdram_bankmachine0_row
- attribute \src "ls180.v:483.5-483.38"
+ attribute \src "ls180.v:479.5-479.38"
wire \main_sdram_bankmachine0_row_close
- attribute \src "ls180.v:484.5-484.47"
+ attribute \src "ls180.v:480.5-480.47"
wire \main_sdram_bankmachine0_row_col_n_addr_sel
- attribute \src "ls180.v:481.6-481.37"
+ attribute \src "ls180.v:477.6-477.37"
wire \main_sdram_bankmachine0_row_hit
- attribute \src "ls180.v:482.5-482.37"
+ attribute \src "ls180.v:478.5-478.37"
wire \main_sdram_bankmachine0_row_open
- attribute \src "ls180.v:480.5-480.39"
+ attribute \src "ls180.v:476.5-476.39"
wire \main_sdram_bankmachine0_row_opened
attribute \no_retiming "true"
- attribute \src "ls180.v:491.32-491.69"
+ attribute \src "ls180.v:487.32-487.69"
wire \main_sdram_bankmachine0_trascon_ready
- attribute \src "ls180.v:490.6-490.43"
+ attribute \src "ls180.v:486.6-486.43"
wire \main_sdram_bankmachine0_trascon_valid
attribute \no_retiming "true"
- attribute \src "ls180.v:489.32-489.68"
+ attribute \src "ls180.v:485.32-485.68"
wire \main_sdram_bankmachine0_trccon_ready
- attribute \src "ls180.v:488.6-488.42"
+ attribute \src "ls180.v:484.6-484.42"
wire \main_sdram_bankmachine0_trccon_valid
- attribute \src "ls180.v:487.11-487.48"
+ attribute \src "ls180.v:483.11-483.48"
wire width 3 \main_sdram_bankmachine0_twtpcon_count
attribute \no_retiming "true"
- attribute \src "ls180.v:486.32-486.69"
+ attribute \src "ls180.v:482.32-482.69"
wire \main_sdram_bankmachine0_twtpcon_ready
- attribute \src "ls180.v:485.6-485.43"
+ attribute \src "ls180.v:481.6-481.43"
wire \main_sdram_bankmachine0_twtpcon_valid
- attribute \src "ls180.v:511.5-511.43"
+ attribute \src "ls180.v:507.5-507.43"
wire \main_sdram_bankmachine1_auto_precharge
- attribute \src "ls180.v:533.11-533.63"
+ attribute \src "ls180.v:529.11-529.63"
wire width 3 \main_sdram_bankmachine1_cmd_buffer_lookahead_consume
- attribute \src "ls180.v:538.6-538.58"
+ attribute \src "ls180.v:534.6-534.58"
wire \main_sdram_bankmachine1_cmd_buffer_lookahead_do_read
- attribute \src "ls180.v:543.6-543.64"
+ attribute \src "ls180.v:539.6-539.64"
wire \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_first
- attribute \src "ls180.v:544.6-544.63"
+ attribute \src "ls180.v:540.6-540.63"
wire \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_last
- attribute \src "ls180.v:542.13-542.78"
+ attribute \src "ls180.v:538.13-538.78"
wire width 22 \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr
- attribute \src "ls180.v:541.6-541.69"
+ attribute \src "ls180.v:537.6-537.69"
wire \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we
- attribute \src "ls180.v:547.6-547.65"
+ attribute \src "ls180.v:543.6-543.65"
wire \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first
- attribute \src "ls180.v:548.6-548.64"
+ attribute \src "ls180.v:544.6-544.64"
wire \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last
- attribute \src "ls180.v:546.13-546.79"
+ attribute \src "ls180.v:542.13-542.79"
wire width 22 \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr
- attribute \src "ls180.v:545.6-545.70"
+ attribute \src "ls180.v:541.6-541.70"
wire \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we
- attribute \src "ls180.v:530.11-530.61"
+ attribute \src "ls180.v:526.11-526.61"
wire width 4 \main_sdram_bankmachine1_cmd_buffer_lookahead_level
- attribute \src "ls180.v:532.11-532.63"
+ attribute \src "ls180.v:528.11-528.63"
wire width 3 \main_sdram_bankmachine1_cmd_buffer_lookahead_produce
- attribute \src "ls180.v:539.12-539.67"
+ attribute \src "ls180.v:535.12-535.67"
wire width 3 \main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_adr
- attribute \src "ls180.v:540.13-540.70"
+ attribute \src "ls180.v:536.13-536.70"
wire width 25 \main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r
- attribute \src "ls180.v:531.5-531.57"
+ attribute \src "ls180.v:527.5-527.57"
wire \main_sdram_bankmachine1_cmd_buffer_lookahead_replace
- attribute \src "ls180.v:514.5-514.60"
+ attribute \src "ls180.v:510.5-510.60"
wire \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first
- attribute \src "ls180.v:515.5-515.59"
+ attribute \src "ls180.v:511.5-511.59"
wire \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last
- attribute \src "ls180.v:517.13-517.75"
+ attribute \src "ls180.v:513.13-513.75"
wire width 22 \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_addr
- attribute \src "ls180.v:516.6-516.66"
+ attribute \src "ls180.v:512.6-512.66"
wire \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_we
- attribute \src "ls180.v:513.6-513.61"
+ attribute \src "ls180.v:509.6-509.61"
wire \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_ready
- attribute \src "ls180.v:512.6-512.61"
+ attribute \src "ls180.v:508.6-508.61"
wire \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_valid
- attribute \src "ls180.v:520.6-520.63"
+ attribute \src "ls180.v:516.6-516.63"
wire \main_sdram_bankmachine1_cmd_buffer_lookahead_source_first
- attribute \src "ls180.v:521.6-521.62"
+ attribute \src "ls180.v:517.6-517.62"
wire \main_sdram_bankmachine1_cmd_buffer_lookahead_source_last
- attribute \src "ls180.v:523.13-523.77"
+ attribute \src "ls180.v:519.13-519.77"
wire width 22 \main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr
- attribute \src "ls180.v:522.6-522.68"
+ attribute \src "ls180.v:518.6-518.68"
wire \main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_we
- attribute \src "ls180.v:519.6-519.63"
+ attribute \src "ls180.v:515.6-515.63"
wire \main_sdram_bankmachine1_cmd_buffer_lookahead_source_ready
- attribute \src "ls180.v:518.6-518.63"
+ attribute \src "ls180.v:514.6-514.63"
wire \main_sdram_bankmachine1_cmd_buffer_lookahead_source_valid
- attribute \src "ls180.v:528.13-528.71"
+ attribute \src "ls180.v:524.13-524.71"
wire width 25 \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_din
- attribute \src "ls180.v:529.13-529.72"
+ attribute \src "ls180.v:525.13-525.72"
wire width 25 \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout
- attribute \src "ls180.v:526.6-526.63"
+ attribute \src "ls180.v:522.6-522.63"
wire \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_re
- attribute \src "ls180.v:527.6-527.69"
+ attribute \src "ls180.v:523.6-523.69"
wire \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable
- attribute \src "ls180.v:524.6-524.63"
+ attribute \src "ls180.v:520.6-520.63"
wire \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we
- attribute \src "ls180.v:525.6-525.69"
+ attribute \src "ls180.v:521.6-521.69"
wire \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable
- attribute \src "ls180.v:534.11-534.66"
+ attribute \src "ls180.v:530.11-530.66"
wire width 3 \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr
- attribute \src "ls180.v:535.13-535.70"
+ attribute \src "ls180.v:531.13-531.70"
wire width 25 \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_r
- attribute \src "ls180.v:537.13-537.70"
+ attribute \src "ls180.v:533.13-533.70"
wire width 25 \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w
- attribute \src "ls180.v:536.6-536.60"
+ attribute \src "ls180.v:532.6-532.60"
wire \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_we
- attribute \src "ls180.v:551.6-551.51"
+ attribute \src "ls180.v:547.6-547.51"
wire \main_sdram_bankmachine1_cmd_buffer_sink_first
- attribute \src "ls180.v:552.6-552.50"
+ attribute \src "ls180.v:548.6-548.50"
wire \main_sdram_bankmachine1_cmd_buffer_sink_last
- attribute \src "ls180.v:554.13-554.65"
+ attribute \src "ls180.v:550.13-550.65"
wire width 22 \main_sdram_bankmachine1_cmd_buffer_sink_payload_addr
- attribute \src "ls180.v:553.6-553.56"
+ attribute \src "ls180.v:549.6-549.56"
wire \main_sdram_bankmachine1_cmd_buffer_sink_payload_we
- attribute \src "ls180.v:550.6-550.51"
+ attribute \src "ls180.v:546.6-546.51"
wire \main_sdram_bankmachine1_cmd_buffer_sink_ready
- attribute \src "ls180.v:549.6-549.51"
+ attribute \src "ls180.v:545.6-545.51"
wire \main_sdram_bankmachine1_cmd_buffer_sink_valid
- attribute \src "ls180.v:557.5-557.52"
+ attribute \src "ls180.v:553.5-553.52"
wire \main_sdram_bankmachine1_cmd_buffer_source_first
- attribute \src "ls180.v:558.5-558.51"
+ attribute \src "ls180.v:554.5-554.51"
wire \main_sdram_bankmachine1_cmd_buffer_source_last
- attribute \src "ls180.v:560.12-560.66"
+ attribute \src "ls180.v:556.12-556.66"
wire width 22 \main_sdram_bankmachine1_cmd_buffer_source_payload_addr
- attribute \src "ls180.v:559.5-559.57"
+ attribute \src "ls180.v:555.5-555.57"
wire \main_sdram_bankmachine1_cmd_buffer_source_payload_we
- attribute \src "ls180.v:556.6-556.53"
+ attribute \src "ls180.v:552.6-552.53"
wire \main_sdram_bankmachine1_cmd_buffer_source_ready
- attribute \src "ls180.v:555.5-555.52"
+ attribute \src "ls180.v:551.5-551.52"
wire \main_sdram_bankmachine1_cmd_buffer_source_valid
- attribute \src "ls180.v:503.12-503.49"
+ attribute \src "ls180.v:499.12-499.49"
wire width 13 \main_sdram_bankmachine1_cmd_payload_a
- attribute \src "ls180.v:504.12-504.50"
+ attribute \src "ls180.v:500.12-500.50"
wire width 2 \main_sdram_bankmachine1_cmd_payload_ba
- attribute \src "ls180.v:505.5-505.44"
+ attribute \src "ls180.v:501.5-501.44"
wire \main_sdram_bankmachine1_cmd_payload_cas
- attribute \src "ls180.v:508.5-508.47"
+ attribute \src "ls180.v:504.5-504.47"
wire \main_sdram_bankmachine1_cmd_payload_is_cmd
- attribute \src "ls180.v:509.5-509.48"
+ attribute \src "ls180.v:505.5-505.48"
wire \main_sdram_bankmachine1_cmd_payload_is_read
- attribute \src "ls180.v:510.5-510.49"
+ attribute \src "ls180.v:506.5-506.49"
wire \main_sdram_bankmachine1_cmd_payload_is_write
- attribute \src "ls180.v:506.5-506.44"
+ attribute \src "ls180.v:502.5-502.44"
wire \main_sdram_bankmachine1_cmd_payload_ras
- attribute \src "ls180.v:507.5-507.43"
+ attribute \src "ls180.v:503.5-503.43"
wire \main_sdram_bankmachine1_cmd_payload_we
- attribute \src "ls180.v:502.5-502.38"
+ attribute \src "ls180.v:498.5-498.38"
wire \main_sdram_bankmachine1_cmd_ready
- attribute \src "ls180.v:501.5-501.38"
+ attribute \src "ls180.v:497.5-497.38"
wire \main_sdram_bankmachine1_cmd_valid
- attribute \src "ls180.v:500.5-500.40"
+ attribute \src "ls180.v:496.5-496.40"
wire \main_sdram_bankmachine1_refresh_gnt
- attribute \src "ls180.v:499.6-499.41"
+ attribute \src "ls180.v:495.6-495.41"
wire \main_sdram_bankmachine1_refresh_req
- attribute \src "ls180.v:495.13-495.45"
+ attribute \src "ls180.v:491.13-491.45"
wire width 22 \main_sdram_bankmachine1_req_addr
- attribute \src "ls180.v:496.6-496.38"
+ attribute \src "ls180.v:492.6-492.38"
wire \main_sdram_bankmachine1_req_lock
- attribute \src "ls180.v:498.5-498.44"
+ attribute \src "ls180.v:494.5-494.44"
wire \main_sdram_bankmachine1_req_rdata_valid
- attribute \src "ls180.v:493.6-493.39"
+ attribute \src "ls180.v:489.6-489.39"
wire \main_sdram_bankmachine1_req_ready
- attribute \src "ls180.v:492.6-492.39"
+ attribute \src "ls180.v:488.6-488.39"
wire \main_sdram_bankmachine1_req_valid
- attribute \src "ls180.v:497.5-497.44"
+ attribute \src "ls180.v:493.5-493.44"
wire \main_sdram_bankmachine1_req_wdata_ready
- attribute \src "ls180.v:494.6-494.36"
+ attribute \src "ls180.v:490.6-490.36"
wire \main_sdram_bankmachine1_req_we
- attribute \src "ls180.v:561.12-561.39"
+ attribute \src "ls180.v:557.12-557.39"
wire width 13 \main_sdram_bankmachine1_row
- attribute \src "ls180.v:565.5-565.38"
+ attribute \src "ls180.v:561.5-561.38"
wire \main_sdram_bankmachine1_row_close
- attribute \src "ls180.v:566.5-566.47"
+ attribute \src "ls180.v:562.5-562.47"
wire \main_sdram_bankmachine1_row_col_n_addr_sel
- attribute \src "ls180.v:563.6-563.37"
+ attribute \src "ls180.v:559.6-559.37"
wire \main_sdram_bankmachine1_row_hit
- attribute \src "ls180.v:564.5-564.37"
+ attribute \src "ls180.v:560.5-560.37"
wire \main_sdram_bankmachine1_row_open
- attribute \src "ls180.v:562.5-562.39"
+ attribute \src "ls180.v:558.5-558.39"
wire \main_sdram_bankmachine1_row_opened
attribute \no_retiming "true"
- attribute \src "ls180.v:573.32-573.69"
+ attribute \src "ls180.v:569.32-569.69"
wire \main_sdram_bankmachine1_trascon_ready
- attribute \src "ls180.v:572.6-572.43"
+ attribute \src "ls180.v:568.6-568.43"
wire \main_sdram_bankmachine1_trascon_valid
attribute \no_retiming "true"
- attribute \src "ls180.v:571.32-571.68"
+ attribute \src "ls180.v:567.32-567.68"
wire \main_sdram_bankmachine1_trccon_ready
- attribute \src "ls180.v:570.6-570.42"
+ attribute \src "ls180.v:566.6-566.42"
wire \main_sdram_bankmachine1_trccon_valid
- attribute \src "ls180.v:569.11-569.48"
+ attribute \src "ls180.v:565.11-565.48"
wire width 3 \main_sdram_bankmachine1_twtpcon_count
attribute \no_retiming "true"
- attribute \src "ls180.v:568.32-568.69"
+ attribute \src "ls180.v:564.32-564.69"
wire \main_sdram_bankmachine1_twtpcon_ready
- attribute \src "ls180.v:567.6-567.43"
+ attribute \src "ls180.v:563.6-563.43"
wire \main_sdram_bankmachine1_twtpcon_valid
- attribute \src "ls180.v:593.5-593.43"
+ attribute \src "ls180.v:589.5-589.43"
wire \main_sdram_bankmachine2_auto_precharge
- attribute \src "ls180.v:615.11-615.63"
+ attribute \src "ls180.v:611.11-611.63"
wire width 3 \main_sdram_bankmachine2_cmd_buffer_lookahead_consume
- attribute \src "ls180.v:620.6-620.58"
+ attribute \src "ls180.v:616.6-616.58"
wire \main_sdram_bankmachine2_cmd_buffer_lookahead_do_read
- attribute \src "ls180.v:625.6-625.64"
+ attribute \src "ls180.v:621.6-621.64"
wire \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_first
- attribute \src "ls180.v:626.6-626.63"
+ attribute \src "ls180.v:622.6-622.63"
wire \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_last
- attribute \src "ls180.v:624.13-624.78"
+ attribute \src "ls180.v:620.13-620.78"
wire width 22 \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr
- attribute \src "ls180.v:623.6-623.69"
+ attribute \src "ls180.v:619.6-619.69"
wire \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we
- attribute \src "ls180.v:629.6-629.65"
+ attribute \src "ls180.v:625.6-625.65"
wire \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first
- attribute \src "ls180.v:630.6-630.64"
+ attribute \src "ls180.v:626.6-626.64"
wire \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last
- attribute \src "ls180.v:628.13-628.79"
+ attribute \src "ls180.v:624.13-624.79"
wire width 22 \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr
- attribute \src "ls180.v:627.6-627.70"
+ attribute \src "ls180.v:623.6-623.70"
wire \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we
- attribute \src "ls180.v:612.11-612.61"
+ attribute \src "ls180.v:608.11-608.61"
wire width 4 \main_sdram_bankmachine2_cmd_buffer_lookahead_level
- attribute \src "ls180.v:614.11-614.63"
+ attribute \src "ls180.v:610.11-610.63"
wire width 3 \main_sdram_bankmachine2_cmd_buffer_lookahead_produce
- attribute \src "ls180.v:621.12-621.67"
+ attribute \src "ls180.v:617.12-617.67"
wire width 3 \main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_adr
- attribute \src "ls180.v:622.13-622.70"
+ attribute \src "ls180.v:618.13-618.70"
wire width 25 \main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r
- attribute \src "ls180.v:613.5-613.57"
+ attribute \src "ls180.v:609.5-609.57"
wire \main_sdram_bankmachine2_cmd_buffer_lookahead_replace
- attribute \src "ls180.v:596.5-596.60"
+ attribute \src "ls180.v:592.5-592.60"
wire \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first
- attribute \src "ls180.v:597.5-597.59"
+ attribute \src "ls180.v:593.5-593.59"
wire \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last
- attribute \src "ls180.v:599.13-599.75"
+ attribute \src "ls180.v:595.13-595.75"
wire width 22 \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_addr
- attribute \src "ls180.v:598.6-598.66"
+ attribute \src "ls180.v:594.6-594.66"
wire \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_we
- attribute \src "ls180.v:595.6-595.61"
+ attribute \src "ls180.v:591.6-591.61"
wire \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_ready
- attribute \src "ls180.v:594.6-594.61"
+ attribute \src "ls180.v:590.6-590.61"
wire \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_valid
- attribute \src "ls180.v:602.6-602.63"
+ attribute \src "ls180.v:598.6-598.63"
wire \main_sdram_bankmachine2_cmd_buffer_lookahead_source_first
- attribute \src "ls180.v:603.6-603.62"
+ attribute \src "ls180.v:599.6-599.62"
wire \main_sdram_bankmachine2_cmd_buffer_lookahead_source_last
- attribute \src "ls180.v:605.13-605.77"
+ attribute \src "ls180.v:601.13-601.77"
wire width 22 \main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr
- attribute \src "ls180.v:604.6-604.68"
+ attribute \src "ls180.v:600.6-600.68"
wire \main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_we
- attribute \src "ls180.v:601.6-601.63"
+ attribute \src "ls180.v:597.6-597.63"
wire \main_sdram_bankmachine2_cmd_buffer_lookahead_source_ready
- attribute \src "ls180.v:600.6-600.63"
+ attribute \src "ls180.v:596.6-596.63"
wire \main_sdram_bankmachine2_cmd_buffer_lookahead_source_valid
- attribute \src "ls180.v:610.13-610.71"
+ attribute \src "ls180.v:606.13-606.71"
wire width 25 \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_din
- attribute \src "ls180.v:611.13-611.72"
+ attribute \src "ls180.v:607.13-607.72"
wire width 25 \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout
- attribute \src "ls180.v:608.6-608.63"
+ attribute \src "ls180.v:604.6-604.63"
wire \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_re
- attribute \src "ls180.v:609.6-609.69"
+ attribute \src "ls180.v:605.6-605.69"
wire \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable
- attribute \src "ls180.v:606.6-606.63"
+ attribute \src "ls180.v:602.6-602.63"
wire \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we
- attribute \src "ls180.v:607.6-607.69"
+ attribute \src "ls180.v:603.6-603.69"
wire \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable
- attribute \src "ls180.v:616.11-616.66"
+ attribute \src "ls180.v:612.11-612.66"
wire width 3 \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr
- attribute \src "ls180.v:617.13-617.70"
+ attribute \src "ls180.v:613.13-613.70"
wire width 25 \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_r
- attribute \src "ls180.v:619.13-619.70"
+ attribute \src "ls180.v:615.13-615.70"
wire width 25 \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w
- attribute \src "ls180.v:618.6-618.60"
+ attribute \src "ls180.v:614.6-614.60"
wire \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_we
- attribute \src "ls180.v:633.6-633.51"
+ attribute \src "ls180.v:629.6-629.51"
wire \main_sdram_bankmachine2_cmd_buffer_sink_first
- attribute \src "ls180.v:634.6-634.50"
+ attribute \src "ls180.v:630.6-630.50"
wire \main_sdram_bankmachine2_cmd_buffer_sink_last
- attribute \src "ls180.v:636.13-636.65"
+ attribute \src "ls180.v:632.13-632.65"
wire width 22 \main_sdram_bankmachine2_cmd_buffer_sink_payload_addr
- attribute \src "ls180.v:635.6-635.56"
+ attribute \src "ls180.v:631.6-631.56"
wire \main_sdram_bankmachine2_cmd_buffer_sink_payload_we
- attribute \src "ls180.v:632.6-632.51"
+ attribute \src "ls180.v:628.6-628.51"
wire \main_sdram_bankmachine2_cmd_buffer_sink_ready
- attribute \src "ls180.v:631.6-631.51"
+ attribute \src "ls180.v:627.6-627.51"
wire \main_sdram_bankmachine2_cmd_buffer_sink_valid
- attribute \src "ls180.v:639.5-639.52"
+ attribute \src "ls180.v:635.5-635.52"
wire \main_sdram_bankmachine2_cmd_buffer_source_first
- attribute \src "ls180.v:640.5-640.51"
+ attribute \src "ls180.v:636.5-636.51"
wire \main_sdram_bankmachine2_cmd_buffer_source_last
- attribute \src "ls180.v:642.12-642.66"
+ attribute \src "ls180.v:638.12-638.66"
wire width 22 \main_sdram_bankmachine2_cmd_buffer_source_payload_addr
- attribute \src "ls180.v:641.5-641.57"
+ attribute \src "ls180.v:637.5-637.57"
wire \main_sdram_bankmachine2_cmd_buffer_source_payload_we
- attribute \src "ls180.v:638.6-638.53"
+ attribute \src "ls180.v:634.6-634.53"
wire \main_sdram_bankmachine2_cmd_buffer_source_ready
- attribute \src "ls180.v:637.5-637.52"
+ attribute \src "ls180.v:633.5-633.52"
wire \main_sdram_bankmachine2_cmd_buffer_source_valid
- attribute \src "ls180.v:585.12-585.49"
+ attribute \src "ls180.v:581.12-581.49"
wire width 13 \main_sdram_bankmachine2_cmd_payload_a
- attribute \src "ls180.v:586.12-586.50"
+ attribute \src "ls180.v:582.12-582.50"
wire width 2 \main_sdram_bankmachine2_cmd_payload_ba
- attribute \src "ls180.v:587.5-587.44"
+ attribute \src "ls180.v:583.5-583.44"
wire \main_sdram_bankmachine2_cmd_payload_cas
- attribute \src "ls180.v:590.5-590.47"
+ attribute \src "ls180.v:586.5-586.47"
wire \main_sdram_bankmachine2_cmd_payload_is_cmd
- attribute \src "ls180.v:591.5-591.48"
+ attribute \src "ls180.v:587.5-587.48"
wire \main_sdram_bankmachine2_cmd_payload_is_read
- attribute \src "ls180.v:592.5-592.49"
+ attribute \src "ls180.v:588.5-588.49"
wire \main_sdram_bankmachine2_cmd_payload_is_write
- attribute \src "ls180.v:588.5-588.44"
+ attribute \src "ls180.v:584.5-584.44"
wire \main_sdram_bankmachine2_cmd_payload_ras
- attribute \src "ls180.v:589.5-589.43"
+ attribute \src "ls180.v:585.5-585.43"
wire \main_sdram_bankmachine2_cmd_payload_we
- attribute \src "ls180.v:584.5-584.38"
+ attribute \src "ls180.v:580.5-580.38"
wire \main_sdram_bankmachine2_cmd_ready
- attribute \src "ls180.v:583.5-583.38"
+ attribute \src "ls180.v:579.5-579.38"
wire \main_sdram_bankmachine2_cmd_valid
- attribute \src "ls180.v:582.5-582.40"
+ attribute \src "ls180.v:578.5-578.40"
wire \main_sdram_bankmachine2_refresh_gnt
- attribute \src "ls180.v:581.6-581.41"
+ attribute \src "ls180.v:577.6-577.41"
wire \main_sdram_bankmachine2_refresh_req
- attribute \src "ls180.v:577.13-577.45"
+ attribute \src "ls180.v:573.13-573.45"
wire width 22 \main_sdram_bankmachine2_req_addr
- attribute \src "ls180.v:578.6-578.38"
+ attribute \src "ls180.v:574.6-574.38"
wire \main_sdram_bankmachine2_req_lock
- attribute \src "ls180.v:580.5-580.44"
+ attribute \src "ls180.v:576.5-576.44"
wire \main_sdram_bankmachine2_req_rdata_valid
- attribute \src "ls180.v:575.6-575.39"
+ attribute \src "ls180.v:571.6-571.39"
wire \main_sdram_bankmachine2_req_ready
- attribute \src "ls180.v:574.6-574.39"
+ attribute \src "ls180.v:570.6-570.39"
wire \main_sdram_bankmachine2_req_valid
- attribute \src "ls180.v:579.5-579.44"
+ attribute \src "ls180.v:575.5-575.44"
wire \main_sdram_bankmachine2_req_wdata_ready
- attribute \src "ls180.v:576.6-576.36"
+ attribute \src "ls180.v:572.6-572.36"
wire \main_sdram_bankmachine2_req_we
- attribute \src "ls180.v:643.12-643.39"
+ attribute \src "ls180.v:639.12-639.39"
wire width 13 \main_sdram_bankmachine2_row
- attribute \src "ls180.v:647.5-647.38"
+ attribute \src "ls180.v:643.5-643.38"
wire \main_sdram_bankmachine2_row_close
- attribute \src "ls180.v:648.5-648.47"
+ attribute \src "ls180.v:644.5-644.47"
wire \main_sdram_bankmachine2_row_col_n_addr_sel
- attribute \src "ls180.v:645.6-645.37"
+ attribute \src "ls180.v:641.6-641.37"
wire \main_sdram_bankmachine2_row_hit
- attribute \src "ls180.v:646.5-646.37"
+ attribute \src "ls180.v:642.5-642.37"
wire \main_sdram_bankmachine2_row_open
- attribute \src "ls180.v:644.5-644.39"
+ attribute \src "ls180.v:640.5-640.39"
wire \main_sdram_bankmachine2_row_opened
attribute \no_retiming "true"
- attribute \src "ls180.v:655.32-655.69"
+ attribute \src "ls180.v:651.32-651.69"
wire \main_sdram_bankmachine2_trascon_ready
- attribute \src "ls180.v:654.6-654.43"
+ attribute \src "ls180.v:650.6-650.43"
wire \main_sdram_bankmachine2_trascon_valid
attribute \no_retiming "true"
- attribute \src "ls180.v:653.32-653.68"
+ attribute \src "ls180.v:649.32-649.68"
wire \main_sdram_bankmachine2_trccon_ready
- attribute \src "ls180.v:652.6-652.42"
+ attribute \src "ls180.v:648.6-648.42"
wire \main_sdram_bankmachine2_trccon_valid
- attribute \src "ls180.v:651.11-651.48"
+ attribute \src "ls180.v:647.11-647.48"
wire width 3 \main_sdram_bankmachine2_twtpcon_count
attribute \no_retiming "true"
- attribute \src "ls180.v:650.32-650.69"
+ attribute \src "ls180.v:646.32-646.69"
wire \main_sdram_bankmachine2_twtpcon_ready
- attribute \src "ls180.v:649.6-649.43"
+ attribute \src "ls180.v:645.6-645.43"
wire \main_sdram_bankmachine2_twtpcon_valid
- attribute \src "ls180.v:675.5-675.43"
+ attribute \src "ls180.v:671.5-671.43"
wire \main_sdram_bankmachine3_auto_precharge
- attribute \src "ls180.v:697.11-697.63"
+ attribute \src "ls180.v:693.11-693.63"
wire width 3 \main_sdram_bankmachine3_cmd_buffer_lookahead_consume
- attribute \src "ls180.v:702.6-702.58"
+ attribute \src "ls180.v:698.6-698.58"
wire \main_sdram_bankmachine3_cmd_buffer_lookahead_do_read
- attribute \src "ls180.v:707.6-707.64"
+ attribute \src "ls180.v:703.6-703.64"
wire \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_first
- attribute \src "ls180.v:708.6-708.63"
+ attribute \src "ls180.v:704.6-704.63"
wire \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_last
- attribute \src "ls180.v:706.13-706.78"
+ attribute \src "ls180.v:702.13-702.78"
wire width 22 \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr
- attribute \src "ls180.v:705.6-705.69"
+ attribute \src "ls180.v:701.6-701.69"
wire \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we
- attribute \src "ls180.v:711.6-711.65"
+ attribute \src "ls180.v:707.6-707.65"
wire \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first
- attribute \src "ls180.v:712.6-712.64"
+ attribute \src "ls180.v:708.6-708.64"
wire \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last
- attribute \src "ls180.v:710.13-710.79"
+ attribute \src "ls180.v:706.13-706.79"
wire width 22 \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr
- attribute \src "ls180.v:709.6-709.70"
+ attribute \src "ls180.v:705.6-705.70"
wire \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we
- attribute \src "ls180.v:694.11-694.61"
+ attribute \src "ls180.v:690.11-690.61"
wire width 4 \main_sdram_bankmachine3_cmd_buffer_lookahead_level
- attribute \src "ls180.v:696.11-696.63"
+ attribute \src "ls180.v:692.11-692.63"
wire width 3 \main_sdram_bankmachine3_cmd_buffer_lookahead_produce
- attribute \src "ls180.v:703.12-703.67"
+ attribute \src "ls180.v:699.12-699.67"
wire width 3 \main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_adr
- attribute \src "ls180.v:704.13-704.70"
+ attribute \src "ls180.v:700.13-700.70"
wire width 25 \main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r
- attribute \src "ls180.v:695.5-695.57"
+ attribute \src "ls180.v:691.5-691.57"
wire \main_sdram_bankmachine3_cmd_buffer_lookahead_replace
- attribute \src "ls180.v:678.5-678.60"
+ attribute \src "ls180.v:674.5-674.60"
wire \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first
- attribute \src "ls180.v:679.5-679.59"
+ attribute \src "ls180.v:675.5-675.59"
wire \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last
- attribute \src "ls180.v:681.13-681.75"
+ attribute \src "ls180.v:677.13-677.75"
wire width 22 \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_addr
- attribute \src "ls180.v:680.6-680.66"
+ attribute \src "ls180.v:676.6-676.66"
wire \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_we
- attribute \src "ls180.v:677.6-677.61"
+ attribute \src "ls180.v:673.6-673.61"
wire \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_ready
- attribute \src "ls180.v:676.6-676.61"
+ attribute \src "ls180.v:672.6-672.61"
wire \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_valid
- attribute \src "ls180.v:684.6-684.63"
+ attribute \src "ls180.v:680.6-680.63"
wire \main_sdram_bankmachine3_cmd_buffer_lookahead_source_first
- attribute \src "ls180.v:685.6-685.62"
+ attribute \src "ls180.v:681.6-681.62"
wire \main_sdram_bankmachine3_cmd_buffer_lookahead_source_last
- attribute \src "ls180.v:687.13-687.77"
+ attribute \src "ls180.v:683.13-683.77"
wire width 22 \main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr
- attribute \src "ls180.v:686.6-686.68"
+ attribute \src "ls180.v:682.6-682.68"
wire \main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_we
- attribute \src "ls180.v:683.6-683.63"
+ attribute \src "ls180.v:679.6-679.63"
wire \main_sdram_bankmachine3_cmd_buffer_lookahead_source_ready
- attribute \src "ls180.v:682.6-682.63"
+ attribute \src "ls180.v:678.6-678.63"
wire \main_sdram_bankmachine3_cmd_buffer_lookahead_source_valid
- attribute \src "ls180.v:692.13-692.71"
+ attribute \src "ls180.v:688.13-688.71"
wire width 25 \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_din
- attribute \src "ls180.v:693.13-693.72"
+ attribute \src "ls180.v:689.13-689.72"
wire width 25 \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout
- attribute \src "ls180.v:690.6-690.63"
+ attribute \src "ls180.v:686.6-686.63"
wire \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_re
- attribute \src "ls180.v:691.6-691.69"
+ attribute \src "ls180.v:687.6-687.69"
wire \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable
- attribute \src "ls180.v:688.6-688.63"
+ attribute \src "ls180.v:684.6-684.63"
wire \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we
- attribute \src "ls180.v:689.6-689.69"
+ attribute \src "ls180.v:685.6-685.69"
wire \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable
- attribute \src "ls180.v:698.11-698.66"
+ attribute \src "ls180.v:694.11-694.66"
wire width 3 \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr
- attribute \src "ls180.v:699.13-699.70"
+ attribute \src "ls180.v:695.13-695.70"
wire width 25 \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_r
- attribute \src "ls180.v:701.13-701.70"
+ attribute \src "ls180.v:697.13-697.70"
wire width 25 \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w
- attribute \src "ls180.v:700.6-700.60"
+ attribute \src "ls180.v:696.6-696.60"
wire \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_we
- attribute \src "ls180.v:715.6-715.51"
+ attribute \src "ls180.v:711.6-711.51"
wire \main_sdram_bankmachine3_cmd_buffer_sink_first
- attribute \src "ls180.v:716.6-716.50"
+ attribute \src "ls180.v:712.6-712.50"
wire \main_sdram_bankmachine3_cmd_buffer_sink_last
- attribute \src "ls180.v:718.13-718.65"
+ attribute \src "ls180.v:714.13-714.65"
wire width 22 \main_sdram_bankmachine3_cmd_buffer_sink_payload_addr
- attribute \src "ls180.v:717.6-717.56"
+ attribute \src "ls180.v:713.6-713.56"
wire \main_sdram_bankmachine3_cmd_buffer_sink_payload_we
- attribute \src "ls180.v:714.6-714.51"
+ attribute \src "ls180.v:710.6-710.51"
wire \main_sdram_bankmachine3_cmd_buffer_sink_ready
- attribute \src "ls180.v:713.6-713.51"
+ attribute \src "ls180.v:709.6-709.51"
wire \main_sdram_bankmachine3_cmd_buffer_sink_valid
- attribute \src "ls180.v:721.5-721.52"
+ attribute \src "ls180.v:717.5-717.52"
wire \main_sdram_bankmachine3_cmd_buffer_source_first
- attribute \src "ls180.v:722.5-722.51"
+ attribute \src "ls180.v:718.5-718.51"
wire \main_sdram_bankmachine3_cmd_buffer_source_last
- attribute \src "ls180.v:724.12-724.66"
+ attribute \src "ls180.v:720.12-720.66"
wire width 22 \main_sdram_bankmachine3_cmd_buffer_source_payload_addr
- attribute \src "ls180.v:723.5-723.57"
+ attribute \src "ls180.v:719.5-719.57"
wire \main_sdram_bankmachine3_cmd_buffer_source_payload_we
- attribute \src "ls180.v:720.6-720.53"
+ attribute \src "ls180.v:716.6-716.53"
wire \main_sdram_bankmachine3_cmd_buffer_source_ready
- attribute \src "ls180.v:719.5-719.52"
+ attribute \src "ls180.v:715.5-715.52"
wire \main_sdram_bankmachine3_cmd_buffer_source_valid
- attribute \src "ls180.v:667.12-667.49"
+ attribute \src "ls180.v:663.12-663.49"
wire width 13 \main_sdram_bankmachine3_cmd_payload_a
- attribute \src "ls180.v:668.12-668.50"
+ attribute \src "ls180.v:664.12-664.50"
wire width 2 \main_sdram_bankmachine3_cmd_payload_ba
- attribute \src "ls180.v:669.5-669.44"
+ attribute \src "ls180.v:665.5-665.44"
wire \main_sdram_bankmachine3_cmd_payload_cas
- attribute \src "ls180.v:672.5-672.47"
+ attribute \src "ls180.v:668.5-668.47"
wire \main_sdram_bankmachine3_cmd_payload_is_cmd
- attribute \src "ls180.v:673.5-673.48"
+ attribute \src "ls180.v:669.5-669.48"
wire \main_sdram_bankmachine3_cmd_payload_is_read
- attribute \src "ls180.v:674.5-674.49"
+ attribute \src "ls180.v:670.5-670.49"
wire \main_sdram_bankmachine3_cmd_payload_is_write
- attribute \src "ls180.v:670.5-670.44"
+ attribute \src "ls180.v:666.5-666.44"
wire \main_sdram_bankmachine3_cmd_payload_ras
- attribute \src "ls180.v:671.5-671.43"
+ attribute \src "ls180.v:667.5-667.43"
wire \main_sdram_bankmachine3_cmd_payload_we
- attribute \src "ls180.v:666.5-666.38"
+ attribute \src "ls180.v:662.5-662.38"
wire \main_sdram_bankmachine3_cmd_ready
- attribute \src "ls180.v:665.5-665.38"
+ attribute \src "ls180.v:661.5-661.38"
wire \main_sdram_bankmachine3_cmd_valid
- attribute \src "ls180.v:664.5-664.40"
+ attribute \src "ls180.v:660.5-660.40"
wire \main_sdram_bankmachine3_refresh_gnt
- attribute \src "ls180.v:663.6-663.41"
+ attribute \src "ls180.v:659.6-659.41"
wire \main_sdram_bankmachine3_refresh_req
- attribute \src "ls180.v:659.13-659.45"
+ attribute \src "ls180.v:655.13-655.45"
wire width 22 \main_sdram_bankmachine3_req_addr
- attribute \src "ls180.v:660.6-660.38"
+ attribute \src "ls180.v:656.6-656.38"
wire \main_sdram_bankmachine3_req_lock
- attribute \src "ls180.v:662.5-662.44"
+ attribute \src "ls180.v:658.5-658.44"
wire \main_sdram_bankmachine3_req_rdata_valid
- attribute \src "ls180.v:657.6-657.39"
+ attribute \src "ls180.v:653.6-653.39"
wire \main_sdram_bankmachine3_req_ready
- attribute \src "ls180.v:656.6-656.39"
+ attribute \src "ls180.v:652.6-652.39"
wire \main_sdram_bankmachine3_req_valid
- attribute \src "ls180.v:661.5-661.44"
+ attribute \src "ls180.v:657.5-657.44"
wire \main_sdram_bankmachine3_req_wdata_ready
- attribute \src "ls180.v:658.6-658.36"
+ attribute \src "ls180.v:654.6-654.36"
wire \main_sdram_bankmachine3_req_we
- attribute \src "ls180.v:725.12-725.39"
+ attribute \src "ls180.v:721.12-721.39"
wire width 13 \main_sdram_bankmachine3_row
- attribute \src "ls180.v:729.5-729.38"
+ attribute \src "ls180.v:725.5-725.38"
wire \main_sdram_bankmachine3_row_close
- attribute \src "ls180.v:730.5-730.47"
+ attribute \src "ls180.v:726.5-726.47"
wire \main_sdram_bankmachine3_row_col_n_addr_sel
- attribute \src "ls180.v:727.6-727.37"
+ attribute \src "ls180.v:723.6-723.37"
wire \main_sdram_bankmachine3_row_hit
- attribute \src "ls180.v:728.5-728.37"
+ attribute \src "ls180.v:724.5-724.37"
wire \main_sdram_bankmachine3_row_open
- attribute \src "ls180.v:726.5-726.39"
+ attribute \src "ls180.v:722.5-722.39"
wire \main_sdram_bankmachine3_row_opened
attribute \no_retiming "true"
- attribute \src "ls180.v:737.32-737.69"
+ attribute \src "ls180.v:733.32-733.69"
wire \main_sdram_bankmachine3_trascon_ready
- attribute \src "ls180.v:736.6-736.43"
+ attribute \src "ls180.v:732.6-732.43"
wire \main_sdram_bankmachine3_trascon_valid
attribute \no_retiming "true"
- attribute \src "ls180.v:735.32-735.68"
+ attribute \src "ls180.v:731.32-731.68"
wire \main_sdram_bankmachine3_trccon_ready
- attribute \src "ls180.v:734.6-734.42"
+ attribute \src "ls180.v:730.6-730.42"
wire \main_sdram_bankmachine3_trccon_valid
- attribute \src "ls180.v:733.11-733.48"
+ attribute \src "ls180.v:729.11-729.48"
wire width 3 \main_sdram_bankmachine3_twtpcon_count
attribute \no_retiming "true"
- attribute \src "ls180.v:732.32-732.69"
+ attribute \src "ls180.v:728.32-728.69"
wire \main_sdram_bankmachine3_twtpcon_ready
- attribute \src "ls180.v:731.6-731.43"
+ attribute \src "ls180.v:727.6-727.43"
wire \main_sdram_bankmachine3_twtpcon_valid
- attribute \src "ls180.v:739.6-739.28"
+ attribute \src "ls180.v:735.6-735.28"
wire \main_sdram_cas_allowed
- attribute \src "ls180.v:757.6-757.30"
+ attribute \src "ls180.v:753.6-753.30"
wire \main_sdram_choose_cmd_ce
- attribute \src "ls180.v:746.13-746.48"
+ attribute \src "ls180.v:742.13-742.48"
wire width 13 \main_sdram_choose_cmd_cmd_payload_a
- attribute \src "ls180.v:747.12-747.48"
+ attribute \src "ls180.v:743.12-743.48"
wire width 2 \main_sdram_choose_cmd_cmd_payload_ba
- attribute \src "ls180.v:748.5-748.42"
+ attribute \src "ls180.v:744.5-744.42"
wire \main_sdram_choose_cmd_cmd_payload_cas
- attribute \src "ls180.v:751.6-751.46"
+ attribute \src "ls180.v:747.6-747.46"
wire \main_sdram_choose_cmd_cmd_payload_is_cmd
- attribute \src "ls180.v:752.6-752.47"
+ attribute \src "ls180.v:748.6-748.47"
wire \main_sdram_choose_cmd_cmd_payload_is_read
- attribute \src "ls180.v:753.6-753.48"
+ attribute \src "ls180.v:749.6-749.48"
wire \main_sdram_choose_cmd_cmd_payload_is_write
- attribute \src "ls180.v:749.5-749.42"
+ attribute \src "ls180.v:745.5-745.42"
wire \main_sdram_choose_cmd_cmd_payload_ras
- attribute \src "ls180.v:750.5-750.41"
+ attribute \src "ls180.v:746.5-746.41"
wire \main_sdram_choose_cmd_cmd_payload_we
- attribute \src "ls180.v:745.5-745.36"
+ attribute \src "ls180.v:741.5-741.36"
wire \main_sdram_choose_cmd_cmd_ready
- attribute \src "ls180.v:744.6-744.37"
+ attribute \src "ls180.v:740.6-740.37"
wire \main_sdram_choose_cmd_cmd_valid
- attribute \src "ls180.v:756.11-756.38"
+ attribute \src "ls180.v:752.11-752.38"
wire width 2 \main_sdram_choose_cmd_grant
- attribute \src "ls180.v:755.12-755.41"
+ attribute \src "ls180.v:751.12-751.41"
wire width 4 \main_sdram_choose_cmd_request
- attribute \src "ls180.v:754.11-754.39"
+ attribute \src "ls180.v:750.11-750.39"
wire width 4 \main_sdram_choose_cmd_valids
- attribute \src "ls180.v:743.5-743.41"
+ attribute \src "ls180.v:739.5-739.41"
wire \main_sdram_choose_cmd_want_activates
- attribute \src "ls180.v:742.5-742.36"
+ attribute \src "ls180.v:738.5-738.36"
wire \main_sdram_choose_cmd_want_cmds
- attribute \src "ls180.v:740.5-740.37"
+ attribute \src "ls180.v:736.5-736.37"
wire \main_sdram_choose_cmd_want_reads
- attribute \src "ls180.v:741.5-741.38"
+ attribute \src "ls180.v:737.5-737.38"
wire \main_sdram_choose_cmd_want_writes
- attribute \src "ls180.v:775.6-775.30"
+ attribute \src "ls180.v:771.6-771.30"
wire \main_sdram_choose_req_ce
- attribute \src "ls180.v:764.13-764.48"
+ attribute \src "ls180.v:760.13-760.48"
wire width 13 \main_sdram_choose_req_cmd_payload_a
- attribute \src "ls180.v:765.12-765.48"
+ attribute \src "ls180.v:761.12-761.48"
wire width 2 \main_sdram_choose_req_cmd_payload_ba
- attribute \src "ls180.v:766.5-766.42"
+ attribute \src "ls180.v:762.5-762.42"
wire \main_sdram_choose_req_cmd_payload_cas
- attribute \src "ls180.v:769.6-769.46"
+ attribute \src "ls180.v:765.6-765.46"
wire \main_sdram_choose_req_cmd_payload_is_cmd
- attribute \src "ls180.v:770.6-770.47"
+ attribute \src "ls180.v:766.6-766.47"
wire \main_sdram_choose_req_cmd_payload_is_read
- attribute \src "ls180.v:771.6-771.48"
+ attribute \src "ls180.v:767.6-767.48"
wire \main_sdram_choose_req_cmd_payload_is_write
- attribute \src "ls180.v:767.5-767.42"
+ attribute \src "ls180.v:763.5-763.42"
wire \main_sdram_choose_req_cmd_payload_ras
- attribute \src "ls180.v:768.5-768.41"
+ attribute \src "ls180.v:764.5-764.41"
wire \main_sdram_choose_req_cmd_payload_we
- attribute \src "ls180.v:763.5-763.36"
+ attribute \src "ls180.v:759.5-759.36"
wire \main_sdram_choose_req_cmd_ready
- attribute \src "ls180.v:762.6-762.37"
+ attribute \src "ls180.v:758.6-758.37"
wire \main_sdram_choose_req_cmd_valid
- attribute \src "ls180.v:774.11-774.38"
+ attribute \src "ls180.v:770.11-770.38"
wire width 2 \main_sdram_choose_req_grant
- attribute \src "ls180.v:773.12-773.41"
+ attribute \src "ls180.v:769.12-769.41"
wire width 4 \main_sdram_choose_req_request
- attribute \src "ls180.v:772.11-772.39"
+ attribute \src "ls180.v:768.11-768.39"
wire width 4 \main_sdram_choose_req_valids
- attribute \src "ls180.v:761.5-761.41"
+ attribute \src "ls180.v:757.5-757.41"
wire \main_sdram_choose_req_want_activates
- attribute \src "ls180.v:760.6-760.37"
+ attribute \src "ls180.v:756.6-756.37"
wire \main_sdram_choose_req_want_cmds
- attribute \src "ls180.v:758.5-758.37"
+ attribute \src "ls180.v:754.5-754.37"
wire \main_sdram_choose_req_want_reads
- attribute \src "ls180.v:759.5-759.38"
+ attribute \src "ls180.v:755.5-755.38"
wire \main_sdram_choose_req_want_writes
- attribute \src "ls180.v:319.6-319.20"
+ attribute \src "ls180.v:315.6-315.20"
wire \main_sdram_cke
- attribute \src "ls180.v:387.5-387.24"
+ attribute \src "ls180.v:383.5-383.24"
wire \main_sdram_cmd_last
- attribute \src "ls180.v:388.12-388.36"
+ attribute \src "ls180.v:384.12-384.36"
wire width 13 \main_sdram_cmd_payload_a
- attribute \src "ls180.v:389.11-389.36"
+ attribute \src "ls180.v:385.11-385.36"
wire width 2 \main_sdram_cmd_payload_ba
- attribute \src "ls180.v:390.5-390.31"
+ attribute \src "ls180.v:386.5-386.31"
wire \main_sdram_cmd_payload_cas
- attribute \src "ls180.v:393.5-393.35"
+ attribute \src "ls180.v:389.5-389.35"
wire \main_sdram_cmd_payload_is_read
- attribute \src "ls180.v:394.5-394.36"
+ attribute \src "ls180.v:390.5-390.36"
wire \main_sdram_cmd_payload_is_write
- attribute \src "ls180.v:391.5-391.31"
+ attribute \src "ls180.v:387.5-387.31"
wire \main_sdram_cmd_payload_ras
- attribute \src "ls180.v:392.5-392.30"
+ attribute \src "ls180.v:388.5-388.30"
wire \main_sdram_cmd_payload_we
- attribute \src "ls180.v:386.5-386.25"
+ attribute \src "ls180.v:382.5-382.25"
wire \main_sdram_cmd_ready
- attribute \src "ls180.v:385.5-385.25"
+ attribute \src "ls180.v:381.5-381.25"
wire \main_sdram_cmd_valid
- attribute \src "ls180.v:327.6-327.32"
+ attribute \src "ls180.v:323.6-323.32"
wire \main_sdram_command_issue_r
- attribute \src "ls180.v:326.6-326.33"
+ attribute \src "ls180.v:322.6-322.33"
wire \main_sdram_command_issue_re
- attribute \src "ls180.v:329.5-329.31"
+ attribute \src "ls180.v:325.5-325.31"
wire \main_sdram_command_issue_w
- attribute \src "ls180.v:328.6-328.33"
+ attribute \src "ls180.v:324.6-324.33"
wire \main_sdram_command_issue_we
- attribute \src "ls180.v:325.5-325.26"
+ attribute \src "ls180.v:321.5-321.26"
wire \main_sdram_command_re
- attribute \src "ls180.v:324.11-324.37"
+ attribute \src "ls180.v:320.11-320.37"
wire width 6 \main_sdram_command_storage
- attribute \src "ls180.v:378.5-378.28"
+ attribute \src "ls180.v:374.5-374.28"
wire \main_sdram_dfi_p0_act_n
- attribute \src "ls180.v:369.12-369.37"
+ attribute \src "ls180.v:365.12-365.37"
wire width 13 \main_sdram_dfi_p0_address
- attribute \src "ls180.v:370.11-370.33"
+ attribute \src "ls180.v:366.11-366.33"
wire width 2 \main_sdram_dfi_p0_bank
- attribute \src "ls180.v:371.5-371.28"
+ attribute \src "ls180.v:367.5-367.28"
wire \main_sdram_dfi_p0_cas_n
- attribute \src "ls180.v:375.6-375.27"
+ attribute \src "ls180.v:371.6-371.27"
wire \main_sdram_dfi_p0_cke
- attribute \src "ls180.v:372.5-372.27"
+ attribute \src "ls180.v:368.5-368.27"
wire \main_sdram_dfi_p0_cs_n
- attribute \src "ls180.v:376.6-376.27"
+ attribute \src "ls180.v:372.6-372.27"
wire \main_sdram_dfi_p0_odt
- attribute \src "ls180.v:373.5-373.28"
+ attribute \src "ls180.v:369.5-369.28"
wire \main_sdram_dfi_p0_ras_n
- attribute \src "ls180.v:383.13-383.37"
+ attribute \src "ls180.v:379.13-379.37"
wire width 16 \main_sdram_dfi_p0_rddata
- attribute \src "ls180.v:382.5-382.32"
+ attribute \src "ls180.v:378.5-378.32"
wire \main_sdram_dfi_p0_rddata_en
- attribute \src "ls180.v:384.6-384.36"
+ attribute \src "ls180.v:380.6-380.36"
wire \main_sdram_dfi_p0_rddata_valid
- attribute \src "ls180.v:377.6-377.31"
+ attribute \src "ls180.v:373.6-373.31"
wire \main_sdram_dfi_p0_reset_n
- attribute \src "ls180.v:374.5-374.27"
+ attribute \src "ls180.v:370.5-370.27"
wire \main_sdram_dfi_p0_we_n
- attribute \src "ls180.v:379.13-379.37"
+ attribute \src "ls180.v:375.13-375.37"
wire width 16 \main_sdram_dfi_p0_wrdata
- attribute \src "ls180.v:380.5-380.32"
+ attribute \src "ls180.v:376.5-376.32"
wire \main_sdram_dfi_p0_wrdata_en
- attribute \src "ls180.v:381.12-381.41"
+ attribute \src "ls180.v:377.12-377.41"
wire width 2 \main_sdram_dfi_p0_wrdata_mask
- attribute \src "ls180.v:793.5-793.19"
+ attribute \src "ls180.v:789.5-789.19"
wire \main_sdram_en0
- attribute \src "ls180.v:796.5-796.19"
+ attribute \src "ls180.v:792.5-792.19"
wire \main_sdram_en1
- attribute \src "ls180.v:799.6-799.30"
+ attribute \src "ls180.v:795.6-795.30"
wire \main_sdram_go_to_refresh
- attribute \src "ls180.v:341.13-341.44"
+ attribute \src "ls180.v:337.13-337.44"
wire width 22 \main_sdram_interface_bank0_addr
- attribute \src "ls180.v:342.6-342.37"
+ attribute \src "ls180.v:338.6-338.37"
wire \main_sdram_interface_bank0_lock
- attribute \src "ls180.v:344.6-344.44"
+ attribute \src "ls180.v:340.6-340.44"
wire \main_sdram_interface_bank0_rdata_valid
- attribute \src "ls180.v:339.6-339.38"
+ attribute \src "ls180.v:335.6-335.38"
wire \main_sdram_interface_bank0_ready
- attribute \src "ls180.v:338.6-338.38"
+ attribute \src "ls180.v:334.6-334.38"
wire \main_sdram_interface_bank0_valid
- attribute \src "ls180.v:343.6-343.44"
+ attribute \src "ls180.v:339.6-339.44"
wire \main_sdram_interface_bank0_wdata_ready
- attribute \src "ls180.v:340.6-340.35"
+ attribute \src "ls180.v:336.6-336.35"
wire \main_sdram_interface_bank0_we
- attribute \src "ls180.v:348.13-348.44"
+ attribute \src "ls180.v:344.13-344.44"
wire width 22 \main_sdram_interface_bank1_addr
- attribute \src "ls180.v:349.6-349.37"
+ attribute \src "ls180.v:345.6-345.37"
wire \main_sdram_interface_bank1_lock
- attribute \src "ls180.v:351.6-351.44"
+ attribute \src "ls180.v:347.6-347.44"
wire \main_sdram_interface_bank1_rdata_valid
- attribute \src "ls180.v:346.6-346.38"
+ attribute \src "ls180.v:342.6-342.38"
wire \main_sdram_interface_bank1_ready
- attribute \src "ls180.v:345.6-345.38"
+ attribute \src "ls180.v:341.6-341.38"
wire \main_sdram_interface_bank1_valid
- attribute \src "ls180.v:350.6-350.44"
+ attribute \src "ls180.v:346.6-346.44"
wire \main_sdram_interface_bank1_wdata_ready
- attribute \src "ls180.v:347.6-347.35"
+ attribute \src "ls180.v:343.6-343.35"
wire \main_sdram_interface_bank1_we
- attribute \src "ls180.v:355.13-355.44"
+ attribute \src "ls180.v:351.13-351.44"
wire width 22 \main_sdram_interface_bank2_addr
- attribute \src "ls180.v:356.6-356.37"
+ attribute \src "ls180.v:352.6-352.37"
wire \main_sdram_interface_bank2_lock
- attribute \src "ls180.v:358.6-358.44"
+ attribute \src "ls180.v:354.6-354.44"
wire \main_sdram_interface_bank2_rdata_valid
- attribute \src "ls180.v:353.6-353.38"
+ attribute \src "ls180.v:349.6-349.38"
wire \main_sdram_interface_bank2_ready
- attribute \src "ls180.v:352.6-352.38"
+ attribute \src "ls180.v:348.6-348.38"
wire \main_sdram_interface_bank2_valid
- attribute \src "ls180.v:357.6-357.44"
+ attribute \src "ls180.v:353.6-353.44"
wire \main_sdram_interface_bank2_wdata_ready
- attribute \src "ls180.v:354.6-354.35"
+ attribute \src "ls180.v:350.6-350.35"
wire \main_sdram_interface_bank2_we
- attribute \src "ls180.v:362.13-362.44"
+ attribute \src "ls180.v:358.13-358.44"
wire width 22 \main_sdram_interface_bank3_addr
- attribute \src "ls180.v:363.6-363.37"
+ attribute \src "ls180.v:359.6-359.37"
wire \main_sdram_interface_bank3_lock
- attribute \src "ls180.v:365.6-365.44"
+ attribute \src "ls180.v:361.6-361.44"
wire \main_sdram_interface_bank3_rdata_valid
- attribute \src "ls180.v:360.6-360.38"
+ attribute \src "ls180.v:356.6-356.38"
wire \main_sdram_interface_bank3_ready
- attribute \src "ls180.v:359.6-359.38"
+ attribute \src "ls180.v:355.6-355.38"
wire \main_sdram_interface_bank3_valid
- attribute \src "ls180.v:364.6-364.44"
+ attribute \src "ls180.v:360.6-360.44"
wire \main_sdram_interface_bank3_wdata_ready
- attribute \src "ls180.v:361.6-361.35"
+ attribute \src "ls180.v:357.6-357.35"
wire \main_sdram_interface_bank3_we
- attribute \src "ls180.v:368.13-368.39"
+ attribute \src "ls180.v:364.13-364.39"
wire width 16 \main_sdram_interface_rdata
- attribute \src "ls180.v:366.12-366.38"
+ attribute \src "ls180.v:362.12-362.38"
wire width 16 \main_sdram_interface_wdata
- attribute \src "ls180.v:367.11-367.40"
+ attribute \src "ls180.v:363.11-363.40"
wire width 2 \main_sdram_interface_wdata_we
- attribute \src "ls180.v:279.5-279.29"
+ attribute \src "ls180.v:275.5-275.29"
wire \main_sdram_inti_p0_act_n
- attribute \src "ls180.v:270.13-270.39"
+ attribute \src "ls180.v:266.13-266.39"
wire width 13 \main_sdram_inti_p0_address
- attribute \src "ls180.v:271.12-271.35"
+ attribute \src "ls180.v:267.12-267.35"
wire width 2 \main_sdram_inti_p0_bank
- attribute \src "ls180.v:272.5-272.29"
+ attribute \src "ls180.v:268.5-268.29"
wire \main_sdram_inti_p0_cas_n
- attribute \src "ls180.v:276.6-276.28"
+ attribute \src "ls180.v:272.6-272.28"
wire \main_sdram_inti_p0_cke
- attribute \src "ls180.v:273.5-273.28"
+ attribute \src "ls180.v:269.5-269.28"
wire \main_sdram_inti_p0_cs_n
- attribute \src "ls180.v:277.6-277.28"
+ attribute \src "ls180.v:273.6-273.28"
wire \main_sdram_inti_p0_odt
- attribute \src "ls180.v:274.5-274.29"
+ attribute \src "ls180.v:270.5-270.29"
wire \main_sdram_inti_p0_ras_n
- attribute \src "ls180.v:284.12-284.37"
+ attribute \src "ls180.v:280.12-280.37"
wire width 16 \main_sdram_inti_p0_rddata
- attribute \src "ls180.v:283.6-283.34"
+ attribute \src "ls180.v:279.6-279.34"
wire \main_sdram_inti_p0_rddata_en
- attribute \src "ls180.v:285.5-285.36"
+ attribute \src "ls180.v:281.5-281.36"
wire \main_sdram_inti_p0_rddata_valid
- attribute \src "ls180.v:278.6-278.32"
+ attribute \src "ls180.v:274.6-274.32"
wire \main_sdram_inti_p0_reset_n
- attribute \src "ls180.v:275.5-275.28"
+ attribute \src "ls180.v:271.5-271.28"
wire \main_sdram_inti_p0_we_n
- attribute \src "ls180.v:280.13-280.38"
+ attribute \src "ls180.v:276.13-276.38"
wire width 16 \main_sdram_inti_p0_wrdata
- attribute \src "ls180.v:281.6-281.34"
+ attribute \src "ls180.v:277.6-277.34"
wire \main_sdram_inti_p0_wrdata_en
- attribute \src "ls180.v:282.12-282.42"
+ attribute \src "ls180.v:278.12-278.42"
wire width 2 \main_sdram_inti_p0_wrdata_mask
- attribute \src "ls180.v:311.5-311.31"
+ attribute \src "ls180.v:307.5-307.31"
wire \main_sdram_master_p0_act_n
- attribute \src "ls180.v:302.12-302.40"
+ attribute \src "ls180.v:298.12-298.40"
wire width 13 \main_sdram_master_p0_address
- attribute \src "ls180.v:303.11-303.36"
+ attribute \src "ls180.v:299.11-299.36"
wire width 2 \main_sdram_master_p0_bank
- attribute \src "ls180.v:304.5-304.31"
+ attribute \src "ls180.v:300.5-300.31"
wire \main_sdram_master_p0_cas_n
- attribute \src "ls180.v:308.5-308.29"
+ attribute \src "ls180.v:304.5-304.29"
wire \main_sdram_master_p0_cke
- attribute \src "ls180.v:305.5-305.30"
+ attribute \src "ls180.v:301.5-301.30"
wire \main_sdram_master_p0_cs_n
- attribute \src "ls180.v:309.5-309.29"
+ attribute \src "ls180.v:305.5-305.29"
wire \main_sdram_master_p0_odt
- attribute \src "ls180.v:306.5-306.31"
+ attribute \src "ls180.v:302.5-302.31"
wire \main_sdram_master_p0_ras_n
- attribute \src "ls180.v:316.13-316.40"
+ attribute \src "ls180.v:312.13-312.40"
wire width 16 \main_sdram_master_p0_rddata
- attribute \src "ls180.v:315.5-315.35"
+ attribute \src "ls180.v:311.5-311.35"
wire \main_sdram_master_p0_rddata_en
- attribute \src "ls180.v:317.6-317.39"
+ attribute \src "ls180.v:313.6-313.39"
wire \main_sdram_master_p0_rddata_valid
- attribute \src "ls180.v:310.5-310.33"
+ attribute \src "ls180.v:306.5-306.33"
wire \main_sdram_master_p0_reset_n
- attribute \src "ls180.v:307.5-307.30"
+ attribute \src "ls180.v:303.5-303.30"
wire \main_sdram_master_p0_we_n
- attribute \src "ls180.v:312.12-312.39"
+ attribute \src "ls180.v:308.12-308.39"
wire width 16 \main_sdram_master_p0_wrdata
- attribute \src "ls180.v:313.5-313.35"
+ attribute \src "ls180.v:309.5-309.35"
wire \main_sdram_master_p0_wrdata_en
- attribute \src "ls180.v:314.11-314.43"
+ attribute \src "ls180.v:310.11-310.43"
wire width 2 \main_sdram_master_p0_wrdata_mask
- attribute \src "ls180.v:794.6-794.26"
+ attribute \src "ls180.v:790.6-790.26"
wire \main_sdram_max_time0
- attribute \src "ls180.v:797.6-797.26"
+ attribute \src "ls180.v:793.6-793.26"
wire \main_sdram_max_time1
- attribute \src "ls180.v:776.12-776.28"
+ attribute \src "ls180.v:772.12-772.28"
wire width 13 \main_sdram_nop_a
- attribute \src "ls180.v:777.11-777.28"
+ attribute \src "ls180.v:773.11-773.28"
wire width 2 \main_sdram_nop_ba
- attribute \src "ls180.v:320.6-320.20"
+ attribute \src "ls180.v:316.6-316.20"
wire \main_sdram_odt
- attribute \src "ls180.v:403.5-403.31"
+ attribute \src "ls180.v:399.5-399.31"
wire \main_sdram_postponer_count
- attribute \src "ls180.v:401.6-401.32"
+ attribute \src "ls180.v:397.6-397.32"
wire \main_sdram_postponer_req_i
- attribute \src "ls180.v:402.5-402.31"
+ attribute \src "ls180.v:398.5-398.31"
wire \main_sdram_postponer_req_o
- attribute \src "ls180.v:738.6-738.28"
+ attribute \src "ls180.v:734.6-734.28"
wire \main_sdram_ras_allowed
- attribute \src "ls180.v:323.5-323.18"
+ attribute \src "ls180.v:319.5-319.18"
wire \main_sdram_re
- attribute \src "ls180.v:791.6-791.31"
+ attribute \src "ls180.v:787.6-787.31"
wire \main_sdram_read_available
- attribute \src "ls180.v:321.6-321.24"
+ attribute \src "ls180.v:317.6-317.24"
wire \main_sdram_reset_n
- attribute \src "ls180.v:318.6-318.20"
+ attribute \src "ls180.v:314.6-314.20"
wire \main_sdram_sel
- attribute \src "ls180.v:409.5-409.31"
+ attribute \src "ls180.v:405.5-405.31"
wire \main_sdram_sequencer_count
- attribute \src "ls180.v:408.11-408.39"
+ attribute \src "ls180.v:404.11-404.39"
wire width 4 \main_sdram_sequencer_counter
- attribute \src "ls180.v:405.6-405.32"
+ attribute \src "ls180.v:401.6-401.32"
wire \main_sdram_sequencer_done0
- attribute \src "ls180.v:407.5-407.31"
+ attribute \src "ls180.v:403.5-403.31"
wire \main_sdram_sequencer_done1
- attribute \src "ls180.v:404.5-404.32"
+ attribute \src "ls180.v:400.5-400.32"
wire \main_sdram_sequencer_start0
- attribute \src "ls180.v:406.6-406.33"
+ attribute \src "ls180.v:402.6-402.33"
wire \main_sdram_sequencer_start1
- attribute \src "ls180.v:295.6-295.31"
+ attribute \src "ls180.v:291.6-291.31"
wire \main_sdram_slave_p0_act_n
- attribute \src "ls180.v:286.13-286.40"
+ attribute \src "ls180.v:282.13-282.40"
wire width 13 \main_sdram_slave_p0_address
- attribute \src "ls180.v:287.12-287.36"
+ attribute \src "ls180.v:283.12-283.36"
wire width 2 \main_sdram_slave_p0_bank
- attribute \src "ls180.v:288.6-288.31"
+ attribute \src "ls180.v:284.6-284.31"
wire \main_sdram_slave_p0_cas_n
- attribute \src "ls180.v:292.6-292.29"
+ attribute \src "ls180.v:288.6-288.29"
wire \main_sdram_slave_p0_cke
- attribute \src "ls180.v:289.6-289.30"
+ attribute \src "ls180.v:285.6-285.30"
wire \main_sdram_slave_p0_cs_n
- attribute \src "ls180.v:293.6-293.29"
+ attribute \src "ls180.v:289.6-289.29"
wire \main_sdram_slave_p0_odt
- attribute \src "ls180.v:290.6-290.31"
+ attribute \src "ls180.v:286.6-286.31"
wire \main_sdram_slave_p0_ras_n
- attribute \src "ls180.v:300.12-300.38"
+ attribute \src "ls180.v:296.12-296.38"
wire width 16 \main_sdram_slave_p0_rddata
- attribute \src "ls180.v:299.6-299.35"
+ attribute \src "ls180.v:295.6-295.35"
wire \main_sdram_slave_p0_rddata_en
- attribute \src "ls180.v:301.5-301.37"
+ attribute \src "ls180.v:297.5-297.37"
wire \main_sdram_slave_p0_rddata_valid
- attribute \src "ls180.v:294.6-294.33"
+ attribute \src "ls180.v:290.6-290.33"
wire \main_sdram_slave_p0_reset_n
- attribute \src "ls180.v:291.6-291.30"
+ attribute \src "ls180.v:287.6-287.30"
wire \main_sdram_slave_p0_we_n
- attribute \src "ls180.v:296.13-296.39"
+ attribute \src "ls180.v:292.13-292.39"
wire width 16 \main_sdram_slave_p0_wrdata
- attribute \src "ls180.v:297.6-297.35"
+ attribute \src "ls180.v:293.6-293.35"
wire \main_sdram_slave_p0_wrdata_en
- attribute \src "ls180.v:298.12-298.43"
+ attribute \src "ls180.v:294.12-294.43"
wire width 2 \main_sdram_slave_p0_wrdata_mask
- attribute \src "ls180.v:336.12-336.29"
+ attribute \src "ls180.v:332.12-332.29"
wire width 16 \main_sdram_status
- attribute \src "ls180.v:779.5-779.24"
+ attribute \src "ls180.v:775.5-775.24"
wire \main_sdram_steerer0
- attribute \src "ls180.v:780.5-780.24"
+ attribute \src "ls180.v:776.5-776.24"
wire \main_sdram_steerer1
- attribute \src "ls180.v:778.11-778.33"
+ attribute \src "ls180.v:774.11-774.33"
wire width 2 \main_sdram_steerer_sel
- attribute \src "ls180.v:322.11-322.29"
+ attribute \src "ls180.v:318.11-318.29"
wire width 4 \main_sdram_storage
- attribute \src "ls180.v:787.5-787.29"
+ attribute \src "ls180.v:783.5-783.29"
wire \main_sdram_tccdcon_count
attribute \no_retiming "true"
- attribute \src "ls180.v:786.32-786.56"
+ attribute \src "ls180.v:782.32-782.56"
wire \main_sdram_tccdcon_ready
- attribute \src "ls180.v:785.6-785.30"
+ attribute \src "ls180.v:781.6-781.30"
wire \main_sdram_tccdcon_valid
attribute \no_retiming "true"
- attribute \src "ls180.v:784.32-784.56"
+ attribute \src "ls180.v:780.32-780.56"
wire \main_sdram_tfawcon_ready
- attribute \src "ls180.v:783.6-783.30"
+ attribute \src "ls180.v:779.6-779.30"
wire \main_sdram_tfawcon_valid
- attribute \src "ls180.v:795.11-795.27"
+ attribute \src "ls180.v:791.11-791.27"
wire width 5 \main_sdram_time0
- attribute \src "ls180.v:798.11-798.27"
+ attribute \src "ls180.v:794.11-794.27"
wire width 4 \main_sdram_time1
- attribute \src "ls180.v:398.12-398.35"
+ attribute \src "ls180.v:394.12-394.35"
wire width 10 \main_sdram_timer_count0
- attribute \src "ls180.v:400.11-400.34"
+ attribute \src "ls180.v:396.11-396.34"
wire width 10 \main_sdram_timer_count1
- attribute \src "ls180.v:397.6-397.28"
+ attribute \src "ls180.v:393.6-393.28"
wire \main_sdram_timer_done0
- attribute \src "ls180.v:399.6-399.28"
+ attribute \src "ls180.v:395.6-395.28"
wire \main_sdram_timer_done1
- attribute \src "ls180.v:396.6-396.27"
+ attribute \src "ls180.v:392.6-392.27"
wire \main_sdram_timer_wait
attribute \no_retiming "true"
- attribute \src "ls180.v:782.32-782.56"
+ attribute \src "ls180.v:778.32-778.56"
wire \main_sdram_trrdcon_ready
- attribute \src "ls180.v:781.6-781.30"
+ attribute \src "ls180.v:777.6-777.30"
wire \main_sdram_trrdcon_valid
- attribute \src "ls180.v:790.11-790.35"
+ attribute \src "ls180.v:786.11-786.35"
wire width 3 \main_sdram_twtrcon_count
attribute \no_retiming "true"
- attribute \src "ls180.v:789.32-789.56"
+ attribute \src "ls180.v:785.32-785.56"
wire \main_sdram_twtrcon_ready
- attribute \src "ls180.v:788.6-788.30"
+ attribute \src "ls180.v:784.6-784.30"
wire \main_sdram_twtrcon_valid
- attribute \src "ls180.v:395.6-395.30"
+ attribute \src "ls180.v:391.6-391.30"
wire \main_sdram_wants_refresh
- attribute \src "ls180.v:337.6-337.19"
+ attribute \src "ls180.v:333.6-333.19"
wire \main_sdram_we
- attribute \src "ls180.v:335.5-335.25"
+ attribute \src "ls180.v:331.5-331.25"
wire \main_sdram_wrdata_re
- attribute \src "ls180.v:334.12-334.37"
+ attribute \src "ls180.v:330.12-330.37"
wire width 16 \main_sdram_wrdata_storage
- attribute \src "ls180.v:792.6-792.32"
+ attribute \src "ls180.v:788.6-788.32"
wire \main_sdram_write_available
- attribute \src "ls180.v:992.6-992.27"
+ attribute \src "ls180.v:988.6-988.27"
wire \main_spimaster0_start
- attribute \src "ls180.v:1002.12-1002.35"
+ attribute \src "ls180.v:998.12-998.35"
wire width 8 \main_spimaster10_length
- attribute \src "ls180.v:1003.12-1003.36"
+ attribute \src "ls180.v:999.12-999.36"
wire width 16 \main_spimaster11_storage
- attribute \src "ls180.v:1004.5-1004.24"
+ attribute \src "ls180.v:1000.5-1000.24"
wire \main_spimaster12_re
- attribute \src "ls180.v:1005.6-1005.27"
+ attribute \src "ls180.v:1001.6-1001.27"
wire \main_spimaster13_done
- attribute \src "ls180.v:1006.6-1006.29"
+ attribute \src "ls180.v:1002.6-1002.29"
wire \main_spimaster14_status
- attribute \src "ls180.v:1007.6-1007.25"
+ attribute \src "ls180.v:1003.6-1003.25"
wire \main_spimaster15_we
- attribute \src "ls180.v:1008.11-1008.35"
+ attribute \src "ls180.v:1004.11-1004.35"
wire width 8 \main_spimaster16_storage
- attribute \src "ls180.v:1009.5-1009.24"
+ attribute \src "ls180.v:1005.5-1005.24"
wire \main_spimaster17_re
- attribute \src "ls180.v:1010.12-1010.35"
+ attribute \src "ls180.v:1006.12-1006.35"
wire width 8 \main_spimaster18_status
- attribute \src "ls180.v:1011.6-1011.25"
+ attribute \src "ls180.v:1007.6-1007.25"
wire \main_spimaster19_we
- attribute \src "ls180.v:993.12-993.34"
+ attribute \src "ls180.v:989.12-989.34"
wire width 8 \main_spimaster1_length
- attribute \src "ls180.v:1065.5-1065.23"
+ attribute \src "ls180.v:1061.5-1061.23"
wire \main_spimaster1_re
- attribute \src "ls180.v:1064.12-1064.35"
+ attribute \src "ls180.v:1060.12-1060.35"
wire width 16 \main_spimaster1_storage
- attribute \src "ls180.v:1012.6-1012.26"
+ attribute \src "ls180.v:1008.6-1008.26"
wire \main_spimaster20_sel
- attribute \src "ls180.v:1013.5-1013.29"
+ attribute \src "ls180.v:1009.5-1009.29"
wire \main_spimaster21_storage
- attribute \src "ls180.v:1014.5-1014.24"
+ attribute \src "ls180.v:1010.5-1010.24"
wire \main_spimaster22_re
- attribute \src "ls180.v:1015.5-1015.29"
+ attribute \src "ls180.v:1011.5-1011.29"
wire \main_spimaster23_storage
- attribute \src "ls180.v:1016.5-1016.24"
+ attribute \src "ls180.v:1012.5-1012.24"
wire \main_spimaster24_re
- attribute \src "ls180.v:1017.5-1017.32"
+ attribute \src "ls180.v:1013.5-1013.32"
wire \main_spimaster25_clk_enable
- attribute \src "ls180.v:1018.5-1018.31"
+ attribute \src "ls180.v:1014.5-1014.31"
wire \main_spimaster26_cs_enable
- attribute \src "ls180.v:1019.11-1019.33"
+ attribute \src "ls180.v:1015.11-1015.33"
wire width 3 \main_spimaster27_count
- attribute \src "ls180.v:1785.11-1785.55"
+ attribute \src "ls180.v:1781.11-1781.55"
wire width 3 \main_spimaster27_count_spimaster0_next_value
- attribute \src "ls180.v:1786.5-1786.52"
+ attribute \src "ls180.v:1782.5-1782.52"
wire \main_spimaster27_count_spimaster0_next_value_ce
- attribute \src "ls180.v:1020.5-1020.32"
+ attribute \src "ls180.v:1016.5-1016.32"
wire \main_spimaster28_mosi_latch
- attribute \src "ls180.v:1021.5-1021.32"
+ attribute \src "ls180.v:1017.5-1017.32"
wire \main_spimaster29_miso_latch
- attribute \src "ls180.v:994.5-994.25"
+ attribute \src "ls180.v:990.5-990.25"
wire \main_spimaster2_done
- attribute \src "ls180.v:1022.12-1022.40"
+ attribute \src "ls180.v:1018.12-1018.40"
wire width 16 \main_spimaster30_clk_divider
- attribute \src "ls180.v:1023.6-1023.31"
+ attribute \src "ls180.v:1019.6-1019.31"
wire \main_spimaster31_clk_rise
- attribute \src "ls180.v:1024.6-1024.31"
+ attribute \src "ls180.v:1020.6-1020.31"
wire \main_spimaster32_clk_fall
- attribute \src "ls180.v:1025.11-1025.37"
+ attribute \src "ls180.v:1021.11-1021.37"
wire width 8 \main_spimaster33_mosi_data
- attribute \src "ls180.v:1026.11-1026.36"
+ attribute \src "ls180.v:1022.11-1022.36"
wire width 3 \main_spimaster34_mosi_sel
- attribute \src "ls180.v:1027.11-1027.37"
+ attribute \src "ls180.v:1023.11-1023.37"
wire width 8 \main_spimaster35_miso_data
- attribute \src "ls180.v:995.5-995.24"
+ attribute \src "ls180.v:991.5-991.24"
wire \main_spimaster3_irq
- attribute \src "ls180.v:996.12-996.32"
+ attribute \src "ls180.v:992.12-992.32"
wire width 8 \main_spimaster4_mosi
- attribute \src "ls180.v:997.11-997.31"
+ attribute \src "ls180.v:993.11-993.31"
wire width 8 \main_spimaster5_miso
- attribute \src "ls180.v:998.6-998.24"
+ attribute \src "ls180.v:994.6-994.24"
wire \main_spimaster6_cs
- attribute \src "ls180.v:999.6-999.30"
+ attribute \src "ls180.v:995.6-995.30"
wire \main_spimaster7_loopback
- attribute \src "ls180.v:1000.12-1000.39"
+ attribute \src "ls180.v:996.12-996.39"
wire width 16 \main_spimaster8_clk_divider
- attribute \src "ls180.v:1001.5-1001.26"
+ attribute \src "ls180.v:997.5-997.26"
wire \main_spimaster9_start
- attribute \src "ls180.v:1036.13-1036.40"
+ attribute \src "ls180.v:1032.13-1032.40"
wire width 16 \main_spisdcard_clk_divider0
- attribute \src "ls180.v:1058.12-1058.39"
+ attribute \src "ls180.v:1054.12-1054.39"
wire width 16 \main_spisdcard_clk_divider1
- attribute \src "ls180.v:1053.5-1053.30"
+ attribute \src "ls180.v:1049.5-1049.30"
wire \main_spisdcard_clk_enable
- attribute \src "ls180.v:1060.6-1060.29"
+ attribute \src "ls180.v:1056.6-1056.29"
wire \main_spisdcard_clk_fall
- attribute \src "ls180.v:1059.6-1059.29"
+ attribute \src "ls180.v:1055.6-1055.29"
wire \main_spisdcard_clk_rise
- attribute \src "ls180.v:1040.5-1040.30"
+ attribute \src "ls180.v:1036.5-1036.30"
wire \main_spisdcard_control_re
- attribute \src "ls180.v:1039.12-1039.42"
+ attribute \src "ls180.v:1035.12-1035.42"
wire width 16 \main_spisdcard_control_storage
- attribute \src "ls180.v:1055.11-1055.31"
+ attribute \src "ls180.v:1051.11-1051.31"
wire width 3 \main_spisdcard_count
- attribute \src "ls180.v:1789.11-1789.53"
+ attribute \src "ls180.v:1785.11-1785.53"
wire width 3 \main_spisdcard_count_spimaster1_next_value
- attribute \src "ls180.v:1790.5-1790.50"
+ attribute \src "ls180.v:1786.5-1786.50"
wire \main_spisdcard_count_spimaster1_next_value_ce
- attribute \src "ls180.v:1034.6-1034.23"
+ attribute \src "ls180.v:1030.6-1030.23"
wire \main_spisdcard_cs
- attribute \src "ls180.v:1054.5-1054.29"
+ attribute \src "ls180.v:1050.5-1050.29"
wire \main_spisdcard_cs_enable
- attribute \src "ls180.v:1050.5-1050.25"
+ attribute \src "ls180.v:1046.5-1046.25"
wire \main_spisdcard_cs_re
- attribute \src "ls180.v:1049.5-1049.30"
+ attribute \src "ls180.v:1045.5-1045.30"
wire \main_spisdcard_cs_storage
- attribute \src "ls180.v:1030.5-1030.25"
+ attribute \src "ls180.v:1026.5-1026.25"
wire \main_spisdcard_done0
- attribute \src "ls180.v:1041.6-1041.26"
+ attribute \src "ls180.v:1037.6-1037.26"
wire \main_spisdcard_done1
- attribute \src "ls180.v:1031.5-1031.23"
+ attribute \src "ls180.v:1027.5-1027.23"
wire \main_spisdcard_irq
- attribute \src "ls180.v:1029.12-1029.34"
+ attribute \src "ls180.v:1025.12-1025.34"
wire width 8 \main_spisdcard_length0
- attribute \src "ls180.v:1038.12-1038.34"
+ attribute \src "ls180.v:1034.12-1034.34"
wire width 8 \main_spisdcard_length1
- attribute \src "ls180.v:1035.6-1035.29"
+ attribute \src "ls180.v:1031.6-1031.29"
wire \main_spisdcard_loopback
- attribute \src "ls180.v:1052.5-1052.31"
+ attribute \src "ls180.v:1048.5-1048.31"
wire \main_spisdcard_loopback_re
- attribute \src "ls180.v:1051.5-1051.36"
+ attribute \src "ls180.v:1047.5-1047.36"
wire \main_spisdcard_loopback_storage
- attribute \src "ls180.v:1033.11-1033.30"
+ attribute \src "ls180.v:1029.11-1029.30"
wire width 8 \main_spisdcard_miso
- attribute \src "ls180.v:1063.11-1063.35"
+ attribute \src "ls180.v:1059.11-1059.35"
wire width 8 \main_spisdcard_miso_data
- attribute \src "ls180.v:1057.5-1057.30"
+ attribute \src "ls180.v:1053.5-1053.30"
wire \main_spisdcard_miso_latch
- attribute \src "ls180.v:1046.12-1046.38"
+ attribute \src "ls180.v:1042.12-1042.38"
wire width 8 \main_spisdcard_miso_status
- attribute \src "ls180.v:1047.6-1047.28"
+ attribute \src "ls180.v:1043.6-1043.28"
wire \main_spisdcard_miso_we
- attribute \src "ls180.v:1032.12-1032.31"
+ attribute \src "ls180.v:1028.12-1028.31"
wire width 8 \main_spisdcard_mosi
- attribute \src "ls180.v:1061.11-1061.35"
+ attribute \src "ls180.v:1057.11-1057.35"
wire width 8 \main_spisdcard_mosi_data
- attribute \src "ls180.v:1056.5-1056.30"
+ attribute \src "ls180.v:1052.5-1052.30"
wire \main_spisdcard_mosi_latch
- attribute \src "ls180.v:1045.5-1045.27"
+ attribute \src "ls180.v:1041.5-1041.27"
wire \main_spisdcard_mosi_re
- attribute \src "ls180.v:1062.11-1062.34"
+ attribute \src "ls180.v:1058.11-1058.34"
wire width 3 \main_spisdcard_mosi_sel
- attribute \src "ls180.v:1044.11-1044.38"
+ attribute \src "ls180.v:1040.11-1040.38"
wire width 8 \main_spisdcard_mosi_storage
- attribute \src "ls180.v:1048.6-1048.24"
+ attribute \src "ls180.v:1044.6-1044.24"
wire \main_spisdcard_sel
- attribute \src "ls180.v:1028.6-1028.27"
+ attribute \src "ls180.v:1024.6-1024.27"
wire \main_spisdcard_start0
- attribute \src "ls180.v:1037.5-1037.26"
+ attribute \src "ls180.v:1033.5-1033.26"
wire \main_spisdcard_start1
- attribute \src "ls180.v:1042.6-1042.34"
+ attribute \src "ls180.v:1038.6-1038.34"
wire \main_spisdcard_status_status
- attribute \src "ls180.v:1043.6-1043.30"
+ attribute \src "ls180.v:1039.6-1039.30"
wire \main_spisdcard_status_we
- attribute \src "ls180.v:889.12-889.44"
+ attribute \src "ls180.v:885.12-885.44"
wire width 2 \main_uart_eventmanager_pending_r
- attribute \src "ls180.v:888.6-888.39"
+ attribute \src "ls180.v:884.6-884.39"
wire \main_uart_eventmanager_pending_re
- attribute \src "ls180.v:891.11-891.43"
+ attribute \src "ls180.v:887.11-887.43"
wire width 2 \main_uart_eventmanager_pending_w
- attribute \src "ls180.v:890.6-890.39"
+ attribute \src "ls180.v:886.6-886.39"
wire \main_uart_eventmanager_pending_we
- attribute \src "ls180.v:893.5-893.30"
+ attribute \src "ls180.v:889.5-889.30"
wire \main_uart_eventmanager_re
- attribute \src "ls180.v:885.12-885.43"
+ attribute \src "ls180.v:881.12-881.43"
wire width 2 \main_uart_eventmanager_status_r
- attribute \src "ls180.v:884.6-884.38"
+ attribute \src "ls180.v:880.6-880.38"
wire \main_uart_eventmanager_status_re
- attribute \src "ls180.v:887.11-887.42"
+ attribute \src "ls180.v:883.11-883.42"
wire width 2 \main_uart_eventmanager_status_w
- attribute \src "ls180.v:886.6-886.38"
+ attribute \src "ls180.v:882.6-882.38"
wire \main_uart_eventmanager_status_we
- attribute \src "ls180.v:892.11-892.41"
+ attribute \src "ls180.v:888.11-888.41"
wire width 2 \main_uart_eventmanager_storage
- attribute \src "ls180.v:873.6-873.19"
+ attribute \src "ls180.v:869.6-869.19"
wire \main_uart_irq
- attribute \src "ls180.v:859.12-859.46"
+ attribute \src "ls180.v:855.12-855.46"
wire width 32 \main_uart_phy_phase_accumulator_rx
- attribute \src "ls180.v:849.12-849.46"
+ attribute \src "ls180.v:845.12-845.46"
wire width 32 \main_uart_phy_phase_accumulator_tx
- attribute \src "ls180.v:842.5-842.21"
+ attribute \src "ls180.v:838.5-838.21"
wire \main_uart_phy_re
- attribute \src "ls180.v:860.6-860.22"
+ attribute \src "ls180.v:856.6-856.22"
wire \main_uart_phy_rx
- attribute \src "ls180.v:863.11-863.36"
+ attribute \src "ls180.v:859.11-859.36"
wire width 4 \main_uart_phy_rx_bitcount
- attribute \src "ls180.v:864.5-864.26"
+ attribute \src "ls180.v:860.5-860.26"
wire \main_uart_phy_rx_busy
- attribute \src "ls180.v:861.5-861.23"
+ attribute \src "ls180.v:857.5-857.23"
wire \main_uart_phy_rx_r
- attribute \src "ls180.v:862.11-862.31"
+ attribute \src "ls180.v:858.11-858.31"
wire width 8 \main_uart_phy_rx_reg
- attribute \src "ls180.v:845.6-845.30"
+ attribute \src "ls180.v:841.6-841.30"
wire \main_uart_phy_sink_first
- attribute \src "ls180.v:846.6-846.29"
+ attribute \src "ls180.v:842.6-842.29"
wire \main_uart_phy_sink_last
- attribute \src "ls180.v:847.12-847.43"
+ attribute \src "ls180.v:843.12-843.43"
wire width 8 \main_uart_phy_sink_payload_data
- attribute \src "ls180.v:844.5-844.29"
+ attribute \src "ls180.v:840.5-840.29"
wire \main_uart_phy_sink_ready
- attribute \src "ls180.v:843.6-843.30"
+ attribute \src "ls180.v:839.6-839.30"
wire \main_uart_phy_sink_valid
- attribute \src "ls180.v:855.5-855.31"
+ attribute \src "ls180.v:851.5-851.31"
wire \main_uart_phy_source_first
- attribute \src "ls180.v:856.5-856.30"
+ attribute \src "ls180.v:852.5-852.30"
wire \main_uart_phy_source_last
- attribute \src "ls180.v:857.11-857.44"
+ attribute \src "ls180.v:853.11-853.44"
wire width 8 \main_uart_phy_source_payload_data
- attribute \src "ls180.v:854.6-854.32"
+ attribute \src "ls180.v:850.6-850.32"
wire \main_uart_phy_source_ready
- attribute \src "ls180.v:853.5-853.31"
+ attribute \src "ls180.v:849.5-849.31"
wire \main_uart_phy_source_valid
- attribute \src "ls180.v:841.12-841.33"
+ attribute \src "ls180.v:837.12-837.33"
wire width 32 \main_uart_phy_storage
- attribute \src "ls180.v:851.11-851.36"
+ attribute \src "ls180.v:847.11-847.36"
wire width 4 \main_uart_phy_tx_bitcount
- attribute \src "ls180.v:852.5-852.26"
+ attribute \src "ls180.v:848.5-848.26"
wire \main_uart_phy_tx_busy
- attribute \src "ls180.v:850.11-850.31"
+ attribute \src "ls180.v:846.11-846.31"
wire width 8 \main_uart_phy_tx_reg
- attribute \src "ls180.v:858.5-858.32"
+ attribute \src "ls180.v:854.5-854.32"
wire \main_uart_phy_uart_clk_rxen
- attribute \src "ls180.v:848.5-848.32"
+ attribute \src "ls180.v:844.5-844.32"
wire \main_uart_phy_uart_clk_txen
- attribute \src "ls180.v:982.5-982.20"
+ attribute \src "ls180.v:978.5-978.20"
wire \main_uart_reset
- attribute \src "ls180.v:882.5-882.23"
+ attribute \src "ls180.v:878.5-878.23"
wire \main_uart_rx_clear
- attribute \src "ls180.v:966.11-966.36"
+ attribute \src "ls180.v:962.11-962.36"
wire width 4 \main_uart_rx_fifo_consume
- attribute \src "ls180.v:971.6-971.31"
+ attribute \src "ls180.v:967.6-967.31"
wire \main_uart_rx_fifo_do_read
- attribute \src "ls180.v:977.6-977.37"
+ attribute \src "ls180.v:973.6-973.37"
wire \main_uart_rx_fifo_fifo_in_first
- attribute \src "ls180.v:978.6-978.36"
+ attribute \src "ls180.v:974.6-974.36"
wire \main_uart_rx_fifo_fifo_in_last
- attribute \src "ls180.v:976.12-976.50"
+ attribute \src "ls180.v:972.12-972.50"
wire width 8 \main_uart_rx_fifo_fifo_in_payload_data
- attribute \src "ls180.v:980.6-980.38"
+ attribute \src "ls180.v:976.6-976.38"
wire \main_uart_rx_fifo_fifo_out_first
- attribute \src "ls180.v:981.6-981.37"
+ attribute \src "ls180.v:977.6-977.37"
wire \main_uart_rx_fifo_fifo_out_last
- attribute \src "ls180.v:979.12-979.51"
+ attribute \src "ls180.v:975.12-975.51"
wire width 8 \main_uart_rx_fifo_fifo_out_payload_data
- attribute \src "ls180.v:963.11-963.35"
+ attribute \src "ls180.v:959.11-959.35"
wire width 5 \main_uart_rx_fifo_level0
- attribute \src "ls180.v:975.12-975.36"
+ attribute \src "ls180.v:971.12-971.36"
wire width 5 \main_uart_rx_fifo_level1
- attribute \src "ls180.v:965.11-965.36"
+ attribute \src "ls180.v:961.11-961.36"
wire width 4 \main_uart_rx_fifo_produce
- attribute \src "ls180.v:972.12-972.40"
+ attribute \src "ls180.v:968.12-968.40"
wire width 4 \main_uart_rx_fifo_rdport_adr
- attribute \src "ls180.v:973.12-973.42"
+ attribute \src "ls180.v:969.12-969.42"
wire width 10 \main_uart_rx_fifo_rdport_dat_r
- attribute \src "ls180.v:974.6-974.33"
+ attribute \src "ls180.v:970.6-970.33"
wire \main_uart_rx_fifo_rdport_re
- attribute \src "ls180.v:955.6-955.26"
+ attribute \src "ls180.v:951.6-951.26"
wire \main_uart_rx_fifo_re
- attribute \src "ls180.v:956.5-956.31"
+ attribute \src "ls180.v:952.5-952.31"
wire \main_uart_rx_fifo_readable
- attribute \src "ls180.v:964.5-964.30"
+ attribute \src "ls180.v:960.5-960.30"
wire \main_uart_rx_fifo_replace
- attribute \src "ls180.v:947.6-947.34"
+ attribute \src "ls180.v:943.6-943.34"
wire \main_uart_rx_fifo_sink_first
- attribute \src "ls180.v:948.6-948.33"
+ attribute \src "ls180.v:944.6-944.33"
wire \main_uart_rx_fifo_sink_last
- attribute \src "ls180.v:949.12-949.47"
+ attribute \src "ls180.v:945.12-945.47"
wire width 8 \main_uart_rx_fifo_sink_payload_data
- attribute \src "ls180.v:946.6-946.34"
+ attribute \src "ls180.v:942.6-942.34"
wire \main_uart_rx_fifo_sink_ready
- attribute \src "ls180.v:945.6-945.34"
+ attribute \src "ls180.v:941.6-941.34"
wire \main_uart_rx_fifo_sink_valid
- attribute \src "ls180.v:952.6-952.36"
+ attribute \src "ls180.v:948.6-948.36"
wire \main_uart_rx_fifo_source_first
- attribute \src "ls180.v:953.6-953.35"
+ attribute \src "ls180.v:949.6-949.35"
wire \main_uart_rx_fifo_source_last
- attribute \src "ls180.v:954.12-954.49"
+ attribute \src "ls180.v:950.12-950.49"
wire width 8 \main_uart_rx_fifo_source_payload_data
- attribute \src "ls180.v:951.6-951.36"
+ attribute \src "ls180.v:947.6-947.36"
wire \main_uart_rx_fifo_source_ready
- attribute \src "ls180.v:950.6-950.36"
+ attribute \src "ls180.v:946.6-946.36"
wire \main_uart_rx_fifo_source_valid
- attribute \src "ls180.v:961.12-961.42"
+ attribute \src "ls180.v:957.12-957.42"
wire width 10 \main_uart_rx_fifo_syncfifo_din
- attribute \src "ls180.v:962.12-962.43"
+ attribute \src "ls180.v:958.12-958.43"
wire width 10 \main_uart_rx_fifo_syncfifo_dout
- attribute \src "ls180.v:959.6-959.35"
+ attribute \src "ls180.v:955.6-955.35"
wire \main_uart_rx_fifo_syncfifo_re
- attribute \src "ls180.v:960.6-960.41"
+ attribute \src "ls180.v:956.6-956.41"
wire \main_uart_rx_fifo_syncfifo_readable
- attribute \src "ls180.v:957.6-957.35"
+ attribute \src "ls180.v:953.6-953.35"
wire \main_uart_rx_fifo_syncfifo_we
- attribute \src "ls180.v:958.6-958.41"
+ attribute \src "ls180.v:954.6-954.41"
wire \main_uart_rx_fifo_syncfifo_writable
- attribute \src "ls180.v:967.11-967.39"
+ attribute \src "ls180.v:963.11-963.39"
wire width 4 \main_uart_rx_fifo_wrport_adr
- attribute \src "ls180.v:968.12-968.42"
+ attribute \src "ls180.v:964.12-964.42"
wire width 10 \main_uart_rx_fifo_wrport_dat_r
- attribute \src "ls180.v:970.12-970.42"
+ attribute \src "ls180.v:966.12-966.42"
wire width 10 \main_uart_rx_fifo_wrport_dat_w
- attribute \src "ls180.v:969.6-969.33"
+ attribute \src "ls180.v:965.6-965.33"
wire \main_uart_rx_fifo_wrport_we
- attribute \src "ls180.v:883.5-883.29"
+ attribute \src "ls180.v:879.5-879.29"
wire \main_uart_rx_old_trigger
- attribute \src "ls180.v:880.5-880.25"
+ attribute \src "ls180.v:876.5-876.25"
wire \main_uart_rx_pending
- attribute \src "ls180.v:879.6-879.25"
+ attribute \src "ls180.v:875.6-875.25"
wire \main_uart_rx_status
- attribute \src "ls180.v:881.6-881.26"
+ attribute \src "ls180.v:877.6-877.26"
wire \main_uart_rx_trigger
- attribute \src "ls180.v:871.6-871.30"
+ attribute \src "ls180.v:867.6-867.30"
wire \main_uart_rxempty_status
- attribute \src "ls180.v:872.6-872.26"
+ attribute \src "ls180.v:868.6-868.26"
wire \main_uart_rxempty_we
- attribute \src "ls180.v:896.6-896.29"
+ attribute \src "ls180.v:892.6-892.29"
wire \main_uart_rxfull_status
- attribute \src "ls180.v:897.6-897.25"
+ attribute \src "ls180.v:893.6-893.25"
wire \main_uart_rxfull_we
- attribute \src "ls180.v:866.12-866.28"
+ attribute \src "ls180.v:862.12-862.28"
wire width 8 \main_uart_rxtx_r
- attribute \src "ls180.v:865.6-865.23"
+ attribute \src "ls180.v:861.6-861.23"
wire \main_uart_rxtx_re
- attribute \src "ls180.v:868.12-868.28"
+ attribute \src "ls180.v:864.12-864.28"
wire width 8 \main_uart_rxtx_w
- attribute \src "ls180.v:867.6-867.23"
+ attribute \src "ls180.v:863.6-863.23"
wire \main_uart_rxtx_we
- attribute \src "ls180.v:877.5-877.23"
+ attribute \src "ls180.v:873.5-873.23"
wire \main_uart_tx_clear
- attribute \src "ls180.v:929.11-929.36"
+ attribute \src "ls180.v:925.11-925.36"
wire width 4 \main_uart_tx_fifo_consume
- attribute \src "ls180.v:934.6-934.31"
+ attribute \src "ls180.v:930.6-930.31"
wire \main_uart_tx_fifo_do_read
- attribute \src "ls180.v:940.6-940.37"
+ attribute \src "ls180.v:936.6-936.37"
wire \main_uart_tx_fifo_fifo_in_first
- attribute \src "ls180.v:941.6-941.36"
+ attribute \src "ls180.v:937.6-937.36"
wire \main_uart_tx_fifo_fifo_in_last
- attribute \src "ls180.v:939.12-939.50"
+ attribute \src "ls180.v:935.12-935.50"
wire width 8 \main_uart_tx_fifo_fifo_in_payload_data
- attribute \src "ls180.v:943.6-943.38"
+ attribute \src "ls180.v:939.6-939.38"
wire \main_uart_tx_fifo_fifo_out_first
- attribute \src "ls180.v:944.6-944.37"
+ attribute \src "ls180.v:940.6-940.37"
wire \main_uart_tx_fifo_fifo_out_last
- attribute \src "ls180.v:942.12-942.51"
+ attribute \src "ls180.v:938.12-938.51"
wire width 8 \main_uart_tx_fifo_fifo_out_payload_data
- attribute \src "ls180.v:926.11-926.35"
+ attribute \src "ls180.v:922.11-922.35"
wire width 5 \main_uart_tx_fifo_level0
- attribute \src "ls180.v:938.12-938.36"
+ attribute \src "ls180.v:934.12-934.36"
wire width 5 \main_uart_tx_fifo_level1
- attribute \src "ls180.v:928.11-928.36"
+ attribute \src "ls180.v:924.11-924.36"
wire width 4 \main_uart_tx_fifo_produce
- attribute \src "ls180.v:935.12-935.40"
+ attribute \src "ls180.v:931.12-931.40"
wire width 4 \main_uart_tx_fifo_rdport_adr
- attribute \src "ls180.v:936.12-936.42"
+ attribute \src "ls180.v:932.12-932.42"
wire width 10 \main_uart_tx_fifo_rdport_dat_r
- attribute \src "ls180.v:937.6-937.33"
+ attribute \src "ls180.v:933.6-933.33"
wire \main_uart_tx_fifo_rdport_re
- attribute \src "ls180.v:918.6-918.26"
+ attribute \src "ls180.v:914.6-914.26"
wire \main_uart_tx_fifo_re
- attribute \src "ls180.v:919.5-919.31"
+ attribute \src "ls180.v:915.5-915.31"
wire \main_uart_tx_fifo_readable
- attribute \src "ls180.v:927.5-927.30"
+ attribute \src "ls180.v:923.5-923.30"
wire \main_uart_tx_fifo_replace
- attribute \src "ls180.v:910.5-910.33"
+ attribute \src "ls180.v:906.5-906.33"
wire \main_uart_tx_fifo_sink_first
- attribute \src "ls180.v:911.5-911.32"
+ attribute \src "ls180.v:907.5-907.32"
wire \main_uart_tx_fifo_sink_last
- attribute \src "ls180.v:912.12-912.47"
+ attribute \src "ls180.v:908.12-908.47"
wire width 8 \main_uart_tx_fifo_sink_payload_data
- attribute \src "ls180.v:909.6-909.34"
+ attribute \src "ls180.v:905.6-905.34"
wire \main_uart_tx_fifo_sink_ready
- attribute \src "ls180.v:908.6-908.34"
+ attribute \src "ls180.v:904.6-904.34"
wire \main_uart_tx_fifo_sink_valid
- attribute \src "ls180.v:915.6-915.36"
+ attribute \src "ls180.v:911.6-911.36"
wire \main_uart_tx_fifo_source_first
- attribute \src "ls180.v:916.6-916.35"
+ attribute \src "ls180.v:912.6-912.35"
wire \main_uart_tx_fifo_source_last
- attribute \src "ls180.v:917.12-917.49"
+ attribute \src "ls180.v:913.12-913.49"
wire width 8 \main_uart_tx_fifo_source_payload_data
- attribute \src "ls180.v:914.6-914.36"
+ attribute \src "ls180.v:910.6-910.36"
wire \main_uart_tx_fifo_source_ready
- attribute \src "ls180.v:913.6-913.36"
+ attribute \src "ls180.v:909.6-909.36"
wire \main_uart_tx_fifo_source_valid
- attribute \src "ls180.v:924.12-924.42"
+ attribute \src "ls180.v:920.12-920.42"
wire width 10 \main_uart_tx_fifo_syncfifo_din
- attribute \src "ls180.v:925.12-925.43"
+ attribute \src "ls180.v:921.12-921.43"
wire width 10 \main_uart_tx_fifo_syncfifo_dout
- attribute \src "ls180.v:922.6-922.35"
+ attribute \src "ls180.v:918.6-918.35"
wire \main_uart_tx_fifo_syncfifo_re
- attribute \src "ls180.v:923.6-923.41"
+ attribute \src "ls180.v:919.6-919.41"
wire \main_uart_tx_fifo_syncfifo_readable
- attribute \src "ls180.v:920.6-920.35"
+ attribute \src "ls180.v:916.6-916.35"
wire \main_uart_tx_fifo_syncfifo_we
- attribute \src "ls180.v:921.6-921.41"
+ attribute \src "ls180.v:917.6-917.41"
wire \main_uart_tx_fifo_syncfifo_writable
- attribute \src "ls180.v:930.11-930.39"
+ attribute \src "ls180.v:926.11-926.39"
wire width 4 \main_uart_tx_fifo_wrport_adr
- attribute \src "ls180.v:931.12-931.42"
+ attribute \src "ls180.v:927.12-927.42"
wire width 10 \main_uart_tx_fifo_wrport_dat_r
- attribute \src "ls180.v:933.12-933.42"
+ attribute \src "ls180.v:929.12-929.42"
wire width 10 \main_uart_tx_fifo_wrport_dat_w
- attribute \src "ls180.v:932.6-932.33"
+ attribute \src "ls180.v:928.6-928.33"
wire \main_uart_tx_fifo_wrport_we
- attribute \src "ls180.v:878.5-878.29"
+ attribute \src "ls180.v:874.5-874.29"
wire \main_uart_tx_old_trigger
- attribute \src "ls180.v:875.5-875.25"
+ attribute \src "ls180.v:871.5-871.25"
wire \main_uart_tx_pending
- attribute \src "ls180.v:874.6-874.25"
+ attribute \src "ls180.v:870.6-870.25"
wire \main_uart_tx_status
- attribute \src "ls180.v:876.6-876.26"
+ attribute \src "ls180.v:872.6-872.26"
wire \main_uart_tx_trigger
- attribute \src "ls180.v:894.6-894.30"
+ attribute \src "ls180.v:890.6-890.30"
wire \main_uart_txempty_status
- attribute \src "ls180.v:895.6-895.26"
+ attribute \src "ls180.v:891.6-891.26"
wire \main_uart_txempty_we
- attribute \src "ls180.v:869.6-869.29"
+ attribute \src "ls180.v:865.6-865.29"
wire \main_uart_txfull_status
- attribute \src "ls180.v:870.6-870.25"
+ attribute \src "ls180.v:866.6-866.25"
wire \main_uart_txfull_we
- attribute \src "ls180.v:900.6-900.31"
+ attribute \src "ls180.v:896.6-896.31"
wire \main_uart_uart_sink_first
- attribute \src "ls180.v:901.6-901.30"
+ attribute \src "ls180.v:897.6-897.30"
wire \main_uart_uart_sink_last
- attribute \src "ls180.v:902.12-902.44"
+ attribute \src "ls180.v:898.12-898.44"
wire width 8 \main_uart_uart_sink_payload_data
- attribute \src "ls180.v:899.6-899.31"
+ attribute \src "ls180.v:895.6-895.31"
wire \main_uart_uart_sink_ready
- attribute \src "ls180.v:898.6-898.31"
+ attribute \src "ls180.v:894.6-894.31"
wire \main_uart_uart_sink_valid
- attribute \src "ls180.v:905.6-905.33"
+ attribute \src "ls180.v:901.6-901.33"
wire \main_uart_uart_source_first
- attribute \src "ls180.v:906.6-906.32"
+ attribute \src "ls180.v:902.6-902.32"
wire \main_uart_uart_source_last
- attribute \src "ls180.v:907.12-907.46"
+ attribute \src "ls180.v:903.12-903.46"
wire width 8 \main_uart_uart_source_payload_data
- attribute \src "ls180.v:904.6-904.33"
+ attribute \src "ls180.v:900.6-900.33"
wire \main_uart_uart_source_ready
- attribute \src "ls180.v:903.6-903.33"
+ attribute \src "ls180.v:899.6-899.33"
wire \main_uart_uart_source_valid
- attribute \src "ls180.v:819.5-819.22"
+ attribute \src "ls180.v:815.5-815.22"
wire \main_wb_sdram_ack
- attribute \src "ls180.v:813.13-813.30"
+ attribute \src "ls180.v:809.13-809.30"
wire width 30 \main_wb_sdram_adr
- attribute \src "ls180.v:822.12-822.29"
+ attribute \src "ls180.v:818.12-818.29"
wire width 2 \main_wb_sdram_bte
- attribute \src "ls180.v:821.12-821.29"
+ attribute \src "ls180.v:817.12-817.29"
wire width 3 \main_wb_sdram_cti
- attribute \src "ls180.v:817.6-817.23"
+ attribute \src "ls180.v:813.6-813.23"
wire \main_wb_sdram_cyc
- attribute \src "ls180.v:815.13-815.32"
+ attribute \src "ls180.v:811.13-811.32"
wire width 32 \main_wb_sdram_dat_r
- attribute \src "ls180.v:814.13-814.32"
+ attribute \src "ls180.v:810.13-810.32"
wire width 32 \main_wb_sdram_dat_w
- attribute \src "ls180.v:823.5-823.22"
+ attribute \src "ls180.v:819.5-819.22"
wire \main_wb_sdram_err
- attribute \src "ls180.v:816.12-816.29"
+ attribute \src "ls180.v:812.12-812.29"
wire width 4 \main_wb_sdram_sel
- attribute \src "ls180.v:818.6-818.23"
+ attribute \src "ls180.v:814.6-814.23"
wire \main_wb_sdram_stb
- attribute \src "ls180.v:820.6-820.22"
+ attribute \src "ls180.v:816.6-816.22"
wire \main_wb_sdram_we
- attribute \src "ls180.v:837.5-837.24"
+ attribute \src "ls180.v:833.5-833.24"
wire \main_wdata_consumed
- attribute \src "ls180.v:10046.11-10046.17"
+ attribute \src "ls180.v:10042.11-10042.17"
wire width 7 \memadr
- attribute \src "ls180.v:10066.12-10066.18"
+ attribute \src "ls180.v:10062.12-10062.18"
wire width 25 \memdat
- attribute \src "ls180.v:10080.12-10080.20"
+ attribute \src "ls180.v:10076.12-10076.20"
wire width 25 \memdat_1
- attribute \src "ls180.v:10094.12-10094.20"
+ attribute \src "ls180.v:10090.12-10090.20"
wire width 25 \memdat_2
- attribute \src "ls180.v:10108.12-10108.20"
+ attribute \src "ls180.v:10104.12-10104.20"
wire width 25 \memdat_3
- attribute \src "ls180.v:10122.11-10122.19"
+ attribute \src "ls180.v:10118.11-10118.19"
wire width 10 \memdat_4
- attribute \src "ls180.v:10123.11-10123.19"
+ attribute \src "ls180.v:10119.11-10119.19"
wire width 10 \memdat_5
- attribute \src "ls180.v:10139.11-10139.19"
+ attribute \src "ls180.v:10135.11-10135.19"
wire width 10 \memdat_6
- attribute \src "ls180.v:10140.11-10140.19"
+ attribute \src "ls180.v:10136.11-10136.19"
wire width 10 \memdat_7
- attribute \src "ls180.v:10156.11-10156.19"
+ attribute \src "ls180.v:10152.11-10152.19"
wire width 10 \memdat_8
- attribute \src "ls180.v:10170.11-10170.19"
+ attribute \src "ls180.v:10166.11-10166.19"
wire width 10 \memdat_9
attribute \src "ls180.v:52.20-52.22"
wire width 24 input 48 \nc
- attribute \src "ls180.v:251.6-251.13"
+ attribute \src "ls180.v:247.6-247.13"
wire \por_clk
- attribute \src "ls180.v:5.19-5.22"
- wire width 2 output 1 \pwm
+ attribute \src "ls180.v:9.19-9.22"
+ wire width 2 output 5 \pwm
attribute \src "ls180.v:129.12-129.17"
wire width 2 \pwm_1
- attribute \src "ls180.v:10.13-10.23"
- wire output 6 \sdcard_clk
- attribute \src "ls180.v:11.13-11.25"
- wire input 7 \sdcard_cmd_i
- attribute \src "ls180.v:12.13-12.25"
- wire output 8 \sdcard_cmd_o
- attribute \src "ls180.v:13.13-13.26"
- wire output 9 \sdcard_cmd_oe
- attribute \src "ls180.v:14.19-14.32"
- wire width 4 input 10 \sdcard_data_i
- attribute \src "ls180.v:15.19-15.32"
- wire width 4 output 11 \sdcard_data_o
- attribute \src "ls180.v:16.13-16.27"
- wire output 12 \sdcard_data_oe
- attribute \src "ls180.v:19.20-19.27"
- wire width 13 output 15 \sdram_a
- attribute \src "ls180.v:28.19-28.27"
- wire width 2 output 24 \sdram_ba
- attribute \src "ls180.v:25.13-25.24"
- wire output 21 \sdram_cas_n
- attribute \src "ls180.v:27.13-27.22"
- wire output 23 \sdram_cke
- attribute \src "ls180.v:30.13-30.24"
- wire output 26 \sdram_clock
- attribute \src "ls180.v:149.6-149.19"
+ attribute \src "ls180.v:14.13-14.23"
+ wire output 10 \sdcard_clk
+ attribute \src "ls180.v:15.13-15.25"
+ wire input 11 \sdcard_cmd_i
+ attribute \src "ls180.v:16.13-16.25"
+ wire output 12 \sdcard_cmd_o
+ attribute \src "ls180.v:17.13-17.26"
+ wire output 13 \sdcard_cmd_oe
+ attribute \src "ls180.v:18.19-18.32"
+ wire width 4 input 14 \sdcard_data_i
+ attribute \src "ls180.v:19.19-19.32"
+ wire width 4 output 15 \sdcard_data_o
+ attribute \src "ls180.v:20.13-20.27"
+ wire output 16 \sdcard_data_oe
+ attribute \src "ls180.v:31.20-31.27"
+ wire width 13 output 27 \sdram_a
+ attribute \src "ls180.v:40.19-40.27"
+ wire width 2 output 36 \sdram_ba
+ attribute \src "ls180.v:37.13-37.24"
+ wire output 33 \sdram_cas_n
+ attribute \src "ls180.v:39.13-39.22"
+ wire output 35 \sdram_cke
+ attribute \src "ls180.v:42.13-42.24"
+ wire output 38 \sdram_clock
+ attribute \src "ls180.v:157.6-157.19"
wire \sdram_clock_1
- attribute \src "ls180.v:26.13-26.23"
- wire output 22 \sdram_cs_n
- attribute \src "ls180.v:29.19-29.27"
- wire width 2 output 25 \sdram_dm
- attribute \src "ls180.v:20.20-20.30"
- wire width 16 input 16 \sdram_dq_i
- attribute \src "ls180.v:21.20-21.30"
- wire width 16 output 17 \sdram_dq_o
- attribute \src "ls180.v:22.13-22.24"
- wire output 18 \sdram_dq_oe
- attribute \src "ls180.v:24.13-24.24"
- wire output 20 \sdram_ras_n
- attribute \src "ls180.v:23.13-23.23"
- wire output 19 \sdram_we_n
- attribute \src "ls180.v:2647.6-2647.15"
+ attribute \src "ls180.v:38.13-38.23"
+ wire output 34 \sdram_cs_n
+ attribute \src "ls180.v:41.19-41.27"
+ wire width 2 output 37 \sdram_dm
+ attribute \src "ls180.v:32.20-32.30"
+ wire width 16 input 28 \sdram_dq_i
+ attribute \src "ls180.v:33.20-33.30"
+ wire width 16 output 29 \sdram_dq_o
+ attribute \src "ls180.v:34.13-34.24"
+ wire output 30 \sdram_dq_oe
+ attribute \src "ls180.v:36.13-36.24"
+ wire output 32 \sdram_ras_n
+ attribute \src "ls180.v:35.13-35.23"
+ wire output 31 \sdram_we_n
+ attribute \src "ls180.v:2643.6-2643.15"
wire \sdrio_clk
- attribute \src "ls180.v:2648.6-2648.17"
+ attribute \src "ls180.v:2644.6-2644.17"
wire \sdrio_clk_1
- attribute \src "ls180.v:2657.6-2657.18"
+ attribute \src "ls180.v:2653.6-2653.18"
wire \sdrio_clk_10
- attribute \src "ls180.v:2658.6-2658.18"
+ attribute \src "ls180.v:2654.6-2654.18"
wire \sdrio_clk_11
- attribute \src "ls180.v:2659.6-2659.18"
+ attribute \src "ls180.v:2655.6-2655.18"
wire \sdrio_clk_12
- attribute \src "ls180.v:2660.6-2660.18"
+ attribute \src "ls180.v:2656.6-2656.18"
wire \sdrio_clk_13
- attribute \src "ls180.v:2661.6-2661.18"
+ attribute \src "ls180.v:2657.6-2657.18"
wire \sdrio_clk_14
- attribute \src "ls180.v:2662.6-2662.18"
+ attribute \src "ls180.v:2658.6-2658.18"
wire \sdrio_clk_15
- attribute \src "ls180.v:2663.6-2663.18"
+ attribute \src "ls180.v:2659.6-2659.18"
wire \sdrio_clk_16
- attribute \src "ls180.v:2664.6-2664.18"
+ attribute \src "ls180.v:2660.6-2660.18"
wire \sdrio_clk_17
- attribute \src "ls180.v:2665.6-2665.18"
+ attribute \src "ls180.v:2661.6-2661.18"
wire \sdrio_clk_18
- attribute \src "ls180.v:2666.6-2666.18"
+ attribute \src "ls180.v:2662.6-2662.18"
wire \sdrio_clk_19
- attribute \src "ls180.v:2649.6-2649.17"
+ attribute \src "ls180.v:2645.6-2645.17"
wire \sdrio_clk_2
- attribute \src "ls180.v:2667.6-2667.18"
+ attribute \src "ls180.v:2663.6-2663.18"
wire \sdrio_clk_20
- attribute \src "ls180.v:2668.6-2668.18"
+ attribute \src "ls180.v:2664.6-2664.18"
wire \sdrio_clk_21
- attribute \src "ls180.v:2669.6-2669.18"
+ attribute \src "ls180.v:2665.6-2665.18"
wire \sdrio_clk_22
- attribute \src "ls180.v:2670.6-2670.18"
+ attribute \src "ls180.v:2666.6-2666.18"
wire \sdrio_clk_23
- attribute \src "ls180.v:2671.6-2671.18"
+ attribute \src "ls180.v:2667.6-2667.18"
wire \sdrio_clk_24
- attribute \src "ls180.v:2672.6-2672.18"
+ attribute \src "ls180.v:2668.6-2668.18"
wire \sdrio_clk_25
- attribute \src "ls180.v:2673.6-2673.18"
+ attribute \src "ls180.v:2669.6-2669.18"
wire \sdrio_clk_26
- attribute \src "ls180.v:2674.6-2674.18"
+ attribute \src "ls180.v:2670.6-2670.18"
wire \sdrio_clk_27
- attribute \src "ls180.v:2675.6-2675.18"
+ attribute \src "ls180.v:2671.6-2671.18"
wire \sdrio_clk_28
- attribute \src "ls180.v:2676.6-2676.18"
+ attribute \src "ls180.v:2672.6-2672.18"
wire \sdrio_clk_29
- attribute \src "ls180.v:2650.6-2650.17"
+ attribute \src "ls180.v:2646.6-2646.17"
wire \sdrio_clk_3
- attribute \src "ls180.v:2677.6-2677.18"
+ attribute \src "ls180.v:2673.6-2673.18"
wire \sdrio_clk_30
- attribute \src "ls180.v:2678.6-2678.18"
+ attribute \src "ls180.v:2674.6-2674.18"
wire \sdrio_clk_31
- attribute \src "ls180.v:2679.6-2679.18"
+ attribute \src "ls180.v:2675.6-2675.18"
wire \sdrio_clk_32
- attribute \src "ls180.v:2680.6-2680.18"
+ attribute \src "ls180.v:2676.6-2676.18"
wire \sdrio_clk_33
- attribute \src "ls180.v:2681.6-2681.18"
+ attribute \src "ls180.v:2677.6-2677.18"
wire \sdrio_clk_34
- attribute \src "ls180.v:2682.6-2682.18"
+ attribute \src "ls180.v:2678.6-2678.18"
wire \sdrio_clk_35
- attribute \src "ls180.v:2683.6-2683.18"
+ attribute \src "ls180.v:2679.6-2679.18"
wire \sdrio_clk_36
- attribute \src "ls180.v:2684.6-2684.18"
+ attribute \src "ls180.v:2680.6-2680.18"
wire \sdrio_clk_37
- attribute \src "ls180.v:2685.6-2685.18"
+ attribute \src "ls180.v:2681.6-2681.18"
wire \sdrio_clk_38
- attribute \src "ls180.v:2686.6-2686.18"
+ attribute \src "ls180.v:2682.6-2682.18"
wire \sdrio_clk_39
- attribute \src "ls180.v:2651.6-2651.17"
+ attribute \src "ls180.v:2647.6-2647.17"
wire \sdrio_clk_4
- attribute \src "ls180.v:2687.6-2687.18"
+ attribute \src "ls180.v:2683.6-2683.18"
wire \sdrio_clk_40
- attribute \src "ls180.v:2688.6-2688.18"
+ attribute \src "ls180.v:2684.6-2684.18"
wire \sdrio_clk_41
- attribute \src "ls180.v:2689.6-2689.18"
+ attribute \src "ls180.v:2685.6-2685.18"
wire \sdrio_clk_42
- attribute \src "ls180.v:2690.6-2690.18"
+ attribute \src "ls180.v:2686.6-2686.18"
wire \sdrio_clk_43
- attribute \src "ls180.v:2691.6-2691.18"
+ attribute \src "ls180.v:2687.6-2687.18"
wire \sdrio_clk_44
- attribute \src "ls180.v:2692.6-2692.18"
+ attribute \src "ls180.v:2688.6-2688.18"
wire \sdrio_clk_45
- attribute \src "ls180.v:2693.6-2693.18"
+ attribute \src "ls180.v:2689.6-2689.18"
wire \sdrio_clk_46
- attribute \src "ls180.v:2694.6-2694.18"
+ attribute \src "ls180.v:2690.6-2690.18"
wire \sdrio_clk_47
- attribute \src "ls180.v:2695.6-2695.18"
+ attribute \src "ls180.v:2691.6-2691.18"
wire \sdrio_clk_48
- attribute \src "ls180.v:2696.6-2696.18"
+ attribute \src "ls180.v:2692.6-2692.18"
wire \sdrio_clk_49
- attribute \src "ls180.v:2652.6-2652.17"
+ attribute \src "ls180.v:2648.6-2648.17"
wire \sdrio_clk_5
- attribute \src "ls180.v:2697.6-2697.18"
+ attribute \src "ls180.v:2693.6-2693.18"
wire \sdrio_clk_50
- attribute \src "ls180.v:2698.6-2698.18"
+ attribute \src "ls180.v:2694.6-2694.18"
wire \sdrio_clk_51
- attribute \src "ls180.v:2699.6-2699.18"
+ attribute \src "ls180.v:2695.6-2695.18"
wire \sdrio_clk_52
- attribute \src "ls180.v:2700.6-2700.18"
+ attribute \src "ls180.v:2696.6-2696.18"
wire \sdrio_clk_53
- attribute \src "ls180.v:2701.6-2701.18"
+ attribute \src "ls180.v:2697.6-2697.18"
wire \sdrio_clk_54
- attribute \src "ls180.v:2702.6-2702.18"
+ attribute \src "ls180.v:2698.6-2698.18"
wire \sdrio_clk_55
- attribute \src "ls180.v:2737.6-2737.18"
+ attribute \src "ls180.v:2733.6-2733.18"
wire \sdrio_clk_56
- attribute \src "ls180.v:2738.6-2738.18"
+ attribute \src "ls180.v:2734.6-2734.18"
wire \sdrio_clk_57
- attribute \src "ls180.v:2739.6-2739.18"
+ attribute \src "ls180.v:2735.6-2735.18"
wire \sdrio_clk_58
- attribute \src "ls180.v:2740.6-2740.18"
+ attribute \src "ls180.v:2736.6-2736.18"
wire \sdrio_clk_59
- attribute \src "ls180.v:2653.6-2653.17"
+ attribute \src "ls180.v:2649.6-2649.17"
wire \sdrio_clk_6
- attribute \src "ls180.v:2741.6-2741.18"
+ attribute \src "ls180.v:2737.6-2737.18"
wire \sdrio_clk_60
- attribute \src "ls180.v:2742.6-2742.18"
+ attribute \src "ls180.v:2738.6-2738.18"
wire \sdrio_clk_61
- attribute \src "ls180.v:2743.6-2743.18"
+ attribute \src "ls180.v:2739.6-2739.18"
wire \sdrio_clk_62
- attribute \src "ls180.v:2744.6-2744.18"
+ attribute \src "ls180.v:2740.6-2740.18"
wire \sdrio_clk_63
- attribute \src "ls180.v:2745.6-2745.18"
+ attribute \src "ls180.v:2741.6-2741.18"
wire \sdrio_clk_64
- attribute \src "ls180.v:2746.6-2746.18"
+ attribute \src "ls180.v:2742.6-2742.18"
wire \sdrio_clk_65
- attribute \src "ls180.v:2747.6-2747.18"
+ attribute \src "ls180.v:2743.6-2743.18"
wire \sdrio_clk_66
- attribute \src "ls180.v:2748.6-2748.18"
+ attribute \src "ls180.v:2744.6-2744.18"
wire \sdrio_clk_67
- attribute \src "ls180.v:2749.6-2749.18"
+ attribute \src "ls180.v:2745.6-2745.18"
wire \sdrio_clk_68
- attribute \src "ls180.v:2654.6-2654.17"
+ attribute \src "ls180.v:2650.6-2650.17"
wire \sdrio_clk_7
- attribute \src "ls180.v:2655.6-2655.17"
+ attribute \src "ls180.v:2651.6-2651.17"
wire \sdrio_clk_8
- attribute \src "ls180.v:2656.6-2656.17"
+ attribute \src "ls180.v:2652.6-2652.17"
wire \sdrio_clk_9
- attribute \src "ls180.v:32.13-32.26"
- wire output 28 \spimaster_clk
- attribute \src "ls180.v:34.13-34.27"
- wire output 30 \spimaster_cs_n
- attribute \src "ls180.v:35.13-35.27"
- wire input 31 \spimaster_miso
- attribute \src "ls180.v:33.13-33.27"
- wire output 29 \spimaster_mosi
- attribute \src "ls180.v:39.13-39.26"
- wire output 35 \spisdcard_clk
- attribute \src "ls180.v:41.13-41.27"
- wire output 37 \spisdcard_cs_n
- attribute \src "ls180.v:42.13-42.27"
- wire input 38 \spisdcard_miso
- attribute \src "ls180.v:40.13-40.27"
- wire output 36 \spisdcard_mosi
+ attribute \src "ls180.v:21.13-21.26"
+ wire output 17 \spimaster_clk
+ attribute \src "ls180.v:23.13-23.27"
+ wire output 19 \spimaster_cs_n
+ attribute \src "ls180.v:24.13-24.27"
+ wire input 20 \spimaster_miso
+ attribute \src "ls180.v:22.13-22.27"
+ wire output 18 \spimaster_mosi
+ attribute \src "ls180.v:10.13-10.26"
+ wire output 6 \spisdcard_clk
+ attribute \src "ls180.v:12.13-12.27"
+ wire output 8 \spisdcard_cs_n
+ attribute \src "ls180.v:13.13-13.27"
+ wire input 9 \spisdcard_miso
+ attribute \src "ls180.v:11.13-11.27"
+ wire output 7 \spisdcard_mosi
attribute \src "ls180.v:43.13-43.20"
wire input 39 \sys_clk
- attribute \src "ls180.v:249.6-249.15"
+ attribute \src "ls180.v:245.6-245.15"
wire \sys_clk_1
attribute \src "ls180.v:45.19-45.31"
wire width 2 input 41 \sys_clksel_i
wire output 43 \sys_pll_lck_o
attribute \src "ls180.v:44.13-44.20"
wire input 40 \sys_rst
- attribute \src "ls180.v:250.6-250.15"
+ attribute \src "ls180.v:246.6-246.15"
wire \sys_rst_1
- attribute \src "ls180.v:18.13-18.20"
- wire input 14 \uart_rx
- attribute \src "ls180.v:17.13-17.20"
- wire output 13 \uart_tx
- attribute \src "ls180.v:10045.12-10045.15"
+ attribute \src "ls180.v:29.13-29.20"
+ wire input 25 \uart_rx
+ attribute \src "ls180.v:28.13-28.20"
+ wire output 24 \uart_tx
+ attribute \src "ls180.v:10041.12-10041.15"
memory width 32 size 128 \mem
- attribute \src "ls180.v:10065.12-10065.19"
+ attribute \src "ls180.v:10061.12-10061.19"
memory width 25 size 8 \storage
- attribute \src "ls180.v:10079.12-10079.21"
+ attribute \src "ls180.v:10075.12-10075.21"
memory width 25 size 8 \storage_1
- attribute \src "ls180.v:10093.12-10093.21"
+ attribute \src "ls180.v:10089.12-10089.21"
memory width 25 size 8 \storage_2
- attribute \src "ls180.v:10107.12-10107.21"
+ attribute \src "ls180.v:10103.12-10103.21"
memory width 25 size 8 \storage_3
- attribute \src "ls180.v:10121.11-10121.20"
+ attribute \src "ls180.v:10117.11-10117.20"
memory width 10 size 16 \storage_4
- attribute \src "ls180.v:10138.11-10138.20"
+ attribute \src "ls180.v:10134.11-10134.20"
memory width 10 size 16 \storage_5
- attribute \src "ls180.v:10155.11-10155.20"
+ attribute \src "ls180.v:10151.11-10151.20"
memory width 10 size 32 \storage_6
- attribute \src "ls180.v:10169.11-10169.20"
+ attribute \src "ls180.v:10165.11-10165.20"
memory width 10 size 32 \storage_7
- attribute \src "ls180.v:2819.68-2819.110"
- cell $add $add$ls180.v:2819$22
+ attribute \src "ls180.v:2815.68-2815.110"
+ cell $add $add$ls180.v:2815$22
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_libresocsim_converter0_counter
connect \B 1'1
- connect \Y $add$ls180.v:2819$22_Y
+ connect \Y $add$ls180.v:2815$22_Y
end
- attribute \src "ls180.v:2879.68-2879.110"
- cell $add $add$ls180.v:2879$33
+ attribute \src "ls180.v:2875.68-2875.110"
+ cell $add $add$ls180.v:2875$33
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_libresocsim_converter1_counter
connect \B 1'1
- connect \Y $add$ls180.v:2879$33_Y
+ connect \Y $add$ls180.v:2875$33_Y
end
- attribute \src "ls180.v:2939.68-2939.110"
- cell $add $add$ls180.v:2939$44
+ attribute \src "ls180.v:2935.68-2935.110"
+ cell $add $add$ls180.v:2935$44
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_libresocsim_converter2_counter
connect \B 1'1
- connect \Y $add$ls180.v:2939$44_Y
+ connect \Y $add$ls180.v:2935$44_Y
end
- attribute \src "ls180.v:4072.54-4072.83"
- cell $add $add$ls180.v:4072$537
+ attribute \src "ls180.v:4068.54-4068.83"
+ cell $add $add$ls180.v:4068$537
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_converter_counter
connect \B 1'1
- connect \Y $add$ls180.v:4072$537_Y
+ connect \Y $add$ls180.v:4068$537_Y
end
- attribute \src "ls180.v:4172.36-4172.89"
- cell $add $add$ls180.v:4172$583
+ attribute \src "ls180.v:4168.36-4168.89"
+ cell $add $add$ls180.v:4168$583
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 5
connect \A \main_uart_tx_fifo_level0
connect \B \main_uart_tx_fifo_readable
- connect \Y $add$ls180.v:4172$583_Y
+ connect \Y $add$ls180.v:4168$583_Y
end
- attribute \src "ls180.v:4202.36-4202.89"
- cell $add $add$ls180.v:4202$594
+ attribute \src "ls180.v:4198.36-4198.89"
+ cell $add $add$ls180.v:4198$594
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 5
connect \A \main_uart_rx_fifo_level0
connect \B \main_uart_rx_fifo_readable
- connect \Y $add$ls180.v:4202$594_Y
+ connect \Y $add$ls180.v:4198$594_Y
end
- attribute \src "ls180.v:4257.54-4257.83"
- cell $add $add$ls180.v:4257$607
+ attribute \src "ls180.v:4253.54-4253.83"
+ cell $add $add$ls180.v:4253$607
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \main_spimaster27_count
connect \B 1'1
- connect \Y $add$ls180.v:4257$607_Y
+ connect \Y $add$ls180.v:4253$607_Y
end
- attribute \src "ls180.v:4316.52-4316.79"
- cell $add $add$ls180.v:4316$615
+ attribute \src "ls180.v:4312.52-4312.79"
+ cell $add $add$ls180.v:4312$615
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \main_spisdcard_count
connect \B 1'1
- connect \Y $add$ls180.v:4316$615_Y
+ connect \Y $add$ls180.v:4312$615_Y
end
- attribute \src "ls180.v:4420.58-4420.86"
- cell $add $add$ls180.v:4420$643
+ attribute \src "ls180.v:4416.58-4416.86"
+ cell $add $add$ls180.v:4416$643
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 8
connect \A \main_sdphy_init_count
connect \B 1'1
- connect \Y $add$ls180.v:4420$643_Y
+ connect \Y $add$ls180.v:4416$643_Y
end
- attribute \src "ls180.v:4477.58-4477.86"
- cell $add $add$ls180.v:4477$646
+ attribute \src "ls180.v:4473.58-4473.86"
+ cell $add $add$ls180.v:4473$646
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 8
connect \A \main_sdphy_cmdw_count
connect \B 1'1
- connect \Y $add$ls180.v:4477$646_Y
+ connect \Y $add$ls180.v:4473$646_Y
end
- attribute \src "ls180.v:4494.58-4494.86"
- cell $add $add$ls180.v:4494$648
+ attribute \src "ls180.v:4490.58-4490.86"
+ cell $add $add$ls180.v:4490$648
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 8
connect \A \main_sdphy_cmdw_count
connect \B 1'1
- connect \Y $add$ls180.v:4494$648_Y
+ connect \Y $add$ls180.v:4490$648_Y
end
- attribute \src "ls180.v:4587.59-4587.87"
- cell $add $add$ls180.v:4587$665
+ attribute \src "ls180.v:4583.59-4583.87"
+ cell $add $add$ls180.v:4583$665
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 8
connect \A \main_sdphy_cmdr_count
connect \B 1'1
- connect \Y $add$ls180.v:4587$665_Y
+ connect \Y $add$ls180.v:4583$665_Y
end
- attribute \src "ls180.v:4612.59-4612.87"
- cell $add $add$ls180.v:4612$668
+ attribute \src "ls180.v:4608.59-4608.87"
+ cell $add $add$ls180.v:4608$668
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 8
connect \A \main_sdphy_cmdr_count
connect \B 1'1
- connect \Y $add$ls180.v:4612$668_Y
+ connect \Y $add$ls180.v:4608$668_Y
end
- attribute \src "ls180.v:4734.53-4734.82"
- cell $add $add$ls180.v:4734$685
+ attribute \src "ls180.v:4730.53-4730.82"
+ cell $add $add$ls180.v:4730$685
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 8
connect \A \main_sdphy_dataw_count
connect \B 1'1
- connect \Y $add$ls180.v:4734$685_Y
+ connect \Y $add$ls180.v:4730$685_Y
end
- attribute \src "ls180.v:4845.65-4845.114"
- cell $add $add$ls180.v:4845$699
+ attribute \src "ls180.v:4841.65-4841.114"
+ cell $add $add$ls180.v:4841$699
parameter \A_SIGNED 0
parameter \A_WIDTH 10
parameter \B_SIGNED 0
parameter \Y_WIDTH 10
connect \A \main_sdphy_datar_sink_payload_block_length
connect \B 4'1000
- connect \Y $add$ls180.v:4845$699_Y
+ connect \Y $add$ls180.v:4841$699_Y
end
- attribute \src "ls180.v:4850.62-4850.91"
- cell $add $add$ls180.v:4850$702
+ attribute \src "ls180.v:4846.62-4846.91"
+ cell $add $add$ls180.v:4846$702
parameter \A_SIGNED 0
parameter \A_WIDTH 10
parameter \B_SIGNED 0
parameter \Y_WIDTH 10
connect \A \main_sdphy_datar_count
connect \B 1'1
- connect \Y $add$ls180.v:4850$702_Y
+ connect \Y $add$ls180.v:4846$702_Y
end
- attribute \src "ls180.v:4876.61-4876.90"
- cell $add $add$ls180.v:4876$705
+ attribute \src "ls180.v:4872.61-4872.90"
+ cell $add $add$ls180.v:4872$705
parameter \A_SIGNED 0
parameter \A_WIDTH 10
parameter \B_SIGNED 0
parameter \Y_WIDTH 10
connect \A \main_sdphy_datar_count
connect \B 1'1
- connect \Y $add$ls180.v:4876$705_Y
+ connect \Y $add$ls180.v:4872$705_Y
end
- attribute \src "ls180.v:5080.80-5080.117"
- cell $add $add$ls180.v:5080$890
+ attribute \src "ls180.v:5076.80-5076.117"
+ cell $add $add$ls180.v:5076$890
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \main_sdcore_crc16_inserter_cnt
connect \B 1'1
- connect \Y $add$ls180.v:5080$890_Y
+ connect \Y $add$ls180.v:5076$890_Y
end
- attribute \src "ls180.v:5274.54-5274.82"
- cell $add $add$ls180.v:5274$965
+ attribute \src "ls180.v:5270.54-5270.82"
+ cell $add $add$ls180.v:5270$965
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \main_sdcore_cmd_count
connect \B 1'1
- connect \Y $add$ls180.v:5274$965_Y
+ connect \Y $add$ls180.v:5270$965_Y
end
- attribute \src "ls180.v:5326.55-5326.84"
- cell $add $add$ls180.v:5326$975
+ attribute \src "ls180.v:5322.55-5322.84"
+ cell $add $add$ls180.v:5322$975
parameter \A_SIGNED 0
parameter \A_WIDTH 32
parameter \B_SIGNED 0
parameter \Y_WIDTH 32
connect \A \main_sdcore_data_count
connect \B 1'1
- connect \Y $add$ls180.v:5326$975_Y
+ connect \Y $add$ls180.v:5322$975_Y
end
- attribute \src "ls180.v:5352.57-5352.86"
- cell $add $add$ls180.v:5352$983
+ attribute \src "ls180.v:5348.57-5348.86"
+ cell $add $add$ls180.v:5348$983
parameter \A_SIGNED 0
parameter \A_WIDTH 32
parameter \B_SIGNED 0
parameter \Y_WIDTH 32
connect \A \main_sdcore_data_count
connect \B 1'1
- connect \Y $add$ls180.v:5352$983_Y
+ connect \Y $add$ls180.v:5348$983_Y
end
- attribute \src "ls180.v:5473.51-5473.134"
- cell $add $add$ls180.v:5473$999
+ attribute \src "ls180.v:5469.51-5469.134"
+ cell $add $add$ls180.v:5469$999
parameter \A_SIGNED 0
parameter \A_WIDTH 32
parameter \B_SIGNED 0
parameter \Y_WIDTH 32
connect \A \main_sdblock2mem_wishbonedmawriter_base
connect \B \main_sdblock2mem_wishbonedmawriter_offset
- connect \Y $add$ls180.v:5473$999_Y
+ connect \Y $add$ls180.v:5469$999_Y
end
- attribute \src "ls180.v:5476.77-5476.125"
- cell $add $add$ls180.v:5476$1001
+ attribute \src "ls180.v:5472.77-5472.125"
+ cell $add $add$ls180.v:5472$1001
parameter \A_SIGNED 0
parameter \A_WIDTH 32
parameter \B_SIGNED 0
parameter \Y_WIDTH 32
connect \A \main_sdblock2mem_wishbonedmawriter_offset
connect \B 1'1
- connect \Y $add$ls180.v:5476$1001_Y
+ connect \Y $add$ls180.v:5472$1001_Y
end
- attribute \src "ls180.v:5569.50-5569.105"
- cell $add $add$ls180.v:5569$1010
+ attribute \src "ls180.v:5565.50-5565.105"
+ cell $add $add$ls180.v:5565$1010
parameter \A_SIGNED 0
parameter \A_WIDTH 32
parameter \B_SIGNED 0
parameter \Y_WIDTH 32
connect \A \main_sdmem2block_dma_base
connect \B \main_sdmem2block_dma_offset
- connect \Y $add$ls180.v:5569$1010_Y
+ connect \Y $add$ls180.v:5565$1010_Y
end
- attribute \src "ls180.v:5571.77-5571.111"
- cell $add $add$ls180.v:5571$1011
+ attribute \src "ls180.v:5567.77-5567.111"
+ cell $add $add$ls180.v:5567$1011
parameter \A_SIGNED 0
parameter \A_WIDTH 32
parameter \B_SIGNED 0
parameter \Y_WIDTH 32
connect \A \main_sdmem2block_dma_offset
connect \B 1'1
- connect \Y $add$ls180.v:5571$1011_Y
+ connect \Y $add$ls180.v:5567$1011_Y
end
- attribute \src "ls180.v:7491.36-7491.70"
- cell $add $add$ls180.v:7491$2403
+ attribute \src "ls180.v:7487.36-7487.70"
+ cell $add $add$ls180.v:7487$2403
parameter \A_SIGNED 0
parameter \A_WIDTH 32
parameter \B_SIGNED 0
parameter \Y_WIDTH 32
connect \A \main_libresocsim_bus_errors
connect \B 1'1
- connect \Y $add$ls180.v:7491$2403_Y
+ connect \Y $add$ls180.v:7487$2403_Y
end
- attribute \src "ls180.v:7576.37-7576.72"
- cell $add $add$ls180.v:7576$2424
+ attribute \src "ls180.v:7572.37-7572.72"
+ cell $add $add$ls180.v:7572$2424
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \main_sdram_sequencer_counter
connect \B 1'1
- connect \Y $add$ls180.v:7576$2424_Y
+ connect \Y $add$ls180.v:7572$2424_Y
end
- attribute \src "ls180.v:7593.60-7593.119"
- cell $add $add$ls180.v:7593$2428
+ attribute \src "ls180.v:7589.60-7589.119"
+ cell $add $add$ls180.v:7589$2428
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_produce
connect \B 1'1
- connect \Y $add$ls180.v:7593$2428_Y
+ connect \Y $add$ls180.v:7589$2428_Y
end
- attribute \src "ls180.v:7596.60-7596.119"
- cell $add $add$ls180.v:7596$2429
+ attribute \src "ls180.v:7592.60-7592.119"
+ cell $add $add$ls180.v:7592$2429
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_consume
connect \B 1'1
- connect \Y $add$ls180.v:7596$2429_Y
+ connect \Y $add$ls180.v:7592$2429_Y
end
- attribute \src "ls180.v:7600.59-7600.116"
- cell $add $add$ls180.v:7600$2434
+ attribute \src "ls180.v:7596.59-7596.116"
+ cell $add $add$ls180.v:7596$2434
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_level
connect \B 1'1
- connect \Y $add$ls180.v:7600$2434_Y
+ connect \Y $add$ls180.v:7596$2434_Y
end
- attribute \src "ls180.v:7639.60-7639.119"
- cell $add $add$ls180.v:7639$2444
+ attribute \src "ls180.v:7635.60-7635.119"
+ cell $add $add$ls180.v:7635$2444
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_produce
connect \B 1'1
- connect \Y $add$ls180.v:7639$2444_Y
+ connect \Y $add$ls180.v:7635$2444_Y
end
- attribute \src "ls180.v:7642.60-7642.119"
- cell $add $add$ls180.v:7642$2445
+ attribute \src "ls180.v:7638.60-7638.119"
+ cell $add $add$ls180.v:7638$2445
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_consume
connect \B 1'1
- connect \Y $add$ls180.v:7642$2445_Y
+ connect \Y $add$ls180.v:7638$2445_Y
end
- attribute \src "ls180.v:7646.59-7646.116"
- cell $add $add$ls180.v:7646$2450
+ attribute \src "ls180.v:7642.59-7642.116"
+ cell $add $add$ls180.v:7642$2450
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_level
connect \B 1'1
- connect \Y $add$ls180.v:7646$2450_Y
+ connect \Y $add$ls180.v:7642$2450_Y
end
- attribute \src "ls180.v:7685.60-7685.119"
- cell $add $add$ls180.v:7685$2460
+ attribute \src "ls180.v:7681.60-7681.119"
+ cell $add $add$ls180.v:7681$2460
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_produce
connect \B 1'1
- connect \Y $add$ls180.v:7685$2460_Y
+ connect \Y $add$ls180.v:7681$2460_Y
end
- attribute \src "ls180.v:7688.60-7688.119"
- cell $add $add$ls180.v:7688$2461
+ attribute \src "ls180.v:7684.60-7684.119"
+ cell $add $add$ls180.v:7684$2461
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_consume
connect \B 1'1
- connect \Y $add$ls180.v:7688$2461_Y
+ connect \Y $add$ls180.v:7684$2461_Y
end
- attribute \src "ls180.v:7692.59-7692.116"
- cell $add $add$ls180.v:7692$2466
+ attribute \src "ls180.v:7688.59-7688.116"
+ cell $add $add$ls180.v:7688$2466
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_level
connect \B 1'1
- connect \Y $add$ls180.v:7692$2466_Y
+ connect \Y $add$ls180.v:7688$2466_Y
end
- attribute \src "ls180.v:7731.60-7731.119"
- cell $add $add$ls180.v:7731$2476
+ attribute \src "ls180.v:7727.60-7727.119"
+ cell $add $add$ls180.v:7727$2476
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_produce
connect \B 1'1
- connect \Y $add$ls180.v:7731$2476_Y
+ connect \Y $add$ls180.v:7727$2476_Y
end
- attribute \src "ls180.v:7734.60-7734.119"
- cell $add $add$ls180.v:7734$2477
+ attribute \src "ls180.v:7730.60-7730.119"
+ cell $add $add$ls180.v:7730$2477
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_consume
connect \B 1'1
- connect \Y $add$ls180.v:7734$2477_Y
+ connect \Y $add$ls180.v:7730$2477_Y
end
- attribute \src "ls180.v:7738.59-7738.116"
- cell $add $add$ls180.v:7738$2482
+ attribute \src "ls180.v:7734.59-7734.116"
+ cell $add $add$ls180.v:7734$2482
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_level
connect \B 1'1
- connect \Y $add$ls180.v:7738$2482_Y
+ connect \Y $add$ls180.v:7734$2482_Y
end
- attribute \src "ls180.v:7968.34-7968.66"
- cell $add $add$ls180.v:7968$2536
+ attribute \src "ls180.v:7964.34-7964.66"
+ cell $add $add$ls180.v:7964$2536
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \main_uart_phy_tx_bitcount
connect \B 1'1
- connect \Y $add$ls180.v:7968$2536_Y
+ connect \Y $add$ls180.v:7964$2536_Y
end
- attribute \src "ls180.v:7984.73-7984.131"
- cell $add $add$ls180.v:7984$2539
+ attribute \src "ls180.v:7980.73-7980.131"
+ cell $add $add$ls180.v:7980$2539
parameter \A_SIGNED 0
parameter \A_WIDTH 32
parameter \B_SIGNED 0
parameter \Y_WIDTH 33
connect \A \main_uart_phy_phase_accumulator_tx
connect \B \main_uart_phy_storage
- connect \Y $add$ls180.v:7984$2539_Y
+ connect \Y $add$ls180.v:7980$2539_Y
end
- attribute \src "ls180.v:7997.34-7997.66"
- cell $add $add$ls180.v:7997$2543
+ attribute \src "ls180.v:7993.34-7993.66"
+ cell $add $add$ls180.v:7993$2543
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \main_uart_phy_rx_bitcount
connect \B 1'1
- connect \Y $add$ls180.v:7997$2543_Y
+ connect \Y $add$ls180.v:7993$2543_Y
end
- attribute \src "ls180.v:8016.73-8016.131"
- cell $add $add$ls180.v:8016$2546
+ attribute \src "ls180.v:8012.73-8012.131"
+ cell $add $add$ls180.v:8012$2546
parameter \A_SIGNED 0
parameter \A_WIDTH 32
parameter \B_SIGNED 0
parameter \Y_WIDTH 33
connect \A \main_uart_phy_phase_accumulator_rx
connect \B \main_uart_phy_storage
- connect \Y $add$ls180.v:8016$2546_Y
+ connect \Y $add$ls180.v:8012$2546_Y
end
- attribute \src "ls180.v:8042.33-8042.65"
- cell $add $add$ls180.v:8042$2554
+ attribute \src "ls180.v:8038.33-8038.65"
+ cell $add $add$ls180.v:8038$2554
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \main_uart_tx_fifo_produce
connect \B 1'1
- connect \Y $add$ls180.v:8042$2554_Y
+ connect \Y $add$ls180.v:8038$2554_Y
end
- attribute \src "ls180.v:8045.33-8045.65"
- cell $add $add$ls180.v:8045$2555
+ attribute \src "ls180.v:8041.33-8041.65"
+ cell $add $add$ls180.v:8041$2555
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \main_uart_tx_fifo_consume
connect \B 1'1
- connect \Y $add$ls180.v:8045$2555_Y
+ connect \Y $add$ls180.v:8041$2555_Y
end
- attribute \src "ls180.v:8049.33-8049.64"
- cell $add $add$ls180.v:8049$2560
+ attribute \src "ls180.v:8045.33-8045.64"
+ cell $add $add$ls180.v:8045$2560
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 5
connect \A \main_uart_tx_fifo_level0
connect \B 1'1
- connect \Y $add$ls180.v:8049$2560_Y
+ connect \Y $add$ls180.v:8045$2560_Y
end
- attribute \src "ls180.v:8064.33-8064.65"
- cell $add $add$ls180.v:8064$2565
+ attribute \src "ls180.v:8060.33-8060.65"
+ cell $add $add$ls180.v:8060$2565
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \main_uart_rx_fifo_produce
connect \B 1'1
- connect \Y $add$ls180.v:8064$2565_Y
+ connect \Y $add$ls180.v:8060$2565_Y
end
- attribute \src "ls180.v:8067.33-8067.65"
- cell $add $add$ls180.v:8067$2566
+ attribute \src "ls180.v:8063.33-8063.65"
+ cell $add $add$ls180.v:8063$2566
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \main_uart_rx_fifo_consume
connect \B 1'1
- connect \Y $add$ls180.v:8067$2566_Y
+ connect \Y $add$ls180.v:8063$2566_Y
end
- attribute \src "ls180.v:8071.33-8071.64"
- cell $add $add$ls180.v:8071$2571
+ attribute \src "ls180.v:8067.33-8067.64"
+ cell $add $add$ls180.v:8067$2571
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 5
connect \A \main_uart_rx_fifo_level0
connect \B 1'1
- connect \Y $add$ls180.v:8071$2571_Y
+ connect \Y $add$ls180.v:8067$2571_Y
end
- attribute \src "ls180.v:8092.35-8092.70"
- cell $add $add$ls180.v:8092$2573
+ attribute \src "ls180.v:8088.35-8088.70"
+ cell $add $add$ls180.v:8088$2573
parameter \A_SIGNED 0
parameter \A_WIDTH 16
parameter \B_SIGNED 0
parameter \Y_WIDTH 16
connect \A \main_spimaster30_clk_divider
connect \B 1'1
- connect \Y $add$ls180.v:8092$2573_Y
+ connect \Y $add$ls180.v:8088$2573_Y
end
- attribute \src "ls180.v:8127.34-8127.68"
- cell $add $add$ls180.v:8127$2578
+ attribute \src "ls180.v:8123.34-8123.68"
+ cell $add $add$ls180.v:8123$2578
parameter \A_SIGNED 0
parameter \A_WIDTH 16
parameter \B_SIGNED 0
parameter \Y_WIDTH 16
connect \A \main_spisdcard_clk_divider1
connect \B 1'1
- connect \Y $add$ls180.v:8127$2578_Y
+ connect \Y $add$ls180.v:8123$2578_Y
end
- attribute \src "ls180.v:8163.25-8163.49"
- cell $add $add$ls180.v:8163$2583
+ attribute \src "ls180.v:8159.25-8159.49"
+ cell $add $add$ls180.v:8159$2583
parameter \A_SIGNED 0
parameter \A_WIDTH 32
parameter \B_SIGNED 0
parameter \Y_WIDTH 32
connect \A \main_pwm0_counter
connect \B 1'1
- connect \Y $add$ls180.v:8163$2583_Y
+ connect \Y $add$ls180.v:8159$2583_Y
end
- attribute \src "ls180.v:8177.25-8177.49"
- cell $add $add$ls180.v:8177$2587
+ attribute \src "ls180.v:8173.25-8173.49"
+ cell $add $add$ls180.v:8173$2587
parameter \A_SIGNED 0
parameter \A_WIDTH 32
parameter \B_SIGNED 0
parameter \Y_WIDTH 32
connect \A \main_pwm1_counter
connect \B 1'1
- connect \Y $add$ls180.v:8177$2587_Y
+ connect \Y $add$ls180.v:8173$2587_Y
end
- attribute \src "ls180.v:8191.31-8191.61"
- cell $add $add$ls180.v:8191$2592
+ attribute \src "ls180.v:8187.31-8187.61"
+ cell $add $add$ls180.v:8187$2592
parameter \A_SIGNED 0
parameter \A_WIDTH 9
parameter \B_SIGNED 0
parameter \Y_WIDTH 9
connect \A \main_sdphy_clocker_clks
connect \B 1'1
- connect \Y $add$ls180.v:8191$2592_Y
+ connect \Y $add$ls180.v:8187$2592_Y
end
- attribute \src "ls180.v:8214.45-8214.88"
- cell $add $add$ls180.v:8214$2596
+ attribute \src "ls180.v:8210.45-8210.88"
+ cell $add $add$ls180.v:8210$2596
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \main_sdphy_cmdr_cmdr_converter_demux
connect \B 1'1
- connect \Y $add$ls180.v:8214$2596_Y
+ connect \Y $add$ls180.v:8210$2596_Y
end
- attribute \src "ls180.v:8260.71-8260.114"
- cell $add $add$ls180.v:8260$2602
+ attribute \src "ls180.v:8256.71-8256.114"
+ cell $add $add$ls180.v:8256$2602
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \main_sdphy_cmdr_cmdr_converter_demux
connect \B 1'1
- connect \Y $add$ls180.v:8260$2602_Y
+ connect \Y $add$ls180.v:8256$2602_Y
end
- attribute \src "ls180.v:8295.46-8295.90"
- cell $add $add$ls180.v:8295$2608
+ attribute \src "ls180.v:8291.46-8291.90"
+ cell $add $add$ls180.v:8291$2608
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \main_sdphy_dataw_crcr_converter_demux
connect \B 1'1
- connect \Y $add$ls180.v:8295$2608_Y
+ connect \Y $add$ls180.v:8291$2608_Y
end
- attribute \src "ls180.v:8341.72-8341.116"
- cell $add $add$ls180.v:8341$2614
+ attribute \src "ls180.v:8337.72-8337.116"
+ cell $add $add$ls180.v:8337$2614
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \main_sdphy_dataw_crcr_converter_demux
connect \B 1'1
- connect \Y $add$ls180.v:8341$2614_Y
+ connect \Y $add$ls180.v:8337$2614_Y
end
- attribute \src "ls180.v:8374.47-8374.92"
- cell $add $add$ls180.v:8374$2620
+ attribute \src "ls180.v:8370.47-8370.92"
+ cell $add $add$ls180.v:8370$2620
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdphy_datar_datar_converter_demux
connect \B 1'1
- connect \Y $add$ls180.v:8374$2620_Y
+ connect \Y $add$ls180.v:8370$2620_Y
end
- attribute \src "ls180.v:8402.73-8402.118"
- cell $add $add$ls180.v:8402$2626
+ attribute \src "ls180.v:8398.73-8398.118"
+ cell $add $add$ls180.v:8398$2626
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 2
connect \A \main_sdphy_datar_datar_converter_demux
connect \B 1'1
- connect \Y $add$ls180.v:8402$2626_Y
+ connect \Y $add$ls180.v:8398$2626_Y
end
- attribute \src "ls180.v:8514.39-8514.75"
- cell $add $add$ls180.v:8514$2639
+ attribute \src "ls180.v:8510.39-8510.75"
+ cell $add $add$ls180.v:8510$2639
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \main_sdcore_crc16_checker_cnt
connect \B 1'1
- connect \Y $add$ls180.v:8514$2639_Y
+ connect \Y $add$ls180.v:8510$2639_Y
end
- attribute \src "ls180.v:8575.37-8575.73"
- cell $add $add$ls180.v:8575$2643
+ attribute \src "ls180.v:8571.37-8571.73"
+ cell $add $add$ls180.v:8571$2643
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 5
connect \A \main_sdblock2mem_fifo_produce
connect \B 1'1
- connect \Y $add$ls180.v:8575$2643_Y
+ connect \Y $add$ls180.v:8571$2643_Y
end
- attribute \src "ls180.v:8578.37-8578.73"
- cell $add $add$ls180.v:8578$2644
+ attribute \src "ls180.v:8574.37-8574.73"
+ cell $add $add$ls180.v:8574$2644
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 5
connect \A \main_sdblock2mem_fifo_consume
connect \B 1'1
- connect \Y $add$ls180.v:8578$2644_Y
+ connect \Y $add$ls180.v:8574$2644_Y
end
- attribute \src "ls180.v:8582.36-8582.70"
- cell $add $add$ls180.v:8582$2649
+ attribute \src "ls180.v:8578.36-8578.70"
+ cell $add $add$ls180.v:8578$2649
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 6
connect \A \main_sdblock2mem_fifo_level
connect \B 1'1
- connect \Y $add$ls180.v:8582$2649_Y
+ connect \Y $add$ls180.v:8578$2649_Y
end
- attribute \src "ls180.v:8597.41-8597.80"
- cell $add $add$ls180.v:8597$2653
+ attribute \src "ls180.v:8593.41-8593.80"
+ cell $add $add$ls180.v:8593$2653
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 2
connect \A \main_sdblock2mem_converter_demux
connect \B 1'1
- connect \Y $add$ls180.v:8597$2653_Y
+ connect \Y $add$ls180.v:8593$2653_Y
end
- attribute \src "ls180.v:8631.67-8631.106"
- cell $add $add$ls180.v:8631$2659
+ attribute \src "ls180.v:8627.67-8627.106"
+ cell $add $add$ls180.v:8627$2659
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \main_sdblock2mem_converter_demux
connect \B 1'1
- connect \Y $add$ls180.v:8631$2659_Y
+ connect \Y $add$ls180.v:8627$2659_Y
end
- attribute \src "ls180.v:8657.39-8657.76"
- cell $add $add$ls180.v:8657$2661
+ attribute \src "ls180.v:8653.39-8653.76"
+ cell $add $add$ls180.v:8653$2661
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 2
connect \A \main_sdmem2block_converter_mux
connect \B 1'1
- connect \Y $add$ls180.v:8657$2661_Y
+ connect \Y $add$ls180.v:8653$2661_Y
end
- attribute \src "ls180.v:8661.37-8661.73"
- cell $add $add$ls180.v:8661$2665
+ attribute \src "ls180.v:8657.37-8657.73"
+ cell $add $add$ls180.v:8657$2665
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 5
connect \A \main_sdmem2block_fifo_produce
connect \B 1'1
- connect \Y $add$ls180.v:8661$2665_Y
+ connect \Y $add$ls180.v:8657$2665_Y
end
- attribute \src "ls180.v:8664.37-8664.73"
- cell $add $add$ls180.v:8664$2666
+ attribute \src "ls180.v:8660.37-8660.73"
+ cell $add $add$ls180.v:8660$2666
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 5
connect \A \main_sdmem2block_fifo_consume
connect \B 1'1
- connect \Y $add$ls180.v:8664$2666_Y
+ connect \Y $add$ls180.v:8660$2666_Y
end
- attribute \src "ls180.v:8668.36-8668.70"
- cell $add $add$ls180.v:8668$2671
+ attribute \src "ls180.v:8664.36-8664.70"
+ cell $add $add$ls180.v:8664$2671
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 6
connect \A \main_sdmem2block_fifo_level
connect \B 1'1
- connect \Y $add$ls180.v:8668$2671_Y
+ connect \Y $add$ls180.v:8664$2671_Y
end
- attribute \src "ls180.v:2813.9-2813.80"
- cell $and $and$ls180.v:2813$17
+ attribute \src "ls180.v:2809.9-2809.80"
+ cell $and $and$ls180.v:2809$17
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_libresocsim_libresoc_ibus_stb
connect \B \main_libresocsim_libresoc_ibus_cyc
- connect \Y $and$ls180.v:2813$17_Y
+ connect \Y $and$ls180.v:2809$17_Y
end
- attribute \src "ls180.v:2831.9-2831.80"
- cell $and $and$ls180.v:2831$24
+ attribute \src "ls180.v:2827.9-2827.80"
+ cell $and $and$ls180.v:2827$24
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_libresocsim_libresoc_ibus_stb
connect \B \main_libresocsim_libresoc_ibus_cyc
- connect \Y $and$ls180.v:2831$24_Y
+ connect \Y $and$ls180.v:2827$24_Y
end
- attribute \src "ls180.v:2873.9-2873.80"
- cell $and $and$ls180.v:2873$28
+ attribute \src "ls180.v:2869.9-2869.80"
+ cell $and $and$ls180.v:2869$28
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_libresocsim_libresoc_dbus_stb
connect \B \main_libresocsim_libresoc_dbus_cyc
- connect \Y $and$ls180.v:2873$28_Y
+ connect \Y $and$ls180.v:2869$28_Y
end
- attribute \src "ls180.v:2891.9-2891.80"
- cell $and $and$ls180.v:2891$35
+ attribute \src "ls180.v:2887.9-2887.80"
+ cell $and $and$ls180.v:2887$35
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_libresocsim_libresoc_dbus_stb
connect \B \main_libresocsim_libresoc_dbus_cyc
- connect \Y $and$ls180.v:2891$35_Y
+ connect \Y $and$ls180.v:2887$35_Y
end
- attribute \src "ls180.v:2933.9-2933.86"
- cell $and $and$ls180.v:2933$39
+ attribute \src "ls180.v:2929.9-2929.86"
+ cell $and $and$ls180.v:2929$39
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_libresocsim_libresoc_jtag_wb_stb
connect \B \main_libresocsim_libresoc_jtag_wb_cyc
- connect \Y $and$ls180.v:2933$39_Y
+ connect \Y $and$ls180.v:2929$39_Y
end
- attribute \src "ls180.v:2951.9-2951.86"
- cell $and $and$ls180.v:2951$46
+ attribute \src "ls180.v:2947.9-2947.86"
+ cell $and $and$ls180.v:2947$46
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_libresocsim_libresoc_jtag_wb_stb
connect \B \main_libresocsim_libresoc_jtag_wb_cyc
- connect \Y $and$ls180.v:2951$46_Y
+ connect \Y $and$ls180.v:2947$46_Y
end
- attribute \src "ls180.v:2961.31-2961.90"
- cell $and $and$ls180.v:2961$48
+ attribute \src "ls180.v:2957.31-2957.90"
+ cell $and $and$ls180.v:2957$48
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_libresocsim_ram_bus_cyc
connect \B \main_libresocsim_ram_bus_stb
- connect \Y $and$ls180.v:2961$48_Y
+ connect \Y $and$ls180.v:2957$48_Y
end
- attribute \src "ls180.v:2961.30-2961.121"
- cell $and $and$ls180.v:2961$49
+ attribute \src "ls180.v:2957.30-2957.121"
+ cell $and $and$ls180.v:2957$49
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:2961$48_Y
+ connect \A $and$ls180.v:2957$48_Y
connect \B \main_libresocsim_ram_bus_we
- connect \Y $and$ls180.v:2961$49_Y
+ connect \Y $and$ls180.v:2957$49_Y
end
- attribute \src "ls180.v:2961.29-2961.156"
- cell $and $and$ls180.v:2961$50
+ attribute \src "ls180.v:2957.29-2957.156"
+ cell $and $and$ls180.v:2957$50
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:2961$49_Y
+ connect \A $and$ls180.v:2957$49_Y
connect \B \main_libresocsim_ram_bus_sel [0]
- connect \Y $and$ls180.v:2961$50_Y
+ connect \Y $and$ls180.v:2957$50_Y
end
- attribute \src "ls180.v:2962.31-2962.90"
- cell $and $and$ls180.v:2962$51
+ attribute \src "ls180.v:2958.31-2958.90"
+ cell $and $and$ls180.v:2958$51
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_libresocsim_ram_bus_cyc
connect \B \main_libresocsim_ram_bus_stb
- connect \Y $and$ls180.v:2962$51_Y
+ connect \Y $and$ls180.v:2958$51_Y
end
- attribute \src "ls180.v:2962.30-2962.121"
- cell $and $and$ls180.v:2962$52
+ attribute \src "ls180.v:2958.30-2958.121"
+ cell $and $and$ls180.v:2958$52
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:2962$51_Y
+ connect \A $and$ls180.v:2958$51_Y
connect \B \main_libresocsim_ram_bus_we
- connect \Y $and$ls180.v:2962$52_Y
+ connect \Y $and$ls180.v:2958$52_Y
end
- attribute \src "ls180.v:2962.29-2962.156"
- cell $and $and$ls180.v:2962$53
+ attribute \src "ls180.v:2958.29-2958.156"
+ cell $and $and$ls180.v:2958$53
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:2962$52_Y
+ connect \A $and$ls180.v:2958$52_Y
connect \B \main_libresocsim_ram_bus_sel [1]
- connect \Y $and$ls180.v:2962$53_Y
+ connect \Y $and$ls180.v:2958$53_Y
end
- attribute \src "ls180.v:2963.31-2963.90"
- cell $and $and$ls180.v:2963$54
+ attribute \src "ls180.v:2959.31-2959.90"
+ cell $and $and$ls180.v:2959$54
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_libresocsim_ram_bus_cyc
connect \B \main_libresocsim_ram_bus_stb
- connect \Y $and$ls180.v:2963$54_Y
+ connect \Y $and$ls180.v:2959$54_Y
end
- attribute \src "ls180.v:2963.30-2963.121"
- cell $and $and$ls180.v:2963$55
+ attribute \src "ls180.v:2959.30-2959.121"
+ cell $and $and$ls180.v:2959$55
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:2963$54_Y
+ connect \A $and$ls180.v:2959$54_Y
connect \B \main_libresocsim_ram_bus_we
- connect \Y $and$ls180.v:2963$55_Y
+ connect \Y $and$ls180.v:2959$55_Y
end
- attribute \src "ls180.v:2963.29-2963.156"
- cell $and $and$ls180.v:2963$56
+ attribute \src "ls180.v:2959.29-2959.156"
+ cell $and $and$ls180.v:2959$56
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:2963$55_Y
+ connect \A $and$ls180.v:2959$55_Y
connect \B \main_libresocsim_ram_bus_sel [2]
- connect \Y $and$ls180.v:2963$56_Y
+ connect \Y $and$ls180.v:2959$56_Y
end
- attribute \src "ls180.v:2964.31-2964.90"
- cell $and $and$ls180.v:2964$57
+ attribute \src "ls180.v:2960.31-2960.90"
+ cell $and $and$ls180.v:2960$57
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_libresocsim_ram_bus_cyc
connect \B \main_libresocsim_ram_bus_stb
- connect \Y $and$ls180.v:2964$57_Y
+ connect \Y $and$ls180.v:2960$57_Y
end
- attribute \src "ls180.v:2964.30-2964.121"
- cell $and $and$ls180.v:2964$58
+ attribute \src "ls180.v:2960.30-2960.121"
+ cell $and $and$ls180.v:2960$58
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:2964$57_Y
+ connect \A $and$ls180.v:2960$57_Y
connect \B \main_libresocsim_ram_bus_we
- connect \Y $and$ls180.v:2964$58_Y
+ connect \Y $and$ls180.v:2960$58_Y
end
- attribute \src "ls180.v:2964.29-2964.156"
- cell $and $and$ls180.v:2964$59
+ attribute \src "ls180.v:2960.29-2960.156"
+ cell $and $and$ls180.v:2960$59
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:2964$58_Y
+ connect \A $and$ls180.v:2960$58_Y
connect \B \main_libresocsim_ram_bus_sel [3]
- connect \Y $and$ls180.v:2964$59_Y
+ connect \Y $and$ls180.v:2960$59_Y
end
- attribute \src "ls180.v:2973.7-2973.89"
- cell $and $and$ls180.v:2973$62
+ attribute \src "ls180.v:2969.7-2969.89"
+ cell $and $and$ls180.v:2969$62
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_libresocsim_eventmanager_pending_re
connect \B \main_libresocsim_eventmanager_pending_r
- connect \Y $and$ls180.v:2973$62_Y
+ connect \Y $and$ls180.v:2969$62_Y
end
- attribute \src "ls180.v:2978.32-2978.111"
- cell $and $and$ls180.v:2978$63
+ attribute \src "ls180.v:2974.32-2974.111"
+ cell $and $and$ls180.v:2974$63
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_libresocsim_eventmanager_pending_w
connect \B \main_libresocsim_eventmanager_storage
- connect \Y $and$ls180.v:2978$63_Y
+ connect \Y $and$ls180.v:2974$63_Y
end
- attribute \src "ls180.v:3092.40-3092.99"
- cell $and $and$ls180.v:3092$70
+ attribute \src "ls180.v:3088.40-3088.99"
+ cell $and $and$ls180.v:3088$70
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_command_issue_re
connect \B \main_sdram_command_storage [4]
- connect \Y $and$ls180.v:3092$70_Y
+ connect \Y $and$ls180.v:3088$70_Y
end
- attribute \src "ls180.v:3093.40-3093.99"
- cell $and $and$ls180.v:3093$71
+ attribute \src "ls180.v:3089.40-3089.99"
+ cell $and $and$ls180.v:3089$71
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_command_issue_re
connect \B \main_sdram_command_storage [5]
- connect \Y $and$ls180.v:3093$71_Y
+ connect \Y $and$ls180.v:3089$71_Y
end
- attribute \src "ls180.v:3131.38-3131.103"
- cell $and $and$ls180.v:3131$77
+ attribute \src "ls180.v:3127.38-3127.103"
+ cell $and $and$ls180.v:3127$77
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_sequencer_done1
- connect \B $eq$ls180.v:3131$76_Y
- connect \Y $and$ls180.v:3131$77_Y
+ connect \B $eq$ls180.v:3127$76_Y
+ connect \Y $and$ls180.v:3127$77_Y
end
- attribute \src "ls180.v:3185.50-3185.119"
- cell $and $and$ls180.v:3185$85
+ attribute \src "ls180.v:3181.50-3181.119"
+ cell $and $and$ls180.v:3181$85
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine0_cmd_valid
connect \B \main_sdram_bankmachine0_cmd_ready
- connect \Y $and$ls180.v:3185$85_Y
+ connect \Y $and$ls180.v:3181$85_Y
end
- attribute \src "ls180.v:3185.49-3185.167"
- cell $and $and$ls180.v:3185$86
+ attribute \src "ls180.v:3181.49-3181.167"
+ cell $and $and$ls180.v:3181$86
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3185$85_Y
+ connect \A $and$ls180.v:3181$85_Y
connect \B \main_sdram_bankmachine0_cmd_payload_is_write
- connect \Y $and$ls180.v:3185$86_Y
+ connect \Y $and$ls180.v:3181$86_Y
end
- attribute \src "ls180.v:3186.49-3186.118"
- cell $and $and$ls180.v:3186$87
+ attribute \src "ls180.v:3182.49-3182.118"
+ cell $and $and$ls180.v:3182$87
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine0_cmd_valid
connect \B \main_sdram_bankmachine0_cmd_ready
- connect \Y $and$ls180.v:3186$87_Y
+ connect \Y $and$ls180.v:3182$87_Y
end
- attribute \src "ls180.v:3186.48-3186.154"
- cell $and $and$ls180.v:3186$88
+ attribute \src "ls180.v:3182.48-3182.154"
+ cell $and $and$ls180.v:3182$88
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3186$87_Y
+ connect \A $and$ls180.v:3182$87_Y
connect \B \main_sdram_bankmachine0_row_open
- connect \Y $and$ls180.v:3186$88_Y
+ connect \Y $and$ls180.v:3182$88_Y
end
- attribute \src "ls180.v:3187.50-3187.119"
- cell $and $and$ls180.v:3187$89
+ attribute \src "ls180.v:3183.50-3183.119"
+ cell $and $and$ls180.v:3183$89
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine0_cmd_valid
connect \B \main_sdram_bankmachine0_cmd_ready
- connect \Y $and$ls180.v:3187$89_Y
+ connect \Y $and$ls180.v:3183$89_Y
end
- attribute \src "ls180.v:3187.49-3187.155"
- cell $and $and$ls180.v:3187$90
+ attribute \src "ls180.v:3183.49-3183.155"
+ cell $and $and$ls180.v:3183$90
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3187$89_Y
+ connect \A $and$ls180.v:3183$89_Y
connect \B \main_sdram_bankmachine0_row_open
- connect \Y $and$ls180.v:3187$90_Y
+ connect \Y $and$ls180.v:3183$90_Y
end
- attribute \src "ls180.v:3190.7-3190.114"
- cell $and $and$ls180.v:3190$92
+ attribute \src "ls180.v:3186.7-3186.114"
+ cell $and $and$ls180.v:3186$92
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_source_valid
connect \B \main_sdram_bankmachine0_cmd_buffer_source_valid
- connect \Y $and$ls180.v:3190$92_Y
+ connect \Y $and$ls180.v:3186$92_Y
end
- attribute \src "ls180.v:3219.66-3219.246"
- cell $and $and$ls180.v:3219$98
+ attribute \src "ls180.v:3215.66-3215.246"
+ cell $and $and$ls180.v:3215$98
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we
- connect \B $or$ls180.v:3219$97_Y
- connect \Y $and$ls180.v:3219$98_Y
+ connect \B $or$ls180.v:3215$97_Y
+ connect \Y $and$ls180.v:3215$98_Y
end
- attribute \src "ls180.v:3220.64-3220.187"
- cell $and $and$ls180.v:3220$99
+ attribute \src "ls180.v:3216.64-3216.187"
+ cell $and $and$ls180.v:3216$99
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable
connect \B \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_re
- connect \Y $and$ls180.v:3220$99_Y
+ connect \Y $and$ls180.v:3216$99_Y
end
- attribute \src "ls180.v:3244.9-3244.86"
- cell $and $and$ls180.v:3244$105
+ attribute \src "ls180.v:3240.9-3240.86"
+ cell $and $and$ls180.v:3240$105
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine0_twtpcon_ready
connect \B \main_sdram_bankmachine0_trascon_ready
- connect \Y $and$ls180.v:3244$105_Y
+ connect \Y $and$ls180.v:3240$105_Y
end
- attribute \src "ls180.v:3256.9-3256.86"
- cell $and $and$ls180.v:3256$106
+ attribute \src "ls180.v:3252.9-3252.86"
+ cell $and $and$ls180.v:3252$106
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine0_twtpcon_ready
connect \B \main_sdram_bankmachine0_trascon_ready
- connect \Y $and$ls180.v:3256$106_Y
+ connect \Y $and$ls180.v:3252$106_Y
end
- attribute \src "ls180.v:3306.13-3306.87"
- cell $and $and$ls180.v:3306$108
+ attribute \src "ls180.v:3302.13-3302.87"
+ cell $and $and$ls180.v:3302$108
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine0_cmd_ready
connect \B \main_sdram_bankmachine0_auto_precharge
- connect \Y $and$ls180.v:3306$108_Y
+ connect \Y $and$ls180.v:3302$108_Y
end
- attribute \src "ls180.v:3342.50-3342.119"
- cell $and $and$ls180.v:3342$115
+ attribute \src "ls180.v:3338.50-3338.119"
+ cell $and $and$ls180.v:3338$115
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine1_cmd_valid
connect \B \main_sdram_bankmachine1_cmd_ready
- connect \Y $and$ls180.v:3342$115_Y
+ connect \Y $and$ls180.v:3338$115_Y
end
- attribute \src "ls180.v:3342.49-3342.167"
- cell $and $and$ls180.v:3342$116
+ attribute \src "ls180.v:3338.49-3338.167"
+ cell $and $and$ls180.v:3338$116
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3342$115_Y
+ connect \A $and$ls180.v:3338$115_Y
connect \B \main_sdram_bankmachine1_cmd_payload_is_write
- connect \Y $and$ls180.v:3342$116_Y
+ connect \Y $and$ls180.v:3338$116_Y
end
- attribute \src "ls180.v:3343.49-3343.118"
- cell $and $and$ls180.v:3343$117
+ attribute \src "ls180.v:3339.49-3339.118"
+ cell $and $and$ls180.v:3339$117
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine1_cmd_valid
connect \B \main_sdram_bankmachine1_cmd_ready
- connect \Y $and$ls180.v:3343$117_Y
+ connect \Y $and$ls180.v:3339$117_Y
end
- attribute \src "ls180.v:3343.48-3343.154"
- cell $and $and$ls180.v:3343$118
+ attribute \src "ls180.v:3339.48-3339.154"
+ cell $and $and$ls180.v:3339$118
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3343$117_Y
+ connect \A $and$ls180.v:3339$117_Y
connect \B \main_sdram_bankmachine1_row_open
- connect \Y $and$ls180.v:3343$118_Y
+ connect \Y $and$ls180.v:3339$118_Y
end
- attribute \src "ls180.v:3344.50-3344.119"
- cell $and $and$ls180.v:3344$119
+ attribute \src "ls180.v:3340.50-3340.119"
+ cell $and $and$ls180.v:3340$119
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine1_cmd_valid
connect \B \main_sdram_bankmachine1_cmd_ready
- connect \Y $and$ls180.v:3344$119_Y
+ connect \Y $and$ls180.v:3340$119_Y
end
- attribute \src "ls180.v:3344.49-3344.155"
- cell $and $and$ls180.v:3344$120
+ attribute \src "ls180.v:3340.49-3340.155"
+ cell $and $and$ls180.v:3340$120
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3344$119_Y
+ connect \A $and$ls180.v:3340$119_Y
connect \B \main_sdram_bankmachine1_row_open
- connect \Y $and$ls180.v:3344$120_Y
+ connect \Y $and$ls180.v:3340$120_Y
end
- attribute \src "ls180.v:3347.7-3347.114"
- cell $and $and$ls180.v:3347$122
+ attribute \src "ls180.v:3343.7-3343.114"
+ cell $and $and$ls180.v:3343$122
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_source_valid
connect \B \main_sdram_bankmachine1_cmd_buffer_source_valid
- connect \Y $and$ls180.v:3347$122_Y
+ connect \Y $and$ls180.v:3343$122_Y
end
- attribute \src "ls180.v:3376.66-3376.246"
- cell $and $and$ls180.v:3376$128
+ attribute \src "ls180.v:3372.66-3372.246"
+ cell $and $and$ls180.v:3372$128
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we
- connect \B $or$ls180.v:3376$127_Y
- connect \Y $and$ls180.v:3376$128_Y
+ connect \B $or$ls180.v:3372$127_Y
+ connect \Y $and$ls180.v:3372$128_Y
end
- attribute \src "ls180.v:3377.64-3377.187"
- cell $and $and$ls180.v:3377$129
+ attribute \src "ls180.v:3373.64-3373.187"
+ cell $and $and$ls180.v:3373$129
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable
connect \B \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_re
- connect \Y $and$ls180.v:3377$129_Y
+ connect \Y $and$ls180.v:3373$129_Y
end
- attribute \src "ls180.v:3401.9-3401.86"
- cell $and $and$ls180.v:3401$135
+ attribute \src "ls180.v:3397.9-3397.86"
+ cell $and $and$ls180.v:3397$135
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine1_twtpcon_ready
connect \B \main_sdram_bankmachine1_trascon_ready
- connect \Y $and$ls180.v:3401$135_Y
+ connect \Y $and$ls180.v:3397$135_Y
end
- attribute \src "ls180.v:3413.9-3413.86"
- cell $and $and$ls180.v:3413$136
+ attribute \src "ls180.v:3409.9-3409.86"
+ cell $and $and$ls180.v:3409$136
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine1_twtpcon_ready
connect \B \main_sdram_bankmachine1_trascon_ready
- connect \Y $and$ls180.v:3413$136_Y
+ connect \Y $and$ls180.v:3409$136_Y
end
- attribute \src "ls180.v:3463.13-3463.87"
- cell $and $and$ls180.v:3463$138
+ attribute \src "ls180.v:3459.13-3459.87"
+ cell $and $and$ls180.v:3459$138
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine1_cmd_ready
connect \B \main_sdram_bankmachine1_auto_precharge
- connect \Y $and$ls180.v:3463$138_Y
+ connect \Y $and$ls180.v:3459$138_Y
end
- attribute \src "ls180.v:3499.50-3499.119"
- cell $and $and$ls180.v:3499$145
+ attribute \src "ls180.v:3495.50-3495.119"
+ cell $and $and$ls180.v:3495$145
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine2_cmd_valid
connect \B \main_sdram_bankmachine2_cmd_ready
- connect \Y $and$ls180.v:3499$145_Y
+ connect \Y $and$ls180.v:3495$145_Y
end
- attribute \src "ls180.v:3499.49-3499.167"
- cell $and $and$ls180.v:3499$146
+ attribute \src "ls180.v:3495.49-3495.167"
+ cell $and $and$ls180.v:3495$146
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3499$145_Y
+ connect \A $and$ls180.v:3495$145_Y
connect \B \main_sdram_bankmachine2_cmd_payload_is_write
- connect \Y $and$ls180.v:3499$146_Y
+ connect \Y $and$ls180.v:3495$146_Y
end
- attribute \src "ls180.v:3500.49-3500.118"
- cell $and $and$ls180.v:3500$147
+ attribute \src "ls180.v:3496.49-3496.118"
+ cell $and $and$ls180.v:3496$147
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine2_cmd_valid
connect \B \main_sdram_bankmachine2_cmd_ready
- connect \Y $and$ls180.v:3500$147_Y
+ connect \Y $and$ls180.v:3496$147_Y
end
- attribute \src "ls180.v:3500.48-3500.154"
- cell $and $and$ls180.v:3500$148
+ attribute \src "ls180.v:3496.48-3496.154"
+ cell $and $and$ls180.v:3496$148
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3500$147_Y
+ connect \A $and$ls180.v:3496$147_Y
connect \B \main_sdram_bankmachine2_row_open
- connect \Y $and$ls180.v:3500$148_Y
+ connect \Y $and$ls180.v:3496$148_Y
end
- attribute \src "ls180.v:3501.50-3501.119"
- cell $and $and$ls180.v:3501$149
+ attribute \src "ls180.v:3497.50-3497.119"
+ cell $and $and$ls180.v:3497$149
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine2_cmd_valid
connect \B \main_sdram_bankmachine2_cmd_ready
- connect \Y $and$ls180.v:3501$149_Y
+ connect \Y $and$ls180.v:3497$149_Y
end
- attribute \src "ls180.v:3501.49-3501.155"
- cell $and $and$ls180.v:3501$150
+ attribute \src "ls180.v:3497.49-3497.155"
+ cell $and $and$ls180.v:3497$150
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3501$149_Y
+ connect \A $and$ls180.v:3497$149_Y
connect \B \main_sdram_bankmachine2_row_open
- connect \Y $and$ls180.v:3501$150_Y
+ connect \Y $and$ls180.v:3497$150_Y
end
- attribute \src "ls180.v:3504.7-3504.114"
- cell $and $and$ls180.v:3504$152
+ attribute \src "ls180.v:3500.7-3500.114"
+ cell $and $and$ls180.v:3500$152
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_source_valid
connect \B \main_sdram_bankmachine2_cmd_buffer_source_valid
- connect \Y $and$ls180.v:3504$152_Y
+ connect \Y $and$ls180.v:3500$152_Y
end
- attribute \src "ls180.v:3533.66-3533.246"
- cell $and $and$ls180.v:3533$158
+ attribute \src "ls180.v:3529.66-3529.246"
+ cell $and $and$ls180.v:3529$158
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we
- connect \B $or$ls180.v:3533$157_Y
- connect \Y $and$ls180.v:3533$158_Y
+ connect \B $or$ls180.v:3529$157_Y
+ connect \Y $and$ls180.v:3529$158_Y
end
- attribute \src "ls180.v:3534.64-3534.187"
- cell $and $and$ls180.v:3534$159
+ attribute \src "ls180.v:3530.64-3530.187"
+ cell $and $and$ls180.v:3530$159
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable
connect \B \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_re
- connect \Y $and$ls180.v:3534$159_Y
+ connect \Y $and$ls180.v:3530$159_Y
end
- attribute \src "ls180.v:3558.9-3558.86"
- cell $and $and$ls180.v:3558$165
+ attribute \src "ls180.v:3554.9-3554.86"
+ cell $and $and$ls180.v:3554$165
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine2_twtpcon_ready
connect \B \main_sdram_bankmachine2_trascon_ready
- connect \Y $and$ls180.v:3558$165_Y
+ connect \Y $and$ls180.v:3554$165_Y
end
- attribute \src "ls180.v:3570.9-3570.86"
- cell $and $and$ls180.v:3570$166
+ attribute \src "ls180.v:3566.9-3566.86"
+ cell $and $and$ls180.v:3566$166
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine2_twtpcon_ready
connect \B \main_sdram_bankmachine2_trascon_ready
- connect \Y $and$ls180.v:3570$166_Y
+ connect \Y $and$ls180.v:3566$166_Y
end
- attribute \src "ls180.v:3620.13-3620.87"
- cell $and $and$ls180.v:3620$168
+ attribute \src "ls180.v:3616.13-3616.87"
+ cell $and $and$ls180.v:3616$168
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine2_cmd_ready
connect \B \main_sdram_bankmachine2_auto_precharge
- connect \Y $and$ls180.v:3620$168_Y
+ connect \Y $and$ls180.v:3616$168_Y
end
- attribute \src "ls180.v:3656.50-3656.119"
- cell $and $and$ls180.v:3656$175
+ attribute \src "ls180.v:3652.50-3652.119"
+ cell $and $and$ls180.v:3652$175
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine3_cmd_valid
connect \B \main_sdram_bankmachine3_cmd_ready
- connect \Y $and$ls180.v:3656$175_Y
+ connect \Y $and$ls180.v:3652$175_Y
end
- attribute \src "ls180.v:3656.49-3656.167"
- cell $and $and$ls180.v:3656$176
+ attribute \src "ls180.v:3652.49-3652.167"
+ cell $and $and$ls180.v:3652$176
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3656$175_Y
+ connect \A $and$ls180.v:3652$175_Y
connect \B \main_sdram_bankmachine3_cmd_payload_is_write
- connect \Y $and$ls180.v:3656$176_Y
+ connect \Y $and$ls180.v:3652$176_Y
end
- attribute \src "ls180.v:3657.49-3657.118"
- cell $and $and$ls180.v:3657$177
+ attribute \src "ls180.v:3653.49-3653.118"
+ cell $and $and$ls180.v:3653$177
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine3_cmd_valid
connect \B \main_sdram_bankmachine3_cmd_ready
- connect \Y $and$ls180.v:3657$177_Y
+ connect \Y $and$ls180.v:3653$177_Y
end
- attribute \src "ls180.v:3657.48-3657.154"
- cell $and $and$ls180.v:3657$178
+ attribute \src "ls180.v:3653.48-3653.154"
+ cell $and $and$ls180.v:3653$178
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3657$177_Y
+ connect \A $and$ls180.v:3653$177_Y
connect \B \main_sdram_bankmachine3_row_open
- connect \Y $and$ls180.v:3657$178_Y
+ connect \Y $and$ls180.v:3653$178_Y
end
- attribute \src "ls180.v:3658.50-3658.119"
- cell $and $and$ls180.v:3658$179
+ attribute \src "ls180.v:3654.50-3654.119"
+ cell $and $and$ls180.v:3654$179
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine3_cmd_valid
connect \B \main_sdram_bankmachine3_cmd_ready
- connect \Y $and$ls180.v:3658$179_Y
+ connect \Y $and$ls180.v:3654$179_Y
end
- attribute \src "ls180.v:3658.49-3658.155"
- cell $and $and$ls180.v:3658$180
+ attribute \src "ls180.v:3654.49-3654.155"
+ cell $and $and$ls180.v:3654$180
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3658$179_Y
+ connect \A $and$ls180.v:3654$179_Y
connect \B \main_sdram_bankmachine3_row_open
- connect \Y $and$ls180.v:3658$180_Y
+ connect \Y $and$ls180.v:3654$180_Y
end
- attribute \src "ls180.v:3661.7-3661.114"
- cell $and $and$ls180.v:3661$182
+ attribute \src "ls180.v:3657.7-3657.114"
+ cell $and $and$ls180.v:3657$182
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_source_valid
connect \B \main_sdram_bankmachine3_cmd_buffer_source_valid
- connect \Y $and$ls180.v:3661$182_Y
+ connect \Y $and$ls180.v:3657$182_Y
end
- attribute \src "ls180.v:3690.66-3690.246"
- cell $and $and$ls180.v:3690$188
+ attribute \src "ls180.v:3686.66-3686.246"
+ cell $and $and$ls180.v:3686$188
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we
- connect \B $or$ls180.v:3690$187_Y
- connect \Y $and$ls180.v:3690$188_Y
+ connect \B $or$ls180.v:3686$187_Y
+ connect \Y $and$ls180.v:3686$188_Y
end
- attribute \src "ls180.v:3691.64-3691.187"
- cell $and $and$ls180.v:3691$189
+ attribute \src "ls180.v:3687.64-3687.187"
+ cell $and $and$ls180.v:3687$189
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable
connect \B \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_re
- connect \Y $and$ls180.v:3691$189_Y
+ connect \Y $and$ls180.v:3687$189_Y
end
- attribute \src "ls180.v:3715.9-3715.86"
- cell $and $and$ls180.v:3715$195
+ attribute \src "ls180.v:3711.9-3711.86"
+ cell $and $and$ls180.v:3711$195
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine3_twtpcon_ready
connect \B \main_sdram_bankmachine3_trascon_ready
- connect \Y $and$ls180.v:3715$195_Y
+ connect \Y $and$ls180.v:3711$195_Y
end
- attribute \src "ls180.v:3727.9-3727.86"
- cell $and $and$ls180.v:3727$196
+ attribute \src "ls180.v:3723.9-3723.86"
+ cell $and $and$ls180.v:3723$196
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine3_twtpcon_ready
connect \B \main_sdram_bankmachine3_trascon_ready
- connect \Y $and$ls180.v:3727$196_Y
+ connect \Y $and$ls180.v:3723$196_Y
end
- attribute \src "ls180.v:3777.13-3777.87"
- cell $and $and$ls180.v:3777$198
+ attribute \src "ls180.v:3773.13-3773.87"
+ cell $and $and$ls180.v:3773$198
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine3_cmd_ready
connect \B \main_sdram_bankmachine3_auto_precharge
- connect \Y $and$ls180.v:3777$198_Y
+ connect \Y $and$ls180.v:3773$198_Y
end
- attribute \src "ls180.v:3792.37-3792.102"
- cell $and $and$ls180.v:3792$199
+ attribute \src "ls180.v:3788.37-3788.102"
+ cell $and $and$ls180.v:3788$199
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_choose_req_cmd_valid
connect \B \main_sdram_choose_req_cmd_ready
- connect \Y $and$ls180.v:3792$199_Y
+ connect \Y $and$ls180.v:3788$199_Y
end
- attribute \src "ls180.v:3792.108-3792.188"
- cell $and $and$ls180.v:3792$201
+ attribute \src "ls180.v:3788.108-3788.188"
+ cell $and $and$ls180.v:3788$201
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_choose_req_cmd_payload_ras
- connect \B $not$ls180.v:3792$200_Y
- connect \Y $and$ls180.v:3792$201_Y
+ connect \B $not$ls180.v:3788$200_Y
+ connect \Y $and$ls180.v:3788$201_Y
end
- attribute \src "ls180.v:3792.107-3792.231"
- cell $and $and$ls180.v:3792$203
+ attribute \src "ls180.v:3788.107-3788.231"
+ cell $and $and$ls180.v:3788$203
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3792$201_Y
- connect \B $not$ls180.v:3792$202_Y
- connect \Y $and$ls180.v:3792$203_Y
+ connect \A $and$ls180.v:3788$201_Y
+ connect \B $not$ls180.v:3788$202_Y
+ connect \Y $and$ls180.v:3788$203_Y
end
- attribute \src "ls180.v:3792.36-3792.232"
- cell $and $and$ls180.v:3792$204
+ attribute \src "ls180.v:3788.36-3788.232"
+ cell $and $and$ls180.v:3788$204
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3792$199_Y
- connect \B $and$ls180.v:3792$203_Y
- connect \Y $and$ls180.v:3792$204_Y
+ connect \A $and$ls180.v:3788$199_Y
+ connect \B $and$ls180.v:3788$203_Y
+ connect \Y $and$ls180.v:3788$204_Y
end
- attribute \src "ls180.v:3793.37-3793.102"
- cell $and $and$ls180.v:3793$205
+ attribute \src "ls180.v:3789.37-3789.102"
+ cell $and $and$ls180.v:3789$205
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_choose_req_cmd_valid
connect \B \main_sdram_choose_req_cmd_ready
- connect \Y $and$ls180.v:3793$205_Y
+ connect \Y $and$ls180.v:3789$205_Y
end
- attribute \src "ls180.v:3793.108-3793.188"
- cell $and $and$ls180.v:3793$207
+ attribute \src "ls180.v:3789.108-3789.188"
+ cell $and $and$ls180.v:3789$207
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_choose_req_cmd_payload_ras
- connect \B $not$ls180.v:3793$206_Y
- connect \Y $and$ls180.v:3793$207_Y
+ connect \B $not$ls180.v:3789$206_Y
+ connect \Y $and$ls180.v:3789$207_Y
end
- attribute \src "ls180.v:3793.107-3793.231"
- cell $and $and$ls180.v:3793$209
+ attribute \src "ls180.v:3789.107-3789.231"
+ cell $and $and$ls180.v:3789$209
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3793$207_Y
- connect \B $not$ls180.v:3793$208_Y
- connect \Y $and$ls180.v:3793$209_Y
+ connect \A $and$ls180.v:3789$207_Y
+ connect \B $not$ls180.v:3789$208_Y
+ connect \Y $and$ls180.v:3789$209_Y
end
- attribute \src "ls180.v:3793.36-3793.232"
- cell $and $and$ls180.v:3793$210
+ attribute \src "ls180.v:3789.36-3789.232"
+ cell $and $and$ls180.v:3789$210
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3793$205_Y
- connect \B $and$ls180.v:3793$209_Y
- connect \Y $and$ls180.v:3793$210_Y
+ connect \A $and$ls180.v:3789$205_Y
+ connect \B $and$ls180.v:3789$209_Y
+ connect \Y $and$ls180.v:3789$210_Y
end
- attribute \src "ls180.v:3794.34-3794.85"
- cell $and $and$ls180.v:3794$211
+ attribute \src "ls180.v:3790.34-3790.85"
+ cell $and $and$ls180.v:3790$211
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_trrdcon_ready
connect \B \main_sdram_tfawcon_ready
- connect \Y $and$ls180.v:3794$211_Y
+ connect \Y $and$ls180.v:3790$211_Y
end
- attribute \src "ls180.v:3795.37-3795.102"
- cell $and $and$ls180.v:3795$212
+ attribute \src "ls180.v:3791.37-3791.102"
+ cell $and $and$ls180.v:3791$212
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_choose_req_cmd_valid
connect \B \main_sdram_choose_req_cmd_ready
- connect \Y $and$ls180.v:3795$212_Y
+ connect \Y $and$ls180.v:3791$212_Y
end
- attribute \src "ls180.v:3795.36-3795.194"
- cell $and $and$ls180.v:3795$214
+ attribute \src "ls180.v:3791.36-3791.194"
+ cell $and $and$ls180.v:3791$214
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3795$212_Y
- connect \B $or$ls180.v:3795$213_Y
- connect \Y $and$ls180.v:3795$214_Y
+ connect \A $and$ls180.v:3791$212_Y
+ connect \B $or$ls180.v:3791$213_Y
+ connect \Y $and$ls180.v:3791$214_Y
end
- attribute \src "ls180.v:3797.37-3797.102"
- cell $and $and$ls180.v:3797$215
+ attribute \src "ls180.v:3793.37-3793.102"
+ cell $and $and$ls180.v:3793$215
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_choose_req_cmd_valid
connect \B \main_sdram_choose_req_cmd_ready
- connect \Y $and$ls180.v:3797$215_Y
+ connect \Y $and$ls180.v:3793$215_Y
end
- attribute \src "ls180.v:3797.36-3797.148"
- cell $and $and$ls180.v:3797$216
+ attribute \src "ls180.v:3793.36-3793.148"
+ cell $and $and$ls180.v:3793$216
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3797$215_Y
+ connect \A $and$ls180.v:3793$215_Y
connect \B \main_sdram_choose_req_cmd_payload_is_write
- connect \Y $and$ls180.v:3797$216_Y
+ connect \Y $and$ls180.v:3793$216_Y
end
- attribute \src "ls180.v:3798.40-3798.119"
- cell $and $and$ls180.v:3798$217
+ attribute \src "ls180.v:3794.40-3794.119"
+ cell $and $and$ls180.v:3794$217
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine0_cmd_valid
connect \B \main_sdram_bankmachine0_cmd_payload_is_read
- connect \Y $and$ls180.v:3798$217_Y
+ connect \Y $and$ls180.v:3794$217_Y
end
- attribute \src "ls180.v:3798.124-3798.203"
- cell $and $and$ls180.v:3798$218
+ attribute \src "ls180.v:3794.124-3794.203"
+ cell $and $and$ls180.v:3794$218
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine1_cmd_valid
connect \B \main_sdram_bankmachine1_cmd_payload_is_read
- connect \Y $and$ls180.v:3798$218_Y
+ connect \Y $and$ls180.v:3794$218_Y
end
- attribute \src "ls180.v:3798.209-3798.288"
- cell $and $and$ls180.v:3798$220
+ attribute \src "ls180.v:3794.209-3794.288"
+ cell $and $and$ls180.v:3794$220
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine2_cmd_valid
connect \B \main_sdram_bankmachine2_cmd_payload_is_read
- connect \Y $and$ls180.v:3798$220_Y
+ connect \Y $and$ls180.v:3794$220_Y
end
- attribute \src "ls180.v:3798.294-3798.373"
- cell $and $and$ls180.v:3798$222
+ attribute \src "ls180.v:3794.294-3794.373"
+ cell $and $and$ls180.v:3794$222
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine3_cmd_valid
connect \B \main_sdram_bankmachine3_cmd_payload_is_read
- connect \Y $and$ls180.v:3798$222_Y
+ connect \Y $and$ls180.v:3794$222_Y
end
- attribute \src "ls180.v:3799.41-3799.121"
- cell $and $and$ls180.v:3799$224
+ attribute \src "ls180.v:3795.41-3795.121"
+ cell $and $and$ls180.v:3795$224
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine0_cmd_valid
connect \B \main_sdram_bankmachine0_cmd_payload_is_write
- connect \Y $and$ls180.v:3799$224_Y
+ connect \Y $and$ls180.v:3795$224_Y
end
- attribute \src "ls180.v:3799.126-3799.206"
- cell $and $and$ls180.v:3799$225
+ attribute \src "ls180.v:3795.126-3795.206"
+ cell $and $and$ls180.v:3795$225
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine1_cmd_valid
connect \B \main_sdram_bankmachine1_cmd_payload_is_write
- connect \Y $and$ls180.v:3799$225_Y
+ connect \Y $and$ls180.v:3795$225_Y
end
- attribute \src "ls180.v:3799.212-3799.292"
- cell $and $and$ls180.v:3799$227
+ attribute \src "ls180.v:3795.212-3795.292"
+ cell $and $and$ls180.v:3795$227
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine2_cmd_valid
connect \B \main_sdram_bankmachine2_cmd_payload_is_write
- connect \Y $and$ls180.v:3799$227_Y
+ connect \Y $and$ls180.v:3795$227_Y
end
- attribute \src "ls180.v:3799.298-3799.378"
- cell $and $and$ls180.v:3799$229
+ attribute \src "ls180.v:3795.298-3795.378"
+ cell $and $and$ls180.v:3795$229
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine3_cmd_valid
connect \B \main_sdram_bankmachine3_cmd_payload_is_write
- connect \Y $and$ls180.v:3799$229_Y
+ connect \Y $and$ls180.v:3795$229_Y
end
- attribute \src "ls180.v:3806.38-3806.111"
- cell $and $and$ls180.v:3806$233
+ attribute \src "ls180.v:3802.38-3802.111"
+ cell $and $and$ls180.v:3802$233
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine0_refresh_gnt
connect \B \main_sdram_bankmachine1_refresh_gnt
- connect \Y $and$ls180.v:3806$233_Y
+ connect \Y $and$ls180.v:3802$233_Y
end
- attribute \src "ls180.v:3806.37-3806.150"
- cell $and $and$ls180.v:3806$234
+ attribute \src "ls180.v:3802.37-3802.150"
+ cell $and $and$ls180.v:3802$234
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3806$233_Y
+ connect \A $and$ls180.v:3802$233_Y
connect \B \main_sdram_bankmachine2_refresh_gnt
- connect \Y $and$ls180.v:3806$234_Y
+ connect \Y $and$ls180.v:3802$234_Y
end
- attribute \src "ls180.v:3806.36-3806.189"
- cell $and $and$ls180.v:3806$235
+ attribute \src "ls180.v:3802.36-3802.189"
+ cell $and $and$ls180.v:3802$235
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3806$234_Y
+ connect \A $and$ls180.v:3802$234_Y
connect \B \main_sdram_bankmachine3_refresh_gnt
- connect \Y $and$ls180.v:3806$235_Y
+ connect \Y $and$ls180.v:3802$235_Y
end
- attribute \src "ls180.v:3812.77-3812.153"
- cell $and $and$ls180.v:3812$238
+ attribute \src "ls180.v:3808.77-3808.153"
+ cell $and $and$ls180.v:3808$238
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine0_cmd_payload_is_cmd
connect \B \main_sdram_choose_cmd_want_cmds
- connect \Y $and$ls180.v:3812$238_Y
+ connect \Y $and$ls180.v:3808$238_Y
end
- attribute \src "ls180.v:3812.162-3812.246"
- cell $and $and$ls180.v:3812$240
+ attribute \src "ls180.v:3808.162-3808.246"
+ cell $and $and$ls180.v:3808$240
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine0_cmd_payload_ras
- connect \B $not$ls180.v:3812$239_Y
- connect \Y $and$ls180.v:3812$240_Y
+ connect \B $not$ls180.v:3808$239_Y
+ connect \Y $and$ls180.v:3808$240_Y
end
- attribute \src "ls180.v:3812.161-3812.291"
- cell $and $and$ls180.v:3812$242
+ attribute \src "ls180.v:3808.161-3808.291"
+ cell $and $and$ls180.v:3808$242
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3812$240_Y
- connect \B $not$ls180.v:3812$241_Y
- connect \Y $and$ls180.v:3812$242_Y
+ connect \A $and$ls180.v:3808$240_Y
+ connect \B $not$ls180.v:3808$241_Y
+ connect \Y $and$ls180.v:3808$242_Y
end
- attribute \src "ls180.v:3812.76-3812.333"
- cell $and $and$ls180.v:3812$245
+ attribute \src "ls180.v:3808.76-3808.333"
+ cell $and $and$ls180.v:3808$245
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3812$238_Y
- connect \B $or$ls180.v:3812$244_Y
- connect \Y $and$ls180.v:3812$245_Y
+ connect \A $and$ls180.v:3808$238_Y
+ connect \B $or$ls180.v:3808$244_Y
+ connect \Y $and$ls180.v:3808$245_Y
end
- attribute \src "ls180.v:3812.338-3812.505"
- cell $and $and$ls180.v:3812$248
+ attribute \src "ls180.v:3808.338-3808.505"
+ cell $and $and$ls180.v:3808$248
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $eq$ls180.v:3812$246_Y
- connect \B $eq$ls180.v:3812$247_Y
- connect \Y $and$ls180.v:3812$248_Y
+ connect \A $eq$ls180.v:3808$246_Y
+ connect \B $eq$ls180.v:3808$247_Y
+ connect \Y $and$ls180.v:3808$248_Y
end
- attribute \src "ls180.v:3812.38-3812.507"
- cell $and $and$ls180.v:3812$250
+ attribute \src "ls180.v:3808.38-3808.507"
+ cell $and $and$ls180.v:3808$250
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine0_cmd_valid
- connect \B $or$ls180.v:3812$249_Y
- connect \Y $and$ls180.v:3812$250_Y
+ connect \B $or$ls180.v:3808$249_Y
+ connect \Y $and$ls180.v:3808$250_Y
end
- attribute \src "ls180.v:3813.77-3813.153"
- cell $and $and$ls180.v:3813$251
+ attribute \src "ls180.v:3809.77-3809.153"
+ cell $and $and$ls180.v:3809$251
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine1_cmd_payload_is_cmd
connect \B \main_sdram_choose_cmd_want_cmds
- connect \Y $and$ls180.v:3813$251_Y
+ connect \Y $and$ls180.v:3809$251_Y
end
- attribute \src "ls180.v:3813.162-3813.246"
- cell $and $and$ls180.v:3813$253
+ attribute \src "ls180.v:3809.162-3809.246"
+ cell $and $and$ls180.v:3809$253
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine1_cmd_payload_ras
- connect \B $not$ls180.v:3813$252_Y
- connect \Y $and$ls180.v:3813$253_Y
+ connect \B $not$ls180.v:3809$252_Y
+ connect \Y $and$ls180.v:3809$253_Y
end
- attribute \src "ls180.v:3813.161-3813.291"
- cell $and $and$ls180.v:3813$255
+ attribute \src "ls180.v:3809.161-3809.291"
+ cell $and $and$ls180.v:3809$255
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3813$253_Y
- connect \B $not$ls180.v:3813$254_Y
- connect \Y $and$ls180.v:3813$255_Y
+ connect \A $and$ls180.v:3809$253_Y
+ connect \B $not$ls180.v:3809$254_Y
+ connect \Y $and$ls180.v:3809$255_Y
end
- attribute \src "ls180.v:3813.76-3813.333"
- cell $and $and$ls180.v:3813$258
+ attribute \src "ls180.v:3809.76-3809.333"
+ cell $and $and$ls180.v:3809$258
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3813$251_Y
- connect \B $or$ls180.v:3813$257_Y
- connect \Y $and$ls180.v:3813$258_Y
+ connect \A $and$ls180.v:3809$251_Y
+ connect \B $or$ls180.v:3809$257_Y
+ connect \Y $and$ls180.v:3809$258_Y
end
- attribute \src "ls180.v:3813.338-3813.505"
- cell $and $and$ls180.v:3813$261
+ attribute \src "ls180.v:3809.338-3809.505"
+ cell $and $and$ls180.v:3809$261
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $eq$ls180.v:3813$259_Y
- connect \B $eq$ls180.v:3813$260_Y
- connect \Y $and$ls180.v:3813$261_Y
+ connect \A $eq$ls180.v:3809$259_Y
+ connect \B $eq$ls180.v:3809$260_Y
+ connect \Y $and$ls180.v:3809$261_Y
end
- attribute \src "ls180.v:3813.38-3813.507"
- cell $and $and$ls180.v:3813$263
+ attribute \src "ls180.v:3809.38-3809.507"
+ cell $and $and$ls180.v:3809$263
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine1_cmd_valid
- connect \B $or$ls180.v:3813$262_Y
- connect \Y $and$ls180.v:3813$263_Y
+ connect \B $or$ls180.v:3809$262_Y
+ connect \Y $and$ls180.v:3809$263_Y
end
- attribute \src "ls180.v:3814.77-3814.153"
- cell $and $and$ls180.v:3814$264
+ attribute \src "ls180.v:3810.77-3810.153"
+ cell $and $and$ls180.v:3810$264
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine2_cmd_payload_is_cmd
connect \B \main_sdram_choose_cmd_want_cmds
- connect \Y $and$ls180.v:3814$264_Y
+ connect \Y $and$ls180.v:3810$264_Y
end
- attribute \src "ls180.v:3814.162-3814.246"
- cell $and $and$ls180.v:3814$266
+ attribute \src "ls180.v:3810.162-3810.246"
+ cell $and $and$ls180.v:3810$266
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine2_cmd_payload_ras
- connect \B $not$ls180.v:3814$265_Y
- connect \Y $and$ls180.v:3814$266_Y
+ connect \B $not$ls180.v:3810$265_Y
+ connect \Y $and$ls180.v:3810$266_Y
end
- attribute \src "ls180.v:3814.161-3814.291"
- cell $and $and$ls180.v:3814$268
+ attribute \src "ls180.v:3810.161-3810.291"
+ cell $and $and$ls180.v:3810$268
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3814$266_Y
- connect \B $not$ls180.v:3814$267_Y
- connect \Y $and$ls180.v:3814$268_Y
+ connect \A $and$ls180.v:3810$266_Y
+ connect \B $not$ls180.v:3810$267_Y
+ connect \Y $and$ls180.v:3810$268_Y
end
- attribute \src "ls180.v:3814.76-3814.333"
- cell $and $and$ls180.v:3814$271
+ attribute \src "ls180.v:3810.76-3810.333"
+ cell $and $and$ls180.v:3810$271
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3814$264_Y
- connect \B $or$ls180.v:3814$270_Y
- connect \Y $and$ls180.v:3814$271_Y
+ connect \A $and$ls180.v:3810$264_Y
+ connect \B $or$ls180.v:3810$270_Y
+ connect \Y $and$ls180.v:3810$271_Y
end
- attribute \src "ls180.v:3814.338-3814.505"
- cell $and $and$ls180.v:3814$274
+ attribute \src "ls180.v:3810.338-3810.505"
+ cell $and $and$ls180.v:3810$274
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $eq$ls180.v:3814$272_Y
- connect \B $eq$ls180.v:3814$273_Y
- connect \Y $and$ls180.v:3814$274_Y
+ connect \A $eq$ls180.v:3810$272_Y
+ connect \B $eq$ls180.v:3810$273_Y
+ connect \Y $and$ls180.v:3810$274_Y
end
- attribute \src "ls180.v:3814.38-3814.507"
- cell $and $and$ls180.v:3814$276
+ attribute \src "ls180.v:3810.38-3810.507"
+ cell $and $and$ls180.v:3810$276
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine2_cmd_valid
- connect \B $or$ls180.v:3814$275_Y
- connect \Y $and$ls180.v:3814$276_Y
+ connect \B $or$ls180.v:3810$275_Y
+ connect \Y $and$ls180.v:3810$276_Y
end
- attribute \src "ls180.v:3815.77-3815.153"
- cell $and $and$ls180.v:3815$277
+ attribute \src "ls180.v:3811.77-3811.153"
+ cell $and $and$ls180.v:3811$277
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine3_cmd_payload_is_cmd
connect \B \main_sdram_choose_cmd_want_cmds
- connect \Y $and$ls180.v:3815$277_Y
+ connect \Y $and$ls180.v:3811$277_Y
end
- attribute \src "ls180.v:3815.162-3815.246"
- cell $and $and$ls180.v:3815$279
+ attribute \src "ls180.v:3811.162-3811.246"
+ cell $and $and$ls180.v:3811$279
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine3_cmd_payload_ras
- connect \B $not$ls180.v:3815$278_Y
- connect \Y $and$ls180.v:3815$279_Y
+ connect \B $not$ls180.v:3811$278_Y
+ connect \Y $and$ls180.v:3811$279_Y
end
- attribute \src "ls180.v:3815.161-3815.291"
- cell $and $and$ls180.v:3815$281
+ attribute \src "ls180.v:3811.161-3811.291"
+ cell $and $and$ls180.v:3811$281
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3815$279_Y
- connect \B $not$ls180.v:3815$280_Y
- connect \Y $and$ls180.v:3815$281_Y
+ connect \A $and$ls180.v:3811$279_Y
+ connect \B $not$ls180.v:3811$280_Y
+ connect \Y $and$ls180.v:3811$281_Y
end
- attribute \src "ls180.v:3815.76-3815.333"
- cell $and $and$ls180.v:3815$284
+ attribute \src "ls180.v:3811.76-3811.333"
+ cell $and $and$ls180.v:3811$284
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3815$277_Y
- connect \B $or$ls180.v:3815$283_Y
- connect \Y $and$ls180.v:3815$284_Y
+ connect \A $and$ls180.v:3811$277_Y
+ connect \B $or$ls180.v:3811$283_Y
+ connect \Y $and$ls180.v:3811$284_Y
end
- attribute \src "ls180.v:3815.338-3815.505"
- cell $and $and$ls180.v:3815$287
+ attribute \src "ls180.v:3811.338-3811.505"
+ cell $and $and$ls180.v:3811$287
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $eq$ls180.v:3815$285_Y
- connect \B $eq$ls180.v:3815$286_Y
- connect \Y $and$ls180.v:3815$287_Y
+ connect \A $eq$ls180.v:3811$285_Y
+ connect \B $eq$ls180.v:3811$286_Y
+ connect \Y $and$ls180.v:3811$287_Y
end
- attribute \src "ls180.v:3815.38-3815.507"
- cell $and $and$ls180.v:3815$289
+ attribute \src "ls180.v:3811.38-3811.507"
+ cell $and $and$ls180.v:3811$289
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine3_cmd_valid
- connect \B $or$ls180.v:3815$288_Y
- connect \Y $and$ls180.v:3815$289_Y
+ connect \B $or$ls180.v:3811$288_Y
+ connect \Y $and$ls180.v:3811$289_Y
end
- attribute \src "ls180.v:3845.77-3845.153"
- cell $and $and$ls180.v:3845$296
+ attribute \src "ls180.v:3841.77-3841.153"
+ cell $and $and$ls180.v:3841$296
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine0_cmd_payload_is_cmd
connect \B \main_sdram_choose_req_want_cmds
- connect \Y $and$ls180.v:3845$296_Y
+ connect \Y $and$ls180.v:3841$296_Y
end
- attribute \src "ls180.v:3845.162-3845.246"
- cell $and $and$ls180.v:3845$298
+ attribute \src "ls180.v:3841.162-3841.246"
+ cell $and $and$ls180.v:3841$298
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine0_cmd_payload_ras
- connect \B $not$ls180.v:3845$297_Y
- connect \Y $and$ls180.v:3845$298_Y
+ connect \B $not$ls180.v:3841$297_Y
+ connect \Y $and$ls180.v:3841$298_Y
end
- attribute \src "ls180.v:3845.161-3845.291"
- cell $and $and$ls180.v:3845$300
+ attribute \src "ls180.v:3841.161-3841.291"
+ cell $and $and$ls180.v:3841$300
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3845$298_Y
- connect \B $not$ls180.v:3845$299_Y
- connect \Y $and$ls180.v:3845$300_Y
+ connect \A $and$ls180.v:3841$298_Y
+ connect \B $not$ls180.v:3841$299_Y
+ connect \Y $and$ls180.v:3841$300_Y
end
- attribute \src "ls180.v:3845.76-3845.333"
- cell $and $and$ls180.v:3845$303
+ attribute \src "ls180.v:3841.76-3841.333"
+ cell $and $and$ls180.v:3841$303
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3845$296_Y
- connect \B $or$ls180.v:3845$302_Y
- connect \Y $and$ls180.v:3845$303_Y
+ connect \A $and$ls180.v:3841$296_Y
+ connect \B $or$ls180.v:3841$302_Y
+ connect \Y $and$ls180.v:3841$303_Y
end
- attribute \src "ls180.v:3845.338-3845.505"
- cell $and $and$ls180.v:3845$306
+ attribute \src "ls180.v:3841.338-3841.505"
+ cell $and $and$ls180.v:3841$306
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $eq$ls180.v:3845$304_Y
- connect \B $eq$ls180.v:3845$305_Y
- connect \Y $and$ls180.v:3845$306_Y
+ connect \A $eq$ls180.v:3841$304_Y
+ connect \B $eq$ls180.v:3841$305_Y
+ connect \Y $and$ls180.v:3841$306_Y
end
- attribute \src "ls180.v:3845.38-3845.507"
- cell $and $and$ls180.v:3845$308
+ attribute \src "ls180.v:3841.38-3841.507"
+ cell $and $and$ls180.v:3841$308
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine0_cmd_valid
- connect \B $or$ls180.v:3845$307_Y
- connect \Y $and$ls180.v:3845$308_Y
+ connect \B $or$ls180.v:3841$307_Y
+ connect \Y $and$ls180.v:3841$308_Y
end
- attribute \src "ls180.v:3846.77-3846.153"
- cell $and $and$ls180.v:3846$309
+ attribute \src "ls180.v:3842.77-3842.153"
+ cell $and $and$ls180.v:3842$309
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine1_cmd_payload_is_cmd
connect \B \main_sdram_choose_req_want_cmds
- connect \Y $and$ls180.v:3846$309_Y
+ connect \Y $and$ls180.v:3842$309_Y
end
- attribute \src "ls180.v:3846.162-3846.246"
- cell $and $and$ls180.v:3846$311
+ attribute \src "ls180.v:3842.162-3842.246"
+ cell $and $and$ls180.v:3842$311
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine1_cmd_payload_ras
- connect \B $not$ls180.v:3846$310_Y
- connect \Y $and$ls180.v:3846$311_Y
+ connect \B $not$ls180.v:3842$310_Y
+ connect \Y $and$ls180.v:3842$311_Y
end
- attribute \src "ls180.v:3846.161-3846.291"
- cell $and $and$ls180.v:3846$313
+ attribute \src "ls180.v:3842.161-3842.291"
+ cell $and $and$ls180.v:3842$313
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3846$311_Y
- connect \B $not$ls180.v:3846$312_Y
- connect \Y $and$ls180.v:3846$313_Y
+ connect \A $and$ls180.v:3842$311_Y
+ connect \B $not$ls180.v:3842$312_Y
+ connect \Y $and$ls180.v:3842$313_Y
end
- attribute \src "ls180.v:3846.76-3846.333"
- cell $and $and$ls180.v:3846$316
+ attribute \src "ls180.v:3842.76-3842.333"
+ cell $and $and$ls180.v:3842$316
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3846$309_Y
- connect \B $or$ls180.v:3846$315_Y
- connect \Y $and$ls180.v:3846$316_Y
+ connect \A $and$ls180.v:3842$309_Y
+ connect \B $or$ls180.v:3842$315_Y
+ connect \Y $and$ls180.v:3842$316_Y
end
- attribute \src "ls180.v:3846.338-3846.505"
- cell $and $and$ls180.v:3846$319
+ attribute \src "ls180.v:3842.338-3842.505"
+ cell $and $and$ls180.v:3842$319
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $eq$ls180.v:3846$317_Y
- connect \B $eq$ls180.v:3846$318_Y
- connect \Y $and$ls180.v:3846$319_Y
+ connect \A $eq$ls180.v:3842$317_Y
+ connect \B $eq$ls180.v:3842$318_Y
+ connect \Y $and$ls180.v:3842$319_Y
end
- attribute \src "ls180.v:3846.38-3846.507"
- cell $and $and$ls180.v:3846$321
+ attribute \src "ls180.v:3842.38-3842.507"
+ cell $and $and$ls180.v:3842$321
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine1_cmd_valid
- connect \B $or$ls180.v:3846$320_Y
- connect \Y $and$ls180.v:3846$321_Y
+ connect \B $or$ls180.v:3842$320_Y
+ connect \Y $and$ls180.v:3842$321_Y
end
- attribute \src "ls180.v:3847.77-3847.153"
- cell $and $and$ls180.v:3847$322
+ attribute \src "ls180.v:3843.77-3843.153"
+ cell $and $and$ls180.v:3843$322
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine2_cmd_payload_is_cmd
connect \B \main_sdram_choose_req_want_cmds
- connect \Y $and$ls180.v:3847$322_Y
+ connect \Y $and$ls180.v:3843$322_Y
end
- attribute \src "ls180.v:3847.162-3847.246"
- cell $and $and$ls180.v:3847$324
+ attribute \src "ls180.v:3843.162-3843.246"
+ cell $and $and$ls180.v:3843$324
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine2_cmd_payload_ras
- connect \B $not$ls180.v:3847$323_Y
- connect \Y $and$ls180.v:3847$324_Y
+ connect \B $not$ls180.v:3843$323_Y
+ connect \Y $and$ls180.v:3843$324_Y
end
- attribute \src "ls180.v:3847.161-3847.291"
- cell $and $and$ls180.v:3847$326
+ attribute \src "ls180.v:3843.161-3843.291"
+ cell $and $and$ls180.v:3843$326
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3847$324_Y
- connect \B $not$ls180.v:3847$325_Y
- connect \Y $and$ls180.v:3847$326_Y
+ connect \A $and$ls180.v:3843$324_Y
+ connect \B $not$ls180.v:3843$325_Y
+ connect \Y $and$ls180.v:3843$326_Y
end
- attribute \src "ls180.v:3847.76-3847.333"
- cell $and $and$ls180.v:3847$329
+ attribute \src "ls180.v:3843.76-3843.333"
+ cell $and $and$ls180.v:3843$329
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3847$322_Y
- connect \B $or$ls180.v:3847$328_Y
- connect \Y $and$ls180.v:3847$329_Y
+ connect \A $and$ls180.v:3843$322_Y
+ connect \B $or$ls180.v:3843$328_Y
+ connect \Y $and$ls180.v:3843$329_Y
end
- attribute \src "ls180.v:3847.338-3847.505"
- cell $and $and$ls180.v:3847$332
+ attribute \src "ls180.v:3843.338-3843.505"
+ cell $and $and$ls180.v:3843$332
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $eq$ls180.v:3847$330_Y
- connect \B $eq$ls180.v:3847$331_Y
- connect \Y $and$ls180.v:3847$332_Y
+ connect \A $eq$ls180.v:3843$330_Y
+ connect \B $eq$ls180.v:3843$331_Y
+ connect \Y $and$ls180.v:3843$332_Y
end
- attribute \src "ls180.v:3847.38-3847.507"
- cell $and $and$ls180.v:3847$334
+ attribute \src "ls180.v:3843.38-3843.507"
+ cell $and $and$ls180.v:3843$334
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine2_cmd_valid
- connect \B $or$ls180.v:3847$333_Y
- connect \Y $and$ls180.v:3847$334_Y
+ connect \B $or$ls180.v:3843$333_Y
+ connect \Y $and$ls180.v:3843$334_Y
end
- attribute \src "ls180.v:3848.77-3848.153"
- cell $and $and$ls180.v:3848$335
+ attribute \src "ls180.v:3844.77-3844.153"
+ cell $and $and$ls180.v:3844$335
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine3_cmd_payload_is_cmd
connect \B \main_sdram_choose_req_want_cmds
- connect \Y $and$ls180.v:3848$335_Y
+ connect \Y $and$ls180.v:3844$335_Y
end
- attribute \src "ls180.v:3848.162-3848.246"
- cell $and $and$ls180.v:3848$337
+ attribute \src "ls180.v:3844.162-3844.246"
+ cell $and $and$ls180.v:3844$337
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine3_cmd_payload_ras
- connect \B $not$ls180.v:3848$336_Y
- connect \Y $and$ls180.v:3848$337_Y
+ connect \B $not$ls180.v:3844$336_Y
+ connect \Y $and$ls180.v:3844$337_Y
end
- attribute \src "ls180.v:3848.161-3848.291"
- cell $and $and$ls180.v:3848$339
+ attribute \src "ls180.v:3844.161-3844.291"
+ cell $and $and$ls180.v:3844$339
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3848$337_Y
- connect \B $not$ls180.v:3848$338_Y
- connect \Y $and$ls180.v:3848$339_Y
+ connect \A $and$ls180.v:3844$337_Y
+ connect \B $not$ls180.v:3844$338_Y
+ connect \Y $and$ls180.v:3844$339_Y
end
- attribute \src "ls180.v:3848.76-3848.333"
- cell $and $and$ls180.v:3848$342
+ attribute \src "ls180.v:3844.76-3844.333"
+ cell $and $and$ls180.v:3844$342
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3848$335_Y
- connect \B $or$ls180.v:3848$341_Y
- connect \Y $and$ls180.v:3848$342_Y
+ connect \A $and$ls180.v:3844$335_Y
+ connect \B $or$ls180.v:3844$341_Y
+ connect \Y $and$ls180.v:3844$342_Y
end
- attribute \src "ls180.v:3848.338-3848.505"
- cell $and $and$ls180.v:3848$345
+ attribute \src "ls180.v:3844.338-3844.505"
+ cell $and $and$ls180.v:3844$345
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $eq$ls180.v:3848$343_Y
- connect \B $eq$ls180.v:3848$344_Y
- connect \Y $and$ls180.v:3848$345_Y
+ connect \A $eq$ls180.v:3844$343_Y
+ connect \B $eq$ls180.v:3844$344_Y
+ connect \Y $and$ls180.v:3844$345_Y
end
- attribute \src "ls180.v:3848.38-3848.507"
- cell $and $and$ls180.v:3848$347
+ attribute \src "ls180.v:3844.38-3844.507"
+ cell $and $and$ls180.v:3844$347
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine3_cmd_valid
- connect \B $or$ls180.v:3848$346_Y
- connect \Y $and$ls180.v:3848$347_Y
+ connect \B $or$ls180.v:3844$346_Y
+ connect \Y $and$ls180.v:3844$347_Y
end
- attribute \src "ls180.v:3877.8-3877.73"
- cell $and $and$ls180.v:3877$352
+ attribute \src "ls180.v:3873.8-3873.73"
+ cell $and $and$ls180.v:3873$352
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_choose_cmd_cmd_valid
connect \B \main_sdram_choose_cmd_cmd_ready
- connect \Y $and$ls180.v:3877$352_Y
+ connect \Y $and$ls180.v:3873$352_Y
end
- attribute \src "ls180.v:3877.7-3877.114"
- cell $and $and$ls180.v:3877$354
+ attribute \src "ls180.v:3873.7-3873.114"
+ cell $and $and$ls180.v:3873$354
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3877$352_Y
- connect \B $eq$ls180.v:3877$353_Y
- connect \Y $and$ls180.v:3877$354_Y
+ connect \A $and$ls180.v:3873$352_Y
+ connect \B $eq$ls180.v:3873$353_Y
+ connect \Y $and$ls180.v:3873$354_Y
end
- attribute \src "ls180.v:3880.8-3880.73"
- cell $and $and$ls180.v:3880$355
+ attribute \src "ls180.v:3876.8-3876.73"
+ cell $and $and$ls180.v:3876$355
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_choose_req_cmd_valid
connect \B \main_sdram_choose_req_cmd_ready
- connect \Y $and$ls180.v:3880$355_Y
+ connect \Y $and$ls180.v:3876$355_Y
end
- attribute \src "ls180.v:3880.7-3880.114"
- cell $and $and$ls180.v:3880$357
+ attribute \src "ls180.v:3876.7-3876.114"
+ cell $and $and$ls180.v:3876$357
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3880$355_Y
- connect \B $eq$ls180.v:3880$356_Y
- connect \Y $and$ls180.v:3880$357_Y
+ connect \A $and$ls180.v:3876$355_Y
+ connect \B $eq$ls180.v:3876$356_Y
+ connect \Y $and$ls180.v:3876$357_Y
end
- attribute \src "ls180.v:3886.8-3886.73"
- cell $and $and$ls180.v:3886$359
+ attribute \src "ls180.v:3882.8-3882.73"
+ cell $and $and$ls180.v:3882$359
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_choose_cmd_cmd_valid
connect \B \main_sdram_choose_cmd_cmd_ready
- connect \Y $and$ls180.v:3886$359_Y
+ connect \Y $and$ls180.v:3882$359_Y
end
- attribute \src "ls180.v:3886.7-3886.114"
- cell $and $and$ls180.v:3886$361
+ attribute \src "ls180.v:3882.7-3882.114"
+ cell $and $and$ls180.v:3882$361
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3886$359_Y
- connect \B $eq$ls180.v:3886$360_Y
- connect \Y $and$ls180.v:3886$361_Y
+ connect \A $and$ls180.v:3882$359_Y
+ connect \B $eq$ls180.v:3882$360_Y
+ connect \Y $and$ls180.v:3882$361_Y
end
- attribute \src "ls180.v:3889.8-3889.73"
- cell $and $and$ls180.v:3889$362
+ attribute \src "ls180.v:3885.8-3885.73"
+ cell $and $and$ls180.v:3885$362
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_choose_req_cmd_valid
connect \B \main_sdram_choose_req_cmd_ready
- connect \Y $and$ls180.v:3889$362_Y
+ connect \Y $and$ls180.v:3885$362_Y
end
- attribute \src "ls180.v:3889.7-3889.114"
- cell $and $and$ls180.v:3889$364
+ attribute \src "ls180.v:3885.7-3885.114"
+ cell $and $and$ls180.v:3885$364
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3889$362_Y
- connect \B $eq$ls180.v:3889$363_Y
- connect \Y $and$ls180.v:3889$364_Y
+ connect \A $and$ls180.v:3885$362_Y
+ connect \B $eq$ls180.v:3885$363_Y
+ connect \Y $and$ls180.v:3885$364_Y
end
- attribute \src "ls180.v:3895.8-3895.73"
- cell $and $and$ls180.v:3895$366
+ attribute \src "ls180.v:3891.8-3891.73"
+ cell $and $and$ls180.v:3891$366
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_choose_cmd_cmd_valid
connect \B \main_sdram_choose_cmd_cmd_ready
- connect \Y $and$ls180.v:3895$366_Y
+ connect \Y $and$ls180.v:3891$366_Y
end
- attribute \src "ls180.v:3895.7-3895.114"
- cell $and $and$ls180.v:3895$368
+ attribute \src "ls180.v:3891.7-3891.114"
+ cell $and $and$ls180.v:3891$368
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3895$366_Y
- connect \B $eq$ls180.v:3895$367_Y
- connect \Y $and$ls180.v:3895$368_Y
+ connect \A $and$ls180.v:3891$366_Y
+ connect \B $eq$ls180.v:3891$367_Y
+ connect \Y $and$ls180.v:3891$368_Y
end
- attribute \src "ls180.v:3898.8-3898.73"
- cell $and $and$ls180.v:3898$369
+ attribute \src "ls180.v:3894.8-3894.73"
+ cell $and $and$ls180.v:3894$369
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_choose_req_cmd_valid
connect \B \main_sdram_choose_req_cmd_ready
- connect \Y $and$ls180.v:3898$369_Y
+ connect \Y $and$ls180.v:3894$369_Y
end
- attribute \src "ls180.v:3898.7-3898.114"
- cell $and $and$ls180.v:3898$371
+ attribute \src "ls180.v:3894.7-3894.114"
+ cell $and $and$ls180.v:3894$371
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3898$369_Y
- connect \B $eq$ls180.v:3898$370_Y
- connect \Y $and$ls180.v:3898$371_Y
+ connect \A $and$ls180.v:3894$369_Y
+ connect \B $eq$ls180.v:3894$370_Y
+ connect \Y $and$ls180.v:3894$371_Y
end
- attribute \src "ls180.v:3904.8-3904.73"
- cell $and $and$ls180.v:3904$373
+ attribute \src "ls180.v:3900.8-3900.73"
+ cell $and $and$ls180.v:3900$373
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_choose_cmd_cmd_valid
connect \B \main_sdram_choose_cmd_cmd_ready
- connect \Y $and$ls180.v:3904$373_Y
+ connect \Y $and$ls180.v:3900$373_Y
end
- attribute \src "ls180.v:3904.7-3904.114"
- cell $and $and$ls180.v:3904$375
+ attribute \src "ls180.v:3900.7-3900.114"
+ cell $and $and$ls180.v:3900$375
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3904$373_Y
- connect \B $eq$ls180.v:3904$374_Y
- connect \Y $and$ls180.v:3904$375_Y
+ connect \A $and$ls180.v:3900$373_Y
+ connect \B $eq$ls180.v:3900$374_Y
+ connect \Y $and$ls180.v:3900$375_Y
end
- attribute \src "ls180.v:3907.8-3907.73"
- cell $and $and$ls180.v:3907$376
+ attribute \src "ls180.v:3903.8-3903.73"
+ cell $and $and$ls180.v:3903$376
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_choose_req_cmd_valid
connect \B \main_sdram_choose_req_cmd_ready
- connect \Y $and$ls180.v:3907$376_Y
+ connect \Y $and$ls180.v:3903$376_Y
end
- attribute \src "ls180.v:3907.7-3907.114"
- cell $and $and$ls180.v:3907$378
+ attribute \src "ls180.v:3903.7-3903.114"
+ cell $and $and$ls180.v:3903$378
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3907$376_Y
- connect \B $eq$ls180.v:3907$377_Y
- connect \Y $and$ls180.v:3907$378_Y
+ connect \A $and$ls180.v:3903$376_Y
+ connect \B $eq$ls180.v:3903$377_Y
+ connect \Y $and$ls180.v:3903$378_Y
end
- attribute \src "ls180.v:3932.71-3932.151"
- cell $and $and$ls180.v:3932$383
+ attribute \src "ls180.v:3928.71-3928.151"
+ cell $and $and$ls180.v:3928$383
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_choose_req_cmd_payload_ras
- connect \B $not$ls180.v:3932$382_Y
- connect \Y $and$ls180.v:3932$383_Y
+ connect \B $not$ls180.v:3928$382_Y
+ connect \Y $and$ls180.v:3928$383_Y
end
- attribute \src "ls180.v:3932.70-3932.194"
- cell $and $and$ls180.v:3932$385
+ attribute \src "ls180.v:3928.70-3928.194"
+ cell $and $and$ls180.v:3928$385
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3932$383_Y
- connect \B $not$ls180.v:3932$384_Y
- connect \Y $and$ls180.v:3932$385_Y
+ connect \A $and$ls180.v:3928$383_Y
+ connect \B $not$ls180.v:3928$384_Y
+ connect \Y $and$ls180.v:3928$385_Y
end
- attribute \src "ls180.v:3932.41-3932.222"
- cell $and $and$ls180.v:3932$388
+ attribute \src "ls180.v:3928.41-3928.222"
+ cell $and $and$ls180.v:3928$388
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_cas_allowed
- connect \B $or$ls180.v:3932$387_Y
- connect \Y $and$ls180.v:3932$388_Y
+ connect \B $or$ls180.v:3928$387_Y
+ connect \Y $and$ls180.v:3928$388_Y
end
- attribute \src "ls180.v:3970.71-3970.151"
- cell $and $and$ls180.v:3970$392
+ attribute \src "ls180.v:3966.71-3966.151"
+ cell $and $and$ls180.v:3966$392
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_choose_req_cmd_payload_ras
- connect \B $not$ls180.v:3970$391_Y
- connect \Y $and$ls180.v:3970$392_Y
+ connect \B $not$ls180.v:3966$391_Y
+ connect \Y $and$ls180.v:3966$392_Y
end
- attribute \src "ls180.v:3970.70-3970.194"
- cell $and $and$ls180.v:3970$394
+ attribute \src "ls180.v:3966.70-3966.194"
+ cell $and $and$ls180.v:3966$394
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3970$392_Y
- connect \B $not$ls180.v:3970$393_Y
- connect \Y $and$ls180.v:3970$394_Y
+ connect \A $and$ls180.v:3966$392_Y
+ connect \B $not$ls180.v:3966$393_Y
+ connect \Y $and$ls180.v:3966$394_Y
end
- attribute \src "ls180.v:3970.41-3970.222"
- cell $and $and$ls180.v:3970$397
+ attribute \src "ls180.v:3966.41-3966.222"
+ cell $and $and$ls180.v:3966$397
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_cas_allowed
- connect \B $or$ls180.v:3970$396_Y
- connect \Y $and$ls180.v:3970$397_Y
+ connect \B $or$ls180.v:3966$396_Y
+ connect \Y $and$ls180.v:3966$397_Y
end
- attribute \src "ls180.v:3988.110-3988.179"
- cell $and $and$ls180.v:3988$402
+ attribute \src "ls180.v:3984.110-3984.179"
+ cell $and $and$ls180.v:3984$402
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_interface_bank1_lock
- connect \B $eq$ls180.v:3988$401_Y
- connect \Y $and$ls180.v:3988$402_Y
+ connect \B $eq$ls180.v:3984$401_Y
+ connect \Y $and$ls180.v:3984$402_Y
end
- attribute \src "ls180.v:3988.185-3988.254"
- cell $and $and$ls180.v:3988$405
+ attribute \src "ls180.v:3984.185-3984.254"
+ cell $and $and$ls180.v:3984$405
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_interface_bank2_lock
- connect \B $eq$ls180.v:3988$404_Y
- connect \Y $and$ls180.v:3988$405_Y
+ connect \B $eq$ls180.v:3984$404_Y
+ connect \Y $and$ls180.v:3984$405_Y
end
- attribute \src "ls180.v:3988.260-3988.329"
- cell $and $and$ls180.v:3988$408
+ attribute \src "ls180.v:3984.260-3984.329"
+ cell $and $and$ls180.v:3984$408
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_interface_bank3_lock
- connect \B $eq$ls180.v:3988$407_Y
- connect \Y $and$ls180.v:3988$408_Y
+ connect \B $eq$ls180.v:3984$407_Y
+ connect \Y $and$ls180.v:3984$408_Y
end
- attribute \src "ls180.v:3988.41-3988.332"
- cell $and $and$ls180.v:3988$411
+ attribute \src "ls180.v:3984.41-3984.332"
+ cell $and $and$ls180.v:3984$411
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $eq$ls180.v:3988$400_Y
- connect \B $not$ls180.v:3988$410_Y
- connect \Y $and$ls180.v:3988$411_Y
+ connect \A $eq$ls180.v:3984$400_Y
+ connect \B $not$ls180.v:3984$410_Y
+ connect \Y $and$ls180.v:3984$411_Y
end
- attribute \src "ls180.v:3988.40-3988.355"
- cell $and $and$ls180.v:3988$412
+ attribute \src "ls180.v:3984.40-3984.355"
+ cell $and $and$ls180.v:3984$412
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3988$411_Y
+ connect \A $and$ls180.v:3984$411_Y
connect \B \main_port_cmd_valid
- connect \Y $and$ls180.v:3988$412_Y
+ connect \Y $and$ls180.v:3984$412_Y
end
- attribute \src "ls180.v:3989.34-3989.106"
- cell $and $and$ls180.v:3989$415
+ attribute \src "ls180.v:3985.34-3985.106"
+ cell $and $and$ls180.v:3985$415
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $not$ls180.v:3989$413_Y
- connect \B $not$ls180.v:3989$414_Y
- connect \Y $and$ls180.v:3989$415_Y
+ connect \A $not$ls180.v:3985$413_Y
+ connect \B $not$ls180.v:3985$414_Y
+ connect \Y $and$ls180.v:3985$415_Y
end
- attribute \src "ls180.v:3993.110-3993.179"
- cell $and $and$ls180.v:3993$418
+ attribute \src "ls180.v:3989.110-3989.179"
+ cell $and $and$ls180.v:3989$418
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_interface_bank0_lock
- connect \B $eq$ls180.v:3993$417_Y
- connect \Y $and$ls180.v:3993$418_Y
+ connect \B $eq$ls180.v:3989$417_Y
+ connect \Y $and$ls180.v:3989$418_Y
end
- attribute \src "ls180.v:3993.185-3993.254"
- cell $and $and$ls180.v:3993$421
+ attribute \src "ls180.v:3989.185-3989.254"
+ cell $and $and$ls180.v:3989$421
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_interface_bank2_lock
- connect \B $eq$ls180.v:3993$420_Y
- connect \Y $and$ls180.v:3993$421_Y
+ connect \B $eq$ls180.v:3989$420_Y
+ connect \Y $and$ls180.v:3989$421_Y
end
- attribute \src "ls180.v:3993.260-3993.329"
- cell $and $and$ls180.v:3993$424
+ attribute \src "ls180.v:3989.260-3989.329"
+ cell $and $and$ls180.v:3989$424
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_interface_bank3_lock
- connect \B $eq$ls180.v:3993$423_Y
- connect \Y $and$ls180.v:3993$424_Y
+ connect \B $eq$ls180.v:3989$423_Y
+ connect \Y $and$ls180.v:3989$424_Y
end
- attribute \src "ls180.v:3993.41-3993.332"
- cell $and $and$ls180.v:3993$427
+ attribute \src "ls180.v:3989.41-3989.332"
+ cell $and $and$ls180.v:3989$427
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $eq$ls180.v:3993$416_Y
- connect \B $not$ls180.v:3993$426_Y
- connect \Y $and$ls180.v:3993$427_Y
+ connect \A $eq$ls180.v:3989$416_Y
+ connect \B $not$ls180.v:3989$426_Y
+ connect \Y $and$ls180.v:3989$427_Y
end
- attribute \src "ls180.v:3993.40-3993.355"
- cell $and $and$ls180.v:3993$428
+ attribute \src "ls180.v:3989.40-3989.355"
+ cell $and $and$ls180.v:3989$428
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3993$427_Y
+ connect \A $and$ls180.v:3989$427_Y
connect \B \main_port_cmd_valid
- connect \Y $and$ls180.v:3993$428_Y
+ connect \Y $and$ls180.v:3989$428_Y
end
- attribute \src "ls180.v:3994.34-3994.106"
- cell $and $and$ls180.v:3994$431
+ attribute \src "ls180.v:3990.34-3990.106"
+ cell $and $and$ls180.v:3990$431
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $not$ls180.v:3994$429_Y
- connect \B $not$ls180.v:3994$430_Y
- connect \Y $and$ls180.v:3994$431_Y
+ connect \A $not$ls180.v:3990$429_Y
+ connect \B $not$ls180.v:3990$430_Y
+ connect \Y $and$ls180.v:3990$431_Y
end
- attribute \src "ls180.v:3998.110-3998.179"
- cell $and $and$ls180.v:3998$434
+ attribute \src "ls180.v:3994.110-3994.179"
+ cell $and $and$ls180.v:3994$434
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_interface_bank0_lock
- connect \B $eq$ls180.v:3998$433_Y
- connect \Y $and$ls180.v:3998$434_Y
+ connect \B $eq$ls180.v:3994$433_Y
+ connect \Y $and$ls180.v:3994$434_Y
end
- attribute \src "ls180.v:3998.185-3998.254"
- cell $and $and$ls180.v:3998$437
+ attribute \src "ls180.v:3994.185-3994.254"
+ cell $and $and$ls180.v:3994$437
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_interface_bank1_lock
- connect \B $eq$ls180.v:3998$436_Y
- connect \Y $and$ls180.v:3998$437_Y
+ connect \B $eq$ls180.v:3994$436_Y
+ connect \Y $and$ls180.v:3994$437_Y
end
- attribute \src "ls180.v:3998.260-3998.329"
- cell $and $and$ls180.v:3998$440
+ attribute \src "ls180.v:3994.260-3994.329"
+ cell $and $and$ls180.v:3994$440
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_interface_bank3_lock
- connect \B $eq$ls180.v:3998$439_Y
- connect \Y $and$ls180.v:3998$440_Y
+ connect \B $eq$ls180.v:3994$439_Y
+ connect \Y $and$ls180.v:3994$440_Y
end
- attribute \src "ls180.v:3998.41-3998.332"
- cell $and $and$ls180.v:3998$443
+ attribute \src "ls180.v:3994.41-3994.332"
+ cell $and $and$ls180.v:3994$443
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $eq$ls180.v:3998$432_Y
- connect \B $not$ls180.v:3998$442_Y
- connect \Y $and$ls180.v:3998$443_Y
+ connect \A $eq$ls180.v:3994$432_Y
+ connect \B $not$ls180.v:3994$442_Y
+ connect \Y $and$ls180.v:3994$443_Y
end
- attribute \src "ls180.v:3998.40-3998.355"
- cell $and $and$ls180.v:3998$444
+ attribute \src "ls180.v:3994.40-3994.355"
+ cell $and $and$ls180.v:3994$444
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3998$443_Y
+ connect \A $and$ls180.v:3994$443_Y
connect \B \main_port_cmd_valid
- connect \Y $and$ls180.v:3998$444_Y
+ connect \Y $and$ls180.v:3994$444_Y
end
- attribute \src "ls180.v:3999.34-3999.106"
- cell $and $and$ls180.v:3999$447
+ attribute \src "ls180.v:3995.34-3995.106"
+ cell $and $and$ls180.v:3995$447
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $not$ls180.v:3999$445_Y
- connect \B $not$ls180.v:3999$446_Y
- connect \Y $and$ls180.v:3999$447_Y
+ connect \A $not$ls180.v:3995$445_Y
+ connect \B $not$ls180.v:3995$446_Y
+ connect \Y $and$ls180.v:3995$447_Y
end
- attribute \src "ls180.v:4003.110-4003.179"
- cell $and $and$ls180.v:4003$450
+ attribute \src "ls180.v:3999.110-3999.179"
+ cell $and $and$ls180.v:3999$450
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_interface_bank0_lock
- connect \B $eq$ls180.v:4003$449_Y
- connect \Y $and$ls180.v:4003$450_Y
+ connect \B $eq$ls180.v:3999$449_Y
+ connect \Y $and$ls180.v:3999$450_Y
end
- attribute \src "ls180.v:4003.185-4003.254"
- cell $and $and$ls180.v:4003$453
+ attribute \src "ls180.v:3999.185-3999.254"
+ cell $and $and$ls180.v:3999$453
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_interface_bank1_lock
- connect \B $eq$ls180.v:4003$452_Y
- connect \Y $and$ls180.v:4003$453_Y
+ connect \B $eq$ls180.v:3999$452_Y
+ connect \Y $and$ls180.v:3999$453_Y
end
- attribute \src "ls180.v:4003.260-4003.329"
- cell $and $and$ls180.v:4003$456
+ attribute \src "ls180.v:3999.260-3999.329"
+ cell $and $and$ls180.v:3999$456
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_interface_bank2_lock
- connect \B $eq$ls180.v:4003$455_Y
- connect \Y $and$ls180.v:4003$456_Y
+ connect \B $eq$ls180.v:3999$455_Y
+ connect \Y $and$ls180.v:3999$456_Y
end
- attribute \src "ls180.v:4003.41-4003.332"
- cell $and $and$ls180.v:4003$459
+ attribute \src "ls180.v:3999.41-3999.332"
+ cell $and $and$ls180.v:3999$459
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $eq$ls180.v:4003$448_Y
- connect \B $not$ls180.v:4003$458_Y
- connect \Y $and$ls180.v:4003$459_Y
+ connect \A $eq$ls180.v:3999$448_Y
+ connect \B $not$ls180.v:3999$458_Y
+ connect \Y $and$ls180.v:3999$459_Y
end
- attribute \src "ls180.v:4003.40-4003.355"
- cell $and $and$ls180.v:4003$460
+ attribute \src "ls180.v:3999.40-3999.355"
+ cell $and $and$ls180.v:3999$460
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:4003$459_Y
+ connect \A $and$ls180.v:3999$459_Y
connect \B \main_port_cmd_valid
- connect \Y $and$ls180.v:4003$460_Y
+ connect \Y $and$ls180.v:3999$460_Y
end
- attribute \src "ls180.v:4004.34-4004.106"
- cell $and $and$ls180.v:4004$463
+ attribute \src "ls180.v:4000.34-4000.106"
+ cell $and $and$ls180.v:4000$463
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $not$ls180.v:4004$461_Y
- connect \B $not$ls180.v:4004$462_Y
- connect \Y $and$ls180.v:4004$463_Y
+ connect \A $not$ls180.v:4000$461_Y
+ connect \B $not$ls180.v:4000$462_Y
+ connect \Y $and$ls180.v:4000$463_Y
end
- attribute \src "ls180.v:4008.151-4008.220"
- cell $and $and$ls180.v:4008$467
+ attribute \src "ls180.v:4004.151-4004.220"
+ cell $and $and$ls180.v:4004$467
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_interface_bank1_lock
- connect \B $eq$ls180.v:4008$466_Y
- connect \Y $and$ls180.v:4008$467_Y
+ connect \B $eq$ls180.v:4004$466_Y
+ connect \Y $and$ls180.v:4004$467_Y
end
- attribute \src "ls180.v:4008.226-4008.295"
- cell $and $and$ls180.v:4008$470
+ attribute \src "ls180.v:4004.226-4004.295"
+ cell $and $and$ls180.v:4004$470
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_interface_bank2_lock
- connect \B $eq$ls180.v:4008$469_Y
- connect \Y $and$ls180.v:4008$470_Y
+ connect \B $eq$ls180.v:4004$469_Y
+ connect \Y $and$ls180.v:4004$470_Y
end
- attribute \src "ls180.v:4008.301-4008.370"
- cell $and $and$ls180.v:4008$473
+ attribute \src "ls180.v:4004.301-4004.370"
+ cell $and $and$ls180.v:4004$473
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_interface_bank3_lock
- connect \B $eq$ls180.v:4008$472_Y
- connect \Y $and$ls180.v:4008$473_Y
+ connect \B $eq$ls180.v:4004$472_Y
+ connect \Y $and$ls180.v:4004$473_Y
end
- attribute \src "ls180.v:4008.82-4008.373"
- cell $and $and$ls180.v:4008$476
+ attribute \src "ls180.v:4004.82-4004.373"
+ cell $and $and$ls180.v:4004$476
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $eq$ls180.v:4008$465_Y
- connect \B $not$ls180.v:4008$475_Y
- connect \Y $and$ls180.v:4008$476_Y
+ connect \A $eq$ls180.v:4004$465_Y
+ connect \B $not$ls180.v:4004$475_Y
+ connect \Y $and$ls180.v:4004$476_Y
end
- attribute \src "ls180.v:4008.43-4008.374"
- cell $and $and$ls180.v:4008$477
+ attribute \src "ls180.v:4004.43-4004.374"
+ cell $and $and$ls180.v:4004$477
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $eq$ls180.v:4008$464_Y
- connect \B $and$ls180.v:4008$476_Y
- connect \Y $and$ls180.v:4008$477_Y
+ connect \A $eq$ls180.v:4004$464_Y
+ connect \B $and$ls180.v:4004$476_Y
+ connect \Y $and$ls180.v:4004$477_Y
end
- attribute \src "ls180.v:4008.42-4008.410"
- cell $and $and$ls180.v:4008$478
+ attribute \src "ls180.v:4004.42-4004.410"
+ cell $and $and$ls180.v:4004$478
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:4008$477_Y
+ connect \A $and$ls180.v:4004$477_Y
connect \B \main_sdram_interface_bank0_ready
- connect \Y $and$ls180.v:4008$478_Y
+ connect \Y $and$ls180.v:4004$478_Y
end
- attribute \src "ls180.v:4008.525-4008.594"
- cell $and $and$ls180.v:4008$483
+ attribute \src "ls180.v:4004.525-4004.594"
+ cell $and $and$ls180.v:4004$483
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_interface_bank0_lock
- connect \B $eq$ls180.v:4008$482_Y
- connect \Y $and$ls180.v:4008$483_Y
+ connect \B $eq$ls180.v:4004$482_Y
+ connect \Y $and$ls180.v:4004$483_Y
end
- attribute \src "ls180.v:4008.600-4008.669"
- cell $and $and$ls180.v:4008$486
+ attribute \src "ls180.v:4004.600-4004.669"
+ cell $and $and$ls180.v:4004$486
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_interface_bank2_lock
- connect \B $eq$ls180.v:4008$485_Y
- connect \Y $and$ls180.v:4008$486_Y
+ connect \B $eq$ls180.v:4004$485_Y
+ connect \Y $and$ls180.v:4004$486_Y
end
- attribute \src "ls180.v:4008.675-4008.744"
- cell $and $and$ls180.v:4008$489
+ attribute \src "ls180.v:4004.675-4004.744"
+ cell $and $and$ls180.v:4004$489
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_interface_bank3_lock
- connect \B $eq$ls180.v:4008$488_Y
- connect \Y $and$ls180.v:4008$489_Y
+ connect \B $eq$ls180.v:4004$488_Y
+ connect \Y $and$ls180.v:4004$489_Y
end
- attribute \src "ls180.v:4008.456-4008.747"
- cell $and $and$ls180.v:4008$492
+ attribute \src "ls180.v:4004.456-4004.747"
+ cell $and $and$ls180.v:4004$492
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $eq$ls180.v:4008$481_Y
- connect \B $not$ls180.v:4008$491_Y
- connect \Y $and$ls180.v:4008$492_Y
+ connect \A $eq$ls180.v:4004$481_Y
+ connect \B $not$ls180.v:4004$491_Y
+ connect \Y $and$ls180.v:4004$492_Y
end
- attribute \src "ls180.v:4008.417-4008.748"
- cell $and $and$ls180.v:4008$493
+ attribute \src "ls180.v:4004.417-4004.748"
+ cell $and $and$ls180.v:4004$493
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $eq$ls180.v:4008$480_Y
- connect \B $and$ls180.v:4008$492_Y
- connect \Y $and$ls180.v:4008$493_Y
+ connect \A $eq$ls180.v:4004$480_Y
+ connect \B $and$ls180.v:4004$492_Y
+ connect \Y $and$ls180.v:4004$493_Y
end
- attribute \src "ls180.v:4008.416-4008.784"
- cell $and $and$ls180.v:4008$494
+ attribute \src "ls180.v:4004.416-4004.784"
+ cell $and $and$ls180.v:4004$494
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:4008$493_Y
+ connect \A $and$ls180.v:4004$493_Y
connect \B \main_sdram_interface_bank1_ready
- connect \Y $and$ls180.v:4008$494_Y
+ connect \Y $and$ls180.v:4004$494_Y
end
- attribute \src "ls180.v:4008.899-4008.968"
- cell $and $and$ls180.v:4008$499
+ attribute \src "ls180.v:4004.899-4004.968"
+ cell $and $and$ls180.v:4004$499
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_interface_bank0_lock
- connect \B $eq$ls180.v:4008$498_Y
- connect \Y $and$ls180.v:4008$499_Y
+ connect \B $eq$ls180.v:4004$498_Y
+ connect \Y $and$ls180.v:4004$499_Y
end
- attribute \src "ls180.v:4008.974-4008.1043"
- cell $and $and$ls180.v:4008$502
+ attribute \src "ls180.v:4004.974-4004.1043"
+ cell $and $and$ls180.v:4004$502
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_interface_bank1_lock
- connect \B $eq$ls180.v:4008$501_Y
- connect \Y $and$ls180.v:4008$502_Y
+ connect \B $eq$ls180.v:4004$501_Y
+ connect \Y $and$ls180.v:4004$502_Y
end
- attribute \src "ls180.v:4008.1049-4008.1118"
- cell $and $and$ls180.v:4008$505
+ attribute \src "ls180.v:4004.1049-4004.1118"
+ cell $and $and$ls180.v:4004$505
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_interface_bank3_lock
- connect \B $eq$ls180.v:4008$504_Y
- connect \Y $and$ls180.v:4008$505_Y
+ connect \B $eq$ls180.v:4004$504_Y
+ connect \Y $and$ls180.v:4004$505_Y
end
- attribute \src "ls180.v:4008.830-4008.1121"
- cell $and $and$ls180.v:4008$508
+ attribute \src "ls180.v:4004.830-4004.1121"
+ cell $and $and$ls180.v:4004$508
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $eq$ls180.v:4008$497_Y
- connect \B $not$ls180.v:4008$507_Y
- connect \Y $and$ls180.v:4008$508_Y
+ connect \A $eq$ls180.v:4004$497_Y
+ connect \B $not$ls180.v:4004$507_Y
+ connect \Y $and$ls180.v:4004$508_Y
end
- attribute \src "ls180.v:4008.791-4008.1122"
- cell $and $and$ls180.v:4008$509
+ attribute \src "ls180.v:4004.791-4004.1122"
+ cell $and $and$ls180.v:4004$509
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $eq$ls180.v:4008$496_Y
- connect \B $and$ls180.v:4008$508_Y
- connect \Y $and$ls180.v:4008$509_Y
+ connect \A $eq$ls180.v:4004$496_Y
+ connect \B $and$ls180.v:4004$508_Y
+ connect \Y $and$ls180.v:4004$509_Y
end
- attribute \src "ls180.v:4008.790-4008.1158"
- cell $and $and$ls180.v:4008$510
+ attribute \src "ls180.v:4004.790-4004.1158"
+ cell $and $and$ls180.v:4004$510
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:4008$509_Y
+ connect \A $and$ls180.v:4004$509_Y
connect \B \main_sdram_interface_bank2_ready
- connect \Y $and$ls180.v:4008$510_Y
+ connect \Y $and$ls180.v:4004$510_Y
end
- attribute \src "ls180.v:4008.1273-4008.1342"
- cell $and $and$ls180.v:4008$515
+ attribute \src "ls180.v:4004.1273-4004.1342"
+ cell $and $and$ls180.v:4004$515
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_interface_bank0_lock
- connect \B $eq$ls180.v:4008$514_Y
- connect \Y $and$ls180.v:4008$515_Y
+ connect \B $eq$ls180.v:4004$514_Y
+ connect \Y $and$ls180.v:4004$515_Y
end
- attribute \src "ls180.v:4008.1348-4008.1417"
- cell $and $and$ls180.v:4008$518
+ attribute \src "ls180.v:4004.1348-4004.1417"
+ cell $and $and$ls180.v:4004$518
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_interface_bank1_lock
- connect \B $eq$ls180.v:4008$517_Y
- connect \Y $and$ls180.v:4008$518_Y
+ connect \B $eq$ls180.v:4004$517_Y
+ connect \Y $and$ls180.v:4004$518_Y
end
- attribute \src "ls180.v:4008.1423-4008.1492"
- cell $and $and$ls180.v:4008$521
+ attribute \src "ls180.v:4004.1423-4004.1492"
+ cell $and $and$ls180.v:4004$521
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_interface_bank2_lock
- connect \B $eq$ls180.v:4008$520_Y
- connect \Y $and$ls180.v:4008$521_Y
+ connect \B $eq$ls180.v:4004$520_Y
+ connect \Y $and$ls180.v:4004$521_Y
end
- attribute \src "ls180.v:4008.1204-4008.1495"
- cell $and $and$ls180.v:4008$524
+ attribute \src "ls180.v:4004.1204-4004.1495"
+ cell $and $and$ls180.v:4004$524
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $eq$ls180.v:4008$513_Y
- connect \B $not$ls180.v:4008$523_Y
- connect \Y $and$ls180.v:4008$524_Y
+ connect \A $eq$ls180.v:4004$513_Y
+ connect \B $not$ls180.v:4004$523_Y
+ connect \Y $and$ls180.v:4004$524_Y
end
- attribute \src "ls180.v:4008.1165-4008.1496"
- cell $and $and$ls180.v:4008$525
+ attribute \src "ls180.v:4004.1165-4004.1496"
+ cell $and $and$ls180.v:4004$525
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $eq$ls180.v:4008$512_Y
- connect \B $and$ls180.v:4008$524_Y
- connect \Y $and$ls180.v:4008$525_Y
+ connect \A $eq$ls180.v:4004$512_Y
+ connect \B $and$ls180.v:4004$524_Y
+ connect \Y $and$ls180.v:4004$525_Y
end
- attribute \src "ls180.v:4008.1164-4008.1532"
- cell $and $and$ls180.v:4008$526
+ attribute \src "ls180.v:4004.1164-4004.1532"
+ cell $and $and$ls180.v:4004$526
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:4008$525_Y
+ connect \A $and$ls180.v:4004$525_Y
connect \B \main_sdram_interface_bank3_ready
- connect \Y $and$ls180.v:4008$526_Y
+ connect \Y $and$ls180.v:4004$526_Y
end
- attribute \src "ls180.v:4066.9-4066.46"
- cell $and $and$ls180.v:4066$532
+ attribute \src "ls180.v:4062.9-4062.46"
+ cell $and $and$ls180.v:4062$532
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_wb_sdram_stb
connect \B \main_wb_sdram_cyc
- connect \Y $and$ls180.v:4066$532_Y
+ connect \Y $and$ls180.v:4062$532_Y
end
- attribute \src "ls180.v:4084.9-4084.46"
- cell $and $and$ls180.v:4084$539
+ attribute \src "ls180.v:4080.9-4080.46"
+ cell $and $and$ls180.v:4080$539
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_wb_sdram_stb
connect \B \main_wb_sdram_cyc
- connect \Y $and$ls180.v:4084$539_Y
+ connect \Y $and$ls180.v:4080$539_Y
end
- attribute \src "ls180.v:4097.32-4097.75"
- cell $and $and$ls180.v:4097$543
+ attribute \src "ls180.v:4093.32-4093.75"
+ cell $and $and$ls180.v:4093$543
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_litedram_wb_cyc
connect \B \main_litedram_wb_stb
- connect \Y $and$ls180.v:4097$543_Y
+ connect \Y $and$ls180.v:4093$543_Y
end
- attribute \src "ls180.v:4097.31-4097.99"
- cell $and $and$ls180.v:4097$545
+ attribute \src "ls180.v:4093.31-4093.99"
+ cell $and $and$ls180.v:4093$545
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:4097$543_Y
- connect \B $not$ls180.v:4097$544_Y
- connect \Y $and$ls180.v:4097$545_Y
+ connect \A $and$ls180.v:4093$543_Y
+ connect \B $not$ls180.v:4093$544_Y
+ connect \Y $and$ls180.v:4093$545_Y
end
- attribute \src "ls180.v:4098.34-4098.102"
- cell $and $and$ls180.v:4098$547
+ attribute \src "ls180.v:4094.34-4094.102"
+ cell $and $and$ls180.v:4094$547
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:4098$546_Y
+ connect \A $or$ls180.v:4094$546_Y
connect \B \main_port_cmd_payload_we
- connect \Y $and$ls180.v:4098$547_Y
+ connect \Y $and$ls180.v:4094$547_Y
end
- attribute \src "ls180.v:4098.33-4098.128"
- cell $and $and$ls180.v:4098$549
+ attribute \src "ls180.v:4094.33-4094.128"
+ cell $and $and$ls180.v:4094$549
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:4098$547_Y
- connect \B $not$ls180.v:4098$548_Y
- connect \Y $and$ls180.v:4098$549_Y
+ connect \A $and$ls180.v:4094$547_Y
+ connect \B $not$ls180.v:4094$548_Y
+ connect \Y $and$ls180.v:4094$549_Y
end
- attribute \src "ls180.v:4099.33-4099.104"
- cell $and $and$ls180.v:4099$552
+ attribute \src "ls180.v:4095.33-4095.104"
+ cell $and $and$ls180.v:4095$552
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:4099$550_Y
- connect \B $not$ls180.v:4099$551_Y
- connect \Y $and$ls180.v:4099$552_Y
+ connect \A $or$ls180.v:4095$550_Y
+ connect \B $not$ls180.v:4095$551_Y
+ connect \Y $and$ls180.v:4095$552_Y
end
- attribute \src "ls180.v:4100.49-4100.85"
- cell $and $and$ls180.v:4100$553
+ attribute \src "ls180.v:4096.49-4096.85"
+ cell $and $and$ls180.v:4096$553
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_litedram_wb_we
connect \B \main_ack_wdata
- connect \Y $and$ls180.v:4100$553_Y
+ connect \Y $and$ls180.v:4096$553_Y
end
- attribute \src "ls180.v:4100.90-4100.129"
- cell $and $and$ls180.v:4100$555
+ attribute \src "ls180.v:4096.90-4096.129"
+ cell $and $and$ls180.v:4096$555
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $not$ls180.v:4100$554_Y
+ connect \A $not$ls180.v:4096$554_Y
connect \B \main_ack_rdata
- connect \Y $and$ls180.v:4100$555_Y
+ connect \Y $and$ls180.v:4096$555_Y
end
- attribute \src "ls180.v:4100.32-4100.131"
- cell $and $and$ls180.v:4100$557
+ attribute \src "ls180.v:4096.32-4096.131"
+ cell $and $and$ls180.v:4096$557
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_ack_cmd
- connect \B $or$ls180.v:4100$556_Y
- connect \Y $and$ls180.v:4100$557_Y
+ connect \B $or$ls180.v:4096$556_Y
+ connect \Y $and$ls180.v:4096$557_Y
end
- attribute \src "ls180.v:4101.25-4101.66"
- cell $and $and$ls180.v:4101$558
+ attribute \src "ls180.v:4097.25-4097.66"
+ cell $and $and$ls180.v:4097$558
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_port_cmd_valid
connect \B \main_port_cmd_ready
- connect \Y $and$ls180.v:4101$558_Y
+ connect \Y $and$ls180.v:4097$558_Y
end
- attribute \src "ls180.v:4102.27-4102.72"
- cell $and $and$ls180.v:4102$560
+ attribute \src "ls180.v:4098.27-4098.72"
+ cell $and $and$ls180.v:4098$560
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_port_wdata_valid
connect \B \main_port_wdata_ready
- connect \Y $and$ls180.v:4102$560_Y
+ connect \Y $and$ls180.v:4098$560_Y
end
- attribute \src "ls180.v:4103.26-4103.71"
- cell $and $and$ls180.v:4103$562
+ attribute \src "ls180.v:4099.26-4099.71"
+ cell $and $and$ls180.v:4099$562
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_port_rdata_valid
connect \B \main_port_rdata_ready
- connect \Y $and$ls180.v:4103$562_Y
+ connect \Y $and$ls180.v:4099$562_Y
end
- attribute \src "ls180.v:4132.64-4132.88"
- cell $and $and$ls180.v:4132$568
+ attribute \src "ls180.v:4128.64-4128.88"
+ cell $and $and$ls180.v:4128$568
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A 1'0
connect \B \main_uart_rxtx_we
- connect \Y $and$ls180.v:4132$568_Y
+ connect \Y $and$ls180.v:4128$568_Y
end
- attribute \src "ls180.v:4136.7-4136.78"
- cell $and $and$ls180.v:4136$572
+ attribute \src "ls180.v:4132.7-4132.78"
+ cell $and $and$ls180.v:4132$572
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_uart_eventmanager_pending_re
connect \B \main_uart_eventmanager_pending_r [0]
- connect \Y $and$ls180.v:4136$572_Y
+ connect \Y $and$ls180.v:4132$572_Y
end
- attribute \src "ls180.v:4147.7-4147.78"
- cell $and $and$ls180.v:4147$575
+ attribute \src "ls180.v:4143.7-4143.78"
+ cell $and $and$ls180.v:4143$575
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_uart_eventmanager_pending_re
connect \B \main_uart_eventmanager_pending_r [1]
- connect \Y $and$ls180.v:4147$575_Y
+ connect \Y $and$ls180.v:4143$575_Y
end
- attribute \src "ls180.v:4156.26-4156.97"
- cell $and $and$ls180.v:4156$577
+ attribute \src "ls180.v:4152.26-4152.97"
+ cell $and $and$ls180.v:4152$577
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_uart_eventmanager_pending_w [0]
connect \B \main_uart_eventmanager_storage [0]
- connect \Y $and$ls180.v:4156$577_Y
+ connect \Y $and$ls180.v:4152$577_Y
end
- attribute \src "ls180.v:4156.102-4156.173"
- cell $and $and$ls180.v:4156$578
+ attribute \src "ls180.v:4152.102-4152.173"
+ cell $and $and$ls180.v:4152$578
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_uart_eventmanager_pending_w [1]
connect \B \main_uart_eventmanager_storage [1]
- connect \Y $and$ls180.v:4156$578_Y
+ connect \Y $and$ls180.v:4152$578_Y
end
- attribute \src "ls180.v:4171.41-4171.133"
- cell $and $and$ls180.v:4171$582
+ attribute \src "ls180.v:4167.41-4167.133"
+ cell $and $and$ls180.v:4167$582
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_uart_tx_fifo_syncfifo_readable
- connect \B $or$ls180.v:4171$581_Y
- connect \Y $and$ls180.v:4171$582_Y
+ connect \B $or$ls180.v:4167$581_Y
+ connect \Y $and$ls180.v:4167$582_Y
end
- attribute \src "ls180.v:4182.39-4182.136"
- cell $and $and$ls180.v:4182$587
+ attribute \src "ls180.v:4178.39-4178.136"
+ cell $and $and$ls180.v:4178$587
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_uart_tx_fifo_syncfifo_we
- connect \B $or$ls180.v:4182$586_Y
- connect \Y $and$ls180.v:4182$587_Y
+ connect \B $or$ls180.v:4178$586_Y
+ connect \Y $and$ls180.v:4178$587_Y
end
- attribute \src "ls180.v:4183.37-4183.104"
- cell $and $and$ls180.v:4183$588
+ attribute \src "ls180.v:4179.37-4179.104"
+ cell $and $and$ls180.v:4179$588
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_uart_tx_fifo_syncfifo_readable
connect \B \main_uart_tx_fifo_syncfifo_re
- connect \Y $and$ls180.v:4183$588_Y
+ connect \Y $and$ls180.v:4179$588_Y
end
- attribute \src "ls180.v:4201.41-4201.133"
- cell $and $and$ls180.v:4201$593
+ attribute \src "ls180.v:4197.41-4197.133"
+ cell $and $and$ls180.v:4197$593
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_uart_rx_fifo_syncfifo_readable
- connect \B $or$ls180.v:4201$592_Y
- connect \Y $and$ls180.v:4201$593_Y
+ connect \B $or$ls180.v:4197$592_Y
+ connect \Y $and$ls180.v:4197$593_Y
end
- attribute \src "ls180.v:4212.39-4212.136"
- cell $and $and$ls180.v:4212$598
+ attribute \src "ls180.v:4208.39-4208.136"
+ cell $and $and$ls180.v:4208$598
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_uart_rx_fifo_syncfifo_we
- connect \B $or$ls180.v:4212$597_Y
- connect \Y $and$ls180.v:4212$598_Y
+ connect \B $or$ls180.v:4208$597_Y
+ connect \Y $and$ls180.v:4208$598_Y
end
- attribute \src "ls180.v:4213.37-4213.104"
- cell $and $and$ls180.v:4213$599
+ attribute \src "ls180.v:4209.37-4209.104"
+ cell $and $and$ls180.v:4209$599
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_uart_rx_fifo_syncfifo_readable
connect \B \main_uart_rx_fifo_syncfifo_re
- connect \Y $and$ls180.v:4213$599_Y
+ connect \Y $and$ls180.v:4209$599_Y
end
- attribute \src "ls180.v:4401.33-4401.86"
- cell $and $and$ls180.v:4401$641
+ attribute \src "ls180.v:4397.33-4397.86"
+ cell $and $and$ls180.v:4397$641
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdphy_clocker_clk1
- connect \B $not$ls180.v:4401$640_Y
- connect \Y $and$ls180.v:4401$641_Y
+ connect \B $not$ls180.v:4397$640_Y
+ connect \Y $and$ls180.v:4397$641_Y
end
- attribute \src "ls180.v:4505.9-4505.68"
- cell $and $and$ls180.v:4505$650
+ attribute \src "ls180.v:4501.9-4501.68"
+ cell $and $and$ls180.v:4501$650
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdphy_cmdw_sink_valid
connect \B \main_sdphy_cmdw_pads_out_ready
- connect \Y $and$ls180.v:4505$650_Y
+ connect \Y $and$ls180.v:4501$650_Y
end
- attribute \src "ls180.v:4525.53-4525.145"
- cell $and $and$ls180.v:4525$653
+ attribute \src "ls180.v:4521.53-4521.145"
+ cell $and $and$ls180.v:4521$653
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdphy_cmdr_cmdr_pads_in_valid
- connect \B $or$ls180.v:4525$652_Y
- connect \Y $and$ls180.v:4525$653_Y
+ connect \B $or$ls180.v:4521$652_Y
+ connect \Y $and$ls180.v:4521$653_Y
end
- attribute \src "ls180.v:4544.52-4544.137"
- cell $and $and$ls180.v:4544$656
+ attribute \src "ls180.v:4540.52-4540.137"
+ cell $and $and$ls180.v:4540$656
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdphy_cmdr_cmdr_converter_sink_valid
connect \B \main_sdphy_cmdr_cmdr_converter_sink_ready
- connect \Y $and$ls180.v:4544$656_Y
+ connect \Y $and$ls180.v:4540$656_Y
end
- attribute \src "ls180.v:4585.9-4585.68"
- cell $and $and$ls180.v:4585$664
+ attribute \src "ls180.v:4581.9-4581.68"
+ cell $and $and$ls180.v:4581$664
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdphy_cmdr_source_valid
connect \B \main_sdphy_cmdr_source_ready
- connect \Y $and$ls180.v:4585$664_Y
+ connect \Y $and$ls180.v:4581$664_Y
end
- attribute \src "ls180.v:4623.9-4623.68"
- cell $and $and$ls180.v:4623$670
+ attribute \src "ls180.v:4619.9-4619.68"
+ cell $and $and$ls180.v:4619$670
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdphy_cmdr_source_valid
connect \B \main_sdphy_cmdr_source_ready
- connect \Y $and$ls180.v:4623$670_Y
+ connect \Y $and$ls180.v:4619$670_Y
end
- attribute \src "ls180.v:4632.10-4632.69"
- cell $and $and$ls180.v:4632$671
+ attribute \src "ls180.v:4628.10-4628.69"
+ cell $and $and$ls180.v:4628$671
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdphy_cmdr_sink_valid
connect \B \main_sdphy_cmdr_pads_out_ready
- connect \Y $and$ls180.v:4632$671_Y
+ connect \Y $and$ls180.v:4628$671_Y
end
- attribute \src "ls180.v:4632.9-4632.93"
- cell $and $and$ls180.v:4632$672
+ attribute \src "ls180.v:4628.9-4628.93"
+ cell $and $and$ls180.v:4628$672
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:4632$671_Y
+ connect \A $and$ls180.v:4628$671_Y
connect \B \main_sdphy_cmdw_done
- connect \Y $and$ls180.v:4632$672_Y
+ connect \Y $and$ls180.v:4628$672_Y
end
- attribute \src "ls180.v:4652.54-4652.117"
- cell $and $and$ls180.v:4652$674
+ attribute \src "ls180.v:4648.54-4648.117"
+ cell $and $and$ls180.v:4648$674
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdphy_dataw_crcr_pads_in_valid
connect \B \main_sdphy_dataw_crcr_run
- connect \Y $and$ls180.v:4652$674_Y
+ connect \Y $and$ls180.v:4648$674_Y
end
- attribute \src "ls180.v:4671.53-4671.140"
- cell $and $and$ls180.v:4671$677
+ attribute \src "ls180.v:4667.53-4667.140"
+ cell $and $and$ls180.v:4667$677
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdphy_dataw_crcr_converter_sink_valid
connect \B \main_sdphy_dataw_crcr_converter_sink_ready
- connect \Y $and$ls180.v:4671$677_Y
+ connect \Y $and$ls180.v:4667$677_Y
end
- attribute \src "ls180.v:4768.9-4768.70"
- cell $and $and$ls180.v:4768$687
+ attribute \src "ls180.v:4764.9-4764.70"
+ cell $and $and$ls180.v:4764$687
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdphy_dataw_sink_valid
connect \B \main_sdphy_dataw_pads_out_ready
- connect \Y $and$ls180.v:4768$687_Y
+ connect \Y $and$ls180.v:4764$687_Y
end
- attribute \src "ls180.v:4786.55-4786.120"
- cell $and $and$ls180.v:4786$689
+ attribute \src "ls180.v:4782.55-4782.120"
+ cell $and $and$ls180.v:4782$689
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdphy_datar_datar_pads_in_valid
connect \B \main_sdphy_datar_datar_run
- connect \Y $and$ls180.v:4786$689_Y
+ connect \Y $and$ls180.v:4782$689_Y
end
- attribute \src "ls180.v:4805.54-4805.143"
- cell $and $and$ls180.v:4805$692
+ attribute \src "ls180.v:4801.54-4801.143"
+ cell $and $and$ls180.v:4801$692
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdphy_datar_datar_converter_sink_valid
connect \B \main_sdphy_datar_datar_converter_sink_ready
- connect \Y $and$ls180.v:4805$692_Y
+ connect \Y $and$ls180.v:4801$692_Y
end
- attribute \src "ls180.v:4887.9-4887.70"
- cell $and $and$ls180.v:4887$707
+ attribute \src "ls180.v:4883.9-4883.70"
+ cell $and $and$ls180.v:4883$707
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdphy_datar_source_valid
connect \B \main_sdphy_datar_source_ready
- connect \Y $and$ls180.v:4887$707_Y
+ connect \Y $and$ls180.v:4883$707_Y
end
- attribute \src "ls180.v:4894.9-4894.70"
- cell $and $and$ls180.v:4894$708
+ attribute \src "ls180.v:4890.9-4890.70"
+ cell $and $and$ls180.v:4890$708
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdphy_datar_sink_valid
connect \B \main_sdphy_datar_pads_out_ready
- connect \Y $and$ls180.v:4894$708_Y
+ connect \Y $and$ls180.v:4890$708_Y
end
- attribute \src "ls180.v:4975.48-4975.124"
- cell $and $and$ls180.v:4975$831
+ attribute \src "ls180.v:4971.48-4971.124"
+ cell $and $and$ls180.v:4971$831
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_inserter_sink_last
connect \B \main_sdcore_crc16_inserter_sink_valid
- connect \Y $and$ls180.v:4975$831_Y
+ connect \Y $and$ls180.v:4971$831_Y
end
- attribute \src "ls180.v:4975.47-4975.165"
- cell $and $and$ls180.v:4975$832
+ attribute \src "ls180.v:4971.47-4971.165"
+ cell $and $and$ls180.v:4971$832
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:4975$831_Y
+ connect \A $and$ls180.v:4971$831_Y
connect \B \main_sdcore_crc16_inserter_sink_ready
- connect \Y $and$ls180.v:4975$832_Y
+ connect \Y $and$ls180.v:4971$832_Y
end
- attribute \src "ls180.v:4976.50-4976.127"
- cell $and $and$ls180.v:4976$833
+ attribute \src "ls180.v:4972.50-4972.127"
+ cell $and $and$ls180.v:4972$833
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_inserter_sink_valid
connect \B \main_sdcore_crc16_inserter_sink_ready
- connect \Y $and$ls180.v:4976$833_Y
+ connect \Y $and$ls180.v:4972$833_Y
end
- attribute \src "ls180.v:4978.48-4978.124"
- cell $and $and$ls180.v:4978$834
+ attribute \src "ls180.v:4974.48-4974.124"
+ cell $and $and$ls180.v:4974$834
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_inserter_sink_last
connect \B \main_sdcore_crc16_inserter_sink_valid
- connect \Y $and$ls180.v:4978$834_Y
+ connect \Y $and$ls180.v:4974$834_Y
end
- attribute \src "ls180.v:4978.47-4978.165"
- cell $and $and$ls180.v:4978$835
+ attribute \src "ls180.v:4974.47-4974.165"
+ cell $and $and$ls180.v:4974$835
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:4978$834_Y
+ connect \A $and$ls180.v:4974$834_Y
connect \B \main_sdcore_crc16_inserter_sink_ready
- connect \Y $and$ls180.v:4978$835_Y
+ connect \Y $and$ls180.v:4974$835_Y
end
- attribute \src "ls180.v:4979.50-4979.127"
- cell $and $and$ls180.v:4979$836
+ attribute \src "ls180.v:4975.50-4975.127"
+ cell $and $and$ls180.v:4975$836
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_inserter_sink_valid
connect \B \main_sdcore_crc16_inserter_sink_ready
- connect \Y $and$ls180.v:4979$836_Y
+ connect \Y $and$ls180.v:4975$836_Y
end
- attribute \src "ls180.v:4981.48-4981.124"
- cell $and $and$ls180.v:4981$837
+ attribute \src "ls180.v:4977.48-4977.124"
+ cell $and $and$ls180.v:4977$837
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_inserter_sink_last
connect \B \main_sdcore_crc16_inserter_sink_valid
- connect \Y $and$ls180.v:4981$837_Y
+ connect \Y $and$ls180.v:4977$837_Y
end
- attribute \src "ls180.v:4981.47-4981.165"
- cell $and $and$ls180.v:4981$838
+ attribute \src "ls180.v:4977.47-4977.165"
+ cell $and $and$ls180.v:4977$838
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:4981$837_Y
+ connect \A $and$ls180.v:4977$837_Y
connect \B \main_sdcore_crc16_inserter_sink_ready
- connect \Y $and$ls180.v:4981$838_Y
+ connect \Y $and$ls180.v:4977$838_Y
end
- attribute \src "ls180.v:4982.50-4982.127"
- cell $and $and$ls180.v:4982$839
+ attribute \src "ls180.v:4978.50-4978.127"
+ cell $and $and$ls180.v:4978$839
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_inserter_sink_valid
connect \B \main_sdcore_crc16_inserter_sink_ready
- connect \Y $and$ls180.v:4982$839_Y
+ connect \Y $and$ls180.v:4978$839_Y
end
- attribute \src "ls180.v:4984.48-4984.124"
- cell $and $and$ls180.v:4984$840
+ attribute \src "ls180.v:4980.48-4980.124"
+ cell $and $and$ls180.v:4980$840
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_inserter_sink_last
connect \B \main_sdcore_crc16_inserter_sink_valid
- connect \Y $and$ls180.v:4984$840_Y
+ connect \Y $and$ls180.v:4980$840_Y
end
- attribute \src "ls180.v:4984.47-4984.165"
- cell $and $and$ls180.v:4984$841
+ attribute \src "ls180.v:4980.47-4980.165"
+ cell $and $and$ls180.v:4980$841
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:4984$840_Y
+ connect \A $and$ls180.v:4980$840_Y
connect \B \main_sdcore_crc16_inserter_sink_ready
- connect \Y $and$ls180.v:4984$841_Y
+ connect \Y $and$ls180.v:4980$841_Y
end
- attribute \src "ls180.v:4985.50-4985.127"
- cell $and $and$ls180.v:4985$842
+ attribute \src "ls180.v:4981.50-4981.127"
+ cell $and $and$ls180.v:4981$842
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_inserter_sink_valid
connect \B \main_sdcore_crc16_inserter_sink_ready
- connect \Y $and$ls180.v:4985$842_Y
+ connect \Y $and$ls180.v:4981$842_Y
end
- attribute \src "ls180.v:5098.10-5098.86"
- cell $and $and$ls180.v:5098$891
+ attribute \src "ls180.v:5094.10-5094.86"
+ cell $and $and$ls180.v:5094$891
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_inserter_sink_valid
connect \B \main_sdcore_crc16_inserter_sink_last
- connect \Y $and$ls180.v:5098$891_Y
+ connect \Y $and$ls180.v:5094$891_Y
end
- attribute \src "ls180.v:5098.9-5098.127"
- cell $and $and$ls180.v:5098$892
+ attribute \src "ls180.v:5094.9-5094.127"
+ cell $and $and$ls180.v:5094$892
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5098$891_Y
+ connect \A $and$ls180.v:5094$891_Y
connect \B \main_sdcore_crc16_inserter_sink_ready
- connect \Y $and$ls180.v:5098$892_Y
+ connect \Y $and$ls180.v:5094$892_Y
end
- attribute \src "ls180.v:5108.9-5108.152"
- cell $and $and$ls180.v:5108$896
+ attribute \src "ls180.v:5104.9-5104.152"
+ cell $and $and$ls180.v:5104$896
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $eq$ls180.v:5108$894_Y
- connect \B $eq$ls180.v:5108$895_Y
- connect \Y $and$ls180.v:5108$896_Y
+ connect \A $eq$ls180.v:5104$894_Y
+ connect \B $eq$ls180.v:5104$895_Y
+ connect \Y $and$ls180.v:5104$896_Y
end
- attribute \src "ls180.v:5108.8-5108.226"
- cell $and $and$ls180.v:5108$898
+ attribute \src "ls180.v:5104.8-5104.226"
+ cell $and $and$ls180.v:5104$898
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5108$896_Y
- connect \B $eq$ls180.v:5108$897_Y
- connect \Y $and$ls180.v:5108$898_Y
+ connect \A $and$ls180.v:5104$896_Y
+ connect \B $eq$ls180.v:5104$897_Y
+ connect \Y $and$ls180.v:5104$898_Y
end
- attribute \src "ls180.v:5108.7-5108.300"
- cell $and $and$ls180.v:5108$900
+ attribute \src "ls180.v:5104.7-5104.300"
+ cell $and $and$ls180.v:5104$900
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5108$898_Y
- connect \B $eq$ls180.v:5108$899_Y
- connect \Y $and$ls180.v:5108$900_Y
+ connect \A $and$ls180.v:5104$898_Y
+ connect \B $eq$ls180.v:5104$899_Y
+ connect \Y $and$ls180.v:5104$900_Y
end
- attribute \src "ls180.v:5113.49-5113.124"
- cell $and $and$ls180.v:5113$901
+ attribute \src "ls180.v:5109.49-5109.124"
+ cell $and $and$ls180.v:5109$901
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_checker_sink_valid
connect \B \main_sdcore_crc16_checker_sink_ready
- connect \Y $and$ls180.v:5113$901_Y
+ connect \Y $and$ls180.v:5109$901_Y
end
- attribute \src "ls180.v:5123.49-5123.124"
- cell $and $and$ls180.v:5123$904
+ attribute \src "ls180.v:5119.49-5119.124"
+ cell $and $and$ls180.v:5119$904
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_checker_sink_valid
connect \B \main_sdcore_crc16_checker_sink_ready
- connect \Y $and$ls180.v:5123$904_Y
+ connect \Y $and$ls180.v:5119$904_Y
end
- attribute \src "ls180.v:5133.49-5133.124"
- cell $and $and$ls180.v:5133$907
+ attribute \src "ls180.v:5129.49-5129.124"
+ cell $and $and$ls180.v:5129$907
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_checker_sink_valid
connect \B \main_sdcore_crc16_checker_sink_ready
- connect \Y $and$ls180.v:5133$907_Y
+ connect \Y $and$ls180.v:5129$907_Y
end
- attribute \src "ls180.v:5143.49-5143.124"
- cell $and $and$ls180.v:5143$910
+ attribute \src "ls180.v:5139.49-5139.124"
+ cell $and $and$ls180.v:5139$910
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_checker_sink_valid
connect \B \main_sdcore_crc16_checker_sink_ready
- connect \Y $and$ls180.v:5143$910_Y
+ connect \Y $and$ls180.v:5139$910_Y
end
- attribute \src "ls180.v:5155.7-5155.84"
- cell $and $and$ls180.v:5155$915
+ attribute \src "ls180.v:5151.7-5151.84"
+ cell $and $and$ls180.v:5151$915
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_checker_sink_valid
- connect \B $gt$ls180.v:5155$914_Y
- connect \Y $and$ls180.v:5155$915_Y
+ connect \B $gt$ls180.v:5151$914_Y
+ connect \Y $and$ls180.v:5151$915_Y
end
- attribute \src "ls180.v:5273.9-5273.64"
- cell $and $and$ls180.v:5273$964
+ attribute \src "ls180.v:5269.9-5269.64"
+ cell $and $and$ls180.v:5269$964
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdphy_cmdw_sink_valid
connect \B \main_sdphy_cmdw_sink_ready
- connect \Y $and$ls180.v:5273$964_Y
+ connect \Y $and$ls180.v:5269$964_Y
end
- attribute \src "ls180.v:5325.10-5325.66"
- cell $and $and$ls180.v:5325$973
+ attribute \src "ls180.v:5321.10-5321.66"
+ cell $and $and$ls180.v:5321$973
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdphy_dataw_sink_valid
connect \B \main_sdphy_dataw_sink_last
- connect \Y $and$ls180.v:5325$973_Y
+ connect \Y $and$ls180.v:5321$973_Y
end
- attribute \src "ls180.v:5325.9-5325.97"
- cell $and $and$ls180.v:5325$974
+ attribute \src "ls180.v:5321.9-5321.97"
+ cell $and $and$ls180.v:5321$974
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5325$973_Y
+ connect \A $and$ls180.v:5321$973_Y
connect \B \main_sdphy_dataw_sink_ready
- connect \Y $and$ls180.v:5325$974_Y
+ connect \Y $and$ls180.v:5321$974_Y
end
- attribute \src "ls180.v:5351.11-5351.71"
- cell $and $and$ls180.v:5351$982
+ attribute \src "ls180.v:5347.11-5347.71"
+ cell $and $and$ls180.v:5347$982
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdphy_datar_source_last
connect \B \main_sdphy_datar_source_ready
- connect \Y $and$ls180.v:5351$982_Y
+ connect \Y $and$ls180.v:5347$982_Y
end
- attribute \src "ls180.v:5435.43-5435.152"
- cell $and $and$ls180.v:5435$990
+ attribute \src "ls180.v:5431.43-5431.152"
+ cell $and $and$ls180.v:5431$990
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdblock2mem_fifo_syncfifo_we
- connect \B $or$ls180.v:5435$989_Y
- connect \Y $and$ls180.v:5435$990_Y
+ connect \B $or$ls180.v:5431$989_Y
+ connect \Y $and$ls180.v:5431$990_Y
end
- attribute \src "ls180.v:5436.41-5436.116"
- cell $and $and$ls180.v:5436$991
+ attribute \src "ls180.v:5432.41-5432.116"
+ cell $and $and$ls180.v:5432$991
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdblock2mem_fifo_syncfifo_readable
connect \B \main_sdblock2mem_fifo_syncfifo_re
- connect \Y $and$ls180.v:5436$991_Y
+ connect \Y $and$ls180.v:5432$991_Y
end
- attribute \src "ls180.v:5448.48-5448.125"
- cell $and $and$ls180.v:5448$996
+ attribute \src "ls180.v:5444.48-5444.125"
+ cell $and $and$ls180.v:5444$996
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdblock2mem_converter_sink_valid
connect \B \main_sdblock2mem_converter_sink_ready
- connect \Y $and$ls180.v:5448$996_Y
+ connect \Y $and$ls180.v:5444$996_Y
end
- attribute \src "ls180.v:5475.9-5475.102"
- cell $and $and$ls180.v:5475$1000
+ attribute \src "ls180.v:5471.9-5471.102"
+ cell $and $and$ls180.v:5471$1000
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdblock2mem_wishbonedmawriter_sink_valid
connect \B \main_sdblock2mem_wishbonedmawriter_sink_ready
- connect \Y $and$ls180.v:5475$1000_Y
+ connect \Y $and$ls180.v:5471$1000_Y
end
- attribute \src "ls180.v:5548.9-5548.58"
- cell $and $and$ls180.v:5548$1006
+ attribute \src "ls180.v:5544.9-5544.58"
+ cell $and $and$ls180.v:5544$1006
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_interface1_bus_stb
connect \B \main_interface1_bus_ack
- connect \Y $and$ls180.v:5548$1006_Y
+ connect \Y $and$ls180.v:5544$1006_Y
end
- attribute \src "ls180.v:5601.51-5601.123"
- cell $and $and$ls180.v:5601$1014
+ attribute \src "ls180.v:5597.51-5597.123"
+ cell $and $and$ls180.v:5597$1014
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdmem2block_converter_sink_first
connect \B \main_sdmem2block_converter_first
- connect \Y $and$ls180.v:5601$1014_Y
+ connect \Y $and$ls180.v:5597$1014_Y
end
- attribute \src "ls180.v:5602.50-5602.120"
- cell $and $and$ls180.v:5602$1015
+ attribute \src "ls180.v:5598.50-5598.120"
+ cell $and $and$ls180.v:5598$1015
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdmem2block_converter_sink_last
connect \B \main_sdmem2block_converter_last
- connect \Y $and$ls180.v:5602$1015_Y
+ connect \Y $and$ls180.v:5598$1015_Y
end
- attribute \src "ls180.v:5603.49-5603.122"
- cell $and $and$ls180.v:5603$1016
+ attribute \src "ls180.v:5599.49-5599.122"
+ cell $and $and$ls180.v:5599$1016
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdmem2block_converter_last
connect \B \main_sdmem2block_converter_source_ready
- connect \Y $and$ls180.v:5603$1016_Y
+ connect \Y $and$ls180.v:5599$1016_Y
end
- attribute \src "ls180.v:5643.43-5643.152"
- cell $and $and$ls180.v:5643$1021
+ attribute \src "ls180.v:5639.43-5639.152"
+ cell $and $and$ls180.v:5639$1021
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdmem2block_fifo_syncfifo_we
- connect \B $or$ls180.v:5643$1020_Y
- connect \Y $and$ls180.v:5643$1021_Y
+ connect \B $or$ls180.v:5639$1020_Y
+ connect \Y $and$ls180.v:5639$1021_Y
end
- attribute \src "ls180.v:5644.41-5644.116"
- cell $and $and$ls180.v:5644$1022
+ attribute \src "ls180.v:5640.41-5640.116"
+ cell $and $and$ls180.v:5640$1022
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdmem2block_fifo_syncfifo_readable
connect \B \main_sdmem2block_fifo_syncfifo_re
- connect \Y $and$ls180.v:5644$1022_Y
+ connect \Y $and$ls180.v:5640$1022_Y
end
- attribute \src "ls180.v:5676.9-5676.76"
- cell $and $and$ls180.v:5676$1026
+ attribute \src "ls180.v:5672.9-5672.76"
+ cell $and $and$ls180.v:5672$1026
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_libresocsim_wishbone_cyc
connect \B \builder_libresocsim_wishbone_stb
- connect \Y $and$ls180.v:5676$1026_Y
+ connect \Y $and$ls180.v:5672$1026_Y
end
- attribute \src "ls180.v:5679.44-5679.120"
- cell $and $and$ls180.v:5679$1028
+ attribute \src "ls180.v:5675.44-5675.120"
+ cell $and $and$ls180.v:5675$1028
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_libresocsim_wishbone_we
- connect \B $ne$ls180.v:5679$1027_Y
- connect \Y $and$ls180.v:5679$1028_Y
+ connect \B $ne$ls180.v:5675$1027_Y
+ connect \Y $and$ls180.v:5675$1028_Y
end
- attribute \src "ls180.v:5699.63-5699.107"
- cell $and $and$ls180.v:5699$1030
+ attribute \src "ls180.v:5695.63-5695.107"
+ cell $and $and$ls180.v:5695$1030
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_shared_ack
- connect \B $eq$ls180.v:5699$1029_Y
- connect \Y $and$ls180.v:5699$1030_Y
+ connect \B $eq$ls180.v:5695$1029_Y
+ connect \Y $and$ls180.v:5695$1030_Y
end
- attribute \src "ls180.v:5700.63-5700.107"
- cell $and $and$ls180.v:5700$1032
+ attribute \src "ls180.v:5696.63-5696.107"
+ cell $and $and$ls180.v:5696$1032
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_shared_ack
- connect \B $eq$ls180.v:5700$1031_Y
- connect \Y $and$ls180.v:5700$1032_Y
+ connect \B $eq$ls180.v:5696$1031_Y
+ connect \Y $and$ls180.v:5696$1032_Y
end
- attribute \src "ls180.v:5701.63-5701.107"
- cell $and $and$ls180.v:5701$1034
+ attribute \src "ls180.v:5697.63-5697.107"
+ cell $and $and$ls180.v:5697$1034
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_shared_ack
- connect \B $eq$ls180.v:5701$1033_Y
- connect \Y $and$ls180.v:5701$1034_Y
+ connect \B $eq$ls180.v:5697$1033_Y
+ connect \Y $and$ls180.v:5697$1034_Y
end
- attribute \src "ls180.v:5702.35-5702.79"
- cell $and $and$ls180.v:5702$1036
+ attribute \src "ls180.v:5698.35-5698.79"
+ cell $and $and$ls180.v:5698$1036
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_shared_ack
- connect \B $eq$ls180.v:5702$1035_Y
- connect \Y $and$ls180.v:5702$1036_Y
+ connect \B $eq$ls180.v:5698$1035_Y
+ connect \Y $and$ls180.v:5698$1036_Y
end
- attribute \src "ls180.v:5703.35-5703.79"
- cell $and $and$ls180.v:5703$1038
+ attribute \src "ls180.v:5699.35-5699.79"
+ cell $and $and$ls180.v:5699$1038
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_shared_ack
- connect \B $eq$ls180.v:5703$1037_Y
- connect \Y $and$ls180.v:5703$1038_Y
+ connect \B $eq$ls180.v:5699$1037_Y
+ connect \Y $and$ls180.v:5699$1038_Y
end
- attribute \src "ls180.v:5704.63-5704.107"
- cell $and $and$ls180.v:5704$1040
+ attribute \src "ls180.v:5700.63-5700.107"
+ cell $and $and$ls180.v:5700$1040
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_shared_err
- connect \B $eq$ls180.v:5704$1039_Y
- connect \Y $and$ls180.v:5704$1040_Y
+ connect \B $eq$ls180.v:5700$1039_Y
+ connect \Y $and$ls180.v:5700$1040_Y
end
- attribute \src "ls180.v:5705.63-5705.107"
- cell $and $and$ls180.v:5705$1042
+ attribute \src "ls180.v:5701.63-5701.107"
+ cell $and $and$ls180.v:5701$1042
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_shared_err
- connect \B $eq$ls180.v:5705$1041_Y
- connect \Y $and$ls180.v:5705$1042_Y
+ connect \B $eq$ls180.v:5701$1041_Y
+ connect \Y $and$ls180.v:5701$1042_Y
end
- attribute \src "ls180.v:5706.63-5706.107"
- cell $and $and$ls180.v:5706$1044
+ attribute \src "ls180.v:5702.63-5702.107"
+ cell $and $and$ls180.v:5702$1044
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_shared_err
- connect \B $eq$ls180.v:5706$1043_Y
- connect \Y $and$ls180.v:5706$1044_Y
+ connect \B $eq$ls180.v:5702$1043_Y
+ connect \Y $and$ls180.v:5702$1044_Y
end
- attribute \src "ls180.v:5707.35-5707.79"
- cell $and $and$ls180.v:5707$1046
+ attribute \src "ls180.v:5703.35-5703.79"
+ cell $and $and$ls180.v:5703$1046
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_shared_err
- connect \B $eq$ls180.v:5707$1045_Y
- connect \Y $and$ls180.v:5707$1046_Y
+ connect \B $eq$ls180.v:5703$1045_Y
+ connect \Y $and$ls180.v:5703$1046_Y
end
- attribute \src "ls180.v:5708.35-5708.79"
- cell $and $and$ls180.v:5708$1048
+ attribute \src "ls180.v:5704.35-5704.79"
+ cell $and $and$ls180.v:5704$1048
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_shared_err
- connect \B $eq$ls180.v:5708$1047_Y
- connect \Y $and$ls180.v:5708$1048_Y
+ connect \B $eq$ls180.v:5704$1047_Y
+ connect \Y $and$ls180.v:5704$1048_Y
end
- attribute \src "ls180.v:5753.40-5753.81"
- cell $and $and$ls180.v:5753$1055
+ attribute \src "ls180.v:5749.40-5749.81"
+ cell $and $and$ls180.v:5749$1055
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_shared_cyc
connect \B \builder_slave_sel [0]
- connect \Y $and$ls180.v:5753$1055_Y
+ connect \Y $and$ls180.v:5749$1055_Y
end
- attribute \src "ls180.v:5754.50-5754.91"
- cell $and $and$ls180.v:5754$1056
+ attribute \src "ls180.v:5750.50-5750.91"
+ cell $and $and$ls180.v:5750$1056
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_shared_cyc
connect \B \builder_slave_sel [1]
- connect \Y $and$ls180.v:5754$1056_Y
+ connect \Y $and$ls180.v:5750$1056_Y
end
- attribute \src "ls180.v:5755.50-5755.91"
- cell $and $and$ls180.v:5755$1057
+ attribute \src "ls180.v:5751.50-5751.91"
+ cell $and $and$ls180.v:5751$1057
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_shared_cyc
connect \B \builder_slave_sel [2]
- connect \Y $and$ls180.v:5755$1057_Y
+ connect \Y $and$ls180.v:5751$1057_Y
end
- attribute \src "ls180.v:5756.29-5756.70"
- cell $and $and$ls180.v:5756$1058
+ attribute \src "ls180.v:5752.29-5752.70"
+ cell $and $and$ls180.v:5752$1058
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_shared_cyc
connect \B \builder_slave_sel [3]
- connect \Y $and$ls180.v:5756$1058_Y
+ connect \Y $and$ls180.v:5752$1058_Y
end
- attribute \src "ls180.v:5757.44-5757.85"
- cell $and $and$ls180.v:5757$1059
+ attribute \src "ls180.v:5753.44-5753.85"
+ cell $and $and$ls180.v:5753$1059
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_shared_cyc
connect \B \builder_slave_sel [4]
- connect \Y $and$ls180.v:5757$1059_Y
+ connect \Y $and$ls180.v:5753$1059_Y
end
- attribute \src "ls180.v:5759.25-5759.64"
- cell $and $and$ls180.v:5759$1064
+ attribute \src "ls180.v:5755.25-5755.64"
+ cell $and $and$ls180.v:5755$1064
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_shared_stb
connect \B \builder_shared_cyc
- connect \Y $and$ls180.v:5759$1064_Y
+ connect \Y $and$ls180.v:5755$1064_Y
end
- attribute \src "ls180.v:5759.24-5759.89"
- cell $and $and$ls180.v:5759$1066
+ attribute \src "ls180.v:5755.24-5755.89"
+ cell $and $and$ls180.v:5755$1066
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5759$1064_Y
- connect \B $not$ls180.v:5759$1065_Y
- connect \Y $and$ls180.v:5759$1066_Y
+ connect \A $and$ls180.v:5755$1064_Y
+ connect \B $not$ls180.v:5755$1065_Y
+ connect \Y $and$ls180.v:5755$1066_Y
end
- attribute \src "ls180.v:5765.31-5765.92"
- cell $and $and$ls180.v:5765$1072
+ attribute \src "ls180.v:5761.31-5761.92"
+ cell $and $and$ls180.v:5761$1072
parameter \A_SIGNED 0
parameter \A_WIDTH 32
parameter \B_SIGNED 0
parameter \Y_WIDTH 32
connect \A { \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] }
connect \B \main_libresocsim_ram_bus_dat_r
- connect \Y $and$ls180.v:5765$1072_Y
+ connect \Y $and$ls180.v:5761$1072_Y
end
- attribute \src "ls180.v:5765.97-5765.168"
- cell $and $and$ls180.v:5765$1073
+ attribute \src "ls180.v:5761.97-5761.168"
+ cell $and $and$ls180.v:5761$1073
parameter \A_SIGNED 0
parameter \A_WIDTH 32
parameter \B_SIGNED 0
parameter \Y_WIDTH 32
connect \A { \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] }
connect \B \main_libresocsim_libresoc_xics_icp_dat_r
- connect \Y $and$ls180.v:5765$1073_Y
+ connect \Y $and$ls180.v:5761$1073_Y
end
- attribute \src "ls180.v:5765.174-5765.245"
- cell $and $and$ls180.v:5765$1075
+ attribute \src "ls180.v:5761.174-5761.245"
+ cell $and $and$ls180.v:5761$1075
parameter \A_SIGNED 0
parameter \A_WIDTH 32
parameter \B_SIGNED 0
parameter \Y_WIDTH 32
connect \A { \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] }
connect \B \main_libresocsim_libresoc_xics_ics_dat_r
- connect \Y $and$ls180.v:5765$1075_Y
+ connect \Y $and$ls180.v:5761$1075_Y
end
- attribute \src "ls180.v:5765.251-5765.301"
- cell $and $and$ls180.v:5765$1077
+ attribute \src "ls180.v:5761.251-5761.301"
+ cell $and $and$ls180.v:5761$1077
parameter \A_SIGNED 0
parameter \A_WIDTH 32
parameter \B_SIGNED 0
parameter \Y_WIDTH 32
connect \A { \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] }
connect \B \main_wb_sdram_dat_r
- connect \Y $and$ls180.v:5765$1077_Y
+ connect \Y $and$ls180.v:5761$1077_Y
end
- attribute \src "ls180.v:5765.307-5765.372"
- cell $and $and$ls180.v:5765$1079
+ attribute \src "ls180.v:5761.307-5761.372"
+ cell $and $and$ls180.v:5761$1079
parameter \A_SIGNED 0
parameter \A_WIDTH 32
parameter \B_SIGNED 0
parameter \Y_WIDTH 32
connect \A { \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] }
connect \B \builder_libresocsim_wishbone_dat_r
- connect \Y $and$ls180.v:5765$1079_Y
+ connect \Y $and$ls180.v:5761$1079_Y
end
- attribute \src "ls180.v:5775.39-5775.92"
- cell $and $and$ls180.v:5775$1083
+ attribute \src "ls180.v:5771.39-5771.92"
+ cell $and $and$ls180.v:5771$1083
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank0_sel
connect \B \builder_interface0_bank_bus_we
- connect \Y $and$ls180.v:5775$1083_Y
+ connect \Y $and$ls180.v:5771$1083_Y
end
- attribute \src "ls180.v:5775.38-5775.142"
- cell $and $and$ls180.v:5775$1085
+ attribute \src "ls180.v:5771.38-5771.142"
+ cell $and $and$ls180.v:5771$1085
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5775$1083_Y
- connect \B $eq$ls180.v:5775$1084_Y
- connect \Y $and$ls180.v:5775$1085_Y
+ connect \A $and$ls180.v:5771$1083_Y
+ connect \B $eq$ls180.v:5771$1084_Y
+ connect \Y $and$ls180.v:5771$1085_Y
end
- attribute \src "ls180.v:5776.39-5776.95"
- cell $and $and$ls180.v:5776$1087
+ attribute \src "ls180.v:5772.39-5772.95"
+ cell $and $and$ls180.v:5772$1087
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank0_sel
- connect \B $not$ls180.v:5776$1086_Y
- connect \Y $and$ls180.v:5776$1087_Y
+ connect \B $not$ls180.v:5772$1086_Y
+ connect \Y $and$ls180.v:5772$1087_Y
end
- attribute \src "ls180.v:5776.38-5776.145"
- cell $and $and$ls180.v:5776$1089
+ attribute \src "ls180.v:5772.38-5772.145"
+ cell $and $and$ls180.v:5772$1089
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5776$1087_Y
- connect \B $eq$ls180.v:5776$1088_Y
- connect \Y $and$ls180.v:5776$1089_Y
+ connect \A $and$ls180.v:5772$1087_Y
+ connect \B $eq$ls180.v:5772$1088_Y
+ connect \Y $and$ls180.v:5772$1089_Y
end
- attribute \src "ls180.v:5778.41-5778.94"
- cell $and $and$ls180.v:5778$1090
+ attribute \src "ls180.v:5774.41-5774.94"
+ cell $and $and$ls180.v:5774$1090
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank0_sel
connect \B \builder_interface0_bank_bus_we
- connect \Y $and$ls180.v:5778$1090_Y
+ connect \Y $and$ls180.v:5774$1090_Y
end
- attribute \src "ls180.v:5778.40-5778.144"
- cell $and $and$ls180.v:5778$1092
+ attribute \src "ls180.v:5774.40-5774.144"
+ cell $and $and$ls180.v:5774$1092
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5778$1090_Y
- connect \B $eq$ls180.v:5778$1091_Y
- connect \Y $and$ls180.v:5778$1092_Y
+ connect \A $and$ls180.v:5774$1090_Y
+ connect \B $eq$ls180.v:5774$1091_Y
+ connect \Y $and$ls180.v:5774$1092_Y
end
- attribute \src "ls180.v:5779.41-5779.97"
- cell $and $and$ls180.v:5779$1094
+ attribute \src "ls180.v:5775.41-5775.97"
+ cell $and $and$ls180.v:5775$1094
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank0_sel
- connect \B $not$ls180.v:5779$1093_Y
- connect \Y $and$ls180.v:5779$1094_Y
+ connect \B $not$ls180.v:5775$1093_Y
+ connect \Y $and$ls180.v:5775$1094_Y
end
- attribute \src "ls180.v:5779.40-5779.147"
- cell $and $and$ls180.v:5779$1096
+ attribute \src "ls180.v:5775.40-5775.147"
+ cell $and $and$ls180.v:5775$1096
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5779$1094_Y
- connect \B $eq$ls180.v:5779$1095_Y
- connect \Y $and$ls180.v:5779$1096_Y
+ connect \A $and$ls180.v:5775$1094_Y
+ connect \B $eq$ls180.v:5775$1095_Y
+ connect \Y $and$ls180.v:5775$1096_Y
end
- attribute \src "ls180.v:5781.41-5781.94"
- cell $and $and$ls180.v:5781$1097
+ attribute \src "ls180.v:5777.41-5777.94"
+ cell $and $and$ls180.v:5777$1097
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank0_sel
connect \B \builder_interface0_bank_bus_we
- connect \Y $and$ls180.v:5781$1097_Y
+ connect \Y $and$ls180.v:5777$1097_Y
end
- attribute \src "ls180.v:5781.40-5781.144"
- cell $and $and$ls180.v:5781$1099
+ attribute \src "ls180.v:5777.40-5777.144"
+ cell $and $and$ls180.v:5777$1099
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5781$1097_Y
- connect \B $eq$ls180.v:5781$1098_Y
- connect \Y $and$ls180.v:5781$1099_Y
+ connect \A $and$ls180.v:5777$1097_Y
+ connect \B $eq$ls180.v:5777$1098_Y
+ connect \Y $and$ls180.v:5777$1099_Y
end
- attribute \src "ls180.v:5782.41-5782.97"
- cell $and $and$ls180.v:5782$1101
+ attribute \src "ls180.v:5778.41-5778.97"
+ cell $and $and$ls180.v:5778$1101
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank0_sel
- connect \B $not$ls180.v:5782$1100_Y
- connect \Y $and$ls180.v:5782$1101_Y
+ connect \B $not$ls180.v:5778$1100_Y
+ connect \Y $and$ls180.v:5778$1101_Y
end
- attribute \src "ls180.v:5782.40-5782.147"
- cell $and $and$ls180.v:5782$1103
+ attribute \src "ls180.v:5778.40-5778.147"
+ cell $and $and$ls180.v:5778$1103
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5782$1101_Y
- connect \B $eq$ls180.v:5782$1102_Y
- connect \Y $and$ls180.v:5782$1103_Y
+ connect \A $and$ls180.v:5778$1101_Y
+ connect \B $eq$ls180.v:5778$1102_Y
+ connect \Y $and$ls180.v:5778$1103_Y
end
- attribute \src "ls180.v:5784.41-5784.94"
- cell $and $and$ls180.v:5784$1104
+ attribute \src "ls180.v:5780.41-5780.94"
+ cell $and $and$ls180.v:5780$1104
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank0_sel
connect \B \builder_interface0_bank_bus_we
- connect \Y $and$ls180.v:5784$1104_Y
+ connect \Y $and$ls180.v:5780$1104_Y
end
- attribute \src "ls180.v:5784.40-5784.144"
- cell $and $and$ls180.v:5784$1106
+ attribute \src "ls180.v:5780.40-5780.144"
+ cell $and $and$ls180.v:5780$1106
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5784$1104_Y
- connect \B $eq$ls180.v:5784$1105_Y
- connect \Y $and$ls180.v:5784$1106_Y
+ connect \A $and$ls180.v:5780$1104_Y
+ connect \B $eq$ls180.v:5780$1105_Y
+ connect \Y $and$ls180.v:5780$1106_Y
end
- attribute \src "ls180.v:5785.41-5785.97"
- cell $and $and$ls180.v:5785$1108
+ attribute \src "ls180.v:5781.41-5781.97"
+ cell $and $and$ls180.v:5781$1108
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank0_sel
- connect \B $not$ls180.v:5785$1107_Y
- connect \Y $and$ls180.v:5785$1108_Y
+ connect \B $not$ls180.v:5781$1107_Y
+ connect \Y $and$ls180.v:5781$1108_Y
end
- attribute \src "ls180.v:5785.40-5785.147"
- cell $and $and$ls180.v:5785$1110
+ attribute \src "ls180.v:5781.40-5781.147"
+ cell $and $and$ls180.v:5781$1110
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5785$1108_Y
- connect \B $eq$ls180.v:5785$1109_Y
- connect \Y $and$ls180.v:5785$1110_Y
+ connect \A $and$ls180.v:5781$1108_Y
+ connect \B $eq$ls180.v:5781$1109_Y
+ connect \Y $and$ls180.v:5781$1110_Y
end
- attribute \src "ls180.v:5787.41-5787.94"
- cell $and $and$ls180.v:5787$1111
+ attribute \src "ls180.v:5783.41-5783.94"
+ cell $and $and$ls180.v:5783$1111
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank0_sel
connect \B \builder_interface0_bank_bus_we
- connect \Y $and$ls180.v:5787$1111_Y
+ connect \Y $and$ls180.v:5783$1111_Y
end
- attribute \src "ls180.v:5787.40-5787.144"
- cell $and $and$ls180.v:5787$1113
+ attribute \src "ls180.v:5783.40-5783.144"
+ cell $and $and$ls180.v:5783$1113
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5787$1111_Y
- connect \B $eq$ls180.v:5787$1112_Y
- connect \Y $and$ls180.v:5787$1113_Y
+ connect \A $and$ls180.v:5783$1111_Y
+ connect \B $eq$ls180.v:5783$1112_Y
+ connect \Y $and$ls180.v:5783$1113_Y
end
- attribute \src "ls180.v:5788.41-5788.97"
- cell $and $and$ls180.v:5788$1115
+ attribute \src "ls180.v:5784.41-5784.97"
+ cell $and $and$ls180.v:5784$1115
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank0_sel
- connect \B $not$ls180.v:5788$1114_Y
- connect \Y $and$ls180.v:5788$1115_Y
+ connect \B $not$ls180.v:5784$1114_Y
+ connect \Y $and$ls180.v:5784$1115_Y
end
- attribute \src "ls180.v:5788.40-5788.147"
- cell $and $and$ls180.v:5788$1117
+ attribute \src "ls180.v:5784.40-5784.147"
+ cell $and $and$ls180.v:5784$1117
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5788$1115_Y
- connect \B $eq$ls180.v:5788$1116_Y
- connect \Y $and$ls180.v:5788$1117_Y
+ connect \A $and$ls180.v:5784$1115_Y
+ connect \B $eq$ls180.v:5784$1116_Y
+ connect \Y $and$ls180.v:5784$1117_Y
end
- attribute \src "ls180.v:5790.44-5790.97"
- cell $and $and$ls180.v:5790$1118
+ attribute \src "ls180.v:5786.44-5786.97"
+ cell $and $and$ls180.v:5786$1118
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank0_sel
connect \B \builder_interface0_bank_bus_we
- connect \Y $and$ls180.v:5790$1118_Y
+ connect \Y $and$ls180.v:5786$1118_Y
end
- attribute \src "ls180.v:5790.43-5790.147"
- cell $and $and$ls180.v:5790$1120
+ attribute \src "ls180.v:5786.43-5786.147"
+ cell $and $and$ls180.v:5786$1120
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5790$1118_Y
- connect \B $eq$ls180.v:5790$1119_Y
- connect \Y $and$ls180.v:5790$1120_Y
+ connect \A $and$ls180.v:5786$1118_Y
+ connect \B $eq$ls180.v:5786$1119_Y
+ connect \Y $and$ls180.v:5786$1120_Y
end
- attribute \src "ls180.v:5791.44-5791.100"
- cell $and $and$ls180.v:5791$1122
+ attribute \src "ls180.v:5787.44-5787.100"
+ cell $and $and$ls180.v:5787$1122
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank0_sel
- connect \B $not$ls180.v:5791$1121_Y
- connect \Y $and$ls180.v:5791$1122_Y
+ connect \B $not$ls180.v:5787$1121_Y
+ connect \Y $and$ls180.v:5787$1122_Y
end
- attribute \src "ls180.v:5791.43-5791.150"
- cell $and $and$ls180.v:5791$1124
+ attribute \src "ls180.v:5787.43-5787.150"
+ cell $and $and$ls180.v:5787$1124
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5791$1122_Y
- connect \B $eq$ls180.v:5791$1123_Y
- connect \Y $and$ls180.v:5791$1124_Y
+ connect \A $and$ls180.v:5787$1122_Y
+ connect \B $eq$ls180.v:5787$1123_Y
+ connect \Y $and$ls180.v:5787$1124_Y
end
- attribute \src "ls180.v:5793.44-5793.97"
- cell $and $and$ls180.v:5793$1125
+ attribute \src "ls180.v:5789.44-5789.97"
+ cell $and $and$ls180.v:5789$1125
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank0_sel
connect \B \builder_interface0_bank_bus_we
- connect \Y $and$ls180.v:5793$1125_Y
+ connect \Y $and$ls180.v:5789$1125_Y
end
- attribute \src "ls180.v:5793.43-5793.147"
- cell $and $and$ls180.v:5793$1127
+ attribute \src "ls180.v:5789.43-5789.147"
+ cell $and $and$ls180.v:5789$1127
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5793$1125_Y
- connect \B $eq$ls180.v:5793$1126_Y
- connect \Y $and$ls180.v:5793$1127_Y
+ connect \A $and$ls180.v:5789$1125_Y
+ connect \B $eq$ls180.v:5789$1126_Y
+ connect \Y $and$ls180.v:5789$1127_Y
end
- attribute \src "ls180.v:5794.44-5794.100"
- cell $and $and$ls180.v:5794$1129
+ attribute \src "ls180.v:5790.44-5790.100"
+ cell $and $and$ls180.v:5790$1129
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank0_sel
- connect \B $not$ls180.v:5794$1128_Y
- connect \Y $and$ls180.v:5794$1129_Y
+ connect \B $not$ls180.v:5790$1128_Y
+ connect \Y $and$ls180.v:5790$1129_Y
end
- attribute \src "ls180.v:5794.43-5794.150"
- cell $and $and$ls180.v:5794$1131
+ attribute \src "ls180.v:5790.43-5790.150"
+ cell $and $and$ls180.v:5790$1131
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5794$1129_Y
- connect \B $eq$ls180.v:5794$1130_Y
- connect \Y $and$ls180.v:5794$1131_Y
+ connect \A $and$ls180.v:5790$1129_Y
+ connect \B $eq$ls180.v:5790$1130_Y
+ connect \Y $and$ls180.v:5790$1131_Y
end
- attribute \src "ls180.v:5796.44-5796.97"
- cell $and $and$ls180.v:5796$1132
+ attribute \src "ls180.v:5792.44-5792.97"
+ cell $and $and$ls180.v:5792$1132
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank0_sel
connect \B \builder_interface0_bank_bus_we
- connect \Y $and$ls180.v:5796$1132_Y
+ connect \Y $and$ls180.v:5792$1132_Y
end
- attribute \src "ls180.v:5796.43-5796.147"
- cell $and $and$ls180.v:5796$1134
+ attribute \src "ls180.v:5792.43-5792.147"
+ cell $and $and$ls180.v:5792$1134
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5796$1132_Y
- connect \B $eq$ls180.v:5796$1133_Y
- connect \Y $and$ls180.v:5796$1134_Y
+ connect \A $and$ls180.v:5792$1132_Y
+ connect \B $eq$ls180.v:5792$1133_Y
+ connect \Y $and$ls180.v:5792$1134_Y
end
- attribute \src "ls180.v:5797.44-5797.100"
- cell $and $and$ls180.v:5797$1136
+ attribute \src "ls180.v:5793.44-5793.100"
+ cell $and $and$ls180.v:5793$1136
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank0_sel
- connect \B $not$ls180.v:5797$1135_Y
- connect \Y $and$ls180.v:5797$1136_Y
+ connect \B $not$ls180.v:5793$1135_Y
+ connect \Y $and$ls180.v:5793$1136_Y
end
- attribute \src "ls180.v:5797.43-5797.150"
- cell $and $and$ls180.v:5797$1138
+ attribute \src "ls180.v:5793.43-5793.150"
+ cell $and $and$ls180.v:5793$1138
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5797$1136_Y
- connect \B $eq$ls180.v:5797$1137_Y
- connect \Y $and$ls180.v:5797$1138_Y
+ connect \A $and$ls180.v:5793$1136_Y
+ connect \B $eq$ls180.v:5793$1137_Y
+ connect \Y $and$ls180.v:5793$1138_Y
end
- attribute \src "ls180.v:5799.44-5799.97"
- cell $and $and$ls180.v:5799$1139
+ attribute \src "ls180.v:5795.44-5795.97"
+ cell $and $and$ls180.v:5795$1139
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank0_sel
connect \B \builder_interface0_bank_bus_we
- connect \Y $and$ls180.v:5799$1139_Y
+ connect \Y $and$ls180.v:5795$1139_Y
end
- attribute \src "ls180.v:5799.43-5799.147"
- cell $and $and$ls180.v:5799$1141
+ attribute \src "ls180.v:5795.43-5795.147"
+ cell $and $and$ls180.v:5795$1141
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5799$1139_Y
- connect \B $eq$ls180.v:5799$1140_Y
- connect \Y $and$ls180.v:5799$1141_Y
+ connect \A $and$ls180.v:5795$1139_Y
+ connect \B $eq$ls180.v:5795$1140_Y
+ connect \Y $and$ls180.v:5795$1141_Y
end
- attribute \src "ls180.v:5800.44-5800.100"
- cell $and $and$ls180.v:5800$1143
+ attribute \src "ls180.v:5796.44-5796.100"
+ cell $and $and$ls180.v:5796$1143
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank0_sel
- connect \B $not$ls180.v:5800$1142_Y
- connect \Y $and$ls180.v:5800$1143_Y
+ connect \B $not$ls180.v:5796$1142_Y
+ connect \Y $and$ls180.v:5796$1143_Y
end
- attribute \src "ls180.v:5800.43-5800.150"
- cell $and $and$ls180.v:5800$1145
+ attribute \src "ls180.v:5796.43-5796.150"
+ cell $and $and$ls180.v:5796$1145
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5800$1143_Y
- connect \B $eq$ls180.v:5800$1144_Y
- connect \Y $and$ls180.v:5800$1145_Y
+ connect \A $and$ls180.v:5796$1143_Y
+ connect \B $eq$ls180.v:5796$1144_Y
+ connect \Y $and$ls180.v:5796$1145_Y
end
- attribute \src "ls180.v:5813.36-5813.89"
- cell $and $and$ls180.v:5813$1147
+ attribute \src "ls180.v:5809.36-5809.89"
+ cell $and $and$ls180.v:5809$1147
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank1_sel
connect \B \builder_interface1_bank_bus_we
- connect \Y $and$ls180.v:5813$1147_Y
+ connect \Y $and$ls180.v:5809$1147_Y
end
- attribute \src "ls180.v:5813.35-5813.139"
- cell $and $and$ls180.v:5813$1149
+ attribute \src "ls180.v:5809.35-5809.139"
+ cell $and $and$ls180.v:5809$1149
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5813$1147_Y
- connect \B $eq$ls180.v:5813$1148_Y
- connect \Y $and$ls180.v:5813$1149_Y
+ connect \A $and$ls180.v:5809$1147_Y
+ connect \B $eq$ls180.v:5809$1148_Y
+ connect \Y $and$ls180.v:5809$1149_Y
end
- attribute \src "ls180.v:5814.36-5814.92"
- cell $and $and$ls180.v:5814$1151
+ attribute \src "ls180.v:5810.36-5810.92"
+ cell $and $and$ls180.v:5810$1151
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank1_sel
- connect \B $not$ls180.v:5814$1150_Y
- connect \Y $and$ls180.v:5814$1151_Y
+ connect \B $not$ls180.v:5810$1150_Y
+ connect \Y $and$ls180.v:5810$1151_Y
end
- attribute \src "ls180.v:5814.35-5814.142"
- cell $and $and$ls180.v:5814$1153
+ attribute \src "ls180.v:5810.35-5810.142"
+ cell $and $and$ls180.v:5810$1153
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5814$1151_Y
- connect \B $eq$ls180.v:5814$1152_Y
- connect \Y $and$ls180.v:5814$1153_Y
+ connect \A $and$ls180.v:5810$1151_Y
+ connect \B $eq$ls180.v:5810$1152_Y
+ connect \Y $and$ls180.v:5810$1153_Y
end
- attribute \src "ls180.v:5816.36-5816.89"
- cell $and $and$ls180.v:5816$1154
+ attribute \src "ls180.v:5812.36-5812.89"
+ cell $and $and$ls180.v:5812$1154
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank1_sel
connect \B \builder_interface1_bank_bus_we
- connect \Y $and$ls180.v:5816$1154_Y
+ connect \Y $and$ls180.v:5812$1154_Y
end
- attribute \src "ls180.v:5816.35-5816.139"
- cell $and $and$ls180.v:5816$1156
+ attribute \src "ls180.v:5812.35-5812.139"
+ cell $and $and$ls180.v:5812$1156
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5816$1154_Y
- connect \B $eq$ls180.v:5816$1155_Y
- connect \Y $and$ls180.v:5816$1156_Y
+ connect \A $and$ls180.v:5812$1154_Y
+ connect \B $eq$ls180.v:5812$1155_Y
+ connect \Y $and$ls180.v:5812$1156_Y
end
- attribute \src "ls180.v:5817.36-5817.92"
- cell $and $and$ls180.v:5817$1158
+ attribute \src "ls180.v:5813.36-5813.92"
+ cell $and $and$ls180.v:5813$1158
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank1_sel
- connect \B $not$ls180.v:5817$1157_Y
- connect \Y $and$ls180.v:5817$1158_Y
+ connect \B $not$ls180.v:5813$1157_Y
+ connect \Y $and$ls180.v:5813$1158_Y
end
- attribute \src "ls180.v:5817.35-5817.142"
- cell $and $and$ls180.v:5817$1160
+ attribute \src "ls180.v:5813.35-5813.142"
+ cell $and $and$ls180.v:5813$1160
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5817$1158_Y
- connect \B $eq$ls180.v:5817$1159_Y
- connect \Y $and$ls180.v:5817$1160_Y
+ connect \A $and$ls180.v:5813$1158_Y
+ connect \B $eq$ls180.v:5813$1159_Y
+ connect \Y $and$ls180.v:5813$1160_Y
end
- attribute \src "ls180.v:5819.36-5819.89"
- cell $and $and$ls180.v:5819$1161
+ attribute \src "ls180.v:5815.36-5815.89"
+ cell $and $and$ls180.v:5815$1161
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank1_sel
connect \B \builder_interface1_bank_bus_we
- connect \Y $and$ls180.v:5819$1161_Y
+ connect \Y $and$ls180.v:5815$1161_Y
end
- attribute \src "ls180.v:5819.35-5819.139"
- cell $and $and$ls180.v:5819$1163
+ attribute \src "ls180.v:5815.35-5815.139"
+ cell $and $and$ls180.v:5815$1163
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5819$1161_Y
- connect \B $eq$ls180.v:5819$1162_Y
- connect \Y $and$ls180.v:5819$1163_Y
+ connect \A $and$ls180.v:5815$1161_Y
+ connect \B $eq$ls180.v:5815$1162_Y
+ connect \Y $and$ls180.v:5815$1163_Y
end
- attribute \src "ls180.v:5820.36-5820.92"
- cell $and $and$ls180.v:5820$1165
+ attribute \src "ls180.v:5816.36-5816.92"
+ cell $and $and$ls180.v:5816$1165
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank1_sel
- connect \B $not$ls180.v:5820$1164_Y
- connect \Y $and$ls180.v:5820$1165_Y
+ connect \B $not$ls180.v:5816$1164_Y
+ connect \Y $and$ls180.v:5816$1165_Y
end
- attribute \src "ls180.v:5820.35-5820.142"
- cell $and $and$ls180.v:5820$1167
+ attribute \src "ls180.v:5816.35-5816.142"
+ cell $and $and$ls180.v:5816$1167
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5820$1165_Y
- connect \B $eq$ls180.v:5820$1166_Y
- connect \Y $and$ls180.v:5820$1167_Y
+ connect \A $and$ls180.v:5816$1165_Y
+ connect \B $eq$ls180.v:5816$1166_Y
+ connect \Y $and$ls180.v:5816$1167_Y
end
- attribute \src "ls180.v:5822.36-5822.89"
- cell $and $and$ls180.v:5822$1168
+ attribute \src "ls180.v:5818.36-5818.89"
+ cell $and $and$ls180.v:5818$1168
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank1_sel
connect \B \builder_interface1_bank_bus_we
- connect \Y $and$ls180.v:5822$1168_Y
+ connect \Y $and$ls180.v:5818$1168_Y
end
- attribute \src "ls180.v:5822.35-5822.139"
- cell $and $and$ls180.v:5822$1170
+ attribute \src "ls180.v:5818.35-5818.139"
+ cell $and $and$ls180.v:5818$1170
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5822$1168_Y
- connect \B $eq$ls180.v:5822$1169_Y
- connect \Y $and$ls180.v:5822$1170_Y
+ connect \A $and$ls180.v:5818$1168_Y
+ connect \B $eq$ls180.v:5818$1169_Y
+ connect \Y $and$ls180.v:5818$1170_Y
end
- attribute \src "ls180.v:5823.36-5823.92"
- cell $and $and$ls180.v:5823$1172
+ attribute \src "ls180.v:5819.36-5819.92"
+ cell $and $and$ls180.v:5819$1172
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank1_sel
- connect \B $not$ls180.v:5823$1171_Y
- connect \Y $and$ls180.v:5823$1172_Y
+ connect \B $not$ls180.v:5819$1171_Y
+ connect \Y $and$ls180.v:5819$1172_Y
end
- attribute \src "ls180.v:5823.35-5823.142"
- cell $and $and$ls180.v:5823$1174
+ attribute \src "ls180.v:5819.35-5819.142"
+ cell $and $and$ls180.v:5819$1174
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5823$1172_Y
- connect \B $eq$ls180.v:5823$1173_Y
- connect \Y $and$ls180.v:5823$1174_Y
+ connect \A $and$ls180.v:5819$1172_Y
+ connect \B $eq$ls180.v:5819$1173_Y
+ connect \Y $and$ls180.v:5819$1174_Y
end
- attribute \src "ls180.v:5825.37-5825.90"
- cell $and $and$ls180.v:5825$1175
+ attribute \src "ls180.v:5821.37-5821.90"
+ cell $and $and$ls180.v:5821$1175
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank1_sel
connect \B \builder_interface1_bank_bus_we
- connect \Y $and$ls180.v:5825$1175_Y
+ connect \Y $and$ls180.v:5821$1175_Y
end
- attribute \src "ls180.v:5825.36-5825.140"
- cell $and $and$ls180.v:5825$1177
+ attribute \src "ls180.v:5821.36-5821.140"
+ cell $and $and$ls180.v:5821$1177
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5825$1175_Y
- connect \B $eq$ls180.v:5825$1176_Y
- connect \Y $and$ls180.v:5825$1177_Y
+ connect \A $and$ls180.v:5821$1175_Y
+ connect \B $eq$ls180.v:5821$1176_Y
+ connect \Y $and$ls180.v:5821$1177_Y
end
- attribute \src "ls180.v:5826.37-5826.93"
- cell $and $and$ls180.v:5826$1179
+ attribute \src "ls180.v:5822.37-5822.93"
+ cell $and $and$ls180.v:5822$1179
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank1_sel
- connect \B $not$ls180.v:5826$1178_Y
- connect \Y $and$ls180.v:5826$1179_Y
+ connect \B $not$ls180.v:5822$1178_Y
+ connect \Y $and$ls180.v:5822$1179_Y
end
- attribute \src "ls180.v:5826.36-5826.143"
- cell $and $and$ls180.v:5826$1181
+ attribute \src "ls180.v:5822.36-5822.143"
+ cell $and $and$ls180.v:5822$1181
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5826$1179_Y
- connect \B $eq$ls180.v:5826$1180_Y
- connect \Y $and$ls180.v:5826$1181_Y
+ connect \A $and$ls180.v:5822$1179_Y
+ connect \B $eq$ls180.v:5822$1180_Y
+ connect \Y $and$ls180.v:5822$1181_Y
end
- attribute \src "ls180.v:5828.37-5828.90"
- cell $and $and$ls180.v:5828$1182
+ attribute \src "ls180.v:5824.37-5824.90"
+ cell $and $and$ls180.v:5824$1182
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank1_sel
connect \B \builder_interface1_bank_bus_we
- connect \Y $and$ls180.v:5828$1182_Y
+ connect \Y $and$ls180.v:5824$1182_Y
end
- attribute \src "ls180.v:5828.36-5828.140"
- cell $and $and$ls180.v:5828$1184
+ attribute \src "ls180.v:5824.36-5824.140"
+ cell $and $and$ls180.v:5824$1184
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5828$1182_Y
- connect \B $eq$ls180.v:5828$1183_Y
- connect \Y $and$ls180.v:5828$1184_Y
+ connect \A $and$ls180.v:5824$1182_Y
+ connect \B $eq$ls180.v:5824$1183_Y
+ connect \Y $and$ls180.v:5824$1184_Y
end
- attribute \src "ls180.v:5829.37-5829.93"
- cell $and $and$ls180.v:5829$1186
+ attribute \src "ls180.v:5825.37-5825.93"
+ cell $and $and$ls180.v:5825$1186
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank1_sel
- connect \B $not$ls180.v:5829$1185_Y
- connect \Y $and$ls180.v:5829$1186_Y
+ connect \B $not$ls180.v:5825$1185_Y
+ connect \Y $and$ls180.v:5825$1186_Y
end
- attribute \src "ls180.v:5829.36-5829.143"
- cell $and $and$ls180.v:5829$1188
+ attribute \src "ls180.v:5825.36-5825.143"
+ cell $and $and$ls180.v:5825$1188
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5829$1186_Y
- connect \B $eq$ls180.v:5829$1187_Y
- connect \Y $and$ls180.v:5829$1188_Y
+ connect \A $and$ls180.v:5825$1186_Y
+ connect \B $eq$ls180.v:5825$1187_Y
+ connect \Y $and$ls180.v:5825$1188_Y
end
- attribute \src "ls180.v:5839.35-5839.88"
- cell $and $and$ls180.v:5839$1190
+ attribute \src "ls180.v:5835.35-5835.88"
+ cell $and $and$ls180.v:5835$1190
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank2_sel
connect \B \builder_interface2_bank_bus_we
- connect \Y $and$ls180.v:5839$1190_Y
+ connect \Y $and$ls180.v:5835$1190_Y
end
- attribute \src "ls180.v:5839.34-5839.136"
- cell $and $and$ls180.v:5839$1192
+ attribute \src "ls180.v:5835.34-5835.136"
+ cell $and $and$ls180.v:5835$1192
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5839$1190_Y
- connect \B $eq$ls180.v:5839$1191_Y
- connect \Y $and$ls180.v:5839$1192_Y
+ connect \A $and$ls180.v:5835$1190_Y
+ connect \B $eq$ls180.v:5835$1191_Y
+ connect \Y $and$ls180.v:5835$1192_Y
end
- attribute \src "ls180.v:5840.35-5840.91"
- cell $and $and$ls180.v:5840$1194
+ attribute \src "ls180.v:5836.35-5836.91"
+ cell $and $and$ls180.v:5836$1194
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank2_sel
- connect \B $not$ls180.v:5840$1193_Y
- connect \Y $and$ls180.v:5840$1194_Y
+ connect \B $not$ls180.v:5836$1193_Y
+ connect \Y $and$ls180.v:5836$1194_Y
end
- attribute \src "ls180.v:5840.34-5840.139"
- cell $and $and$ls180.v:5840$1196
+ attribute \src "ls180.v:5836.34-5836.139"
+ cell $and $and$ls180.v:5836$1196
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5840$1194_Y
- connect \B $eq$ls180.v:5840$1195_Y
- connect \Y $and$ls180.v:5840$1196_Y
+ connect \A $and$ls180.v:5836$1194_Y
+ connect \B $eq$ls180.v:5836$1195_Y
+ connect \Y $and$ls180.v:5836$1196_Y
end
- attribute \src "ls180.v:5842.34-5842.87"
- cell $and $and$ls180.v:5842$1197
+ attribute \src "ls180.v:5838.34-5838.87"
+ cell $and $and$ls180.v:5838$1197
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank2_sel
connect \B \builder_interface2_bank_bus_we
- connect \Y $and$ls180.v:5842$1197_Y
+ connect \Y $and$ls180.v:5838$1197_Y
end
- attribute \src "ls180.v:5842.33-5842.135"
- cell $and $and$ls180.v:5842$1199
+ attribute \src "ls180.v:5838.33-5838.135"
+ cell $and $and$ls180.v:5838$1199
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5842$1197_Y
- connect \B $eq$ls180.v:5842$1198_Y
- connect \Y $and$ls180.v:5842$1199_Y
+ connect \A $and$ls180.v:5838$1197_Y
+ connect \B $eq$ls180.v:5838$1198_Y
+ connect \Y $and$ls180.v:5838$1199_Y
end
- attribute \src "ls180.v:5843.34-5843.90"
- cell $and $and$ls180.v:5843$1201
+ attribute \src "ls180.v:5839.34-5839.90"
+ cell $and $and$ls180.v:5839$1201
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank2_sel
- connect \B $not$ls180.v:5843$1200_Y
- connect \Y $and$ls180.v:5843$1201_Y
+ connect \B $not$ls180.v:5839$1200_Y
+ connect \Y $and$ls180.v:5839$1201_Y
end
- attribute \src "ls180.v:5843.33-5843.138"
- cell $and $and$ls180.v:5843$1203
+ attribute \src "ls180.v:5839.33-5839.138"
+ cell $and $and$ls180.v:5839$1203
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5843$1201_Y
- connect \B $eq$ls180.v:5843$1202_Y
- connect \Y $and$ls180.v:5843$1203_Y
+ connect \A $and$ls180.v:5839$1201_Y
+ connect \B $eq$ls180.v:5839$1202_Y
+ connect \Y $and$ls180.v:5839$1203_Y
end
- attribute \src "ls180.v:5853.40-5853.93"
- cell $and $and$ls180.v:5853$1205
+ attribute \src "ls180.v:5849.40-5849.93"
+ cell $and $and$ls180.v:5849$1205
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank3_sel
connect \B \builder_interface3_bank_bus_we
- connect \Y $and$ls180.v:5853$1205_Y
+ connect \Y $and$ls180.v:5849$1205_Y
end
- attribute \src "ls180.v:5853.39-5853.143"
- cell $and $and$ls180.v:5853$1207
+ attribute \src "ls180.v:5849.39-5849.143"
+ cell $and $and$ls180.v:5849$1207
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5853$1205_Y
- connect \B $eq$ls180.v:5853$1206_Y
- connect \Y $and$ls180.v:5853$1207_Y
+ connect \A $and$ls180.v:5849$1205_Y
+ connect \B $eq$ls180.v:5849$1206_Y
+ connect \Y $and$ls180.v:5849$1207_Y
end
- attribute \src "ls180.v:5854.40-5854.96"
- cell $and $and$ls180.v:5854$1209
+ attribute \src "ls180.v:5850.40-5850.96"
+ cell $and $and$ls180.v:5850$1209
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank3_sel
- connect \B $not$ls180.v:5854$1208_Y
- connect \Y $and$ls180.v:5854$1209_Y
+ connect \B $not$ls180.v:5850$1208_Y
+ connect \Y $and$ls180.v:5850$1209_Y
end
- attribute \src "ls180.v:5854.39-5854.146"
- cell $and $and$ls180.v:5854$1211
+ attribute \src "ls180.v:5850.39-5850.146"
+ cell $and $and$ls180.v:5850$1211
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5854$1209_Y
- connect \B $eq$ls180.v:5854$1210_Y
- connect \Y $and$ls180.v:5854$1211_Y
+ connect \A $and$ls180.v:5850$1209_Y
+ connect \B $eq$ls180.v:5850$1210_Y
+ connect \Y $and$ls180.v:5850$1211_Y
end
- attribute \src "ls180.v:5856.39-5856.92"
- cell $and $and$ls180.v:5856$1212
+ attribute \src "ls180.v:5852.39-5852.92"
+ cell $and $and$ls180.v:5852$1212
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank3_sel
connect \B \builder_interface3_bank_bus_we
- connect \Y $and$ls180.v:5856$1212_Y
+ connect \Y $and$ls180.v:5852$1212_Y
end
- attribute \src "ls180.v:5856.38-5856.142"
- cell $and $and$ls180.v:5856$1214
+ attribute \src "ls180.v:5852.38-5852.142"
+ cell $and $and$ls180.v:5852$1214
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5856$1212_Y
- connect \B $eq$ls180.v:5856$1213_Y
- connect \Y $and$ls180.v:5856$1214_Y
+ connect \A $and$ls180.v:5852$1212_Y
+ connect \B $eq$ls180.v:5852$1213_Y
+ connect \Y $and$ls180.v:5852$1214_Y
end
- attribute \src "ls180.v:5857.39-5857.95"
- cell $and $and$ls180.v:5857$1216
+ attribute \src "ls180.v:5853.39-5853.95"
+ cell $and $and$ls180.v:5853$1216
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank3_sel
- connect \B $not$ls180.v:5857$1215_Y
- connect \Y $and$ls180.v:5857$1216_Y
+ connect \B $not$ls180.v:5853$1215_Y
+ connect \Y $and$ls180.v:5853$1216_Y
end
- attribute \src "ls180.v:5857.38-5857.145"
- cell $and $and$ls180.v:5857$1218
+ attribute \src "ls180.v:5853.38-5853.145"
+ cell $and $and$ls180.v:5853$1218
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5857$1216_Y
- connect \B $eq$ls180.v:5857$1217_Y
- connect \Y $and$ls180.v:5857$1218_Y
+ connect \A $and$ls180.v:5853$1216_Y
+ connect \B $eq$ls180.v:5853$1217_Y
+ connect \Y $and$ls180.v:5853$1218_Y
end
- attribute \src "ls180.v:5859.39-5859.92"
- cell $and $and$ls180.v:5859$1219
+ attribute \src "ls180.v:5855.39-5855.92"
+ cell $and $and$ls180.v:5855$1219
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank3_sel
connect \B \builder_interface3_bank_bus_we
- connect \Y $and$ls180.v:5859$1219_Y
+ connect \Y $and$ls180.v:5855$1219_Y
end
- attribute \src "ls180.v:5859.38-5859.142"
- cell $and $and$ls180.v:5859$1221
+ attribute \src "ls180.v:5855.38-5855.142"
+ cell $and $and$ls180.v:5855$1221
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5859$1219_Y
- connect \B $eq$ls180.v:5859$1220_Y
- connect \Y $and$ls180.v:5859$1221_Y
+ connect \A $and$ls180.v:5855$1219_Y
+ connect \B $eq$ls180.v:5855$1220_Y
+ connect \Y $and$ls180.v:5855$1221_Y
end
- attribute \src "ls180.v:5860.39-5860.95"
- cell $and $and$ls180.v:5860$1223
+ attribute \src "ls180.v:5856.39-5856.95"
+ cell $and $and$ls180.v:5856$1223
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank3_sel
- connect \B $not$ls180.v:5860$1222_Y
- connect \Y $and$ls180.v:5860$1223_Y
+ connect \B $not$ls180.v:5856$1222_Y
+ connect \Y $and$ls180.v:5856$1223_Y
end
- attribute \src "ls180.v:5860.38-5860.145"
- cell $and $and$ls180.v:5860$1225
+ attribute \src "ls180.v:5856.38-5856.145"
+ cell $and $and$ls180.v:5856$1225
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5860$1223_Y
- connect \B $eq$ls180.v:5860$1224_Y
- connect \Y $and$ls180.v:5860$1225_Y
+ connect \A $and$ls180.v:5856$1223_Y
+ connect \B $eq$ls180.v:5856$1224_Y
+ connect \Y $and$ls180.v:5856$1225_Y
end
- attribute \src "ls180.v:5862.39-5862.92"
- cell $and $and$ls180.v:5862$1226
+ attribute \src "ls180.v:5858.39-5858.92"
+ cell $and $and$ls180.v:5858$1226
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank3_sel
connect \B \builder_interface3_bank_bus_we
- connect \Y $and$ls180.v:5862$1226_Y
+ connect \Y $and$ls180.v:5858$1226_Y
end
- attribute \src "ls180.v:5862.38-5862.142"
- cell $and $and$ls180.v:5862$1228
+ attribute \src "ls180.v:5858.38-5858.142"
+ cell $and $and$ls180.v:5858$1228
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5862$1226_Y
- connect \B $eq$ls180.v:5862$1227_Y
- connect \Y $and$ls180.v:5862$1228_Y
+ connect \A $and$ls180.v:5858$1226_Y
+ connect \B $eq$ls180.v:5858$1227_Y
+ connect \Y $and$ls180.v:5858$1228_Y
end
- attribute \src "ls180.v:5863.39-5863.95"
- cell $and $and$ls180.v:5863$1230
+ attribute \src "ls180.v:5859.39-5859.95"
+ cell $and $and$ls180.v:5859$1230
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank3_sel
- connect \B $not$ls180.v:5863$1229_Y
- connect \Y $and$ls180.v:5863$1230_Y
+ connect \B $not$ls180.v:5859$1229_Y
+ connect \Y $and$ls180.v:5859$1230_Y
end
- attribute \src "ls180.v:5863.38-5863.145"
- cell $and $and$ls180.v:5863$1232
+ attribute \src "ls180.v:5859.38-5859.145"
+ cell $and $and$ls180.v:5859$1232
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5863$1230_Y
- connect \B $eq$ls180.v:5863$1231_Y
- connect \Y $and$ls180.v:5863$1232_Y
+ connect \A $and$ls180.v:5859$1230_Y
+ connect \B $eq$ls180.v:5859$1231_Y
+ connect \Y $and$ls180.v:5859$1232_Y
end
- attribute \src "ls180.v:5865.39-5865.92"
- cell $and $and$ls180.v:5865$1233
+ attribute \src "ls180.v:5861.39-5861.92"
+ cell $and $and$ls180.v:5861$1233
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank3_sel
connect \B \builder_interface3_bank_bus_we
- connect \Y $and$ls180.v:5865$1233_Y
+ connect \Y $and$ls180.v:5861$1233_Y
end
- attribute \src "ls180.v:5865.38-5865.142"
- cell $and $and$ls180.v:5865$1235
+ attribute \src "ls180.v:5861.38-5861.142"
+ cell $and $and$ls180.v:5861$1235
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5865$1233_Y
- connect \B $eq$ls180.v:5865$1234_Y
- connect \Y $and$ls180.v:5865$1235_Y
+ connect \A $and$ls180.v:5861$1233_Y
+ connect \B $eq$ls180.v:5861$1234_Y
+ connect \Y $and$ls180.v:5861$1235_Y
end
- attribute \src "ls180.v:5866.39-5866.95"
- cell $and $and$ls180.v:5866$1237
+ attribute \src "ls180.v:5862.39-5862.95"
+ cell $and $and$ls180.v:5862$1237
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank3_sel
- connect \B $not$ls180.v:5866$1236_Y
- connect \Y $and$ls180.v:5866$1237_Y
+ connect \B $not$ls180.v:5862$1236_Y
+ connect \Y $and$ls180.v:5862$1237_Y
end
- attribute \src "ls180.v:5866.38-5866.145"
- cell $and $and$ls180.v:5866$1239
+ attribute \src "ls180.v:5862.38-5862.145"
+ cell $and $and$ls180.v:5862$1239
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5866$1237_Y
- connect \B $eq$ls180.v:5866$1238_Y
- connect \Y $and$ls180.v:5866$1239_Y
+ connect \A $and$ls180.v:5862$1237_Y
+ connect \B $eq$ls180.v:5862$1238_Y
+ connect \Y $and$ls180.v:5862$1239_Y
end
- attribute \src "ls180.v:5868.40-5868.93"
- cell $and $and$ls180.v:5868$1240
+ attribute \src "ls180.v:5864.40-5864.93"
+ cell $and $and$ls180.v:5864$1240
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank3_sel
connect \B \builder_interface3_bank_bus_we
- connect \Y $and$ls180.v:5868$1240_Y
+ connect \Y $and$ls180.v:5864$1240_Y
end
- attribute \src "ls180.v:5868.39-5868.143"
- cell $and $and$ls180.v:5868$1242
+ attribute \src "ls180.v:5864.39-5864.143"
+ cell $and $and$ls180.v:5864$1242
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5868$1240_Y
- connect \B $eq$ls180.v:5868$1241_Y
- connect \Y $and$ls180.v:5868$1242_Y
+ connect \A $and$ls180.v:5864$1240_Y
+ connect \B $eq$ls180.v:5864$1241_Y
+ connect \Y $and$ls180.v:5864$1242_Y
end
- attribute \src "ls180.v:5869.40-5869.96"
- cell $and $and$ls180.v:5869$1244
+ attribute \src "ls180.v:5865.40-5865.96"
+ cell $and $and$ls180.v:5865$1244
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank3_sel
- connect \B $not$ls180.v:5869$1243_Y
- connect \Y $and$ls180.v:5869$1244_Y
+ connect \B $not$ls180.v:5865$1243_Y
+ connect \Y $and$ls180.v:5865$1244_Y
end
- attribute \src "ls180.v:5869.39-5869.146"
- cell $and $and$ls180.v:5869$1246
+ attribute \src "ls180.v:5865.39-5865.146"
+ cell $and $and$ls180.v:5865$1246
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5869$1244_Y
- connect \B $eq$ls180.v:5869$1245_Y
- connect \Y $and$ls180.v:5869$1246_Y
+ connect \A $and$ls180.v:5865$1244_Y
+ connect \B $eq$ls180.v:5865$1245_Y
+ connect \Y $and$ls180.v:5865$1246_Y
end
- attribute \src "ls180.v:5871.40-5871.93"
- cell $and $and$ls180.v:5871$1247
+ attribute \src "ls180.v:5867.40-5867.93"
+ cell $and $and$ls180.v:5867$1247
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank3_sel
connect \B \builder_interface3_bank_bus_we
- connect \Y $and$ls180.v:5871$1247_Y
+ connect \Y $and$ls180.v:5867$1247_Y
end
- attribute \src "ls180.v:5871.39-5871.143"
- cell $and $and$ls180.v:5871$1249
+ attribute \src "ls180.v:5867.39-5867.143"
+ cell $and $and$ls180.v:5867$1249
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5871$1247_Y
- connect \B $eq$ls180.v:5871$1248_Y
- connect \Y $and$ls180.v:5871$1249_Y
+ connect \A $and$ls180.v:5867$1247_Y
+ connect \B $eq$ls180.v:5867$1248_Y
+ connect \Y $and$ls180.v:5867$1249_Y
end
- attribute \src "ls180.v:5872.40-5872.96"
- cell $and $and$ls180.v:5872$1251
+ attribute \src "ls180.v:5868.40-5868.96"
+ cell $and $and$ls180.v:5868$1251
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank3_sel
- connect \B $not$ls180.v:5872$1250_Y
- connect \Y $and$ls180.v:5872$1251_Y
+ connect \B $not$ls180.v:5868$1250_Y
+ connect \Y $and$ls180.v:5868$1251_Y
end
- attribute \src "ls180.v:5872.39-5872.146"
- cell $and $and$ls180.v:5872$1253
+ attribute \src "ls180.v:5868.39-5868.146"
+ cell $and $and$ls180.v:5868$1253
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5872$1251_Y
- connect \B $eq$ls180.v:5872$1252_Y
- connect \Y $and$ls180.v:5872$1253_Y
+ connect \A $and$ls180.v:5868$1251_Y
+ connect \B $eq$ls180.v:5868$1252_Y
+ connect \Y $and$ls180.v:5868$1253_Y
end
- attribute \src "ls180.v:5874.40-5874.93"
- cell $and $and$ls180.v:5874$1254
+ attribute \src "ls180.v:5870.40-5870.93"
+ cell $and $and$ls180.v:5870$1254
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank3_sel
connect \B \builder_interface3_bank_bus_we
- connect \Y $and$ls180.v:5874$1254_Y
+ connect \Y $and$ls180.v:5870$1254_Y
end
- attribute \src "ls180.v:5874.39-5874.143"
- cell $and $and$ls180.v:5874$1256
+ attribute \src "ls180.v:5870.39-5870.143"
+ cell $and $and$ls180.v:5870$1256
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5874$1254_Y
- connect \B $eq$ls180.v:5874$1255_Y
- connect \Y $and$ls180.v:5874$1256_Y
+ connect \A $and$ls180.v:5870$1254_Y
+ connect \B $eq$ls180.v:5870$1255_Y
+ connect \Y $and$ls180.v:5870$1256_Y
end
- attribute \src "ls180.v:5875.40-5875.96"
- cell $and $and$ls180.v:5875$1258
+ attribute \src "ls180.v:5871.40-5871.96"
+ cell $and $and$ls180.v:5871$1258
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank3_sel
- connect \B $not$ls180.v:5875$1257_Y
- connect \Y $and$ls180.v:5875$1258_Y
+ connect \B $not$ls180.v:5871$1257_Y
+ connect \Y $and$ls180.v:5871$1258_Y
end
- attribute \src "ls180.v:5875.39-5875.146"
- cell $and $and$ls180.v:5875$1260
+ attribute \src "ls180.v:5871.39-5871.146"
+ cell $and $and$ls180.v:5871$1260
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5875$1258_Y
- connect \B $eq$ls180.v:5875$1259_Y
- connect \Y $and$ls180.v:5875$1260_Y
+ connect \A $and$ls180.v:5871$1258_Y
+ connect \B $eq$ls180.v:5871$1259_Y
+ connect \Y $and$ls180.v:5871$1260_Y
end
- attribute \src "ls180.v:5877.40-5877.93"
- cell $and $and$ls180.v:5877$1261
+ attribute \src "ls180.v:5873.40-5873.93"
+ cell $and $and$ls180.v:5873$1261
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank3_sel
connect \B \builder_interface3_bank_bus_we
- connect \Y $and$ls180.v:5877$1261_Y
+ connect \Y $and$ls180.v:5873$1261_Y
end
- attribute \src "ls180.v:5877.39-5877.143"
- cell $and $and$ls180.v:5877$1263
+ attribute \src "ls180.v:5873.39-5873.143"
+ cell $and $and$ls180.v:5873$1263
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5877$1261_Y
- connect \B $eq$ls180.v:5877$1262_Y
- connect \Y $and$ls180.v:5877$1263_Y
+ connect \A $and$ls180.v:5873$1261_Y
+ connect \B $eq$ls180.v:5873$1262_Y
+ connect \Y $and$ls180.v:5873$1263_Y
end
- attribute \src "ls180.v:5878.40-5878.96"
- cell $and $and$ls180.v:5878$1265
+ attribute \src "ls180.v:5874.40-5874.96"
+ cell $and $and$ls180.v:5874$1265
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank3_sel
- connect \B $not$ls180.v:5878$1264_Y
- connect \Y $and$ls180.v:5878$1265_Y
+ connect \B $not$ls180.v:5874$1264_Y
+ connect \Y $and$ls180.v:5874$1265_Y
end
- attribute \src "ls180.v:5878.39-5878.146"
- cell $and $and$ls180.v:5878$1267
+ attribute \src "ls180.v:5874.39-5874.146"
+ cell $and $and$ls180.v:5874$1267
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5878$1265_Y
- connect \B $eq$ls180.v:5878$1266_Y
- connect \Y $and$ls180.v:5878$1267_Y
+ connect \A $and$ls180.v:5874$1265_Y
+ connect \B $eq$ls180.v:5874$1266_Y
+ connect \Y $and$ls180.v:5874$1267_Y
end
- attribute \src "ls180.v:5890.40-5890.93"
- cell $and $and$ls180.v:5890$1269
+ attribute \src "ls180.v:5886.40-5886.93"
+ cell $and $and$ls180.v:5886$1269
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank4_sel
connect \B \builder_interface4_bank_bus_we
- connect \Y $and$ls180.v:5890$1269_Y
+ connect \Y $and$ls180.v:5886$1269_Y
end
- attribute \src "ls180.v:5890.39-5890.143"
- cell $and $and$ls180.v:5890$1271
+ attribute \src "ls180.v:5886.39-5886.143"
+ cell $and $and$ls180.v:5886$1271
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5890$1269_Y
- connect \B $eq$ls180.v:5890$1270_Y
- connect \Y $and$ls180.v:5890$1271_Y
+ connect \A $and$ls180.v:5886$1269_Y
+ connect \B $eq$ls180.v:5886$1270_Y
+ connect \Y $and$ls180.v:5886$1271_Y
end
- attribute \src "ls180.v:5891.40-5891.96"
- cell $and $and$ls180.v:5891$1273
+ attribute \src "ls180.v:5887.40-5887.96"
+ cell $and $and$ls180.v:5887$1273
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank4_sel
- connect \B $not$ls180.v:5891$1272_Y
- connect \Y $and$ls180.v:5891$1273_Y
+ connect \B $not$ls180.v:5887$1272_Y
+ connect \Y $and$ls180.v:5887$1273_Y
end
- attribute \src "ls180.v:5891.39-5891.146"
- cell $and $and$ls180.v:5891$1275
+ attribute \src "ls180.v:5887.39-5887.146"
+ cell $and $and$ls180.v:5887$1275
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5891$1273_Y
- connect \B $eq$ls180.v:5891$1274_Y
- connect \Y $and$ls180.v:5891$1275_Y
+ connect \A $and$ls180.v:5887$1273_Y
+ connect \B $eq$ls180.v:5887$1274_Y
+ connect \Y $and$ls180.v:5887$1275_Y
end
- attribute \src "ls180.v:5893.39-5893.92"
- cell $and $and$ls180.v:5893$1276
+ attribute \src "ls180.v:5889.39-5889.92"
+ cell $and $and$ls180.v:5889$1276
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank4_sel
connect \B \builder_interface4_bank_bus_we
- connect \Y $and$ls180.v:5893$1276_Y
+ connect \Y $and$ls180.v:5889$1276_Y
end
- attribute \src "ls180.v:5893.38-5893.142"
- cell $and $and$ls180.v:5893$1278
+ attribute \src "ls180.v:5889.38-5889.142"
+ cell $and $and$ls180.v:5889$1278
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5893$1276_Y
- connect \B $eq$ls180.v:5893$1277_Y
- connect \Y $and$ls180.v:5893$1278_Y
+ connect \A $and$ls180.v:5889$1276_Y
+ connect \B $eq$ls180.v:5889$1277_Y
+ connect \Y $and$ls180.v:5889$1278_Y
end
- attribute \src "ls180.v:5894.39-5894.95"
- cell $and $and$ls180.v:5894$1280
+ attribute \src "ls180.v:5890.39-5890.95"
+ cell $and $and$ls180.v:5890$1280
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank4_sel
- connect \B $not$ls180.v:5894$1279_Y
- connect \Y $and$ls180.v:5894$1280_Y
+ connect \B $not$ls180.v:5890$1279_Y
+ connect \Y $and$ls180.v:5890$1280_Y
end
- attribute \src "ls180.v:5894.38-5894.145"
- cell $and $and$ls180.v:5894$1282
+ attribute \src "ls180.v:5890.38-5890.145"
+ cell $and $and$ls180.v:5890$1282
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5894$1280_Y
- connect \B $eq$ls180.v:5894$1281_Y
- connect \Y $and$ls180.v:5894$1282_Y
+ connect \A $and$ls180.v:5890$1280_Y
+ connect \B $eq$ls180.v:5890$1281_Y
+ connect \Y $and$ls180.v:5890$1282_Y
end
- attribute \src "ls180.v:5896.39-5896.92"
- cell $and $and$ls180.v:5896$1283
+ attribute \src "ls180.v:5892.39-5892.92"
+ cell $and $and$ls180.v:5892$1283
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank4_sel
connect \B \builder_interface4_bank_bus_we
- connect \Y $and$ls180.v:5896$1283_Y
+ connect \Y $and$ls180.v:5892$1283_Y
end
- attribute \src "ls180.v:5896.38-5896.142"
- cell $and $and$ls180.v:5896$1285
+ attribute \src "ls180.v:5892.38-5892.142"
+ cell $and $and$ls180.v:5892$1285
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5896$1283_Y
- connect \B $eq$ls180.v:5896$1284_Y
- connect \Y $and$ls180.v:5896$1285_Y
+ connect \A $and$ls180.v:5892$1283_Y
+ connect \B $eq$ls180.v:5892$1284_Y
+ connect \Y $and$ls180.v:5892$1285_Y
end
- attribute \src "ls180.v:5897.39-5897.95"
- cell $and $and$ls180.v:5897$1287
+ attribute \src "ls180.v:5893.39-5893.95"
+ cell $and $and$ls180.v:5893$1287
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank4_sel
- connect \B $not$ls180.v:5897$1286_Y
- connect \Y $and$ls180.v:5897$1287_Y
+ connect \B $not$ls180.v:5893$1286_Y
+ connect \Y $and$ls180.v:5893$1287_Y
end
- attribute \src "ls180.v:5897.38-5897.145"
- cell $and $and$ls180.v:5897$1289
+ attribute \src "ls180.v:5893.38-5893.145"
+ cell $and $and$ls180.v:5893$1289
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5897$1287_Y
- connect \B $eq$ls180.v:5897$1288_Y
- connect \Y $and$ls180.v:5897$1289_Y
+ connect \A $and$ls180.v:5893$1287_Y
+ connect \B $eq$ls180.v:5893$1288_Y
+ connect \Y $and$ls180.v:5893$1289_Y
end
- attribute \src "ls180.v:5899.39-5899.92"
- cell $and $and$ls180.v:5899$1290
+ attribute \src "ls180.v:5895.39-5895.92"
+ cell $and $and$ls180.v:5895$1290
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank4_sel
connect \B \builder_interface4_bank_bus_we
- connect \Y $and$ls180.v:5899$1290_Y
+ connect \Y $and$ls180.v:5895$1290_Y
end
- attribute \src "ls180.v:5899.38-5899.142"
- cell $and $and$ls180.v:5899$1292
+ attribute \src "ls180.v:5895.38-5895.142"
+ cell $and $and$ls180.v:5895$1292
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5899$1290_Y
- connect \B $eq$ls180.v:5899$1291_Y
- connect \Y $and$ls180.v:5899$1292_Y
+ connect \A $and$ls180.v:5895$1290_Y
+ connect \B $eq$ls180.v:5895$1291_Y
+ connect \Y $and$ls180.v:5895$1292_Y
end
- attribute \src "ls180.v:5900.39-5900.95"
- cell $and $and$ls180.v:5900$1294
+ attribute \src "ls180.v:5896.39-5896.95"
+ cell $and $and$ls180.v:5896$1294
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank4_sel
- connect \B $not$ls180.v:5900$1293_Y
- connect \Y $and$ls180.v:5900$1294_Y
+ connect \B $not$ls180.v:5896$1293_Y
+ connect \Y $and$ls180.v:5896$1294_Y
end
- attribute \src "ls180.v:5900.38-5900.145"
- cell $and $and$ls180.v:5900$1296
+ attribute \src "ls180.v:5896.38-5896.145"
+ cell $and $and$ls180.v:5896$1296
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5900$1294_Y
- connect \B $eq$ls180.v:5900$1295_Y
- connect \Y $and$ls180.v:5900$1296_Y
+ connect \A $and$ls180.v:5896$1294_Y
+ connect \B $eq$ls180.v:5896$1295_Y
+ connect \Y $and$ls180.v:5896$1296_Y
end
- attribute \src "ls180.v:5902.39-5902.92"
- cell $and $and$ls180.v:5902$1297
+ attribute \src "ls180.v:5898.39-5898.92"
+ cell $and $and$ls180.v:5898$1297
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank4_sel
connect \B \builder_interface4_bank_bus_we
- connect \Y $and$ls180.v:5902$1297_Y
+ connect \Y $and$ls180.v:5898$1297_Y
end
- attribute \src "ls180.v:5902.38-5902.142"
- cell $and $and$ls180.v:5902$1299
+ attribute \src "ls180.v:5898.38-5898.142"
+ cell $and $and$ls180.v:5898$1299
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5902$1297_Y
- connect \B $eq$ls180.v:5902$1298_Y
- connect \Y $and$ls180.v:5902$1299_Y
+ connect \A $and$ls180.v:5898$1297_Y
+ connect \B $eq$ls180.v:5898$1298_Y
+ connect \Y $and$ls180.v:5898$1299_Y
end
- attribute \src "ls180.v:5903.39-5903.95"
- cell $and $and$ls180.v:5903$1301
+ attribute \src "ls180.v:5899.39-5899.95"
+ cell $and $and$ls180.v:5899$1301
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank4_sel
- connect \B $not$ls180.v:5903$1300_Y
- connect \Y $and$ls180.v:5903$1301_Y
+ connect \B $not$ls180.v:5899$1300_Y
+ connect \Y $and$ls180.v:5899$1301_Y
end
- attribute \src "ls180.v:5903.38-5903.145"
- cell $and $and$ls180.v:5903$1303
+ attribute \src "ls180.v:5899.38-5899.145"
+ cell $and $and$ls180.v:5899$1303
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5903$1301_Y
- connect \B $eq$ls180.v:5903$1302_Y
- connect \Y $and$ls180.v:5903$1303_Y
+ connect \A $and$ls180.v:5899$1301_Y
+ connect \B $eq$ls180.v:5899$1302_Y
+ connect \Y $and$ls180.v:5899$1303_Y
end
- attribute \src "ls180.v:5905.40-5905.93"
- cell $and $and$ls180.v:5905$1304
+ attribute \src "ls180.v:5901.40-5901.93"
+ cell $and $and$ls180.v:5901$1304
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank4_sel
connect \B \builder_interface4_bank_bus_we
- connect \Y $and$ls180.v:5905$1304_Y
+ connect \Y $and$ls180.v:5901$1304_Y
end
- attribute \src "ls180.v:5905.39-5905.143"
- cell $and $and$ls180.v:5905$1306
+ attribute \src "ls180.v:5901.39-5901.143"
+ cell $and $and$ls180.v:5901$1306
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5905$1304_Y
- connect \B $eq$ls180.v:5905$1305_Y
- connect \Y $and$ls180.v:5905$1306_Y
+ connect \A $and$ls180.v:5901$1304_Y
+ connect \B $eq$ls180.v:5901$1305_Y
+ connect \Y $and$ls180.v:5901$1306_Y
end
- attribute \src "ls180.v:5906.40-5906.96"
- cell $and $and$ls180.v:5906$1308
+ attribute \src "ls180.v:5902.40-5902.96"
+ cell $and $and$ls180.v:5902$1308
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank4_sel
- connect \B $not$ls180.v:5906$1307_Y
- connect \Y $and$ls180.v:5906$1308_Y
+ connect \B $not$ls180.v:5902$1307_Y
+ connect \Y $and$ls180.v:5902$1308_Y
end
- attribute \src "ls180.v:5906.39-5906.146"
- cell $and $and$ls180.v:5906$1310
+ attribute \src "ls180.v:5902.39-5902.146"
+ cell $and $and$ls180.v:5902$1310
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5906$1308_Y
- connect \B $eq$ls180.v:5906$1309_Y
- connect \Y $and$ls180.v:5906$1310_Y
+ connect \A $and$ls180.v:5902$1308_Y
+ connect \B $eq$ls180.v:5902$1309_Y
+ connect \Y $and$ls180.v:5902$1310_Y
end
- attribute \src "ls180.v:5908.40-5908.93"
- cell $and $and$ls180.v:5908$1311
+ attribute \src "ls180.v:5904.40-5904.93"
+ cell $and $and$ls180.v:5904$1311
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank4_sel
connect \B \builder_interface4_bank_bus_we
- connect \Y $and$ls180.v:5908$1311_Y
+ connect \Y $and$ls180.v:5904$1311_Y
end
- attribute \src "ls180.v:5908.39-5908.143"
- cell $and $and$ls180.v:5908$1313
+ attribute \src "ls180.v:5904.39-5904.143"
+ cell $and $and$ls180.v:5904$1313
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5908$1311_Y
- connect \B $eq$ls180.v:5908$1312_Y
- connect \Y $and$ls180.v:5908$1313_Y
+ connect \A $and$ls180.v:5904$1311_Y
+ connect \B $eq$ls180.v:5904$1312_Y
+ connect \Y $and$ls180.v:5904$1313_Y
end
- attribute \src "ls180.v:5909.40-5909.96"
- cell $and $and$ls180.v:5909$1315
+ attribute \src "ls180.v:5905.40-5905.96"
+ cell $and $and$ls180.v:5905$1315
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank4_sel
- connect \B $not$ls180.v:5909$1314_Y
- connect \Y $and$ls180.v:5909$1315_Y
+ connect \B $not$ls180.v:5905$1314_Y
+ connect \Y $and$ls180.v:5905$1315_Y
end
- attribute \src "ls180.v:5909.39-5909.146"
- cell $and $and$ls180.v:5909$1317
+ attribute \src "ls180.v:5905.39-5905.146"
+ cell $and $and$ls180.v:5905$1317
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5909$1315_Y
- connect \B $eq$ls180.v:5909$1316_Y
- connect \Y $and$ls180.v:5909$1317_Y
+ connect \A $and$ls180.v:5905$1315_Y
+ connect \B $eq$ls180.v:5905$1316_Y
+ connect \Y $and$ls180.v:5905$1317_Y
end
- attribute \src "ls180.v:5911.40-5911.93"
- cell $and $and$ls180.v:5911$1318
+ attribute \src "ls180.v:5907.40-5907.93"
+ cell $and $and$ls180.v:5907$1318
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank4_sel
connect \B \builder_interface4_bank_bus_we
- connect \Y $and$ls180.v:5911$1318_Y
+ connect \Y $and$ls180.v:5907$1318_Y
end
- attribute \src "ls180.v:5911.39-5911.143"
- cell $and $and$ls180.v:5911$1320
+ attribute \src "ls180.v:5907.39-5907.143"
+ cell $and $and$ls180.v:5907$1320
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5911$1318_Y
- connect \B $eq$ls180.v:5911$1319_Y
- connect \Y $and$ls180.v:5911$1320_Y
+ connect \A $and$ls180.v:5907$1318_Y
+ connect \B $eq$ls180.v:5907$1319_Y
+ connect \Y $and$ls180.v:5907$1320_Y
end
- attribute \src "ls180.v:5912.40-5912.96"
- cell $and $and$ls180.v:5912$1322
+ attribute \src "ls180.v:5908.40-5908.96"
+ cell $and $and$ls180.v:5908$1322
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank4_sel
- connect \B $not$ls180.v:5912$1321_Y
- connect \Y $and$ls180.v:5912$1322_Y
+ connect \B $not$ls180.v:5908$1321_Y
+ connect \Y $and$ls180.v:5908$1322_Y
end
- attribute \src "ls180.v:5912.39-5912.146"
- cell $and $and$ls180.v:5912$1324
+ attribute \src "ls180.v:5908.39-5908.146"
+ cell $and $and$ls180.v:5908$1324
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5912$1322_Y
- connect \B $eq$ls180.v:5912$1323_Y
- connect \Y $and$ls180.v:5912$1324_Y
+ connect \A $and$ls180.v:5908$1322_Y
+ connect \B $eq$ls180.v:5908$1323_Y
+ connect \Y $and$ls180.v:5908$1324_Y
end
- attribute \src "ls180.v:5914.40-5914.93"
- cell $and $and$ls180.v:5914$1325
+ attribute \src "ls180.v:5910.40-5910.93"
+ cell $and $and$ls180.v:5910$1325
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank4_sel
connect \B \builder_interface4_bank_bus_we
- connect \Y $and$ls180.v:5914$1325_Y
+ connect \Y $and$ls180.v:5910$1325_Y
end
- attribute \src "ls180.v:5914.39-5914.143"
- cell $and $and$ls180.v:5914$1327
+ attribute \src "ls180.v:5910.39-5910.143"
+ cell $and $and$ls180.v:5910$1327
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5914$1325_Y
- connect \B $eq$ls180.v:5914$1326_Y
- connect \Y $and$ls180.v:5914$1327_Y
+ connect \A $and$ls180.v:5910$1325_Y
+ connect \B $eq$ls180.v:5910$1326_Y
+ connect \Y $and$ls180.v:5910$1327_Y
end
- attribute \src "ls180.v:5915.40-5915.96"
- cell $and $and$ls180.v:5915$1329
+ attribute \src "ls180.v:5911.40-5911.96"
+ cell $and $and$ls180.v:5911$1329
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank4_sel
- connect \B $not$ls180.v:5915$1328_Y
- connect \Y $and$ls180.v:5915$1329_Y
+ connect \B $not$ls180.v:5911$1328_Y
+ connect \Y $and$ls180.v:5911$1329_Y
end
- attribute \src "ls180.v:5915.39-5915.146"
- cell $and $and$ls180.v:5915$1331
+ attribute \src "ls180.v:5911.39-5911.146"
+ cell $and $and$ls180.v:5911$1331
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5915$1329_Y
- connect \B $eq$ls180.v:5915$1330_Y
- connect \Y $and$ls180.v:5915$1331_Y
+ connect \A $and$ls180.v:5911$1329_Y
+ connect \B $eq$ls180.v:5911$1330_Y
+ connect \Y $and$ls180.v:5911$1331_Y
end
- attribute \src "ls180.v:5927.42-5927.95"
- cell $and $and$ls180.v:5927$1333
+ attribute \src "ls180.v:5923.42-5923.95"
+ cell $and $and$ls180.v:5923$1333
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank5_sel
connect \B \builder_interface5_bank_bus_we
- connect \Y $and$ls180.v:5927$1333_Y
+ connect \Y $and$ls180.v:5923$1333_Y
end
- attribute \src "ls180.v:5927.41-5927.145"
- cell $and $and$ls180.v:5927$1335
+ attribute \src "ls180.v:5923.41-5923.145"
+ cell $and $and$ls180.v:5923$1335
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5927$1333_Y
- connect \B $eq$ls180.v:5927$1334_Y
- connect \Y $and$ls180.v:5927$1335_Y
+ connect \A $and$ls180.v:5923$1333_Y
+ connect \B $eq$ls180.v:5923$1334_Y
+ connect \Y $and$ls180.v:5923$1335_Y
end
- attribute \src "ls180.v:5928.42-5928.98"
- cell $and $and$ls180.v:5928$1337
+ attribute \src "ls180.v:5924.42-5924.98"
+ cell $and $and$ls180.v:5924$1337
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank5_sel
- connect \B $not$ls180.v:5928$1336_Y
- connect \Y $and$ls180.v:5928$1337_Y
+ connect \B $not$ls180.v:5924$1336_Y
+ connect \Y $and$ls180.v:5924$1337_Y
end
- attribute \src "ls180.v:5928.41-5928.148"
- cell $and $and$ls180.v:5928$1339
+ attribute \src "ls180.v:5924.41-5924.148"
+ cell $and $and$ls180.v:5924$1339
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5928$1337_Y
- connect \B $eq$ls180.v:5928$1338_Y
- connect \Y $and$ls180.v:5928$1339_Y
+ connect \A $and$ls180.v:5924$1337_Y
+ connect \B $eq$ls180.v:5924$1338_Y
+ connect \Y $and$ls180.v:5924$1339_Y
end
- attribute \src "ls180.v:5930.42-5930.95"
- cell $and $and$ls180.v:5930$1340
+ attribute \src "ls180.v:5926.42-5926.95"
+ cell $and $and$ls180.v:5926$1340
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank5_sel
connect \B \builder_interface5_bank_bus_we
- connect \Y $and$ls180.v:5930$1340_Y
+ connect \Y $and$ls180.v:5926$1340_Y
end
- attribute \src "ls180.v:5930.41-5930.145"
- cell $and $and$ls180.v:5930$1342
+ attribute \src "ls180.v:5926.41-5926.145"
+ cell $and $and$ls180.v:5926$1342
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5930$1340_Y
- connect \B $eq$ls180.v:5930$1341_Y
- connect \Y $and$ls180.v:5930$1342_Y
+ connect \A $and$ls180.v:5926$1340_Y
+ connect \B $eq$ls180.v:5926$1341_Y
+ connect \Y $and$ls180.v:5926$1342_Y
end
- attribute \src "ls180.v:5931.42-5931.98"
- cell $and $and$ls180.v:5931$1344
+ attribute \src "ls180.v:5927.42-5927.98"
+ cell $and $and$ls180.v:5927$1344
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank5_sel
- connect \B $not$ls180.v:5931$1343_Y
- connect \Y $and$ls180.v:5931$1344_Y
+ connect \B $not$ls180.v:5927$1343_Y
+ connect \Y $and$ls180.v:5927$1344_Y
end
- attribute \src "ls180.v:5931.41-5931.148"
- cell $and $and$ls180.v:5931$1346
+ attribute \src "ls180.v:5927.41-5927.148"
+ cell $and $and$ls180.v:5927$1346
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5931$1344_Y
- connect \B $eq$ls180.v:5931$1345_Y
- connect \Y $and$ls180.v:5931$1346_Y
+ connect \A $and$ls180.v:5927$1344_Y
+ connect \B $eq$ls180.v:5927$1345_Y
+ connect \Y $and$ls180.v:5927$1346_Y
end
- attribute \src "ls180.v:5933.42-5933.95"
- cell $and $and$ls180.v:5933$1347
+ attribute \src "ls180.v:5929.42-5929.95"
+ cell $and $and$ls180.v:5929$1347
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank5_sel
connect \B \builder_interface5_bank_bus_we
- connect \Y $and$ls180.v:5933$1347_Y
+ connect \Y $and$ls180.v:5929$1347_Y
end
- attribute \src "ls180.v:5933.41-5933.145"
- cell $and $and$ls180.v:5933$1349
+ attribute \src "ls180.v:5929.41-5929.145"
+ cell $and $and$ls180.v:5929$1349
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5933$1347_Y
- connect \B $eq$ls180.v:5933$1348_Y
- connect \Y $and$ls180.v:5933$1349_Y
+ connect \A $and$ls180.v:5929$1347_Y
+ connect \B $eq$ls180.v:5929$1348_Y
+ connect \Y $and$ls180.v:5929$1349_Y
end
- attribute \src "ls180.v:5934.42-5934.98"
- cell $and $and$ls180.v:5934$1351
+ attribute \src "ls180.v:5930.42-5930.98"
+ cell $and $and$ls180.v:5930$1351
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank5_sel
- connect \B $not$ls180.v:5934$1350_Y
- connect \Y $and$ls180.v:5934$1351_Y
+ connect \B $not$ls180.v:5930$1350_Y
+ connect \Y $and$ls180.v:5930$1351_Y
end
- attribute \src "ls180.v:5934.41-5934.148"
- cell $and $and$ls180.v:5934$1353
+ attribute \src "ls180.v:5930.41-5930.148"
+ cell $and $and$ls180.v:5930$1353
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5934$1351_Y
- connect \B $eq$ls180.v:5934$1352_Y
- connect \Y $and$ls180.v:5934$1353_Y
+ connect \A $and$ls180.v:5930$1351_Y
+ connect \B $eq$ls180.v:5930$1352_Y
+ connect \Y $and$ls180.v:5930$1353_Y
end
- attribute \src "ls180.v:5936.42-5936.95"
- cell $and $and$ls180.v:5936$1354
+ attribute \src "ls180.v:5932.42-5932.95"
+ cell $and $and$ls180.v:5932$1354
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank5_sel
connect \B \builder_interface5_bank_bus_we
- connect \Y $and$ls180.v:5936$1354_Y
+ connect \Y $and$ls180.v:5932$1354_Y
end
- attribute \src "ls180.v:5936.41-5936.145"
- cell $and $and$ls180.v:5936$1356
+ attribute \src "ls180.v:5932.41-5932.145"
+ cell $and $and$ls180.v:5932$1356
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5936$1354_Y
- connect \B $eq$ls180.v:5936$1355_Y
- connect \Y $and$ls180.v:5936$1356_Y
+ connect \A $and$ls180.v:5932$1354_Y
+ connect \B $eq$ls180.v:5932$1355_Y
+ connect \Y $and$ls180.v:5932$1356_Y
end
- attribute \src "ls180.v:5937.42-5937.98"
- cell $and $and$ls180.v:5937$1358
+ attribute \src "ls180.v:5933.42-5933.98"
+ cell $and $and$ls180.v:5933$1358
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank5_sel
- connect \B $not$ls180.v:5937$1357_Y
- connect \Y $and$ls180.v:5937$1358_Y
+ connect \B $not$ls180.v:5933$1357_Y
+ connect \Y $and$ls180.v:5933$1358_Y
end
- attribute \src "ls180.v:5937.41-5937.148"
- cell $and $and$ls180.v:5937$1360
+ attribute \src "ls180.v:5933.41-5933.148"
+ cell $and $and$ls180.v:5933$1360
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5937$1358_Y
- connect \B $eq$ls180.v:5937$1359_Y
- connect \Y $and$ls180.v:5937$1360_Y
+ connect \A $and$ls180.v:5933$1358_Y
+ connect \B $eq$ls180.v:5933$1359_Y
+ connect \Y $and$ls180.v:5933$1360_Y
end
- attribute \src "ls180.v:5939.42-5939.95"
- cell $and $and$ls180.v:5939$1361
+ attribute \src "ls180.v:5935.42-5935.95"
+ cell $and $and$ls180.v:5935$1361
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank5_sel
connect \B \builder_interface5_bank_bus_we
- connect \Y $and$ls180.v:5939$1361_Y
+ connect \Y $and$ls180.v:5935$1361_Y
end
- attribute \src "ls180.v:5939.41-5939.145"
- cell $and $and$ls180.v:5939$1363
+ attribute \src "ls180.v:5935.41-5935.145"
+ cell $and $and$ls180.v:5935$1363
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5939$1361_Y
- connect \B $eq$ls180.v:5939$1362_Y
- connect \Y $and$ls180.v:5939$1363_Y
+ connect \A $and$ls180.v:5935$1361_Y
+ connect \B $eq$ls180.v:5935$1362_Y
+ connect \Y $and$ls180.v:5935$1363_Y
end
- attribute \src "ls180.v:5940.42-5940.98"
- cell $and $and$ls180.v:5940$1365
+ attribute \src "ls180.v:5936.42-5936.98"
+ cell $and $and$ls180.v:5936$1365
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank5_sel
- connect \B $not$ls180.v:5940$1364_Y
- connect \Y $and$ls180.v:5940$1365_Y
+ connect \B $not$ls180.v:5936$1364_Y
+ connect \Y $and$ls180.v:5936$1365_Y
end
- attribute \src "ls180.v:5940.41-5940.148"
- cell $and $and$ls180.v:5940$1367
+ attribute \src "ls180.v:5936.41-5936.148"
+ cell $and $and$ls180.v:5936$1367
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5940$1365_Y
- connect \B $eq$ls180.v:5940$1366_Y
- connect \Y $and$ls180.v:5940$1367_Y
+ connect \A $and$ls180.v:5936$1365_Y
+ connect \B $eq$ls180.v:5936$1366_Y
+ connect \Y $and$ls180.v:5936$1367_Y
end
- attribute \src "ls180.v:5942.42-5942.95"
- cell $and $and$ls180.v:5942$1368
+ attribute \src "ls180.v:5938.42-5938.95"
+ cell $and $and$ls180.v:5938$1368
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank5_sel
connect \B \builder_interface5_bank_bus_we
- connect \Y $and$ls180.v:5942$1368_Y
+ connect \Y $and$ls180.v:5938$1368_Y
end
- attribute \src "ls180.v:5942.41-5942.145"
- cell $and $and$ls180.v:5942$1370
+ attribute \src "ls180.v:5938.41-5938.145"
+ cell $and $and$ls180.v:5938$1370
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5942$1368_Y
- connect \B $eq$ls180.v:5942$1369_Y
- connect \Y $and$ls180.v:5942$1370_Y
+ connect \A $and$ls180.v:5938$1368_Y
+ connect \B $eq$ls180.v:5938$1369_Y
+ connect \Y $and$ls180.v:5938$1370_Y
end
- attribute \src "ls180.v:5943.42-5943.98"
- cell $and $and$ls180.v:5943$1372
+ attribute \src "ls180.v:5939.42-5939.98"
+ cell $and $and$ls180.v:5939$1372
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank5_sel
- connect \B $not$ls180.v:5943$1371_Y
- connect \Y $and$ls180.v:5943$1372_Y
+ connect \B $not$ls180.v:5939$1371_Y
+ connect \Y $and$ls180.v:5939$1372_Y
end
- attribute \src "ls180.v:5943.41-5943.148"
- cell $and $and$ls180.v:5943$1374
+ attribute \src "ls180.v:5939.41-5939.148"
+ cell $and $and$ls180.v:5939$1374
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5943$1372_Y
- connect \B $eq$ls180.v:5943$1373_Y
- connect \Y $and$ls180.v:5943$1374_Y
+ connect \A $and$ls180.v:5939$1372_Y
+ connect \B $eq$ls180.v:5939$1373_Y
+ connect \Y $and$ls180.v:5939$1374_Y
end
- attribute \src "ls180.v:5945.42-5945.95"
- cell $and $and$ls180.v:5945$1375
+ attribute \src "ls180.v:5941.42-5941.95"
+ cell $and $and$ls180.v:5941$1375
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank5_sel
connect \B \builder_interface5_bank_bus_we
- connect \Y $and$ls180.v:5945$1375_Y
+ connect \Y $and$ls180.v:5941$1375_Y
end
- attribute \src "ls180.v:5945.41-5945.145"
- cell $and $and$ls180.v:5945$1377
+ attribute \src "ls180.v:5941.41-5941.145"
+ cell $and $and$ls180.v:5941$1377
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5945$1375_Y
- connect \B $eq$ls180.v:5945$1376_Y
- connect \Y $and$ls180.v:5945$1377_Y
+ connect \A $and$ls180.v:5941$1375_Y
+ connect \B $eq$ls180.v:5941$1376_Y
+ connect \Y $and$ls180.v:5941$1377_Y
end
- attribute \src "ls180.v:5946.42-5946.98"
- cell $and $and$ls180.v:5946$1379
+ attribute \src "ls180.v:5942.42-5942.98"
+ cell $and $and$ls180.v:5942$1379
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank5_sel
- connect \B $not$ls180.v:5946$1378_Y
- connect \Y $and$ls180.v:5946$1379_Y
+ connect \B $not$ls180.v:5942$1378_Y
+ connect \Y $and$ls180.v:5942$1379_Y
end
- attribute \src "ls180.v:5946.41-5946.148"
- cell $and $and$ls180.v:5946$1381
+ attribute \src "ls180.v:5942.41-5942.148"
+ cell $and $and$ls180.v:5942$1381
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5946$1379_Y
- connect \B $eq$ls180.v:5946$1380_Y
- connect \Y $and$ls180.v:5946$1381_Y
+ connect \A $and$ls180.v:5942$1379_Y
+ connect \B $eq$ls180.v:5942$1380_Y
+ connect \Y $and$ls180.v:5942$1381_Y
end
- attribute \src "ls180.v:5948.42-5948.95"
- cell $and $and$ls180.v:5948$1382
+ attribute \src "ls180.v:5944.42-5944.95"
+ cell $and $and$ls180.v:5944$1382
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank5_sel
connect \B \builder_interface5_bank_bus_we
- connect \Y $and$ls180.v:5948$1382_Y
+ connect \Y $and$ls180.v:5944$1382_Y
end
- attribute \src "ls180.v:5948.41-5948.145"
- cell $and $and$ls180.v:5948$1384
+ attribute \src "ls180.v:5944.41-5944.145"
+ cell $and $and$ls180.v:5944$1384
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5948$1382_Y
- connect \B $eq$ls180.v:5948$1383_Y
- connect \Y $and$ls180.v:5948$1384_Y
+ connect \A $and$ls180.v:5944$1382_Y
+ connect \B $eq$ls180.v:5944$1383_Y
+ connect \Y $and$ls180.v:5944$1384_Y
end
- attribute \src "ls180.v:5949.42-5949.98"
- cell $and $and$ls180.v:5949$1386
+ attribute \src "ls180.v:5945.42-5945.98"
+ cell $and $and$ls180.v:5945$1386
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank5_sel
- connect \B $not$ls180.v:5949$1385_Y
- connect \Y $and$ls180.v:5949$1386_Y
+ connect \B $not$ls180.v:5945$1385_Y
+ connect \Y $and$ls180.v:5945$1386_Y
end
- attribute \src "ls180.v:5949.41-5949.148"
- cell $and $and$ls180.v:5949$1388
+ attribute \src "ls180.v:5945.41-5945.148"
+ cell $and $and$ls180.v:5945$1388
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5949$1386_Y
- connect \B $eq$ls180.v:5949$1387_Y
- connect \Y $and$ls180.v:5949$1388_Y
+ connect \A $and$ls180.v:5945$1386_Y
+ connect \B $eq$ls180.v:5945$1387_Y
+ connect \Y $and$ls180.v:5945$1388_Y
end
- attribute \src "ls180.v:5951.44-5951.97"
- cell $and $and$ls180.v:5951$1389
+ attribute \src "ls180.v:5947.44-5947.97"
+ cell $and $and$ls180.v:5947$1389
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank5_sel
connect \B \builder_interface5_bank_bus_we
- connect \Y $and$ls180.v:5951$1389_Y
+ connect \Y $and$ls180.v:5947$1389_Y
end
- attribute \src "ls180.v:5951.43-5951.147"
- cell $and $and$ls180.v:5951$1391
+ attribute \src "ls180.v:5947.43-5947.147"
+ cell $and $and$ls180.v:5947$1391
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5951$1389_Y
- connect \B $eq$ls180.v:5951$1390_Y
- connect \Y $and$ls180.v:5951$1391_Y
+ connect \A $and$ls180.v:5947$1389_Y
+ connect \B $eq$ls180.v:5947$1390_Y
+ connect \Y $and$ls180.v:5947$1391_Y
end
- attribute \src "ls180.v:5952.44-5952.100"
- cell $and $and$ls180.v:5952$1393
+ attribute \src "ls180.v:5948.44-5948.100"
+ cell $and $and$ls180.v:5948$1393
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank5_sel
- connect \B $not$ls180.v:5952$1392_Y
- connect \Y $and$ls180.v:5952$1393_Y
+ connect \B $not$ls180.v:5948$1392_Y
+ connect \Y $and$ls180.v:5948$1393_Y
end
- attribute \src "ls180.v:5952.43-5952.150"
- cell $and $and$ls180.v:5952$1395
+ attribute \src "ls180.v:5948.43-5948.150"
+ cell $and $and$ls180.v:5948$1395
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5952$1393_Y
- connect \B $eq$ls180.v:5952$1394_Y
- connect \Y $and$ls180.v:5952$1395_Y
+ connect \A $and$ls180.v:5948$1393_Y
+ connect \B $eq$ls180.v:5948$1394_Y
+ connect \Y $and$ls180.v:5948$1395_Y
end
- attribute \src "ls180.v:5954.44-5954.97"
- cell $and $and$ls180.v:5954$1396
+ attribute \src "ls180.v:5950.44-5950.97"
+ cell $and $and$ls180.v:5950$1396
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank5_sel
connect \B \builder_interface5_bank_bus_we
- connect \Y $and$ls180.v:5954$1396_Y
+ connect \Y $and$ls180.v:5950$1396_Y
end
- attribute \src "ls180.v:5954.43-5954.147"
- cell $and $and$ls180.v:5954$1398
+ attribute \src "ls180.v:5950.43-5950.147"
+ cell $and $and$ls180.v:5950$1398
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5954$1396_Y
- connect \B $eq$ls180.v:5954$1397_Y
- connect \Y $and$ls180.v:5954$1398_Y
+ connect \A $and$ls180.v:5950$1396_Y
+ connect \B $eq$ls180.v:5950$1397_Y
+ connect \Y $and$ls180.v:5950$1398_Y
end
- attribute \src "ls180.v:5955.44-5955.100"
- cell $and $and$ls180.v:5955$1400
+ attribute \src "ls180.v:5951.44-5951.100"
+ cell $and $and$ls180.v:5951$1400
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank5_sel
- connect \B $not$ls180.v:5955$1399_Y
- connect \Y $and$ls180.v:5955$1400_Y
+ connect \B $not$ls180.v:5951$1399_Y
+ connect \Y $and$ls180.v:5951$1400_Y
end
- attribute \src "ls180.v:5955.43-5955.150"
- cell $and $and$ls180.v:5955$1402
+ attribute \src "ls180.v:5951.43-5951.150"
+ cell $and $and$ls180.v:5951$1402
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5955$1400_Y
- connect \B $eq$ls180.v:5955$1401_Y
- connect \Y $and$ls180.v:5955$1402_Y
+ connect \A $and$ls180.v:5951$1400_Y
+ connect \B $eq$ls180.v:5951$1401_Y
+ connect \Y $and$ls180.v:5951$1402_Y
end
- attribute \src "ls180.v:5957.44-5957.97"
- cell $and $and$ls180.v:5957$1403
+ attribute \src "ls180.v:5953.44-5953.97"
+ cell $and $and$ls180.v:5953$1403
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank5_sel
connect \B \builder_interface5_bank_bus_we
- connect \Y $and$ls180.v:5957$1403_Y
+ connect \Y $and$ls180.v:5953$1403_Y
end
- attribute \src "ls180.v:5957.43-5957.148"
- cell $and $and$ls180.v:5957$1405
+ attribute \src "ls180.v:5953.43-5953.148"
+ cell $and $and$ls180.v:5953$1405
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5957$1403_Y
- connect \B $eq$ls180.v:5957$1404_Y
- connect \Y $and$ls180.v:5957$1405_Y
+ connect \A $and$ls180.v:5953$1403_Y
+ connect \B $eq$ls180.v:5953$1404_Y
+ connect \Y $and$ls180.v:5953$1405_Y
end
- attribute \src "ls180.v:5958.44-5958.100"
- cell $and $and$ls180.v:5958$1407
+ attribute \src "ls180.v:5954.44-5954.100"
+ cell $and $and$ls180.v:5954$1407
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank5_sel
- connect \B $not$ls180.v:5958$1406_Y
- connect \Y $and$ls180.v:5958$1407_Y
+ connect \B $not$ls180.v:5954$1406_Y
+ connect \Y $and$ls180.v:5954$1407_Y
end
- attribute \src "ls180.v:5958.43-5958.151"
- cell $and $and$ls180.v:5958$1409
+ attribute \src "ls180.v:5954.43-5954.151"
+ cell $and $and$ls180.v:5954$1409
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5958$1407_Y
- connect \B $eq$ls180.v:5958$1408_Y
- connect \Y $and$ls180.v:5958$1409_Y
+ connect \A $and$ls180.v:5954$1407_Y
+ connect \B $eq$ls180.v:5954$1408_Y
+ connect \Y $and$ls180.v:5954$1409_Y
end
- attribute \src "ls180.v:5960.44-5960.97"
- cell $and $and$ls180.v:5960$1410
+ attribute \src "ls180.v:5956.44-5956.97"
+ cell $and $and$ls180.v:5956$1410
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank5_sel
connect \B \builder_interface5_bank_bus_we
- connect \Y $and$ls180.v:5960$1410_Y
+ connect \Y $and$ls180.v:5956$1410_Y
end
- attribute \src "ls180.v:5960.43-5960.148"
- cell $and $and$ls180.v:5960$1412
+ attribute \src "ls180.v:5956.43-5956.148"
+ cell $and $and$ls180.v:5956$1412
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5960$1410_Y
- connect \B $eq$ls180.v:5960$1411_Y
- connect \Y $and$ls180.v:5960$1412_Y
+ connect \A $and$ls180.v:5956$1410_Y
+ connect \B $eq$ls180.v:5956$1411_Y
+ connect \Y $and$ls180.v:5956$1412_Y
end
- attribute \src "ls180.v:5961.44-5961.100"
- cell $and $and$ls180.v:5961$1414
+ attribute \src "ls180.v:5957.44-5957.100"
+ cell $and $and$ls180.v:5957$1414
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank5_sel
- connect \B $not$ls180.v:5961$1413_Y
- connect \Y $and$ls180.v:5961$1414_Y
+ connect \B $not$ls180.v:5957$1413_Y
+ connect \Y $and$ls180.v:5957$1414_Y
end
- attribute \src "ls180.v:5961.43-5961.151"
- cell $and $and$ls180.v:5961$1416
+ attribute \src "ls180.v:5957.43-5957.151"
+ cell $and $and$ls180.v:5957$1416
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5961$1414_Y
- connect \B $eq$ls180.v:5961$1415_Y
- connect \Y $and$ls180.v:5961$1416_Y
+ connect \A $and$ls180.v:5957$1414_Y
+ connect \B $eq$ls180.v:5957$1415_Y
+ connect \Y $and$ls180.v:5957$1416_Y
end
- attribute \src "ls180.v:5963.44-5963.97"
- cell $and $and$ls180.v:5963$1417
+ attribute \src "ls180.v:5959.44-5959.97"
+ cell $and $and$ls180.v:5959$1417
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank5_sel
connect \B \builder_interface5_bank_bus_we
- connect \Y $and$ls180.v:5963$1417_Y
+ connect \Y $and$ls180.v:5959$1417_Y
end
- attribute \src "ls180.v:5963.43-5963.148"
- cell $and $and$ls180.v:5963$1419
+ attribute \src "ls180.v:5959.43-5959.148"
+ cell $and $and$ls180.v:5959$1419
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5963$1417_Y
- connect \B $eq$ls180.v:5963$1418_Y
- connect \Y $and$ls180.v:5963$1419_Y
+ connect \A $and$ls180.v:5959$1417_Y
+ connect \B $eq$ls180.v:5959$1418_Y
+ connect \Y $and$ls180.v:5959$1419_Y
end
- attribute \src "ls180.v:5964.44-5964.100"
- cell $and $and$ls180.v:5964$1421
+ attribute \src "ls180.v:5960.44-5960.100"
+ cell $and $and$ls180.v:5960$1421
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank5_sel
- connect \B $not$ls180.v:5964$1420_Y
- connect \Y $and$ls180.v:5964$1421_Y
+ connect \B $not$ls180.v:5960$1420_Y
+ connect \Y $and$ls180.v:5960$1421_Y
end
- attribute \src "ls180.v:5964.43-5964.151"
- cell $and $and$ls180.v:5964$1423
+ attribute \src "ls180.v:5960.43-5960.151"
+ cell $and $and$ls180.v:5960$1423
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5964$1421_Y
- connect \B $eq$ls180.v:5964$1422_Y
- connect \Y $and$ls180.v:5964$1423_Y
+ connect \A $and$ls180.v:5960$1421_Y
+ connect \B $eq$ls180.v:5960$1422_Y
+ connect \Y $and$ls180.v:5960$1423_Y
end
- attribute \src "ls180.v:5966.41-5966.94"
- cell $and $and$ls180.v:5966$1424
+ attribute \src "ls180.v:5962.41-5962.94"
+ cell $and $and$ls180.v:5962$1424
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank5_sel
connect \B \builder_interface5_bank_bus_we
- connect \Y $and$ls180.v:5966$1424_Y
+ connect \Y $and$ls180.v:5962$1424_Y
end
- attribute \src "ls180.v:5966.40-5966.145"
- cell $and $and$ls180.v:5966$1426
+ attribute \src "ls180.v:5962.40-5962.145"
+ cell $and $and$ls180.v:5962$1426
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5966$1424_Y
- connect \B $eq$ls180.v:5966$1425_Y
- connect \Y $and$ls180.v:5966$1426_Y
+ connect \A $and$ls180.v:5962$1424_Y
+ connect \B $eq$ls180.v:5962$1425_Y
+ connect \Y $and$ls180.v:5962$1426_Y
end
- attribute \src "ls180.v:5967.41-5967.97"
- cell $and $and$ls180.v:5967$1428
+ attribute \src "ls180.v:5963.41-5963.97"
+ cell $and $and$ls180.v:5963$1428
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank5_sel
- connect \B $not$ls180.v:5967$1427_Y
- connect \Y $and$ls180.v:5967$1428_Y
+ connect \B $not$ls180.v:5963$1427_Y
+ connect \Y $and$ls180.v:5963$1428_Y
end
- attribute \src "ls180.v:5967.40-5967.148"
- cell $and $and$ls180.v:5967$1430
+ attribute \src "ls180.v:5963.40-5963.148"
+ cell $and $and$ls180.v:5963$1430
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5967$1428_Y
- connect \B $eq$ls180.v:5967$1429_Y
- connect \Y $and$ls180.v:5967$1430_Y
+ connect \A $and$ls180.v:5963$1428_Y
+ connect \B $eq$ls180.v:5963$1429_Y
+ connect \Y $and$ls180.v:5963$1430_Y
end
- attribute \src "ls180.v:5969.42-5969.95"
- cell $and $and$ls180.v:5969$1431
+ attribute \src "ls180.v:5965.42-5965.95"
+ cell $and $and$ls180.v:5965$1431
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank5_sel
connect \B \builder_interface5_bank_bus_we
- connect \Y $and$ls180.v:5969$1431_Y
+ connect \Y $and$ls180.v:5965$1431_Y
end
- attribute \src "ls180.v:5969.41-5969.146"
- cell $and $and$ls180.v:5969$1433
+ attribute \src "ls180.v:5965.41-5965.146"
+ cell $and $and$ls180.v:5965$1433
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5969$1431_Y
- connect \B $eq$ls180.v:5969$1432_Y
- connect \Y $and$ls180.v:5969$1433_Y
+ connect \A $and$ls180.v:5965$1431_Y
+ connect \B $eq$ls180.v:5965$1432_Y
+ connect \Y $and$ls180.v:5965$1433_Y
end
- attribute \src "ls180.v:5970.42-5970.98"
- cell $and $and$ls180.v:5970$1435
+ attribute \src "ls180.v:5966.42-5966.98"
+ cell $and $and$ls180.v:5966$1435
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank5_sel
- connect \B $not$ls180.v:5970$1434_Y
- connect \Y $and$ls180.v:5970$1435_Y
+ connect \B $not$ls180.v:5966$1434_Y
+ connect \Y $and$ls180.v:5966$1435_Y
end
- attribute \src "ls180.v:5970.41-5970.149"
- cell $and $and$ls180.v:5970$1437
+ attribute \src "ls180.v:5966.41-5966.149"
+ cell $and $and$ls180.v:5966$1437
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5970$1435_Y
- connect \B $eq$ls180.v:5970$1436_Y
- connect \Y $and$ls180.v:5970$1437_Y
+ connect \A $and$ls180.v:5966$1435_Y
+ connect \B $eq$ls180.v:5966$1436_Y
+ connect \Y $and$ls180.v:5966$1437_Y
end
- attribute \src "ls180.v:5989.46-5989.99"
- cell $and $and$ls180.v:5989$1439
+ attribute \src "ls180.v:5985.46-5985.99"
+ cell $and $and$ls180.v:5985$1439
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank6_sel
connect \B \builder_interface6_bank_bus_we
- connect \Y $and$ls180.v:5989$1439_Y
+ connect \Y $and$ls180.v:5985$1439_Y
end
- attribute \src "ls180.v:5989.45-5989.149"
- cell $and $and$ls180.v:5989$1441
+ attribute \src "ls180.v:5985.45-5985.149"
+ cell $and $and$ls180.v:5985$1441
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5989$1439_Y
- connect \B $eq$ls180.v:5989$1440_Y
- connect \Y $and$ls180.v:5989$1441_Y
+ connect \A $and$ls180.v:5985$1439_Y
+ connect \B $eq$ls180.v:5985$1440_Y
+ connect \Y $and$ls180.v:5985$1441_Y
end
- attribute \src "ls180.v:5990.46-5990.102"
- cell $and $and$ls180.v:5990$1443
+ attribute \src "ls180.v:5986.46-5986.102"
+ cell $and $and$ls180.v:5986$1443
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank6_sel
- connect \B $not$ls180.v:5990$1442_Y
- connect \Y $and$ls180.v:5990$1443_Y
+ connect \B $not$ls180.v:5986$1442_Y
+ connect \Y $and$ls180.v:5986$1443_Y
end
- attribute \src "ls180.v:5990.45-5990.152"
- cell $and $and$ls180.v:5990$1445
+ attribute \src "ls180.v:5986.45-5986.152"
+ cell $and $and$ls180.v:5986$1445
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5990$1443_Y
- connect \B $eq$ls180.v:5990$1444_Y
- connect \Y $and$ls180.v:5990$1445_Y
+ connect \A $and$ls180.v:5986$1443_Y
+ connect \B $eq$ls180.v:5986$1444_Y
+ connect \Y $and$ls180.v:5986$1445_Y
end
- attribute \src "ls180.v:5992.46-5992.99"
- cell $and $and$ls180.v:5992$1446
+ attribute \src "ls180.v:5988.46-5988.99"
+ cell $and $and$ls180.v:5988$1446
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank6_sel
connect \B \builder_interface6_bank_bus_we
- connect \Y $and$ls180.v:5992$1446_Y
+ connect \Y $and$ls180.v:5988$1446_Y
end
- attribute \src "ls180.v:5992.45-5992.149"
- cell $and $and$ls180.v:5992$1448
+ attribute \src "ls180.v:5988.45-5988.149"
+ cell $and $and$ls180.v:5988$1448
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5992$1446_Y
- connect \B $eq$ls180.v:5992$1447_Y
- connect \Y $and$ls180.v:5992$1448_Y
+ connect \A $and$ls180.v:5988$1446_Y
+ connect \B $eq$ls180.v:5988$1447_Y
+ connect \Y $and$ls180.v:5988$1448_Y
end
- attribute \src "ls180.v:5993.46-5993.102"
- cell $and $and$ls180.v:5993$1450
+ attribute \src "ls180.v:5989.46-5989.102"
+ cell $and $and$ls180.v:5989$1450
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank6_sel
- connect \B $not$ls180.v:5993$1449_Y
- connect \Y $and$ls180.v:5993$1450_Y
+ connect \B $not$ls180.v:5989$1449_Y
+ connect \Y $and$ls180.v:5989$1450_Y
end
- attribute \src "ls180.v:5993.45-5993.152"
- cell $and $and$ls180.v:5993$1452
+ attribute \src "ls180.v:5989.45-5989.152"
+ cell $and $and$ls180.v:5989$1452
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5993$1450_Y
- connect \B $eq$ls180.v:5993$1451_Y
- connect \Y $and$ls180.v:5993$1452_Y
+ connect \A $and$ls180.v:5989$1450_Y
+ connect \B $eq$ls180.v:5989$1451_Y
+ connect \Y $and$ls180.v:5989$1452_Y
end
- attribute \src "ls180.v:5995.46-5995.99"
- cell $and $and$ls180.v:5995$1453
+ attribute \src "ls180.v:5991.46-5991.99"
+ cell $and $and$ls180.v:5991$1453
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank6_sel
connect \B \builder_interface6_bank_bus_we
- connect \Y $and$ls180.v:5995$1453_Y
+ connect \Y $and$ls180.v:5991$1453_Y
end
- attribute \src "ls180.v:5995.45-5995.149"
- cell $and $and$ls180.v:5995$1455
+ attribute \src "ls180.v:5991.45-5991.149"
+ cell $and $and$ls180.v:5991$1455
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5995$1453_Y
- connect \B $eq$ls180.v:5995$1454_Y
- connect \Y $and$ls180.v:5995$1455_Y
+ connect \A $and$ls180.v:5991$1453_Y
+ connect \B $eq$ls180.v:5991$1454_Y
+ connect \Y $and$ls180.v:5991$1455_Y
end
- attribute \src "ls180.v:5996.46-5996.102"
- cell $and $and$ls180.v:5996$1457
+ attribute \src "ls180.v:5992.46-5992.102"
+ cell $and $and$ls180.v:5992$1457
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank6_sel
- connect \B $not$ls180.v:5996$1456_Y
- connect \Y $and$ls180.v:5996$1457_Y
+ connect \B $not$ls180.v:5992$1456_Y
+ connect \Y $and$ls180.v:5992$1457_Y
end
- attribute \src "ls180.v:5996.45-5996.152"
- cell $and $and$ls180.v:5996$1459
+ attribute \src "ls180.v:5992.45-5992.152"
+ cell $and $and$ls180.v:5992$1459
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5996$1457_Y
- connect \B $eq$ls180.v:5996$1458_Y
- connect \Y $and$ls180.v:5996$1459_Y
+ connect \A $and$ls180.v:5992$1457_Y
+ connect \B $eq$ls180.v:5992$1458_Y
+ connect \Y $and$ls180.v:5992$1459_Y
end
- attribute \src "ls180.v:5998.46-5998.99"
- cell $and $and$ls180.v:5998$1460
+ attribute \src "ls180.v:5994.46-5994.99"
+ cell $and $and$ls180.v:5994$1460
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank6_sel
connect \B \builder_interface6_bank_bus_we
- connect \Y $and$ls180.v:5998$1460_Y
+ connect \Y $and$ls180.v:5994$1460_Y
end
- attribute \src "ls180.v:5998.45-5998.149"
- cell $and $and$ls180.v:5998$1462
+ attribute \src "ls180.v:5994.45-5994.149"
+ cell $and $and$ls180.v:5994$1462
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5998$1460_Y
- connect \B $eq$ls180.v:5998$1461_Y
- connect \Y $and$ls180.v:5998$1462_Y
+ connect \A $and$ls180.v:5994$1460_Y
+ connect \B $eq$ls180.v:5994$1461_Y
+ connect \Y $and$ls180.v:5994$1462_Y
end
- attribute \src "ls180.v:5999.46-5999.102"
- cell $and $and$ls180.v:5999$1464
+ attribute \src "ls180.v:5995.46-5995.102"
+ cell $and $and$ls180.v:5995$1464
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank6_sel
- connect \B $not$ls180.v:5999$1463_Y
- connect \Y $and$ls180.v:5999$1464_Y
+ connect \B $not$ls180.v:5995$1463_Y
+ connect \Y $and$ls180.v:5995$1464_Y
end
- attribute \src "ls180.v:5999.45-5999.152"
- cell $and $and$ls180.v:5999$1466
+ attribute \src "ls180.v:5995.45-5995.152"
+ cell $and $and$ls180.v:5995$1466
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5999$1464_Y
- connect \B $eq$ls180.v:5999$1465_Y
- connect \Y $and$ls180.v:5999$1466_Y
+ connect \A $and$ls180.v:5995$1464_Y
+ connect \B $eq$ls180.v:5995$1465_Y
+ connect \Y $and$ls180.v:5995$1466_Y
end
- attribute \src "ls180.v:6001.45-6001.98"
- cell $and $and$ls180.v:6001$1467
+ attribute \src "ls180.v:5997.45-5997.98"
+ cell $and $and$ls180.v:5997$1467
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank6_sel
connect \B \builder_interface6_bank_bus_we
- connect \Y $and$ls180.v:6001$1467_Y
+ connect \Y $and$ls180.v:5997$1467_Y
end
- attribute \src "ls180.v:6001.44-6001.148"
- cell $and $and$ls180.v:6001$1469
+ attribute \src "ls180.v:5997.44-5997.148"
+ cell $and $and$ls180.v:5997$1469
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6001$1467_Y
- connect \B $eq$ls180.v:6001$1468_Y
- connect \Y $and$ls180.v:6001$1469_Y
+ connect \A $and$ls180.v:5997$1467_Y
+ connect \B $eq$ls180.v:5997$1468_Y
+ connect \Y $and$ls180.v:5997$1469_Y
end
- attribute \src "ls180.v:6002.45-6002.101"
- cell $and $and$ls180.v:6002$1471
+ attribute \src "ls180.v:5998.45-5998.101"
+ cell $and $and$ls180.v:5998$1471
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank6_sel
- connect \B $not$ls180.v:6002$1470_Y
- connect \Y $and$ls180.v:6002$1471_Y
+ connect \B $not$ls180.v:5998$1470_Y
+ connect \Y $and$ls180.v:5998$1471_Y
end
- attribute \src "ls180.v:6002.44-6002.151"
- cell $and $and$ls180.v:6002$1473
+ attribute \src "ls180.v:5998.44-5998.151"
+ cell $and $and$ls180.v:5998$1473
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6002$1471_Y
- connect \B $eq$ls180.v:6002$1472_Y
- connect \Y $and$ls180.v:6002$1473_Y
+ connect \A $and$ls180.v:5998$1471_Y
+ connect \B $eq$ls180.v:5998$1472_Y
+ connect \Y $and$ls180.v:5998$1473_Y
end
- attribute \src "ls180.v:6004.45-6004.98"
- cell $and $and$ls180.v:6004$1474
+ attribute \src "ls180.v:6000.45-6000.98"
+ cell $and $and$ls180.v:6000$1474
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank6_sel
connect \B \builder_interface6_bank_bus_we
- connect \Y $and$ls180.v:6004$1474_Y
+ connect \Y $and$ls180.v:6000$1474_Y
end
- attribute \src "ls180.v:6004.44-6004.148"
- cell $and $and$ls180.v:6004$1476
+ attribute \src "ls180.v:6000.44-6000.148"
+ cell $and $and$ls180.v:6000$1476
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6004$1474_Y
- connect \B $eq$ls180.v:6004$1475_Y
- connect \Y $and$ls180.v:6004$1476_Y
+ connect \A $and$ls180.v:6000$1474_Y
+ connect \B $eq$ls180.v:6000$1475_Y
+ connect \Y $and$ls180.v:6000$1476_Y
end
- attribute \src "ls180.v:6005.45-6005.101"
- cell $and $and$ls180.v:6005$1478
+ attribute \src "ls180.v:6001.45-6001.101"
+ cell $and $and$ls180.v:6001$1478
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank6_sel
- connect \B $not$ls180.v:6005$1477_Y
- connect \Y $and$ls180.v:6005$1478_Y
+ connect \B $not$ls180.v:6001$1477_Y
+ connect \Y $and$ls180.v:6001$1478_Y
end
- attribute \src "ls180.v:6005.44-6005.151"
- cell $and $and$ls180.v:6005$1480
+ attribute \src "ls180.v:6001.44-6001.151"
+ cell $and $and$ls180.v:6001$1480
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6005$1478_Y
- connect \B $eq$ls180.v:6005$1479_Y
- connect \Y $and$ls180.v:6005$1480_Y
+ connect \A $and$ls180.v:6001$1478_Y
+ connect \B $eq$ls180.v:6001$1479_Y
+ connect \Y $and$ls180.v:6001$1480_Y
end
- attribute \src "ls180.v:6007.45-6007.98"
- cell $and $and$ls180.v:6007$1481
+ attribute \src "ls180.v:6003.45-6003.98"
+ cell $and $and$ls180.v:6003$1481
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank6_sel
connect \B \builder_interface6_bank_bus_we
- connect \Y $and$ls180.v:6007$1481_Y
+ connect \Y $and$ls180.v:6003$1481_Y
end
- attribute \src "ls180.v:6007.44-6007.148"
- cell $and $and$ls180.v:6007$1483
+ attribute \src "ls180.v:6003.44-6003.148"
+ cell $and $and$ls180.v:6003$1483
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6007$1481_Y
- connect \B $eq$ls180.v:6007$1482_Y
- connect \Y $and$ls180.v:6007$1483_Y
+ connect \A $and$ls180.v:6003$1481_Y
+ connect \B $eq$ls180.v:6003$1482_Y
+ connect \Y $and$ls180.v:6003$1483_Y
end
- attribute \src "ls180.v:6008.45-6008.101"
- cell $and $and$ls180.v:6008$1485
+ attribute \src "ls180.v:6004.45-6004.101"
+ cell $and $and$ls180.v:6004$1485
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank6_sel
- connect \B $not$ls180.v:6008$1484_Y
- connect \Y $and$ls180.v:6008$1485_Y
+ connect \B $not$ls180.v:6004$1484_Y
+ connect \Y $and$ls180.v:6004$1485_Y
end
- attribute \src "ls180.v:6008.44-6008.151"
- cell $and $and$ls180.v:6008$1487
+ attribute \src "ls180.v:6004.44-6004.151"
+ cell $and $and$ls180.v:6004$1487
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6008$1485_Y
- connect \B $eq$ls180.v:6008$1486_Y
- connect \Y $and$ls180.v:6008$1487_Y
+ connect \A $and$ls180.v:6004$1485_Y
+ connect \B $eq$ls180.v:6004$1486_Y
+ connect \Y $and$ls180.v:6004$1487_Y
end
- attribute \src "ls180.v:6010.45-6010.98"
- cell $and $and$ls180.v:6010$1488
+ attribute \src "ls180.v:6006.45-6006.98"
+ cell $and $and$ls180.v:6006$1488
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank6_sel
connect \B \builder_interface6_bank_bus_we
- connect \Y $and$ls180.v:6010$1488_Y
+ connect \Y $and$ls180.v:6006$1488_Y
end
- attribute \src "ls180.v:6010.44-6010.148"
- cell $and $and$ls180.v:6010$1490
+ attribute \src "ls180.v:6006.44-6006.148"
+ cell $and $and$ls180.v:6006$1490
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6010$1488_Y
- connect \B $eq$ls180.v:6010$1489_Y
- connect \Y $and$ls180.v:6010$1490_Y
+ connect \A $and$ls180.v:6006$1488_Y
+ connect \B $eq$ls180.v:6006$1489_Y
+ connect \Y $and$ls180.v:6006$1490_Y
end
- attribute \src "ls180.v:6011.45-6011.101"
- cell $and $and$ls180.v:6011$1492
+ attribute \src "ls180.v:6007.45-6007.101"
+ cell $and $and$ls180.v:6007$1492
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank6_sel
- connect \B $not$ls180.v:6011$1491_Y
- connect \Y $and$ls180.v:6011$1492_Y
+ connect \B $not$ls180.v:6007$1491_Y
+ connect \Y $and$ls180.v:6007$1492_Y
end
- attribute \src "ls180.v:6011.44-6011.151"
- cell $and $and$ls180.v:6011$1494
+ attribute \src "ls180.v:6007.44-6007.151"
+ cell $and $and$ls180.v:6007$1494
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6011$1492_Y
- connect \B $eq$ls180.v:6011$1493_Y
- connect \Y $and$ls180.v:6011$1494_Y
+ connect \A $and$ls180.v:6007$1492_Y
+ connect \B $eq$ls180.v:6007$1493_Y
+ connect \Y $and$ls180.v:6007$1494_Y
end
- attribute \src "ls180.v:6013.36-6013.89"
- cell $and $and$ls180.v:6013$1495
+ attribute \src "ls180.v:6009.36-6009.89"
+ cell $and $and$ls180.v:6009$1495
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank6_sel
connect \B \builder_interface6_bank_bus_we
- connect \Y $and$ls180.v:6013$1495_Y
+ connect \Y $and$ls180.v:6009$1495_Y
end
- attribute \src "ls180.v:6013.35-6013.139"
- cell $and $and$ls180.v:6013$1497
+ attribute \src "ls180.v:6009.35-6009.139"
+ cell $and $and$ls180.v:6009$1497
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6013$1495_Y
- connect \B $eq$ls180.v:6013$1496_Y
- connect \Y $and$ls180.v:6013$1497_Y
+ connect \A $and$ls180.v:6009$1495_Y
+ connect \B $eq$ls180.v:6009$1496_Y
+ connect \Y $and$ls180.v:6009$1497_Y
end
- attribute \src "ls180.v:6014.36-6014.92"
- cell $and $and$ls180.v:6014$1499
+ attribute \src "ls180.v:6010.36-6010.92"
+ cell $and $and$ls180.v:6010$1499
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank6_sel
- connect \B $not$ls180.v:6014$1498_Y
- connect \Y $and$ls180.v:6014$1499_Y
+ connect \B $not$ls180.v:6010$1498_Y
+ connect \Y $and$ls180.v:6010$1499_Y
end
- attribute \src "ls180.v:6014.35-6014.142"
- cell $and $and$ls180.v:6014$1501
+ attribute \src "ls180.v:6010.35-6010.142"
+ cell $and $and$ls180.v:6010$1501
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6014$1499_Y
- connect \B $eq$ls180.v:6014$1500_Y
- connect \Y $and$ls180.v:6014$1501_Y
+ connect \A $and$ls180.v:6010$1499_Y
+ connect \B $eq$ls180.v:6010$1500_Y
+ connect \Y $and$ls180.v:6010$1501_Y
end
- attribute \src "ls180.v:6016.47-6016.100"
- cell $and $and$ls180.v:6016$1502
+ attribute \src "ls180.v:6012.47-6012.100"
+ cell $and $and$ls180.v:6012$1502
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank6_sel
connect \B \builder_interface6_bank_bus_we
- connect \Y $and$ls180.v:6016$1502_Y
+ connect \Y $and$ls180.v:6012$1502_Y
end
- attribute \src "ls180.v:6016.46-6016.150"
- cell $and $and$ls180.v:6016$1504
+ attribute \src "ls180.v:6012.46-6012.150"
+ cell $and $and$ls180.v:6012$1504
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6016$1502_Y
- connect \B $eq$ls180.v:6016$1503_Y
- connect \Y $and$ls180.v:6016$1504_Y
+ connect \A $and$ls180.v:6012$1502_Y
+ connect \B $eq$ls180.v:6012$1503_Y
+ connect \Y $and$ls180.v:6012$1504_Y
end
- attribute \src "ls180.v:6017.47-6017.103"
- cell $and $and$ls180.v:6017$1506
+ attribute \src "ls180.v:6013.47-6013.103"
+ cell $and $and$ls180.v:6013$1506
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank6_sel
- connect \B $not$ls180.v:6017$1505_Y
- connect \Y $and$ls180.v:6017$1506_Y
+ connect \B $not$ls180.v:6013$1505_Y
+ connect \Y $and$ls180.v:6013$1506_Y
end
- attribute \src "ls180.v:6017.46-6017.153"
- cell $and $and$ls180.v:6017$1508
+ attribute \src "ls180.v:6013.46-6013.153"
+ cell $and $and$ls180.v:6013$1508
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6017$1506_Y
- connect \B $eq$ls180.v:6017$1507_Y
- connect \Y $and$ls180.v:6017$1508_Y
+ connect \A $and$ls180.v:6013$1506_Y
+ connect \B $eq$ls180.v:6013$1507_Y
+ connect \Y $and$ls180.v:6013$1508_Y
end
- attribute \src "ls180.v:6019.47-6019.100"
- cell $and $and$ls180.v:6019$1509
+ attribute \src "ls180.v:6015.47-6015.100"
+ cell $and $and$ls180.v:6015$1509
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank6_sel
connect \B \builder_interface6_bank_bus_we
- connect \Y $and$ls180.v:6019$1509_Y
+ connect \Y $and$ls180.v:6015$1509_Y
end
- attribute \src "ls180.v:6019.46-6019.151"
- cell $and $and$ls180.v:6019$1511
+ attribute \src "ls180.v:6015.46-6015.151"
+ cell $and $and$ls180.v:6015$1511
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6019$1509_Y
- connect \B $eq$ls180.v:6019$1510_Y
- connect \Y $and$ls180.v:6019$1511_Y
+ connect \A $and$ls180.v:6015$1509_Y
+ connect \B $eq$ls180.v:6015$1510_Y
+ connect \Y $and$ls180.v:6015$1511_Y
end
- attribute \src "ls180.v:6020.47-6020.103"
- cell $and $and$ls180.v:6020$1513
+ attribute \src "ls180.v:6016.47-6016.103"
+ cell $and $and$ls180.v:6016$1513
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank6_sel
- connect \B $not$ls180.v:6020$1512_Y
- connect \Y $and$ls180.v:6020$1513_Y
+ connect \B $not$ls180.v:6016$1512_Y
+ connect \Y $and$ls180.v:6016$1513_Y
end
- attribute \src "ls180.v:6020.46-6020.154"
- cell $and $and$ls180.v:6020$1515
+ attribute \src "ls180.v:6016.46-6016.154"
+ cell $and $and$ls180.v:6016$1515
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6020$1513_Y
- connect \B $eq$ls180.v:6020$1514_Y
- connect \Y $and$ls180.v:6020$1515_Y
+ connect \A $and$ls180.v:6016$1513_Y
+ connect \B $eq$ls180.v:6016$1514_Y
+ connect \Y $and$ls180.v:6016$1515_Y
end
- attribute \src "ls180.v:6022.47-6022.100"
- cell $and $and$ls180.v:6022$1516
+ attribute \src "ls180.v:6018.47-6018.100"
+ cell $and $and$ls180.v:6018$1516
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank6_sel
connect \B \builder_interface6_bank_bus_we
- connect \Y $and$ls180.v:6022$1516_Y
+ connect \Y $and$ls180.v:6018$1516_Y
end
- attribute \src "ls180.v:6022.46-6022.151"
- cell $and $and$ls180.v:6022$1518
+ attribute \src "ls180.v:6018.46-6018.151"
+ cell $and $and$ls180.v:6018$1518
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6022$1516_Y
- connect \B $eq$ls180.v:6022$1517_Y
- connect \Y $and$ls180.v:6022$1518_Y
+ connect \A $and$ls180.v:6018$1516_Y
+ connect \B $eq$ls180.v:6018$1517_Y
+ connect \Y $and$ls180.v:6018$1518_Y
end
- attribute \src "ls180.v:6023.47-6023.103"
- cell $and $and$ls180.v:6023$1520
+ attribute \src "ls180.v:6019.47-6019.103"
+ cell $and $and$ls180.v:6019$1520
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank6_sel
- connect \B $not$ls180.v:6023$1519_Y
- connect \Y $and$ls180.v:6023$1520_Y
+ connect \B $not$ls180.v:6019$1519_Y
+ connect \Y $and$ls180.v:6019$1520_Y
end
- attribute \src "ls180.v:6023.46-6023.154"
- cell $and $and$ls180.v:6023$1522
+ attribute \src "ls180.v:6019.46-6019.154"
+ cell $and $and$ls180.v:6019$1522
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6023$1520_Y
- connect \B $eq$ls180.v:6023$1521_Y
- connect \Y $and$ls180.v:6023$1522_Y
+ connect \A $and$ls180.v:6019$1520_Y
+ connect \B $eq$ls180.v:6019$1521_Y
+ connect \Y $and$ls180.v:6019$1522_Y
end
- attribute \src "ls180.v:6025.47-6025.100"
- cell $and $and$ls180.v:6025$1523
+ attribute \src "ls180.v:6021.47-6021.100"
+ cell $and $and$ls180.v:6021$1523
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank6_sel
connect \B \builder_interface6_bank_bus_we
- connect \Y $and$ls180.v:6025$1523_Y
+ connect \Y $and$ls180.v:6021$1523_Y
end
- attribute \src "ls180.v:6025.46-6025.151"
- cell $and $and$ls180.v:6025$1525
+ attribute \src "ls180.v:6021.46-6021.151"
+ cell $and $and$ls180.v:6021$1525
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6025$1523_Y
- connect \B $eq$ls180.v:6025$1524_Y
- connect \Y $and$ls180.v:6025$1525_Y
+ connect \A $and$ls180.v:6021$1523_Y
+ connect \B $eq$ls180.v:6021$1524_Y
+ connect \Y $and$ls180.v:6021$1525_Y
end
- attribute \src "ls180.v:6026.47-6026.103"
- cell $and $and$ls180.v:6026$1527
+ attribute \src "ls180.v:6022.47-6022.103"
+ cell $and $and$ls180.v:6022$1527
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank6_sel
- connect \B $not$ls180.v:6026$1526_Y
- connect \Y $and$ls180.v:6026$1527_Y
+ connect \B $not$ls180.v:6022$1526_Y
+ connect \Y $and$ls180.v:6022$1527_Y
end
- attribute \src "ls180.v:6026.46-6026.154"
- cell $and $and$ls180.v:6026$1529
+ attribute \src "ls180.v:6022.46-6022.154"
+ cell $and $and$ls180.v:6022$1529
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6026$1527_Y
- connect \B $eq$ls180.v:6026$1528_Y
- connect \Y $and$ls180.v:6026$1529_Y
+ connect \A $and$ls180.v:6022$1527_Y
+ connect \B $eq$ls180.v:6022$1528_Y
+ connect \Y $and$ls180.v:6022$1529_Y
end
- attribute \src "ls180.v:6028.47-6028.100"
- cell $and $and$ls180.v:6028$1530
+ attribute \src "ls180.v:6024.47-6024.100"
+ cell $and $and$ls180.v:6024$1530
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank6_sel
connect \B \builder_interface6_bank_bus_we
- connect \Y $and$ls180.v:6028$1530_Y
+ connect \Y $and$ls180.v:6024$1530_Y
end
- attribute \src "ls180.v:6028.46-6028.151"
- cell $and $and$ls180.v:6028$1532
+ attribute \src "ls180.v:6024.46-6024.151"
+ cell $and $and$ls180.v:6024$1532
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6028$1530_Y
- connect \B $eq$ls180.v:6028$1531_Y
- connect \Y $and$ls180.v:6028$1532_Y
+ connect \A $and$ls180.v:6024$1530_Y
+ connect \B $eq$ls180.v:6024$1531_Y
+ connect \Y $and$ls180.v:6024$1532_Y
end
- attribute \src "ls180.v:6029.47-6029.103"
- cell $and $and$ls180.v:6029$1534
+ attribute \src "ls180.v:6025.47-6025.103"
+ cell $and $and$ls180.v:6025$1534
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank6_sel
- connect \B $not$ls180.v:6029$1533_Y
- connect \Y $and$ls180.v:6029$1534_Y
+ connect \B $not$ls180.v:6025$1533_Y
+ connect \Y $and$ls180.v:6025$1534_Y
end
- attribute \src "ls180.v:6029.46-6029.154"
- cell $and $and$ls180.v:6029$1536
+ attribute \src "ls180.v:6025.46-6025.154"
+ cell $and $and$ls180.v:6025$1536
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6029$1534_Y
- connect \B $eq$ls180.v:6029$1535_Y
- connect \Y $and$ls180.v:6029$1536_Y
+ connect \A $and$ls180.v:6025$1534_Y
+ connect \B $eq$ls180.v:6025$1535_Y
+ connect \Y $and$ls180.v:6025$1536_Y
end
- attribute \src "ls180.v:6031.47-6031.100"
- cell $and $and$ls180.v:6031$1537
+ attribute \src "ls180.v:6027.47-6027.100"
+ cell $and $and$ls180.v:6027$1537
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank6_sel
connect \B \builder_interface6_bank_bus_we
- connect \Y $and$ls180.v:6031$1537_Y
+ connect \Y $and$ls180.v:6027$1537_Y
end
- attribute \src "ls180.v:6031.46-6031.151"
- cell $and $and$ls180.v:6031$1539
+ attribute \src "ls180.v:6027.46-6027.151"
+ cell $and $and$ls180.v:6027$1539
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6031$1537_Y
- connect \B $eq$ls180.v:6031$1538_Y
- connect \Y $and$ls180.v:6031$1539_Y
+ connect \A $and$ls180.v:6027$1537_Y
+ connect \B $eq$ls180.v:6027$1538_Y
+ connect \Y $and$ls180.v:6027$1539_Y
end
- attribute \src "ls180.v:6032.47-6032.103"
- cell $and $and$ls180.v:6032$1541
+ attribute \src "ls180.v:6028.47-6028.103"
+ cell $and $and$ls180.v:6028$1541
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank6_sel
- connect \B $not$ls180.v:6032$1540_Y
- connect \Y $and$ls180.v:6032$1541_Y
+ connect \B $not$ls180.v:6028$1540_Y
+ connect \Y $and$ls180.v:6028$1541_Y
end
- attribute \src "ls180.v:6032.46-6032.154"
- cell $and $and$ls180.v:6032$1543
+ attribute \src "ls180.v:6028.46-6028.154"
+ cell $and $and$ls180.v:6028$1543
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6032$1541_Y
- connect \B $eq$ls180.v:6032$1542_Y
- connect \Y $and$ls180.v:6032$1543_Y
+ connect \A $and$ls180.v:6028$1541_Y
+ connect \B $eq$ls180.v:6028$1542_Y
+ connect \Y $and$ls180.v:6028$1543_Y
end
- attribute \src "ls180.v:6034.46-6034.99"
- cell $and $and$ls180.v:6034$1544
+ attribute \src "ls180.v:6030.46-6030.99"
+ cell $and $and$ls180.v:6030$1544
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank6_sel
connect \B \builder_interface6_bank_bus_we
- connect \Y $and$ls180.v:6034$1544_Y
+ connect \Y $and$ls180.v:6030$1544_Y
end
- attribute \src "ls180.v:6034.45-6034.150"
- cell $and $and$ls180.v:6034$1546
+ attribute \src "ls180.v:6030.45-6030.150"
+ cell $and $and$ls180.v:6030$1546
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6034$1544_Y
- connect \B $eq$ls180.v:6034$1545_Y
- connect \Y $and$ls180.v:6034$1546_Y
+ connect \A $and$ls180.v:6030$1544_Y
+ connect \B $eq$ls180.v:6030$1545_Y
+ connect \Y $and$ls180.v:6030$1546_Y
end
- attribute \src "ls180.v:6035.46-6035.102"
- cell $and $and$ls180.v:6035$1548
+ attribute \src "ls180.v:6031.46-6031.102"
+ cell $and $and$ls180.v:6031$1548
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank6_sel
- connect \B $not$ls180.v:6035$1547_Y
- connect \Y $and$ls180.v:6035$1548_Y
+ connect \B $not$ls180.v:6031$1547_Y
+ connect \Y $and$ls180.v:6031$1548_Y
end
- attribute \src "ls180.v:6035.45-6035.153"
- cell $and $and$ls180.v:6035$1550
+ attribute \src "ls180.v:6031.45-6031.153"
+ cell $and $and$ls180.v:6031$1550
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6035$1548_Y
- connect \B $eq$ls180.v:6035$1549_Y
- connect \Y $and$ls180.v:6035$1550_Y
+ connect \A $and$ls180.v:6031$1548_Y
+ connect \B $eq$ls180.v:6031$1549_Y
+ connect \Y $and$ls180.v:6031$1550_Y
end
- attribute \src "ls180.v:6037.46-6037.99"
- cell $and $and$ls180.v:6037$1551
+ attribute \src "ls180.v:6033.46-6033.99"
+ cell $and $and$ls180.v:6033$1551
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank6_sel
connect \B \builder_interface6_bank_bus_we
- connect \Y $and$ls180.v:6037$1551_Y
+ connect \Y $and$ls180.v:6033$1551_Y
end
- attribute \src "ls180.v:6037.45-6037.150"
- cell $and $and$ls180.v:6037$1553
+ attribute \src "ls180.v:6033.45-6033.150"
+ cell $and $and$ls180.v:6033$1553
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6037$1551_Y
- connect \B $eq$ls180.v:6037$1552_Y
- connect \Y $and$ls180.v:6037$1553_Y
+ connect \A $and$ls180.v:6033$1551_Y
+ connect \B $eq$ls180.v:6033$1552_Y
+ connect \Y $and$ls180.v:6033$1553_Y
end
- attribute \src "ls180.v:6038.46-6038.102"
- cell $and $and$ls180.v:6038$1555
+ attribute \src "ls180.v:6034.46-6034.102"
+ cell $and $and$ls180.v:6034$1555
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank6_sel
- connect \B $not$ls180.v:6038$1554_Y
- connect \Y $and$ls180.v:6038$1555_Y
+ connect \B $not$ls180.v:6034$1554_Y
+ connect \Y $and$ls180.v:6034$1555_Y
end
- attribute \src "ls180.v:6038.45-6038.153"
- cell $and $and$ls180.v:6038$1557
+ attribute \src "ls180.v:6034.45-6034.153"
+ cell $and $and$ls180.v:6034$1557
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6038$1555_Y
- connect \B $eq$ls180.v:6038$1556_Y
- connect \Y $and$ls180.v:6038$1557_Y
+ connect \A $and$ls180.v:6034$1555_Y
+ connect \B $eq$ls180.v:6034$1556_Y
+ connect \Y $and$ls180.v:6034$1557_Y
end
- attribute \src "ls180.v:6040.46-6040.99"
- cell $and $and$ls180.v:6040$1558
+ attribute \src "ls180.v:6036.46-6036.99"
+ cell $and $and$ls180.v:6036$1558
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank6_sel
connect \B \builder_interface6_bank_bus_we
- connect \Y $and$ls180.v:6040$1558_Y
+ connect \Y $and$ls180.v:6036$1558_Y
end
- attribute \src "ls180.v:6040.45-6040.150"
- cell $and $and$ls180.v:6040$1560
+ attribute \src "ls180.v:6036.45-6036.150"
+ cell $and $and$ls180.v:6036$1560
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6040$1558_Y
- connect \B $eq$ls180.v:6040$1559_Y
- connect \Y $and$ls180.v:6040$1560_Y
+ connect \A $and$ls180.v:6036$1558_Y
+ connect \B $eq$ls180.v:6036$1559_Y
+ connect \Y $and$ls180.v:6036$1560_Y
end
- attribute \src "ls180.v:6041.46-6041.102"
- cell $and $and$ls180.v:6041$1562
+ attribute \src "ls180.v:6037.46-6037.102"
+ cell $and $and$ls180.v:6037$1562
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank6_sel
- connect \B $not$ls180.v:6041$1561_Y
- connect \Y $and$ls180.v:6041$1562_Y
+ connect \B $not$ls180.v:6037$1561_Y
+ connect \Y $and$ls180.v:6037$1562_Y
end
- attribute \src "ls180.v:6041.45-6041.153"
- cell $and $and$ls180.v:6041$1564
+ attribute \src "ls180.v:6037.45-6037.153"
+ cell $and $and$ls180.v:6037$1564
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6041$1562_Y
- connect \B $eq$ls180.v:6041$1563_Y
- connect \Y $and$ls180.v:6041$1564_Y
+ connect \A $and$ls180.v:6037$1562_Y
+ connect \B $eq$ls180.v:6037$1563_Y
+ connect \Y $and$ls180.v:6037$1564_Y
end
- attribute \src "ls180.v:6043.46-6043.99"
- cell $and $and$ls180.v:6043$1565
+ attribute \src "ls180.v:6039.46-6039.99"
+ cell $and $and$ls180.v:6039$1565
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank6_sel
connect \B \builder_interface6_bank_bus_we
- connect \Y $and$ls180.v:6043$1565_Y
+ connect \Y $and$ls180.v:6039$1565_Y
end
- attribute \src "ls180.v:6043.45-6043.150"
- cell $and $and$ls180.v:6043$1567
+ attribute \src "ls180.v:6039.45-6039.150"
+ cell $and $and$ls180.v:6039$1567
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6043$1565_Y
- connect \B $eq$ls180.v:6043$1566_Y
- connect \Y $and$ls180.v:6043$1567_Y
+ connect \A $and$ls180.v:6039$1565_Y
+ connect \B $eq$ls180.v:6039$1566_Y
+ connect \Y $and$ls180.v:6039$1567_Y
end
- attribute \src "ls180.v:6044.46-6044.102"
- cell $and $and$ls180.v:6044$1569
+ attribute \src "ls180.v:6040.46-6040.102"
+ cell $and $and$ls180.v:6040$1569
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank6_sel
- connect \B $not$ls180.v:6044$1568_Y
- connect \Y $and$ls180.v:6044$1569_Y
+ connect \B $not$ls180.v:6040$1568_Y
+ connect \Y $and$ls180.v:6040$1569_Y
end
- attribute \src "ls180.v:6044.45-6044.153"
- cell $and $and$ls180.v:6044$1571
+ attribute \src "ls180.v:6040.45-6040.153"
+ cell $and $and$ls180.v:6040$1571
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6044$1569_Y
- connect \B $eq$ls180.v:6044$1570_Y
- connect \Y $and$ls180.v:6044$1571_Y
+ connect \A $and$ls180.v:6040$1569_Y
+ connect \B $eq$ls180.v:6040$1570_Y
+ connect \Y $and$ls180.v:6040$1571_Y
end
- attribute \src "ls180.v:6046.46-6046.99"
- cell $and $and$ls180.v:6046$1572
+ attribute \src "ls180.v:6042.46-6042.99"
+ cell $and $and$ls180.v:6042$1572
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank6_sel
connect \B \builder_interface6_bank_bus_we
- connect \Y $and$ls180.v:6046$1572_Y
+ connect \Y $and$ls180.v:6042$1572_Y
end
- attribute \src "ls180.v:6046.45-6046.150"
- cell $and $and$ls180.v:6046$1574
+ attribute \src "ls180.v:6042.45-6042.150"
+ cell $and $and$ls180.v:6042$1574
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6046$1572_Y
- connect \B $eq$ls180.v:6046$1573_Y
- connect \Y $and$ls180.v:6046$1574_Y
+ connect \A $and$ls180.v:6042$1572_Y
+ connect \B $eq$ls180.v:6042$1573_Y
+ connect \Y $and$ls180.v:6042$1574_Y
end
- attribute \src "ls180.v:6047.46-6047.102"
- cell $and $and$ls180.v:6047$1576
+ attribute \src "ls180.v:6043.46-6043.102"
+ cell $and $and$ls180.v:6043$1576
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank6_sel
- connect \B $not$ls180.v:6047$1575_Y
- connect \Y $and$ls180.v:6047$1576_Y
+ connect \B $not$ls180.v:6043$1575_Y
+ connect \Y $and$ls180.v:6043$1576_Y
end
- attribute \src "ls180.v:6047.45-6047.153"
- cell $and $and$ls180.v:6047$1578
+ attribute \src "ls180.v:6043.45-6043.153"
+ cell $and $and$ls180.v:6043$1578
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6047$1576_Y
- connect \B $eq$ls180.v:6047$1577_Y
- connect \Y $and$ls180.v:6047$1578_Y
+ connect \A $and$ls180.v:6043$1576_Y
+ connect \B $eq$ls180.v:6043$1577_Y
+ connect \Y $and$ls180.v:6043$1578_Y
end
- attribute \src "ls180.v:6049.46-6049.99"
- cell $and $and$ls180.v:6049$1579
+ attribute \src "ls180.v:6045.46-6045.99"
+ cell $and $and$ls180.v:6045$1579
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank6_sel
connect \B \builder_interface6_bank_bus_we
- connect \Y $and$ls180.v:6049$1579_Y
+ connect \Y $and$ls180.v:6045$1579_Y
end
- attribute \src "ls180.v:6049.45-6049.150"
- cell $and $and$ls180.v:6049$1581
+ attribute \src "ls180.v:6045.45-6045.150"
+ cell $and $and$ls180.v:6045$1581
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6049$1579_Y
- connect \B $eq$ls180.v:6049$1580_Y
- connect \Y $and$ls180.v:6049$1581_Y
+ connect \A $and$ls180.v:6045$1579_Y
+ connect \B $eq$ls180.v:6045$1580_Y
+ connect \Y $and$ls180.v:6045$1581_Y
end
- attribute \src "ls180.v:6050.46-6050.102"
- cell $and $and$ls180.v:6050$1583
+ attribute \src "ls180.v:6046.46-6046.102"
+ cell $and $and$ls180.v:6046$1583
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank6_sel
- connect \B $not$ls180.v:6050$1582_Y
- connect \Y $and$ls180.v:6050$1583_Y
+ connect \B $not$ls180.v:6046$1582_Y
+ connect \Y $and$ls180.v:6046$1583_Y
end
- attribute \src "ls180.v:6050.45-6050.153"
- cell $and $and$ls180.v:6050$1585
+ attribute \src "ls180.v:6046.45-6046.153"
+ cell $and $and$ls180.v:6046$1585
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6050$1583_Y
- connect \B $eq$ls180.v:6050$1584_Y
- connect \Y $and$ls180.v:6050$1585_Y
+ connect \A $and$ls180.v:6046$1583_Y
+ connect \B $eq$ls180.v:6046$1584_Y
+ connect \Y $and$ls180.v:6046$1585_Y
end
- attribute \src "ls180.v:6052.46-6052.99"
- cell $and $and$ls180.v:6052$1586
+ attribute \src "ls180.v:6048.46-6048.99"
+ cell $and $and$ls180.v:6048$1586
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank6_sel
connect \B \builder_interface6_bank_bus_we
- connect \Y $and$ls180.v:6052$1586_Y
+ connect \Y $and$ls180.v:6048$1586_Y
end
- attribute \src "ls180.v:6052.45-6052.150"
- cell $and $and$ls180.v:6052$1588
+ attribute \src "ls180.v:6048.45-6048.150"
+ cell $and $and$ls180.v:6048$1588
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6052$1586_Y
- connect \B $eq$ls180.v:6052$1587_Y
- connect \Y $and$ls180.v:6052$1588_Y
+ connect \A $and$ls180.v:6048$1586_Y
+ connect \B $eq$ls180.v:6048$1587_Y
+ connect \Y $and$ls180.v:6048$1588_Y
end
- attribute \src "ls180.v:6053.46-6053.102"
- cell $and $and$ls180.v:6053$1590
+ attribute \src "ls180.v:6049.46-6049.102"
+ cell $and $and$ls180.v:6049$1590
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank6_sel
- connect \B $not$ls180.v:6053$1589_Y
- connect \Y $and$ls180.v:6053$1590_Y
+ connect \B $not$ls180.v:6049$1589_Y
+ connect \Y $and$ls180.v:6049$1590_Y
end
- attribute \src "ls180.v:6053.45-6053.153"
- cell $and $and$ls180.v:6053$1592
+ attribute \src "ls180.v:6049.45-6049.153"
+ cell $and $and$ls180.v:6049$1592
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6053$1590_Y
- connect \B $eq$ls180.v:6053$1591_Y
- connect \Y $and$ls180.v:6053$1592_Y
+ connect \A $and$ls180.v:6049$1590_Y
+ connect \B $eq$ls180.v:6049$1591_Y
+ connect \Y $and$ls180.v:6049$1592_Y
end
- attribute \src "ls180.v:6055.46-6055.99"
- cell $and $and$ls180.v:6055$1593
+ attribute \src "ls180.v:6051.46-6051.99"
+ cell $and $and$ls180.v:6051$1593
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank6_sel
connect \B \builder_interface6_bank_bus_we
- connect \Y $and$ls180.v:6055$1593_Y
+ connect \Y $and$ls180.v:6051$1593_Y
end
- attribute \src "ls180.v:6055.45-6055.150"
- cell $and $and$ls180.v:6055$1595
+ attribute \src "ls180.v:6051.45-6051.150"
+ cell $and $and$ls180.v:6051$1595
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6055$1593_Y
- connect \B $eq$ls180.v:6055$1594_Y
- connect \Y $and$ls180.v:6055$1595_Y
+ connect \A $and$ls180.v:6051$1593_Y
+ connect \B $eq$ls180.v:6051$1594_Y
+ connect \Y $and$ls180.v:6051$1595_Y
end
- attribute \src "ls180.v:6056.46-6056.102"
- cell $and $and$ls180.v:6056$1597
+ attribute \src "ls180.v:6052.46-6052.102"
+ cell $and $and$ls180.v:6052$1597
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank6_sel
- connect \B $not$ls180.v:6056$1596_Y
- connect \Y $and$ls180.v:6056$1597_Y
+ connect \B $not$ls180.v:6052$1596_Y
+ connect \Y $and$ls180.v:6052$1597_Y
end
- attribute \src "ls180.v:6056.45-6056.153"
- cell $and $and$ls180.v:6056$1599
+ attribute \src "ls180.v:6052.45-6052.153"
+ cell $and $and$ls180.v:6052$1599
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6056$1597_Y
- connect \B $eq$ls180.v:6056$1598_Y
- connect \Y $and$ls180.v:6056$1599_Y
+ connect \A $and$ls180.v:6052$1597_Y
+ connect \B $eq$ls180.v:6052$1598_Y
+ connect \Y $and$ls180.v:6052$1599_Y
end
- attribute \src "ls180.v:6058.46-6058.99"
- cell $and $and$ls180.v:6058$1600
+ attribute \src "ls180.v:6054.46-6054.99"
+ cell $and $and$ls180.v:6054$1600
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank6_sel
connect \B \builder_interface6_bank_bus_we
- connect \Y $and$ls180.v:6058$1600_Y
+ connect \Y $and$ls180.v:6054$1600_Y
end
- attribute \src "ls180.v:6058.45-6058.150"
- cell $and $and$ls180.v:6058$1602
+ attribute \src "ls180.v:6054.45-6054.150"
+ cell $and $and$ls180.v:6054$1602
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6058$1600_Y
- connect \B $eq$ls180.v:6058$1601_Y
- connect \Y $and$ls180.v:6058$1602_Y
+ connect \A $and$ls180.v:6054$1600_Y
+ connect \B $eq$ls180.v:6054$1601_Y
+ connect \Y $and$ls180.v:6054$1602_Y
end
- attribute \src "ls180.v:6059.46-6059.102"
- cell $and $and$ls180.v:6059$1604
+ attribute \src "ls180.v:6055.46-6055.102"
+ cell $and $and$ls180.v:6055$1604
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank6_sel
- connect \B $not$ls180.v:6059$1603_Y
- connect \Y $and$ls180.v:6059$1604_Y
+ connect \B $not$ls180.v:6055$1603_Y
+ connect \Y $and$ls180.v:6055$1604_Y
end
- attribute \src "ls180.v:6059.45-6059.153"
- cell $and $and$ls180.v:6059$1606
+ attribute \src "ls180.v:6055.45-6055.153"
+ cell $and $and$ls180.v:6055$1606
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6059$1604_Y
- connect \B $eq$ls180.v:6059$1605_Y
- connect \Y $and$ls180.v:6059$1606_Y
+ connect \A $and$ls180.v:6055$1604_Y
+ connect \B $eq$ls180.v:6055$1605_Y
+ connect \Y $and$ls180.v:6055$1606_Y
end
- attribute \src "ls180.v:6061.46-6061.99"
- cell $and $and$ls180.v:6061$1607
+ attribute \src "ls180.v:6057.46-6057.99"
+ cell $and $and$ls180.v:6057$1607
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank6_sel
connect \B \builder_interface6_bank_bus_we
- connect \Y $and$ls180.v:6061$1607_Y
+ connect \Y $and$ls180.v:6057$1607_Y
end
- attribute \src "ls180.v:6061.45-6061.150"
- cell $and $and$ls180.v:6061$1609
+ attribute \src "ls180.v:6057.45-6057.150"
+ cell $and $and$ls180.v:6057$1609
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6061$1607_Y
- connect \B $eq$ls180.v:6061$1608_Y
- connect \Y $and$ls180.v:6061$1609_Y
+ connect \A $and$ls180.v:6057$1607_Y
+ connect \B $eq$ls180.v:6057$1608_Y
+ connect \Y $and$ls180.v:6057$1609_Y
end
- attribute \src "ls180.v:6062.46-6062.102"
- cell $and $and$ls180.v:6062$1611
+ attribute \src "ls180.v:6058.46-6058.102"
+ cell $and $and$ls180.v:6058$1611
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank6_sel
- connect \B $not$ls180.v:6062$1610_Y
- connect \Y $and$ls180.v:6062$1611_Y
+ connect \B $not$ls180.v:6058$1610_Y
+ connect \Y $and$ls180.v:6058$1611_Y
end
- attribute \src "ls180.v:6062.45-6062.153"
- cell $and $and$ls180.v:6062$1613
+ attribute \src "ls180.v:6058.45-6058.153"
+ cell $and $and$ls180.v:6058$1613
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6062$1611_Y
- connect \B $eq$ls180.v:6062$1612_Y
- connect \Y $and$ls180.v:6062$1613_Y
+ connect \A $and$ls180.v:6058$1611_Y
+ connect \B $eq$ls180.v:6058$1612_Y
+ connect \Y $and$ls180.v:6058$1613_Y
end
- attribute \src "ls180.v:6064.42-6064.95"
- cell $and $and$ls180.v:6064$1614
+ attribute \src "ls180.v:6060.42-6060.95"
+ cell $and $and$ls180.v:6060$1614
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank6_sel
connect \B \builder_interface6_bank_bus_we
- connect \Y $and$ls180.v:6064$1614_Y
+ connect \Y $and$ls180.v:6060$1614_Y
end
- attribute \src "ls180.v:6064.41-6064.146"
- cell $and $and$ls180.v:6064$1616
+ attribute \src "ls180.v:6060.41-6060.146"
+ cell $and $and$ls180.v:6060$1616
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6064$1614_Y
- connect \B $eq$ls180.v:6064$1615_Y
- connect \Y $and$ls180.v:6064$1616_Y
+ connect \A $and$ls180.v:6060$1614_Y
+ connect \B $eq$ls180.v:6060$1615_Y
+ connect \Y $and$ls180.v:6060$1616_Y
end
- attribute \src "ls180.v:6065.42-6065.98"
- cell $and $and$ls180.v:6065$1618
+ attribute \src "ls180.v:6061.42-6061.98"
+ cell $and $and$ls180.v:6061$1618
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank6_sel
- connect \B $not$ls180.v:6065$1617_Y
- connect \Y $and$ls180.v:6065$1618_Y
+ connect \B $not$ls180.v:6061$1617_Y
+ connect \Y $and$ls180.v:6061$1618_Y
end
- attribute \src "ls180.v:6065.41-6065.149"
- cell $and $and$ls180.v:6065$1620
+ attribute \src "ls180.v:6061.41-6061.149"
+ cell $and $and$ls180.v:6061$1620
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6065$1618_Y
- connect \B $eq$ls180.v:6065$1619_Y
- connect \Y $and$ls180.v:6065$1620_Y
+ connect \A $and$ls180.v:6061$1618_Y
+ connect \B $eq$ls180.v:6061$1619_Y
+ connect \Y $and$ls180.v:6061$1620_Y
end
- attribute \src "ls180.v:6067.43-6067.96"
- cell $and $and$ls180.v:6067$1621
+ attribute \src "ls180.v:6063.43-6063.96"
+ cell $and $and$ls180.v:6063$1621
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank6_sel
connect \B \builder_interface6_bank_bus_we
- connect \Y $and$ls180.v:6067$1621_Y
+ connect \Y $and$ls180.v:6063$1621_Y
end
- attribute \src "ls180.v:6067.42-6067.147"
- cell $and $and$ls180.v:6067$1623
+ attribute \src "ls180.v:6063.42-6063.147"
+ cell $and $and$ls180.v:6063$1623
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6067$1621_Y
- connect \B $eq$ls180.v:6067$1622_Y
- connect \Y $and$ls180.v:6067$1623_Y
+ connect \A $and$ls180.v:6063$1621_Y
+ connect \B $eq$ls180.v:6063$1622_Y
+ connect \Y $and$ls180.v:6063$1623_Y
end
- attribute \src "ls180.v:6068.43-6068.99"
- cell $and $and$ls180.v:6068$1625
+ attribute \src "ls180.v:6064.43-6064.99"
+ cell $and $and$ls180.v:6064$1625
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank6_sel
- connect \B $not$ls180.v:6068$1624_Y
- connect \Y $and$ls180.v:6068$1625_Y
+ connect \B $not$ls180.v:6064$1624_Y
+ connect \Y $and$ls180.v:6064$1625_Y
end
- attribute \src "ls180.v:6068.42-6068.150"
- cell $and $and$ls180.v:6068$1627
+ attribute \src "ls180.v:6064.42-6064.150"
+ cell $and $and$ls180.v:6064$1627
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6068$1625_Y
- connect \B $eq$ls180.v:6068$1626_Y
- connect \Y $and$ls180.v:6068$1627_Y
+ connect \A $and$ls180.v:6064$1625_Y
+ connect \B $eq$ls180.v:6064$1626_Y
+ connect \Y $and$ls180.v:6064$1627_Y
end
- attribute \src "ls180.v:6070.46-6070.99"
- cell $and $and$ls180.v:6070$1628
+ attribute \src "ls180.v:6066.46-6066.99"
+ cell $and $and$ls180.v:6066$1628
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank6_sel
connect \B \builder_interface6_bank_bus_we
- connect \Y $and$ls180.v:6070$1628_Y
+ connect \Y $and$ls180.v:6066$1628_Y
end
- attribute \src "ls180.v:6070.45-6070.150"
- cell $and $and$ls180.v:6070$1630
+ attribute \src "ls180.v:6066.45-6066.150"
+ cell $and $and$ls180.v:6066$1630
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6070$1628_Y
- connect \B $eq$ls180.v:6070$1629_Y
- connect \Y $and$ls180.v:6070$1630_Y
+ connect \A $and$ls180.v:6066$1628_Y
+ connect \B $eq$ls180.v:6066$1629_Y
+ connect \Y $and$ls180.v:6066$1630_Y
end
- attribute \src "ls180.v:6071.46-6071.102"
- cell $and $and$ls180.v:6071$1632
+ attribute \src "ls180.v:6067.46-6067.102"
+ cell $and $and$ls180.v:6067$1632
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank6_sel
- connect \B $not$ls180.v:6071$1631_Y
- connect \Y $and$ls180.v:6071$1632_Y
+ connect \B $not$ls180.v:6067$1631_Y
+ connect \Y $and$ls180.v:6067$1632_Y
end
- attribute \src "ls180.v:6071.45-6071.153"
- cell $and $and$ls180.v:6071$1634
+ attribute \src "ls180.v:6067.45-6067.153"
+ cell $and $and$ls180.v:6067$1634
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6071$1632_Y
- connect \B $eq$ls180.v:6071$1633_Y
- connect \Y $and$ls180.v:6071$1634_Y
+ connect \A $and$ls180.v:6067$1632_Y
+ connect \B $eq$ls180.v:6067$1633_Y
+ connect \Y $and$ls180.v:6067$1634_Y
end
- attribute \src "ls180.v:6073.46-6073.99"
- cell $and $and$ls180.v:6073$1635
+ attribute \src "ls180.v:6069.46-6069.99"
+ cell $and $and$ls180.v:6069$1635
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank6_sel
connect \B \builder_interface6_bank_bus_we
- connect \Y $and$ls180.v:6073$1635_Y
+ connect \Y $and$ls180.v:6069$1635_Y
end
- attribute \src "ls180.v:6073.45-6073.150"
- cell $and $and$ls180.v:6073$1637
+ attribute \src "ls180.v:6069.45-6069.150"
+ cell $and $and$ls180.v:6069$1637
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6073$1635_Y
- connect \B $eq$ls180.v:6073$1636_Y
- connect \Y $and$ls180.v:6073$1637_Y
+ connect \A $and$ls180.v:6069$1635_Y
+ connect \B $eq$ls180.v:6069$1636_Y
+ connect \Y $and$ls180.v:6069$1637_Y
end
- attribute \src "ls180.v:6074.46-6074.102"
- cell $and $and$ls180.v:6074$1639
+ attribute \src "ls180.v:6070.46-6070.102"
+ cell $and $and$ls180.v:6070$1639
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank6_sel
- connect \B $not$ls180.v:6074$1638_Y
- connect \Y $and$ls180.v:6074$1639_Y
+ connect \B $not$ls180.v:6070$1638_Y
+ connect \Y $and$ls180.v:6070$1639_Y
end
- attribute \src "ls180.v:6074.45-6074.153"
- cell $and $and$ls180.v:6074$1641
+ attribute \src "ls180.v:6070.45-6070.153"
+ cell $and $and$ls180.v:6070$1641
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6074$1639_Y
- connect \B $eq$ls180.v:6074$1640_Y
- connect \Y $and$ls180.v:6074$1641_Y
+ connect \A $and$ls180.v:6070$1639_Y
+ connect \B $eq$ls180.v:6070$1640_Y
+ connect \Y $and$ls180.v:6070$1641_Y
end
- attribute \src "ls180.v:6076.45-6076.98"
- cell $and $and$ls180.v:6076$1642
+ attribute \src "ls180.v:6072.45-6072.98"
+ cell $and $and$ls180.v:6072$1642
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank6_sel
connect \B \builder_interface6_bank_bus_we
- connect \Y $and$ls180.v:6076$1642_Y
+ connect \Y $and$ls180.v:6072$1642_Y
end
- attribute \src "ls180.v:6076.44-6076.149"
- cell $and $and$ls180.v:6076$1644
+ attribute \src "ls180.v:6072.44-6072.149"
+ cell $and $and$ls180.v:6072$1644
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6076$1642_Y
- connect \B $eq$ls180.v:6076$1643_Y
- connect \Y $and$ls180.v:6076$1644_Y
+ connect \A $and$ls180.v:6072$1642_Y
+ connect \B $eq$ls180.v:6072$1643_Y
+ connect \Y $and$ls180.v:6072$1644_Y
end
- attribute \src "ls180.v:6077.45-6077.101"
- cell $and $and$ls180.v:6077$1646
+ attribute \src "ls180.v:6073.45-6073.101"
+ cell $and $and$ls180.v:6073$1646
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank6_sel
- connect \B $not$ls180.v:6077$1645_Y
- connect \Y $and$ls180.v:6077$1646_Y
+ connect \B $not$ls180.v:6073$1645_Y
+ connect \Y $and$ls180.v:6073$1646_Y
end
- attribute \src "ls180.v:6077.44-6077.152"
- cell $and $and$ls180.v:6077$1648
+ attribute \src "ls180.v:6073.44-6073.152"
+ cell $and $and$ls180.v:6073$1648
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6077$1646_Y
- connect \B $eq$ls180.v:6077$1647_Y
- connect \Y $and$ls180.v:6077$1648_Y
+ connect \A $and$ls180.v:6073$1646_Y
+ connect \B $eq$ls180.v:6073$1647_Y
+ connect \Y $and$ls180.v:6073$1648_Y
end
- attribute \src "ls180.v:6079.45-6079.98"
- cell $and $and$ls180.v:6079$1649
+ attribute \src "ls180.v:6075.45-6075.98"
+ cell $and $and$ls180.v:6075$1649
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank6_sel
connect \B \builder_interface6_bank_bus_we
- connect \Y $and$ls180.v:6079$1649_Y
+ connect \Y $and$ls180.v:6075$1649_Y
end
- attribute \src "ls180.v:6079.44-6079.149"
- cell $and $and$ls180.v:6079$1651
+ attribute \src "ls180.v:6075.44-6075.149"
+ cell $and $and$ls180.v:6075$1651
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6079$1649_Y
- connect \B $eq$ls180.v:6079$1650_Y
- connect \Y $and$ls180.v:6079$1651_Y
+ connect \A $and$ls180.v:6075$1649_Y
+ connect \B $eq$ls180.v:6075$1650_Y
+ connect \Y $and$ls180.v:6075$1651_Y
end
- attribute \src "ls180.v:6080.45-6080.101"
- cell $and $and$ls180.v:6080$1653
+ attribute \src "ls180.v:6076.45-6076.101"
+ cell $and $and$ls180.v:6076$1653
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank6_sel
- connect \B $not$ls180.v:6080$1652_Y
- connect \Y $and$ls180.v:6080$1653_Y
+ connect \B $not$ls180.v:6076$1652_Y
+ connect \Y $and$ls180.v:6076$1653_Y
end
- attribute \src "ls180.v:6080.44-6080.152"
- cell $and $and$ls180.v:6080$1655
+ attribute \src "ls180.v:6076.44-6076.152"
+ cell $and $and$ls180.v:6076$1655
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6080$1653_Y
- connect \B $eq$ls180.v:6080$1654_Y
- connect \Y $and$ls180.v:6080$1655_Y
+ connect \A $and$ls180.v:6076$1653_Y
+ connect \B $eq$ls180.v:6076$1654_Y
+ connect \Y $and$ls180.v:6076$1655_Y
end
- attribute \src "ls180.v:6082.45-6082.98"
- cell $and $and$ls180.v:6082$1656
+ attribute \src "ls180.v:6078.45-6078.98"
+ cell $and $and$ls180.v:6078$1656
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank6_sel
connect \B \builder_interface6_bank_bus_we
- connect \Y $and$ls180.v:6082$1656_Y
+ connect \Y $and$ls180.v:6078$1656_Y
end
- attribute \src "ls180.v:6082.44-6082.149"
- cell $and $and$ls180.v:6082$1658
+ attribute \src "ls180.v:6078.44-6078.149"
+ cell $and $and$ls180.v:6078$1658
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6082$1656_Y
- connect \B $eq$ls180.v:6082$1657_Y
- connect \Y $and$ls180.v:6082$1658_Y
+ connect \A $and$ls180.v:6078$1656_Y
+ connect \B $eq$ls180.v:6078$1657_Y
+ connect \Y $and$ls180.v:6078$1658_Y
end
- attribute \src "ls180.v:6083.45-6083.101"
- cell $and $and$ls180.v:6083$1660
+ attribute \src "ls180.v:6079.45-6079.101"
+ cell $and $and$ls180.v:6079$1660
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank6_sel
- connect \B $not$ls180.v:6083$1659_Y
- connect \Y $and$ls180.v:6083$1660_Y
+ connect \B $not$ls180.v:6079$1659_Y
+ connect \Y $and$ls180.v:6079$1660_Y
end
- attribute \src "ls180.v:6083.44-6083.152"
- cell $and $and$ls180.v:6083$1662
+ attribute \src "ls180.v:6079.44-6079.152"
+ cell $and $and$ls180.v:6079$1662
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6083$1660_Y
- connect \B $eq$ls180.v:6083$1661_Y
- connect \Y $and$ls180.v:6083$1662_Y
+ connect \A $and$ls180.v:6079$1660_Y
+ connect \B $eq$ls180.v:6079$1661_Y
+ connect \Y $and$ls180.v:6079$1662_Y
end
- attribute \src "ls180.v:6085.45-6085.98"
- cell $and $and$ls180.v:6085$1663
+ attribute \src "ls180.v:6081.45-6081.98"
+ cell $and $and$ls180.v:6081$1663
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank6_sel
connect \B \builder_interface6_bank_bus_we
- connect \Y $and$ls180.v:6085$1663_Y
+ connect \Y $and$ls180.v:6081$1663_Y
end
- attribute \src "ls180.v:6085.44-6085.149"
- cell $and $and$ls180.v:6085$1665
+ attribute \src "ls180.v:6081.44-6081.149"
+ cell $and $and$ls180.v:6081$1665
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6085$1663_Y
- connect \B $eq$ls180.v:6085$1664_Y
- connect \Y $and$ls180.v:6085$1665_Y
+ connect \A $and$ls180.v:6081$1663_Y
+ connect \B $eq$ls180.v:6081$1664_Y
+ connect \Y $and$ls180.v:6081$1665_Y
end
- attribute \src "ls180.v:6086.45-6086.101"
- cell $and $and$ls180.v:6086$1667
+ attribute \src "ls180.v:6082.45-6082.101"
+ cell $and $and$ls180.v:6082$1667
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank6_sel
- connect \B $not$ls180.v:6086$1666_Y
- connect \Y $and$ls180.v:6086$1667_Y
+ connect \B $not$ls180.v:6082$1666_Y
+ connect \Y $and$ls180.v:6082$1667_Y
end
- attribute \src "ls180.v:6086.44-6086.152"
- cell $and $and$ls180.v:6086$1669
+ attribute \src "ls180.v:6082.44-6082.152"
+ cell $and $and$ls180.v:6082$1669
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6086$1667_Y
- connect \B $eq$ls180.v:6086$1668_Y
- connect \Y $and$ls180.v:6086$1669_Y
+ connect \A $and$ls180.v:6082$1667_Y
+ connect \B $eq$ls180.v:6082$1668_Y
+ connect \Y $and$ls180.v:6082$1669_Y
end
- attribute \src "ls180.v:6124.42-6124.95"
- cell $and $and$ls180.v:6124$1671
+ attribute \src "ls180.v:6120.42-6120.95"
+ cell $and $and$ls180.v:6120$1671
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank7_sel
connect \B \builder_interface7_bank_bus_we
- connect \Y $and$ls180.v:6124$1671_Y
+ connect \Y $and$ls180.v:6120$1671_Y
end
- attribute \src "ls180.v:6124.41-6124.145"
- cell $and $and$ls180.v:6124$1673
+ attribute \src "ls180.v:6120.41-6120.145"
+ cell $and $and$ls180.v:6120$1673
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6124$1671_Y
- connect \B $eq$ls180.v:6124$1672_Y
- connect \Y $and$ls180.v:6124$1673_Y
+ connect \A $and$ls180.v:6120$1671_Y
+ connect \B $eq$ls180.v:6120$1672_Y
+ connect \Y $and$ls180.v:6120$1673_Y
end
- attribute \src "ls180.v:6125.42-6125.98"
- cell $and $and$ls180.v:6125$1675
+ attribute \src "ls180.v:6121.42-6121.98"
+ cell $and $and$ls180.v:6121$1675
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank7_sel
- connect \B $not$ls180.v:6125$1674_Y
- connect \Y $and$ls180.v:6125$1675_Y
+ connect \B $not$ls180.v:6121$1674_Y
+ connect \Y $and$ls180.v:6121$1675_Y
end
- attribute \src "ls180.v:6125.41-6125.148"
- cell $and $and$ls180.v:6125$1677
+ attribute \src "ls180.v:6121.41-6121.148"
+ cell $and $and$ls180.v:6121$1677
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6125$1675_Y
- connect \B $eq$ls180.v:6125$1676_Y
- connect \Y $and$ls180.v:6125$1677_Y
+ connect \A $and$ls180.v:6121$1675_Y
+ connect \B $eq$ls180.v:6121$1676_Y
+ connect \Y $and$ls180.v:6121$1677_Y
end
- attribute \src "ls180.v:6127.42-6127.95"
- cell $and $and$ls180.v:6127$1678
+ attribute \src "ls180.v:6123.42-6123.95"
+ cell $and $and$ls180.v:6123$1678
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank7_sel
connect \B \builder_interface7_bank_bus_we
- connect \Y $and$ls180.v:6127$1678_Y
+ connect \Y $and$ls180.v:6123$1678_Y
end
- attribute \src "ls180.v:6127.41-6127.145"
- cell $and $and$ls180.v:6127$1680
+ attribute \src "ls180.v:6123.41-6123.145"
+ cell $and $and$ls180.v:6123$1680
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6127$1678_Y
- connect \B $eq$ls180.v:6127$1679_Y
- connect \Y $and$ls180.v:6127$1680_Y
+ connect \A $and$ls180.v:6123$1678_Y
+ connect \B $eq$ls180.v:6123$1679_Y
+ connect \Y $and$ls180.v:6123$1680_Y
end
- attribute \src "ls180.v:6128.42-6128.98"
- cell $and $and$ls180.v:6128$1682
+ attribute \src "ls180.v:6124.42-6124.98"
+ cell $and $and$ls180.v:6124$1682
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank7_sel
- connect \B $not$ls180.v:6128$1681_Y
- connect \Y $and$ls180.v:6128$1682_Y
+ connect \B $not$ls180.v:6124$1681_Y
+ connect \Y $and$ls180.v:6124$1682_Y
end
- attribute \src "ls180.v:6128.41-6128.148"
- cell $and $and$ls180.v:6128$1684
+ attribute \src "ls180.v:6124.41-6124.148"
+ cell $and $and$ls180.v:6124$1684
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6128$1682_Y
- connect \B $eq$ls180.v:6128$1683_Y
- connect \Y $and$ls180.v:6128$1684_Y
+ connect \A $and$ls180.v:6124$1682_Y
+ connect \B $eq$ls180.v:6124$1683_Y
+ connect \Y $and$ls180.v:6124$1684_Y
end
- attribute \src "ls180.v:6130.42-6130.95"
- cell $and $and$ls180.v:6130$1685
+ attribute \src "ls180.v:6126.42-6126.95"
+ cell $and $and$ls180.v:6126$1685
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank7_sel
connect \B \builder_interface7_bank_bus_we
- connect \Y $and$ls180.v:6130$1685_Y
+ connect \Y $and$ls180.v:6126$1685_Y
end
- attribute \src "ls180.v:6130.41-6130.145"
- cell $and $and$ls180.v:6130$1687
+ attribute \src "ls180.v:6126.41-6126.145"
+ cell $and $and$ls180.v:6126$1687
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6130$1685_Y
- connect \B $eq$ls180.v:6130$1686_Y
- connect \Y $and$ls180.v:6130$1687_Y
+ connect \A $and$ls180.v:6126$1685_Y
+ connect \B $eq$ls180.v:6126$1686_Y
+ connect \Y $and$ls180.v:6126$1687_Y
end
- attribute \src "ls180.v:6131.42-6131.98"
- cell $and $and$ls180.v:6131$1689
+ attribute \src "ls180.v:6127.42-6127.98"
+ cell $and $and$ls180.v:6127$1689
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank7_sel
- connect \B $not$ls180.v:6131$1688_Y
- connect \Y $and$ls180.v:6131$1689_Y
+ connect \B $not$ls180.v:6127$1688_Y
+ connect \Y $and$ls180.v:6127$1689_Y
end
- attribute \src "ls180.v:6131.41-6131.148"
- cell $and $and$ls180.v:6131$1691
+ attribute \src "ls180.v:6127.41-6127.148"
+ cell $and $and$ls180.v:6127$1691
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6131$1689_Y
- connect \B $eq$ls180.v:6131$1690_Y
- connect \Y $and$ls180.v:6131$1691_Y
+ connect \A $and$ls180.v:6127$1689_Y
+ connect \B $eq$ls180.v:6127$1690_Y
+ connect \Y $and$ls180.v:6127$1691_Y
end
- attribute \src "ls180.v:6133.42-6133.95"
- cell $and $and$ls180.v:6133$1692
+ attribute \src "ls180.v:6129.42-6129.95"
+ cell $and $and$ls180.v:6129$1692
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank7_sel
connect \B \builder_interface7_bank_bus_we
- connect \Y $and$ls180.v:6133$1692_Y
+ connect \Y $and$ls180.v:6129$1692_Y
end
- attribute \src "ls180.v:6133.41-6133.145"
- cell $and $and$ls180.v:6133$1694
+ attribute \src "ls180.v:6129.41-6129.145"
+ cell $and $and$ls180.v:6129$1694
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6133$1692_Y
- connect \B $eq$ls180.v:6133$1693_Y
- connect \Y $and$ls180.v:6133$1694_Y
+ connect \A $and$ls180.v:6129$1692_Y
+ connect \B $eq$ls180.v:6129$1693_Y
+ connect \Y $and$ls180.v:6129$1694_Y
end
- attribute \src "ls180.v:6134.42-6134.98"
- cell $and $and$ls180.v:6134$1696
+ attribute \src "ls180.v:6130.42-6130.98"
+ cell $and $and$ls180.v:6130$1696
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank7_sel
- connect \B $not$ls180.v:6134$1695_Y
- connect \Y $and$ls180.v:6134$1696_Y
+ connect \B $not$ls180.v:6130$1695_Y
+ connect \Y $and$ls180.v:6130$1696_Y
end
- attribute \src "ls180.v:6134.41-6134.148"
- cell $and $and$ls180.v:6134$1698
+ attribute \src "ls180.v:6130.41-6130.148"
+ cell $and $and$ls180.v:6130$1698
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6134$1696_Y
- connect \B $eq$ls180.v:6134$1697_Y
- connect \Y $and$ls180.v:6134$1698_Y
+ connect \A $and$ls180.v:6130$1696_Y
+ connect \B $eq$ls180.v:6130$1697_Y
+ connect \Y $and$ls180.v:6130$1698_Y
end
- attribute \src "ls180.v:6136.42-6136.95"
- cell $and $and$ls180.v:6136$1699
+ attribute \src "ls180.v:6132.42-6132.95"
+ cell $and $and$ls180.v:6132$1699
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank7_sel
connect \B \builder_interface7_bank_bus_we
- connect \Y $and$ls180.v:6136$1699_Y
+ connect \Y $and$ls180.v:6132$1699_Y
end
- attribute \src "ls180.v:6136.41-6136.145"
- cell $and $and$ls180.v:6136$1701
+ attribute \src "ls180.v:6132.41-6132.145"
+ cell $and $and$ls180.v:6132$1701
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6136$1699_Y
- connect \B $eq$ls180.v:6136$1700_Y
- connect \Y $and$ls180.v:6136$1701_Y
+ connect \A $and$ls180.v:6132$1699_Y
+ connect \B $eq$ls180.v:6132$1700_Y
+ connect \Y $and$ls180.v:6132$1701_Y
end
- attribute \src "ls180.v:6137.42-6137.98"
- cell $and $and$ls180.v:6137$1703
+ attribute \src "ls180.v:6133.42-6133.98"
+ cell $and $and$ls180.v:6133$1703
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank7_sel
- connect \B $not$ls180.v:6137$1702_Y
- connect \Y $and$ls180.v:6137$1703_Y
+ connect \B $not$ls180.v:6133$1702_Y
+ connect \Y $and$ls180.v:6133$1703_Y
end
- attribute \src "ls180.v:6137.41-6137.148"
- cell $and $and$ls180.v:6137$1705
+ attribute \src "ls180.v:6133.41-6133.148"
+ cell $and $and$ls180.v:6133$1705
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6137$1703_Y
- connect \B $eq$ls180.v:6137$1704_Y
- connect \Y $and$ls180.v:6137$1705_Y
+ connect \A $and$ls180.v:6133$1703_Y
+ connect \B $eq$ls180.v:6133$1704_Y
+ connect \Y $and$ls180.v:6133$1705_Y
end
- attribute \src "ls180.v:6139.42-6139.95"
- cell $and $and$ls180.v:6139$1706
+ attribute \src "ls180.v:6135.42-6135.95"
+ cell $and $and$ls180.v:6135$1706
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank7_sel
connect \B \builder_interface7_bank_bus_we
- connect \Y $and$ls180.v:6139$1706_Y
+ connect \Y $and$ls180.v:6135$1706_Y
end
- attribute \src "ls180.v:6139.41-6139.145"
- cell $and $and$ls180.v:6139$1708
+ attribute \src "ls180.v:6135.41-6135.145"
+ cell $and $and$ls180.v:6135$1708
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6139$1706_Y
- connect \B $eq$ls180.v:6139$1707_Y
- connect \Y $and$ls180.v:6139$1708_Y
+ connect \A $and$ls180.v:6135$1706_Y
+ connect \B $eq$ls180.v:6135$1707_Y
+ connect \Y $and$ls180.v:6135$1708_Y
end
- attribute \src "ls180.v:6140.42-6140.98"
- cell $and $and$ls180.v:6140$1710
+ attribute \src "ls180.v:6136.42-6136.98"
+ cell $and $and$ls180.v:6136$1710
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank7_sel
- connect \B $not$ls180.v:6140$1709_Y
- connect \Y $and$ls180.v:6140$1710_Y
+ connect \B $not$ls180.v:6136$1709_Y
+ connect \Y $and$ls180.v:6136$1710_Y
end
- attribute \src "ls180.v:6140.41-6140.148"
- cell $and $and$ls180.v:6140$1712
+ attribute \src "ls180.v:6136.41-6136.148"
+ cell $and $and$ls180.v:6136$1712
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6140$1710_Y
- connect \B $eq$ls180.v:6140$1711_Y
- connect \Y $and$ls180.v:6140$1712_Y
+ connect \A $and$ls180.v:6136$1710_Y
+ connect \B $eq$ls180.v:6136$1711_Y
+ connect \Y $and$ls180.v:6136$1712_Y
end
- attribute \src "ls180.v:6142.42-6142.95"
- cell $and $and$ls180.v:6142$1713
+ attribute \src "ls180.v:6138.42-6138.95"
+ cell $and $and$ls180.v:6138$1713
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank7_sel
connect \B \builder_interface7_bank_bus_we
- connect \Y $and$ls180.v:6142$1713_Y
+ connect \Y $and$ls180.v:6138$1713_Y
end
- attribute \src "ls180.v:6142.41-6142.145"
- cell $and $and$ls180.v:6142$1715
+ attribute \src "ls180.v:6138.41-6138.145"
+ cell $and $and$ls180.v:6138$1715
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6142$1713_Y
- connect \B $eq$ls180.v:6142$1714_Y
- connect \Y $and$ls180.v:6142$1715_Y
+ connect \A $and$ls180.v:6138$1713_Y
+ connect \B $eq$ls180.v:6138$1714_Y
+ connect \Y $and$ls180.v:6138$1715_Y
end
- attribute \src "ls180.v:6143.42-6143.98"
- cell $and $and$ls180.v:6143$1717
+ attribute \src "ls180.v:6139.42-6139.98"
+ cell $and $and$ls180.v:6139$1717
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank7_sel
- connect \B $not$ls180.v:6143$1716_Y
- connect \Y $and$ls180.v:6143$1717_Y
+ connect \B $not$ls180.v:6139$1716_Y
+ connect \Y $and$ls180.v:6139$1717_Y
end
- attribute \src "ls180.v:6143.41-6143.148"
- cell $and $and$ls180.v:6143$1719
+ attribute \src "ls180.v:6139.41-6139.148"
+ cell $and $and$ls180.v:6139$1719
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6143$1717_Y
- connect \B $eq$ls180.v:6143$1718_Y
- connect \Y $and$ls180.v:6143$1719_Y
+ connect \A $and$ls180.v:6139$1717_Y
+ connect \B $eq$ls180.v:6139$1718_Y
+ connect \Y $and$ls180.v:6139$1719_Y
end
- attribute \src "ls180.v:6145.42-6145.95"
- cell $and $and$ls180.v:6145$1720
+ attribute \src "ls180.v:6141.42-6141.95"
+ cell $and $and$ls180.v:6141$1720
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank7_sel
connect \B \builder_interface7_bank_bus_we
- connect \Y $and$ls180.v:6145$1720_Y
+ connect \Y $and$ls180.v:6141$1720_Y
end
- attribute \src "ls180.v:6145.41-6145.145"
- cell $and $and$ls180.v:6145$1722
+ attribute \src "ls180.v:6141.41-6141.145"
+ cell $and $and$ls180.v:6141$1722
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6145$1720_Y
- connect \B $eq$ls180.v:6145$1721_Y
- connect \Y $and$ls180.v:6145$1722_Y
+ connect \A $and$ls180.v:6141$1720_Y
+ connect \B $eq$ls180.v:6141$1721_Y
+ connect \Y $and$ls180.v:6141$1722_Y
end
- attribute \src "ls180.v:6146.42-6146.98"
- cell $and $and$ls180.v:6146$1724
+ attribute \src "ls180.v:6142.42-6142.98"
+ cell $and $and$ls180.v:6142$1724
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank7_sel
- connect \B $not$ls180.v:6146$1723_Y
- connect \Y $and$ls180.v:6146$1724_Y
+ connect \B $not$ls180.v:6142$1723_Y
+ connect \Y $and$ls180.v:6142$1724_Y
end
- attribute \src "ls180.v:6146.41-6146.148"
- cell $and $and$ls180.v:6146$1726
+ attribute \src "ls180.v:6142.41-6142.148"
+ cell $and $and$ls180.v:6142$1726
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6146$1724_Y
- connect \B $eq$ls180.v:6146$1725_Y
- connect \Y $and$ls180.v:6146$1726_Y
+ connect \A $and$ls180.v:6142$1724_Y
+ connect \B $eq$ls180.v:6142$1725_Y
+ connect \Y $and$ls180.v:6142$1726_Y
end
- attribute \src "ls180.v:6148.44-6148.97"
- cell $and $and$ls180.v:6148$1727
+ attribute \src "ls180.v:6144.44-6144.97"
+ cell $and $and$ls180.v:6144$1727
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank7_sel
connect \B \builder_interface7_bank_bus_we
- connect \Y $and$ls180.v:6148$1727_Y
+ connect \Y $and$ls180.v:6144$1727_Y
end
- attribute \src "ls180.v:6148.43-6148.147"
- cell $and $and$ls180.v:6148$1729
+ attribute \src "ls180.v:6144.43-6144.147"
+ cell $and $and$ls180.v:6144$1729
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6148$1727_Y
- connect \B $eq$ls180.v:6148$1728_Y
- connect \Y $and$ls180.v:6148$1729_Y
+ connect \A $and$ls180.v:6144$1727_Y
+ connect \B $eq$ls180.v:6144$1728_Y
+ connect \Y $and$ls180.v:6144$1729_Y
end
- attribute \src "ls180.v:6149.44-6149.100"
- cell $and $and$ls180.v:6149$1731
+ attribute \src "ls180.v:6145.44-6145.100"
+ cell $and $and$ls180.v:6145$1731
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank7_sel
- connect \B $not$ls180.v:6149$1730_Y
- connect \Y $and$ls180.v:6149$1731_Y
+ connect \B $not$ls180.v:6145$1730_Y
+ connect \Y $and$ls180.v:6145$1731_Y
end
- attribute \src "ls180.v:6149.43-6149.150"
- cell $and $and$ls180.v:6149$1733
+ attribute \src "ls180.v:6145.43-6145.150"
+ cell $and $and$ls180.v:6145$1733
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6149$1731_Y
- connect \B $eq$ls180.v:6149$1732_Y
- connect \Y $and$ls180.v:6149$1733_Y
+ connect \A $and$ls180.v:6145$1731_Y
+ connect \B $eq$ls180.v:6145$1732_Y
+ connect \Y $and$ls180.v:6145$1733_Y
end
- attribute \src "ls180.v:6151.44-6151.97"
- cell $and $and$ls180.v:6151$1734
+ attribute \src "ls180.v:6147.44-6147.97"
+ cell $and $and$ls180.v:6147$1734
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank7_sel
connect \B \builder_interface7_bank_bus_we
- connect \Y $and$ls180.v:6151$1734_Y
+ connect \Y $and$ls180.v:6147$1734_Y
end
- attribute \src "ls180.v:6151.43-6151.147"
- cell $and $and$ls180.v:6151$1736
+ attribute \src "ls180.v:6147.43-6147.147"
+ cell $and $and$ls180.v:6147$1736
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6151$1734_Y
- connect \B $eq$ls180.v:6151$1735_Y
- connect \Y $and$ls180.v:6151$1736_Y
+ connect \A $and$ls180.v:6147$1734_Y
+ connect \B $eq$ls180.v:6147$1735_Y
+ connect \Y $and$ls180.v:6147$1736_Y
end
- attribute \src "ls180.v:6152.44-6152.100"
- cell $and $and$ls180.v:6152$1738
+ attribute \src "ls180.v:6148.44-6148.100"
+ cell $and $and$ls180.v:6148$1738
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank7_sel
- connect \B $not$ls180.v:6152$1737_Y
- connect \Y $and$ls180.v:6152$1738_Y
+ connect \B $not$ls180.v:6148$1737_Y
+ connect \Y $and$ls180.v:6148$1738_Y
end
- attribute \src "ls180.v:6152.43-6152.150"
- cell $and $and$ls180.v:6152$1740
+ attribute \src "ls180.v:6148.43-6148.150"
+ cell $and $and$ls180.v:6148$1740
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6152$1738_Y
- connect \B $eq$ls180.v:6152$1739_Y
- connect \Y $and$ls180.v:6152$1740_Y
+ connect \A $and$ls180.v:6148$1738_Y
+ connect \B $eq$ls180.v:6148$1739_Y
+ connect \Y $and$ls180.v:6148$1740_Y
end
- attribute \src "ls180.v:6154.44-6154.97"
- cell $and $and$ls180.v:6154$1741
+ attribute \src "ls180.v:6150.44-6150.97"
+ cell $and $and$ls180.v:6150$1741
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank7_sel
connect \B \builder_interface7_bank_bus_we
- connect \Y $and$ls180.v:6154$1741_Y
+ connect \Y $and$ls180.v:6150$1741_Y
end
- attribute \src "ls180.v:6154.43-6154.148"
- cell $and $and$ls180.v:6154$1743
+ attribute \src "ls180.v:6150.43-6150.148"
+ cell $and $and$ls180.v:6150$1743
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6154$1741_Y
- connect \B $eq$ls180.v:6154$1742_Y
- connect \Y $and$ls180.v:6154$1743_Y
+ connect \A $and$ls180.v:6150$1741_Y
+ connect \B $eq$ls180.v:6150$1742_Y
+ connect \Y $and$ls180.v:6150$1743_Y
end
- attribute \src "ls180.v:6155.44-6155.100"
- cell $and $and$ls180.v:6155$1745
+ attribute \src "ls180.v:6151.44-6151.100"
+ cell $and $and$ls180.v:6151$1745
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank7_sel
- connect \B $not$ls180.v:6155$1744_Y
- connect \Y $and$ls180.v:6155$1745_Y
+ connect \B $not$ls180.v:6151$1744_Y
+ connect \Y $and$ls180.v:6151$1745_Y
end
- attribute \src "ls180.v:6155.43-6155.151"
- cell $and $and$ls180.v:6155$1747
+ attribute \src "ls180.v:6151.43-6151.151"
+ cell $and $and$ls180.v:6151$1747
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6155$1745_Y
- connect \B $eq$ls180.v:6155$1746_Y
- connect \Y $and$ls180.v:6155$1747_Y
+ connect \A $and$ls180.v:6151$1745_Y
+ connect \B $eq$ls180.v:6151$1746_Y
+ connect \Y $and$ls180.v:6151$1747_Y
end
- attribute \src "ls180.v:6157.44-6157.97"
- cell $and $and$ls180.v:6157$1748
+ attribute \src "ls180.v:6153.44-6153.97"
+ cell $and $and$ls180.v:6153$1748
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank7_sel
connect \B \builder_interface7_bank_bus_we
- connect \Y $and$ls180.v:6157$1748_Y
+ connect \Y $and$ls180.v:6153$1748_Y
end
- attribute \src "ls180.v:6157.43-6157.148"
- cell $and $and$ls180.v:6157$1750
+ attribute \src "ls180.v:6153.43-6153.148"
+ cell $and $and$ls180.v:6153$1750
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6157$1748_Y
- connect \B $eq$ls180.v:6157$1749_Y
- connect \Y $and$ls180.v:6157$1750_Y
+ connect \A $and$ls180.v:6153$1748_Y
+ connect \B $eq$ls180.v:6153$1749_Y
+ connect \Y $and$ls180.v:6153$1750_Y
end
- attribute \src "ls180.v:6158.44-6158.100"
- cell $and $and$ls180.v:6158$1752
+ attribute \src "ls180.v:6154.44-6154.100"
+ cell $and $and$ls180.v:6154$1752
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank7_sel
- connect \B $not$ls180.v:6158$1751_Y
- connect \Y $and$ls180.v:6158$1752_Y
+ connect \B $not$ls180.v:6154$1751_Y
+ connect \Y $and$ls180.v:6154$1752_Y
end
- attribute \src "ls180.v:6158.43-6158.151"
- cell $and $and$ls180.v:6158$1754
+ attribute \src "ls180.v:6154.43-6154.151"
+ cell $and $and$ls180.v:6154$1754
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6158$1752_Y
- connect \B $eq$ls180.v:6158$1753_Y
- connect \Y $and$ls180.v:6158$1754_Y
+ connect \A $and$ls180.v:6154$1752_Y
+ connect \B $eq$ls180.v:6154$1753_Y
+ connect \Y $and$ls180.v:6154$1754_Y
end
- attribute \src "ls180.v:6160.44-6160.97"
- cell $and $and$ls180.v:6160$1755
+ attribute \src "ls180.v:6156.44-6156.97"
+ cell $and $and$ls180.v:6156$1755
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank7_sel
connect \B \builder_interface7_bank_bus_we
- connect \Y $and$ls180.v:6160$1755_Y
+ connect \Y $and$ls180.v:6156$1755_Y
end
- attribute \src "ls180.v:6160.43-6160.148"
- cell $and $and$ls180.v:6160$1757
+ attribute \src "ls180.v:6156.43-6156.148"
+ cell $and $and$ls180.v:6156$1757
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6160$1755_Y
- connect \B $eq$ls180.v:6160$1756_Y
- connect \Y $and$ls180.v:6160$1757_Y
+ connect \A $and$ls180.v:6156$1755_Y
+ connect \B $eq$ls180.v:6156$1756_Y
+ connect \Y $and$ls180.v:6156$1757_Y
end
- attribute \src "ls180.v:6161.44-6161.100"
- cell $and $and$ls180.v:6161$1759
+ attribute \src "ls180.v:6157.44-6157.100"
+ cell $and $and$ls180.v:6157$1759
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank7_sel
- connect \B $not$ls180.v:6161$1758_Y
- connect \Y $and$ls180.v:6161$1759_Y
+ connect \B $not$ls180.v:6157$1758_Y
+ connect \Y $and$ls180.v:6157$1759_Y
end
- attribute \src "ls180.v:6161.43-6161.151"
- cell $and $and$ls180.v:6161$1761
+ attribute \src "ls180.v:6157.43-6157.151"
+ cell $and $and$ls180.v:6157$1761
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6161$1759_Y
- connect \B $eq$ls180.v:6161$1760_Y
- connect \Y $and$ls180.v:6161$1761_Y
+ connect \A $and$ls180.v:6157$1759_Y
+ connect \B $eq$ls180.v:6157$1760_Y
+ connect \Y $and$ls180.v:6157$1761_Y
end
- attribute \src "ls180.v:6163.41-6163.94"
- cell $and $and$ls180.v:6163$1762
+ attribute \src "ls180.v:6159.41-6159.94"
+ cell $and $and$ls180.v:6159$1762
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank7_sel
connect \B \builder_interface7_bank_bus_we
- connect \Y $and$ls180.v:6163$1762_Y
+ connect \Y $and$ls180.v:6159$1762_Y
end
- attribute \src "ls180.v:6163.40-6163.145"
- cell $and $and$ls180.v:6163$1764
+ attribute \src "ls180.v:6159.40-6159.145"
+ cell $and $and$ls180.v:6159$1764
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6163$1762_Y
- connect \B $eq$ls180.v:6163$1763_Y
- connect \Y $and$ls180.v:6163$1764_Y
+ connect \A $and$ls180.v:6159$1762_Y
+ connect \B $eq$ls180.v:6159$1763_Y
+ connect \Y $and$ls180.v:6159$1764_Y
end
- attribute \src "ls180.v:6164.41-6164.97"
- cell $and $and$ls180.v:6164$1766
+ attribute \src "ls180.v:6160.41-6160.97"
+ cell $and $and$ls180.v:6160$1766
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank7_sel
- connect \B $not$ls180.v:6164$1765_Y
- connect \Y $and$ls180.v:6164$1766_Y
+ connect \B $not$ls180.v:6160$1765_Y
+ connect \Y $and$ls180.v:6160$1766_Y
end
- attribute \src "ls180.v:6164.40-6164.148"
- cell $and $and$ls180.v:6164$1768
+ attribute \src "ls180.v:6160.40-6160.148"
+ cell $and $and$ls180.v:6160$1768
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6164$1766_Y
- connect \B $eq$ls180.v:6164$1767_Y
- connect \Y $and$ls180.v:6164$1768_Y
+ connect \A $and$ls180.v:6160$1766_Y
+ connect \B $eq$ls180.v:6160$1767_Y
+ connect \Y $and$ls180.v:6160$1768_Y
end
- attribute \src "ls180.v:6166.42-6166.95"
- cell $and $and$ls180.v:6166$1769
+ attribute \src "ls180.v:6162.42-6162.95"
+ cell $and $and$ls180.v:6162$1769
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank7_sel
connect \B \builder_interface7_bank_bus_we
- connect \Y $and$ls180.v:6166$1769_Y
+ connect \Y $and$ls180.v:6162$1769_Y
end
- attribute \src "ls180.v:6166.41-6166.146"
- cell $and $and$ls180.v:6166$1771
+ attribute \src "ls180.v:6162.41-6162.146"
+ cell $and $and$ls180.v:6162$1771
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6166$1769_Y
- connect \B $eq$ls180.v:6166$1770_Y
- connect \Y $and$ls180.v:6166$1771_Y
+ connect \A $and$ls180.v:6162$1769_Y
+ connect \B $eq$ls180.v:6162$1770_Y
+ connect \Y $and$ls180.v:6162$1771_Y
end
- attribute \src "ls180.v:6167.42-6167.98"
- cell $and $and$ls180.v:6167$1773
+ attribute \src "ls180.v:6163.42-6163.98"
+ cell $and $and$ls180.v:6163$1773
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank7_sel
- connect \B $not$ls180.v:6167$1772_Y
- connect \Y $and$ls180.v:6167$1773_Y
+ connect \B $not$ls180.v:6163$1772_Y
+ connect \Y $and$ls180.v:6163$1773_Y
end
- attribute \src "ls180.v:6167.41-6167.149"
- cell $and $and$ls180.v:6167$1775
+ attribute \src "ls180.v:6163.41-6163.149"
+ cell $and $and$ls180.v:6163$1775
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6167$1773_Y
- connect \B $eq$ls180.v:6167$1774_Y
- connect \Y $and$ls180.v:6167$1775_Y
+ connect \A $and$ls180.v:6163$1773_Y
+ connect \B $eq$ls180.v:6163$1774_Y
+ connect \Y $and$ls180.v:6163$1775_Y
end
- attribute \src "ls180.v:6169.44-6169.97"
- cell $and $and$ls180.v:6169$1776
+ attribute \src "ls180.v:6165.44-6165.97"
+ cell $and $and$ls180.v:6165$1776
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank7_sel
connect \B \builder_interface7_bank_bus_we
- connect \Y $and$ls180.v:6169$1776_Y
+ connect \Y $and$ls180.v:6165$1776_Y
end
- attribute \src "ls180.v:6169.43-6169.148"
- cell $and $and$ls180.v:6169$1778
+ attribute \src "ls180.v:6165.43-6165.148"
+ cell $and $and$ls180.v:6165$1778
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6169$1776_Y
- connect \B $eq$ls180.v:6169$1777_Y
- connect \Y $and$ls180.v:6169$1778_Y
+ connect \A $and$ls180.v:6165$1776_Y
+ connect \B $eq$ls180.v:6165$1777_Y
+ connect \Y $and$ls180.v:6165$1778_Y
end
- attribute \src "ls180.v:6170.44-6170.100"
- cell $and $and$ls180.v:6170$1780
+ attribute \src "ls180.v:6166.44-6166.100"
+ cell $and $and$ls180.v:6166$1780
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank7_sel
- connect \B $not$ls180.v:6170$1779_Y
- connect \Y $and$ls180.v:6170$1780_Y
+ connect \B $not$ls180.v:6166$1779_Y
+ connect \Y $and$ls180.v:6166$1780_Y
end
- attribute \src "ls180.v:6170.43-6170.151"
- cell $and $and$ls180.v:6170$1782
+ attribute \src "ls180.v:6166.43-6166.151"
+ cell $and $and$ls180.v:6166$1782
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6170$1780_Y
- connect \B $eq$ls180.v:6170$1781_Y
- connect \Y $and$ls180.v:6170$1782_Y
+ connect \A $and$ls180.v:6166$1780_Y
+ connect \B $eq$ls180.v:6166$1781_Y
+ connect \Y $and$ls180.v:6166$1782_Y
end
- attribute \src "ls180.v:6172.44-6172.97"
- cell $and $and$ls180.v:6172$1783
+ attribute \src "ls180.v:6168.44-6168.97"
+ cell $and $and$ls180.v:6168$1783
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank7_sel
connect \B \builder_interface7_bank_bus_we
- connect \Y $and$ls180.v:6172$1783_Y
+ connect \Y $and$ls180.v:6168$1783_Y
end
- attribute \src "ls180.v:6172.43-6172.148"
- cell $and $and$ls180.v:6172$1785
+ attribute \src "ls180.v:6168.43-6168.148"
+ cell $and $and$ls180.v:6168$1785
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6172$1783_Y
- connect \B $eq$ls180.v:6172$1784_Y
- connect \Y $and$ls180.v:6172$1785_Y
+ connect \A $and$ls180.v:6168$1783_Y
+ connect \B $eq$ls180.v:6168$1784_Y
+ connect \Y $and$ls180.v:6168$1785_Y
end
- attribute \src "ls180.v:6173.44-6173.100"
- cell $and $and$ls180.v:6173$1787
+ attribute \src "ls180.v:6169.44-6169.100"
+ cell $and $and$ls180.v:6169$1787
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank7_sel
- connect \B $not$ls180.v:6173$1786_Y
- connect \Y $and$ls180.v:6173$1787_Y
+ connect \B $not$ls180.v:6169$1786_Y
+ connect \Y $and$ls180.v:6169$1787_Y
end
- attribute \src "ls180.v:6173.43-6173.151"
- cell $and $and$ls180.v:6173$1789
+ attribute \src "ls180.v:6169.43-6169.151"
+ cell $and $and$ls180.v:6169$1789
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6173$1787_Y
- connect \B $eq$ls180.v:6173$1788_Y
- connect \Y $and$ls180.v:6173$1789_Y
+ connect \A $and$ls180.v:6169$1787_Y
+ connect \B $eq$ls180.v:6169$1788_Y
+ connect \Y $and$ls180.v:6169$1789_Y
end
- attribute \src "ls180.v:6175.44-6175.97"
- cell $and $and$ls180.v:6175$1790
+ attribute \src "ls180.v:6171.44-6171.97"
+ cell $and $and$ls180.v:6171$1790
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank7_sel
connect \B \builder_interface7_bank_bus_we
- connect \Y $and$ls180.v:6175$1790_Y
+ connect \Y $and$ls180.v:6171$1790_Y
end
- attribute \src "ls180.v:6175.43-6175.148"
- cell $and $and$ls180.v:6175$1792
+ attribute \src "ls180.v:6171.43-6171.148"
+ cell $and $and$ls180.v:6171$1792
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6175$1790_Y
- connect \B $eq$ls180.v:6175$1791_Y
- connect \Y $and$ls180.v:6175$1792_Y
+ connect \A $and$ls180.v:6171$1790_Y
+ connect \B $eq$ls180.v:6171$1791_Y
+ connect \Y $and$ls180.v:6171$1792_Y
end
- attribute \src "ls180.v:6176.44-6176.100"
- cell $and $and$ls180.v:6176$1794
+ attribute \src "ls180.v:6172.44-6172.100"
+ cell $and $and$ls180.v:6172$1794
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank7_sel
- connect \B $not$ls180.v:6176$1793_Y
- connect \Y $and$ls180.v:6176$1794_Y
+ connect \B $not$ls180.v:6172$1793_Y
+ connect \Y $and$ls180.v:6172$1794_Y
end
- attribute \src "ls180.v:6176.43-6176.151"
- cell $and $and$ls180.v:6176$1796
+ attribute \src "ls180.v:6172.43-6172.151"
+ cell $and $and$ls180.v:6172$1796
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6176$1794_Y
- connect \B $eq$ls180.v:6176$1795_Y
- connect \Y $and$ls180.v:6176$1796_Y
+ connect \A $and$ls180.v:6172$1794_Y
+ connect \B $eq$ls180.v:6172$1795_Y
+ connect \Y $and$ls180.v:6172$1796_Y
end
- attribute \src "ls180.v:6178.44-6178.97"
- cell $and $and$ls180.v:6178$1797
+ attribute \src "ls180.v:6174.44-6174.97"
+ cell $and $and$ls180.v:6174$1797
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank7_sel
connect \B \builder_interface7_bank_bus_we
- connect \Y $and$ls180.v:6178$1797_Y
+ connect \Y $and$ls180.v:6174$1797_Y
end
- attribute \src "ls180.v:6178.43-6178.148"
- cell $and $and$ls180.v:6178$1799
+ attribute \src "ls180.v:6174.43-6174.148"
+ cell $and $and$ls180.v:6174$1799
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6178$1797_Y
- connect \B $eq$ls180.v:6178$1798_Y
- connect \Y $and$ls180.v:6178$1799_Y
+ connect \A $and$ls180.v:6174$1797_Y
+ connect \B $eq$ls180.v:6174$1798_Y
+ connect \Y $and$ls180.v:6174$1799_Y
end
- attribute \src "ls180.v:6179.44-6179.100"
- cell $and $and$ls180.v:6179$1801
+ attribute \src "ls180.v:6175.44-6175.100"
+ cell $and $and$ls180.v:6175$1801
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank7_sel
- connect \B $not$ls180.v:6179$1800_Y
- connect \Y $and$ls180.v:6179$1801_Y
+ connect \B $not$ls180.v:6175$1800_Y
+ connect \Y $and$ls180.v:6175$1801_Y
end
- attribute \src "ls180.v:6179.43-6179.151"
- cell $and $and$ls180.v:6179$1803
+ attribute \src "ls180.v:6175.43-6175.151"
+ cell $and $and$ls180.v:6175$1803
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6179$1801_Y
- connect \B $eq$ls180.v:6179$1802_Y
- connect \Y $and$ls180.v:6179$1803_Y
+ connect \A $and$ls180.v:6175$1801_Y
+ connect \B $eq$ls180.v:6175$1802_Y
+ connect \Y $and$ls180.v:6175$1803_Y
end
- attribute \src "ls180.v:6203.44-6203.97"
- cell $and $and$ls180.v:6203$1805
+ attribute \src "ls180.v:6199.44-6199.97"
+ cell $and $and$ls180.v:6199$1805
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank8_sel
connect \B \builder_interface8_bank_bus_we
- connect \Y $and$ls180.v:6203$1805_Y
+ connect \Y $and$ls180.v:6199$1805_Y
end
- attribute \src "ls180.v:6203.43-6203.147"
- cell $and $and$ls180.v:6203$1807
+ attribute \src "ls180.v:6199.43-6199.147"
+ cell $and $and$ls180.v:6199$1807
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6203$1805_Y
- connect \B $eq$ls180.v:6203$1806_Y
- connect \Y $and$ls180.v:6203$1807_Y
+ connect \A $and$ls180.v:6199$1805_Y
+ connect \B $eq$ls180.v:6199$1806_Y
+ connect \Y $and$ls180.v:6199$1807_Y
end
- attribute \src "ls180.v:6204.44-6204.100"
- cell $and $and$ls180.v:6204$1809
+ attribute \src "ls180.v:6200.44-6200.100"
+ cell $and $and$ls180.v:6200$1809
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank8_sel
- connect \B $not$ls180.v:6204$1808_Y
- connect \Y $and$ls180.v:6204$1809_Y
+ connect \B $not$ls180.v:6200$1808_Y
+ connect \Y $and$ls180.v:6200$1809_Y
end
- attribute \src "ls180.v:6204.43-6204.150"
- cell $and $and$ls180.v:6204$1811
+ attribute \src "ls180.v:6200.43-6200.150"
+ cell $and $and$ls180.v:6200$1811
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6204$1809_Y
- connect \B $eq$ls180.v:6204$1810_Y
- connect \Y $and$ls180.v:6204$1811_Y
+ connect \A $and$ls180.v:6200$1809_Y
+ connect \B $eq$ls180.v:6200$1810_Y
+ connect \Y $and$ls180.v:6200$1811_Y
end
- attribute \src "ls180.v:6206.49-6206.102"
- cell $and $and$ls180.v:6206$1812
+ attribute \src "ls180.v:6202.49-6202.102"
+ cell $and $and$ls180.v:6202$1812
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank8_sel
connect \B \builder_interface8_bank_bus_we
- connect \Y $and$ls180.v:6206$1812_Y
+ connect \Y $and$ls180.v:6202$1812_Y
end
- attribute \src "ls180.v:6206.48-6206.152"
- cell $and $and$ls180.v:6206$1814
+ attribute \src "ls180.v:6202.48-6202.152"
+ cell $and $and$ls180.v:6202$1814
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6206$1812_Y
- connect \B $eq$ls180.v:6206$1813_Y
- connect \Y $and$ls180.v:6206$1814_Y
+ connect \A $and$ls180.v:6202$1812_Y
+ connect \B $eq$ls180.v:6202$1813_Y
+ connect \Y $and$ls180.v:6202$1814_Y
end
- attribute \src "ls180.v:6207.49-6207.105"
- cell $and $and$ls180.v:6207$1816
+ attribute \src "ls180.v:6203.49-6203.105"
+ cell $and $and$ls180.v:6203$1816
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank8_sel
- connect \B $not$ls180.v:6207$1815_Y
- connect \Y $and$ls180.v:6207$1816_Y
+ connect \B $not$ls180.v:6203$1815_Y
+ connect \Y $and$ls180.v:6203$1816_Y
end
- attribute \src "ls180.v:6207.48-6207.155"
- cell $and $and$ls180.v:6207$1818
+ attribute \src "ls180.v:6203.48-6203.155"
+ cell $and $and$ls180.v:6203$1818
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6207$1816_Y
- connect \B $eq$ls180.v:6207$1817_Y
- connect \Y $and$ls180.v:6207$1818_Y
+ connect \A $and$ls180.v:6203$1816_Y
+ connect \B $eq$ls180.v:6203$1817_Y
+ connect \Y $and$ls180.v:6203$1818_Y
end
- attribute \src "ls180.v:6209.49-6209.102"
- cell $and $and$ls180.v:6209$1819
+ attribute \src "ls180.v:6205.49-6205.102"
+ cell $and $and$ls180.v:6205$1819
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank8_sel
connect \B \builder_interface8_bank_bus_we
- connect \Y $and$ls180.v:6209$1819_Y
+ connect \Y $and$ls180.v:6205$1819_Y
end
- attribute \src "ls180.v:6209.48-6209.152"
- cell $and $and$ls180.v:6209$1821
+ attribute \src "ls180.v:6205.48-6205.152"
+ cell $and $and$ls180.v:6205$1821
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6209$1819_Y
- connect \B $eq$ls180.v:6209$1820_Y
- connect \Y $and$ls180.v:6209$1821_Y
+ connect \A $and$ls180.v:6205$1819_Y
+ connect \B $eq$ls180.v:6205$1820_Y
+ connect \Y $and$ls180.v:6205$1821_Y
end
- attribute \src "ls180.v:6210.49-6210.105"
- cell $and $and$ls180.v:6210$1823
+ attribute \src "ls180.v:6206.49-6206.105"
+ cell $and $and$ls180.v:6206$1823
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank8_sel
- connect \B $not$ls180.v:6210$1822_Y
- connect \Y $and$ls180.v:6210$1823_Y
+ connect \B $not$ls180.v:6206$1822_Y
+ connect \Y $and$ls180.v:6206$1823_Y
end
- attribute \src "ls180.v:6210.48-6210.155"
- cell $and $and$ls180.v:6210$1825
+ attribute \src "ls180.v:6206.48-6206.155"
+ cell $and $and$ls180.v:6206$1825
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6210$1823_Y
- connect \B $eq$ls180.v:6210$1824_Y
- connect \Y $and$ls180.v:6210$1825_Y
+ connect \A $and$ls180.v:6206$1823_Y
+ connect \B $eq$ls180.v:6206$1824_Y
+ connect \Y $and$ls180.v:6206$1825_Y
end
- attribute \src "ls180.v:6212.42-6212.95"
- cell $and $and$ls180.v:6212$1826
+ attribute \src "ls180.v:6208.42-6208.95"
+ cell $and $and$ls180.v:6208$1826
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank8_sel
connect \B \builder_interface8_bank_bus_we
- connect \Y $and$ls180.v:6212$1826_Y
+ connect \Y $and$ls180.v:6208$1826_Y
end
- attribute \src "ls180.v:6212.41-6212.145"
- cell $and $and$ls180.v:6212$1828
+ attribute \src "ls180.v:6208.41-6208.145"
+ cell $and $and$ls180.v:6208$1828
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6212$1826_Y
- connect \B $eq$ls180.v:6212$1827_Y
- connect \Y $and$ls180.v:6212$1828_Y
+ connect \A $and$ls180.v:6208$1826_Y
+ connect \B $eq$ls180.v:6208$1827_Y
+ connect \Y $and$ls180.v:6208$1828_Y
end
- attribute \src "ls180.v:6213.42-6213.98"
- cell $and $and$ls180.v:6213$1830
+ attribute \src "ls180.v:6209.42-6209.98"
+ cell $and $and$ls180.v:6209$1830
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank8_sel
- connect \B $not$ls180.v:6213$1829_Y
- connect \Y $and$ls180.v:6213$1830_Y
+ connect \B $not$ls180.v:6209$1829_Y
+ connect \Y $and$ls180.v:6209$1830_Y
end
- attribute \src "ls180.v:6213.41-6213.148"
- cell $and $and$ls180.v:6213$1832
+ attribute \src "ls180.v:6209.41-6209.148"
+ cell $and $and$ls180.v:6209$1832
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6213$1830_Y
- connect \B $eq$ls180.v:6213$1831_Y
- connect \Y $and$ls180.v:6213$1832_Y
+ connect \A $and$ls180.v:6209$1830_Y
+ connect \B $eq$ls180.v:6209$1831_Y
+ connect \Y $and$ls180.v:6209$1832_Y
end
- attribute \src "ls180.v:6220.46-6220.99"
- cell $and $and$ls180.v:6220$1834
+ attribute \src "ls180.v:6216.46-6216.99"
+ cell $and $and$ls180.v:6216$1834
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank9_sel
connect \B \builder_interface9_bank_bus_we
- connect \Y $and$ls180.v:6220$1834_Y
+ connect \Y $and$ls180.v:6216$1834_Y
end
- attribute \src "ls180.v:6220.45-6220.149"
- cell $and $and$ls180.v:6220$1836
+ attribute \src "ls180.v:6216.45-6216.149"
+ cell $and $and$ls180.v:6216$1836
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6220$1834_Y
- connect \B $eq$ls180.v:6220$1835_Y
- connect \Y $and$ls180.v:6220$1836_Y
+ connect \A $and$ls180.v:6216$1834_Y
+ connect \B $eq$ls180.v:6216$1835_Y
+ connect \Y $and$ls180.v:6216$1836_Y
end
- attribute \src "ls180.v:6221.46-6221.102"
- cell $and $and$ls180.v:6221$1838
+ attribute \src "ls180.v:6217.46-6217.102"
+ cell $and $and$ls180.v:6217$1838
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank9_sel
- connect \B $not$ls180.v:6221$1837_Y
- connect \Y $and$ls180.v:6221$1838_Y
+ connect \B $not$ls180.v:6217$1837_Y
+ connect \Y $and$ls180.v:6217$1838_Y
end
- attribute \src "ls180.v:6221.45-6221.152"
- cell $and $and$ls180.v:6221$1840
+ attribute \src "ls180.v:6217.45-6217.152"
+ cell $and $and$ls180.v:6217$1840
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6221$1838_Y
- connect \B $eq$ls180.v:6221$1839_Y
- connect \Y $and$ls180.v:6221$1840_Y
+ connect \A $and$ls180.v:6217$1838_Y
+ connect \B $eq$ls180.v:6217$1839_Y
+ connect \Y $and$ls180.v:6217$1840_Y
end
- attribute \src "ls180.v:6223.50-6223.103"
- cell $and $and$ls180.v:6223$1841
+ attribute \src "ls180.v:6219.50-6219.103"
+ cell $and $and$ls180.v:6219$1841
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank9_sel
connect \B \builder_interface9_bank_bus_we
- connect \Y $and$ls180.v:6223$1841_Y
+ connect \Y $and$ls180.v:6219$1841_Y
end
- attribute \src "ls180.v:6223.49-6223.153"
- cell $and $and$ls180.v:6223$1843
+ attribute \src "ls180.v:6219.49-6219.153"
+ cell $and $and$ls180.v:6219$1843
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6223$1841_Y
- connect \B $eq$ls180.v:6223$1842_Y
- connect \Y $and$ls180.v:6223$1843_Y
+ connect \A $and$ls180.v:6219$1841_Y
+ connect \B $eq$ls180.v:6219$1842_Y
+ connect \Y $and$ls180.v:6219$1843_Y
end
- attribute \src "ls180.v:6224.50-6224.106"
- cell $and $and$ls180.v:6224$1845
+ attribute \src "ls180.v:6220.50-6220.106"
+ cell $and $and$ls180.v:6220$1845
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank9_sel
- connect \B $not$ls180.v:6224$1844_Y
- connect \Y $and$ls180.v:6224$1845_Y
+ connect \B $not$ls180.v:6220$1844_Y
+ connect \Y $and$ls180.v:6220$1845_Y
end
- attribute \src "ls180.v:6224.49-6224.156"
- cell $and $and$ls180.v:6224$1847
+ attribute \src "ls180.v:6220.49-6220.156"
+ cell $and $and$ls180.v:6220$1847
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6224$1845_Y
- connect \B $eq$ls180.v:6224$1846_Y
- connect \Y $and$ls180.v:6224$1847_Y
+ connect \A $and$ls180.v:6220$1845_Y
+ connect \B $eq$ls180.v:6220$1846_Y
+ connect \Y $and$ls180.v:6220$1847_Y
end
- attribute \src "ls180.v:6226.40-6226.93"
- cell $and $and$ls180.v:6226$1848
+ attribute \src "ls180.v:6222.40-6222.93"
+ cell $and $and$ls180.v:6222$1848
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank9_sel
connect \B \builder_interface9_bank_bus_we
- connect \Y $and$ls180.v:6226$1848_Y
+ connect \Y $and$ls180.v:6222$1848_Y
end
- attribute \src "ls180.v:6226.39-6226.143"
- cell $and $and$ls180.v:6226$1850
+ attribute \src "ls180.v:6222.39-6222.143"
+ cell $and $and$ls180.v:6222$1850
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6226$1848_Y
- connect \B $eq$ls180.v:6226$1849_Y
- connect \Y $and$ls180.v:6226$1850_Y
+ connect \A $and$ls180.v:6222$1848_Y
+ connect \B $eq$ls180.v:6222$1849_Y
+ connect \Y $and$ls180.v:6222$1850_Y
end
- attribute \src "ls180.v:6227.40-6227.96"
- cell $and $and$ls180.v:6227$1852
+ attribute \src "ls180.v:6223.40-6223.96"
+ cell $and $and$ls180.v:6223$1852
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank9_sel
- connect \B $not$ls180.v:6227$1851_Y
- connect \Y $and$ls180.v:6227$1852_Y
+ connect \B $not$ls180.v:6223$1851_Y
+ connect \Y $and$ls180.v:6223$1852_Y
end
- attribute \src "ls180.v:6227.39-6227.146"
- cell $and $and$ls180.v:6227$1854
+ attribute \src "ls180.v:6223.39-6223.146"
+ cell $and $and$ls180.v:6223$1854
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6227$1852_Y
- connect \B $eq$ls180.v:6227$1853_Y
- connect \Y $and$ls180.v:6227$1854_Y
+ connect \A $and$ls180.v:6223$1852_Y
+ connect \B $eq$ls180.v:6223$1853_Y
+ connect \Y $and$ls180.v:6223$1854_Y
end
- attribute \src "ls180.v:6229.50-6229.103"
- cell $and $and$ls180.v:6229$1855
+ attribute \src "ls180.v:6225.50-6225.103"
+ cell $and $and$ls180.v:6225$1855
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank9_sel
connect \B \builder_interface9_bank_bus_we
- connect \Y $and$ls180.v:6229$1855_Y
+ connect \Y $and$ls180.v:6225$1855_Y
end
- attribute \src "ls180.v:6229.49-6229.153"
- cell $and $and$ls180.v:6229$1857
+ attribute \src "ls180.v:6225.49-6225.153"
+ cell $and $and$ls180.v:6225$1857
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6229$1855_Y
- connect \B $eq$ls180.v:6229$1856_Y
- connect \Y $and$ls180.v:6229$1857_Y
+ connect \A $and$ls180.v:6225$1855_Y
+ connect \B $eq$ls180.v:6225$1856_Y
+ connect \Y $and$ls180.v:6225$1857_Y
end
- attribute \src "ls180.v:6230.50-6230.106"
- cell $and $and$ls180.v:6230$1859
+ attribute \src "ls180.v:6226.50-6226.106"
+ cell $and $and$ls180.v:6226$1859
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank9_sel
- connect \B $not$ls180.v:6230$1858_Y
- connect \Y $and$ls180.v:6230$1859_Y
+ connect \B $not$ls180.v:6226$1858_Y
+ connect \Y $and$ls180.v:6226$1859_Y
end
- attribute \src "ls180.v:6230.49-6230.156"
- cell $and $and$ls180.v:6230$1861
+ attribute \src "ls180.v:6226.49-6226.156"
+ cell $and $and$ls180.v:6226$1861
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6230$1859_Y
- connect \B $eq$ls180.v:6230$1860_Y
- connect \Y $and$ls180.v:6230$1861_Y
+ connect \A $and$ls180.v:6226$1859_Y
+ connect \B $eq$ls180.v:6226$1860_Y
+ connect \Y $and$ls180.v:6226$1861_Y
end
- attribute \src "ls180.v:6232.50-6232.103"
- cell $and $and$ls180.v:6232$1862
+ attribute \src "ls180.v:6228.50-6228.103"
+ cell $and $and$ls180.v:6228$1862
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank9_sel
connect \B \builder_interface9_bank_bus_we
- connect \Y $and$ls180.v:6232$1862_Y
+ connect \Y $and$ls180.v:6228$1862_Y
end
- attribute \src "ls180.v:6232.49-6232.153"
- cell $and $and$ls180.v:6232$1864
+ attribute \src "ls180.v:6228.49-6228.153"
+ cell $and $and$ls180.v:6228$1864
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6232$1862_Y
- connect \B $eq$ls180.v:6232$1863_Y
- connect \Y $and$ls180.v:6232$1864_Y
+ connect \A $and$ls180.v:6228$1862_Y
+ connect \B $eq$ls180.v:6228$1863_Y
+ connect \Y $and$ls180.v:6228$1864_Y
end
- attribute \src "ls180.v:6233.50-6233.106"
- cell $and $and$ls180.v:6233$1866
+ attribute \src "ls180.v:6229.50-6229.106"
+ cell $and $and$ls180.v:6229$1866
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank9_sel
- connect \B $not$ls180.v:6233$1865_Y
- connect \Y $and$ls180.v:6233$1866_Y
+ connect \B $not$ls180.v:6229$1865_Y
+ connect \Y $and$ls180.v:6229$1866_Y
end
- attribute \src "ls180.v:6233.49-6233.156"
- cell $and $and$ls180.v:6233$1868
+ attribute \src "ls180.v:6229.49-6229.156"
+ cell $and $and$ls180.v:6229$1868
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6233$1866_Y
- connect \B $eq$ls180.v:6233$1867_Y
- connect \Y $and$ls180.v:6233$1868_Y
+ connect \A $and$ls180.v:6229$1866_Y
+ connect \B $eq$ls180.v:6229$1867_Y
+ connect \Y $and$ls180.v:6229$1868_Y
end
- attribute \src "ls180.v:6235.51-6235.104"
- cell $and $and$ls180.v:6235$1869
+ attribute \src "ls180.v:6231.51-6231.104"
+ cell $and $and$ls180.v:6231$1869
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank9_sel
connect \B \builder_interface9_bank_bus_we
- connect \Y $and$ls180.v:6235$1869_Y
+ connect \Y $and$ls180.v:6231$1869_Y
end
- attribute \src "ls180.v:6235.50-6235.154"
- cell $and $and$ls180.v:6235$1871
+ attribute \src "ls180.v:6231.50-6231.154"
+ cell $and $and$ls180.v:6231$1871
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6235$1869_Y
- connect \B $eq$ls180.v:6235$1870_Y
- connect \Y $and$ls180.v:6235$1871_Y
+ connect \A $and$ls180.v:6231$1869_Y
+ connect \B $eq$ls180.v:6231$1870_Y
+ connect \Y $and$ls180.v:6231$1871_Y
end
- attribute \src "ls180.v:6236.51-6236.107"
- cell $and $and$ls180.v:6236$1873
+ attribute \src "ls180.v:6232.51-6232.107"
+ cell $and $and$ls180.v:6232$1873
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank9_sel
- connect \B $not$ls180.v:6236$1872_Y
- connect \Y $and$ls180.v:6236$1873_Y
+ connect \B $not$ls180.v:6232$1872_Y
+ connect \Y $and$ls180.v:6232$1873_Y
end
- attribute \src "ls180.v:6236.50-6236.157"
- cell $and $and$ls180.v:6236$1875
+ attribute \src "ls180.v:6232.50-6232.157"
+ cell $and $and$ls180.v:6232$1875
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6236$1873_Y
- connect \B $eq$ls180.v:6236$1874_Y
- connect \Y $and$ls180.v:6236$1875_Y
+ connect \A $and$ls180.v:6232$1873_Y
+ connect \B $eq$ls180.v:6232$1874_Y
+ connect \Y $and$ls180.v:6232$1875_Y
end
- attribute \src "ls180.v:6238.49-6238.102"
- cell $and $and$ls180.v:6238$1876
+ attribute \src "ls180.v:6234.49-6234.102"
+ cell $and $and$ls180.v:6234$1876
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank9_sel
connect \B \builder_interface9_bank_bus_we
- connect \Y $and$ls180.v:6238$1876_Y
+ connect \Y $and$ls180.v:6234$1876_Y
end
- attribute \src "ls180.v:6238.48-6238.152"
- cell $and $and$ls180.v:6238$1878
+ attribute \src "ls180.v:6234.48-6234.152"
+ cell $and $and$ls180.v:6234$1878
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6238$1876_Y
- connect \B $eq$ls180.v:6238$1877_Y
- connect \Y $and$ls180.v:6238$1878_Y
+ connect \A $and$ls180.v:6234$1876_Y
+ connect \B $eq$ls180.v:6234$1877_Y
+ connect \Y $and$ls180.v:6234$1878_Y
end
- attribute \src "ls180.v:6239.49-6239.105"
- cell $and $and$ls180.v:6239$1880
+ attribute \src "ls180.v:6235.49-6235.105"
+ cell $and $and$ls180.v:6235$1880
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank9_sel
- connect \B $not$ls180.v:6239$1879_Y
- connect \Y $and$ls180.v:6239$1880_Y
+ connect \B $not$ls180.v:6235$1879_Y
+ connect \Y $and$ls180.v:6235$1880_Y
end
- attribute \src "ls180.v:6239.48-6239.155"
- cell $and $and$ls180.v:6239$1882
+ attribute \src "ls180.v:6235.48-6235.155"
+ cell $and $and$ls180.v:6235$1882
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6239$1880_Y
- connect \B $eq$ls180.v:6239$1881_Y
- connect \Y $and$ls180.v:6239$1882_Y
+ connect \A $and$ls180.v:6235$1880_Y
+ connect \B $eq$ls180.v:6235$1881_Y
+ connect \Y $and$ls180.v:6235$1882_Y
end
- attribute \src "ls180.v:6241.49-6241.102"
- cell $and $and$ls180.v:6241$1883
+ attribute \src "ls180.v:6237.49-6237.102"
+ cell $and $and$ls180.v:6237$1883
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank9_sel
connect \B \builder_interface9_bank_bus_we
- connect \Y $and$ls180.v:6241$1883_Y
+ connect \Y $and$ls180.v:6237$1883_Y
end
- attribute \src "ls180.v:6241.48-6241.152"
- cell $and $and$ls180.v:6241$1885
+ attribute \src "ls180.v:6237.48-6237.152"
+ cell $and $and$ls180.v:6237$1885
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6241$1883_Y
- connect \B $eq$ls180.v:6241$1884_Y
- connect \Y $and$ls180.v:6241$1885_Y
+ connect \A $and$ls180.v:6237$1883_Y
+ connect \B $eq$ls180.v:6237$1884_Y
+ connect \Y $and$ls180.v:6237$1885_Y
end
- attribute \src "ls180.v:6242.49-6242.105"
- cell $and $and$ls180.v:6242$1887
+ attribute \src "ls180.v:6238.49-6238.105"
+ cell $and $and$ls180.v:6238$1887
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank9_sel
- connect \B $not$ls180.v:6242$1886_Y
- connect \Y $and$ls180.v:6242$1887_Y
+ connect \B $not$ls180.v:6238$1886_Y
+ connect \Y $and$ls180.v:6238$1887_Y
end
- attribute \src "ls180.v:6242.48-6242.155"
- cell $and $and$ls180.v:6242$1889
+ attribute \src "ls180.v:6238.48-6238.155"
+ cell $and $and$ls180.v:6238$1889
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6242$1887_Y
- connect \B $eq$ls180.v:6242$1888_Y
- connect \Y $and$ls180.v:6242$1889_Y
+ connect \A $and$ls180.v:6238$1887_Y
+ connect \B $eq$ls180.v:6238$1888_Y
+ connect \Y $and$ls180.v:6238$1889_Y
end
- attribute \src "ls180.v:6244.49-6244.102"
- cell $and $and$ls180.v:6244$1890
+ attribute \src "ls180.v:6240.49-6240.102"
+ cell $and $and$ls180.v:6240$1890
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank9_sel
connect \B \builder_interface9_bank_bus_we
- connect \Y $and$ls180.v:6244$1890_Y
+ connect \Y $and$ls180.v:6240$1890_Y
end
- attribute \src "ls180.v:6244.48-6244.152"
- cell $and $and$ls180.v:6244$1892
+ attribute \src "ls180.v:6240.48-6240.152"
+ cell $and $and$ls180.v:6240$1892
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6244$1890_Y
- connect \B $eq$ls180.v:6244$1891_Y
- connect \Y $and$ls180.v:6244$1892_Y
+ connect \A $and$ls180.v:6240$1890_Y
+ connect \B $eq$ls180.v:6240$1891_Y
+ connect \Y $and$ls180.v:6240$1892_Y
end
- attribute \src "ls180.v:6245.49-6245.105"
- cell $and $and$ls180.v:6245$1894
+ attribute \src "ls180.v:6241.49-6241.105"
+ cell $and $and$ls180.v:6241$1894
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank9_sel
- connect \B $not$ls180.v:6245$1893_Y
- connect \Y $and$ls180.v:6245$1894_Y
+ connect \B $not$ls180.v:6241$1893_Y
+ connect \Y $and$ls180.v:6241$1894_Y
end
- attribute \src "ls180.v:6245.48-6245.155"
- cell $and $and$ls180.v:6245$1896
+ attribute \src "ls180.v:6241.48-6241.155"
+ cell $and $and$ls180.v:6241$1896
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6245$1894_Y
- connect \B $eq$ls180.v:6245$1895_Y
- connect \Y $and$ls180.v:6245$1896_Y
+ connect \A $and$ls180.v:6241$1894_Y
+ connect \B $eq$ls180.v:6241$1895_Y
+ connect \Y $and$ls180.v:6241$1896_Y
end
- attribute \src "ls180.v:6247.49-6247.102"
- cell $and $and$ls180.v:6247$1897
+ attribute \src "ls180.v:6243.49-6243.102"
+ cell $and $and$ls180.v:6243$1897
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank9_sel
connect \B \builder_interface9_bank_bus_we
- connect \Y $and$ls180.v:6247$1897_Y
+ connect \Y $and$ls180.v:6243$1897_Y
end
- attribute \src "ls180.v:6247.48-6247.152"
- cell $and $and$ls180.v:6247$1899
+ attribute \src "ls180.v:6243.48-6243.152"
+ cell $and $and$ls180.v:6243$1899
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6247$1897_Y
- connect \B $eq$ls180.v:6247$1898_Y
- connect \Y $and$ls180.v:6247$1899_Y
+ connect \A $and$ls180.v:6243$1897_Y
+ connect \B $eq$ls180.v:6243$1898_Y
+ connect \Y $and$ls180.v:6243$1899_Y
end
- attribute \src "ls180.v:6248.49-6248.105"
- cell $and $and$ls180.v:6248$1901
+ attribute \src "ls180.v:6244.49-6244.105"
+ cell $and $and$ls180.v:6244$1901
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank9_sel
- connect \B $not$ls180.v:6248$1900_Y
- connect \Y $and$ls180.v:6248$1901_Y
+ connect \B $not$ls180.v:6244$1900_Y
+ connect \Y $and$ls180.v:6244$1901_Y
end
- attribute \src "ls180.v:6248.48-6248.155"
- cell $and $and$ls180.v:6248$1903
+ attribute \src "ls180.v:6244.48-6244.155"
+ cell $and $and$ls180.v:6244$1903
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6248$1901_Y
- connect \B $eq$ls180.v:6248$1902_Y
- connect \Y $and$ls180.v:6248$1903_Y
+ connect \A $and$ls180.v:6244$1901_Y
+ connect \B $eq$ls180.v:6244$1902_Y
+ connect \Y $and$ls180.v:6244$1903_Y
end
- attribute \src "ls180.v:6265.42-6265.97"
- cell $and $and$ls180.v:6265$1905
+ attribute \src "ls180.v:6261.42-6261.97"
+ cell $and $and$ls180.v:6261$1905
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank10_sel
connect \B \builder_interface10_bank_bus_we
- connect \Y $and$ls180.v:6265$1905_Y
+ connect \Y $and$ls180.v:6261$1905_Y
end
- attribute \src "ls180.v:6265.41-6265.148"
- cell $and $and$ls180.v:6265$1907
+ attribute \src "ls180.v:6261.41-6261.148"
+ cell $and $and$ls180.v:6261$1907
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6265$1905_Y
- connect \B $eq$ls180.v:6265$1906_Y
- connect \Y $and$ls180.v:6265$1907_Y
+ connect \A $and$ls180.v:6261$1905_Y
+ connect \B $eq$ls180.v:6261$1906_Y
+ connect \Y $and$ls180.v:6261$1907_Y
end
- attribute \src "ls180.v:6266.42-6266.100"
- cell $and $and$ls180.v:6266$1909
+ attribute \src "ls180.v:6262.42-6262.100"
+ cell $and $and$ls180.v:6262$1909
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank10_sel
- connect \B $not$ls180.v:6266$1908_Y
- connect \Y $and$ls180.v:6266$1909_Y
+ connect \B $not$ls180.v:6262$1908_Y
+ connect \Y $and$ls180.v:6262$1909_Y
end
- attribute \src "ls180.v:6266.41-6266.151"
- cell $and $and$ls180.v:6266$1911
+ attribute \src "ls180.v:6262.41-6262.151"
+ cell $and $and$ls180.v:6262$1911
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6266$1909_Y
- connect \B $eq$ls180.v:6266$1910_Y
- connect \Y $and$ls180.v:6266$1911_Y
+ connect \A $and$ls180.v:6262$1909_Y
+ connect \B $eq$ls180.v:6262$1910_Y
+ connect \Y $and$ls180.v:6262$1911_Y
end
- attribute \src "ls180.v:6268.42-6268.97"
- cell $and $and$ls180.v:6268$1912
+ attribute \src "ls180.v:6264.42-6264.97"
+ cell $and $and$ls180.v:6264$1912
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank10_sel
connect \B \builder_interface10_bank_bus_we
- connect \Y $and$ls180.v:6268$1912_Y
+ connect \Y $and$ls180.v:6264$1912_Y
end
- attribute \src "ls180.v:6268.41-6268.148"
- cell $and $and$ls180.v:6268$1914
+ attribute \src "ls180.v:6264.41-6264.148"
+ cell $and $and$ls180.v:6264$1914
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6268$1912_Y
- connect \B $eq$ls180.v:6268$1913_Y
- connect \Y $and$ls180.v:6268$1914_Y
+ connect \A $and$ls180.v:6264$1912_Y
+ connect \B $eq$ls180.v:6264$1913_Y
+ connect \Y $and$ls180.v:6264$1914_Y
end
- attribute \src "ls180.v:6269.42-6269.100"
- cell $and $and$ls180.v:6269$1916
+ attribute \src "ls180.v:6265.42-6265.100"
+ cell $and $and$ls180.v:6265$1916
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank10_sel
- connect \B $not$ls180.v:6269$1915_Y
- connect \Y $and$ls180.v:6269$1916_Y
+ connect \B $not$ls180.v:6265$1915_Y
+ connect \Y $and$ls180.v:6265$1916_Y
end
- attribute \src "ls180.v:6269.41-6269.151"
- cell $and $and$ls180.v:6269$1918
+ attribute \src "ls180.v:6265.41-6265.151"
+ cell $and $and$ls180.v:6265$1918
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6269$1916_Y
- connect \B $eq$ls180.v:6269$1917_Y
- connect \Y $and$ls180.v:6269$1918_Y
+ connect \A $and$ls180.v:6265$1916_Y
+ connect \B $eq$ls180.v:6265$1917_Y
+ connect \Y $and$ls180.v:6265$1918_Y
end
- attribute \src "ls180.v:6271.40-6271.95"
- cell $and $and$ls180.v:6271$1919
+ attribute \src "ls180.v:6267.40-6267.95"
+ cell $and $and$ls180.v:6267$1919
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank10_sel
connect \B \builder_interface10_bank_bus_we
- connect \Y $and$ls180.v:6271$1919_Y
+ connect \Y $and$ls180.v:6267$1919_Y
end
- attribute \src "ls180.v:6271.39-6271.146"
- cell $and $and$ls180.v:6271$1921
+ attribute \src "ls180.v:6267.39-6267.146"
+ cell $and $and$ls180.v:6267$1921
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6271$1919_Y
- connect \B $eq$ls180.v:6271$1920_Y
- connect \Y $and$ls180.v:6271$1921_Y
+ connect \A $and$ls180.v:6267$1919_Y
+ connect \B $eq$ls180.v:6267$1920_Y
+ connect \Y $and$ls180.v:6267$1921_Y
end
- attribute \src "ls180.v:6272.40-6272.98"
- cell $and $and$ls180.v:6272$1923
+ attribute \src "ls180.v:6268.40-6268.98"
+ cell $and $and$ls180.v:6268$1923
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank10_sel
- connect \B $not$ls180.v:6272$1922_Y
- connect \Y $and$ls180.v:6272$1923_Y
+ connect \B $not$ls180.v:6268$1922_Y
+ connect \Y $and$ls180.v:6268$1923_Y
end
- attribute \src "ls180.v:6272.39-6272.149"
- cell $and $and$ls180.v:6272$1925
+ attribute \src "ls180.v:6268.39-6268.149"
+ cell $and $and$ls180.v:6268$1925
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6272$1923_Y
- connect \B $eq$ls180.v:6272$1924_Y
- connect \Y $and$ls180.v:6272$1925_Y
+ connect \A $and$ls180.v:6268$1923_Y
+ connect \B $eq$ls180.v:6268$1924_Y
+ connect \Y $and$ls180.v:6268$1925_Y
end
- attribute \src "ls180.v:6274.39-6274.94"
- cell $and $and$ls180.v:6274$1926
+ attribute \src "ls180.v:6270.39-6270.94"
+ cell $and $and$ls180.v:6270$1926
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank10_sel
connect \B \builder_interface10_bank_bus_we
- connect \Y $and$ls180.v:6274$1926_Y
+ connect \Y $and$ls180.v:6270$1926_Y
end
- attribute \src "ls180.v:6274.38-6274.145"
- cell $and $and$ls180.v:6274$1928
+ attribute \src "ls180.v:6270.38-6270.145"
+ cell $and $and$ls180.v:6270$1928
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6274$1926_Y
- connect \B $eq$ls180.v:6274$1927_Y
- connect \Y $and$ls180.v:6274$1928_Y
+ connect \A $and$ls180.v:6270$1926_Y
+ connect \B $eq$ls180.v:6270$1927_Y
+ connect \Y $and$ls180.v:6270$1928_Y
end
- attribute \src "ls180.v:6275.39-6275.97"
- cell $and $and$ls180.v:6275$1930
+ attribute \src "ls180.v:6271.39-6271.97"
+ cell $and $and$ls180.v:6271$1930
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank10_sel
- connect \B $not$ls180.v:6275$1929_Y
- connect \Y $and$ls180.v:6275$1930_Y
+ connect \B $not$ls180.v:6271$1929_Y
+ connect \Y $and$ls180.v:6271$1930_Y
end
- attribute \src "ls180.v:6275.38-6275.148"
- cell $and $and$ls180.v:6275$1932
+ attribute \src "ls180.v:6271.38-6271.148"
+ cell $and $and$ls180.v:6271$1932
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6275$1930_Y
- connect \B $eq$ls180.v:6275$1931_Y
- connect \Y $and$ls180.v:6275$1932_Y
+ connect \A $and$ls180.v:6271$1930_Y
+ connect \B $eq$ls180.v:6271$1931_Y
+ connect \Y $and$ls180.v:6271$1932_Y
end
- attribute \src "ls180.v:6277.38-6277.93"
- cell $and $and$ls180.v:6277$1933
+ attribute \src "ls180.v:6273.38-6273.93"
+ cell $and $and$ls180.v:6273$1933
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank10_sel
connect \B \builder_interface10_bank_bus_we
- connect \Y $and$ls180.v:6277$1933_Y
+ connect \Y $and$ls180.v:6273$1933_Y
end
- attribute \src "ls180.v:6277.37-6277.144"
- cell $and $and$ls180.v:6277$1935
+ attribute \src "ls180.v:6273.37-6273.144"
+ cell $and $and$ls180.v:6273$1935
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6277$1933_Y
- connect \B $eq$ls180.v:6277$1934_Y
- connect \Y $and$ls180.v:6277$1935_Y
+ connect \A $and$ls180.v:6273$1933_Y
+ connect \B $eq$ls180.v:6273$1934_Y
+ connect \Y $and$ls180.v:6273$1935_Y
end
- attribute \src "ls180.v:6278.38-6278.96"
- cell $and $and$ls180.v:6278$1937
+ attribute \src "ls180.v:6274.38-6274.96"
+ cell $and $and$ls180.v:6274$1937
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank10_sel
- connect \B $not$ls180.v:6278$1936_Y
- connect \Y $and$ls180.v:6278$1937_Y
+ connect \B $not$ls180.v:6274$1936_Y
+ connect \Y $and$ls180.v:6274$1937_Y
end
- attribute \src "ls180.v:6278.37-6278.147"
- cell $and $and$ls180.v:6278$1939
+ attribute \src "ls180.v:6274.37-6274.147"
+ cell $and $and$ls180.v:6274$1939
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6278$1937_Y
- connect \B $eq$ls180.v:6278$1938_Y
- connect \Y $and$ls180.v:6278$1939_Y
+ connect \A $and$ls180.v:6274$1937_Y
+ connect \B $eq$ls180.v:6274$1938_Y
+ connect \Y $and$ls180.v:6274$1939_Y
end
- attribute \src "ls180.v:6280.37-6280.92"
- cell $and $and$ls180.v:6280$1940
+ attribute \src "ls180.v:6276.37-6276.92"
+ cell $and $and$ls180.v:6276$1940
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank10_sel
connect \B \builder_interface10_bank_bus_we
- connect \Y $and$ls180.v:6280$1940_Y
+ connect \Y $and$ls180.v:6276$1940_Y
end
- attribute \src "ls180.v:6280.36-6280.143"
- cell $and $and$ls180.v:6280$1942
+ attribute \src "ls180.v:6276.36-6276.143"
+ cell $and $and$ls180.v:6276$1942
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6280$1940_Y
- connect \B $eq$ls180.v:6280$1941_Y
- connect \Y $and$ls180.v:6280$1942_Y
+ connect \A $and$ls180.v:6276$1940_Y
+ connect \B $eq$ls180.v:6276$1941_Y
+ connect \Y $and$ls180.v:6276$1942_Y
end
- attribute \src "ls180.v:6281.37-6281.95"
- cell $and $and$ls180.v:6281$1944
+ attribute \src "ls180.v:6277.37-6277.95"
+ cell $and $and$ls180.v:6277$1944
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank10_sel
- connect \B $not$ls180.v:6281$1943_Y
- connect \Y $and$ls180.v:6281$1944_Y
+ connect \B $not$ls180.v:6277$1943_Y
+ connect \Y $and$ls180.v:6277$1944_Y
end
- attribute \src "ls180.v:6281.36-6281.146"
- cell $and $and$ls180.v:6281$1946
+ attribute \src "ls180.v:6277.36-6277.146"
+ cell $and $and$ls180.v:6277$1946
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6281$1944_Y
- connect \B $eq$ls180.v:6281$1945_Y
- connect \Y $and$ls180.v:6281$1946_Y
+ connect \A $and$ls180.v:6277$1944_Y
+ connect \B $eq$ls180.v:6277$1945_Y
+ connect \Y $and$ls180.v:6277$1946_Y
end
- attribute \src "ls180.v:6283.43-6283.98"
- cell $and $and$ls180.v:6283$1947
+ attribute \src "ls180.v:6279.43-6279.98"
+ cell $and $and$ls180.v:6279$1947
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank10_sel
connect \B \builder_interface10_bank_bus_we
- connect \Y $and$ls180.v:6283$1947_Y
+ connect \Y $and$ls180.v:6279$1947_Y
end
- attribute \src "ls180.v:6283.42-6283.149"
- cell $and $and$ls180.v:6283$1949
+ attribute \src "ls180.v:6279.42-6279.149"
+ cell $and $and$ls180.v:6279$1949
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6283$1947_Y
- connect \B $eq$ls180.v:6283$1948_Y
- connect \Y $and$ls180.v:6283$1949_Y
+ connect \A $and$ls180.v:6279$1947_Y
+ connect \B $eq$ls180.v:6279$1948_Y
+ connect \Y $and$ls180.v:6279$1949_Y
end
- attribute \src "ls180.v:6284.43-6284.101"
- cell $and $and$ls180.v:6284$1951
+ attribute \src "ls180.v:6280.43-6280.101"
+ cell $and $and$ls180.v:6280$1951
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank10_sel
- connect \B $not$ls180.v:6284$1950_Y
- connect \Y $and$ls180.v:6284$1951_Y
+ connect \B $not$ls180.v:6280$1950_Y
+ connect \Y $and$ls180.v:6280$1951_Y
end
- attribute \src "ls180.v:6284.42-6284.152"
- cell $and $and$ls180.v:6284$1953
+ attribute \src "ls180.v:6280.42-6280.152"
+ cell $and $and$ls180.v:6280$1953
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6284$1951_Y
- connect \B $eq$ls180.v:6284$1952_Y
- connect \Y $and$ls180.v:6284$1953_Y
+ connect \A $and$ls180.v:6280$1951_Y
+ connect \B $eq$ls180.v:6280$1952_Y
+ connect \Y $and$ls180.v:6280$1953_Y
end
- attribute \src "ls180.v:6305.42-6305.97"
- cell $and $and$ls180.v:6305$1956
+ attribute \src "ls180.v:6301.42-6301.97"
+ cell $and $and$ls180.v:6301$1956
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank11_sel
connect \B \builder_interface11_bank_bus_we
- connect \Y $and$ls180.v:6305$1956_Y
+ connect \Y $and$ls180.v:6301$1956_Y
end
- attribute \src "ls180.v:6305.41-6305.148"
- cell $and $and$ls180.v:6305$1958
+ attribute \src "ls180.v:6301.41-6301.148"
+ cell $and $and$ls180.v:6301$1958
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6305$1956_Y
- connect \B $eq$ls180.v:6305$1957_Y
- connect \Y $and$ls180.v:6305$1958_Y
+ connect \A $and$ls180.v:6301$1956_Y
+ connect \B $eq$ls180.v:6301$1957_Y
+ connect \Y $and$ls180.v:6301$1958_Y
end
- attribute \src "ls180.v:6306.42-6306.100"
- cell $and $and$ls180.v:6306$1960
+ attribute \src "ls180.v:6302.42-6302.100"
+ cell $and $and$ls180.v:6302$1960
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank11_sel
- connect \B $not$ls180.v:6306$1959_Y
- connect \Y $and$ls180.v:6306$1960_Y
+ connect \B $not$ls180.v:6302$1959_Y
+ connect \Y $and$ls180.v:6302$1960_Y
end
- attribute \src "ls180.v:6306.41-6306.151"
- cell $and $and$ls180.v:6306$1962
+ attribute \src "ls180.v:6302.41-6302.151"
+ cell $and $and$ls180.v:6302$1962
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6306$1960_Y
- connect \B $eq$ls180.v:6306$1961_Y
- connect \Y $and$ls180.v:6306$1962_Y
+ connect \A $and$ls180.v:6302$1960_Y
+ connect \B $eq$ls180.v:6302$1961_Y
+ connect \Y $and$ls180.v:6302$1962_Y
end
- attribute \src "ls180.v:6308.42-6308.97"
- cell $and $and$ls180.v:6308$1963
+ attribute \src "ls180.v:6304.42-6304.97"
+ cell $and $and$ls180.v:6304$1963
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank11_sel
connect \B \builder_interface11_bank_bus_we
- connect \Y $and$ls180.v:6308$1963_Y
+ connect \Y $and$ls180.v:6304$1963_Y
end
- attribute \src "ls180.v:6308.41-6308.148"
- cell $and $and$ls180.v:6308$1965
+ attribute \src "ls180.v:6304.41-6304.148"
+ cell $and $and$ls180.v:6304$1965
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6308$1963_Y
- connect \B $eq$ls180.v:6308$1964_Y
- connect \Y $and$ls180.v:6308$1965_Y
+ connect \A $and$ls180.v:6304$1963_Y
+ connect \B $eq$ls180.v:6304$1964_Y
+ connect \Y $and$ls180.v:6304$1965_Y
end
- attribute \src "ls180.v:6309.42-6309.100"
- cell $and $and$ls180.v:6309$1967
+ attribute \src "ls180.v:6305.42-6305.100"
+ cell $and $and$ls180.v:6305$1967
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank11_sel
- connect \B $not$ls180.v:6309$1966_Y
- connect \Y $and$ls180.v:6309$1967_Y
+ connect \B $not$ls180.v:6305$1966_Y
+ connect \Y $and$ls180.v:6305$1967_Y
end
- attribute \src "ls180.v:6309.41-6309.151"
- cell $and $and$ls180.v:6309$1969
+ attribute \src "ls180.v:6305.41-6305.151"
+ cell $and $and$ls180.v:6305$1969
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6309$1967_Y
- connect \B $eq$ls180.v:6309$1968_Y
- connect \Y $and$ls180.v:6309$1969_Y
+ connect \A $and$ls180.v:6305$1967_Y
+ connect \B $eq$ls180.v:6305$1968_Y
+ connect \Y $and$ls180.v:6305$1969_Y
end
- attribute \src "ls180.v:6311.40-6311.95"
- cell $and $and$ls180.v:6311$1970
+ attribute \src "ls180.v:6307.40-6307.95"
+ cell $and $and$ls180.v:6307$1970
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank11_sel
connect \B \builder_interface11_bank_bus_we
- connect \Y $and$ls180.v:6311$1970_Y
+ connect \Y $and$ls180.v:6307$1970_Y
end
- attribute \src "ls180.v:6311.39-6311.146"
- cell $and $and$ls180.v:6311$1972
+ attribute \src "ls180.v:6307.39-6307.146"
+ cell $and $and$ls180.v:6307$1972
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6311$1970_Y
- connect \B $eq$ls180.v:6311$1971_Y
- connect \Y $and$ls180.v:6311$1972_Y
+ connect \A $and$ls180.v:6307$1970_Y
+ connect \B $eq$ls180.v:6307$1971_Y
+ connect \Y $and$ls180.v:6307$1972_Y
end
- attribute \src "ls180.v:6312.40-6312.98"
- cell $and $and$ls180.v:6312$1974
+ attribute \src "ls180.v:6308.40-6308.98"
+ cell $and $and$ls180.v:6308$1974
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank11_sel
- connect \B $not$ls180.v:6312$1973_Y
- connect \Y $and$ls180.v:6312$1974_Y
+ connect \B $not$ls180.v:6308$1973_Y
+ connect \Y $and$ls180.v:6308$1974_Y
end
- attribute \src "ls180.v:6312.39-6312.149"
- cell $and $and$ls180.v:6312$1976
+ attribute \src "ls180.v:6308.39-6308.149"
+ cell $and $and$ls180.v:6308$1976
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6312$1974_Y
- connect \B $eq$ls180.v:6312$1975_Y
- connect \Y $and$ls180.v:6312$1976_Y
+ connect \A $and$ls180.v:6308$1974_Y
+ connect \B $eq$ls180.v:6308$1975_Y
+ connect \Y $and$ls180.v:6308$1976_Y
end
- attribute \src "ls180.v:6314.39-6314.94"
- cell $and $and$ls180.v:6314$1977
+ attribute \src "ls180.v:6310.39-6310.94"
+ cell $and $and$ls180.v:6310$1977
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank11_sel
connect \B \builder_interface11_bank_bus_we
- connect \Y $and$ls180.v:6314$1977_Y
+ connect \Y $and$ls180.v:6310$1977_Y
end
- attribute \src "ls180.v:6314.38-6314.145"
- cell $and $and$ls180.v:6314$1979
+ attribute \src "ls180.v:6310.38-6310.145"
+ cell $and $and$ls180.v:6310$1979
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6314$1977_Y
- connect \B $eq$ls180.v:6314$1978_Y
- connect \Y $and$ls180.v:6314$1979_Y
+ connect \A $and$ls180.v:6310$1977_Y
+ connect \B $eq$ls180.v:6310$1978_Y
+ connect \Y $and$ls180.v:6310$1979_Y
end
- attribute \src "ls180.v:6315.39-6315.97"
- cell $and $and$ls180.v:6315$1981
+ attribute \src "ls180.v:6311.39-6311.97"
+ cell $and $and$ls180.v:6311$1981
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank11_sel
- connect \B $not$ls180.v:6315$1980_Y
- connect \Y $and$ls180.v:6315$1981_Y
+ connect \B $not$ls180.v:6311$1980_Y
+ connect \Y $and$ls180.v:6311$1981_Y
end
- attribute \src "ls180.v:6315.38-6315.148"
- cell $and $and$ls180.v:6315$1983
+ attribute \src "ls180.v:6311.38-6311.148"
+ cell $and $and$ls180.v:6311$1983
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6315$1981_Y
- connect \B $eq$ls180.v:6315$1982_Y
- connect \Y $and$ls180.v:6315$1983_Y
+ connect \A $and$ls180.v:6311$1981_Y
+ connect \B $eq$ls180.v:6311$1982_Y
+ connect \Y $and$ls180.v:6311$1983_Y
end
- attribute \src "ls180.v:6317.38-6317.93"
- cell $and $and$ls180.v:6317$1984
+ attribute \src "ls180.v:6313.38-6313.93"
+ cell $and $and$ls180.v:6313$1984
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank11_sel
connect \B \builder_interface11_bank_bus_we
- connect \Y $and$ls180.v:6317$1984_Y
+ connect \Y $and$ls180.v:6313$1984_Y
end
- attribute \src "ls180.v:6317.37-6317.144"
- cell $and $and$ls180.v:6317$1986
+ attribute \src "ls180.v:6313.37-6313.144"
+ cell $and $and$ls180.v:6313$1986
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6317$1984_Y
- connect \B $eq$ls180.v:6317$1985_Y
- connect \Y $and$ls180.v:6317$1986_Y
+ connect \A $and$ls180.v:6313$1984_Y
+ connect \B $eq$ls180.v:6313$1985_Y
+ connect \Y $and$ls180.v:6313$1986_Y
end
- attribute \src "ls180.v:6318.38-6318.96"
- cell $and $and$ls180.v:6318$1988
+ attribute \src "ls180.v:6314.38-6314.96"
+ cell $and $and$ls180.v:6314$1988
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank11_sel
- connect \B $not$ls180.v:6318$1987_Y
- connect \Y $and$ls180.v:6318$1988_Y
+ connect \B $not$ls180.v:6314$1987_Y
+ connect \Y $and$ls180.v:6314$1988_Y
end
- attribute \src "ls180.v:6318.37-6318.147"
- cell $and $and$ls180.v:6318$1990
+ attribute \src "ls180.v:6314.37-6314.147"
+ cell $and $and$ls180.v:6314$1990
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6318$1988_Y
- connect \B $eq$ls180.v:6318$1989_Y
- connect \Y $and$ls180.v:6318$1990_Y
+ connect \A $and$ls180.v:6314$1988_Y
+ connect \B $eq$ls180.v:6314$1989_Y
+ connect \Y $and$ls180.v:6314$1990_Y
end
- attribute \src "ls180.v:6320.37-6320.92"
- cell $and $and$ls180.v:6320$1991
+ attribute \src "ls180.v:6316.37-6316.92"
+ cell $and $and$ls180.v:6316$1991
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank11_sel
connect \B \builder_interface11_bank_bus_we
- connect \Y $and$ls180.v:6320$1991_Y
+ connect \Y $and$ls180.v:6316$1991_Y
end
- attribute \src "ls180.v:6320.36-6320.143"
- cell $and $and$ls180.v:6320$1993
+ attribute \src "ls180.v:6316.36-6316.143"
+ cell $and $and$ls180.v:6316$1993
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6320$1991_Y
- connect \B $eq$ls180.v:6320$1992_Y
- connect \Y $and$ls180.v:6320$1993_Y
+ connect \A $and$ls180.v:6316$1991_Y
+ connect \B $eq$ls180.v:6316$1992_Y
+ connect \Y $and$ls180.v:6316$1993_Y
end
- attribute \src "ls180.v:6321.37-6321.95"
- cell $and $and$ls180.v:6321$1995
+ attribute \src "ls180.v:6317.37-6317.95"
+ cell $and $and$ls180.v:6317$1995
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank11_sel
- connect \B $not$ls180.v:6321$1994_Y
- connect \Y $and$ls180.v:6321$1995_Y
+ connect \B $not$ls180.v:6317$1994_Y
+ connect \Y $and$ls180.v:6317$1995_Y
end
- attribute \src "ls180.v:6321.36-6321.146"
- cell $and $and$ls180.v:6321$1997
+ attribute \src "ls180.v:6317.36-6317.146"
+ cell $and $and$ls180.v:6317$1997
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6321$1995_Y
- connect \B $eq$ls180.v:6321$1996_Y
- connect \Y $and$ls180.v:6321$1997_Y
+ connect \A $and$ls180.v:6317$1995_Y
+ connect \B $eq$ls180.v:6317$1996_Y
+ connect \Y $and$ls180.v:6317$1997_Y
end
- attribute \src "ls180.v:6323.43-6323.98"
- cell $and $and$ls180.v:6323$1998
+ attribute \src "ls180.v:6319.43-6319.98"
+ cell $and $and$ls180.v:6319$1998
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank11_sel
connect \B \builder_interface11_bank_bus_we
- connect \Y $and$ls180.v:6323$1998_Y
+ connect \Y $and$ls180.v:6319$1998_Y
end
- attribute \src "ls180.v:6323.42-6323.149"
- cell $and $and$ls180.v:6323$2000
+ attribute \src "ls180.v:6319.42-6319.149"
+ cell $and $and$ls180.v:6319$2000
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6323$1998_Y
- connect \B $eq$ls180.v:6323$1999_Y
- connect \Y $and$ls180.v:6323$2000_Y
+ connect \A $and$ls180.v:6319$1998_Y
+ connect \B $eq$ls180.v:6319$1999_Y
+ connect \Y $and$ls180.v:6319$2000_Y
end
- attribute \src "ls180.v:6324.43-6324.101"
- cell $and $and$ls180.v:6324$2002
+ attribute \src "ls180.v:6320.43-6320.101"
+ cell $and $and$ls180.v:6320$2002
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank11_sel
- connect \B $not$ls180.v:6324$2001_Y
- connect \Y $and$ls180.v:6324$2002_Y
+ connect \B $not$ls180.v:6320$2001_Y
+ connect \Y $and$ls180.v:6320$2002_Y
end
- attribute \src "ls180.v:6324.42-6324.152"
- cell $and $and$ls180.v:6324$2004
+ attribute \src "ls180.v:6320.42-6320.152"
+ cell $and $and$ls180.v:6320$2004
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6324$2002_Y
- connect \B $eq$ls180.v:6324$2003_Y
- connect \Y $and$ls180.v:6324$2004_Y
+ connect \A $and$ls180.v:6320$2002_Y
+ connect \B $eq$ls180.v:6320$2003_Y
+ connect \Y $and$ls180.v:6320$2004_Y
end
- attribute \src "ls180.v:6326.46-6326.101"
- cell $and $and$ls180.v:6326$2005
+ attribute \src "ls180.v:6322.46-6322.101"
+ cell $and $and$ls180.v:6322$2005
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank11_sel
connect \B \builder_interface11_bank_bus_we
- connect \Y $and$ls180.v:6326$2005_Y
+ connect \Y $and$ls180.v:6322$2005_Y
end
- attribute \src "ls180.v:6326.45-6326.152"
- cell $and $and$ls180.v:6326$2007
+ attribute \src "ls180.v:6322.45-6322.152"
+ cell $and $and$ls180.v:6322$2007
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6326$2005_Y
- connect \B $eq$ls180.v:6326$2006_Y
- connect \Y $and$ls180.v:6326$2007_Y
+ connect \A $and$ls180.v:6322$2005_Y
+ connect \B $eq$ls180.v:6322$2006_Y
+ connect \Y $and$ls180.v:6322$2007_Y
end
- attribute \src "ls180.v:6327.46-6327.104"
- cell $and $and$ls180.v:6327$2009
+ attribute \src "ls180.v:6323.46-6323.104"
+ cell $and $and$ls180.v:6323$2009
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank11_sel
- connect \B $not$ls180.v:6327$2008_Y
- connect \Y $and$ls180.v:6327$2009_Y
+ connect \B $not$ls180.v:6323$2008_Y
+ connect \Y $and$ls180.v:6323$2009_Y
end
- attribute \src "ls180.v:6327.45-6327.155"
- cell $and $and$ls180.v:6327$2011
+ attribute \src "ls180.v:6323.45-6323.155"
+ cell $and $and$ls180.v:6323$2011
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6327$2009_Y
- connect \B $eq$ls180.v:6327$2010_Y
- connect \Y $and$ls180.v:6327$2011_Y
+ connect \A $and$ls180.v:6323$2009_Y
+ connect \B $eq$ls180.v:6323$2010_Y
+ connect \Y $and$ls180.v:6323$2011_Y
end
- attribute \src "ls180.v:6329.46-6329.101"
- cell $and $and$ls180.v:6329$2012
+ attribute \src "ls180.v:6325.46-6325.101"
+ cell $and $and$ls180.v:6325$2012
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank11_sel
connect \B \builder_interface11_bank_bus_we
- connect \Y $and$ls180.v:6329$2012_Y
+ connect \Y $and$ls180.v:6325$2012_Y
end
- attribute \src "ls180.v:6329.45-6329.152"
- cell $and $and$ls180.v:6329$2014
+ attribute \src "ls180.v:6325.45-6325.152"
+ cell $and $and$ls180.v:6325$2014
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6329$2012_Y
- connect \B $eq$ls180.v:6329$2013_Y
- connect \Y $and$ls180.v:6329$2014_Y
+ connect \A $and$ls180.v:6325$2012_Y
+ connect \B $eq$ls180.v:6325$2013_Y
+ connect \Y $and$ls180.v:6325$2014_Y
end
- attribute \src "ls180.v:6330.46-6330.104"
- cell $and $and$ls180.v:6330$2016
+ attribute \src "ls180.v:6326.46-6326.104"
+ cell $and $and$ls180.v:6326$2016
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank11_sel
- connect \B $not$ls180.v:6330$2015_Y
- connect \Y $and$ls180.v:6330$2016_Y
+ connect \B $not$ls180.v:6326$2015_Y
+ connect \Y $and$ls180.v:6326$2016_Y
end
- attribute \src "ls180.v:6330.45-6330.155"
- cell $and $and$ls180.v:6330$2018
+ attribute \src "ls180.v:6326.45-6326.155"
+ cell $and $and$ls180.v:6326$2018
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6330$2016_Y
- connect \B $eq$ls180.v:6330$2017_Y
- connect \Y $and$ls180.v:6330$2018_Y
+ connect \A $and$ls180.v:6326$2016_Y
+ connect \B $eq$ls180.v:6326$2017_Y
+ connect \Y $and$ls180.v:6326$2018_Y
end
- attribute \src "ls180.v:6353.39-6353.94"
- cell $and $and$ls180.v:6353$2021
+ attribute \src "ls180.v:6349.39-6349.94"
+ cell $and $and$ls180.v:6349$2021
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank12_sel
connect \B \builder_interface12_bank_bus_we
- connect \Y $and$ls180.v:6353$2021_Y
+ connect \Y $and$ls180.v:6349$2021_Y
end
- attribute \src "ls180.v:6353.38-6353.145"
- cell $and $and$ls180.v:6353$2023
+ attribute \src "ls180.v:6349.38-6349.145"
+ cell $and $and$ls180.v:6349$2023
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6353$2021_Y
- connect \B $eq$ls180.v:6353$2022_Y
- connect \Y $and$ls180.v:6353$2023_Y
+ connect \A $and$ls180.v:6349$2021_Y
+ connect \B $eq$ls180.v:6349$2022_Y
+ connect \Y $and$ls180.v:6349$2023_Y
end
- attribute \src "ls180.v:6354.39-6354.97"
- cell $and $and$ls180.v:6354$2025
+ attribute \src "ls180.v:6350.39-6350.97"
+ cell $and $and$ls180.v:6350$2025
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank12_sel
- connect \B $not$ls180.v:6354$2024_Y
- connect \Y $and$ls180.v:6354$2025_Y
+ connect \B $not$ls180.v:6350$2024_Y
+ connect \Y $and$ls180.v:6350$2025_Y
end
- attribute \src "ls180.v:6354.38-6354.148"
- cell $and $and$ls180.v:6354$2027
+ attribute \src "ls180.v:6350.38-6350.148"
+ cell $and $and$ls180.v:6350$2027
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6354$2025_Y
- connect \B $eq$ls180.v:6354$2026_Y
- connect \Y $and$ls180.v:6354$2027_Y
+ connect \A $and$ls180.v:6350$2025_Y
+ connect \B $eq$ls180.v:6350$2026_Y
+ connect \Y $and$ls180.v:6350$2027_Y
end
- attribute \src "ls180.v:6356.39-6356.94"
- cell $and $and$ls180.v:6356$2028
+ attribute \src "ls180.v:6352.39-6352.94"
+ cell $and $and$ls180.v:6352$2028
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank12_sel
connect \B \builder_interface12_bank_bus_we
- connect \Y $and$ls180.v:6356$2028_Y
+ connect \Y $and$ls180.v:6352$2028_Y
end
- attribute \src "ls180.v:6356.38-6356.145"
- cell $and $and$ls180.v:6356$2030
+ attribute \src "ls180.v:6352.38-6352.145"
+ cell $and $and$ls180.v:6352$2030
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6356$2028_Y
- connect \B $eq$ls180.v:6356$2029_Y
- connect \Y $and$ls180.v:6356$2030_Y
+ connect \A $and$ls180.v:6352$2028_Y
+ connect \B $eq$ls180.v:6352$2029_Y
+ connect \Y $and$ls180.v:6352$2030_Y
end
- attribute \src "ls180.v:6357.39-6357.97"
- cell $and $and$ls180.v:6357$2032
+ attribute \src "ls180.v:6353.39-6353.97"
+ cell $and $and$ls180.v:6353$2032
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank12_sel
- connect \B $not$ls180.v:6357$2031_Y
- connect \Y $and$ls180.v:6357$2032_Y
+ connect \B $not$ls180.v:6353$2031_Y
+ connect \Y $and$ls180.v:6353$2032_Y
end
- attribute \src "ls180.v:6357.38-6357.148"
- cell $and $and$ls180.v:6357$2034
+ attribute \src "ls180.v:6353.38-6353.148"
+ cell $and $and$ls180.v:6353$2034
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6357$2032_Y
- connect \B $eq$ls180.v:6357$2033_Y
- connect \Y $and$ls180.v:6357$2034_Y
+ connect \A $and$ls180.v:6353$2032_Y
+ connect \B $eq$ls180.v:6353$2033_Y
+ connect \Y $and$ls180.v:6353$2034_Y
end
- attribute \src "ls180.v:6359.39-6359.94"
- cell $and $and$ls180.v:6359$2035
+ attribute \src "ls180.v:6355.39-6355.94"
+ cell $and $and$ls180.v:6355$2035
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank12_sel
connect \B \builder_interface12_bank_bus_we
- connect \Y $and$ls180.v:6359$2035_Y
+ connect \Y $and$ls180.v:6355$2035_Y
end
- attribute \src "ls180.v:6359.38-6359.145"
- cell $and $and$ls180.v:6359$2037
+ attribute \src "ls180.v:6355.38-6355.145"
+ cell $and $and$ls180.v:6355$2037
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6359$2035_Y
- connect \B $eq$ls180.v:6359$2036_Y
- connect \Y $and$ls180.v:6359$2037_Y
+ connect \A $and$ls180.v:6355$2035_Y
+ connect \B $eq$ls180.v:6355$2036_Y
+ connect \Y $and$ls180.v:6355$2037_Y
end
- attribute \src "ls180.v:6360.39-6360.97"
- cell $and $and$ls180.v:6360$2039
+ attribute \src "ls180.v:6356.39-6356.97"
+ cell $and $and$ls180.v:6356$2039
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank12_sel
- connect \B $not$ls180.v:6360$2038_Y
- connect \Y $and$ls180.v:6360$2039_Y
+ connect \B $not$ls180.v:6356$2038_Y
+ connect \Y $and$ls180.v:6356$2039_Y
end
- attribute \src "ls180.v:6360.38-6360.148"
- cell $and $and$ls180.v:6360$2041
+ attribute \src "ls180.v:6356.38-6356.148"
+ cell $and $and$ls180.v:6356$2041
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6360$2039_Y
- connect \B $eq$ls180.v:6360$2040_Y
- connect \Y $and$ls180.v:6360$2041_Y
+ connect \A $and$ls180.v:6356$2039_Y
+ connect \B $eq$ls180.v:6356$2040_Y
+ connect \Y $and$ls180.v:6356$2041_Y
end
- attribute \src "ls180.v:6362.39-6362.94"
- cell $and $and$ls180.v:6362$2042
+ attribute \src "ls180.v:6358.39-6358.94"
+ cell $and $and$ls180.v:6358$2042
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank12_sel
connect \B \builder_interface12_bank_bus_we
- connect \Y $and$ls180.v:6362$2042_Y
+ connect \Y $and$ls180.v:6358$2042_Y
end
- attribute \src "ls180.v:6362.38-6362.145"
- cell $and $and$ls180.v:6362$2044
+ attribute \src "ls180.v:6358.38-6358.145"
+ cell $and $and$ls180.v:6358$2044
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6362$2042_Y
- connect \B $eq$ls180.v:6362$2043_Y
- connect \Y $and$ls180.v:6362$2044_Y
+ connect \A $and$ls180.v:6358$2042_Y
+ connect \B $eq$ls180.v:6358$2043_Y
+ connect \Y $and$ls180.v:6358$2044_Y
end
- attribute \src "ls180.v:6363.39-6363.97"
- cell $and $and$ls180.v:6363$2046
+ attribute \src "ls180.v:6359.39-6359.97"
+ cell $and $and$ls180.v:6359$2046
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank12_sel
- connect \B $not$ls180.v:6363$2045_Y
- connect \Y $and$ls180.v:6363$2046_Y
+ connect \B $not$ls180.v:6359$2045_Y
+ connect \Y $and$ls180.v:6359$2046_Y
end
- attribute \src "ls180.v:6363.38-6363.148"
- cell $and $and$ls180.v:6363$2048
+ attribute \src "ls180.v:6359.38-6359.148"
+ cell $and $and$ls180.v:6359$2048
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6363$2046_Y
- connect \B $eq$ls180.v:6363$2047_Y
- connect \Y $and$ls180.v:6363$2048_Y
+ connect \A $and$ls180.v:6359$2046_Y
+ connect \B $eq$ls180.v:6359$2047_Y
+ connect \Y $and$ls180.v:6359$2048_Y
end
- attribute \src "ls180.v:6365.41-6365.96"
- cell $and $and$ls180.v:6365$2049
+ attribute \src "ls180.v:6361.41-6361.96"
+ cell $and $and$ls180.v:6361$2049
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank12_sel
connect \B \builder_interface12_bank_bus_we
- connect \Y $and$ls180.v:6365$2049_Y
+ connect \Y $and$ls180.v:6361$2049_Y
end
- attribute \src "ls180.v:6365.40-6365.147"
- cell $and $and$ls180.v:6365$2051
+ attribute \src "ls180.v:6361.40-6361.147"
+ cell $and $and$ls180.v:6361$2051
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6365$2049_Y
- connect \B $eq$ls180.v:6365$2050_Y
- connect \Y $and$ls180.v:6365$2051_Y
+ connect \A $and$ls180.v:6361$2049_Y
+ connect \B $eq$ls180.v:6361$2050_Y
+ connect \Y $and$ls180.v:6361$2051_Y
end
- attribute \src "ls180.v:6366.41-6366.99"
- cell $and $and$ls180.v:6366$2053
+ attribute \src "ls180.v:6362.41-6362.99"
+ cell $and $and$ls180.v:6362$2053
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank12_sel
- connect \B $not$ls180.v:6366$2052_Y
- connect \Y $and$ls180.v:6366$2053_Y
+ connect \B $not$ls180.v:6362$2052_Y
+ connect \Y $and$ls180.v:6362$2053_Y
end
- attribute \src "ls180.v:6366.40-6366.150"
- cell $and $and$ls180.v:6366$2055
+ attribute \src "ls180.v:6362.40-6362.150"
+ cell $and $and$ls180.v:6362$2055
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6366$2053_Y
- connect \B $eq$ls180.v:6366$2054_Y
- connect \Y $and$ls180.v:6366$2055_Y
+ connect \A $and$ls180.v:6362$2053_Y
+ connect \B $eq$ls180.v:6362$2054_Y
+ connect \Y $and$ls180.v:6362$2055_Y
end
- attribute \src "ls180.v:6368.41-6368.96"
- cell $and $and$ls180.v:6368$2056
+ attribute \src "ls180.v:6364.41-6364.96"
+ cell $and $and$ls180.v:6364$2056
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank12_sel
connect \B \builder_interface12_bank_bus_we
- connect \Y $and$ls180.v:6368$2056_Y
+ connect \Y $and$ls180.v:6364$2056_Y
end
- attribute \src "ls180.v:6368.40-6368.147"
- cell $and $and$ls180.v:6368$2058
+ attribute \src "ls180.v:6364.40-6364.147"
+ cell $and $and$ls180.v:6364$2058
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6368$2056_Y
- connect \B $eq$ls180.v:6368$2057_Y
- connect \Y $and$ls180.v:6368$2058_Y
+ connect \A $and$ls180.v:6364$2056_Y
+ connect \B $eq$ls180.v:6364$2057_Y
+ connect \Y $and$ls180.v:6364$2058_Y
end
- attribute \src "ls180.v:6369.41-6369.99"
- cell $and $and$ls180.v:6369$2060
+ attribute \src "ls180.v:6365.41-6365.99"
+ cell $and $and$ls180.v:6365$2060
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank12_sel
- connect \B $not$ls180.v:6369$2059_Y
- connect \Y $and$ls180.v:6369$2060_Y
+ connect \B $not$ls180.v:6365$2059_Y
+ connect \Y $and$ls180.v:6365$2060_Y
end
- attribute \src "ls180.v:6369.40-6369.150"
- cell $and $and$ls180.v:6369$2062
+ attribute \src "ls180.v:6365.40-6365.150"
+ cell $and $and$ls180.v:6365$2062
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6369$2060_Y
- connect \B $eq$ls180.v:6369$2061_Y
- connect \Y $and$ls180.v:6369$2062_Y
+ connect \A $and$ls180.v:6365$2060_Y
+ connect \B $eq$ls180.v:6365$2061_Y
+ connect \Y $and$ls180.v:6365$2062_Y
end
- attribute \src "ls180.v:6371.41-6371.96"
- cell $and $and$ls180.v:6371$2063
+ attribute \src "ls180.v:6367.41-6367.96"
+ cell $and $and$ls180.v:6367$2063
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank12_sel
connect \B \builder_interface12_bank_bus_we
- connect \Y $and$ls180.v:6371$2063_Y
+ connect \Y $and$ls180.v:6367$2063_Y
end
- attribute \src "ls180.v:6371.40-6371.147"
- cell $and $and$ls180.v:6371$2065
+ attribute \src "ls180.v:6367.40-6367.147"
+ cell $and $and$ls180.v:6367$2065
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6371$2063_Y
- connect \B $eq$ls180.v:6371$2064_Y
- connect \Y $and$ls180.v:6371$2065_Y
+ connect \A $and$ls180.v:6367$2063_Y
+ connect \B $eq$ls180.v:6367$2064_Y
+ connect \Y $and$ls180.v:6367$2065_Y
end
- attribute \src "ls180.v:6372.41-6372.99"
- cell $and $and$ls180.v:6372$2067
+ attribute \src "ls180.v:6368.41-6368.99"
+ cell $and $and$ls180.v:6368$2067
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank12_sel
- connect \B $not$ls180.v:6372$2066_Y
- connect \Y $and$ls180.v:6372$2067_Y
+ connect \B $not$ls180.v:6368$2066_Y
+ connect \Y $and$ls180.v:6368$2067_Y
end
- attribute \src "ls180.v:6372.40-6372.150"
- cell $and $and$ls180.v:6372$2069
+ attribute \src "ls180.v:6368.40-6368.150"
+ cell $and $and$ls180.v:6368$2069
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6372$2067_Y
- connect \B $eq$ls180.v:6372$2068_Y
- connect \Y $and$ls180.v:6372$2069_Y
+ connect \A $and$ls180.v:6368$2067_Y
+ connect \B $eq$ls180.v:6368$2068_Y
+ connect \Y $and$ls180.v:6368$2069_Y
end
- attribute \src "ls180.v:6374.41-6374.96"
- cell $and $and$ls180.v:6374$2070
+ attribute \src "ls180.v:6370.41-6370.96"
+ cell $and $and$ls180.v:6370$2070
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank12_sel
connect \B \builder_interface12_bank_bus_we
- connect \Y $and$ls180.v:6374$2070_Y
+ connect \Y $and$ls180.v:6370$2070_Y
end
- attribute \src "ls180.v:6374.40-6374.147"
- cell $and $and$ls180.v:6374$2072
+ attribute \src "ls180.v:6370.40-6370.147"
+ cell $and $and$ls180.v:6370$2072
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6374$2070_Y
- connect \B $eq$ls180.v:6374$2071_Y
- connect \Y $and$ls180.v:6374$2072_Y
+ connect \A $and$ls180.v:6370$2070_Y
+ connect \B $eq$ls180.v:6370$2071_Y
+ connect \Y $and$ls180.v:6370$2072_Y
end
- attribute \src "ls180.v:6375.41-6375.99"
- cell $and $and$ls180.v:6375$2074
+ attribute \src "ls180.v:6371.41-6371.99"
+ cell $and $and$ls180.v:6371$2074
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank12_sel
- connect \B $not$ls180.v:6375$2073_Y
- connect \Y $and$ls180.v:6375$2074_Y
+ connect \B $not$ls180.v:6371$2073_Y
+ connect \Y $and$ls180.v:6371$2074_Y
end
- attribute \src "ls180.v:6375.40-6375.150"
- cell $and $and$ls180.v:6375$2076
+ attribute \src "ls180.v:6371.40-6371.150"
+ cell $and $and$ls180.v:6371$2076
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6375$2074_Y
- connect \B $eq$ls180.v:6375$2075_Y
- connect \Y $and$ls180.v:6375$2076_Y
+ connect \A $and$ls180.v:6371$2074_Y
+ connect \B $eq$ls180.v:6371$2075_Y
+ connect \Y $and$ls180.v:6371$2076_Y
end
- attribute \src "ls180.v:6377.37-6377.92"
- cell $and $and$ls180.v:6377$2077
+ attribute \src "ls180.v:6373.37-6373.92"
+ cell $and $and$ls180.v:6373$2077
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank12_sel
connect \B \builder_interface12_bank_bus_we
- connect \Y $and$ls180.v:6377$2077_Y
+ connect \Y $and$ls180.v:6373$2077_Y
end
- attribute \src "ls180.v:6377.36-6377.143"
- cell $and $and$ls180.v:6377$2079
+ attribute \src "ls180.v:6373.36-6373.143"
+ cell $and $and$ls180.v:6373$2079
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6377$2077_Y
- connect \B $eq$ls180.v:6377$2078_Y
- connect \Y $and$ls180.v:6377$2079_Y
+ connect \A $and$ls180.v:6373$2077_Y
+ connect \B $eq$ls180.v:6373$2078_Y
+ connect \Y $and$ls180.v:6373$2079_Y
end
- attribute \src "ls180.v:6378.37-6378.95"
- cell $and $and$ls180.v:6378$2081
+ attribute \src "ls180.v:6374.37-6374.95"
+ cell $and $and$ls180.v:6374$2081
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank12_sel
- connect \B $not$ls180.v:6378$2080_Y
- connect \Y $and$ls180.v:6378$2081_Y
+ connect \B $not$ls180.v:6374$2080_Y
+ connect \Y $and$ls180.v:6374$2081_Y
end
- attribute \src "ls180.v:6378.36-6378.146"
- cell $and $and$ls180.v:6378$2083
+ attribute \src "ls180.v:6374.36-6374.146"
+ cell $and $and$ls180.v:6374$2083
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6378$2081_Y
- connect \B $eq$ls180.v:6378$2082_Y
- connect \Y $and$ls180.v:6378$2083_Y
+ connect \A $and$ls180.v:6374$2081_Y
+ connect \B $eq$ls180.v:6374$2082_Y
+ connect \Y $and$ls180.v:6374$2083_Y
end
- attribute \src "ls180.v:6380.47-6380.102"
- cell $and $and$ls180.v:6380$2084
+ attribute \src "ls180.v:6376.47-6376.102"
+ cell $and $and$ls180.v:6376$2084
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank12_sel
connect \B \builder_interface12_bank_bus_we
- connect \Y $and$ls180.v:6380$2084_Y
+ connect \Y $and$ls180.v:6376$2084_Y
end
- attribute \src "ls180.v:6380.46-6380.153"
- cell $and $and$ls180.v:6380$2086
+ attribute \src "ls180.v:6376.46-6376.153"
+ cell $and $and$ls180.v:6376$2086
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6380$2084_Y
- connect \B $eq$ls180.v:6380$2085_Y
- connect \Y $and$ls180.v:6380$2086_Y
+ connect \A $and$ls180.v:6376$2084_Y
+ connect \B $eq$ls180.v:6376$2085_Y
+ connect \Y $and$ls180.v:6376$2086_Y
end
- attribute \src "ls180.v:6381.47-6381.105"
- cell $and $and$ls180.v:6381$2088
+ attribute \src "ls180.v:6377.47-6377.105"
+ cell $and $and$ls180.v:6377$2088
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank12_sel
- connect \B $not$ls180.v:6381$2087_Y
- connect \Y $and$ls180.v:6381$2088_Y
+ connect \B $not$ls180.v:6377$2087_Y
+ connect \Y $and$ls180.v:6377$2088_Y
end
- attribute \src "ls180.v:6381.46-6381.156"
- cell $and $and$ls180.v:6381$2090
+ attribute \src "ls180.v:6377.46-6377.156"
+ cell $and $and$ls180.v:6377$2090
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6381$2088_Y
- connect \B $eq$ls180.v:6381$2089_Y
- connect \Y $and$ls180.v:6381$2090_Y
+ connect \A $and$ls180.v:6377$2088_Y
+ connect \B $eq$ls180.v:6377$2089_Y
+ connect \Y $and$ls180.v:6377$2090_Y
end
- attribute \src "ls180.v:6383.40-6383.95"
- cell $and $and$ls180.v:6383$2091
+ attribute \src "ls180.v:6379.40-6379.95"
+ cell $and $and$ls180.v:6379$2091
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank12_sel
connect \B \builder_interface12_bank_bus_we
- connect \Y $and$ls180.v:6383$2091_Y
+ connect \Y $and$ls180.v:6379$2091_Y
end
- attribute \src "ls180.v:6383.39-6383.147"
- cell $and $and$ls180.v:6383$2093
+ attribute \src "ls180.v:6379.39-6379.147"
+ cell $and $and$ls180.v:6379$2093
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6383$2091_Y
- connect \B $eq$ls180.v:6383$2092_Y
- connect \Y $and$ls180.v:6383$2093_Y
+ connect \A $and$ls180.v:6379$2091_Y
+ connect \B $eq$ls180.v:6379$2092_Y
+ connect \Y $and$ls180.v:6379$2093_Y
end
- attribute \src "ls180.v:6384.40-6384.98"
- cell $and $and$ls180.v:6384$2095
+ attribute \src "ls180.v:6380.40-6380.98"
+ cell $and $and$ls180.v:6380$2095
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank12_sel
- connect \B $not$ls180.v:6384$2094_Y
- connect \Y $and$ls180.v:6384$2095_Y
+ connect \B $not$ls180.v:6380$2094_Y
+ connect \Y $and$ls180.v:6380$2095_Y
end
- attribute \src "ls180.v:6384.39-6384.150"
- cell $and $and$ls180.v:6384$2097
+ attribute \src "ls180.v:6380.39-6380.150"
+ cell $and $and$ls180.v:6380$2097
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6384$2095_Y
- connect \B $eq$ls180.v:6384$2096_Y
- connect \Y $and$ls180.v:6384$2097_Y
+ connect \A $and$ls180.v:6380$2095_Y
+ connect \B $eq$ls180.v:6380$2096_Y
+ connect \Y $and$ls180.v:6380$2097_Y
end
- attribute \src "ls180.v:6386.40-6386.95"
- cell $and $and$ls180.v:6386$2098
+ attribute \src "ls180.v:6382.40-6382.95"
+ cell $and $and$ls180.v:6382$2098
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank12_sel
connect \B \builder_interface12_bank_bus_we
- connect \Y $and$ls180.v:6386$2098_Y
+ connect \Y $and$ls180.v:6382$2098_Y
end
- attribute \src "ls180.v:6386.39-6386.147"
- cell $and $and$ls180.v:6386$2100
+ attribute \src "ls180.v:6382.39-6382.147"
+ cell $and $and$ls180.v:6382$2100
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6386$2098_Y
- connect \B $eq$ls180.v:6386$2099_Y
- connect \Y $and$ls180.v:6386$2100_Y
+ connect \A $and$ls180.v:6382$2098_Y
+ connect \B $eq$ls180.v:6382$2099_Y
+ connect \Y $and$ls180.v:6382$2100_Y
end
- attribute \src "ls180.v:6387.40-6387.98"
- cell $and $and$ls180.v:6387$2102
+ attribute \src "ls180.v:6383.40-6383.98"
+ cell $and $and$ls180.v:6383$2102
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank12_sel
- connect \B $not$ls180.v:6387$2101_Y
- connect \Y $and$ls180.v:6387$2102_Y
+ connect \B $not$ls180.v:6383$2101_Y
+ connect \Y $and$ls180.v:6383$2102_Y
end
- attribute \src "ls180.v:6387.39-6387.150"
- cell $and $and$ls180.v:6387$2104
+ attribute \src "ls180.v:6383.39-6383.150"
+ cell $and $and$ls180.v:6383$2104
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6387$2102_Y
- connect \B $eq$ls180.v:6387$2103_Y
- connect \Y $and$ls180.v:6387$2104_Y
+ connect \A $and$ls180.v:6383$2102_Y
+ connect \B $eq$ls180.v:6383$2103_Y
+ connect \Y $and$ls180.v:6383$2104_Y
end
- attribute \src "ls180.v:6389.40-6389.95"
- cell $and $and$ls180.v:6389$2105
+ attribute \src "ls180.v:6385.40-6385.95"
+ cell $and $and$ls180.v:6385$2105
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank12_sel
connect \B \builder_interface12_bank_bus_we
- connect \Y $and$ls180.v:6389$2105_Y
+ connect \Y $and$ls180.v:6385$2105_Y
end
- attribute \src "ls180.v:6389.39-6389.147"
- cell $and $and$ls180.v:6389$2107
+ attribute \src "ls180.v:6385.39-6385.147"
+ cell $and $and$ls180.v:6385$2107
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6389$2105_Y
- connect \B $eq$ls180.v:6389$2106_Y
- connect \Y $and$ls180.v:6389$2107_Y
+ connect \A $and$ls180.v:6385$2105_Y
+ connect \B $eq$ls180.v:6385$2106_Y
+ connect \Y $and$ls180.v:6385$2107_Y
end
- attribute \src "ls180.v:6390.40-6390.98"
- cell $and $and$ls180.v:6390$2109
+ attribute \src "ls180.v:6386.40-6386.98"
+ cell $and $and$ls180.v:6386$2109
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank12_sel
- connect \B $not$ls180.v:6390$2108_Y
- connect \Y $and$ls180.v:6390$2109_Y
+ connect \B $not$ls180.v:6386$2108_Y
+ connect \Y $and$ls180.v:6386$2109_Y
end
- attribute \src "ls180.v:6390.39-6390.150"
- cell $and $and$ls180.v:6390$2111
+ attribute \src "ls180.v:6386.39-6386.150"
+ cell $and $and$ls180.v:6386$2111
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6390$2109_Y
- connect \B $eq$ls180.v:6390$2110_Y
- connect \Y $and$ls180.v:6390$2111_Y
+ connect \A $and$ls180.v:6386$2109_Y
+ connect \B $eq$ls180.v:6386$2110_Y
+ connect \Y $and$ls180.v:6386$2111_Y
end
- attribute \src "ls180.v:6392.40-6392.95"
- cell $and $and$ls180.v:6392$2112
+ attribute \src "ls180.v:6388.40-6388.95"
+ cell $and $and$ls180.v:6388$2112
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank12_sel
connect \B \builder_interface12_bank_bus_we
- connect \Y $and$ls180.v:6392$2112_Y
+ connect \Y $and$ls180.v:6388$2112_Y
end
- attribute \src "ls180.v:6392.39-6392.147"
- cell $and $and$ls180.v:6392$2114
+ attribute \src "ls180.v:6388.39-6388.147"
+ cell $and $and$ls180.v:6388$2114
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6392$2112_Y
- connect \B $eq$ls180.v:6392$2113_Y
- connect \Y $and$ls180.v:6392$2114_Y
+ connect \A $and$ls180.v:6388$2112_Y
+ connect \B $eq$ls180.v:6388$2113_Y
+ connect \Y $and$ls180.v:6388$2114_Y
end
- attribute \src "ls180.v:6393.40-6393.98"
- cell $and $and$ls180.v:6393$2116
+ attribute \src "ls180.v:6389.40-6389.98"
+ cell $and $and$ls180.v:6389$2116
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank12_sel
- connect \B $not$ls180.v:6393$2115_Y
- connect \Y $and$ls180.v:6393$2116_Y
+ connect \B $not$ls180.v:6389$2115_Y
+ connect \Y $and$ls180.v:6389$2116_Y
end
- attribute \src "ls180.v:6393.39-6393.150"
- cell $and $and$ls180.v:6393$2118
+ attribute \src "ls180.v:6389.39-6389.150"
+ cell $and $and$ls180.v:6389$2118
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6393$2116_Y
- connect \B $eq$ls180.v:6393$2117_Y
- connect \Y $and$ls180.v:6393$2118_Y
+ connect \A $and$ls180.v:6389$2116_Y
+ connect \B $eq$ls180.v:6389$2117_Y
+ connect \Y $and$ls180.v:6389$2118_Y
end
- attribute \src "ls180.v:6395.52-6395.107"
- cell $and $and$ls180.v:6395$2119
+ attribute \src "ls180.v:6391.52-6391.107"
+ cell $and $and$ls180.v:6391$2119
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank12_sel
connect \B \builder_interface12_bank_bus_we
- connect \Y $and$ls180.v:6395$2119_Y
+ connect \Y $and$ls180.v:6391$2119_Y
end
- attribute \src "ls180.v:6395.51-6395.159"
- cell $and $and$ls180.v:6395$2121
+ attribute \src "ls180.v:6391.51-6391.159"
+ cell $and $and$ls180.v:6391$2121
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6395$2119_Y
- connect \B $eq$ls180.v:6395$2120_Y
- connect \Y $and$ls180.v:6395$2121_Y
+ connect \A $and$ls180.v:6391$2119_Y
+ connect \B $eq$ls180.v:6391$2120_Y
+ connect \Y $and$ls180.v:6391$2121_Y
end
- attribute \src "ls180.v:6396.52-6396.110"
- cell $and $and$ls180.v:6396$2123
+ attribute \src "ls180.v:6392.52-6392.110"
+ cell $and $and$ls180.v:6392$2123
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank12_sel
- connect \B $not$ls180.v:6396$2122_Y
- connect \Y $and$ls180.v:6396$2123_Y
+ connect \B $not$ls180.v:6392$2122_Y
+ connect \Y $and$ls180.v:6392$2123_Y
end
- attribute \src "ls180.v:6396.51-6396.162"
- cell $and $and$ls180.v:6396$2125
+ attribute \src "ls180.v:6392.51-6392.162"
+ cell $and $and$ls180.v:6392$2125
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6396$2123_Y
- connect \B $eq$ls180.v:6396$2124_Y
- connect \Y $and$ls180.v:6396$2125_Y
+ connect \A $and$ls180.v:6392$2123_Y
+ connect \B $eq$ls180.v:6392$2124_Y
+ connect \Y $and$ls180.v:6392$2125_Y
end
- attribute \src "ls180.v:6398.53-6398.108"
- cell $and $and$ls180.v:6398$2126
+ attribute \src "ls180.v:6394.53-6394.108"
+ cell $and $and$ls180.v:6394$2126
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank12_sel
connect \B \builder_interface12_bank_bus_we
- connect \Y $and$ls180.v:6398$2126_Y
+ connect \Y $and$ls180.v:6394$2126_Y
end
- attribute \src "ls180.v:6398.52-6398.160"
- cell $and $and$ls180.v:6398$2128
+ attribute \src "ls180.v:6394.52-6394.160"
+ cell $and $and$ls180.v:6394$2128
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6398$2126_Y
- connect \B $eq$ls180.v:6398$2127_Y
- connect \Y $and$ls180.v:6398$2128_Y
+ connect \A $and$ls180.v:6394$2126_Y
+ connect \B $eq$ls180.v:6394$2127_Y
+ connect \Y $and$ls180.v:6394$2128_Y
end
- attribute \src "ls180.v:6399.53-6399.111"
- cell $and $and$ls180.v:6399$2130
+ attribute \src "ls180.v:6395.53-6395.111"
+ cell $and $and$ls180.v:6395$2130
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank12_sel
- connect \B $not$ls180.v:6399$2129_Y
- connect \Y $and$ls180.v:6399$2130_Y
+ connect \B $not$ls180.v:6395$2129_Y
+ connect \Y $and$ls180.v:6395$2130_Y
end
- attribute \src "ls180.v:6399.52-6399.163"
- cell $and $and$ls180.v:6399$2132
+ attribute \src "ls180.v:6395.52-6395.163"
+ cell $and $and$ls180.v:6395$2132
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6399$2130_Y
- connect \B $eq$ls180.v:6399$2131_Y
- connect \Y $and$ls180.v:6399$2132_Y
+ connect \A $and$ls180.v:6395$2130_Y
+ connect \B $eq$ls180.v:6395$2131_Y
+ connect \Y $and$ls180.v:6395$2132_Y
end
- attribute \src "ls180.v:6401.44-6401.99"
- cell $and $and$ls180.v:6401$2133
+ attribute \src "ls180.v:6397.44-6397.99"
+ cell $and $and$ls180.v:6397$2133
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank12_sel
connect \B \builder_interface12_bank_bus_we
- connect \Y $and$ls180.v:6401$2133_Y
+ connect \Y $and$ls180.v:6397$2133_Y
end
- attribute \src "ls180.v:6401.43-6401.151"
- cell $and $and$ls180.v:6401$2135
+ attribute \src "ls180.v:6397.43-6397.151"
+ cell $and $and$ls180.v:6397$2135
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6401$2133_Y
- connect \B $eq$ls180.v:6401$2134_Y
- connect \Y $and$ls180.v:6401$2135_Y
+ connect \A $and$ls180.v:6397$2133_Y
+ connect \B $eq$ls180.v:6397$2134_Y
+ connect \Y $and$ls180.v:6397$2135_Y
end
- attribute \src "ls180.v:6402.44-6402.102"
- cell $and $and$ls180.v:6402$2137
+ attribute \src "ls180.v:6398.44-6398.102"
+ cell $and $and$ls180.v:6398$2137
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank12_sel
- connect \B $not$ls180.v:6402$2136_Y
- connect \Y $and$ls180.v:6402$2137_Y
+ connect \B $not$ls180.v:6398$2136_Y
+ connect \Y $and$ls180.v:6398$2137_Y
end
- attribute \src "ls180.v:6402.43-6402.154"
- cell $and $and$ls180.v:6402$2139
+ attribute \src "ls180.v:6398.43-6398.154"
+ cell $and $and$ls180.v:6398$2139
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6402$2137_Y
- connect \B $eq$ls180.v:6402$2138_Y
- connect \Y $and$ls180.v:6402$2139_Y
+ connect \A $and$ls180.v:6398$2137_Y
+ connect \B $eq$ls180.v:6398$2138_Y
+ connect \Y $and$ls180.v:6398$2139_Y
end
- attribute \src "ls180.v:6421.30-6421.85"
- cell $and $and$ls180.v:6421$2141
+ attribute \src "ls180.v:6417.30-6417.85"
+ cell $and $and$ls180.v:6417$2141
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank13_sel
connect \B \builder_interface13_bank_bus_we
- connect \Y $and$ls180.v:6421$2141_Y
+ connect \Y $and$ls180.v:6417$2141_Y
end
- attribute \src "ls180.v:6421.29-6421.136"
- cell $and $and$ls180.v:6421$2143
+ attribute \src "ls180.v:6417.29-6417.136"
+ cell $and $and$ls180.v:6417$2143
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6421$2141_Y
- connect \B $eq$ls180.v:6421$2142_Y
- connect \Y $and$ls180.v:6421$2143_Y
+ connect \A $and$ls180.v:6417$2141_Y
+ connect \B $eq$ls180.v:6417$2142_Y
+ connect \Y $and$ls180.v:6417$2143_Y
end
- attribute \src "ls180.v:6422.30-6422.88"
- cell $and $and$ls180.v:6422$2145
+ attribute \src "ls180.v:6418.30-6418.88"
+ cell $and $and$ls180.v:6418$2145
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank13_sel
- connect \B $not$ls180.v:6422$2144_Y
- connect \Y $and$ls180.v:6422$2145_Y
+ connect \B $not$ls180.v:6418$2144_Y
+ connect \Y $and$ls180.v:6418$2145_Y
end
- attribute \src "ls180.v:6422.29-6422.139"
- cell $and $and$ls180.v:6422$2147
+ attribute \src "ls180.v:6418.29-6418.139"
+ cell $and $and$ls180.v:6418$2147
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6422$2145_Y
- connect \B $eq$ls180.v:6422$2146_Y
- connect \Y $and$ls180.v:6422$2147_Y
+ connect \A $and$ls180.v:6418$2145_Y
+ connect \B $eq$ls180.v:6418$2146_Y
+ connect \Y $and$ls180.v:6418$2147_Y
end
- attribute \src "ls180.v:6424.40-6424.95"
- cell $and $and$ls180.v:6424$2148
+ attribute \src "ls180.v:6420.40-6420.95"
+ cell $and $and$ls180.v:6420$2148
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank13_sel
connect \B \builder_interface13_bank_bus_we
- connect \Y $and$ls180.v:6424$2148_Y
+ connect \Y $and$ls180.v:6420$2148_Y
end
- attribute \src "ls180.v:6424.39-6424.146"
- cell $and $and$ls180.v:6424$2150
+ attribute \src "ls180.v:6420.39-6420.146"
+ cell $and $and$ls180.v:6420$2150
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6424$2148_Y
- connect \B $eq$ls180.v:6424$2149_Y
- connect \Y $and$ls180.v:6424$2150_Y
+ connect \A $and$ls180.v:6420$2148_Y
+ connect \B $eq$ls180.v:6420$2149_Y
+ connect \Y $and$ls180.v:6420$2150_Y
end
- attribute \src "ls180.v:6425.40-6425.98"
- cell $and $and$ls180.v:6425$2152
+ attribute \src "ls180.v:6421.40-6421.98"
+ cell $and $and$ls180.v:6421$2152
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank13_sel
- connect \B $not$ls180.v:6425$2151_Y
- connect \Y $and$ls180.v:6425$2152_Y
+ connect \B $not$ls180.v:6421$2151_Y
+ connect \Y $and$ls180.v:6421$2152_Y
end
- attribute \src "ls180.v:6425.39-6425.149"
- cell $and $and$ls180.v:6425$2154
+ attribute \src "ls180.v:6421.39-6421.149"
+ cell $and $and$ls180.v:6421$2154
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6425$2152_Y
- connect \B $eq$ls180.v:6425$2153_Y
- connect \Y $and$ls180.v:6425$2154_Y
+ connect \A $and$ls180.v:6421$2152_Y
+ connect \B $eq$ls180.v:6421$2153_Y
+ connect \Y $and$ls180.v:6421$2154_Y
end
- attribute \src "ls180.v:6427.41-6427.96"
- cell $and $and$ls180.v:6427$2155
+ attribute \src "ls180.v:6423.41-6423.96"
+ cell $and $and$ls180.v:6423$2155
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank13_sel
connect \B \builder_interface13_bank_bus_we
- connect \Y $and$ls180.v:6427$2155_Y
+ connect \Y $and$ls180.v:6423$2155_Y
end
- attribute \src "ls180.v:6427.40-6427.147"
- cell $and $and$ls180.v:6427$2157
+ attribute \src "ls180.v:6423.40-6423.147"
+ cell $and $and$ls180.v:6423$2157
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6427$2155_Y
- connect \B $eq$ls180.v:6427$2156_Y
- connect \Y $and$ls180.v:6427$2157_Y
+ connect \A $and$ls180.v:6423$2155_Y
+ connect \B $eq$ls180.v:6423$2156_Y
+ connect \Y $and$ls180.v:6423$2157_Y
end
- attribute \src "ls180.v:6428.41-6428.99"
- cell $and $and$ls180.v:6428$2159
+ attribute \src "ls180.v:6424.41-6424.99"
+ cell $and $and$ls180.v:6424$2159
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank13_sel
- connect \B $not$ls180.v:6428$2158_Y
- connect \Y $and$ls180.v:6428$2159_Y
+ connect \B $not$ls180.v:6424$2158_Y
+ connect \Y $and$ls180.v:6424$2159_Y
end
- attribute \src "ls180.v:6428.40-6428.150"
- cell $and $and$ls180.v:6428$2161
+ attribute \src "ls180.v:6424.40-6424.150"
+ cell $and $and$ls180.v:6424$2161
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6428$2159_Y
- connect \B $eq$ls180.v:6428$2160_Y
- connect \Y $and$ls180.v:6428$2161_Y
+ connect \A $and$ls180.v:6424$2159_Y
+ connect \B $eq$ls180.v:6424$2160_Y
+ connect \Y $and$ls180.v:6424$2161_Y
end
- attribute \src "ls180.v:6430.45-6430.100"
- cell $and $and$ls180.v:6430$2162
+ attribute \src "ls180.v:6426.45-6426.100"
+ cell $and $and$ls180.v:6426$2162
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank13_sel
connect \B \builder_interface13_bank_bus_we
- connect \Y $and$ls180.v:6430$2162_Y
+ connect \Y $and$ls180.v:6426$2162_Y
end
- attribute \src "ls180.v:6430.44-6430.151"
- cell $and $and$ls180.v:6430$2164
+ attribute \src "ls180.v:6426.44-6426.151"
+ cell $and $and$ls180.v:6426$2164
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6430$2162_Y
- connect \B $eq$ls180.v:6430$2163_Y
- connect \Y $and$ls180.v:6430$2164_Y
+ connect \A $and$ls180.v:6426$2162_Y
+ connect \B $eq$ls180.v:6426$2163_Y
+ connect \Y $and$ls180.v:6426$2164_Y
end
- attribute \src "ls180.v:6431.45-6431.103"
- cell $and $and$ls180.v:6431$2166
+ attribute \src "ls180.v:6427.45-6427.103"
+ cell $and $and$ls180.v:6427$2166
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank13_sel
- connect \B $not$ls180.v:6431$2165_Y
- connect \Y $and$ls180.v:6431$2166_Y
+ connect \B $not$ls180.v:6427$2165_Y
+ connect \Y $and$ls180.v:6427$2166_Y
end
- attribute \src "ls180.v:6431.44-6431.154"
- cell $and $and$ls180.v:6431$2168
+ attribute \src "ls180.v:6427.44-6427.154"
+ cell $and $and$ls180.v:6427$2168
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6431$2166_Y
- connect \B $eq$ls180.v:6431$2167_Y
- connect \Y $and$ls180.v:6431$2168_Y
+ connect \A $and$ls180.v:6427$2166_Y
+ connect \B $eq$ls180.v:6427$2167_Y
+ connect \Y $and$ls180.v:6427$2168_Y
end
- attribute \src "ls180.v:6433.46-6433.101"
- cell $and $and$ls180.v:6433$2169
+ attribute \src "ls180.v:6429.46-6429.101"
+ cell $and $and$ls180.v:6429$2169
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank13_sel
connect \B \builder_interface13_bank_bus_we
- connect \Y $and$ls180.v:6433$2169_Y
+ connect \Y $and$ls180.v:6429$2169_Y
end
- attribute \src "ls180.v:6433.45-6433.152"
- cell $and $and$ls180.v:6433$2171
+ attribute \src "ls180.v:6429.45-6429.152"
+ cell $and $and$ls180.v:6429$2171
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6433$2169_Y
- connect \B $eq$ls180.v:6433$2170_Y
- connect \Y $and$ls180.v:6433$2171_Y
+ connect \A $and$ls180.v:6429$2169_Y
+ connect \B $eq$ls180.v:6429$2170_Y
+ connect \Y $and$ls180.v:6429$2171_Y
end
- attribute \src "ls180.v:6434.46-6434.104"
- cell $and $and$ls180.v:6434$2173
+ attribute \src "ls180.v:6430.46-6430.104"
+ cell $and $and$ls180.v:6430$2173
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank13_sel
- connect \B $not$ls180.v:6434$2172_Y
- connect \Y $and$ls180.v:6434$2173_Y
+ connect \B $not$ls180.v:6430$2172_Y
+ connect \Y $and$ls180.v:6430$2173_Y
end
- attribute \src "ls180.v:6434.45-6434.155"
- cell $and $and$ls180.v:6434$2175
+ attribute \src "ls180.v:6430.45-6430.155"
+ cell $and $and$ls180.v:6430$2175
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6434$2173_Y
- connect \B $eq$ls180.v:6434$2174_Y
- connect \Y $and$ls180.v:6434$2175_Y
+ connect \A $and$ls180.v:6430$2173_Y
+ connect \B $eq$ls180.v:6430$2174_Y
+ connect \Y $and$ls180.v:6430$2175_Y
end
- attribute \src "ls180.v:6436.44-6436.99"
- cell $and $and$ls180.v:6436$2176
+ attribute \src "ls180.v:6432.44-6432.99"
+ cell $and $and$ls180.v:6432$2176
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank13_sel
connect \B \builder_interface13_bank_bus_we
- connect \Y $and$ls180.v:6436$2176_Y
+ connect \Y $and$ls180.v:6432$2176_Y
end
- attribute \src "ls180.v:6436.43-6436.150"
- cell $and $and$ls180.v:6436$2178
+ attribute \src "ls180.v:6432.43-6432.150"
+ cell $and $and$ls180.v:6432$2178
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6436$2176_Y
- connect \B $eq$ls180.v:6436$2177_Y
- connect \Y $and$ls180.v:6436$2178_Y
+ connect \A $and$ls180.v:6432$2176_Y
+ connect \B $eq$ls180.v:6432$2177_Y
+ connect \Y $and$ls180.v:6432$2178_Y
end
- attribute \src "ls180.v:6437.44-6437.102"
- cell $and $and$ls180.v:6437$2180
+ attribute \src "ls180.v:6433.44-6433.102"
+ cell $and $and$ls180.v:6433$2180
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank13_sel
- connect \B $not$ls180.v:6437$2179_Y
- connect \Y $and$ls180.v:6437$2180_Y
+ connect \B $not$ls180.v:6433$2179_Y
+ connect \Y $and$ls180.v:6433$2180_Y
end
- attribute \src "ls180.v:6437.43-6437.153"
- cell $and $and$ls180.v:6437$2182
+ attribute \src "ls180.v:6433.43-6433.153"
+ cell $and $and$ls180.v:6433$2182
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6437$2180_Y
- connect \B $eq$ls180.v:6437$2181_Y
- connect \Y $and$ls180.v:6437$2182_Y
+ connect \A $and$ls180.v:6433$2180_Y
+ connect \B $eq$ls180.v:6433$2181_Y
+ connect \Y $and$ls180.v:6433$2182_Y
end
- attribute \src "ls180.v:6439.41-6439.96"
- cell $and $and$ls180.v:6439$2183
+ attribute \src "ls180.v:6435.41-6435.96"
+ cell $and $and$ls180.v:6435$2183
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank13_sel
connect \B \builder_interface13_bank_bus_we
- connect \Y $and$ls180.v:6439$2183_Y
+ connect \Y $and$ls180.v:6435$2183_Y
end
- attribute \src "ls180.v:6439.40-6439.147"
- cell $and $and$ls180.v:6439$2185
+ attribute \src "ls180.v:6435.40-6435.147"
+ cell $and $and$ls180.v:6435$2185
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6439$2183_Y
- connect \B $eq$ls180.v:6439$2184_Y
- connect \Y $and$ls180.v:6439$2185_Y
+ connect \A $and$ls180.v:6435$2183_Y
+ connect \B $eq$ls180.v:6435$2184_Y
+ connect \Y $and$ls180.v:6435$2185_Y
end
- attribute \src "ls180.v:6440.41-6440.99"
- cell $and $and$ls180.v:6440$2187
+ attribute \src "ls180.v:6436.41-6436.99"
+ cell $and $and$ls180.v:6436$2187
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank13_sel
- connect \B $not$ls180.v:6440$2186_Y
- connect \Y $and$ls180.v:6440$2187_Y
+ connect \B $not$ls180.v:6436$2186_Y
+ connect \Y $and$ls180.v:6436$2187_Y
end
- attribute \src "ls180.v:6440.40-6440.150"
- cell $and $and$ls180.v:6440$2189
+ attribute \src "ls180.v:6436.40-6436.150"
+ cell $and $and$ls180.v:6436$2189
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6440$2187_Y
- connect \B $eq$ls180.v:6440$2188_Y
- connect \Y $and$ls180.v:6440$2189_Y
+ connect \A $and$ls180.v:6436$2187_Y
+ connect \B $eq$ls180.v:6436$2188_Y
+ connect \Y $and$ls180.v:6436$2189_Y
end
- attribute \src "ls180.v:6442.40-6442.95"
- cell $and $and$ls180.v:6442$2190
+ attribute \src "ls180.v:6438.40-6438.95"
+ cell $and $and$ls180.v:6438$2190
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank13_sel
connect \B \builder_interface13_bank_bus_we
- connect \Y $and$ls180.v:6442$2190_Y
+ connect \Y $and$ls180.v:6438$2190_Y
end
- attribute \src "ls180.v:6442.39-6442.146"
- cell $and $and$ls180.v:6442$2192
+ attribute \src "ls180.v:6438.39-6438.146"
+ cell $and $and$ls180.v:6438$2192
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6442$2190_Y
- connect \B $eq$ls180.v:6442$2191_Y
- connect \Y $and$ls180.v:6442$2192_Y
+ connect \A $and$ls180.v:6438$2190_Y
+ connect \B $eq$ls180.v:6438$2191_Y
+ connect \Y $and$ls180.v:6438$2192_Y
end
- attribute \src "ls180.v:6443.40-6443.98"
- cell $and $and$ls180.v:6443$2194
+ attribute \src "ls180.v:6439.40-6439.98"
+ cell $and $and$ls180.v:6439$2194
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank13_sel
- connect \B $not$ls180.v:6443$2193_Y
- connect \Y $and$ls180.v:6443$2194_Y
+ connect \B $not$ls180.v:6439$2193_Y
+ connect \Y $and$ls180.v:6439$2194_Y
end
- attribute \src "ls180.v:6443.39-6443.149"
- cell $and $and$ls180.v:6443$2196
+ attribute \src "ls180.v:6439.39-6439.149"
+ cell $and $and$ls180.v:6439$2196
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6443$2194_Y
- connect \B $eq$ls180.v:6443$2195_Y
- connect \Y $and$ls180.v:6443$2196_Y
+ connect \A $and$ls180.v:6439$2194_Y
+ connect \B $eq$ls180.v:6439$2195_Y
+ connect \Y $and$ls180.v:6439$2196_Y
end
- attribute \src "ls180.v:6455.46-6455.101"
- cell $and $and$ls180.v:6455$2198
+ attribute \src "ls180.v:6451.46-6451.101"
+ cell $and $and$ls180.v:6451$2198
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank14_sel
connect \B \builder_interface14_bank_bus_we
- connect \Y $and$ls180.v:6455$2198_Y
+ connect \Y $and$ls180.v:6451$2198_Y
end
- attribute \src "ls180.v:6455.45-6455.152"
- cell $and $and$ls180.v:6455$2200
+ attribute \src "ls180.v:6451.45-6451.152"
+ cell $and $and$ls180.v:6451$2200
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6455$2198_Y
- connect \B $eq$ls180.v:6455$2199_Y
- connect \Y $and$ls180.v:6455$2200_Y
+ connect \A $and$ls180.v:6451$2198_Y
+ connect \B $eq$ls180.v:6451$2199_Y
+ connect \Y $and$ls180.v:6451$2200_Y
end
- attribute \src "ls180.v:6456.46-6456.104"
- cell $and $and$ls180.v:6456$2202
+ attribute \src "ls180.v:6452.46-6452.104"
+ cell $and $and$ls180.v:6452$2202
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank14_sel
- connect \B $not$ls180.v:6456$2201_Y
- connect \Y $and$ls180.v:6456$2202_Y
+ connect \B $not$ls180.v:6452$2201_Y
+ connect \Y $and$ls180.v:6452$2202_Y
end
- attribute \src "ls180.v:6456.45-6456.155"
- cell $and $and$ls180.v:6456$2204
+ attribute \src "ls180.v:6452.45-6452.155"
+ cell $and $and$ls180.v:6452$2204
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6456$2202_Y
- connect \B $eq$ls180.v:6456$2203_Y
- connect \Y $and$ls180.v:6456$2204_Y
+ connect \A $and$ls180.v:6452$2202_Y
+ connect \B $eq$ls180.v:6452$2203_Y
+ connect \Y $and$ls180.v:6452$2204_Y
end
- attribute \src "ls180.v:6458.46-6458.101"
- cell $and $and$ls180.v:6458$2205
+ attribute \src "ls180.v:6454.46-6454.101"
+ cell $and $and$ls180.v:6454$2205
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank14_sel
connect \B \builder_interface14_bank_bus_we
- connect \Y $and$ls180.v:6458$2205_Y
+ connect \Y $and$ls180.v:6454$2205_Y
end
- attribute \src "ls180.v:6458.45-6458.152"
- cell $and $and$ls180.v:6458$2207
+ attribute \src "ls180.v:6454.45-6454.152"
+ cell $and $and$ls180.v:6454$2207
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6458$2205_Y
- connect \B $eq$ls180.v:6458$2206_Y
- connect \Y $and$ls180.v:6458$2207_Y
+ connect \A $and$ls180.v:6454$2205_Y
+ connect \B $eq$ls180.v:6454$2206_Y
+ connect \Y $and$ls180.v:6454$2207_Y
end
- attribute \src "ls180.v:6459.46-6459.104"
- cell $and $and$ls180.v:6459$2209
+ attribute \src "ls180.v:6455.46-6455.104"
+ cell $and $and$ls180.v:6455$2209
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank14_sel
- connect \B $not$ls180.v:6459$2208_Y
- connect \Y $and$ls180.v:6459$2209_Y
+ connect \B $not$ls180.v:6455$2208_Y
+ connect \Y $and$ls180.v:6455$2209_Y
end
- attribute \src "ls180.v:6459.45-6459.155"
- cell $and $and$ls180.v:6459$2211
+ attribute \src "ls180.v:6455.45-6455.155"
+ cell $and $and$ls180.v:6455$2211
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6459$2209_Y
- connect \B $eq$ls180.v:6459$2210_Y
- connect \Y $and$ls180.v:6459$2211_Y
+ connect \A $and$ls180.v:6455$2209_Y
+ connect \B $eq$ls180.v:6455$2210_Y
+ connect \Y $and$ls180.v:6455$2211_Y
end
- attribute \src "ls180.v:6461.46-6461.101"
- cell $and $and$ls180.v:6461$2212
+ attribute \src "ls180.v:6457.46-6457.101"
+ cell $and $and$ls180.v:6457$2212
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank14_sel
connect \B \builder_interface14_bank_bus_we
- connect \Y $and$ls180.v:6461$2212_Y
+ connect \Y $and$ls180.v:6457$2212_Y
end
- attribute \src "ls180.v:6461.45-6461.152"
- cell $and $and$ls180.v:6461$2214
+ attribute \src "ls180.v:6457.45-6457.152"
+ cell $and $and$ls180.v:6457$2214
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6461$2212_Y
- connect \B $eq$ls180.v:6461$2213_Y
- connect \Y $and$ls180.v:6461$2214_Y
+ connect \A $and$ls180.v:6457$2212_Y
+ connect \B $eq$ls180.v:6457$2213_Y
+ connect \Y $and$ls180.v:6457$2214_Y
end
- attribute \src "ls180.v:6462.46-6462.104"
- cell $and $and$ls180.v:6462$2216
+ attribute \src "ls180.v:6458.46-6458.104"
+ cell $and $and$ls180.v:6458$2216
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank14_sel
- connect \B $not$ls180.v:6462$2215_Y
- connect \Y $and$ls180.v:6462$2216_Y
+ connect \B $not$ls180.v:6458$2215_Y
+ connect \Y $and$ls180.v:6458$2216_Y
end
- attribute \src "ls180.v:6462.45-6462.155"
- cell $and $and$ls180.v:6462$2218
+ attribute \src "ls180.v:6458.45-6458.155"
+ cell $and $and$ls180.v:6458$2218
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6462$2216_Y
- connect \B $eq$ls180.v:6462$2217_Y
- connect \Y $and$ls180.v:6462$2218_Y
+ connect \A $and$ls180.v:6458$2216_Y
+ connect \B $eq$ls180.v:6458$2217_Y
+ connect \Y $and$ls180.v:6458$2218_Y
end
- attribute \src "ls180.v:6464.46-6464.101"
- cell $and $and$ls180.v:6464$2219
+ attribute \src "ls180.v:6460.46-6460.101"
+ cell $and $and$ls180.v:6460$2219
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank14_sel
connect \B \builder_interface14_bank_bus_we
- connect \Y $and$ls180.v:6464$2219_Y
+ connect \Y $and$ls180.v:6460$2219_Y
end
- attribute \src "ls180.v:6464.45-6464.152"
- cell $and $and$ls180.v:6464$2221
+ attribute \src "ls180.v:6460.45-6460.152"
+ cell $and $and$ls180.v:6460$2221
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6464$2219_Y
- connect \B $eq$ls180.v:6464$2220_Y
- connect \Y $and$ls180.v:6464$2221_Y
+ connect \A $and$ls180.v:6460$2219_Y
+ connect \B $eq$ls180.v:6460$2220_Y
+ connect \Y $and$ls180.v:6460$2221_Y
end
- attribute \src "ls180.v:6465.46-6465.104"
- cell $and $and$ls180.v:6465$2223
+ attribute \src "ls180.v:6461.46-6461.104"
+ cell $and $and$ls180.v:6461$2223
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank14_sel
- connect \B $not$ls180.v:6465$2222_Y
- connect \Y $and$ls180.v:6465$2223_Y
+ connect \B $not$ls180.v:6461$2222_Y
+ connect \Y $and$ls180.v:6461$2223_Y
end
- attribute \src "ls180.v:6465.45-6465.155"
- cell $and $and$ls180.v:6465$2225
+ attribute \src "ls180.v:6461.45-6461.155"
+ cell $and $and$ls180.v:6461$2225
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6465$2223_Y
- connect \B $eq$ls180.v:6465$2224_Y
- connect \Y $and$ls180.v:6465$2225_Y
+ connect \A $and$ls180.v:6461$2223_Y
+ connect \B $eq$ls180.v:6461$2224_Y
+ connect \Y $and$ls180.v:6461$2225_Y
end
- attribute \src "ls180.v:6846.109-6846.178"
- cell $and $and$ls180.v:6846$2263
+ attribute \src "ls180.v:6842.109-6842.178"
+ cell $and $and$ls180.v:6842$2263
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_interface_bank1_lock
- connect \B $eq$ls180.v:6846$2262_Y
- connect \Y $and$ls180.v:6846$2263_Y
+ connect \B $eq$ls180.v:6842$2262_Y
+ connect \Y $and$ls180.v:6842$2263_Y
end
- attribute \src "ls180.v:6846.184-6846.253"
- cell $and $and$ls180.v:6846$2266
+ attribute \src "ls180.v:6842.184-6842.253"
+ cell $and $and$ls180.v:6842$2266
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_interface_bank2_lock
- connect \B $eq$ls180.v:6846$2265_Y
- connect \Y $and$ls180.v:6846$2266_Y
+ connect \B $eq$ls180.v:6842$2265_Y
+ connect \Y $and$ls180.v:6842$2266_Y
end
- attribute \src "ls180.v:6846.259-6846.328"
- cell $and $and$ls180.v:6846$2269
+ attribute \src "ls180.v:6842.259-6842.328"
+ cell $and $and$ls180.v:6842$2269
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_interface_bank3_lock
- connect \B $eq$ls180.v:6846$2268_Y
- connect \Y $and$ls180.v:6846$2269_Y
+ connect \B $eq$ls180.v:6842$2268_Y
+ connect \Y $and$ls180.v:6842$2269_Y
end
- attribute \src "ls180.v:6846.40-6846.331"
- cell $and $and$ls180.v:6846$2272
+ attribute \src "ls180.v:6842.40-6842.331"
+ cell $and $and$ls180.v:6842$2272
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $eq$ls180.v:6846$2261_Y
- connect \B $not$ls180.v:6846$2271_Y
- connect \Y $and$ls180.v:6846$2272_Y
+ connect \A $eq$ls180.v:6842$2261_Y
+ connect \B $not$ls180.v:6842$2271_Y
+ connect \Y $and$ls180.v:6842$2272_Y
end
- attribute \src "ls180.v:6846.39-6846.354"
- cell $and $and$ls180.v:6846$2273
+ attribute \src "ls180.v:6842.39-6842.354"
+ cell $and $and$ls180.v:6842$2273
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6846$2272_Y
+ connect \A $and$ls180.v:6842$2272_Y
connect \B \main_port_cmd_valid
- connect \Y $and$ls180.v:6846$2273_Y
+ connect \Y $and$ls180.v:6842$2273_Y
end
- attribute \src "ls180.v:6870.109-6870.178"
- cell $and $and$ls180.v:6870$2279
+ attribute \src "ls180.v:6866.109-6866.178"
+ cell $and $and$ls180.v:6866$2279
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_interface_bank0_lock
- connect \B $eq$ls180.v:6870$2278_Y
- connect \Y $and$ls180.v:6870$2279_Y
+ connect \B $eq$ls180.v:6866$2278_Y
+ connect \Y $and$ls180.v:6866$2279_Y
end
- attribute \src "ls180.v:6870.184-6870.253"
- cell $and $and$ls180.v:6870$2282
+ attribute \src "ls180.v:6866.184-6866.253"
+ cell $and $and$ls180.v:6866$2282
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_interface_bank2_lock
- connect \B $eq$ls180.v:6870$2281_Y
- connect \Y $and$ls180.v:6870$2282_Y
+ connect \B $eq$ls180.v:6866$2281_Y
+ connect \Y $and$ls180.v:6866$2282_Y
end
- attribute \src "ls180.v:6870.259-6870.328"
- cell $and $and$ls180.v:6870$2285
+ attribute \src "ls180.v:6866.259-6866.328"
+ cell $and $and$ls180.v:6866$2285
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_interface_bank3_lock
- connect \B $eq$ls180.v:6870$2284_Y
- connect \Y $and$ls180.v:6870$2285_Y
+ connect \B $eq$ls180.v:6866$2284_Y
+ connect \Y $and$ls180.v:6866$2285_Y
end
- attribute \src "ls180.v:6870.40-6870.331"
- cell $and $and$ls180.v:6870$2288
+ attribute \src "ls180.v:6866.40-6866.331"
+ cell $and $and$ls180.v:6866$2288
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $eq$ls180.v:6870$2277_Y
- connect \B $not$ls180.v:6870$2287_Y
- connect \Y $and$ls180.v:6870$2288_Y
+ connect \A $eq$ls180.v:6866$2277_Y
+ connect \B $not$ls180.v:6866$2287_Y
+ connect \Y $and$ls180.v:6866$2288_Y
end
- attribute \src "ls180.v:6870.39-6870.354"
- cell $and $and$ls180.v:6870$2289
+ attribute \src "ls180.v:6866.39-6866.354"
+ cell $and $and$ls180.v:6866$2289
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6870$2288_Y
+ connect \A $and$ls180.v:6866$2288_Y
connect \B \main_port_cmd_valid
- connect \Y $and$ls180.v:6870$2289_Y
+ connect \Y $and$ls180.v:6866$2289_Y
end
- attribute \src "ls180.v:6894.109-6894.178"
- cell $and $and$ls180.v:6894$2295
+ attribute \src "ls180.v:6890.109-6890.178"
+ cell $and $and$ls180.v:6890$2295
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_interface_bank0_lock
- connect \B $eq$ls180.v:6894$2294_Y
- connect \Y $and$ls180.v:6894$2295_Y
+ connect \B $eq$ls180.v:6890$2294_Y
+ connect \Y $and$ls180.v:6890$2295_Y
end
- attribute \src "ls180.v:6894.184-6894.253"
- cell $and $and$ls180.v:6894$2298
+ attribute \src "ls180.v:6890.184-6890.253"
+ cell $and $and$ls180.v:6890$2298
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_interface_bank1_lock
- connect \B $eq$ls180.v:6894$2297_Y
- connect \Y $and$ls180.v:6894$2298_Y
+ connect \B $eq$ls180.v:6890$2297_Y
+ connect \Y $and$ls180.v:6890$2298_Y
end
- attribute \src "ls180.v:6894.259-6894.328"
- cell $and $and$ls180.v:6894$2301
+ attribute \src "ls180.v:6890.259-6890.328"
+ cell $and $and$ls180.v:6890$2301
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_interface_bank3_lock
- connect \B $eq$ls180.v:6894$2300_Y
- connect \Y $and$ls180.v:6894$2301_Y
+ connect \B $eq$ls180.v:6890$2300_Y
+ connect \Y $and$ls180.v:6890$2301_Y
end
- attribute \src "ls180.v:6894.40-6894.331"
- cell $and $and$ls180.v:6894$2304
+ attribute \src "ls180.v:6890.40-6890.331"
+ cell $and $and$ls180.v:6890$2304
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $eq$ls180.v:6894$2293_Y
- connect \B $not$ls180.v:6894$2303_Y
- connect \Y $and$ls180.v:6894$2304_Y
+ connect \A $eq$ls180.v:6890$2293_Y
+ connect \B $not$ls180.v:6890$2303_Y
+ connect \Y $and$ls180.v:6890$2304_Y
end
- attribute \src "ls180.v:6894.39-6894.354"
- cell $and $and$ls180.v:6894$2305
+ attribute \src "ls180.v:6890.39-6890.354"
+ cell $and $and$ls180.v:6890$2305
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6894$2304_Y
+ connect \A $and$ls180.v:6890$2304_Y
connect \B \main_port_cmd_valid
- connect \Y $and$ls180.v:6894$2305_Y
+ connect \Y $and$ls180.v:6890$2305_Y
end
- attribute \src "ls180.v:6918.109-6918.178"
- cell $and $and$ls180.v:6918$2311
+ attribute \src "ls180.v:6914.109-6914.178"
+ cell $and $and$ls180.v:6914$2311
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_interface_bank0_lock
- connect \B $eq$ls180.v:6918$2310_Y
- connect \Y $and$ls180.v:6918$2311_Y
+ connect \B $eq$ls180.v:6914$2310_Y
+ connect \Y $and$ls180.v:6914$2311_Y
end
- attribute \src "ls180.v:6918.184-6918.253"
- cell $and $and$ls180.v:6918$2314
+ attribute \src "ls180.v:6914.184-6914.253"
+ cell $and $and$ls180.v:6914$2314
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_interface_bank1_lock
- connect \B $eq$ls180.v:6918$2313_Y
- connect \Y $and$ls180.v:6918$2314_Y
+ connect \B $eq$ls180.v:6914$2313_Y
+ connect \Y $and$ls180.v:6914$2314_Y
end
- attribute \src "ls180.v:6918.259-6918.328"
- cell $and $and$ls180.v:6918$2317
+ attribute \src "ls180.v:6914.259-6914.328"
+ cell $and $and$ls180.v:6914$2317
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_interface_bank2_lock
- connect \B $eq$ls180.v:6918$2316_Y
- connect \Y $and$ls180.v:6918$2317_Y
+ connect \B $eq$ls180.v:6914$2316_Y
+ connect \Y $and$ls180.v:6914$2317_Y
end
- attribute \src "ls180.v:6918.40-6918.331"
- cell $and $and$ls180.v:6918$2320
+ attribute \src "ls180.v:6914.40-6914.331"
+ cell $and $and$ls180.v:6914$2320
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $eq$ls180.v:6918$2309_Y
- connect \B $not$ls180.v:6918$2319_Y
- connect \Y $and$ls180.v:6918$2320_Y
+ connect \A $eq$ls180.v:6914$2309_Y
+ connect \B $not$ls180.v:6914$2319_Y
+ connect \Y $and$ls180.v:6914$2320_Y
end
- attribute \src "ls180.v:6918.39-6918.354"
- cell $and $and$ls180.v:6918$2321
+ attribute \src "ls180.v:6914.39-6914.354"
+ cell $and $and$ls180.v:6914$2321
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6918$2320_Y
+ connect \A $and$ls180.v:6914$2320_Y
connect \B \main_port_cmd_valid
- connect \Y $and$ls180.v:6918$2321_Y
+ connect \Y $and$ls180.v:6914$2321_Y
end
- attribute \src "ls180.v:7123.39-7123.104"
- cell $and $and$ls180.v:7123$2333
+ attribute \src "ls180.v:7119.39-7119.104"
+ cell $and $and$ls180.v:7119$2333
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_choose_req_cmd_valid
connect \B \main_sdram_choose_req_cmd_ready
- connect \Y $and$ls180.v:7123$2333_Y
+ connect \Y $and$ls180.v:7119$2333_Y
end
- attribute \src "ls180.v:7123.38-7123.145"
- cell $and $and$ls180.v:7123$2334
+ attribute \src "ls180.v:7119.38-7119.145"
+ cell $and $and$ls180.v:7119$2334
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:7123$2333_Y
+ connect \A $and$ls180.v:7119$2333_Y
connect \B \main_sdram_choose_req_cmd_payload_cas
- connect \Y $and$ls180.v:7123$2334_Y
+ connect \Y $and$ls180.v:7119$2334_Y
end
- attribute \src "ls180.v:7126.39-7126.104"
- cell $and $and$ls180.v:7126$2335
+ attribute \src "ls180.v:7122.39-7122.104"
+ cell $and $and$ls180.v:7122$2335
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_choose_req_cmd_valid
connect \B \main_sdram_choose_req_cmd_ready
- connect \Y $and$ls180.v:7126$2335_Y
+ connect \Y $and$ls180.v:7122$2335_Y
end
- attribute \src "ls180.v:7126.38-7126.145"
- cell $and $and$ls180.v:7126$2336
+ attribute \src "ls180.v:7122.38-7122.145"
+ cell $and $and$ls180.v:7122$2336
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:7126$2335_Y
+ connect \A $and$ls180.v:7122$2335_Y
connect \B \main_sdram_choose_req_cmd_payload_cas
- connect \Y $and$ls180.v:7126$2336_Y
+ connect \Y $and$ls180.v:7122$2336_Y
end
- attribute \src "ls180.v:7129.39-7129.82"
- cell $and $and$ls180.v:7129$2337
+ attribute \src "ls180.v:7125.39-7125.82"
+ cell $and $and$ls180.v:7125$2337
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_cmd_valid
connect \B \main_sdram_cmd_ready
- connect \Y $and$ls180.v:7129$2337_Y
+ connect \Y $and$ls180.v:7125$2337_Y
end
- attribute \src "ls180.v:7129.38-7129.112"
- cell $and $and$ls180.v:7129$2338
+ attribute \src "ls180.v:7125.38-7125.112"
+ cell $and $and$ls180.v:7125$2338
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:7129$2337_Y
+ connect \A $and$ls180.v:7125$2337_Y
connect \B \main_sdram_cmd_payload_cas
- connect \Y $and$ls180.v:7129$2338_Y
+ connect \Y $and$ls180.v:7125$2338_Y
end
- attribute \src "ls180.v:7140.39-7140.104"
- cell $and $and$ls180.v:7140$2340
+ attribute \src "ls180.v:7136.39-7136.104"
+ cell $and $and$ls180.v:7136$2340
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_choose_req_cmd_valid
connect \B \main_sdram_choose_req_cmd_ready
- connect \Y $and$ls180.v:7140$2340_Y
+ connect \Y $and$ls180.v:7136$2340_Y
end
- attribute \src "ls180.v:7140.38-7140.145"
- cell $and $and$ls180.v:7140$2341
+ attribute \src "ls180.v:7136.38-7136.145"
+ cell $and $and$ls180.v:7136$2341
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:7140$2340_Y
+ connect \A $and$ls180.v:7136$2340_Y
connect \B \main_sdram_choose_req_cmd_payload_ras
- connect \Y $and$ls180.v:7140$2341_Y
+ connect \Y $and$ls180.v:7136$2341_Y
end
- attribute \src "ls180.v:7143.39-7143.104"
- cell $and $and$ls180.v:7143$2342
+ attribute \src "ls180.v:7139.39-7139.104"
+ cell $and $and$ls180.v:7139$2342
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_choose_req_cmd_valid
connect \B \main_sdram_choose_req_cmd_ready
- connect \Y $and$ls180.v:7143$2342_Y
+ connect \Y $and$ls180.v:7139$2342_Y
end
- attribute \src "ls180.v:7143.38-7143.145"
- cell $and $and$ls180.v:7143$2343
+ attribute \src "ls180.v:7139.38-7139.145"
+ cell $and $and$ls180.v:7139$2343
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:7143$2342_Y
+ connect \A $and$ls180.v:7139$2342_Y
connect \B \main_sdram_choose_req_cmd_payload_ras
- connect \Y $and$ls180.v:7143$2343_Y
+ connect \Y $and$ls180.v:7139$2343_Y
end
- attribute \src "ls180.v:7146.39-7146.82"
- cell $and $and$ls180.v:7146$2344
+ attribute \src "ls180.v:7142.39-7142.82"
+ cell $and $and$ls180.v:7142$2344
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_cmd_valid
connect \B \main_sdram_cmd_ready
- connect \Y $and$ls180.v:7146$2344_Y
+ connect \Y $and$ls180.v:7142$2344_Y
end
- attribute \src "ls180.v:7146.38-7146.112"
- cell $and $and$ls180.v:7146$2345
+ attribute \src "ls180.v:7142.38-7142.112"
+ cell $and $and$ls180.v:7142$2345
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:7146$2344_Y
+ connect \A $and$ls180.v:7142$2344_Y
connect \B \main_sdram_cmd_payload_ras
- connect \Y $and$ls180.v:7146$2345_Y
+ connect \Y $and$ls180.v:7142$2345_Y
end
- attribute \src "ls180.v:7157.39-7157.104"
- cell $and $and$ls180.v:7157$2347
+ attribute \src "ls180.v:7153.39-7153.104"
+ cell $and $and$ls180.v:7153$2347
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_choose_req_cmd_valid
connect \B \main_sdram_choose_req_cmd_ready
- connect \Y $and$ls180.v:7157$2347_Y
+ connect \Y $and$ls180.v:7153$2347_Y
end
- attribute \src "ls180.v:7157.38-7157.144"
- cell $and $and$ls180.v:7157$2348
+ attribute \src "ls180.v:7153.38-7153.144"
+ cell $and $and$ls180.v:7153$2348
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:7157$2347_Y
+ connect \A $and$ls180.v:7153$2347_Y
connect \B \main_sdram_choose_req_cmd_payload_we
- connect \Y $and$ls180.v:7157$2348_Y
+ connect \Y $and$ls180.v:7153$2348_Y
end
- attribute \src "ls180.v:7160.39-7160.104"
- cell $and $and$ls180.v:7160$2349
+ attribute \src "ls180.v:7156.39-7156.104"
+ cell $and $and$ls180.v:7156$2349
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_choose_req_cmd_valid
connect \B \main_sdram_choose_req_cmd_ready
- connect \Y $and$ls180.v:7160$2349_Y
+ connect \Y $and$ls180.v:7156$2349_Y
end
- attribute \src "ls180.v:7160.38-7160.144"
- cell $and $and$ls180.v:7160$2350
+ attribute \src "ls180.v:7156.38-7156.144"
+ cell $and $and$ls180.v:7156$2350
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:7160$2349_Y
+ connect \A $and$ls180.v:7156$2349_Y
connect \B \main_sdram_choose_req_cmd_payload_we
- connect \Y $and$ls180.v:7160$2350_Y
+ connect \Y $and$ls180.v:7156$2350_Y
end
- attribute \src "ls180.v:7163.39-7163.82"
- cell $and $and$ls180.v:7163$2351
+ attribute \src "ls180.v:7159.39-7159.82"
+ cell $and $and$ls180.v:7159$2351
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_cmd_valid
connect \B \main_sdram_cmd_ready
- connect \Y $and$ls180.v:7163$2351_Y
+ connect \Y $and$ls180.v:7159$2351_Y
end
- attribute \src "ls180.v:7163.38-7163.111"
- cell $and $and$ls180.v:7163$2352
+ attribute \src "ls180.v:7159.38-7159.111"
+ cell $and $and$ls180.v:7159$2352
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:7163$2351_Y
+ connect \A $and$ls180.v:7159$2351_Y
connect \B \main_sdram_cmd_payload_we
- connect \Y $and$ls180.v:7163$2352_Y
+ connect \Y $and$ls180.v:7159$2352_Y
end
- attribute \src "ls180.v:7174.39-7174.104"
- cell $and $and$ls180.v:7174$2354
+ attribute \src "ls180.v:7170.39-7170.104"
+ cell $and $and$ls180.v:7170$2354
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_choose_req_cmd_valid
connect \B \main_sdram_choose_req_cmd_ready
- connect \Y $and$ls180.v:7174$2354_Y
+ connect \Y $and$ls180.v:7170$2354_Y
end
- attribute \src "ls180.v:7174.38-7174.149"
- cell $and $and$ls180.v:7174$2355
+ attribute \src "ls180.v:7170.38-7170.149"
+ cell $and $and$ls180.v:7170$2355
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:7174$2354_Y
+ connect \A $and$ls180.v:7170$2354_Y
connect \B \main_sdram_choose_req_cmd_payload_is_read
- connect \Y $and$ls180.v:7174$2355_Y
+ connect \Y $and$ls180.v:7170$2355_Y
end
- attribute \src "ls180.v:7177.39-7177.104"
- cell $and $and$ls180.v:7177$2356
+ attribute \src "ls180.v:7173.39-7173.104"
+ cell $and $and$ls180.v:7173$2356
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_choose_req_cmd_valid
connect \B \main_sdram_choose_req_cmd_ready
- connect \Y $and$ls180.v:7177$2356_Y
+ connect \Y $and$ls180.v:7173$2356_Y
end
- attribute \src "ls180.v:7177.38-7177.149"
- cell $and $and$ls180.v:7177$2357
+ attribute \src "ls180.v:7173.38-7173.149"
+ cell $and $and$ls180.v:7173$2357
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:7177$2356_Y
+ connect \A $and$ls180.v:7173$2356_Y
connect \B \main_sdram_choose_req_cmd_payload_is_read
- connect \Y $and$ls180.v:7177$2357_Y
+ connect \Y $and$ls180.v:7173$2357_Y
end
- attribute \src "ls180.v:7180.39-7180.82"
- cell $and $and$ls180.v:7180$2358
+ attribute \src "ls180.v:7176.39-7176.82"
+ cell $and $and$ls180.v:7176$2358
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_cmd_valid
connect \B \main_sdram_cmd_ready
- connect \Y $and$ls180.v:7180$2358_Y
+ connect \Y $and$ls180.v:7176$2358_Y
end
- attribute \src "ls180.v:7180.38-7180.116"
- cell $and $and$ls180.v:7180$2359
+ attribute \src "ls180.v:7176.38-7176.116"
+ cell $and $and$ls180.v:7176$2359
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:7180$2358_Y
+ connect \A $and$ls180.v:7176$2358_Y
connect \B \main_sdram_cmd_payload_is_read
- connect \Y $and$ls180.v:7180$2359_Y
+ connect \Y $and$ls180.v:7176$2359_Y
end
- attribute \src "ls180.v:7191.39-7191.104"
- cell $and $and$ls180.v:7191$2361
+ attribute \src "ls180.v:7187.39-7187.104"
+ cell $and $and$ls180.v:7187$2361
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_choose_req_cmd_valid
connect \B \main_sdram_choose_req_cmd_ready
- connect \Y $and$ls180.v:7191$2361_Y
+ connect \Y $and$ls180.v:7187$2361_Y
end
- attribute \src "ls180.v:7191.38-7191.150"
- cell $and $and$ls180.v:7191$2362
+ attribute \src "ls180.v:7187.38-7187.150"
+ cell $and $and$ls180.v:7187$2362
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:7191$2361_Y
+ connect \A $and$ls180.v:7187$2361_Y
connect \B \main_sdram_choose_req_cmd_payload_is_write
- connect \Y $and$ls180.v:7191$2362_Y
+ connect \Y $and$ls180.v:7187$2362_Y
end
- attribute \src "ls180.v:7194.39-7194.104"
- cell $and $and$ls180.v:7194$2363
+ attribute \src "ls180.v:7190.39-7190.104"
+ cell $and $and$ls180.v:7190$2363
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_choose_req_cmd_valid
connect \B \main_sdram_choose_req_cmd_ready
- connect \Y $and$ls180.v:7194$2363_Y
+ connect \Y $and$ls180.v:7190$2363_Y
end
- attribute \src "ls180.v:7194.38-7194.150"
- cell $and $and$ls180.v:7194$2364
+ attribute \src "ls180.v:7190.38-7190.150"
+ cell $and $and$ls180.v:7190$2364
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:7194$2363_Y
+ connect \A $and$ls180.v:7190$2363_Y
connect \B \main_sdram_choose_req_cmd_payload_is_write
- connect \Y $and$ls180.v:7194$2364_Y
+ connect \Y $and$ls180.v:7190$2364_Y
end
- attribute \src "ls180.v:7197.39-7197.82"
- cell $and $and$ls180.v:7197$2365
+ attribute \src "ls180.v:7193.39-7193.82"
+ cell $and $and$ls180.v:7193$2365
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_cmd_valid
connect \B \main_sdram_cmd_ready
- connect \Y $and$ls180.v:7197$2365_Y
+ connect \Y $and$ls180.v:7193$2365_Y
end
- attribute \src "ls180.v:7197.38-7197.117"
- cell $and $and$ls180.v:7197$2366
+ attribute \src "ls180.v:7193.38-7193.117"
+ cell $and $and$ls180.v:7193$2366
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:7197$2365_Y
+ connect \A $and$ls180.v:7193$2365_Y
connect \B \main_sdram_cmd_payload_is_write
- connect \Y $and$ls180.v:7197$2366_Y
+ connect \Y $and$ls180.v:7193$2366_Y
end
- attribute \src "ls180.v:7416.17-7416.67"
- cell $and $and$ls180.v:7416$2373
+ attribute \src "ls180.v:7412.17-7412.67"
+ cell $and $and$ls180.v:7412$2373
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $not$ls180.v:7416$2372_Y
+ connect \A $not$ls180.v:7412$2372_Y
connect \B \main_sdphy_sdpads_clk
- connect \Y $and$ls180.v:7416$2373_Y
+ connect \Y $and$ls180.v:7412$2373_Y
end
- attribute \src "ls180.v:7495.8-7495.67"
- cell $and $and$ls180.v:7495$2404
+ attribute \src "ls180.v:7491.8-7491.67"
+ cell $and $and$ls180.v:7491$2404
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_libresocsim_ram_bus_cyc
connect \B \main_libresocsim_ram_bus_stb
- connect \Y $and$ls180.v:7495$2404_Y
+ connect \Y $and$ls180.v:7491$2404_Y
end
- attribute \src "ls180.v:7495.7-7495.102"
- cell $and $and$ls180.v:7495$2406
+ attribute \src "ls180.v:7491.7-7491.102"
+ cell $and $and$ls180.v:7491$2406
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:7495$2404_Y
- connect \B $not$ls180.v:7495$2405_Y
- connect \Y $and$ls180.v:7495$2406_Y
+ connect \A $and$ls180.v:7491$2404_Y
+ connect \B $not$ls180.v:7491$2405_Y
+ connect \Y $and$ls180.v:7491$2406_Y
end
- attribute \src "ls180.v:7514.7-7514.75"
- cell $and $and$ls180.v:7514$2410
+ attribute \src "ls180.v:7510.7-7510.75"
+ cell $and $and$ls180.v:7510$2410
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $not$ls180.v:7514$2409_Y
+ connect \A $not$ls180.v:7510$2409_Y
connect \B \main_libresocsim_zero_old_trigger
- connect \Y $and$ls180.v:7514$2410_Y
+ connect \Y $and$ls180.v:7510$2410_Y
end
- attribute \src "ls180.v:7522.7-7522.56"
- cell $and $and$ls180.v:7522$2412
+ attribute \src "ls180.v:7518.7-7518.56"
+ cell $and $and$ls180.v:7518$2412
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_timer_wait
- connect \B $not$ls180.v:7522$2411_Y
- connect \Y $and$ls180.v:7522$2412_Y
+ connect \B $not$ls180.v:7518$2411_Y
+ connect \Y $and$ls180.v:7518$2412_Y
end
- attribute \src "ls180.v:7550.7-7550.75"
- cell $and $and$ls180.v:7550$2419
+ attribute \src "ls180.v:7546.7-7546.75"
+ cell $and $and$ls180.v:7546$2419
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_sequencer_start1
- connect \B $eq$ls180.v:7550$2418_Y
- connect \Y $and$ls180.v:7550$2419_Y
+ connect \B $eq$ls180.v:7546$2418_Y
+ connect \Y $and$ls180.v:7546$2419_Y
end
- attribute \src "ls180.v:7592.8-7592.131"
- cell $and $and$ls180.v:7592$2425
+ attribute \src "ls180.v:7588.8-7588.131"
+ cell $and $and$ls180.v:7588$2425
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we
connect \B \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable
- connect \Y $and$ls180.v:7592$2425_Y
+ connect \Y $and$ls180.v:7588$2425_Y
end
- attribute \src "ls180.v:7592.7-7592.190"
- cell $and $and$ls180.v:7592$2427
+ attribute \src "ls180.v:7588.7-7588.190"
+ cell $and $and$ls180.v:7588$2427
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:7592$2425_Y
- connect \B $not$ls180.v:7592$2426_Y
- connect \Y $and$ls180.v:7592$2427_Y
+ connect \A $and$ls180.v:7588$2425_Y
+ connect \B $not$ls180.v:7588$2426_Y
+ connect \Y $and$ls180.v:7588$2427_Y
end
- attribute \src "ls180.v:7598.8-7598.131"
- cell $and $and$ls180.v:7598$2430
+ attribute \src "ls180.v:7594.8-7594.131"
+ cell $and $and$ls180.v:7594$2430
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we
connect \B \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable
- connect \Y $and$ls180.v:7598$2430_Y
+ connect \Y $and$ls180.v:7594$2430_Y
end
- attribute \src "ls180.v:7598.7-7598.190"
- cell $and $and$ls180.v:7598$2432
+ attribute \src "ls180.v:7594.7-7594.190"
+ cell $and $and$ls180.v:7594$2432
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:7598$2430_Y
- connect \B $not$ls180.v:7598$2431_Y
- connect \Y $and$ls180.v:7598$2432_Y
+ connect \A $and$ls180.v:7594$2430_Y
+ connect \B $not$ls180.v:7594$2431_Y
+ connect \Y $and$ls180.v:7594$2432_Y
end
- attribute \src "ls180.v:7638.8-7638.131"
- cell $and $and$ls180.v:7638$2441
+ attribute \src "ls180.v:7634.8-7634.131"
+ cell $and $and$ls180.v:7634$2441
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we
connect \B \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable
- connect \Y $and$ls180.v:7638$2441_Y
+ connect \Y $and$ls180.v:7634$2441_Y
end
- attribute \src "ls180.v:7638.7-7638.190"
- cell $and $and$ls180.v:7638$2443
+ attribute \src "ls180.v:7634.7-7634.190"
+ cell $and $and$ls180.v:7634$2443
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:7638$2441_Y
- connect \B $not$ls180.v:7638$2442_Y
- connect \Y $and$ls180.v:7638$2443_Y
+ connect \A $and$ls180.v:7634$2441_Y
+ connect \B $not$ls180.v:7634$2442_Y
+ connect \Y $and$ls180.v:7634$2443_Y
end
- attribute \src "ls180.v:7644.8-7644.131"
- cell $and $and$ls180.v:7644$2446
+ attribute \src "ls180.v:7640.8-7640.131"
+ cell $and $and$ls180.v:7640$2446
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we
connect \B \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable
- connect \Y $and$ls180.v:7644$2446_Y
+ connect \Y $and$ls180.v:7640$2446_Y
end
- attribute \src "ls180.v:7644.7-7644.190"
- cell $and $and$ls180.v:7644$2448
+ attribute \src "ls180.v:7640.7-7640.190"
+ cell $and $and$ls180.v:7640$2448
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:7644$2446_Y
- connect \B $not$ls180.v:7644$2447_Y
- connect \Y $and$ls180.v:7644$2448_Y
+ connect \A $and$ls180.v:7640$2446_Y
+ connect \B $not$ls180.v:7640$2447_Y
+ connect \Y $and$ls180.v:7640$2448_Y
end
- attribute \src "ls180.v:7684.8-7684.131"
- cell $and $and$ls180.v:7684$2457
+ attribute \src "ls180.v:7680.8-7680.131"
+ cell $and $and$ls180.v:7680$2457
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we
connect \B \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable
- connect \Y $and$ls180.v:7684$2457_Y
+ connect \Y $and$ls180.v:7680$2457_Y
end
- attribute \src "ls180.v:7684.7-7684.190"
- cell $and $and$ls180.v:7684$2459
+ attribute \src "ls180.v:7680.7-7680.190"
+ cell $and $and$ls180.v:7680$2459
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:7684$2457_Y
- connect \B $not$ls180.v:7684$2458_Y
- connect \Y $and$ls180.v:7684$2459_Y
+ connect \A $and$ls180.v:7680$2457_Y
+ connect \B $not$ls180.v:7680$2458_Y
+ connect \Y $and$ls180.v:7680$2459_Y
end
- attribute \src "ls180.v:7690.8-7690.131"
- cell $and $and$ls180.v:7690$2462
+ attribute \src "ls180.v:7686.8-7686.131"
+ cell $and $and$ls180.v:7686$2462
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we
connect \B \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable
- connect \Y $and$ls180.v:7690$2462_Y
+ connect \Y $and$ls180.v:7686$2462_Y
end
- attribute \src "ls180.v:7690.7-7690.190"
- cell $and $and$ls180.v:7690$2464
+ attribute \src "ls180.v:7686.7-7686.190"
+ cell $and $and$ls180.v:7686$2464
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:7690$2462_Y
- connect \B $not$ls180.v:7690$2463_Y
- connect \Y $and$ls180.v:7690$2464_Y
+ connect \A $and$ls180.v:7686$2462_Y
+ connect \B $not$ls180.v:7686$2463_Y
+ connect \Y $and$ls180.v:7686$2464_Y
end
- attribute \src "ls180.v:7730.8-7730.131"
- cell $and $and$ls180.v:7730$2473
+ attribute \src "ls180.v:7726.8-7726.131"
+ cell $and $and$ls180.v:7726$2473
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we
connect \B \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable
- connect \Y $and$ls180.v:7730$2473_Y
+ connect \Y $and$ls180.v:7726$2473_Y
end
- attribute \src "ls180.v:7730.7-7730.190"
- cell $and $and$ls180.v:7730$2475
+ attribute \src "ls180.v:7726.7-7726.190"
+ cell $and $and$ls180.v:7726$2475
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:7730$2473_Y
- connect \B $not$ls180.v:7730$2474_Y
- connect \Y $and$ls180.v:7730$2475_Y
+ connect \A $and$ls180.v:7726$2473_Y
+ connect \B $not$ls180.v:7726$2474_Y
+ connect \Y $and$ls180.v:7726$2475_Y
end
- attribute \src "ls180.v:7736.8-7736.131"
- cell $and $and$ls180.v:7736$2478
+ attribute \src "ls180.v:7732.8-7732.131"
+ cell $and $and$ls180.v:7732$2478
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we
connect \B \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable
- connect \Y $and$ls180.v:7736$2478_Y
+ connect \Y $and$ls180.v:7732$2478_Y
end
- attribute \src "ls180.v:7736.7-7736.190"
- cell $and $and$ls180.v:7736$2480
+ attribute \src "ls180.v:7732.7-7732.190"
+ cell $and $and$ls180.v:7732$2480
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:7736$2478_Y
- connect \B $not$ls180.v:7736$2479_Y
- connect \Y $and$ls180.v:7736$2480_Y
+ connect \A $and$ls180.v:7732$2478_Y
+ connect \B $not$ls180.v:7732$2479_Y
+ connect \Y $and$ls180.v:7732$2480_Y
end
- attribute \src "ls180.v:7933.48-7933.124"
- cell $and $and$ls180.v:7933$2505
+ attribute \src "ls180.v:7929.48-7929.124"
+ cell $and $and$ls180.v:7929$2505
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $eq$ls180.v:7933$2504_Y
+ connect \A $eq$ls180.v:7929$2504_Y
connect \B \main_sdram_interface_bank0_wdata_ready
- connect \Y $and$ls180.v:7933$2505_Y
+ connect \Y $and$ls180.v:7929$2505_Y
end
- attribute \src "ls180.v:7933.130-7933.206"
- cell $and $and$ls180.v:7933$2508
+ attribute \src "ls180.v:7929.130-7929.206"
+ cell $and $and$ls180.v:7929$2508
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $eq$ls180.v:7933$2507_Y
+ connect \A $eq$ls180.v:7929$2507_Y
connect \B \main_sdram_interface_bank1_wdata_ready
- connect \Y $and$ls180.v:7933$2508_Y
+ connect \Y $and$ls180.v:7929$2508_Y
end
- attribute \src "ls180.v:7933.212-7933.288"
- cell $and $and$ls180.v:7933$2511
+ attribute \src "ls180.v:7929.212-7929.288"
+ cell $and $and$ls180.v:7929$2511
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $eq$ls180.v:7933$2510_Y
+ connect \A $eq$ls180.v:7929$2510_Y
connect \B \main_sdram_interface_bank2_wdata_ready
- connect \Y $and$ls180.v:7933$2511_Y
+ connect \Y $and$ls180.v:7929$2511_Y
end
- attribute \src "ls180.v:7933.294-7933.370"
- cell $and $and$ls180.v:7933$2514
+ attribute \src "ls180.v:7929.294-7929.370"
+ cell $and $and$ls180.v:7929$2514
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $eq$ls180.v:7933$2513_Y
+ connect \A $eq$ls180.v:7929$2513_Y
connect \B \main_sdram_interface_bank3_wdata_ready
- connect \Y $and$ls180.v:7933$2514_Y
+ connect \Y $and$ls180.v:7929$2514_Y
end
- attribute \src "ls180.v:7934.49-7934.125"
- cell $and $and$ls180.v:7934$2517
+ attribute \src "ls180.v:7930.49-7930.125"
+ cell $and $and$ls180.v:7930$2517
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $eq$ls180.v:7934$2516_Y
+ connect \A $eq$ls180.v:7930$2516_Y
connect \B \main_sdram_interface_bank0_rdata_valid
- connect \Y $and$ls180.v:7934$2517_Y
+ connect \Y $and$ls180.v:7930$2517_Y
end
- attribute \src "ls180.v:7934.131-7934.207"
- cell $and $and$ls180.v:7934$2520
+ attribute \src "ls180.v:7930.131-7930.207"
+ cell $and $and$ls180.v:7930$2520
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $eq$ls180.v:7934$2519_Y
+ connect \A $eq$ls180.v:7930$2519_Y
connect \B \main_sdram_interface_bank1_rdata_valid
- connect \Y $and$ls180.v:7934$2520_Y
+ connect \Y $and$ls180.v:7930$2520_Y
end
- attribute \src "ls180.v:7934.213-7934.289"
- cell $and $and$ls180.v:7934$2523
+ attribute \src "ls180.v:7930.213-7930.289"
+ cell $and $and$ls180.v:7930$2523
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $eq$ls180.v:7934$2522_Y
+ connect \A $eq$ls180.v:7930$2522_Y
connect \B \main_sdram_interface_bank2_rdata_valid
- connect \Y $and$ls180.v:7934$2523_Y
+ connect \Y $and$ls180.v:7930$2523_Y
end
- attribute \src "ls180.v:7934.295-7934.371"
- cell $and $and$ls180.v:7934$2526
+ attribute \src "ls180.v:7930.295-7930.371"
+ cell $and $and$ls180.v:7930$2526
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $eq$ls180.v:7934$2525_Y
+ connect \A $eq$ls180.v:7930$2525_Y
connect \B \main_sdram_interface_bank3_rdata_valid
- connect \Y $and$ls180.v:7934$2526_Y
+ connect \Y $and$ls180.v:7930$2526_Y
end
- attribute \src "ls180.v:7953.8-7953.49"
- cell $and $and$ls180.v:7953$2529
+ attribute \src "ls180.v:7949.8-7949.49"
+ cell $and $and$ls180.v:7949$2529
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_port_cmd_valid
connect \B \main_port_cmd_ready
- connect \Y $and$ls180.v:7953$2529_Y
+ connect \Y $and$ls180.v:7949$2529_Y
end
- attribute \src "ls180.v:7956.8-7956.53"
- cell $and $and$ls180.v:7956$2530
+ attribute \src "ls180.v:7952.8-7952.53"
+ cell $and $and$ls180.v:7952$2530
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_port_wdata_valid
connect \B \main_port_wdata_ready
- connect \Y $and$ls180.v:7956$2530_Y
+ connect \Y $and$ls180.v:7952$2530_Y
end
- attribute \src "ls180.v:7961.8-7961.59"
- cell $and $and$ls180.v:7961$2532
+ attribute \src "ls180.v:7957.8-7957.59"
+ cell $and $and$ls180.v:7957$2532
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_uart_phy_sink_valid
- connect \B $not$ls180.v:7961$2531_Y
- connect \Y $and$ls180.v:7961$2532_Y
+ connect \B $not$ls180.v:7957$2531_Y
+ connect \Y $and$ls180.v:7957$2532_Y
end
- attribute \src "ls180.v:7961.7-7961.90"
- cell $and $and$ls180.v:7961$2534
+ attribute \src "ls180.v:7957.7-7957.90"
+ cell $and $and$ls180.v:7957$2534
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:7961$2532_Y
- connect \B $not$ls180.v:7961$2533_Y
- connect \Y $and$ls180.v:7961$2534_Y
+ connect \A $and$ls180.v:7957$2532_Y
+ connect \B $not$ls180.v:7957$2533_Y
+ connect \Y $and$ls180.v:7957$2534_Y
end
- attribute \src "ls180.v:7967.8-7967.59"
- cell $and $and$ls180.v:7967$2535
+ attribute \src "ls180.v:7963.8-7963.59"
+ cell $and $and$ls180.v:7963$2535
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_uart_phy_uart_clk_txen
connect \B \main_uart_phy_tx_busy
- connect \Y $and$ls180.v:7967$2535_Y
+ connect \Y $and$ls180.v:7963$2535_Y
end
- attribute \src "ls180.v:7991.8-7991.48"
- cell $and $and$ls180.v:7991$2542
+ attribute \src "ls180.v:7987.8-7987.48"
+ cell $and $and$ls180.v:7987$2542
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $not$ls180.v:7991$2541_Y
+ connect \A $not$ls180.v:7987$2541_Y
connect \B \main_uart_phy_rx_r
- connect \Y $and$ls180.v:7991$2542_Y
+ connect \Y $and$ls180.v:7987$2542_Y
end
- attribute \src "ls180.v:8024.7-8024.57"
- cell $and $and$ls180.v:8024$2548
+ attribute \src "ls180.v:8020.7-8020.57"
+ cell $and $and$ls180.v:8020$2548
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $not$ls180.v:8024$2547_Y
+ connect \A $not$ls180.v:8020$2547_Y
connect \B \main_uart_tx_old_trigger
- connect \Y $and$ls180.v:8024$2548_Y
+ connect \Y $and$ls180.v:8020$2548_Y
end
- attribute \src "ls180.v:8031.7-8031.57"
- cell $and $and$ls180.v:8031$2550
+ attribute \src "ls180.v:8027.7-8027.57"
+ cell $and $and$ls180.v:8027$2550
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $not$ls180.v:8031$2549_Y
+ connect \A $not$ls180.v:8027$2549_Y
connect \B \main_uart_rx_old_trigger
- connect \Y $and$ls180.v:8031$2550_Y
+ connect \Y $and$ls180.v:8027$2550_Y
end
- attribute \src "ls180.v:8041.8-8041.75"
- cell $and $and$ls180.v:8041$2551
+ attribute \src "ls180.v:8037.8-8037.75"
+ cell $and $and$ls180.v:8037$2551
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_uart_tx_fifo_syncfifo_we
connect \B \main_uart_tx_fifo_syncfifo_writable
- connect \Y $and$ls180.v:8041$2551_Y
+ connect \Y $and$ls180.v:8037$2551_Y
end
- attribute \src "ls180.v:8041.7-8041.107"
- cell $and $and$ls180.v:8041$2553
+ attribute \src "ls180.v:8037.7-8037.107"
+ cell $and $and$ls180.v:8037$2553
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:8041$2551_Y
- connect \B $not$ls180.v:8041$2552_Y
- connect \Y $and$ls180.v:8041$2553_Y
+ connect \A $and$ls180.v:8037$2551_Y
+ connect \B $not$ls180.v:8037$2552_Y
+ connect \Y $and$ls180.v:8037$2553_Y
end
- attribute \src "ls180.v:8047.8-8047.75"
- cell $and $and$ls180.v:8047$2556
+ attribute \src "ls180.v:8043.8-8043.75"
+ cell $and $and$ls180.v:8043$2556
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_uart_tx_fifo_syncfifo_we
connect \B \main_uart_tx_fifo_syncfifo_writable
- connect \Y $and$ls180.v:8047$2556_Y
+ connect \Y $and$ls180.v:8043$2556_Y
end
- attribute \src "ls180.v:8047.7-8047.107"
- cell $and $and$ls180.v:8047$2558
+ attribute \src "ls180.v:8043.7-8043.107"
+ cell $and $and$ls180.v:8043$2558
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:8047$2556_Y
- connect \B $not$ls180.v:8047$2557_Y
- connect \Y $and$ls180.v:8047$2558_Y
+ connect \A $and$ls180.v:8043$2556_Y
+ connect \B $not$ls180.v:8043$2557_Y
+ connect \Y $and$ls180.v:8043$2558_Y
end
- attribute \src "ls180.v:8063.8-8063.75"
- cell $and $and$ls180.v:8063$2562
+ attribute \src "ls180.v:8059.8-8059.75"
+ cell $and $and$ls180.v:8059$2562
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_uart_rx_fifo_syncfifo_we
connect \B \main_uart_rx_fifo_syncfifo_writable
- connect \Y $and$ls180.v:8063$2562_Y
+ connect \Y $and$ls180.v:8059$2562_Y
end
- attribute \src "ls180.v:8063.7-8063.107"
- cell $and $and$ls180.v:8063$2564
+ attribute \src "ls180.v:8059.7-8059.107"
+ cell $and $and$ls180.v:8059$2564
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:8063$2562_Y
- connect \B $not$ls180.v:8063$2563_Y
- connect \Y $and$ls180.v:8063$2564_Y
+ connect \A $and$ls180.v:8059$2562_Y
+ connect \B $not$ls180.v:8059$2563_Y
+ connect \Y $and$ls180.v:8059$2564_Y
end
- attribute \src "ls180.v:8069.8-8069.75"
- cell $and $and$ls180.v:8069$2567
+ attribute \src "ls180.v:8065.8-8065.75"
+ cell $and $and$ls180.v:8065$2567
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_uart_rx_fifo_syncfifo_we
connect \B \main_uart_rx_fifo_syncfifo_writable
- connect \Y $and$ls180.v:8069$2567_Y
+ connect \Y $and$ls180.v:8065$2567_Y
end
- attribute \src "ls180.v:8069.7-8069.107"
- cell $and $and$ls180.v:8069$2569
+ attribute \src "ls180.v:8065.7-8065.107"
+ cell $and $and$ls180.v:8065$2569
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:8069$2567_Y
- connect \B $not$ls180.v:8069$2568_Y
- connect \Y $and$ls180.v:8069$2569_Y
+ connect \A $and$ls180.v:8065$2567_Y
+ connect \B $not$ls180.v:8065$2568_Y
+ connect \Y $and$ls180.v:8065$2569_Y
end
- attribute \src "ls180.v:8217.7-8217.96"
- cell $and $and$ls180.v:8217$2597
+ attribute \src "ls180.v:8213.7-8213.96"
+ cell $and $and$ls180.v:8213$2597
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdphy_cmdr_cmdr_converter_source_valid
connect \B \main_sdphy_cmdr_cmdr_converter_source_ready
- connect \Y $and$ls180.v:8217$2597_Y
+ connect \Y $and$ls180.v:8213$2597_Y
end
- attribute \src "ls180.v:8218.8-8218.93"
- cell $and $and$ls180.v:8218$2598
+ attribute \src "ls180.v:8214.8-8214.93"
+ cell $and $and$ls180.v:8214$2598
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdphy_cmdr_cmdr_converter_sink_valid
connect \B \main_sdphy_cmdr_cmdr_converter_sink_ready
- connect \Y $and$ls180.v:8218$2598_Y
+ connect \Y $and$ls180.v:8214$2598_Y
end
- attribute \src "ls180.v:8226.8-8226.93"
- cell $and $and$ls180.v:8226$2599
+ attribute \src "ls180.v:8222.8-8222.93"
+ cell $and $and$ls180.v:8222$2599
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdphy_cmdr_cmdr_converter_sink_valid
connect \B \main_sdphy_cmdr_cmdr_converter_sink_ready
- connect \Y $and$ls180.v:8226$2599_Y
+ connect \Y $and$ls180.v:8222$2599_Y
end
- attribute \src "ls180.v:8298.7-8298.98"
- cell $and $and$ls180.v:8298$2609
+ attribute \src "ls180.v:8294.7-8294.98"
+ cell $and $and$ls180.v:8294$2609
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdphy_dataw_crcr_converter_source_valid
connect \B \main_sdphy_dataw_crcr_converter_source_ready
- connect \Y $and$ls180.v:8298$2609_Y
+ connect \Y $and$ls180.v:8294$2609_Y
end
- attribute \src "ls180.v:8299.8-8299.95"
- cell $and $and$ls180.v:8299$2610
+ attribute \src "ls180.v:8295.8-8295.95"
+ cell $and $and$ls180.v:8295$2610
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdphy_dataw_crcr_converter_sink_valid
connect \B \main_sdphy_dataw_crcr_converter_sink_ready
- connect \Y $and$ls180.v:8299$2610_Y
+ connect \Y $and$ls180.v:8295$2610_Y
end
- attribute \src "ls180.v:8307.8-8307.95"
- cell $and $and$ls180.v:8307$2611
+ attribute \src "ls180.v:8303.8-8303.95"
+ cell $and $and$ls180.v:8303$2611
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdphy_dataw_crcr_converter_sink_valid
connect \B \main_sdphy_dataw_crcr_converter_sink_ready
- connect \Y $and$ls180.v:8307$2611_Y
+ connect \Y $and$ls180.v:8303$2611_Y
end
- attribute \src "ls180.v:8377.7-8377.100"
- cell $and $and$ls180.v:8377$2621
+ attribute \src "ls180.v:8373.7-8373.100"
+ cell $and $and$ls180.v:8373$2621
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdphy_datar_datar_converter_source_valid
connect \B \main_sdphy_datar_datar_converter_source_ready
- connect \Y $and$ls180.v:8377$2621_Y
+ connect \Y $and$ls180.v:8373$2621_Y
end
- attribute \src "ls180.v:8378.8-8378.97"
- cell $and $and$ls180.v:8378$2622
+ attribute \src "ls180.v:8374.8-8374.97"
+ cell $and $and$ls180.v:8374$2622
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdphy_datar_datar_converter_sink_valid
connect \B \main_sdphy_datar_datar_converter_sink_ready
- connect \Y $and$ls180.v:8378$2622_Y
+ connect \Y $and$ls180.v:8374$2622_Y
end
- attribute \src "ls180.v:8386.8-8386.97"
- cell $and $and$ls180.v:8386$2623
+ attribute \src "ls180.v:8382.8-8382.97"
+ cell $and $and$ls180.v:8382$2623
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdphy_datar_datar_converter_sink_valid
connect \B \main_sdphy_datar_datar_converter_sink_ready
- connect \Y $and$ls180.v:8386$2623_Y
+ connect \Y $and$ls180.v:8382$2623_Y
end
- attribute \src "ls180.v:8477.7-8477.82"
- cell $and $and$ls180.v:8477$2629
+ attribute \src "ls180.v:8473.7-8473.82"
+ cell $and $and$ls180.v:8473$2629
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_checker_sink_ready
connect \B \main_sdcore_crc16_checker_sink_valid
- connect \Y $and$ls180.v:8477$2629_Y
+ connect \Y $and$ls180.v:8473$2629_Y
end
- attribute \src "ls180.v:8480.7-8480.82"
- cell $and $and$ls180.v:8480$2630
+ attribute \src "ls180.v:8476.7-8476.82"
+ cell $and $and$ls180.v:8476$2630
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_checker_sink_ready
connect \B \main_sdcore_crc16_checker_sink_valid
- connect \Y $and$ls180.v:8480$2630_Y
+ connect \Y $and$ls180.v:8476$2630_Y
end
- attribute \src "ls180.v:8483.7-8483.82"
- cell $and $and$ls180.v:8483$2631
+ attribute \src "ls180.v:8479.7-8479.82"
+ cell $and $and$ls180.v:8479$2631
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_checker_sink_ready
connect \B \main_sdcore_crc16_checker_sink_valid
- connect \Y $and$ls180.v:8483$2631_Y
+ connect \Y $and$ls180.v:8479$2631_Y
end
- attribute \src "ls180.v:8486.7-8486.82"
- cell $and $and$ls180.v:8486$2632
+ attribute \src "ls180.v:8482.7-8482.82"
+ cell $and $and$ls180.v:8482$2632
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_checker_sink_ready
connect \B \main_sdcore_crc16_checker_sink_valid
- connect \Y $and$ls180.v:8486$2632_Y
+ connect \Y $and$ls180.v:8482$2632_Y
end
- attribute \src "ls180.v:8489.7-8489.82"
- cell $and $and$ls180.v:8489$2633
+ attribute \src "ls180.v:8485.7-8485.82"
+ cell $and $and$ls180.v:8485$2633
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_checker_sink_valid
connect \B \main_sdcore_crc16_checker_sink_ready
- connect \Y $and$ls180.v:8489$2633_Y
+ connect \Y $and$ls180.v:8485$2633_Y
end
- attribute \src "ls180.v:8494.7-8494.82"
- cell $and $and$ls180.v:8494$2634
+ attribute \src "ls180.v:8490.7-8490.82"
+ cell $and $and$ls180.v:8490$2634
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_checker_sink_valid
connect \B \main_sdcore_crc16_checker_sink_ready
- connect \Y $and$ls180.v:8494$2634_Y
+ connect \Y $and$ls180.v:8490$2634_Y
end
- attribute \src "ls180.v:8499.7-8499.82"
- cell $and $and$ls180.v:8499$2635
+ attribute \src "ls180.v:8495.7-8495.82"
+ cell $and $and$ls180.v:8495$2635
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_checker_sink_valid
connect \B \main_sdcore_crc16_checker_sink_ready
- connect \Y $and$ls180.v:8499$2635_Y
+ connect \Y $and$ls180.v:8495$2635_Y
end
- attribute \src "ls180.v:8504.7-8504.82"
- cell $and $and$ls180.v:8504$2636
+ attribute \src "ls180.v:8500.7-8500.82"
+ cell $and $and$ls180.v:8500$2636
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_checker_sink_valid
connect \B \main_sdcore_crc16_checker_sink_ready
- connect \Y $and$ls180.v:8504$2636_Y
+ connect \Y $and$ls180.v:8500$2636_Y
end
- attribute \src "ls180.v:8509.7-8509.82"
- cell $and $and$ls180.v:8509$2637
+ attribute \src "ls180.v:8505.7-8505.82"
+ cell $and $and$ls180.v:8505$2637
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_checker_sink_valid
connect \B \main_sdcore_crc16_checker_sink_ready
- connect \Y $and$ls180.v:8509$2637_Y
+ connect \Y $and$ls180.v:8505$2637_Y
end
- attribute \src "ls180.v:8574.8-8574.83"
- cell $and $and$ls180.v:8574$2640
+ attribute \src "ls180.v:8570.8-8570.83"
+ cell $and $and$ls180.v:8570$2640
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdblock2mem_fifo_syncfifo_we
connect \B \main_sdblock2mem_fifo_syncfifo_writable
- connect \Y $and$ls180.v:8574$2640_Y
+ connect \Y $and$ls180.v:8570$2640_Y
end
- attribute \src "ls180.v:8574.7-8574.119"
- cell $and $and$ls180.v:8574$2642
+ attribute \src "ls180.v:8570.7-8570.119"
+ cell $and $and$ls180.v:8570$2642
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:8574$2640_Y
- connect \B $not$ls180.v:8574$2641_Y
- connect \Y $and$ls180.v:8574$2642_Y
+ connect \A $and$ls180.v:8570$2640_Y
+ connect \B $not$ls180.v:8570$2641_Y
+ connect \Y $and$ls180.v:8570$2642_Y
end
- attribute \src "ls180.v:8580.8-8580.83"
- cell $and $and$ls180.v:8580$2645
+ attribute \src "ls180.v:8576.8-8576.83"
+ cell $and $and$ls180.v:8576$2645
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdblock2mem_fifo_syncfifo_we
connect \B \main_sdblock2mem_fifo_syncfifo_writable
- connect \Y $and$ls180.v:8580$2645_Y
+ connect \Y $and$ls180.v:8576$2645_Y
end
- attribute \src "ls180.v:8580.7-8580.119"
- cell $and $and$ls180.v:8580$2647
+ attribute \src "ls180.v:8576.7-8576.119"
+ cell $and $and$ls180.v:8576$2647
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:8580$2645_Y
- connect \B $not$ls180.v:8580$2646_Y
- connect \Y $and$ls180.v:8580$2647_Y
+ connect \A $and$ls180.v:8576$2645_Y
+ connect \B $not$ls180.v:8576$2646_Y
+ connect \Y $and$ls180.v:8576$2647_Y
end
- attribute \src "ls180.v:8600.7-8600.88"
- cell $and $and$ls180.v:8600$2654
+ attribute \src "ls180.v:8596.7-8596.88"
+ cell $and $and$ls180.v:8596$2654
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdblock2mem_converter_source_valid
connect \B \main_sdblock2mem_converter_source_ready
- connect \Y $and$ls180.v:8600$2654_Y
+ connect \Y $and$ls180.v:8596$2654_Y
end
- attribute \src "ls180.v:8601.8-8601.85"
- cell $and $and$ls180.v:8601$2655
+ attribute \src "ls180.v:8597.8-8597.85"
+ cell $and $and$ls180.v:8597$2655
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdblock2mem_converter_sink_valid
connect \B \main_sdblock2mem_converter_sink_ready
- connect \Y $and$ls180.v:8601$2655_Y
+ connect \Y $and$ls180.v:8597$2655_Y
end
- attribute \src "ls180.v:8609.8-8609.85"
- cell $and $and$ls180.v:8609$2656
+ attribute \src "ls180.v:8605.8-8605.85"
+ cell $and $and$ls180.v:8605$2656
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdblock2mem_converter_sink_valid
connect \B \main_sdblock2mem_converter_sink_ready
- connect \Y $and$ls180.v:8609$2656_Y
+ connect \Y $and$ls180.v:8605$2656_Y
end
- attribute \src "ls180.v:8653.7-8653.88"
- cell $and $and$ls180.v:8653$2660
+ attribute \src "ls180.v:8649.7-8649.88"
+ cell $and $and$ls180.v:8649$2660
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdmem2block_converter_source_valid
connect \B \main_sdmem2block_converter_source_ready
- connect \Y $and$ls180.v:8653$2660_Y
+ connect \Y $and$ls180.v:8649$2660_Y
end
- attribute \src "ls180.v:8660.8-8660.83"
- cell $and $and$ls180.v:8660$2662
+ attribute \src "ls180.v:8656.8-8656.83"
+ cell $and $and$ls180.v:8656$2662
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdmem2block_fifo_syncfifo_we
connect \B \main_sdmem2block_fifo_syncfifo_writable
- connect \Y $and$ls180.v:8660$2662_Y
+ connect \Y $and$ls180.v:8656$2662_Y
end
- attribute \src "ls180.v:8660.7-8660.119"
- cell $and $and$ls180.v:8660$2664
+ attribute \src "ls180.v:8656.7-8656.119"
+ cell $and $and$ls180.v:8656$2664
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:8660$2662_Y
- connect \B $not$ls180.v:8660$2663_Y
- connect \Y $and$ls180.v:8660$2664_Y
+ connect \A $and$ls180.v:8656$2662_Y
+ connect \B $not$ls180.v:8656$2663_Y
+ connect \Y $and$ls180.v:8656$2664_Y
end
- attribute \src "ls180.v:8666.8-8666.83"
- cell $and $and$ls180.v:8666$2667
+ attribute \src "ls180.v:8662.8-8662.83"
+ cell $and $and$ls180.v:8662$2667
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdmem2block_fifo_syncfifo_we
connect \B \main_sdmem2block_fifo_syncfifo_writable
- connect \Y $and$ls180.v:8666$2667_Y
+ connect \Y $and$ls180.v:8662$2667_Y
end
- attribute \src "ls180.v:8666.7-8666.119"
- cell $and $and$ls180.v:8666$2669
+ attribute \src "ls180.v:8662.7-8662.119"
+ cell $and $and$ls180.v:8662$2669
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:8666$2667_Y
- connect \B $not$ls180.v:8666$2668_Y
- connect \Y $and$ls180.v:8666$2669_Y
+ connect \A $and$ls180.v:8662$2667_Y
+ connect \B $not$ls180.v:8662$2668_Y
+ connect \Y $and$ls180.v:8662$2669_Y
end
- attribute \src "ls180.v:2814.42-2814.101"
- cell $eq $eq$ls180.v:2814$18
+ attribute \src "ls180.v:2810.42-2810.101"
+ cell $eq $eq$ls180.v:2810$18
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_libresocsim_interface0_converted_interface_sel
connect \B 1'0
- connect \Y $eq$ls180.v:2814$18_Y
+ connect \Y $eq$ls180.v:2810$18_Y
end
- attribute \src "ls180.v:2821.11-2821.54"
- cell $eq $eq$ls180.v:2821$23
+ attribute \src "ls180.v:2817.11-2817.54"
+ cell $eq $eq$ls180.v:2817$23
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_libresocsim_converter0_counter
connect \B 1'1
- connect \Y $eq$ls180.v:2821$23_Y
+ connect \Y $eq$ls180.v:2817$23_Y
end
- attribute \src "ls180.v:2874.42-2874.101"
- cell $eq $eq$ls180.v:2874$29
+ attribute \src "ls180.v:2870.42-2870.101"
+ cell $eq $eq$ls180.v:2870$29
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_libresocsim_interface1_converted_interface_sel
connect \B 1'0
- connect \Y $eq$ls180.v:2874$29_Y
+ connect \Y $eq$ls180.v:2870$29_Y
end
- attribute \src "ls180.v:2881.11-2881.54"
- cell $eq $eq$ls180.v:2881$34
+ attribute \src "ls180.v:2877.11-2877.54"
+ cell $eq $eq$ls180.v:2877$34
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_libresocsim_converter1_counter
connect \B 1'1
- connect \Y $eq$ls180.v:2881$34_Y
+ connect \Y $eq$ls180.v:2877$34_Y
end
- attribute \src "ls180.v:2934.42-2934.101"
- cell $eq $eq$ls180.v:2934$40
+ attribute \src "ls180.v:2930.42-2930.101"
+ cell $eq $eq$ls180.v:2930$40
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_libresocsim_interface2_converted_interface_sel
connect \B 1'0
- connect \Y $eq$ls180.v:2934$40_Y
+ connect \Y $eq$ls180.v:2930$40_Y
end
- attribute \src "ls180.v:2941.11-2941.54"
- cell $eq $eq$ls180.v:2941$45
+ attribute \src "ls180.v:2937.11-2937.54"
+ cell $eq $eq$ls180.v:2937$45
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_libresocsim_converter2_counter
connect \B 1'1
- connect \Y $eq$ls180.v:2941$45_Y
+ connect \Y $eq$ls180.v:2937$45_Y
end
- attribute \src "ls180.v:3127.34-3127.65"
- cell $eq $eq$ls180.v:3127$73
+ attribute \src "ls180.v:3123.34-3123.65"
+ cell $eq $eq$ls180.v:3123$73
parameter \A_SIGNED 0
parameter \A_WIDTH 10
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_timer_count1
connect \B 1'0
- connect \Y $eq$ls180.v:3127$73_Y
+ connect \Y $eq$ls180.v:3123$73_Y
end
- attribute \src "ls180.v:3131.68-3131.102"
- cell $eq $eq$ls180.v:3131$76
+ attribute \src "ls180.v:3127.68-3127.102"
+ cell $eq $eq$ls180.v:3127$76
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_sequencer_count
connect \B 1'0
- connect \Y $eq$ls180.v:3131$76_Y
+ connect \Y $eq$ls180.v:3127$76_Y
end
- attribute \src "ls180.v:3175.43-3175.134"
- cell $eq $eq$ls180.v:3175$81
+ attribute \src "ls180.v:3171.43-3171.134"
+ cell $eq $eq$ls180.v:3171$81
parameter \A_SIGNED 0
parameter \A_WIDTH 13
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine0_row
connect \B \main_sdram_bankmachine0_cmd_buffer_source_payload_addr [21:9]
- connect \Y $eq$ls180.v:3175$81_Y
+ connect \Y $eq$ls180.v:3171$81_Y
end
- attribute \src "ls180.v:3192.47-3192.88"
- cell $eq $eq$ls180.v:3192$94
+ attribute \src "ls180.v:3188.47-3188.88"
+ cell $eq $eq$ls180.v:3188$94
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine0_row_close
connect \B 1'0
- connect \Y $eq$ls180.v:3192$94_Y
+ connect \Y $eq$ls180.v:3188$94_Y
end
- attribute \src "ls180.v:3332.43-3332.134"
- cell $eq $eq$ls180.v:3332$111
+ attribute \src "ls180.v:3328.43-3328.134"
+ cell $eq $eq$ls180.v:3328$111
parameter \A_SIGNED 0
parameter \A_WIDTH 13
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine1_row
connect \B \main_sdram_bankmachine1_cmd_buffer_source_payload_addr [21:9]
- connect \Y $eq$ls180.v:3332$111_Y
+ connect \Y $eq$ls180.v:3328$111_Y
end
- attribute \src "ls180.v:3349.47-3349.88"
- cell $eq $eq$ls180.v:3349$124
+ attribute \src "ls180.v:3345.47-3345.88"
+ cell $eq $eq$ls180.v:3345$124
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine1_row_close
connect \B 1'0
- connect \Y $eq$ls180.v:3349$124_Y
+ connect \Y $eq$ls180.v:3345$124_Y
end
- attribute \src "ls180.v:3489.43-3489.134"
- cell $eq $eq$ls180.v:3489$141
+ attribute \src "ls180.v:3485.43-3485.134"
+ cell $eq $eq$ls180.v:3485$141
parameter \A_SIGNED 0
parameter \A_WIDTH 13
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine2_row
connect \B \main_sdram_bankmachine2_cmd_buffer_source_payload_addr [21:9]
- connect \Y $eq$ls180.v:3489$141_Y
+ connect \Y $eq$ls180.v:3485$141_Y
end
- attribute \src "ls180.v:3506.47-3506.88"
- cell $eq $eq$ls180.v:3506$154
+ attribute \src "ls180.v:3502.47-3502.88"
+ cell $eq $eq$ls180.v:3502$154
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine2_row_close
connect \B 1'0
- connect \Y $eq$ls180.v:3506$154_Y
+ connect \Y $eq$ls180.v:3502$154_Y
end
- attribute \src "ls180.v:3646.43-3646.134"
- cell $eq $eq$ls180.v:3646$171
+ attribute \src "ls180.v:3642.43-3642.134"
+ cell $eq $eq$ls180.v:3642$171
parameter \A_SIGNED 0
parameter \A_WIDTH 13
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine3_row
connect \B \main_sdram_bankmachine3_cmd_buffer_source_payload_addr [21:9]
- connect \Y $eq$ls180.v:3646$171_Y
+ connect \Y $eq$ls180.v:3642$171_Y
end
- attribute \src "ls180.v:3663.47-3663.88"
- cell $eq $eq$ls180.v:3663$184
+ attribute \src "ls180.v:3659.47-3659.88"
+ cell $eq $eq$ls180.v:3659$184
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine3_row_close
connect \B 1'0
- connect \Y $eq$ls180.v:3663$184_Y
+ connect \Y $eq$ls180.v:3659$184_Y
end
- attribute \src "ls180.v:3800.32-3800.56"
- cell $eq $eq$ls180.v:3800$231
+ attribute \src "ls180.v:3796.32-3796.56"
+ cell $eq $eq$ls180.v:3796$231
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_time0
connect \B 1'0
- connect \Y $eq$ls180.v:3800$231_Y
+ connect \Y $eq$ls180.v:3796$231_Y
end
- attribute \src "ls180.v:3801.32-3801.56"
- cell $eq $eq$ls180.v:3801$232
+ attribute \src "ls180.v:3797.32-3797.56"
+ cell $eq $eq$ls180.v:3797$232
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_time1
connect \B 1'0
- connect \Y $eq$ls180.v:3801$232_Y
+ connect \Y $eq$ls180.v:3797$232_Y
end
- attribute \src "ls180.v:3812.339-3812.418"
- cell $eq $eq$ls180.v:3812$246
+ attribute \src "ls180.v:3808.339-3808.418"
+ cell $eq $eq$ls180.v:3808$246
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine0_cmd_payload_is_read
connect \B \main_sdram_choose_cmd_want_reads
- connect \Y $eq$ls180.v:3812$246_Y
+ connect \Y $eq$ls180.v:3808$246_Y
end
- attribute \src "ls180.v:3812.423-3812.504"
- cell $eq $eq$ls180.v:3812$247
+ attribute \src "ls180.v:3808.423-3808.504"
+ cell $eq $eq$ls180.v:3808$247
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine0_cmd_payload_is_write
connect \B \main_sdram_choose_cmd_want_writes
- connect \Y $eq$ls180.v:3812$247_Y
+ connect \Y $eq$ls180.v:3808$247_Y
end
- attribute \src "ls180.v:3813.339-3813.418"
- cell $eq $eq$ls180.v:3813$259
+ attribute \src "ls180.v:3809.339-3809.418"
+ cell $eq $eq$ls180.v:3809$259
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine1_cmd_payload_is_read
connect \B \main_sdram_choose_cmd_want_reads
- connect \Y $eq$ls180.v:3813$259_Y
+ connect \Y $eq$ls180.v:3809$259_Y
end
- attribute \src "ls180.v:3813.423-3813.504"
- cell $eq $eq$ls180.v:3813$260
+ attribute \src "ls180.v:3809.423-3809.504"
+ cell $eq $eq$ls180.v:3809$260
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine1_cmd_payload_is_write
connect \B \main_sdram_choose_cmd_want_writes
- connect \Y $eq$ls180.v:3813$260_Y
+ connect \Y $eq$ls180.v:3809$260_Y
end
- attribute \src "ls180.v:3814.339-3814.418"
- cell $eq $eq$ls180.v:3814$272
+ attribute \src "ls180.v:3810.339-3810.418"
+ cell $eq $eq$ls180.v:3810$272
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine2_cmd_payload_is_read
connect \B \main_sdram_choose_cmd_want_reads
- connect \Y $eq$ls180.v:3814$272_Y
+ connect \Y $eq$ls180.v:3810$272_Y
end
- attribute \src "ls180.v:3814.423-3814.504"
- cell $eq $eq$ls180.v:3814$273
+ attribute \src "ls180.v:3810.423-3810.504"
+ cell $eq $eq$ls180.v:3810$273
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine2_cmd_payload_is_write
connect \B \main_sdram_choose_cmd_want_writes
- connect \Y $eq$ls180.v:3814$273_Y
+ connect \Y $eq$ls180.v:3810$273_Y
end
- attribute \src "ls180.v:3815.339-3815.418"
- cell $eq $eq$ls180.v:3815$285
+ attribute \src "ls180.v:3811.339-3811.418"
+ cell $eq $eq$ls180.v:3811$285
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine3_cmd_payload_is_read
connect \B \main_sdram_choose_cmd_want_reads
- connect \Y $eq$ls180.v:3815$285_Y
+ connect \Y $eq$ls180.v:3811$285_Y
end
- attribute \src "ls180.v:3815.423-3815.504"
- cell $eq $eq$ls180.v:3815$286
+ attribute \src "ls180.v:3811.423-3811.504"
+ cell $eq $eq$ls180.v:3811$286
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine3_cmd_payload_is_write
connect \B \main_sdram_choose_cmd_want_writes
- connect \Y $eq$ls180.v:3815$286_Y
+ connect \Y $eq$ls180.v:3811$286_Y
end
- attribute \src "ls180.v:3845.339-3845.418"
- cell $eq $eq$ls180.v:3845$304
+ attribute \src "ls180.v:3841.339-3841.418"
+ cell $eq $eq$ls180.v:3841$304
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine0_cmd_payload_is_read
connect \B \main_sdram_choose_req_want_reads
- connect \Y $eq$ls180.v:3845$304_Y
+ connect \Y $eq$ls180.v:3841$304_Y
end
- attribute \src "ls180.v:3845.423-3845.504"
- cell $eq $eq$ls180.v:3845$305
+ attribute \src "ls180.v:3841.423-3841.504"
+ cell $eq $eq$ls180.v:3841$305
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine0_cmd_payload_is_write
connect \B \main_sdram_choose_req_want_writes
- connect \Y $eq$ls180.v:3845$305_Y
+ connect \Y $eq$ls180.v:3841$305_Y
end
- attribute \src "ls180.v:3846.339-3846.418"
- cell $eq $eq$ls180.v:3846$317
+ attribute \src "ls180.v:3842.339-3842.418"
+ cell $eq $eq$ls180.v:3842$317
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine1_cmd_payload_is_read
connect \B \main_sdram_choose_req_want_reads
- connect \Y $eq$ls180.v:3846$317_Y
+ connect \Y $eq$ls180.v:3842$317_Y
end
- attribute \src "ls180.v:3846.423-3846.504"
- cell $eq $eq$ls180.v:3846$318
+ attribute \src "ls180.v:3842.423-3842.504"
+ cell $eq $eq$ls180.v:3842$318
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine1_cmd_payload_is_write
connect \B \main_sdram_choose_req_want_writes
- connect \Y $eq$ls180.v:3846$318_Y
+ connect \Y $eq$ls180.v:3842$318_Y
end
- attribute \src "ls180.v:3847.339-3847.418"
- cell $eq $eq$ls180.v:3847$330
+ attribute \src "ls180.v:3843.339-3843.418"
+ cell $eq $eq$ls180.v:3843$330
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine2_cmd_payload_is_read
connect \B \main_sdram_choose_req_want_reads
- connect \Y $eq$ls180.v:3847$330_Y
+ connect \Y $eq$ls180.v:3843$330_Y
end
- attribute \src "ls180.v:3847.423-3847.504"
- cell $eq $eq$ls180.v:3847$331
+ attribute \src "ls180.v:3843.423-3843.504"
+ cell $eq $eq$ls180.v:3843$331
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine2_cmd_payload_is_write
connect \B \main_sdram_choose_req_want_writes
- connect \Y $eq$ls180.v:3847$331_Y
+ connect \Y $eq$ls180.v:3843$331_Y
end
- attribute \src "ls180.v:3848.339-3848.418"
- cell $eq $eq$ls180.v:3848$343
+ attribute \src "ls180.v:3844.339-3844.418"
+ cell $eq $eq$ls180.v:3844$343
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine3_cmd_payload_is_read
connect \B \main_sdram_choose_req_want_reads
- connect \Y $eq$ls180.v:3848$343_Y
+ connect \Y $eq$ls180.v:3844$343_Y
end
- attribute \src "ls180.v:3848.423-3848.504"
- cell $eq $eq$ls180.v:3848$344
+ attribute \src "ls180.v:3844.423-3844.504"
+ cell $eq $eq$ls180.v:3844$344
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine3_cmd_payload_is_write
connect \B \main_sdram_choose_req_want_writes
- connect \Y $eq$ls180.v:3848$344_Y
+ connect \Y $eq$ls180.v:3844$344_Y
end
- attribute \src "ls180.v:3877.78-3877.113"
- cell $eq $eq$ls180.v:3877$353
+ attribute \src "ls180.v:3873.78-3873.113"
+ cell $eq $eq$ls180.v:3873$353
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_choose_cmd_grant
connect \B 1'0
- connect \Y $eq$ls180.v:3877$353_Y
+ connect \Y $eq$ls180.v:3873$353_Y
end
- attribute \src "ls180.v:3880.78-3880.113"
- cell $eq $eq$ls180.v:3880$356
+ attribute \src "ls180.v:3876.78-3876.113"
+ cell $eq $eq$ls180.v:3876$356
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_choose_req_grant
connect \B 1'0
- connect \Y $eq$ls180.v:3880$356_Y
+ connect \Y $eq$ls180.v:3876$356_Y
end
- attribute \src "ls180.v:3886.78-3886.113"
- cell $eq $eq$ls180.v:3886$360
+ attribute \src "ls180.v:3882.78-3882.113"
+ cell $eq $eq$ls180.v:3882$360
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_choose_cmd_grant
connect \B 1'1
- connect \Y $eq$ls180.v:3886$360_Y
+ connect \Y $eq$ls180.v:3882$360_Y
end
- attribute \src "ls180.v:3889.78-3889.113"
- cell $eq $eq$ls180.v:3889$363
+ attribute \src "ls180.v:3885.78-3885.113"
+ cell $eq $eq$ls180.v:3885$363
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_choose_req_grant
connect \B 1'1
- connect \Y $eq$ls180.v:3889$363_Y
+ connect \Y $eq$ls180.v:3885$363_Y
end
- attribute \src "ls180.v:3895.78-3895.113"
- cell $eq $eq$ls180.v:3895$367
+ attribute \src "ls180.v:3891.78-3891.113"
+ cell $eq $eq$ls180.v:3891$367
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_choose_cmd_grant
connect \B 2'10
- connect \Y $eq$ls180.v:3895$367_Y
+ connect \Y $eq$ls180.v:3891$367_Y
end
- attribute \src "ls180.v:3898.78-3898.113"
- cell $eq $eq$ls180.v:3898$370
+ attribute \src "ls180.v:3894.78-3894.113"
+ cell $eq $eq$ls180.v:3894$370
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_choose_req_grant
connect \B 2'10
- connect \Y $eq$ls180.v:3898$370_Y
+ connect \Y $eq$ls180.v:3894$370_Y
end
- attribute \src "ls180.v:3904.78-3904.113"
- cell $eq $eq$ls180.v:3904$374
+ attribute \src "ls180.v:3900.78-3900.113"
+ cell $eq $eq$ls180.v:3900$374
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_choose_cmd_grant
connect \B 2'11
- connect \Y $eq$ls180.v:3904$374_Y
+ connect \Y $eq$ls180.v:3900$374_Y
end
- attribute \src "ls180.v:3907.78-3907.113"
- cell $eq $eq$ls180.v:3907$377
+ attribute \src "ls180.v:3903.78-3903.113"
+ cell $eq $eq$ls180.v:3903$377
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_choose_req_grant
connect \B 2'11
- connect \Y $eq$ls180.v:3907$377_Y
+ connect \Y $eq$ls180.v:3903$377_Y
end
- attribute \src "ls180.v:3988.42-3988.82"
- cell $eq $eq$ls180.v:3988$400
+ attribute \src "ls180.v:3984.42-3984.82"
+ cell $eq $eq$ls180.v:3984$400
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_port_cmd_payload_addr [10:9]
connect \B 1'0
- connect \Y $eq$ls180.v:3988$400_Y
+ connect \Y $eq$ls180.v:3984$400_Y
end
- attribute \src "ls180.v:3988.145-3988.178"
- cell $eq $eq$ls180.v:3988$401
+ attribute \src "ls180.v:3984.145-3984.178"
+ cell $eq $eq$ls180.v:3984$401
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_roundrobin1_grant
connect \B 1'0
- connect \Y $eq$ls180.v:3988$401_Y
+ connect \Y $eq$ls180.v:3984$401_Y
end
- attribute \src "ls180.v:3988.220-3988.253"
- cell $eq $eq$ls180.v:3988$404
+ attribute \src "ls180.v:3984.220-3984.253"
+ cell $eq $eq$ls180.v:3984$404
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_roundrobin2_grant
connect \B 1'0
- connect \Y $eq$ls180.v:3988$404_Y
+ connect \Y $eq$ls180.v:3984$404_Y
end
- attribute \src "ls180.v:3988.295-3988.328"
- cell $eq $eq$ls180.v:3988$407
+ attribute \src "ls180.v:3984.295-3984.328"
+ cell $eq $eq$ls180.v:3984$407
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_roundrobin3_grant
connect \B 1'0
- connect \Y $eq$ls180.v:3988$407_Y
+ connect \Y $eq$ls180.v:3984$407_Y
end
- attribute \src "ls180.v:3993.42-3993.82"
- cell $eq $eq$ls180.v:3993$416
+ attribute \src "ls180.v:3989.42-3989.82"
+ cell $eq $eq$ls180.v:3989$416
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_port_cmd_payload_addr [10:9]
connect \B 1'1
- connect \Y $eq$ls180.v:3993$416_Y
+ connect \Y $eq$ls180.v:3989$416_Y
end
- attribute \src "ls180.v:3993.145-3993.178"
- cell $eq $eq$ls180.v:3993$417
+ attribute \src "ls180.v:3989.145-3989.178"
+ cell $eq $eq$ls180.v:3989$417
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_roundrobin0_grant
connect \B 1'0
- connect \Y $eq$ls180.v:3993$417_Y
+ connect \Y $eq$ls180.v:3989$417_Y
end
- attribute \src "ls180.v:3993.220-3993.253"
- cell $eq $eq$ls180.v:3993$420
+ attribute \src "ls180.v:3989.220-3989.253"
+ cell $eq $eq$ls180.v:3989$420
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_roundrobin2_grant
connect \B 1'0
- connect \Y $eq$ls180.v:3993$420_Y
+ connect \Y $eq$ls180.v:3989$420_Y
end
- attribute \src "ls180.v:3993.295-3993.328"
- cell $eq $eq$ls180.v:3993$423
+ attribute \src "ls180.v:3989.295-3989.328"
+ cell $eq $eq$ls180.v:3989$423
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_roundrobin3_grant
connect \B 1'0
- connect \Y $eq$ls180.v:3993$423_Y
+ connect \Y $eq$ls180.v:3989$423_Y
end
- attribute \src "ls180.v:3998.42-3998.82"
- cell $eq $eq$ls180.v:3998$432
+ attribute \src "ls180.v:3994.42-3994.82"
+ cell $eq $eq$ls180.v:3994$432
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_port_cmd_payload_addr [10:9]
connect \B 2'10
- connect \Y $eq$ls180.v:3998$432_Y
+ connect \Y $eq$ls180.v:3994$432_Y
end
- attribute \src "ls180.v:3998.145-3998.178"
- cell $eq $eq$ls180.v:3998$433
+ attribute \src "ls180.v:3994.145-3994.178"
+ cell $eq $eq$ls180.v:3994$433
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_roundrobin0_grant
connect \B 1'0
- connect \Y $eq$ls180.v:3998$433_Y
+ connect \Y $eq$ls180.v:3994$433_Y
end
- attribute \src "ls180.v:3998.220-3998.253"
- cell $eq $eq$ls180.v:3998$436
+ attribute \src "ls180.v:3994.220-3994.253"
+ cell $eq $eq$ls180.v:3994$436
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_roundrobin1_grant
connect \B 1'0
- connect \Y $eq$ls180.v:3998$436_Y
+ connect \Y $eq$ls180.v:3994$436_Y
end
- attribute \src "ls180.v:3998.295-3998.328"
- cell $eq $eq$ls180.v:3998$439
+ attribute \src "ls180.v:3994.295-3994.328"
+ cell $eq $eq$ls180.v:3994$439
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_roundrobin3_grant
connect \B 1'0
- connect \Y $eq$ls180.v:3998$439_Y
+ connect \Y $eq$ls180.v:3994$439_Y
end
- attribute \src "ls180.v:4003.42-4003.82"
- cell $eq $eq$ls180.v:4003$448
+ attribute \src "ls180.v:3999.42-3999.82"
+ cell $eq $eq$ls180.v:3999$448
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_port_cmd_payload_addr [10:9]
connect \B 2'11
- connect \Y $eq$ls180.v:4003$448_Y
+ connect \Y $eq$ls180.v:3999$448_Y
end
- attribute \src "ls180.v:4003.145-4003.178"
- cell $eq $eq$ls180.v:4003$449
+ attribute \src "ls180.v:3999.145-3999.178"
+ cell $eq $eq$ls180.v:3999$449
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_roundrobin0_grant
connect \B 1'0
- connect \Y $eq$ls180.v:4003$449_Y
+ connect \Y $eq$ls180.v:3999$449_Y
end
- attribute \src "ls180.v:4003.220-4003.253"
- cell $eq $eq$ls180.v:4003$452
+ attribute \src "ls180.v:3999.220-3999.253"
+ cell $eq $eq$ls180.v:3999$452
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_roundrobin1_grant
connect \B 1'0
- connect \Y $eq$ls180.v:4003$452_Y
+ connect \Y $eq$ls180.v:3999$452_Y
end
- attribute \src "ls180.v:4003.295-4003.328"
- cell $eq $eq$ls180.v:4003$455
+ attribute \src "ls180.v:3999.295-3999.328"
+ cell $eq $eq$ls180.v:3999$455
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_roundrobin2_grant
connect \B 1'0
- connect \Y $eq$ls180.v:4003$455_Y
+ connect \Y $eq$ls180.v:3999$455_Y
end
- attribute \src "ls180.v:4008.44-4008.77"
- cell $eq $eq$ls180.v:4008$464
+ attribute \src "ls180.v:4004.44-4004.77"
+ cell $eq $eq$ls180.v:4004$464
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_roundrobin0_grant
connect \B 1'0
- connect \Y $eq$ls180.v:4008$464_Y
+ connect \Y $eq$ls180.v:4004$464_Y
end
- attribute \src "ls180.v:4008.83-4008.123"
- cell $eq $eq$ls180.v:4008$465
+ attribute \src "ls180.v:4004.83-4004.123"
+ cell $eq $eq$ls180.v:4004$465
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_port_cmd_payload_addr [10:9]
connect \B 1'0
- connect \Y $eq$ls180.v:4008$465_Y
+ connect \Y $eq$ls180.v:4004$465_Y
end
- attribute \src "ls180.v:4008.186-4008.219"
- cell $eq $eq$ls180.v:4008$466
+ attribute \src "ls180.v:4004.186-4004.219"
+ cell $eq $eq$ls180.v:4004$466
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_roundrobin1_grant
connect \B 1'0
- connect \Y $eq$ls180.v:4008$466_Y
+ connect \Y $eq$ls180.v:4004$466_Y
end
- attribute \src "ls180.v:4008.261-4008.294"
- cell $eq $eq$ls180.v:4008$469
+ attribute \src "ls180.v:4004.261-4004.294"
+ cell $eq $eq$ls180.v:4004$469
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_roundrobin2_grant
connect \B 1'0
- connect \Y $eq$ls180.v:4008$469_Y
+ connect \Y $eq$ls180.v:4004$469_Y
end
- attribute \src "ls180.v:4008.336-4008.369"
- cell $eq $eq$ls180.v:4008$472
+ attribute \src "ls180.v:4004.336-4004.369"
+ cell $eq $eq$ls180.v:4004$472
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_roundrobin3_grant
connect \B 1'0
- connect \Y $eq$ls180.v:4008$472_Y
+ connect \Y $eq$ls180.v:4004$472_Y
end
- attribute \src "ls180.v:4008.418-4008.451"
- cell $eq $eq$ls180.v:4008$480
+ attribute \src "ls180.v:4004.418-4004.451"
+ cell $eq $eq$ls180.v:4004$480
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_roundrobin1_grant
connect \B 1'0
- connect \Y $eq$ls180.v:4008$480_Y
+ connect \Y $eq$ls180.v:4004$480_Y
end
- attribute \src "ls180.v:4008.457-4008.497"
- cell $eq $eq$ls180.v:4008$481
+ attribute \src "ls180.v:4004.457-4004.497"
+ cell $eq $eq$ls180.v:4004$481
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_port_cmd_payload_addr [10:9]
connect \B 1'1
- connect \Y $eq$ls180.v:4008$481_Y
+ connect \Y $eq$ls180.v:4004$481_Y
end
- attribute \src "ls180.v:4008.560-4008.593"
- cell $eq $eq$ls180.v:4008$482
+ attribute \src "ls180.v:4004.560-4004.593"
+ cell $eq $eq$ls180.v:4004$482
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_roundrobin0_grant
connect \B 1'0
- connect \Y $eq$ls180.v:4008$482_Y
+ connect \Y $eq$ls180.v:4004$482_Y
end
- attribute \src "ls180.v:4008.635-4008.668"
- cell $eq $eq$ls180.v:4008$485
+ attribute \src "ls180.v:4004.635-4004.668"
+ cell $eq $eq$ls180.v:4004$485
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_roundrobin2_grant
connect \B 1'0
- connect \Y $eq$ls180.v:4008$485_Y
+ connect \Y $eq$ls180.v:4004$485_Y
end
- attribute \src "ls180.v:4008.710-4008.743"
- cell $eq $eq$ls180.v:4008$488
+ attribute \src "ls180.v:4004.710-4004.743"
+ cell $eq $eq$ls180.v:4004$488
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_roundrobin3_grant
connect \B 1'0
- connect \Y $eq$ls180.v:4008$488_Y
+ connect \Y $eq$ls180.v:4004$488_Y
end
- attribute \src "ls180.v:4008.792-4008.825"
- cell $eq $eq$ls180.v:4008$496
+ attribute \src "ls180.v:4004.792-4004.825"
+ cell $eq $eq$ls180.v:4004$496
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_roundrobin2_grant
connect \B 1'0
- connect \Y $eq$ls180.v:4008$496_Y
+ connect \Y $eq$ls180.v:4004$496_Y
end
- attribute \src "ls180.v:4008.831-4008.871"
- cell $eq $eq$ls180.v:4008$497
+ attribute \src "ls180.v:4004.831-4004.871"
+ cell $eq $eq$ls180.v:4004$497
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_port_cmd_payload_addr [10:9]
connect \B 2'10
- connect \Y $eq$ls180.v:4008$497_Y
+ connect \Y $eq$ls180.v:4004$497_Y
end
- attribute \src "ls180.v:4008.934-4008.967"
- cell $eq $eq$ls180.v:4008$498
+ attribute \src "ls180.v:4004.934-4004.967"
+ cell $eq $eq$ls180.v:4004$498
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_roundrobin0_grant
connect \B 1'0
- connect \Y $eq$ls180.v:4008$498_Y
+ connect \Y $eq$ls180.v:4004$498_Y
end
- attribute \src "ls180.v:4008.1009-4008.1042"
- cell $eq $eq$ls180.v:4008$501
+ attribute \src "ls180.v:4004.1009-4004.1042"
+ cell $eq $eq$ls180.v:4004$501
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_roundrobin1_grant
connect \B 1'0
- connect \Y $eq$ls180.v:4008$501_Y
+ connect \Y $eq$ls180.v:4004$501_Y
end
- attribute \src "ls180.v:4008.1084-4008.1117"
- cell $eq $eq$ls180.v:4008$504
+ attribute \src "ls180.v:4004.1084-4004.1117"
+ cell $eq $eq$ls180.v:4004$504
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_roundrobin3_grant
connect \B 1'0
- connect \Y $eq$ls180.v:4008$504_Y
+ connect \Y $eq$ls180.v:4004$504_Y
end
- attribute \src "ls180.v:4008.1166-4008.1199"
- cell $eq $eq$ls180.v:4008$512
+ attribute \src "ls180.v:4004.1166-4004.1199"
+ cell $eq $eq$ls180.v:4004$512
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_roundrobin3_grant
connect \B 1'0
- connect \Y $eq$ls180.v:4008$512_Y
+ connect \Y $eq$ls180.v:4004$512_Y
end
- attribute \src "ls180.v:4008.1205-4008.1245"
- cell $eq $eq$ls180.v:4008$513
+ attribute \src "ls180.v:4004.1205-4004.1245"
+ cell $eq $eq$ls180.v:4004$513
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_port_cmd_payload_addr [10:9]
connect \B 2'11
- connect \Y $eq$ls180.v:4008$513_Y
+ connect \Y $eq$ls180.v:4004$513_Y
end
- attribute \src "ls180.v:4008.1308-4008.1341"
- cell $eq $eq$ls180.v:4008$514
+ attribute \src "ls180.v:4004.1308-4004.1341"
+ cell $eq $eq$ls180.v:4004$514
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_roundrobin0_grant
connect \B 1'0
- connect \Y $eq$ls180.v:4008$514_Y
+ connect \Y $eq$ls180.v:4004$514_Y
end
- attribute \src "ls180.v:4008.1383-4008.1416"
- cell $eq $eq$ls180.v:4008$517
+ attribute \src "ls180.v:4004.1383-4004.1416"
+ cell $eq $eq$ls180.v:4004$517
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_roundrobin1_grant
connect \B 1'0
- connect \Y $eq$ls180.v:4008$517_Y
+ connect \Y $eq$ls180.v:4004$517_Y
end
- attribute \src "ls180.v:4008.1458-4008.1491"
- cell $eq $eq$ls180.v:4008$520
+ attribute \src "ls180.v:4004.1458-4004.1491"
+ cell $eq $eq$ls180.v:4004$520
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_roundrobin2_grant
connect \B 1'0
- connect \Y $eq$ls180.v:4008$520_Y
+ connect \Y $eq$ls180.v:4004$520_Y
end
- attribute \src "ls180.v:4067.29-4067.57"
- cell $eq $eq$ls180.v:4067$533
+ attribute \src "ls180.v:4063.29-4063.57"
+ cell $eq $eq$ls180.v:4063$533
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_litedram_wb_sel
connect \B 1'0
- connect \Y $eq$ls180.v:4067$533_Y
+ connect \Y $eq$ls180.v:4063$533_Y
end
- attribute \src "ls180.v:4074.11-4074.41"
- cell $eq $eq$ls180.v:4074$538
+ attribute \src "ls180.v:4070.11-4070.41"
+ cell $eq $eq$ls180.v:4070$538
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_converter_counter
connect \B 1'1
- connect \Y $eq$ls180.v:4074$538_Y
+ connect \Y $eq$ls180.v:4070$538_Y
end
- attribute \src "ls180.v:4231.37-4231.111"
- cell $eq $eq$ls180.v:4231$603
+ attribute \src "ls180.v:4227.37-4227.111"
+ cell $eq $eq$ls180.v:4227$603
parameter \A_SIGNED 0
parameter \A_WIDTH 16
parameter \B_SIGNED 0
parameter \B_WIDTH 16
parameter \Y_WIDTH 1
connect \A \main_spimaster30_clk_divider
- connect \B $sub$ls180.v:4231$602_Y
- connect \Y $eq$ls180.v:4231$603_Y
+ connect \B $sub$ls180.v:4227$602_Y
+ connect \Y $eq$ls180.v:4227$603_Y
end
- attribute \src "ls180.v:4232.37-4232.105"
- cell $eq $eq$ls180.v:4232$605
+ attribute \src "ls180.v:4228.37-4228.105"
+ cell $eq $eq$ls180.v:4228$605
parameter \A_SIGNED 0
parameter \A_WIDTH 16
parameter \B_SIGNED 0
parameter \B_WIDTH 16
parameter \Y_WIDTH 1
connect \A \main_spimaster30_clk_divider
- connect \B $sub$ls180.v:4232$604_Y
- connect \Y $eq$ls180.v:4232$605_Y
+ connect \B $sub$ls180.v:4228$604_Y
+ connect \Y $eq$ls180.v:4228$605_Y
end
- attribute \src "ls180.v:4259.10-4259.67"
- cell $eq $eq$ls180.v:4259$609
+ attribute \src "ls180.v:4255.10-4255.67"
+ cell $eq $eq$ls180.v:4255$609
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \B_WIDTH 8
parameter \Y_WIDTH 1
connect \A \main_spimaster27_count
- connect \B $sub$ls180.v:4259$608_Y
- connect \Y $eq$ls180.v:4259$609_Y
+ connect \B $sub$ls180.v:4255$608_Y
+ connect \Y $eq$ls180.v:4255$609_Y
end
- attribute \src "ls180.v:4289.35-4289.108"
- cell $eq $eq$ls180.v:4289$611
+ attribute \src "ls180.v:4285.35-4285.108"
+ cell $eq $eq$ls180.v:4285$611
parameter \A_SIGNED 0
parameter \A_WIDTH 16
parameter \B_SIGNED 0
parameter \B_WIDTH 16
parameter \Y_WIDTH 1
connect \A \main_spisdcard_clk_divider1
- connect \B $sub$ls180.v:4289$610_Y
- connect \Y $eq$ls180.v:4289$611_Y
+ connect \B $sub$ls180.v:4285$610_Y
+ connect \Y $eq$ls180.v:4285$611_Y
end
- attribute \src "ls180.v:4290.35-4290.102"
- cell $eq $eq$ls180.v:4290$613
+ attribute \src "ls180.v:4286.35-4286.102"
+ cell $eq $eq$ls180.v:4286$613
parameter \A_SIGNED 0
parameter \A_WIDTH 16
parameter \B_SIGNED 0
parameter \B_WIDTH 16
parameter \Y_WIDTH 1
connect \A \main_spisdcard_clk_divider1
- connect \B $sub$ls180.v:4290$612_Y
- connect \Y $eq$ls180.v:4290$613_Y
+ connect \B $sub$ls180.v:4286$612_Y
+ connect \Y $eq$ls180.v:4286$613_Y
end
- attribute \src "ls180.v:4318.10-4318.65"
- cell $eq $eq$ls180.v:4318$617
+ attribute \src "ls180.v:4314.10-4314.65"
+ cell $eq $eq$ls180.v:4314$617
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \B_WIDTH 8
parameter \Y_WIDTH 1
connect \A \main_spisdcard_count
- connect \B $sub$ls180.v:4318$616_Y
- connect \Y $eq$ls180.v:4318$617_Y
+ connect \B $sub$ls180.v:4314$616_Y
+ connect \Y $eq$ls180.v:4314$617_Y
end
- attribute \src "ls180.v:4422.10-4422.40"
- cell $eq $eq$ls180.v:4422$644
+ attribute \src "ls180.v:4418.10-4418.40"
+ cell $eq $eq$ls180.v:4418$644
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdphy_init_count
connect \B 7'1001111
- connect \Y $eq$ls180.v:4422$644_Y
+ connect \Y $eq$ls180.v:4418$644_Y
end
- attribute \src "ls180.v:4479.10-4479.39"
- cell $eq $eq$ls180.v:4479$647
+ attribute \src "ls180.v:4475.10-4475.39"
+ cell $eq $eq$ls180.v:4475$647
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdphy_cmdw_count
connect \B 3'111
- connect \Y $eq$ls180.v:4479$647_Y
+ connect \Y $eq$ls180.v:4475$647_Y
end
- attribute \src "ls180.v:4496.10-4496.39"
- cell $eq $eq$ls180.v:4496$649
+ attribute \src "ls180.v:4492.10-4492.39"
+ cell $eq $eq$ls180.v:4492$649
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdphy_cmdw_count
connect \B 3'111
- connect \Y $eq$ls180.v:4496$649_Y
+ connect \Y $eq$ls180.v:4492$649_Y
end
- attribute \src "ls180.v:4524.38-4524.88"
- cell $eq $eq$ls180.v:4524$651
+ attribute \src "ls180.v:4520.38-4520.88"
+ cell $eq $eq$ls180.v:4520$651
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdphy_cmdr_cmdr_pads_in_payload_cmd_i
connect \B 1'0
- connect \Y $eq$ls180.v:4524$651_Y
+ connect \Y $eq$ls180.v:4520$651_Y
end
- attribute \src "ls180.v:4574.9-4574.40"
- cell $eq $eq$ls180.v:4574$661
+ attribute \src "ls180.v:4570.9-4570.40"
+ cell $eq $eq$ls180.v:4570$661
parameter \A_SIGNED 0
parameter \A_WIDTH 32
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdphy_cmdr_timeout
connect \B 1'0
- connect \Y $eq$ls180.v:4574$661_Y
+ connect \Y $eq$ls180.v:4570$661_Y
end
- attribute \src "ls180.v:4583.36-4583.105"
- cell $eq $eq$ls180.v:4583$663
+ attribute \src "ls180.v:4579.36-4579.105"
+ cell $eq $eq$ls180.v:4579$663
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \B_WIDTH 8
parameter \Y_WIDTH 1
connect \A \main_sdphy_cmdr_count
- connect \B $sub$ls180.v:4583$662_Y
- connect \Y $eq$ls180.v:4583$663_Y
+ connect \B $sub$ls180.v:4579$662_Y
+ connect \Y $eq$ls180.v:4579$663_Y
end
- attribute \src "ls180.v:4602.9-4602.40"
- cell $eq $eq$ls180.v:4602$667
+ attribute \src "ls180.v:4598.9-4598.40"
+ cell $eq $eq$ls180.v:4598$667
parameter \A_SIGNED 0
parameter \A_WIDTH 32
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdphy_cmdr_timeout
connect \B 1'0
- connect \Y $eq$ls180.v:4602$667_Y
+ connect \Y $eq$ls180.v:4598$667_Y
end
- attribute \src "ls180.v:4614.10-4614.39"
- cell $eq $eq$ls180.v:4614$669
+ attribute \src "ls180.v:4610.10-4610.39"
+ cell $eq $eq$ls180.v:4610$669
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdphy_cmdr_count
connect \B 3'111
- connect \Y $eq$ls180.v:4614$669_Y
+ connect \Y $eq$ls180.v:4610$669_Y
end
- attribute \src "ls180.v:4651.39-4651.94"
- cell $eq $eq$ls180.v:4651$673
+ attribute \src "ls180.v:4647.39-4647.94"
+ cell $eq $eq$ls180.v:4647$673
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdphy_dataw_crcr_pads_in_payload_data_i [0]
connect \B 1'0
- connect \Y $eq$ls180.v:4651$673_Y
+ connect \Y $eq$ls180.v:4647$673_Y
end
- attribute \src "ls180.v:4688.32-4688.89"
- cell $eq $eq$ls180.v:4688$682
+ attribute \src "ls180.v:4684.32-4684.89"
+ cell $eq $eq$ls180.v:4684$682
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdphy_dataw_crcr_source_source_payload_data0
connect \B 3'101
- connect \Y $eq$ls180.v:4688$682_Y
+ connect \Y $eq$ls180.v:4684$682_Y
end
- attribute \src "ls180.v:4736.10-4736.40"
- cell $eq $eq$ls180.v:4736$686
+ attribute \src "ls180.v:4732.10-4732.40"
+ cell $eq $eq$ls180.v:4732$686
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdphy_dataw_count
connect \B 1'1
- connect \Y $eq$ls180.v:4736$686_Y
+ connect \Y $eq$ls180.v:4732$686_Y
end
- attribute \src "ls180.v:4785.40-4785.98"
- cell $eq $eq$ls180.v:4785$688
+ attribute \src "ls180.v:4781.40-4781.98"
+ cell $eq $eq$ls180.v:4781$688
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdphy_datar_datar_pads_in_payload_data_i
connect \B 1'0
- connect \Y $eq$ls180.v:4785$688_Y
+ connect \Y $eq$ls180.v:4781$688_Y
end
- attribute \src "ls180.v:4836.9-4836.41"
- cell $eq $eq$ls180.v:4836$698
+ attribute \src "ls180.v:4832.9-4832.41"
+ cell $eq $eq$ls180.v:4832$698
parameter \A_SIGNED 0
parameter \A_WIDTH 32
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdphy_datar_timeout
connect \B 1'0
- connect \Y $eq$ls180.v:4836$698_Y
+ connect \Y $eq$ls180.v:4832$698_Y
end
- attribute \src "ls180.v:4845.37-4845.123"
- cell $eq $eq$ls180.v:4845$701
+ attribute \src "ls180.v:4841.37-4841.123"
+ cell $eq $eq$ls180.v:4841$701
parameter \A_SIGNED 0
parameter \A_WIDTH 10
parameter \B_SIGNED 0
parameter \B_WIDTH 10
parameter \Y_WIDTH 1
connect \A \main_sdphy_datar_count
- connect \B $sub$ls180.v:4845$700_Y
- connect \Y $eq$ls180.v:4845$701_Y
+ connect \B $sub$ls180.v:4841$700_Y
+ connect \Y $eq$ls180.v:4841$701_Y
end
- attribute \src "ls180.v:4868.9-4868.41"
- cell $eq $eq$ls180.v:4868$704
+ attribute \src "ls180.v:4864.9-4864.41"
+ cell $eq $eq$ls180.v:4864$704
parameter \A_SIGNED 0
parameter \A_WIDTH 32
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdphy_datar_timeout
connect \B 1'0
- connect \Y $eq$ls180.v:4868$704_Y
+ connect \Y $eq$ls180.v:4864$704_Y
end
- attribute \src "ls180.v:4878.10-4878.41"
- cell $eq $eq$ls180.v:4878$706
+ attribute \src "ls180.v:4874.10-4874.41"
+ cell $eq $eq$ls180.v:4874$706
parameter \A_SIGNED 0
parameter \A_WIDTH 10
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdphy_datar_count
connect \B 6'100111
- connect \Y $eq$ls180.v:4878$706_Y
+ connect \Y $eq$ls180.v:4874$706_Y
end
- attribute \src "ls180.v:5047.9-5047.47"
- cell $eq $eq$ls180.v:5047$888
+ attribute \src "ls180.v:5043.9-5043.47"
+ cell $eq $eq$ls180.v:5043$888
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_inserter_cnt
connect \B 3'111
- connect \Y $eq$ls180.v:5047$888_Y
+ connect \Y $eq$ls180.v:5043$888_Y
end
- attribute \src "ls180.v:5077.10-5077.48"
- cell $eq $eq$ls180.v:5077$889
+ attribute \src "ls180.v:5073.10-5073.48"
+ cell $eq $eq$ls180.v:5073$889
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_inserter_cnt
connect \B 3'111
- connect \Y $eq$ls180.v:5077$889_Y
+ connect \Y $eq$ls180.v:5073$889_Y
end
- attribute \src "ls180.v:5108.10-5108.78"
- cell $eq $eq$ls180.v:5108$894
+ attribute \src "ls180.v:5104.10-5104.78"
+ cell $eq $eq$ls180.v:5104$894
parameter \A_SIGNED 0
parameter \A_WIDTH 16
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_checker_fifo0
connect \B \main_sdcore_crc16_checker_crctmp0
- connect \Y $eq$ls180.v:5108$894_Y
+ connect \Y $eq$ls180.v:5104$894_Y
end
- attribute \src "ls180.v:5108.83-5108.151"
- cell $eq $eq$ls180.v:5108$895
+ attribute \src "ls180.v:5104.83-5104.151"
+ cell $eq $eq$ls180.v:5104$895
parameter \A_SIGNED 0
parameter \A_WIDTH 16
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_checker_fifo1
connect \B \main_sdcore_crc16_checker_crctmp1
- connect \Y $eq$ls180.v:5108$895_Y
+ connect \Y $eq$ls180.v:5104$895_Y
end
- attribute \src "ls180.v:5108.157-5108.225"
- cell $eq $eq$ls180.v:5108$897
+ attribute \src "ls180.v:5104.157-5104.225"
+ cell $eq $eq$ls180.v:5104$897
parameter \A_SIGNED 0
parameter \A_WIDTH 16
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_checker_fifo2
connect \B \main_sdcore_crc16_checker_crctmp2
- connect \Y $eq$ls180.v:5108$897_Y
+ connect \Y $eq$ls180.v:5104$897_Y
end
- attribute \src "ls180.v:5108.231-5108.299"
- cell $eq $eq$ls180.v:5108$899
+ attribute \src "ls180.v:5104.231-5104.299"
+ cell $eq $eq$ls180.v:5104$899
parameter \A_SIGNED 0
parameter \A_WIDTH 16
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_checker_fifo3
connect \B \main_sdcore_crc16_checker_crctmp3
- connect \Y $eq$ls180.v:5108$899_Y
+ connect \Y $eq$ls180.v:5104$899_Y
end
- attribute \src "ls180.v:5116.7-5116.44"
- cell $eq $eq$ls180.v:5116$903
+ attribute \src "ls180.v:5112.7-5112.44"
+ cell $eq $eq$ls180.v:5112$903
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_checker_cnt
connect \B 3'111
- connect \Y $eq$ls180.v:5116$903_Y
+ connect \Y $eq$ls180.v:5112$903_Y
end
- attribute \src "ls180.v:5126.7-5126.44"
- cell $eq $eq$ls180.v:5126$906
+ attribute \src "ls180.v:5122.7-5122.44"
+ cell $eq $eq$ls180.v:5122$906
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_checker_cnt
connect \B 3'111
- connect \Y $eq$ls180.v:5126$906_Y
+ connect \Y $eq$ls180.v:5122$906_Y
end
- attribute \src "ls180.v:5136.7-5136.44"
- cell $eq $eq$ls180.v:5136$909
+ attribute \src "ls180.v:5132.7-5132.44"
+ cell $eq $eq$ls180.v:5132$909
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_checker_cnt
connect \B 3'111
- connect \Y $eq$ls180.v:5136$909_Y
+ connect \Y $eq$ls180.v:5132$909_Y
end
- attribute \src "ls180.v:5146.7-5146.44"
- cell $eq $eq$ls180.v:5146$912
+ attribute \src "ls180.v:5142.7-5142.44"
+ cell $eq $eq$ls180.v:5142$912
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_checker_cnt
connect \B 3'111
- connect \Y $eq$ls180.v:5146$912_Y
+ connect \Y $eq$ls180.v:5142$912_Y
end
- attribute \src "ls180.v:5270.36-5270.64"
- cell $eq $eq$ls180.v:5270$963
+ attribute \src "ls180.v:5266.36-5266.64"
+ cell $eq $eq$ls180.v:5266$963
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_cmd_type
connect \B 1'0
- connect \Y $eq$ls180.v:5270$963_Y
+ connect \Y $eq$ls180.v:5266$963_Y
end
- attribute \src "ls180.v:5276.10-5276.39"
- cell $eq $eq$ls180.v:5276$966
+ attribute \src "ls180.v:5272.10-5272.39"
+ cell $eq $eq$ls180.v:5272$966
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_cmd_count
connect \B 3'101
- connect \Y $eq$ls180.v:5276$966_Y
+ connect \Y $eq$ls180.v:5272$966_Y
end
- attribute \src "ls180.v:5277.11-5277.39"
- cell $eq $eq$ls180.v:5277$967
+ attribute \src "ls180.v:5273.11-5273.39"
+ cell $eq $eq$ls180.v:5273$967
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_cmd_type
connect \B 1'0
- connect \Y $eq$ls180.v:5277$967_Y
+ connect \Y $eq$ls180.v:5273$967_Y
end
- attribute \src "ls180.v:5289.34-5289.63"
- cell $eq $eq$ls180.v:5289$968
+ attribute \src "ls180.v:5285.34-5285.63"
+ cell $eq $eq$ls180.v:5285$968
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_data_type
connect \B 1'0
- connect \Y $eq$ls180.v:5289$968_Y
+ connect \Y $eq$ls180.v:5285$968_Y
end
- attribute \src "ls180.v:5290.9-5290.37"
- cell $eq $eq$ls180.v:5290$969
+ attribute \src "ls180.v:5286.9-5286.37"
+ cell $eq $eq$ls180.v:5286$969
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_cmd_type
connect \B 2'10
- connect \Y $eq$ls180.v:5290$969_Y
+ connect \Y $eq$ls180.v:5286$969_Y
end
- attribute \src "ls180.v:5297.10-5297.55"
- cell $eq $eq$ls180.v:5297$970
+ attribute \src "ls180.v:5293.10-5293.55"
+ cell $eq $eq$ls180.v:5293$970
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdphy_cmdr_source_payload_status
connect \B 1'1
- connect \Y $eq$ls180.v:5297$970_Y
+ connect \Y $eq$ls180.v:5293$970_Y
end
- attribute \src "ls180.v:5303.12-5303.41"
- cell $eq $eq$ls180.v:5303$971
+ attribute \src "ls180.v:5299.12-5299.41"
+ cell $eq $eq$ls180.v:5299$971
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_data_type
connect \B 2'10
- connect \Y $eq$ls180.v:5303$971_Y
+ connect \Y $eq$ls180.v:5299$971_Y
end
- attribute \src "ls180.v:5306.13-5306.42"
- cell $eq $eq$ls180.v:5306$972
+ attribute \src "ls180.v:5302.13-5302.42"
+ cell $eq $eq$ls180.v:5302$972
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_data_type
connect \B 1'1
- connect \Y $eq$ls180.v:5306$972_Y
+ connect \Y $eq$ls180.v:5302$972_Y
end
- attribute \src "ls180.v:5328.10-5328.76"
- cell $eq $eq$ls180.v:5328$977
+ attribute \src "ls180.v:5324.10-5324.76"
+ cell $eq $eq$ls180.v:5324$977
parameter \A_SIGNED 0
parameter \A_WIDTH 32
parameter \B_SIGNED 0
parameter \B_WIDTH 32
parameter \Y_WIDTH 1
connect \A \main_sdcore_data_count
- connect \B $sub$ls180.v:5328$976_Y
- connect \Y $eq$ls180.v:5328$977_Y
+ connect \B $sub$ls180.v:5324$976_Y
+ connect \Y $eq$ls180.v:5324$977_Y
end
- attribute \src "ls180.v:5343.35-5343.101"
- cell $eq $eq$ls180.v:5343$980
+ attribute \src "ls180.v:5339.35-5339.101"
+ cell $eq $eq$ls180.v:5339$980
parameter \A_SIGNED 0
parameter \A_WIDTH 32
parameter \B_SIGNED 0
parameter \B_WIDTH 32
parameter \Y_WIDTH 1
connect \A \main_sdcore_data_count
- connect \B $sub$ls180.v:5343$979_Y
- connect \Y $eq$ls180.v:5343$980_Y
+ connect \B $sub$ls180.v:5339$979_Y
+ connect \Y $eq$ls180.v:5339$980_Y
end
- attribute \src "ls180.v:5345.10-5345.56"
- cell $eq $eq$ls180.v:5345$981
+ attribute \src "ls180.v:5341.10-5341.56"
+ cell $eq $eq$ls180.v:5341$981
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdphy_datar_source_payload_status
connect \B 1'0
- connect \Y $eq$ls180.v:5345$981_Y
+ connect \Y $eq$ls180.v:5341$981_Y
end
- attribute \src "ls180.v:5354.12-5354.78"
- cell $eq $eq$ls180.v:5354$985
+ attribute \src "ls180.v:5350.12-5350.78"
+ cell $eq $eq$ls180.v:5350$985
parameter \A_SIGNED 0
parameter \A_WIDTH 32
parameter \B_SIGNED 0
parameter \B_WIDTH 32
parameter \Y_WIDTH 1
connect \A \main_sdcore_data_count
- connect \B $sub$ls180.v:5354$984_Y
- connect \Y $eq$ls180.v:5354$985_Y
+ connect \B $sub$ls180.v:5350$984_Y
+ connect \Y $eq$ls180.v:5350$985_Y
end
- attribute \src "ls180.v:5361.11-5361.57"
- cell $eq $eq$ls180.v:5361$986
+ attribute \src "ls180.v:5357.11-5357.57"
+ cell $eq $eq$ls180.v:5357$986
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdphy_datar_source_payload_status
connect \B 1'1
- connect \Y $eq$ls180.v:5361$986_Y
+ connect \Y $eq$ls180.v:5357$986_Y
end
- attribute \src "ls180.v:5478.10-5478.105"
- cell $eq $eq$ls180.v:5478$1003
+ attribute \src "ls180.v:5474.10-5474.105"
+ cell $eq $eq$ls180.v:5474$1003
parameter \A_SIGNED 0
parameter \A_WIDTH 32
parameter \B_SIGNED 0
parameter \B_WIDTH 32
parameter \Y_WIDTH 1
connect \A \main_sdblock2mem_wishbonedmawriter_offset
- connect \B $sub$ls180.v:5478$1002_Y
- connect \Y $eq$ls180.v:5478$1003_Y
+ connect \B $sub$ls180.v:5474$1002_Y
+ connect \Y $eq$ls180.v:5474$1003_Y
end
- attribute \src "ls180.v:5568.39-5568.106"
- cell $eq $eq$ls180.v:5568$1009
+ attribute \src "ls180.v:5564.39-5564.106"
+ cell $eq $eq$ls180.v:5564$1009
parameter \A_SIGNED 0
parameter \A_WIDTH 32
parameter \B_SIGNED 0
parameter \B_WIDTH 32
parameter \Y_WIDTH 1
connect \A \main_sdmem2block_dma_offset
- connect \B $sub$ls180.v:5568$1008_Y
- connect \Y $eq$ls180.v:5568$1009_Y
+ connect \B $sub$ls180.v:5564$1008_Y
+ connect \Y $eq$ls180.v:5564$1009_Y
end
- attribute \src "ls180.v:5598.44-5598.82"
- cell $eq $eq$ls180.v:5598$1012
+ attribute \src "ls180.v:5594.44-5594.82"
+ cell $eq $eq$ls180.v:5594$1012
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdmem2block_converter_mux
connect \B 1'0
- connect \Y $eq$ls180.v:5598$1012_Y
+ connect \Y $eq$ls180.v:5594$1012_Y
end
- attribute \src "ls180.v:5599.43-5599.81"
- cell $eq $eq$ls180.v:5599$1013
+ attribute \src "ls180.v:5595.43-5595.81"
+ cell $eq $eq$ls180.v:5595$1013
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdmem2block_converter_mux
connect \B 2'11
- connect \Y $eq$ls180.v:5599$1013_Y
+ connect \Y $eq$ls180.v:5595$1013_Y
end
- attribute \src "ls180.v:5699.85-5699.106"
- cell $eq $eq$ls180.v:5699$1029
+ attribute \src "ls180.v:5695.85-5695.106"
+ cell $eq $eq$ls180.v:5695$1029
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_grant
connect \B 1'0
- connect \Y $eq$ls180.v:5699$1029_Y
+ connect \Y $eq$ls180.v:5695$1029_Y
end
- attribute \src "ls180.v:5700.85-5700.106"
- cell $eq $eq$ls180.v:5700$1031
+ attribute \src "ls180.v:5696.85-5696.106"
+ cell $eq $eq$ls180.v:5696$1031
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_grant
connect \B 1'1
- connect \Y $eq$ls180.v:5700$1031_Y
+ connect \Y $eq$ls180.v:5696$1031_Y
end
- attribute \src "ls180.v:5701.85-5701.106"
- cell $eq $eq$ls180.v:5701$1033
+ attribute \src "ls180.v:5697.85-5697.106"
+ cell $eq $eq$ls180.v:5697$1033
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_grant
connect \B 2'10
- connect \Y $eq$ls180.v:5701$1033_Y
+ connect \Y $eq$ls180.v:5697$1033_Y
end
- attribute \src "ls180.v:5702.57-5702.78"
- cell $eq $eq$ls180.v:5702$1035
+ attribute \src "ls180.v:5698.57-5698.78"
+ cell $eq $eq$ls180.v:5698$1035
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_grant
connect \B 2'11
- connect \Y $eq$ls180.v:5702$1035_Y
+ connect \Y $eq$ls180.v:5698$1035_Y
end
- attribute \src "ls180.v:5703.57-5703.78"
- cell $eq $eq$ls180.v:5703$1037
+ attribute \src "ls180.v:5699.57-5699.78"
+ cell $eq $eq$ls180.v:5699$1037
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_grant
connect \B 3'100
- connect \Y $eq$ls180.v:5703$1037_Y
+ connect \Y $eq$ls180.v:5699$1037_Y
end
- attribute \src "ls180.v:5704.85-5704.106"
- cell $eq $eq$ls180.v:5704$1039
+ attribute \src "ls180.v:5700.85-5700.106"
+ cell $eq $eq$ls180.v:5700$1039
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_grant
connect \B 1'0
- connect \Y $eq$ls180.v:5704$1039_Y
+ connect \Y $eq$ls180.v:5700$1039_Y
end
- attribute \src "ls180.v:5705.85-5705.106"
- cell $eq $eq$ls180.v:5705$1041
+ attribute \src "ls180.v:5701.85-5701.106"
+ cell $eq $eq$ls180.v:5701$1041
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_grant
connect \B 1'1
- connect \Y $eq$ls180.v:5705$1041_Y
+ connect \Y $eq$ls180.v:5701$1041_Y
end
- attribute \src "ls180.v:5706.85-5706.106"
- cell $eq $eq$ls180.v:5706$1043
+ attribute \src "ls180.v:5702.85-5702.106"
+ cell $eq $eq$ls180.v:5702$1043
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_grant
connect \B 2'10
- connect \Y $eq$ls180.v:5706$1043_Y
+ connect \Y $eq$ls180.v:5702$1043_Y
end
- attribute \src "ls180.v:5707.57-5707.78"
- cell $eq $eq$ls180.v:5707$1045
+ attribute \src "ls180.v:5703.57-5703.78"
+ cell $eq $eq$ls180.v:5703$1045
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_grant
connect \B 2'11
- connect \Y $eq$ls180.v:5707$1045_Y
+ connect \Y $eq$ls180.v:5703$1045_Y
end
- attribute \src "ls180.v:5708.57-5708.78"
- cell $eq $eq$ls180.v:5708$1047
+ attribute \src "ls180.v:5704.57-5704.78"
+ cell $eq $eq$ls180.v:5704$1047
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_grant
connect \B 3'100
- connect \Y $eq$ls180.v:5708$1047_Y
+ connect \Y $eq$ls180.v:5704$1047_Y
end
- attribute \src "ls180.v:5712.27-5712.59"
- cell $eq $eq$ls180.v:5712$1050
+ attribute \src "ls180.v:5708.27-5708.59"
+ cell $eq $eq$ls180.v:5708$1050
parameter \A_SIGNED 0
parameter \A_WIDTH 23
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_shared_adr [29:7]
connect \B 1'0
- connect \Y $eq$ls180.v:5712$1050_Y
+ connect \Y $eq$ls180.v:5708$1050_Y
end
- attribute \src "ls180.v:5713.27-5713.68"
- cell $eq $eq$ls180.v:5713$1051
+ attribute \src "ls180.v:5709.27-5709.68"
+ cell $eq $eq$ls180.v:5709$1051
parameter \A_SIGNED 0
parameter \A_WIDTH 27
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_shared_adr [29:3]
connect \B 27'110000000000000100000000000
- connect \Y $eq$ls180.v:5713$1051_Y
+ connect \Y $eq$ls180.v:5709$1051_Y
end
- attribute \src "ls180.v:5714.27-5714.66"
- cell $eq $eq$ls180.v:5714$1052
+ attribute \src "ls180.v:5710.27-5710.66"
+ cell $eq $eq$ls180.v:5710$1052
parameter \A_SIGNED 0
parameter \A_WIDTH 20
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_shared_adr [29:10]
connect \B 20'11000000000000010001
- connect \Y $eq$ls180.v:5714$1052_Y
+ connect \Y $eq$ls180.v:5710$1052_Y
end
- attribute \src "ls180.v:5715.27-5715.61"
- cell $eq $eq$ls180.v:5715$1053
+ attribute \src "ls180.v:5711.27-5711.61"
+ cell $eq $eq$ls180.v:5711$1053
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_shared_adr [29:23]
connect \B 7'1001000
- connect \Y $eq$ls180.v:5715$1053_Y
+ connect \Y $eq$ls180.v:5711$1053_Y
end
- attribute \src "ls180.v:5716.27-5716.65"
- cell $eq $eq$ls180.v:5716$1054
+ attribute \src "ls180.v:5712.27-5712.65"
+ cell $eq $eq$ls180.v:5712$1054
parameter \A_SIGNED 0
parameter \A_WIDTH 16
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_shared_adr [29:14]
connect \B 16'1100000000000000
- connect \Y $eq$ls180.v:5716$1054_Y
+ connect \Y $eq$ls180.v:5712$1054_Y
end
- attribute \src "ls180.v:5772.24-5772.45"
- cell $eq $eq$ls180.v:5772$1081
+ attribute \src "ls180.v:5768.24-5768.45"
+ cell $eq $eq$ls180.v:5768$1081
parameter \A_SIGNED 0
parameter \A_WIDTH 20
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_count
connect \B 1'0
- connect \Y $eq$ls180.v:5772$1081_Y
+ connect \Y $eq$ls180.v:5768$1081_Y
end
- attribute \src "ls180.v:5773.32-5773.77"
- cell $eq $eq$ls180.v:5773$1082
+ attribute \src "ls180.v:5769.32-5769.77"
+ cell $eq $eq$ls180.v:5769$1082
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface0_bank_bus_adr [13:9]
connect \B 1'0
- connect \Y $eq$ls180.v:5773$1082_Y
+ connect \Y $eq$ls180.v:5769$1082_Y
end
- attribute \src "ls180.v:5775.97-5775.141"
- cell $eq $eq$ls180.v:5775$1084
+ attribute \src "ls180.v:5771.97-5771.141"
+ cell $eq $eq$ls180.v:5771$1084
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface0_bank_bus_adr [3:0]
connect \B 1'0
- connect \Y $eq$ls180.v:5775$1084_Y
+ connect \Y $eq$ls180.v:5771$1084_Y
end
- attribute \src "ls180.v:5776.100-5776.144"
- cell $eq $eq$ls180.v:5776$1088
+ attribute \src "ls180.v:5772.100-5772.144"
+ cell $eq $eq$ls180.v:5772$1088
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface0_bank_bus_adr [3:0]
connect \B 1'0
- connect \Y $eq$ls180.v:5776$1088_Y
+ connect \Y $eq$ls180.v:5772$1088_Y
end
- attribute \src "ls180.v:5778.99-5778.143"
- cell $eq $eq$ls180.v:5778$1091
+ attribute \src "ls180.v:5774.99-5774.143"
+ cell $eq $eq$ls180.v:5774$1091
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface0_bank_bus_adr [3:0]
connect \B 1'1
- connect \Y $eq$ls180.v:5778$1091_Y
+ connect \Y $eq$ls180.v:5774$1091_Y
end
- attribute \src "ls180.v:5779.102-5779.146"
- cell $eq $eq$ls180.v:5779$1095
+ attribute \src "ls180.v:5775.102-5775.146"
+ cell $eq $eq$ls180.v:5775$1095
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface0_bank_bus_adr [3:0]
connect \B 1'1
- connect \Y $eq$ls180.v:5779$1095_Y
+ connect \Y $eq$ls180.v:5775$1095_Y
end
- attribute \src "ls180.v:5781.99-5781.143"
- cell $eq $eq$ls180.v:5781$1098
+ attribute \src "ls180.v:5777.99-5777.143"
+ cell $eq $eq$ls180.v:5777$1098
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface0_bank_bus_adr [3:0]
connect \B 2'10
- connect \Y $eq$ls180.v:5781$1098_Y
+ connect \Y $eq$ls180.v:5777$1098_Y
end
- attribute \src "ls180.v:5782.102-5782.146"
- cell $eq $eq$ls180.v:5782$1102
+ attribute \src "ls180.v:5778.102-5778.146"
+ cell $eq $eq$ls180.v:5778$1102
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface0_bank_bus_adr [3:0]
connect \B 2'10
- connect \Y $eq$ls180.v:5782$1102_Y
+ connect \Y $eq$ls180.v:5778$1102_Y
end
- attribute \src "ls180.v:5784.99-5784.143"
- cell $eq $eq$ls180.v:5784$1105
+ attribute \src "ls180.v:5780.99-5780.143"
+ cell $eq $eq$ls180.v:5780$1105
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface0_bank_bus_adr [3:0]
connect \B 2'11
- connect \Y $eq$ls180.v:5784$1105_Y
+ connect \Y $eq$ls180.v:5780$1105_Y
end
- attribute \src "ls180.v:5785.102-5785.146"
- cell $eq $eq$ls180.v:5785$1109
+ attribute \src "ls180.v:5781.102-5781.146"
+ cell $eq $eq$ls180.v:5781$1109
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface0_bank_bus_adr [3:0]
connect \B 2'11
- connect \Y $eq$ls180.v:5785$1109_Y
+ connect \Y $eq$ls180.v:5781$1109_Y
end
- attribute \src "ls180.v:5787.99-5787.143"
- cell $eq $eq$ls180.v:5787$1112
+ attribute \src "ls180.v:5783.99-5783.143"
+ cell $eq $eq$ls180.v:5783$1112
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface0_bank_bus_adr [3:0]
connect \B 3'100
- connect \Y $eq$ls180.v:5787$1112_Y
+ connect \Y $eq$ls180.v:5783$1112_Y
end
- attribute \src "ls180.v:5788.102-5788.146"
- cell $eq $eq$ls180.v:5788$1116
+ attribute \src "ls180.v:5784.102-5784.146"
+ cell $eq $eq$ls180.v:5784$1116
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface0_bank_bus_adr [3:0]
connect \B 3'100
- connect \Y $eq$ls180.v:5788$1116_Y
+ connect \Y $eq$ls180.v:5784$1116_Y
end
- attribute \src "ls180.v:5790.102-5790.146"
- cell $eq $eq$ls180.v:5790$1119
+ attribute \src "ls180.v:5786.102-5786.146"
+ cell $eq $eq$ls180.v:5786$1119
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface0_bank_bus_adr [3:0]
connect \B 3'101
- connect \Y $eq$ls180.v:5790$1119_Y
+ connect \Y $eq$ls180.v:5786$1119_Y
end
- attribute \src "ls180.v:5791.105-5791.149"
- cell $eq $eq$ls180.v:5791$1123
+ attribute \src "ls180.v:5787.105-5787.149"
+ cell $eq $eq$ls180.v:5787$1123
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface0_bank_bus_adr [3:0]
connect \B 3'101
- connect \Y $eq$ls180.v:5791$1123_Y
+ connect \Y $eq$ls180.v:5787$1123_Y
end
- attribute \src "ls180.v:5793.102-5793.146"
- cell $eq $eq$ls180.v:5793$1126
+ attribute \src "ls180.v:5789.102-5789.146"
+ cell $eq $eq$ls180.v:5789$1126
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface0_bank_bus_adr [3:0]
connect \B 3'110
- connect \Y $eq$ls180.v:5793$1126_Y
+ connect \Y $eq$ls180.v:5789$1126_Y
end
- attribute \src "ls180.v:5794.105-5794.149"
- cell $eq $eq$ls180.v:5794$1130
+ attribute \src "ls180.v:5790.105-5790.149"
+ cell $eq $eq$ls180.v:5790$1130
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface0_bank_bus_adr [3:0]
connect \B 3'110
- connect \Y $eq$ls180.v:5794$1130_Y
+ connect \Y $eq$ls180.v:5790$1130_Y
end
- attribute \src "ls180.v:5796.102-5796.146"
- cell $eq $eq$ls180.v:5796$1133
+ attribute \src "ls180.v:5792.102-5792.146"
+ cell $eq $eq$ls180.v:5792$1133
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface0_bank_bus_adr [3:0]
connect \B 3'111
- connect \Y $eq$ls180.v:5796$1133_Y
+ connect \Y $eq$ls180.v:5792$1133_Y
end
- attribute \src "ls180.v:5797.105-5797.149"
- cell $eq $eq$ls180.v:5797$1137
+ attribute \src "ls180.v:5793.105-5793.149"
+ cell $eq $eq$ls180.v:5793$1137
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface0_bank_bus_adr [3:0]
connect \B 3'111
- connect \Y $eq$ls180.v:5797$1137_Y
+ connect \Y $eq$ls180.v:5793$1137_Y
end
- attribute \src "ls180.v:5799.102-5799.146"
- cell $eq $eq$ls180.v:5799$1140
+ attribute \src "ls180.v:5795.102-5795.146"
+ cell $eq $eq$ls180.v:5795$1140
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface0_bank_bus_adr [3:0]
connect \B 4'1000
- connect \Y $eq$ls180.v:5799$1140_Y
+ connect \Y $eq$ls180.v:5795$1140_Y
end
- attribute \src "ls180.v:5800.105-5800.149"
- cell $eq $eq$ls180.v:5800$1144
+ attribute \src "ls180.v:5796.105-5796.149"
+ cell $eq $eq$ls180.v:5796$1144
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface0_bank_bus_adr [3:0]
connect \B 4'1000
- connect \Y $eq$ls180.v:5800$1144_Y
+ connect \Y $eq$ls180.v:5796$1144_Y
end
- attribute \src "ls180.v:5811.32-5811.77"
- cell $eq $eq$ls180.v:5811$1146
+ attribute \src "ls180.v:5807.32-5807.77"
+ cell $eq $eq$ls180.v:5807$1146
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface1_bank_bus_adr [13:9]
connect \B 3'110
- connect \Y $eq$ls180.v:5811$1146_Y
+ connect \Y $eq$ls180.v:5807$1146_Y
end
- attribute \src "ls180.v:5813.94-5813.138"
- cell $eq $eq$ls180.v:5813$1148
+ attribute \src "ls180.v:5809.94-5809.138"
+ cell $eq $eq$ls180.v:5809$1148
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface1_bank_bus_adr [2:0]
connect \B 1'0
- connect \Y $eq$ls180.v:5813$1148_Y
+ connect \Y $eq$ls180.v:5809$1148_Y
end
- attribute \src "ls180.v:5814.97-5814.141"
- cell $eq $eq$ls180.v:5814$1152
+ attribute \src "ls180.v:5810.97-5810.141"
+ cell $eq $eq$ls180.v:5810$1152
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface1_bank_bus_adr [2:0]
connect \B 1'0
- connect \Y $eq$ls180.v:5814$1152_Y
+ connect \Y $eq$ls180.v:5810$1152_Y
end
- attribute \src "ls180.v:5816.94-5816.138"
- cell $eq $eq$ls180.v:5816$1155
+ attribute \src "ls180.v:5812.94-5812.138"
+ cell $eq $eq$ls180.v:5812$1155
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface1_bank_bus_adr [2:0]
connect \B 1'1
- connect \Y $eq$ls180.v:5816$1155_Y
+ connect \Y $eq$ls180.v:5812$1155_Y
end
- attribute \src "ls180.v:5817.97-5817.141"
- cell $eq $eq$ls180.v:5817$1159
+ attribute \src "ls180.v:5813.97-5813.141"
+ cell $eq $eq$ls180.v:5813$1159
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface1_bank_bus_adr [2:0]
connect \B 1'1
- connect \Y $eq$ls180.v:5817$1159_Y
+ connect \Y $eq$ls180.v:5813$1159_Y
end
- attribute \src "ls180.v:5819.94-5819.138"
- cell $eq $eq$ls180.v:5819$1162
+ attribute \src "ls180.v:5815.94-5815.138"
+ cell $eq $eq$ls180.v:5815$1162
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface1_bank_bus_adr [2:0]
connect \B 2'10
- connect \Y $eq$ls180.v:5819$1162_Y
+ connect \Y $eq$ls180.v:5815$1162_Y
end
- attribute \src "ls180.v:5820.97-5820.141"
- cell $eq $eq$ls180.v:5820$1166
+ attribute \src "ls180.v:5816.97-5816.141"
+ cell $eq $eq$ls180.v:5816$1166
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface1_bank_bus_adr [2:0]
connect \B 2'10
- connect \Y $eq$ls180.v:5820$1166_Y
+ connect \Y $eq$ls180.v:5816$1166_Y
end
- attribute \src "ls180.v:5822.94-5822.138"
- cell $eq $eq$ls180.v:5822$1169
+ attribute \src "ls180.v:5818.94-5818.138"
+ cell $eq $eq$ls180.v:5818$1169
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface1_bank_bus_adr [2:0]
connect \B 2'11
- connect \Y $eq$ls180.v:5822$1169_Y
+ connect \Y $eq$ls180.v:5818$1169_Y
end
- attribute \src "ls180.v:5823.97-5823.141"
- cell $eq $eq$ls180.v:5823$1173
+ attribute \src "ls180.v:5819.97-5819.141"
+ cell $eq $eq$ls180.v:5819$1173
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface1_bank_bus_adr [2:0]
connect \B 2'11
- connect \Y $eq$ls180.v:5823$1173_Y
+ connect \Y $eq$ls180.v:5819$1173_Y
end
- attribute \src "ls180.v:5825.95-5825.139"
- cell $eq $eq$ls180.v:5825$1176
+ attribute \src "ls180.v:5821.95-5821.139"
+ cell $eq $eq$ls180.v:5821$1176
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface1_bank_bus_adr [2:0]
connect \B 3'100
- connect \Y $eq$ls180.v:5825$1176_Y
+ connect \Y $eq$ls180.v:5821$1176_Y
end
- attribute \src "ls180.v:5826.98-5826.142"
- cell $eq $eq$ls180.v:5826$1180
+ attribute \src "ls180.v:5822.98-5822.142"
+ cell $eq $eq$ls180.v:5822$1180
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface1_bank_bus_adr [2:0]
connect \B 3'100
- connect \Y $eq$ls180.v:5826$1180_Y
+ connect \Y $eq$ls180.v:5822$1180_Y
end
- attribute \src "ls180.v:5828.95-5828.139"
- cell $eq $eq$ls180.v:5828$1183
+ attribute \src "ls180.v:5824.95-5824.139"
+ cell $eq $eq$ls180.v:5824$1183
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface1_bank_bus_adr [2:0]
connect \B 3'101
- connect \Y $eq$ls180.v:5828$1183_Y
+ connect \Y $eq$ls180.v:5824$1183_Y
end
- attribute \src "ls180.v:5829.98-5829.142"
- cell $eq $eq$ls180.v:5829$1187
+ attribute \src "ls180.v:5825.98-5825.142"
+ cell $eq $eq$ls180.v:5825$1187
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface1_bank_bus_adr [2:0]
connect \B 3'101
- connect \Y $eq$ls180.v:5829$1187_Y
+ connect \Y $eq$ls180.v:5825$1187_Y
end
- attribute \src "ls180.v:5837.32-5837.78"
- cell $eq $eq$ls180.v:5837$1189
+ attribute \src "ls180.v:5833.32-5833.78"
+ cell $eq $eq$ls180.v:5833$1189
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface2_bank_bus_adr [13:9]
connect \B 4'1011
- connect \Y $eq$ls180.v:5837$1189_Y
+ connect \Y $eq$ls180.v:5833$1189_Y
end
- attribute \src "ls180.v:5839.93-5839.135"
- cell $eq $eq$ls180.v:5839$1191
+ attribute \src "ls180.v:5835.93-5835.135"
+ cell $eq $eq$ls180.v:5835$1191
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface2_bank_bus_adr [0]
connect \B 1'0
- connect \Y $eq$ls180.v:5839$1191_Y
+ connect \Y $eq$ls180.v:5835$1191_Y
end
- attribute \src "ls180.v:5840.96-5840.138"
- cell $eq $eq$ls180.v:5840$1195
+ attribute \src "ls180.v:5836.96-5836.138"
+ cell $eq $eq$ls180.v:5836$1195
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface2_bank_bus_adr [0]
connect \B 1'0
- connect \Y $eq$ls180.v:5840$1195_Y
+ connect \Y $eq$ls180.v:5836$1195_Y
end
- attribute \src "ls180.v:5842.92-5842.134"
- cell $eq $eq$ls180.v:5842$1198
+ attribute \src "ls180.v:5838.92-5838.134"
+ cell $eq $eq$ls180.v:5838$1198
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface2_bank_bus_adr [0]
connect \B 1'1
- connect \Y $eq$ls180.v:5842$1198_Y
+ connect \Y $eq$ls180.v:5838$1198_Y
end
- attribute \src "ls180.v:5843.95-5843.137"
- cell $eq $eq$ls180.v:5843$1202
+ attribute \src "ls180.v:5839.95-5839.137"
+ cell $eq $eq$ls180.v:5839$1202
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface2_bank_bus_adr [0]
connect \B 1'1
- connect \Y $eq$ls180.v:5843$1202_Y
+ connect \Y $eq$ls180.v:5839$1202_Y
end
- attribute \src "ls180.v:5851.32-5851.77"
- cell $eq $eq$ls180.v:5851$1204
+ attribute \src "ls180.v:5847.32-5847.77"
+ cell $eq $eq$ls180.v:5847$1204
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface3_bank_bus_adr [13:9]
connect \B 4'1001
- connect \Y $eq$ls180.v:5851$1204_Y
+ connect \Y $eq$ls180.v:5847$1204_Y
end
- attribute \src "ls180.v:5853.98-5853.142"
- cell $eq $eq$ls180.v:5853$1206
+ attribute \src "ls180.v:5849.98-5849.142"
+ cell $eq $eq$ls180.v:5849$1206
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface3_bank_bus_adr [3:0]
connect \B 1'0
- connect \Y $eq$ls180.v:5853$1206_Y
+ connect \Y $eq$ls180.v:5849$1206_Y
end
- attribute \src "ls180.v:5854.101-5854.145"
- cell $eq $eq$ls180.v:5854$1210
+ attribute \src "ls180.v:5850.101-5850.145"
+ cell $eq $eq$ls180.v:5850$1210
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface3_bank_bus_adr [3:0]
connect \B 1'0
- connect \Y $eq$ls180.v:5854$1210_Y
+ connect \Y $eq$ls180.v:5850$1210_Y
end
- attribute \src "ls180.v:5856.97-5856.141"
- cell $eq $eq$ls180.v:5856$1213
+ attribute \src "ls180.v:5852.97-5852.141"
+ cell $eq $eq$ls180.v:5852$1213
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface3_bank_bus_adr [3:0]
connect \B 1'1
- connect \Y $eq$ls180.v:5856$1213_Y
+ connect \Y $eq$ls180.v:5852$1213_Y
end
- attribute \src "ls180.v:5857.100-5857.144"
- cell $eq $eq$ls180.v:5857$1217
+ attribute \src "ls180.v:5853.100-5853.144"
+ cell $eq $eq$ls180.v:5853$1217
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface3_bank_bus_adr [3:0]
connect \B 1'1
- connect \Y $eq$ls180.v:5857$1217_Y
+ connect \Y $eq$ls180.v:5853$1217_Y
end
- attribute \src "ls180.v:5859.97-5859.141"
- cell $eq $eq$ls180.v:5859$1220
+ attribute \src "ls180.v:5855.97-5855.141"
+ cell $eq $eq$ls180.v:5855$1220
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface3_bank_bus_adr [3:0]
connect \B 2'10
- connect \Y $eq$ls180.v:5859$1220_Y
+ connect \Y $eq$ls180.v:5855$1220_Y
end
- attribute \src "ls180.v:5860.100-5860.144"
- cell $eq $eq$ls180.v:5860$1224
+ attribute \src "ls180.v:5856.100-5856.144"
+ cell $eq $eq$ls180.v:5856$1224
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface3_bank_bus_adr [3:0]
connect \B 2'10
- connect \Y $eq$ls180.v:5860$1224_Y
+ connect \Y $eq$ls180.v:5856$1224_Y
end
- attribute \src "ls180.v:5862.97-5862.141"
- cell $eq $eq$ls180.v:5862$1227
+ attribute \src "ls180.v:5858.97-5858.141"
+ cell $eq $eq$ls180.v:5858$1227
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface3_bank_bus_adr [3:0]
connect \B 2'11
- connect \Y $eq$ls180.v:5862$1227_Y
+ connect \Y $eq$ls180.v:5858$1227_Y
end
- attribute \src "ls180.v:5863.100-5863.144"
- cell $eq $eq$ls180.v:5863$1231
+ attribute \src "ls180.v:5859.100-5859.144"
+ cell $eq $eq$ls180.v:5859$1231
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface3_bank_bus_adr [3:0]
connect \B 2'11
- connect \Y $eq$ls180.v:5863$1231_Y
+ connect \Y $eq$ls180.v:5859$1231_Y
end
- attribute \src "ls180.v:5865.97-5865.141"
- cell $eq $eq$ls180.v:5865$1234
+ attribute \src "ls180.v:5861.97-5861.141"
+ cell $eq $eq$ls180.v:5861$1234
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface3_bank_bus_adr [3:0]
connect \B 3'100
- connect \Y $eq$ls180.v:5865$1234_Y
+ connect \Y $eq$ls180.v:5861$1234_Y
end
- attribute \src "ls180.v:5866.100-5866.144"
- cell $eq $eq$ls180.v:5866$1238
+ attribute \src "ls180.v:5862.100-5862.144"
+ cell $eq $eq$ls180.v:5862$1238
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface3_bank_bus_adr [3:0]
connect \B 3'100
- connect \Y $eq$ls180.v:5866$1238_Y
+ connect \Y $eq$ls180.v:5862$1238_Y
end
- attribute \src "ls180.v:5868.98-5868.142"
- cell $eq $eq$ls180.v:5868$1241
+ attribute \src "ls180.v:5864.98-5864.142"
+ cell $eq $eq$ls180.v:5864$1241
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface3_bank_bus_adr [3:0]
connect \B 3'101
- connect \Y $eq$ls180.v:5868$1241_Y
+ connect \Y $eq$ls180.v:5864$1241_Y
end
- attribute \src "ls180.v:5869.101-5869.145"
- cell $eq $eq$ls180.v:5869$1245
+ attribute \src "ls180.v:5865.101-5865.145"
+ cell $eq $eq$ls180.v:5865$1245
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface3_bank_bus_adr [3:0]
connect \B 3'101
- connect \Y $eq$ls180.v:5869$1245_Y
+ connect \Y $eq$ls180.v:5865$1245_Y
end
- attribute \src "ls180.v:5871.98-5871.142"
- cell $eq $eq$ls180.v:5871$1248
+ attribute \src "ls180.v:5867.98-5867.142"
+ cell $eq $eq$ls180.v:5867$1248
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface3_bank_bus_adr [3:0]
connect \B 3'110
- connect \Y $eq$ls180.v:5871$1248_Y
+ connect \Y $eq$ls180.v:5867$1248_Y
end
- attribute \src "ls180.v:5872.101-5872.145"
- cell $eq $eq$ls180.v:5872$1252
+ attribute \src "ls180.v:5868.101-5868.145"
+ cell $eq $eq$ls180.v:5868$1252
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface3_bank_bus_adr [3:0]
connect \B 3'110
- connect \Y $eq$ls180.v:5872$1252_Y
+ connect \Y $eq$ls180.v:5868$1252_Y
end
- attribute \src "ls180.v:5874.98-5874.142"
- cell $eq $eq$ls180.v:5874$1255
+ attribute \src "ls180.v:5870.98-5870.142"
+ cell $eq $eq$ls180.v:5870$1255
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface3_bank_bus_adr [3:0]
connect \B 3'111
- connect \Y $eq$ls180.v:5874$1255_Y
+ connect \Y $eq$ls180.v:5870$1255_Y
end
- attribute \src "ls180.v:5875.101-5875.145"
- cell $eq $eq$ls180.v:5875$1259
+ attribute \src "ls180.v:5871.101-5871.145"
+ cell $eq $eq$ls180.v:5871$1259
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface3_bank_bus_adr [3:0]
connect \B 3'111
- connect \Y $eq$ls180.v:5875$1259_Y
+ connect \Y $eq$ls180.v:5871$1259_Y
end
- attribute \src "ls180.v:5877.98-5877.142"
- cell $eq $eq$ls180.v:5877$1262
+ attribute \src "ls180.v:5873.98-5873.142"
+ cell $eq $eq$ls180.v:5873$1262
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface3_bank_bus_adr [3:0]
connect \B 4'1000
- connect \Y $eq$ls180.v:5877$1262_Y
+ connect \Y $eq$ls180.v:5873$1262_Y
end
- attribute \src "ls180.v:5878.101-5878.145"
- cell $eq $eq$ls180.v:5878$1266
+ attribute \src "ls180.v:5874.101-5874.145"
+ cell $eq $eq$ls180.v:5874$1266
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface3_bank_bus_adr [3:0]
connect \B 4'1000
- connect \Y $eq$ls180.v:5878$1266_Y
+ connect \Y $eq$ls180.v:5874$1266_Y
end
- attribute \src "ls180.v:5888.32-5888.78"
- cell $eq $eq$ls180.v:5888$1268
+ attribute \src "ls180.v:5884.32-5884.78"
+ cell $eq $eq$ls180.v:5884$1268
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface4_bank_bus_adr [13:9]
connect \B 4'1010
- connect \Y $eq$ls180.v:5888$1268_Y
+ connect \Y $eq$ls180.v:5884$1268_Y
end
- attribute \src "ls180.v:5890.98-5890.142"
- cell $eq $eq$ls180.v:5890$1270
+ attribute \src "ls180.v:5886.98-5886.142"
+ cell $eq $eq$ls180.v:5886$1270
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface4_bank_bus_adr [3:0]
connect \B 1'0
- connect \Y $eq$ls180.v:5890$1270_Y
+ connect \Y $eq$ls180.v:5886$1270_Y
end
- attribute \src "ls180.v:5891.101-5891.145"
- cell $eq $eq$ls180.v:5891$1274
+ attribute \src "ls180.v:5887.101-5887.145"
+ cell $eq $eq$ls180.v:5887$1274
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface4_bank_bus_adr [3:0]
connect \B 1'0
- connect \Y $eq$ls180.v:5891$1274_Y
+ connect \Y $eq$ls180.v:5887$1274_Y
end
- attribute \src "ls180.v:5893.97-5893.141"
- cell $eq $eq$ls180.v:5893$1277
+ attribute \src "ls180.v:5889.97-5889.141"
+ cell $eq $eq$ls180.v:5889$1277
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface4_bank_bus_adr [3:0]
connect \B 1'1
- connect \Y $eq$ls180.v:5893$1277_Y
+ connect \Y $eq$ls180.v:5889$1277_Y
end
- attribute \src "ls180.v:5894.100-5894.144"
- cell $eq $eq$ls180.v:5894$1281
+ attribute \src "ls180.v:5890.100-5890.144"
+ cell $eq $eq$ls180.v:5890$1281
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface4_bank_bus_adr [3:0]
connect \B 1'1
- connect \Y $eq$ls180.v:5894$1281_Y
+ connect \Y $eq$ls180.v:5890$1281_Y
end
- attribute \src "ls180.v:5896.97-5896.141"
- cell $eq $eq$ls180.v:5896$1284
+ attribute \src "ls180.v:5892.97-5892.141"
+ cell $eq $eq$ls180.v:5892$1284
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface4_bank_bus_adr [3:0]
connect \B 2'10
- connect \Y $eq$ls180.v:5896$1284_Y
+ connect \Y $eq$ls180.v:5892$1284_Y
end
- attribute \src "ls180.v:5897.100-5897.144"
- cell $eq $eq$ls180.v:5897$1288
+ attribute \src "ls180.v:5893.100-5893.144"
+ cell $eq $eq$ls180.v:5893$1288
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface4_bank_bus_adr [3:0]
connect \B 2'10
- connect \Y $eq$ls180.v:5897$1288_Y
+ connect \Y $eq$ls180.v:5893$1288_Y
end
- attribute \src "ls180.v:5899.97-5899.141"
- cell $eq $eq$ls180.v:5899$1291
+ attribute \src "ls180.v:5895.97-5895.141"
+ cell $eq $eq$ls180.v:5895$1291
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface4_bank_bus_adr [3:0]
connect \B 2'11
- connect \Y $eq$ls180.v:5899$1291_Y
+ connect \Y $eq$ls180.v:5895$1291_Y
end
- attribute \src "ls180.v:5900.100-5900.144"
- cell $eq $eq$ls180.v:5900$1295
+ attribute \src "ls180.v:5896.100-5896.144"
+ cell $eq $eq$ls180.v:5896$1295
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface4_bank_bus_adr [3:0]
connect \B 2'11
- connect \Y $eq$ls180.v:5900$1295_Y
+ connect \Y $eq$ls180.v:5896$1295_Y
end
- attribute \src "ls180.v:5902.97-5902.141"
- cell $eq $eq$ls180.v:5902$1298
+ attribute \src "ls180.v:5898.97-5898.141"
+ cell $eq $eq$ls180.v:5898$1298
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface4_bank_bus_adr [3:0]
connect \B 3'100
- connect \Y $eq$ls180.v:5902$1298_Y
+ connect \Y $eq$ls180.v:5898$1298_Y
end
- attribute \src "ls180.v:5903.100-5903.144"
- cell $eq $eq$ls180.v:5903$1302
+ attribute \src "ls180.v:5899.100-5899.144"
+ cell $eq $eq$ls180.v:5899$1302
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface4_bank_bus_adr [3:0]
connect \B 3'100
- connect \Y $eq$ls180.v:5903$1302_Y
+ connect \Y $eq$ls180.v:5899$1302_Y
end
- attribute \src "ls180.v:5905.98-5905.142"
- cell $eq $eq$ls180.v:5905$1305
+ attribute \src "ls180.v:5901.98-5901.142"
+ cell $eq $eq$ls180.v:5901$1305
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface4_bank_bus_adr [3:0]
connect \B 3'101
- connect \Y $eq$ls180.v:5905$1305_Y
+ connect \Y $eq$ls180.v:5901$1305_Y
end
- attribute \src "ls180.v:5906.101-5906.145"
- cell $eq $eq$ls180.v:5906$1309
+ attribute \src "ls180.v:5902.101-5902.145"
+ cell $eq $eq$ls180.v:5902$1309
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface4_bank_bus_adr [3:0]
connect \B 3'101
- connect \Y $eq$ls180.v:5906$1309_Y
+ connect \Y $eq$ls180.v:5902$1309_Y
end
- attribute \src "ls180.v:5908.98-5908.142"
- cell $eq $eq$ls180.v:5908$1312
+ attribute \src "ls180.v:5904.98-5904.142"
+ cell $eq $eq$ls180.v:5904$1312
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface4_bank_bus_adr [3:0]
connect \B 3'110
- connect \Y $eq$ls180.v:5908$1312_Y
+ connect \Y $eq$ls180.v:5904$1312_Y
end
- attribute \src "ls180.v:5909.101-5909.145"
- cell $eq $eq$ls180.v:5909$1316
+ attribute \src "ls180.v:5905.101-5905.145"
+ cell $eq $eq$ls180.v:5905$1316
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface4_bank_bus_adr [3:0]
connect \B 3'110
- connect \Y $eq$ls180.v:5909$1316_Y
+ connect \Y $eq$ls180.v:5905$1316_Y
end
- attribute \src "ls180.v:5911.98-5911.142"
- cell $eq $eq$ls180.v:5911$1319
+ attribute \src "ls180.v:5907.98-5907.142"
+ cell $eq $eq$ls180.v:5907$1319
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface4_bank_bus_adr [3:0]
connect \B 3'111
- connect \Y $eq$ls180.v:5911$1319_Y
+ connect \Y $eq$ls180.v:5907$1319_Y
end
- attribute \src "ls180.v:5912.101-5912.145"
- cell $eq $eq$ls180.v:5912$1323
+ attribute \src "ls180.v:5908.101-5908.145"
+ cell $eq $eq$ls180.v:5908$1323
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface4_bank_bus_adr [3:0]
connect \B 3'111
- connect \Y $eq$ls180.v:5912$1323_Y
+ connect \Y $eq$ls180.v:5908$1323_Y
end
- attribute \src "ls180.v:5914.98-5914.142"
- cell $eq $eq$ls180.v:5914$1326
+ attribute \src "ls180.v:5910.98-5910.142"
+ cell $eq $eq$ls180.v:5910$1326
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface4_bank_bus_adr [3:0]
connect \B 4'1000
- connect \Y $eq$ls180.v:5914$1326_Y
+ connect \Y $eq$ls180.v:5910$1326_Y
end
- attribute \src "ls180.v:5915.101-5915.145"
- cell $eq $eq$ls180.v:5915$1330
+ attribute \src "ls180.v:5911.101-5911.145"
+ cell $eq $eq$ls180.v:5911$1330
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface4_bank_bus_adr [3:0]
connect \B 4'1000
- connect \Y $eq$ls180.v:5915$1330_Y
+ connect \Y $eq$ls180.v:5911$1330_Y
end
- attribute \src "ls180.v:5925.32-5925.78"
- cell $eq $eq$ls180.v:5925$1332
+ attribute \src "ls180.v:5921.32-5921.78"
+ cell $eq $eq$ls180.v:5921$1332
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface5_bank_bus_adr [13:9]
connect \B 4'1110
- connect \Y $eq$ls180.v:5925$1332_Y
+ connect \Y $eq$ls180.v:5921$1332_Y
end
- attribute \src "ls180.v:5927.100-5927.144"
- cell $eq $eq$ls180.v:5927$1334
+ attribute \src "ls180.v:5923.100-5923.144"
+ cell $eq $eq$ls180.v:5923$1334
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface5_bank_bus_adr [3:0]
connect \B 1'0
- connect \Y $eq$ls180.v:5927$1334_Y
+ connect \Y $eq$ls180.v:5923$1334_Y
end
- attribute \src "ls180.v:5928.103-5928.147"
- cell $eq $eq$ls180.v:5928$1338
+ attribute \src "ls180.v:5924.103-5924.147"
+ cell $eq $eq$ls180.v:5924$1338
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface5_bank_bus_adr [3:0]
connect \B 1'0
- connect \Y $eq$ls180.v:5928$1338_Y
+ connect \Y $eq$ls180.v:5924$1338_Y
end
- attribute \src "ls180.v:5930.100-5930.144"
- cell $eq $eq$ls180.v:5930$1341
+ attribute \src "ls180.v:5926.100-5926.144"
+ cell $eq $eq$ls180.v:5926$1341
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface5_bank_bus_adr [3:0]
connect \B 1'1
- connect \Y $eq$ls180.v:5930$1341_Y
+ connect \Y $eq$ls180.v:5926$1341_Y
end
- attribute \src "ls180.v:5931.103-5931.147"
- cell $eq $eq$ls180.v:5931$1345
+ attribute \src "ls180.v:5927.103-5927.147"
+ cell $eq $eq$ls180.v:5927$1345
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface5_bank_bus_adr [3:0]
connect \B 1'1
- connect \Y $eq$ls180.v:5931$1345_Y
+ connect \Y $eq$ls180.v:5927$1345_Y
end
- attribute \src "ls180.v:5933.100-5933.144"
- cell $eq $eq$ls180.v:5933$1348
+ attribute \src "ls180.v:5929.100-5929.144"
+ cell $eq $eq$ls180.v:5929$1348
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface5_bank_bus_adr [3:0]
connect \B 2'10
- connect \Y $eq$ls180.v:5933$1348_Y
+ connect \Y $eq$ls180.v:5929$1348_Y
end
- attribute \src "ls180.v:5934.103-5934.147"
- cell $eq $eq$ls180.v:5934$1352
+ attribute \src "ls180.v:5930.103-5930.147"
+ cell $eq $eq$ls180.v:5930$1352
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface5_bank_bus_adr [3:0]
connect \B 2'10
- connect \Y $eq$ls180.v:5934$1352_Y
+ connect \Y $eq$ls180.v:5930$1352_Y
end
- attribute \src "ls180.v:5936.100-5936.144"
- cell $eq $eq$ls180.v:5936$1355
+ attribute \src "ls180.v:5932.100-5932.144"
+ cell $eq $eq$ls180.v:5932$1355
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface5_bank_bus_adr [3:0]
connect \B 2'11
- connect \Y $eq$ls180.v:5936$1355_Y
+ connect \Y $eq$ls180.v:5932$1355_Y
end
- attribute \src "ls180.v:5937.103-5937.147"
- cell $eq $eq$ls180.v:5937$1359
+ attribute \src "ls180.v:5933.103-5933.147"
+ cell $eq $eq$ls180.v:5933$1359
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface5_bank_bus_adr [3:0]
connect \B 2'11
- connect \Y $eq$ls180.v:5937$1359_Y
+ connect \Y $eq$ls180.v:5933$1359_Y
end
- attribute \src "ls180.v:5939.100-5939.144"
- cell $eq $eq$ls180.v:5939$1362
+ attribute \src "ls180.v:5935.100-5935.144"
+ cell $eq $eq$ls180.v:5935$1362
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface5_bank_bus_adr [3:0]
connect \B 3'100
- connect \Y $eq$ls180.v:5939$1362_Y
+ connect \Y $eq$ls180.v:5935$1362_Y
end
- attribute \src "ls180.v:5940.103-5940.147"
- cell $eq $eq$ls180.v:5940$1366
+ attribute \src "ls180.v:5936.103-5936.147"
+ cell $eq $eq$ls180.v:5936$1366
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface5_bank_bus_adr [3:0]
connect \B 3'100
- connect \Y $eq$ls180.v:5940$1366_Y
+ connect \Y $eq$ls180.v:5936$1366_Y
end
- attribute \src "ls180.v:5942.100-5942.144"
- cell $eq $eq$ls180.v:5942$1369
+ attribute \src "ls180.v:5938.100-5938.144"
+ cell $eq $eq$ls180.v:5938$1369
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface5_bank_bus_adr [3:0]
connect \B 3'101
- connect \Y $eq$ls180.v:5942$1369_Y
+ connect \Y $eq$ls180.v:5938$1369_Y
end
- attribute \src "ls180.v:5943.103-5943.147"
- cell $eq $eq$ls180.v:5943$1373
+ attribute \src "ls180.v:5939.103-5939.147"
+ cell $eq $eq$ls180.v:5939$1373
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface5_bank_bus_adr [3:0]
connect \B 3'101
- connect \Y $eq$ls180.v:5943$1373_Y
+ connect \Y $eq$ls180.v:5939$1373_Y
end
- attribute \src "ls180.v:5945.100-5945.144"
- cell $eq $eq$ls180.v:5945$1376
+ attribute \src "ls180.v:5941.100-5941.144"
+ cell $eq $eq$ls180.v:5941$1376
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface5_bank_bus_adr [3:0]
connect \B 3'110
- connect \Y $eq$ls180.v:5945$1376_Y
+ connect \Y $eq$ls180.v:5941$1376_Y
end
- attribute \src "ls180.v:5946.103-5946.147"
- cell $eq $eq$ls180.v:5946$1380
+ attribute \src "ls180.v:5942.103-5942.147"
+ cell $eq $eq$ls180.v:5942$1380
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface5_bank_bus_adr [3:0]
connect \B 3'110
- connect \Y $eq$ls180.v:5946$1380_Y
+ connect \Y $eq$ls180.v:5942$1380_Y
end
- attribute \src "ls180.v:5948.100-5948.144"
- cell $eq $eq$ls180.v:5948$1383
+ attribute \src "ls180.v:5944.100-5944.144"
+ cell $eq $eq$ls180.v:5944$1383
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface5_bank_bus_adr [3:0]
connect \B 3'111
- connect \Y $eq$ls180.v:5948$1383_Y
+ connect \Y $eq$ls180.v:5944$1383_Y
end
- attribute \src "ls180.v:5949.103-5949.147"
- cell $eq $eq$ls180.v:5949$1387
+ attribute \src "ls180.v:5945.103-5945.147"
+ cell $eq $eq$ls180.v:5945$1387
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface5_bank_bus_adr [3:0]
connect \B 3'111
- connect \Y $eq$ls180.v:5949$1387_Y
+ connect \Y $eq$ls180.v:5945$1387_Y
end
- attribute \src "ls180.v:5951.102-5951.146"
- cell $eq $eq$ls180.v:5951$1390
+ attribute \src "ls180.v:5947.102-5947.146"
+ cell $eq $eq$ls180.v:5947$1390
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface5_bank_bus_adr [3:0]
connect \B 4'1000
- connect \Y $eq$ls180.v:5951$1390_Y
+ connect \Y $eq$ls180.v:5947$1390_Y
end
- attribute \src "ls180.v:5952.105-5952.149"
- cell $eq $eq$ls180.v:5952$1394
+ attribute \src "ls180.v:5948.105-5948.149"
+ cell $eq $eq$ls180.v:5948$1394
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface5_bank_bus_adr [3:0]
connect \B 4'1000
- connect \Y $eq$ls180.v:5952$1394_Y
+ connect \Y $eq$ls180.v:5948$1394_Y
end
- attribute \src "ls180.v:5954.102-5954.146"
- cell $eq $eq$ls180.v:5954$1397
+ attribute \src "ls180.v:5950.102-5950.146"
+ cell $eq $eq$ls180.v:5950$1397
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface5_bank_bus_adr [3:0]
connect \B 4'1001
- connect \Y $eq$ls180.v:5954$1397_Y
+ connect \Y $eq$ls180.v:5950$1397_Y
end
- attribute \src "ls180.v:5955.105-5955.149"
- cell $eq $eq$ls180.v:5955$1401
+ attribute \src "ls180.v:5951.105-5951.149"
+ cell $eq $eq$ls180.v:5951$1401
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface5_bank_bus_adr [3:0]
connect \B 4'1001
- connect \Y $eq$ls180.v:5955$1401_Y
+ connect \Y $eq$ls180.v:5951$1401_Y
end
- attribute \src "ls180.v:5957.102-5957.147"
- cell $eq $eq$ls180.v:5957$1404
+ attribute \src "ls180.v:5953.102-5953.147"
+ cell $eq $eq$ls180.v:5953$1404
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface5_bank_bus_adr [3:0]
connect \B 4'1010
- connect \Y $eq$ls180.v:5957$1404_Y
+ connect \Y $eq$ls180.v:5953$1404_Y
end
- attribute \src "ls180.v:5958.105-5958.150"
- cell $eq $eq$ls180.v:5958$1408
+ attribute \src "ls180.v:5954.105-5954.150"
+ cell $eq $eq$ls180.v:5954$1408
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface5_bank_bus_adr [3:0]
connect \B 4'1010
- connect \Y $eq$ls180.v:5958$1408_Y
+ connect \Y $eq$ls180.v:5954$1408_Y
end
- attribute \src "ls180.v:5960.102-5960.147"
- cell $eq $eq$ls180.v:5960$1411
+ attribute \src "ls180.v:5956.102-5956.147"
+ cell $eq $eq$ls180.v:5956$1411
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface5_bank_bus_adr [3:0]
connect \B 4'1011
- connect \Y $eq$ls180.v:5960$1411_Y
+ connect \Y $eq$ls180.v:5956$1411_Y
end
- attribute \src "ls180.v:5961.105-5961.150"
- cell $eq $eq$ls180.v:5961$1415
+ attribute \src "ls180.v:5957.105-5957.150"
+ cell $eq $eq$ls180.v:5957$1415
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface5_bank_bus_adr [3:0]
connect \B 4'1011
- connect \Y $eq$ls180.v:5961$1415_Y
+ connect \Y $eq$ls180.v:5957$1415_Y
end
- attribute \src "ls180.v:5963.102-5963.147"
- cell $eq $eq$ls180.v:5963$1418
+ attribute \src "ls180.v:5959.102-5959.147"
+ cell $eq $eq$ls180.v:5959$1418
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface5_bank_bus_adr [3:0]
connect \B 4'1100
- connect \Y $eq$ls180.v:5963$1418_Y
+ connect \Y $eq$ls180.v:5959$1418_Y
end
- attribute \src "ls180.v:5964.105-5964.150"
- cell $eq $eq$ls180.v:5964$1422
+ attribute \src "ls180.v:5960.105-5960.150"
+ cell $eq $eq$ls180.v:5960$1422
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface5_bank_bus_adr [3:0]
connect \B 4'1100
- connect \Y $eq$ls180.v:5964$1422_Y
+ connect \Y $eq$ls180.v:5960$1422_Y
end
- attribute \src "ls180.v:5966.99-5966.144"
- cell $eq $eq$ls180.v:5966$1425
+ attribute \src "ls180.v:5962.99-5962.144"
+ cell $eq $eq$ls180.v:5962$1425
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface5_bank_bus_adr [3:0]
connect \B 4'1101
- connect \Y $eq$ls180.v:5966$1425_Y
+ connect \Y $eq$ls180.v:5962$1425_Y
end
- attribute \src "ls180.v:5967.102-5967.147"
- cell $eq $eq$ls180.v:5967$1429
+ attribute \src "ls180.v:5963.102-5963.147"
+ cell $eq $eq$ls180.v:5963$1429
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface5_bank_bus_adr [3:0]
connect \B 4'1101
- connect \Y $eq$ls180.v:5967$1429_Y
+ connect \Y $eq$ls180.v:5963$1429_Y
end
- attribute \src "ls180.v:5969.100-5969.145"
- cell $eq $eq$ls180.v:5969$1432
+ attribute \src "ls180.v:5965.100-5965.145"
+ cell $eq $eq$ls180.v:5965$1432
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface5_bank_bus_adr [3:0]
connect \B 4'1110
- connect \Y $eq$ls180.v:5969$1432_Y
+ connect \Y $eq$ls180.v:5965$1432_Y
end
- attribute \src "ls180.v:5970.103-5970.148"
- cell $eq $eq$ls180.v:5970$1436
+ attribute \src "ls180.v:5966.103-5966.148"
+ cell $eq $eq$ls180.v:5966$1436
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface5_bank_bus_adr [3:0]
connect \B 4'1110
- connect \Y $eq$ls180.v:5970$1436_Y
+ connect \Y $eq$ls180.v:5966$1436_Y
end
- attribute \src "ls180.v:5987.32-5987.78"
- cell $eq $eq$ls180.v:5987$1438
+ attribute \src "ls180.v:5983.32-5983.78"
+ cell $eq $eq$ls180.v:5983$1438
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface6_bank_bus_adr [13:9]
connect \B 4'1101
- connect \Y $eq$ls180.v:5987$1438_Y
+ connect \Y $eq$ls180.v:5983$1438_Y
end
- attribute \src "ls180.v:5989.104-5989.148"
- cell $eq $eq$ls180.v:5989$1440
+ attribute \src "ls180.v:5985.104-5985.148"
+ cell $eq $eq$ls180.v:5985$1440
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface6_bank_bus_adr [5:0]
connect \B 1'0
- connect \Y $eq$ls180.v:5989$1440_Y
+ connect \Y $eq$ls180.v:5985$1440_Y
end
- attribute \src "ls180.v:5990.107-5990.151"
- cell $eq $eq$ls180.v:5990$1444
+ attribute \src "ls180.v:5986.107-5986.151"
+ cell $eq $eq$ls180.v:5986$1444
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface6_bank_bus_adr [5:0]
connect \B 1'0
- connect \Y $eq$ls180.v:5990$1444_Y
+ connect \Y $eq$ls180.v:5986$1444_Y
end
- attribute \src "ls180.v:5992.104-5992.148"
- cell $eq $eq$ls180.v:5992$1447
+ attribute \src "ls180.v:5988.104-5988.148"
+ cell $eq $eq$ls180.v:5988$1447
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface6_bank_bus_adr [5:0]
connect \B 1'1
- connect \Y $eq$ls180.v:5992$1447_Y
+ connect \Y $eq$ls180.v:5988$1447_Y
end
- attribute \src "ls180.v:5993.107-5993.151"
- cell $eq $eq$ls180.v:5993$1451
+ attribute \src "ls180.v:5989.107-5989.151"
+ cell $eq $eq$ls180.v:5989$1451
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface6_bank_bus_adr [5:0]
connect \B 1'1
- connect \Y $eq$ls180.v:5993$1451_Y
+ connect \Y $eq$ls180.v:5989$1451_Y
end
- attribute \src "ls180.v:5995.104-5995.148"
- cell $eq $eq$ls180.v:5995$1454
+ attribute \src "ls180.v:5991.104-5991.148"
+ cell $eq $eq$ls180.v:5991$1454
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface6_bank_bus_adr [5:0]
connect \B 2'10
- connect \Y $eq$ls180.v:5995$1454_Y
+ connect \Y $eq$ls180.v:5991$1454_Y
end
- attribute \src "ls180.v:5996.107-5996.151"
- cell $eq $eq$ls180.v:5996$1458
+ attribute \src "ls180.v:5992.107-5992.151"
+ cell $eq $eq$ls180.v:5992$1458
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface6_bank_bus_adr [5:0]
connect \B 2'10
- connect \Y $eq$ls180.v:5996$1458_Y
+ connect \Y $eq$ls180.v:5992$1458_Y
end
- attribute \src "ls180.v:5998.104-5998.148"
- cell $eq $eq$ls180.v:5998$1461
+ attribute \src "ls180.v:5994.104-5994.148"
+ cell $eq $eq$ls180.v:5994$1461
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface6_bank_bus_adr [5:0]
connect \B 2'11
- connect \Y $eq$ls180.v:5998$1461_Y
+ connect \Y $eq$ls180.v:5994$1461_Y
end
- attribute \src "ls180.v:5999.107-5999.151"
- cell $eq $eq$ls180.v:5999$1465
+ attribute \src "ls180.v:5995.107-5995.151"
+ cell $eq $eq$ls180.v:5995$1465
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface6_bank_bus_adr [5:0]
connect \B 2'11
- connect \Y $eq$ls180.v:5999$1465_Y
+ connect \Y $eq$ls180.v:5995$1465_Y
end
- attribute \src "ls180.v:6001.103-6001.147"
- cell $eq $eq$ls180.v:6001$1468
+ attribute \src "ls180.v:5997.103-5997.147"
+ cell $eq $eq$ls180.v:5997$1468
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface6_bank_bus_adr [5:0]
connect \B 3'100
- connect \Y $eq$ls180.v:6001$1468_Y
+ connect \Y $eq$ls180.v:5997$1468_Y
end
- attribute \src "ls180.v:6002.106-6002.150"
- cell $eq $eq$ls180.v:6002$1472
+ attribute \src "ls180.v:5998.106-5998.150"
+ cell $eq $eq$ls180.v:5998$1472
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface6_bank_bus_adr [5:0]
connect \B 3'100
- connect \Y $eq$ls180.v:6002$1472_Y
+ connect \Y $eq$ls180.v:5998$1472_Y
end
- attribute \src "ls180.v:6004.103-6004.147"
- cell $eq $eq$ls180.v:6004$1475
+ attribute \src "ls180.v:6000.103-6000.147"
+ cell $eq $eq$ls180.v:6000$1475
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface6_bank_bus_adr [5:0]
connect \B 3'101
- connect \Y $eq$ls180.v:6004$1475_Y
+ connect \Y $eq$ls180.v:6000$1475_Y
end
- attribute \src "ls180.v:6005.106-6005.150"
- cell $eq $eq$ls180.v:6005$1479
+ attribute \src "ls180.v:6001.106-6001.150"
+ cell $eq $eq$ls180.v:6001$1479
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface6_bank_bus_adr [5:0]
connect \B 3'101
- connect \Y $eq$ls180.v:6005$1479_Y
+ connect \Y $eq$ls180.v:6001$1479_Y
end
- attribute \src "ls180.v:6007.103-6007.147"
- cell $eq $eq$ls180.v:6007$1482
+ attribute \src "ls180.v:6003.103-6003.147"
+ cell $eq $eq$ls180.v:6003$1482
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface6_bank_bus_adr [5:0]
connect \B 3'110
- connect \Y $eq$ls180.v:6007$1482_Y
+ connect \Y $eq$ls180.v:6003$1482_Y
end
- attribute \src "ls180.v:6008.106-6008.150"
- cell $eq $eq$ls180.v:6008$1486
+ attribute \src "ls180.v:6004.106-6004.150"
+ cell $eq $eq$ls180.v:6004$1486
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface6_bank_bus_adr [5:0]
connect \B 3'110
- connect \Y $eq$ls180.v:6008$1486_Y
+ connect \Y $eq$ls180.v:6004$1486_Y
end
- attribute \src "ls180.v:6010.103-6010.147"
- cell $eq $eq$ls180.v:6010$1489
+ attribute \src "ls180.v:6006.103-6006.147"
+ cell $eq $eq$ls180.v:6006$1489
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface6_bank_bus_adr [5:0]
connect \B 3'111
- connect \Y $eq$ls180.v:6010$1489_Y
+ connect \Y $eq$ls180.v:6006$1489_Y
end
- attribute \src "ls180.v:6011.106-6011.150"
- cell $eq $eq$ls180.v:6011$1493
+ attribute \src "ls180.v:6007.106-6007.150"
+ cell $eq $eq$ls180.v:6007$1493
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface6_bank_bus_adr [5:0]
connect \B 3'111
- connect \Y $eq$ls180.v:6011$1493_Y
+ connect \Y $eq$ls180.v:6007$1493_Y
end
- attribute \src "ls180.v:6013.94-6013.138"
- cell $eq $eq$ls180.v:6013$1496
+ attribute \src "ls180.v:6009.94-6009.138"
+ cell $eq $eq$ls180.v:6009$1496
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface6_bank_bus_adr [5:0]
connect \B 4'1000
- connect \Y $eq$ls180.v:6013$1496_Y
+ connect \Y $eq$ls180.v:6009$1496_Y
end
- attribute \src "ls180.v:6014.97-6014.141"
- cell $eq $eq$ls180.v:6014$1500
+ attribute \src "ls180.v:6010.97-6010.141"
+ cell $eq $eq$ls180.v:6010$1500
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface6_bank_bus_adr [5:0]
connect \B 4'1000
- connect \Y $eq$ls180.v:6014$1500_Y
+ connect \Y $eq$ls180.v:6010$1500_Y
end
- attribute \src "ls180.v:6016.105-6016.149"
- cell $eq $eq$ls180.v:6016$1503
+ attribute \src "ls180.v:6012.105-6012.149"
+ cell $eq $eq$ls180.v:6012$1503
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface6_bank_bus_adr [5:0]
connect \B 4'1001
- connect \Y $eq$ls180.v:6016$1503_Y
+ connect \Y $eq$ls180.v:6012$1503_Y
end
- attribute \src "ls180.v:6017.108-6017.152"
- cell $eq $eq$ls180.v:6017$1507
+ attribute \src "ls180.v:6013.108-6013.152"
+ cell $eq $eq$ls180.v:6013$1507
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface6_bank_bus_adr [5:0]
connect \B 4'1001
- connect \Y $eq$ls180.v:6017$1507_Y
+ connect \Y $eq$ls180.v:6013$1507_Y
end
- attribute \src "ls180.v:6019.105-6019.150"
- cell $eq $eq$ls180.v:6019$1510
+ attribute \src "ls180.v:6015.105-6015.150"
+ cell $eq $eq$ls180.v:6015$1510
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface6_bank_bus_adr [5:0]
connect \B 4'1010
- connect \Y $eq$ls180.v:6019$1510_Y
+ connect \Y $eq$ls180.v:6015$1510_Y
end
- attribute \src "ls180.v:6020.108-6020.153"
- cell $eq $eq$ls180.v:6020$1514
+ attribute \src "ls180.v:6016.108-6016.153"
+ cell $eq $eq$ls180.v:6016$1514
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface6_bank_bus_adr [5:0]
connect \B 4'1010
- connect \Y $eq$ls180.v:6020$1514_Y
+ connect \Y $eq$ls180.v:6016$1514_Y
end
- attribute \src "ls180.v:6022.105-6022.150"
- cell $eq $eq$ls180.v:6022$1517
+ attribute \src "ls180.v:6018.105-6018.150"
+ cell $eq $eq$ls180.v:6018$1517
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface6_bank_bus_adr [5:0]
connect \B 4'1011
- connect \Y $eq$ls180.v:6022$1517_Y
+ connect \Y $eq$ls180.v:6018$1517_Y
end
- attribute \src "ls180.v:6023.108-6023.153"
- cell $eq $eq$ls180.v:6023$1521
+ attribute \src "ls180.v:6019.108-6019.153"
+ cell $eq $eq$ls180.v:6019$1521
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface6_bank_bus_adr [5:0]
connect \B 4'1011
- connect \Y $eq$ls180.v:6023$1521_Y
+ connect \Y $eq$ls180.v:6019$1521_Y
end
- attribute \src "ls180.v:6025.105-6025.150"
- cell $eq $eq$ls180.v:6025$1524
+ attribute \src "ls180.v:6021.105-6021.150"
+ cell $eq $eq$ls180.v:6021$1524
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface6_bank_bus_adr [5:0]
connect \B 4'1100
- connect \Y $eq$ls180.v:6025$1524_Y
+ connect \Y $eq$ls180.v:6021$1524_Y
end
- attribute \src "ls180.v:6026.108-6026.153"
- cell $eq $eq$ls180.v:6026$1528
+ attribute \src "ls180.v:6022.108-6022.153"
+ cell $eq $eq$ls180.v:6022$1528
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface6_bank_bus_adr [5:0]
connect \B 4'1100
- connect \Y $eq$ls180.v:6026$1528_Y
+ connect \Y $eq$ls180.v:6022$1528_Y
end
- attribute \src "ls180.v:6028.105-6028.150"
- cell $eq $eq$ls180.v:6028$1531
+ attribute \src "ls180.v:6024.105-6024.150"
+ cell $eq $eq$ls180.v:6024$1531
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface6_bank_bus_adr [5:0]
connect \B 4'1101
- connect \Y $eq$ls180.v:6028$1531_Y
+ connect \Y $eq$ls180.v:6024$1531_Y
end
- attribute \src "ls180.v:6029.108-6029.153"
- cell $eq $eq$ls180.v:6029$1535
+ attribute \src "ls180.v:6025.108-6025.153"
+ cell $eq $eq$ls180.v:6025$1535
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface6_bank_bus_adr [5:0]
connect \B 4'1101
- connect \Y $eq$ls180.v:6029$1535_Y
+ connect \Y $eq$ls180.v:6025$1535_Y
end
- attribute \src "ls180.v:6031.105-6031.150"
- cell $eq $eq$ls180.v:6031$1538
+ attribute \src "ls180.v:6027.105-6027.150"
+ cell $eq $eq$ls180.v:6027$1538
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface6_bank_bus_adr [5:0]
connect \B 4'1110
- connect \Y $eq$ls180.v:6031$1538_Y
+ connect \Y $eq$ls180.v:6027$1538_Y
end
- attribute \src "ls180.v:6032.108-6032.153"
- cell $eq $eq$ls180.v:6032$1542
+ attribute \src "ls180.v:6028.108-6028.153"
+ cell $eq $eq$ls180.v:6028$1542
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface6_bank_bus_adr [5:0]
connect \B 4'1110
- connect \Y $eq$ls180.v:6032$1542_Y
+ connect \Y $eq$ls180.v:6028$1542_Y
end
- attribute \src "ls180.v:6034.104-6034.149"
- cell $eq $eq$ls180.v:6034$1545
+ attribute \src "ls180.v:6030.104-6030.149"
+ cell $eq $eq$ls180.v:6030$1545
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface6_bank_bus_adr [5:0]
connect \B 4'1111
- connect \Y $eq$ls180.v:6034$1545_Y
+ connect \Y $eq$ls180.v:6030$1545_Y
end
- attribute \src "ls180.v:6035.107-6035.152"
- cell $eq $eq$ls180.v:6035$1549
+ attribute \src "ls180.v:6031.107-6031.152"
+ cell $eq $eq$ls180.v:6031$1549
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface6_bank_bus_adr [5:0]
connect \B 4'1111
- connect \Y $eq$ls180.v:6035$1549_Y
+ connect \Y $eq$ls180.v:6031$1549_Y
end
- attribute \src "ls180.v:6037.104-6037.149"
- cell $eq $eq$ls180.v:6037$1552
+ attribute \src "ls180.v:6033.104-6033.149"
+ cell $eq $eq$ls180.v:6033$1552
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface6_bank_bus_adr [5:0]
connect \B 5'10000
- connect \Y $eq$ls180.v:6037$1552_Y
+ connect \Y $eq$ls180.v:6033$1552_Y
end
- attribute \src "ls180.v:6038.107-6038.152"
- cell $eq $eq$ls180.v:6038$1556
+ attribute \src "ls180.v:6034.107-6034.152"
+ cell $eq $eq$ls180.v:6034$1556
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface6_bank_bus_adr [5:0]
connect \B 5'10000
- connect \Y $eq$ls180.v:6038$1556_Y
+ connect \Y $eq$ls180.v:6034$1556_Y
end
- attribute \src "ls180.v:6040.104-6040.149"
- cell $eq $eq$ls180.v:6040$1559
+ attribute \src "ls180.v:6036.104-6036.149"
+ cell $eq $eq$ls180.v:6036$1559
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface6_bank_bus_adr [5:0]
connect \B 5'10001
- connect \Y $eq$ls180.v:6040$1559_Y
+ connect \Y $eq$ls180.v:6036$1559_Y
end
- attribute \src "ls180.v:6041.107-6041.152"
- cell $eq $eq$ls180.v:6041$1563
+ attribute \src "ls180.v:6037.107-6037.152"
+ cell $eq $eq$ls180.v:6037$1563
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface6_bank_bus_adr [5:0]
connect \B 5'10001
- connect \Y $eq$ls180.v:6041$1563_Y
+ connect \Y $eq$ls180.v:6037$1563_Y
end
- attribute \src "ls180.v:6043.104-6043.149"
- cell $eq $eq$ls180.v:6043$1566
+ attribute \src "ls180.v:6039.104-6039.149"
+ cell $eq $eq$ls180.v:6039$1566
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface6_bank_bus_adr [5:0]
connect \B 5'10010
- connect \Y $eq$ls180.v:6043$1566_Y
+ connect \Y $eq$ls180.v:6039$1566_Y
end
- attribute \src "ls180.v:6044.107-6044.152"
- cell $eq $eq$ls180.v:6044$1570
+ attribute \src "ls180.v:6040.107-6040.152"
+ cell $eq $eq$ls180.v:6040$1570
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface6_bank_bus_adr [5:0]
connect \B 5'10010
- connect \Y $eq$ls180.v:6044$1570_Y
+ connect \Y $eq$ls180.v:6040$1570_Y
end
- attribute \src "ls180.v:6046.104-6046.149"
- cell $eq $eq$ls180.v:6046$1573
+ attribute \src "ls180.v:6042.104-6042.149"
+ cell $eq $eq$ls180.v:6042$1573
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface6_bank_bus_adr [5:0]
connect \B 5'10011
- connect \Y $eq$ls180.v:6046$1573_Y
+ connect \Y $eq$ls180.v:6042$1573_Y
end
- attribute \src "ls180.v:6047.107-6047.152"
- cell $eq $eq$ls180.v:6047$1577
+ attribute \src "ls180.v:6043.107-6043.152"
+ cell $eq $eq$ls180.v:6043$1577
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface6_bank_bus_adr [5:0]
connect \B 5'10011
- connect \Y $eq$ls180.v:6047$1577_Y
+ connect \Y $eq$ls180.v:6043$1577_Y
end
- attribute \src "ls180.v:6049.104-6049.149"
- cell $eq $eq$ls180.v:6049$1580
+ attribute \src "ls180.v:6045.104-6045.149"
+ cell $eq $eq$ls180.v:6045$1580
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface6_bank_bus_adr [5:0]
connect \B 5'10100
- connect \Y $eq$ls180.v:6049$1580_Y
+ connect \Y $eq$ls180.v:6045$1580_Y
end
- attribute \src "ls180.v:6050.107-6050.152"
- cell $eq $eq$ls180.v:6050$1584
+ attribute \src "ls180.v:6046.107-6046.152"
+ cell $eq $eq$ls180.v:6046$1584
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface6_bank_bus_adr [5:0]
connect \B 5'10100
- connect \Y $eq$ls180.v:6050$1584_Y
+ connect \Y $eq$ls180.v:6046$1584_Y
end
- attribute \src "ls180.v:6052.104-6052.149"
- cell $eq $eq$ls180.v:6052$1587
+ attribute \src "ls180.v:6048.104-6048.149"
+ cell $eq $eq$ls180.v:6048$1587
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface6_bank_bus_adr [5:0]
connect \B 5'10101
- connect \Y $eq$ls180.v:6052$1587_Y
+ connect \Y $eq$ls180.v:6048$1587_Y
end
- attribute \src "ls180.v:6053.107-6053.152"
- cell $eq $eq$ls180.v:6053$1591
+ attribute \src "ls180.v:6049.107-6049.152"
+ cell $eq $eq$ls180.v:6049$1591
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface6_bank_bus_adr [5:0]
connect \B 5'10101
- connect \Y $eq$ls180.v:6053$1591_Y
+ connect \Y $eq$ls180.v:6049$1591_Y
end
- attribute \src "ls180.v:6055.104-6055.149"
- cell $eq $eq$ls180.v:6055$1594
+ attribute \src "ls180.v:6051.104-6051.149"
+ cell $eq $eq$ls180.v:6051$1594
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface6_bank_bus_adr [5:0]
connect \B 5'10110
- connect \Y $eq$ls180.v:6055$1594_Y
+ connect \Y $eq$ls180.v:6051$1594_Y
end
- attribute \src "ls180.v:6056.107-6056.152"
- cell $eq $eq$ls180.v:6056$1598
+ attribute \src "ls180.v:6052.107-6052.152"
+ cell $eq $eq$ls180.v:6052$1598
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface6_bank_bus_adr [5:0]
connect \B 5'10110
- connect \Y $eq$ls180.v:6056$1598_Y
+ connect \Y $eq$ls180.v:6052$1598_Y
end
- attribute \src "ls180.v:6058.104-6058.149"
- cell $eq $eq$ls180.v:6058$1601
+ attribute \src "ls180.v:6054.104-6054.149"
+ cell $eq $eq$ls180.v:6054$1601
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface6_bank_bus_adr [5:0]
connect \B 5'10111
- connect \Y $eq$ls180.v:6058$1601_Y
+ connect \Y $eq$ls180.v:6054$1601_Y
end
- attribute \src "ls180.v:6059.107-6059.152"
- cell $eq $eq$ls180.v:6059$1605
+ attribute \src "ls180.v:6055.107-6055.152"
+ cell $eq $eq$ls180.v:6055$1605
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface6_bank_bus_adr [5:0]
connect \B 5'10111
- connect \Y $eq$ls180.v:6059$1605_Y
+ connect \Y $eq$ls180.v:6055$1605_Y
end
- attribute \src "ls180.v:6061.104-6061.149"
- cell $eq $eq$ls180.v:6061$1608
+ attribute \src "ls180.v:6057.104-6057.149"
+ cell $eq $eq$ls180.v:6057$1608
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface6_bank_bus_adr [5:0]
connect \B 5'11000
- connect \Y $eq$ls180.v:6061$1608_Y
+ connect \Y $eq$ls180.v:6057$1608_Y
end
- attribute \src "ls180.v:6062.107-6062.152"
- cell $eq $eq$ls180.v:6062$1612
+ attribute \src "ls180.v:6058.107-6058.152"
+ cell $eq $eq$ls180.v:6058$1612
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface6_bank_bus_adr [5:0]
connect \B 5'11000
- connect \Y $eq$ls180.v:6062$1612_Y
+ connect \Y $eq$ls180.v:6058$1612_Y
end
- attribute \src "ls180.v:6064.100-6064.145"
- cell $eq $eq$ls180.v:6064$1615
+ attribute \src "ls180.v:6060.100-6060.145"
+ cell $eq $eq$ls180.v:6060$1615
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface6_bank_bus_adr [5:0]
connect \B 5'11001
- connect \Y $eq$ls180.v:6064$1615_Y
+ connect \Y $eq$ls180.v:6060$1615_Y
end
- attribute \src "ls180.v:6065.103-6065.148"
- cell $eq $eq$ls180.v:6065$1619
+ attribute \src "ls180.v:6061.103-6061.148"
+ cell $eq $eq$ls180.v:6061$1619
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface6_bank_bus_adr [5:0]
connect \B 5'11001
- connect \Y $eq$ls180.v:6065$1619_Y
+ connect \Y $eq$ls180.v:6061$1619_Y
end
- attribute \src "ls180.v:6067.101-6067.146"
- cell $eq $eq$ls180.v:6067$1622
+ attribute \src "ls180.v:6063.101-6063.146"
+ cell $eq $eq$ls180.v:6063$1622
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface6_bank_bus_adr [5:0]
connect \B 5'11010
- connect \Y $eq$ls180.v:6067$1622_Y
+ connect \Y $eq$ls180.v:6063$1622_Y
end
- attribute \src "ls180.v:6068.104-6068.149"
- cell $eq $eq$ls180.v:6068$1626
+ attribute \src "ls180.v:6064.104-6064.149"
+ cell $eq $eq$ls180.v:6064$1626
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface6_bank_bus_adr [5:0]
connect \B 5'11010
- connect \Y $eq$ls180.v:6068$1626_Y
+ connect \Y $eq$ls180.v:6064$1626_Y
end
- attribute \src "ls180.v:6070.104-6070.149"
- cell $eq $eq$ls180.v:6070$1629
+ attribute \src "ls180.v:6066.104-6066.149"
+ cell $eq $eq$ls180.v:6066$1629
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface6_bank_bus_adr [5:0]
connect \B 5'11011
- connect \Y $eq$ls180.v:6070$1629_Y
+ connect \Y $eq$ls180.v:6066$1629_Y
end
- attribute \src "ls180.v:6071.107-6071.152"
- cell $eq $eq$ls180.v:6071$1633
+ attribute \src "ls180.v:6067.107-6067.152"
+ cell $eq $eq$ls180.v:6067$1633
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface6_bank_bus_adr [5:0]
connect \B 5'11011
- connect \Y $eq$ls180.v:6071$1633_Y
+ connect \Y $eq$ls180.v:6067$1633_Y
end
- attribute \src "ls180.v:6073.104-6073.149"
- cell $eq $eq$ls180.v:6073$1636
+ attribute \src "ls180.v:6069.104-6069.149"
+ cell $eq $eq$ls180.v:6069$1636
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface6_bank_bus_adr [5:0]
connect \B 5'11100
- connect \Y $eq$ls180.v:6073$1636_Y
+ connect \Y $eq$ls180.v:6069$1636_Y
end
- attribute \src "ls180.v:6074.107-6074.152"
- cell $eq $eq$ls180.v:6074$1640
+ attribute \src "ls180.v:6070.107-6070.152"
+ cell $eq $eq$ls180.v:6070$1640
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface6_bank_bus_adr [5:0]
connect \B 5'11100
- connect \Y $eq$ls180.v:6074$1640_Y
+ connect \Y $eq$ls180.v:6070$1640_Y
end
- attribute \src "ls180.v:6076.103-6076.148"
- cell $eq $eq$ls180.v:6076$1643
+ attribute \src "ls180.v:6072.103-6072.148"
+ cell $eq $eq$ls180.v:6072$1643
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface6_bank_bus_adr [5:0]
connect \B 5'11101
- connect \Y $eq$ls180.v:6076$1643_Y
+ connect \Y $eq$ls180.v:6072$1643_Y
end
- attribute \src "ls180.v:6077.106-6077.151"
- cell $eq $eq$ls180.v:6077$1647
+ attribute \src "ls180.v:6073.106-6073.151"
+ cell $eq $eq$ls180.v:6073$1647
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface6_bank_bus_adr [5:0]
connect \B 5'11101
- connect \Y $eq$ls180.v:6077$1647_Y
+ connect \Y $eq$ls180.v:6073$1647_Y
end
- attribute \src "ls180.v:6079.103-6079.148"
- cell $eq $eq$ls180.v:6079$1650
+ attribute \src "ls180.v:6075.103-6075.148"
+ cell $eq $eq$ls180.v:6075$1650
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface6_bank_bus_adr [5:0]
connect \B 5'11110
- connect \Y $eq$ls180.v:6079$1650_Y
+ connect \Y $eq$ls180.v:6075$1650_Y
end
- attribute \src "ls180.v:6080.106-6080.151"
- cell $eq $eq$ls180.v:6080$1654
+ attribute \src "ls180.v:6076.106-6076.151"
+ cell $eq $eq$ls180.v:6076$1654
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface6_bank_bus_adr [5:0]
connect \B 5'11110
- connect \Y $eq$ls180.v:6080$1654_Y
+ connect \Y $eq$ls180.v:6076$1654_Y
end
- attribute \src "ls180.v:6082.103-6082.148"
- cell $eq $eq$ls180.v:6082$1657
+ attribute \src "ls180.v:6078.103-6078.148"
+ cell $eq $eq$ls180.v:6078$1657
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface6_bank_bus_adr [5:0]
connect \B 5'11111
- connect \Y $eq$ls180.v:6082$1657_Y
+ connect \Y $eq$ls180.v:6078$1657_Y
end
- attribute \src "ls180.v:6083.106-6083.151"
- cell $eq $eq$ls180.v:6083$1661
+ attribute \src "ls180.v:6079.106-6079.151"
+ cell $eq $eq$ls180.v:6079$1661
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface6_bank_bus_adr [5:0]
connect \B 5'11111
- connect \Y $eq$ls180.v:6083$1661_Y
+ connect \Y $eq$ls180.v:6079$1661_Y
end
- attribute \src "ls180.v:6085.103-6085.148"
- cell $eq $eq$ls180.v:6085$1664
+ attribute \src "ls180.v:6081.103-6081.148"
+ cell $eq $eq$ls180.v:6081$1664
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface6_bank_bus_adr [5:0]
connect \B 6'100000
- connect \Y $eq$ls180.v:6085$1664_Y
+ connect \Y $eq$ls180.v:6081$1664_Y
end
- attribute \src "ls180.v:6086.106-6086.151"
- cell $eq $eq$ls180.v:6086$1668
+ attribute \src "ls180.v:6082.106-6082.151"
+ cell $eq $eq$ls180.v:6082$1668
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface6_bank_bus_adr [5:0]
connect \B 6'100000
- connect \Y $eq$ls180.v:6086$1668_Y
+ connect \Y $eq$ls180.v:6082$1668_Y
end
- attribute \src "ls180.v:6122.32-6122.78"
- cell $eq $eq$ls180.v:6122$1670
+ attribute \src "ls180.v:6118.32-6118.78"
+ cell $eq $eq$ls180.v:6118$1670
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface7_bank_bus_adr [13:9]
connect \B 4'1111
- connect \Y $eq$ls180.v:6122$1670_Y
+ connect \Y $eq$ls180.v:6118$1670_Y
end
- attribute \src "ls180.v:6124.100-6124.144"
- cell $eq $eq$ls180.v:6124$1672
+ attribute \src "ls180.v:6120.100-6120.144"
+ cell $eq $eq$ls180.v:6120$1672
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface7_bank_bus_adr [4:0]
connect \B 1'0
- connect \Y $eq$ls180.v:6124$1672_Y
+ connect \Y $eq$ls180.v:6120$1672_Y
end
- attribute \src "ls180.v:6125.103-6125.147"
- cell $eq $eq$ls180.v:6125$1676
+ attribute \src "ls180.v:6121.103-6121.147"
+ cell $eq $eq$ls180.v:6121$1676
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface7_bank_bus_adr [4:0]
connect \B 1'0
- connect \Y $eq$ls180.v:6125$1676_Y
+ connect \Y $eq$ls180.v:6121$1676_Y
end
- attribute \src "ls180.v:6127.100-6127.144"
- cell $eq $eq$ls180.v:6127$1679
+ attribute \src "ls180.v:6123.100-6123.144"
+ cell $eq $eq$ls180.v:6123$1679
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface7_bank_bus_adr [4:0]
connect \B 1'1
- connect \Y $eq$ls180.v:6127$1679_Y
+ connect \Y $eq$ls180.v:6123$1679_Y
end
- attribute \src "ls180.v:6128.103-6128.147"
- cell $eq $eq$ls180.v:6128$1683
+ attribute \src "ls180.v:6124.103-6124.147"
+ cell $eq $eq$ls180.v:6124$1683
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface7_bank_bus_adr [4:0]
connect \B 1'1
- connect \Y $eq$ls180.v:6128$1683_Y
+ connect \Y $eq$ls180.v:6124$1683_Y
end
- attribute \src "ls180.v:6130.100-6130.144"
- cell $eq $eq$ls180.v:6130$1686
+ attribute \src "ls180.v:6126.100-6126.144"
+ cell $eq $eq$ls180.v:6126$1686
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface7_bank_bus_adr [4:0]
connect \B 2'10
- connect \Y $eq$ls180.v:6130$1686_Y
+ connect \Y $eq$ls180.v:6126$1686_Y
end
- attribute \src "ls180.v:6131.103-6131.147"
- cell $eq $eq$ls180.v:6131$1690
+ attribute \src "ls180.v:6127.103-6127.147"
+ cell $eq $eq$ls180.v:6127$1690
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface7_bank_bus_adr [4:0]
connect \B 2'10
- connect \Y $eq$ls180.v:6131$1690_Y
+ connect \Y $eq$ls180.v:6127$1690_Y
end
- attribute \src "ls180.v:6133.100-6133.144"
- cell $eq $eq$ls180.v:6133$1693
+ attribute \src "ls180.v:6129.100-6129.144"
+ cell $eq $eq$ls180.v:6129$1693
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface7_bank_bus_adr [4:0]
connect \B 2'11
- connect \Y $eq$ls180.v:6133$1693_Y
+ connect \Y $eq$ls180.v:6129$1693_Y
end
- attribute \src "ls180.v:6134.103-6134.147"
- cell $eq $eq$ls180.v:6134$1697
+ attribute \src "ls180.v:6130.103-6130.147"
+ cell $eq $eq$ls180.v:6130$1697
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface7_bank_bus_adr [4:0]
connect \B 2'11
- connect \Y $eq$ls180.v:6134$1697_Y
+ connect \Y $eq$ls180.v:6130$1697_Y
end
- attribute \src "ls180.v:6136.100-6136.144"
- cell $eq $eq$ls180.v:6136$1700
+ attribute \src "ls180.v:6132.100-6132.144"
+ cell $eq $eq$ls180.v:6132$1700
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface7_bank_bus_adr [4:0]
connect \B 3'100
- connect \Y $eq$ls180.v:6136$1700_Y
+ connect \Y $eq$ls180.v:6132$1700_Y
end
- attribute \src "ls180.v:6137.103-6137.147"
- cell $eq $eq$ls180.v:6137$1704
+ attribute \src "ls180.v:6133.103-6133.147"
+ cell $eq $eq$ls180.v:6133$1704
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface7_bank_bus_adr [4:0]
connect \B 3'100
- connect \Y $eq$ls180.v:6137$1704_Y
+ connect \Y $eq$ls180.v:6133$1704_Y
end
- attribute \src "ls180.v:6139.100-6139.144"
- cell $eq $eq$ls180.v:6139$1707
+ attribute \src "ls180.v:6135.100-6135.144"
+ cell $eq $eq$ls180.v:6135$1707
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface7_bank_bus_adr [4:0]
connect \B 3'101
- connect \Y $eq$ls180.v:6139$1707_Y
+ connect \Y $eq$ls180.v:6135$1707_Y
end
- attribute \src "ls180.v:6140.103-6140.147"
- cell $eq $eq$ls180.v:6140$1711
+ attribute \src "ls180.v:6136.103-6136.147"
+ cell $eq $eq$ls180.v:6136$1711
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface7_bank_bus_adr [4:0]
connect \B 3'101
- connect \Y $eq$ls180.v:6140$1711_Y
+ connect \Y $eq$ls180.v:6136$1711_Y
end
- attribute \src "ls180.v:6142.100-6142.144"
- cell $eq $eq$ls180.v:6142$1714
+ attribute \src "ls180.v:6138.100-6138.144"
+ cell $eq $eq$ls180.v:6138$1714
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface7_bank_bus_adr [4:0]
connect \B 3'110
- connect \Y $eq$ls180.v:6142$1714_Y
+ connect \Y $eq$ls180.v:6138$1714_Y
end
- attribute \src "ls180.v:6143.103-6143.147"
- cell $eq $eq$ls180.v:6143$1718
+ attribute \src "ls180.v:6139.103-6139.147"
+ cell $eq $eq$ls180.v:6139$1718
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface7_bank_bus_adr [4:0]
connect \B 3'110
- connect \Y $eq$ls180.v:6143$1718_Y
+ connect \Y $eq$ls180.v:6139$1718_Y
end
- attribute \src "ls180.v:6145.100-6145.144"
- cell $eq $eq$ls180.v:6145$1721
+ attribute \src "ls180.v:6141.100-6141.144"
+ cell $eq $eq$ls180.v:6141$1721
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface7_bank_bus_adr [4:0]
connect \B 3'111
- connect \Y $eq$ls180.v:6145$1721_Y
+ connect \Y $eq$ls180.v:6141$1721_Y
end
- attribute \src "ls180.v:6146.103-6146.147"
- cell $eq $eq$ls180.v:6146$1725
+ attribute \src "ls180.v:6142.103-6142.147"
+ cell $eq $eq$ls180.v:6142$1725
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface7_bank_bus_adr [4:0]
connect \B 3'111
- connect \Y $eq$ls180.v:6146$1725_Y
+ connect \Y $eq$ls180.v:6142$1725_Y
end
- attribute \src "ls180.v:6148.102-6148.146"
- cell $eq $eq$ls180.v:6148$1728
+ attribute \src "ls180.v:6144.102-6144.146"
+ cell $eq $eq$ls180.v:6144$1728
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface7_bank_bus_adr [4:0]
connect \B 4'1000
- connect \Y $eq$ls180.v:6148$1728_Y
+ connect \Y $eq$ls180.v:6144$1728_Y
end
- attribute \src "ls180.v:6149.105-6149.149"
- cell $eq $eq$ls180.v:6149$1732
+ attribute \src "ls180.v:6145.105-6145.149"
+ cell $eq $eq$ls180.v:6145$1732
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface7_bank_bus_adr [4:0]
connect \B 4'1000
- connect \Y $eq$ls180.v:6149$1732_Y
+ connect \Y $eq$ls180.v:6145$1732_Y
end
- attribute \src "ls180.v:6151.102-6151.146"
- cell $eq $eq$ls180.v:6151$1735
+ attribute \src "ls180.v:6147.102-6147.146"
+ cell $eq $eq$ls180.v:6147$1735
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface7_bank_bus_adr [4:0]
connect \B 4'1001
- connect \Y $eq$ls180.v:6151$1735_Y
+ connect \Y $eq$ls180.v:6147$1735_Y
end
- attribute \src "ls180.v:6152.105-6152.149"
- cell $eq $eq$ls180.v:6152$1739
+ attribute \src "ls180.v:6148.105-6148.149"
+ cell $eq $eq$ls180.v:6148$1739
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface7_bank_bus_adr [4:0]
connect \B 4'1001
- connect \Y $eq$ls180.v:6152$1739_Y
+ connect \Y $eq$ls180.v:6148$1739_Y
end
- attribute \src "ls180.v:6154.102-6154.147"
- cell $eq $eq$ls180.v:6154$1742
+ attribute \src "ls180.v:6150.102-6150.147"
+ cell $eq $eq$ls180.v:6150$1742
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface7_bank_bus_adr [4:0]
connect \B 4'1010
- connect \Y $eq$ls180.v:6154$1742_Y
+ connect \Y $eq$ls180.v:6150$1742_Y
end
- attribute \src "ls180.v:6155.105-6155.150"
- cell $eq $eq$ls180.v:6155$1746
+ attribute \src "ls180.v:6151.105-6151.150"
+ cell $eq $eq$ls180.v:6151$1746
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface7_bank_bus_adr [4:0]
connect \B 4'1010
- connect \Y $eq$ls180.v:6155$1746_Y
+ connect \Y $eq$ls180.v:6151$1746_Y
end
- attribute \src "ls180.v:6157.102-6157.147"
- cell $eq $eq$ls180.v:6157$1749
+ attribute \src "ls180.v:6153.102-6153.147"
+ cell $eq $eq$ls180.v:6153$1749
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface7_bank_bus_adr [4:0]
connect \B 4'1011
- connect \Y $eq$ls180.v:6157$1749_Y
+ connect \Y $eq$ls180.v:6153$1749_Y
end
- attribute \src "ls180.v:6158.105-6158.150"
- cell $eq $eq$ls180.v:6158$1753
+ attribute \src "ls180.v:6154.105-6154.150"
+ cell $eq $eq$ls180.v:6154$1753
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface7_bank_bus_adr [4:0]
connect \B 4'1011
- connect \Y $eq$ls180.v:6158$1753_Y
+ connect \Y $eq$ls180.v:6154$1753_Y
end
- attribute \src "ls180.v:6160.102-6160.147"
- cell $eq $eq$ls180.v:6160$1756
+ attribute \src "ls180.v:6156.102-6156.147"
+ cell $eq $eq$ls180.v:6156$1756
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface7_bank_bus_adr [4:0]
connect \B 4'1100
- connect \Y $eq$ls180.v:6160$1756_Y
+ connect \Y $eq$ls180.v:6156$1756_Y
end
- attribute \src "ls180.v:6161.105-6161.150"
- cell $eq $eq$ls180.v:6161$1760
+ attribute \src "ls180.v:6157.105-6157.150"
+ cell $eq $eq$ls180.v:6157$1760
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface7_bank_bus_adr [4:0]
connect \B 4'1100
- connect \Y $eq$ls180.v:6161$1760_Y
+ connect \Y $eq$ls180.v:6157$1760_Y
end
- attribute \src "ls180.v:6163.99-6163.144"
- cell $eq $eq$ls180.v:6163$1763
+ attribute \src "ls180.v:6159.99-6159.144"
+ cell $eq $eq$ls180.v:6159$1763
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface7_bank_bus_adr [4:0]
connect \B 4'1101
- connect \Y $eq$ls180.v:6163$1763_Y
+ connect \Y $eq$ls180.v:6159$1763_Y
end
- attribute \src "ls180.v:6164.102-6164.147"
- cell $eq $eq$ls180.v:6164$1767
+ attribute \src "ls180.v:6160.102-6160.147"
+ cell $eq $eq$ls180.v:6160$1767
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface7_bank_bus_adr [4:0]
connect \B 4'1101
- connect \Y $eq$ls180.v:6164$1767_Y
+ connect \Y $eq$ls180.v:6160$1767_Y
end
- attribute \src "ls180.v:6166.100-6166.145"
- cell $eq $eq$ls180.v:6166$1770
+ attribute \src "ls180.v:6162.100-6162.145"
+ cell $eq $eq$ls180.v:6162$1770
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface7_bank_bus_adr [4:0]
connect \B 4'1110
- connect \Y $eq$ls180.v:6166$1770_Y
+ connect \Y $eq$ls180.v:6162$1770_Y
end
- attribute \src "ls180.v:6167.103-6167.148"
- cell $eq $eq$ls180.v:6167$1774
+ attribute \src "ls180.v:6163.103-6163.148"
+ cell $eq $eq$ls180.v:6163$1774
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface7_bank_bus_adr [4:0]
connect \B 4'1110
- connect \Y $eq$ls180.v:6167$1774_Y
+ connect \Y $eq$ls180.v:6163$1774_Y
end
- attribute \src "ls180.v:6169.102-6169.147"
- cell $eq $eq$ls180.v:6169$1777
+ attribute \src "ls180.v:6165.102-6165.147"
+ cell $eq $eq$ls180.v:6165$1777
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface7_bank_bus_adr [4:0]
connect \B 4'1111
- connect \Y $eq$ls180.v:6169$1777_Y
+ connect \Y $eq$ls180.v:6165$1777_Y
end
- attribute \src "ls180.v:6170.105-6170.150"
- cell $eq $eq$ls180.v:6170$1781
+ attribute \src "ls180.v:6166.105-6166.150"
+ cell $eq $eq$ls180.v:6166$1781
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface7_bank_bus_adr [4:0]
connect \B 4'1111
- connect \Y $eq$ls180.v:6170$1781_Y
+ connect \Y $eq$ls180.v:6166$1781_Y
end
- attribute \src "ls180.v:6172.102-6172.147"
- cell $eq $eq$ls180.v:6172$1784
+ attribute \src "ls180.v:6168.102-6168.147"
+ cell $eq $eq$ls180.v:6168$1784
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface7_bank_bus_adr [4:0]
connect \B 5'10000
- connect \Y $eq$ls180.v:6172$1784_Y
+ connect \Y $eq$ls180.v:6168$1784_Y
end
- attribute \src "ls180.v:6173.105-6173.150"
- cell $eq $eq$ls180.v:6173$1788
+ attribute \src "ls180.v:6169.105-6169.150"
+ cell $eq $eq$ls180.v:6169$1788
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface7_bank_bus_adr [4:0]
connect \B 5'10000
- connect \Y $eq$ls180.v:6173$1788_Y
+ connect \Y $eq$ls180.v:6169$1788_Y
end
- attribute \src "ls180.v:6175.102-6175.147"
- cell $eq $eq$ls180.v:6175$1791
+ attribute \src "ls180.v:6171.102-6171.147"
+ cell $eq $eq$ls180.v:6171$1791
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface7_bank_bus_adr [4:0]
connect \B 5'10001
- connect \Y $eq$ls180.v:6175$1791_Y
+ connect \Y $eq$ls180.v:6171$1791_Y
end
- attribute \src "ls180.v:6176.105-6176.150"
- cell $eq $eq$ls180.v:6176$1795
+ attribute \src "ls180.v:6172.105-6172.150"
+ cell $eq $eq$ls180.v:6172$1795
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface7_bank_bus_adr [4:0]
connect \B 5'10001
- connect \Y $eq$ls180.v:6176$1795_Y
+ connect \Y $eq$ls180.v:6172$1795_Y
end
- attribute \src "ls180.v:6178.102-6178.147"
- cell $eq $eq$ls180.v:6178$1798
+ attribute \src "ls180.v:6174.102-6174.147"
+ cell $eq $eq$ls180.v:6174$1798
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface7_bank_bus_adr [4:0]
connect \B 5'10010
- connect \Y $eq$ls180.v:6178$1798_Y
+ connect \Y $eq$ls180.v:6174$1798_Y
end
- attribute \src "ls180.v:6179.105-6179.150"
- cell $eq $eq$ls180.v:6179$1802
+ attribute \src "ls180.v:6175.105-6175.150"
+ cell $eq $eq$ls180.v:6175$1802
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface7_bank_bus_adr [4:0]
connect \B 5'10010
- connect \Y $eq$ls180.v:6179$1802_Y
+ connect \Y $eq$ls180.v:6175$1802_Y
end
- attribute \src "ls180.v:6201.32-6201.78"
- cell $eq $eq$ls180.v:6201$1804
+ attribute \src "ls180.v:6197.32-6197.78"
+ cell $eq $eq$ls180.v:6197$1804
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface8_bank_bus_adr [13:9]
connect \B 4'1100
- connect \Y $eq$ls180.v:6201$1804_Y
+ connect \Y $eq$ls180.v:6197$1804_Y
end
- attribute \src "ls180.v:6203.102-6203.146"
- cell $eq $eq$ls180.v:6203$1806
+ attribute \src "ls180.v:6199.102-6199.146"
+ cell $eq $eq$ls180.v:6199$1806
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface8_bank_bus_adr [1:0]
connect \B 1'0
- connect \Y $eq$ls180.v:6203$1806_Y
+ connect \Y $eq$ls180.v:6199$1806_Y
end
- attribute \src "ls180.v:6204.105-6204.149"
- cell $eq $eq$ls180.v:6204$1810
+ attribute \src "ls180.v:6200.105-6200.149"
+ cell $eq $eq$ls180.v:6200$1810
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface8_bank_bus_adr [1:0]
connect \B 1'0
- connect \Y $eq$ls180.v:6204$1810_Y
+ connect \Y $eq$ls180.v:6200$1810_Y
end
- attribute \src "ls180.v:6206.107-6206.151"
- cell $eq $eq$ls180.v:6206$1813
+ attribute \src "ls180.v:6202.107-6202.151"
+ cell $eq $eq$ls180.v:6202$1813
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface8_bank_bus_adr [1:0]
connect \B 1'1
- connect \Y $eq$ls180.v:6206$1813_Y
+ connect \Y $eq$ls180.v:6202$1813_Y
end
- attribute \src "ls180.v:6207.110-6207.154"
- cell $eq $eq$ls180.v:6207$1817
+ attribute \src "ls180.v:6203.110-6203.154"
+ cell $eq $eq$ls180.v:6203$1817
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface8_bank_bus_adr [1:0]
connect \B 1'1
- connect \Y $eq$ls180.v:6207$1817_Y
+ connect \Y $eq$ls180.v:6203$1817_Y
end
- attribute \src "ls180.v:6209.107-6209.151"
- cell $eq $eq$ls180.v:6209$1820
+ attribute \src "ls180.v:6205.107-6205.151"
+ cell $eq $eq$ls180.v:6205$1820
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface8_bank_bus_adr [1:0]
connect \B 2'10
- connect \Y $eq$ls180.v:6209$1820_Y
+ connect \Y $eq$ls180.v:6205$1820_Y
end
- attribute \src "ls180.v:6210.110-6210.154"
- cell $eq $eq$ls180.v:6210$1824
+ attribute \src "ls180.v:6206.110-6206.154"
+ cell $eq $eq$ls180.v:6206$1824
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface8_bank_bus_adr [1:0]
connect \B 2'10
- connect \Y $eq$ls180.v:6210$1824_Y
+ connect \Y $eq$ls180.v:6206$1824_Y
end
- attribute \src "ls180.v:6212.100-6212.144"
- cell $eq $eq$ls180.v:6212$1827
+ attribute \src "ls180.v:6208.100-6208.144"
+ cell $eq $eq$ls180.v:6208$1827
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface8_bank_bus_adr [1:0]
connect \B 2'11
- connect \Y $eq$ls180.v:6212$1827_Y
+ connect \Y $eq$ls180.v:6208$1827_Y
end
- attribute \src "ls180.v:6213.103-6213.147"
- cell $eq $eq$ls180.v:6213$1831
+ attribute \src "ls180.v:6209.103-6209.147"
+ cell $eq $eq$ls180.v:6209$1831
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface8_bank_bus_adr [1:0]
connect \B 2'11
- connect \Y $eq$ls180.v:6213$1831_Y
+ connect \Y $eq$ls180.v:6209$1831_Y
end
- attribute \src "ls180.v:6218.32-6218.77"
- cell $eq $eq$ls180.v:6218$1833
+ attribute \src "ls180.v:6214.32-6214.77"
+ cell $eq $eq$ls180.v:6214$1833
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface9_bank_bus_adr [13:9]
connect \B 2'11
- connect \Y $eq$ls180.v:6218$1833_Y
+ connect \Y $eq$ls180.v:6214$1833_Y
end
- attribute \src "ls180.v:6220.104-6220.148"
- cell $eq $eq$ls180.v:6220$1835
+ attribute \src "ls180.v:6216.104-6216.148"
+ cell $eq $eq$ls180.v:6216$1835
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface9_bank_bus_adr [3:0]
connect \B 1'0
- connect \Y $eq$ls180.v:6220$1835_Y
+ connect \Y $eq$ls180.v:6216$1835_Y
end
- attribute \src "ls180.v:6221.107-6221.151"
- cell $eq $eq$ls180.v:6221$1839
+ attribute \src "ls180.v:6217.107-6217.151"
+ cell $eq $eq$ls180.v:6217$1839
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface9_bank_bus_adr [3:0]
connect \B 1'0
- connect \Y $eq$ls180.v:6221$1839_Y
+ connect \Y $eq$ls180.v:6217$1839_Y
end
- attribute \src "ls180.v:6223.108-6223.152"
- cell $eq $eq$ls180.v:6223$1842
+ attribute \src "ls180.v:6219.108-6219.152"
+ cell $eq $eq$ls180.v:6219$1842
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface9_bank_bus_adr [3:0]
connect \B 1'1
- connect \Y $eq$ls180.v:6223$1842_Y
+ connect \Y $eq$ls180.v:6219$1842_Y
end
- attribute \src "ls180.v:6224.111-6224.155"
- cell $eq $eq$ls180.v:6224$1846
+ attribute \src "ls180.v:6220.111-6220.155"
+ cell $eq $eq$ls180.v:6220$1846
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface9_bank_bus_adr [3:0]
connect \B 1'1
- connect \Y $eq$ls180.v:6224$1846_Y
+ connect \Y $eq$ls180.v:6220$1846_Y
end
- attribute \src "ls180.v:6226.98-6226.142"
- cell $eq $eq$ls180.v:6226$1849
+ attribute \src "ls180.v:6222.98-6222.142"
+ cell $eq $eq$ls180.v:6222$1849
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface9_bank_bus_adr [3:0]
connect \B 2'10
- connect \Y $eq$ls180.v:6226$1849_Y
+ connect \Y $eq$ls180.v:6222$1849_Y
end
- attribute \src "ls180.v:6227.101-6227.145"
- cell $eq $eq$ls180.v:6227$1853
+ attribute \src "ls180.v:6223.101-6223.145"
+ cell $eq $eq$ls180.v:6223$1853
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface9_bank_bus_adr [3:0]
connect \B 2'10
- connect \Y $eq$ls180.v:6227$1853_Y
+ connect \Y $eq$ls180.v:6223$1853_Y
end
- attribute \src "ls180.v:6229.108-6229.152"
- cell $eq $eq$ls180.v:6229$1856
+ attribute \src "ls180.v:6225.108-6225.152"
+ cell $eq $eq$ls180.v:6225$1856
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface9_bank_bus_adr [3:0]
connect \B 2'11
- connect \Y $eq$ls180.v:6229$1856_Y
+ connect \Y $eq$ls180.v:6225$1856_Y
end
- attribute \src "ls180.v:6230.111-6230.155"
- cell $eq $eq$ls180.v:6230$1860
+ attribute \src "ls180.v:6226.111-6226.155"
+ cell $eq $eq$ls180.v:6226$1860
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface9_bank_bus_adr [3:0]
connect \B 2'11
- connect \Y $eq$ls180.v:6230$1860_Y
+ connect \Y $eq$ls180.v:6226$1860_Y
end
- attribute \src "ls180.v:6232.108-6232.152"
- cell $eq $eq$ls180.v:6232$1863
+ attribute \src "ls180.v:6228.108-6228.152"
+ cell $eq $eq$ls180.v:6228$1863
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface9_bank_bus_adr [3:0]
connect \B 3'100
- connect \Y $eq$ls180.v:6232$1863_Y
+ connect \Y $eq$ls180.v:6228$1863_Y
end
- attribute \src "ls180.v:6233.111-6233.155"
- cell $eq $eq$ls180.v:6233$1867
+ attribute \src "ls180.v:6229.111-6229.155"
+ cell $eq $eq$ls180.v:6229$1867
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface9_bank_bus_adr [3:0]
connect \B 3'100
- connect \Y $eq$ls180.v:6233$1867_Y
+ connect \Y $eq$ls180.v:6229$1867_Y
end
- attribute \src "ls180.v:6235.109-6235.153"
- cell $eq $eq$ls180.v:6235$1870
+ attribute \src "ls180.v:6231.109-6231.153"
+ cell $eq $eq$ls180.v:6231$1870
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface9_bank_bus_adr [3:0]
connect \B 3'101
- connect \Y $eq$ls180.v:6235$1870_Y
+ connect \Y $eq$ls180.v:6231$1870_Y
end
- attribute \src "ls180.v:6236.112-6236.156"
- cell $eq $eq$ls180.v:6236$1874
+ attribute \src "ls180.v:6232.112-6232.156"
+ cell $eq $eq$ls180.v:6232$1874
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface9_bank_bus_adr [3:0]
connect \B 3'101
- connect \Y $eq$ls180.v:6236$1874_Y
+ connect \Y $eq$ls180.v:6232$1874_Y
end
- attribute \src "ls180.v:6238.107-6238.151"
- cell $eq $eq$ls180.v:6238$1877
+ attribute \src "ls180.v:6234.107-6234.151"
+ cell $eq $eq$ls180.v:6234$1877
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface9_bank_bus_adr [3:0]
connect \B 3'110
- connect \Y $eq$ls180.v:6238$1877_Y
+ connect \Y $eq$ls180.v:6234$1877_Y
end
- attribute \src "ls180.v:6239.110-6239.154"
- cell $eq $eq$ls180.v:6239$1881
+ attribute \src "ls180.v:6235.110-6235.154"
+ cell $eq $eq$ls180.v:6235$1881
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface9_bank_bus_adr [3:0]
connect \B 3'110
- connect \Y $eq$ls180.v:6239$1881_Y
+ connect \Y $eq$ls180.v:6235$1881_Y
end
- attribute \src "ls180.v:6241.107-6241.151"
- cell $eq $eq$ls180.v:6241$1884
+ attribute \src "ls180.v:6237.107-6237.151"
+ cell $eq $eq$ls180.v:6237$1884
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface9_bank_bus_adr [3:0]
connect \B 3'111
- connect \Y $eq$ls180.v:6241$1884_Y
+ connect \Y $eq$ls180.v:6237$1884_Y
end
- attribute \src "ls180.v:6242.110-6242.154"
- cell $eq $eq$ls180.v:6242$1888
+ attribute \src "ls180.v:6238.110-6238.154"
+ cell $eq $eq$ls180.v:6238$1888
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface9_bank_bus_adr [3:0]
connect \B 3'111
- connect \Y $eq$ls180.v:6242$1888_Y
+ connect \Y $eq$ls180.v:6238$1888_Y
end
- attribute \src "ls180.v:6244.107-6244.151"
- cell $eq $eq$ls180.v:6244$1891
+ attribute \src "ls180.v:6240.107-6240.151"
+ cell $eq $eq$ls180.v:6240$1891
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface9_bank_bus_adr [3:0]
connect \B 4'1000
- connect \Y $eq$ls180.v:6244$1891_Y
+ connect \Y $eq$ls180.v:6240$1891_Y
end
- attribute \src "ls180.v:6245.110-6245.154"
- cell $eq $eq$ls180.v:6245$1895
+ attribute \src "ls180.v:6241.110-6241.154"
+ cell $eq $eq$ls180.v:6241$1895
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface9_bank_bus_adr [3:0]
connect \B 4'1000
- connect \Y $eq$ls180.v:6245$1895_Y
+ connect \Y $eq$ls180.v:6241$1895_Y
end
- attribute \src "ls180.v:6247.107-6247.151"
- cell $eq $eq$ls180.v:6247$1898
+ attribute \src "ls180.v:6243.107-6243.151"
+ cell $eq $eq$ls180.v:6243$1898
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface9_bank_bus_adr [3:0]
connect \B 4'1001
- connect \Y $eq$ls180.v:6247$1898_Y
+ connect \Y $eq$ls180.v:6243$1898_Y
end
- attribute \src "ls180.v:6248.110-6248.154"
- cell $eq $eq$ls180.v:6248$1902
+ attribute \src "ls180.v:6244.110-6244.154"
+ cell $eq $eq$ls180.v:6244$1902
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface9_bank_bus_adr [3:0]
connect \B 4'1001
- connect \Y $eq$ls180.v:6248$1902_Y
+ connect \Y $eq$ls180.v:6244$1902_Y
end
- attribute \src "ls180.v:6263.33-6263.79"
- cell $eq $eq$ls180.v:6263$1904
+ attribute \src "ls180.v:6259.33-6259.79"
+ cell $eq $eq$ls180.v:6259$1904
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface10_bank_bus_adr [13:9]
connect \B 3'111
- connect \Y $eq$ls180.v:6263$1904_Y
+ connect \Y $eq$ls180.v:6259$1904_Y
end
- attribute \src "ls180.v:6265.102-6265.147"
- cell $eq $eq$ls180.v:6265$1906
+ attribute \src "ls180.v:6261.102-6261.147"
+ cell $eq $eq$ls180.v:6261$1906
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface10_bank_bus_adr [2:0]
connect \B 1'0
- connect \Y $eq$ls180.v:6265$1906_Y
+ connect \Y $eq$ls180.v:6261$1906_Y
end
- attribute \src "ls180.v:6266.105-6266.150"
- cell $eq $eq$ls180.v:6266$1910
+ attribute \src "ls180.v:6262.105-6262.150"
+ cell $eq $eq$ls180.v:6262$1910
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface10_bank_bus_adr [2:0]
connect \B 1'0
- connect \Y $eq$ls180.v:6266$1910_Y
+ connect \Y $eq$ls180.v:6262$1910_Y
end
- attribute \src "ls180.v:6268.102-6268.147"
- cell $eq $eq$ls180.v:6268$1913
+ attribute \src "ls180.v:6264.102-6264.147"
+ cell $eq $eq$ls180.v:6264$1913
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface10_bank_bus_adr [2:0]
connect \B 1'1
- connect \Y $eq$ls180.v:6268$1913_Y
+ connect \Y $eq$ls180.v:6264$1913_Y
end
- attribute \src "ls180.v:6269.105-6269.150"
- cell $eq $eq$ls180.v:6269$1917
+ attribute \src "ls180.v:6265.105-6265.150"
+ cell $eq $eq$ls180.v:6265$1917
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface10_bank_bus_adr [2:0]
connect \B 1'1
- connect \Y $eq$ls180.v:6269$1917_Y
+ connect \Y $eq$ls180.v:6265$1917_Y
end
- attribute \src "ls180.v:6271.100-6271.145"
- cell $eq $eq$ls180.v:6271$1920
+ attribute \src "ls180.v:6267.100-6267.145"
+ cell $eq $eq$ls180.v:6267$1920
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface10_bank_bus_adr [2:0]
connect \B 2'10
- connect \Y $eq$ls180.v:6271$1920_Y
+ connect \Y $eq$ls180.v:6267$1920_Y
end
- attribute \src "ls180.v:6272.103-6272.148"
- cell $eq $eq$ls180.v:6272$1924
+ attribute \src "ls180.v:6268.103-6268.148"
+ cell $eq $eq$ls180.v:6268$1924
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface10_bank_bus_adr [2:0]
connect \B 2'10
- connect \Y $eq$ls180.v:6272$1924_Y
+ connect \Y $eq$ls180.v:6268$1924_Y
end
- attribute \src "ls180.v:6274.99-6274.144"
- cell $eq $eq$ls180.v:6274$1927
+ attribute \src "ls180.v:6270.99-6270.144"
+ cell $eq $eq$ls180.v:6270$1927
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface10_bank_bus_adr [2:0]
connect \B 2'11
- connect \Y $eq$ls180.v:6274$1927_Y
+ connect \Y $eq$ls180.v:6270$1927_Y
end
- attribute \src "ls180.v:6275.102-6275.147"
- cell $eq $eq$ls180.v:6275$1931
+ attribute \src "ls180.v:6271.102-6271.147"
+ cell $eq $eq$ls180.v:6271$1931
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface10_bank_bus_adr [2:0]
connect \B 2'11
- connect \Y $eq$ls180.v:6275$1931_Y
+ connect \Y $eq$ls180.v:6271$1931_Y
end
- attribute \src "ls180.v:6277.98-6277.143"
- cell $eq $eq$ls180.v:6277$1934
+ attribute \src "ls180.v:6273.98-6273.143"
+ cell $eq $eq$ls180.v:6273$1934
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface10_bank_bus_adr [2:0]
connect \B 3'100
- connect \Y $eq$ls180.v:6277$1934_Y
+ connect \Y $eq$ls180.v:6273$1934_Y
end
- attribute \src "ls180.v:6278.101-6278.146"
- cell $eq $eq$ls180.v:6278$1938
+ attribute \src "ls180.v:6274.101-6274.146"
+ cell $eq $eq$ls180.v:6274$1938
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface10_bank_bus_adr [2:0]
connect \B 3'100
- connect \Y $eq$ls180.v:6278$1938_Y
+ connect \Y $eq$ls180.v:6274$1938_Y
end
- attribute \src "ls180.v:6280.97-6280.142"
- cell $eq $eq$ls180.v:6280$1941
+ attribute \src "ls180.v:6276.97-6276.142"
+ cell $eq $eq$ls180.v:6276$1941
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface10_bank_bus_adr [2:0]
connect \B 3'101
- connect \Y $eq$ls180.v:6280$1941_Y
+ connect \Y $eq$ls180.v:6276$1941_Y
end
- attribute \src "ls180.v:6281.100-6281.145"
- cell $eq $eq$ls180.v:6281$1945
+ attribute \src "ls180.v:6277.100-6277.145"
+ cell $eq $eq$ls180.v:6277$1945
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface10_bank_bus_adr [2:0]
connect \B 3'101
- connect \Y $eq$ls180.v:6281$1945_Y
+ connect \Y $eq$ls180.v:6277$1945_Y
end
- attribute \src "ls180.v:6283.103-6283.148"
- cell $eq $eq$ls180.v:6283$1948
+ attribute \src "ls180.v:6279.103-6279.148"
+ cell $eq $eq$ls180.v:6279$1948
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface10_bank_bus_adr [2:0]
connect \B 3'110
- connect \Y $eq$ls180.v:6283$1948_Y
+ connect \Y $eq$ls180.v:6279$1948_Y
end
- attribute \src "ls180.v:6284.106-6284.151"
- cell $eq $eq$ls180.v:6284$1952
+ attribute \src "ls180.v:6280.106-6280.151"
+ cell $eq $eq$ls180.v:6280$1952
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface10_bank_bus_adr [2:0]
connect \B 3'110
- connect \Y $eq$ls180.v:6284$1952_Y
+ connect \Y $eq$ls180.v:6280$1952_Y
end
- attribute \src "ls180.v:6303.33-6303.79"
- cell $eq $eq$ls180.v:6303$1955
+ attribute \src "ls180.v:6299.33-6299.79"
+ cell $eq $eq$ls180.v:6299$1955
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface11_bank_bus_adr [13:9]
connect \B 4'1000
- connect \Y $eq$ls180.v:6303$1955_Y
+ connect \Y $eq$ls180.v:6299$1955_Y
end
- attribute \src "ls180.v:6305.102-6305.147"
- cell $eq $eq$ls180.v:6305$1957
+ attribute \src "ls180.v:6301.102-6301.147"
+ cell $eq $eq$ls180.v:6301$1957
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface11_bank_bus_adr [3:0]
connect \B 1'0
- connect \Y $eq$ls180.v:6305$1957_Y
+ connect \Y $eq$ls180.v:6301$1957_Y
end
- attribute \src "ls180.v:6306.105-6306.150"
- cell $eq $eq$ls180.v:6306$1961
+ attribute \src "ls180.v:6302.105-6302.150"
+ cell $eq $eq$ls180.v:6302$1961
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface11_bank_bus_adr [3:0]
connect \B 1'0
- connect \Y $eq$ls180.v:6306$1961_Y
+ connect \Y $eq$ls180.v:6302$1961_Y
end
- attribute \src "ls180.v:6308.102-6308.147"
- cell $eq $eq$ls180.v:6308$1964
+ attribute \src "ls180.v:6304.102-6304.147"
+ cell $eq $eq$ls180.v:6304$1964
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface11_bank_bus_adr [3:0]
connect \B 1'1
- connect \Y $eq$ls180.v:6308$1964_Y
+ connect \Y $eq$ls180.v:6304$1964_Y
end
- attribute \src "ls180.v:6309.105-6309.150"
- cell $eq $eq$ls180.v:6309$1968
+ attribute \src "ls180.v:6305.105-6305.150"
+ cell $eq $eq$ls180.v:6305$1968
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface11_bank_bus_adr [3:0]
connect \B 1'1
- connect \Y $eq$ls180.v:6309$1968_Y
+ connect \Y $eq$ls180.v:6305$1968_Y
end
- attribute \src "ls180.v:6311.100-6311.145"
- cell $eq $eq$ls180.v:6311$1971
+ attribute \src "ls180.v:6307.100-6307.145"
+ cell $eq $eq$ls180.v:6307$1971
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface11_bank_bus_adr [3:0]
connect \B 2'10
- connect \Y $eq$ls180.v:6311$1971_Y
+ connect \Y $eq$ls180.v:6307$1971_Y
end
- attribute \src "ls180.v:6312.103-6312.148"
- cell $eq $eq$ls180.v:6312$1975
+ attribute \src "ls180.v:6308.103-6308.148"
+ cell $eq $eq$ls180.v:6308$1975
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface11_bank_bus_adr [3:0]
connect \B 2'10
- connect \Y $eq$ls180.v:6312$1975_Y
+ connect \Y $eq$ls180.v:6308$1975_Y
end
- attribute \src "ls180.v:6314.99-6314.144"
- cell $eq $eq$ls180.v:6314$1978
+ attribute \src "ls180.v:6310.99-6310.144"
+ cell $eq $eq$ls180.v:6310$1978
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface11_bank_bus_adr [3:0]
connect \B 2'11
- connect \Y $eq$ls180.v:6314$1978_Y
+ connect \Y $eq$ls180.v:6310$1978_Y
end
- attribute \src "ls180.v:6315.102-6315.147"
- cell $eq $eq$ls180.v:6315$1982
+ attribute \src "ls180.v:6311.102-6311.147"
+ cell $eq $eq$ls180.v:6311$1982
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface11_bank_bus_adr [3:0]
connect \B 2'11
- connect \Y $eq$ls180.v:6315$1982_Y
+ connect \Y $eq$ls180.v:6311$1982_Y
end
- attribute \src "ls180.v:6317.98-6317.143"
- cell $eq $eq$ls180.v:6317$1985
+ attribute \src "ls180.v:6313.98-6313.143"
+ cell $eq $eq$ls180.v:6313$1985
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface11_bank_bus_adr [3:0]
connect \B 3'100
- connect \Y $eq$ls180.v:6317$1985_Y
+ connect \Y $eq$ls180.v:6313$1985_Y
end
- attribute \src "ls180.v:6318.101-6318.146"
- cell $eq $eq$ls180.v:6318$1989
+ attribute \src "ls180.v:6314.101-6314.146"
+ cell $eq $eq$ls180.v:6314$1989
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface11_bank_bus_adr [3:0]
connect \B 3'100
- connect \Y $eq$ls180.v:6318$1989_Y
+ connect \Y $eq$ls180.v:6314$1989_Y
end
- attribute \src "ls180.v:6320.97-6320.142"
- cell $eq $eq$ls180.v:6320$1992
+ attribute \src "ls180.v:6316.97-6316.142"
+ cell $eq $eq$ls180.v:6316$1992
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface11_bank_bus_adr [3:0]
connect \B 3'101
- connect \Y $eq$ls180.v:6320$1992_Y
+ connect \Y $eq$ls180.v:6316$1992_Y
end
- attribute \src "ls180.v:6321.100-6321.145"
- cell $eq $eq$ls180.v:6321$1996
+ attribute \src "ls180.v:6317.100-6317.145"
+ cell $eq $eq$ls180.v:6317$1996
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface11_bank_bus_adr [3:0]
connect \B 3'101
- connect \Y $eq$ls180.v:6321$1996_Y
+ connect \Y $eq$ls180.v:6317$1996_Y
end
- attribute \src "ls180.v:6323.103-6323.148"
- cell $eq $eq$ls180.v:6323$1999
+ attribute \src "ls180.v:6319.103-6319.148"
+ cell $eq $eq$ls180.v:6319$1999
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface11_bank_bus_adr [3:0]
connect \B 3'110
- connect \Y $eq$ls180.v:6323$1999_Y
+ connect \Y $eq$ls180.v:6319$1999_Y
end
- attribute \src "ls180.v:6324.106-6324.151"
- cell $eq $eq$ls180.v:6324$2003
+ attribute \src "ls180.v:6320.106-6320.151"
+ cell $eq $eq$ls180.v:6320$2003
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface11_bank_bus_adr [3:0]
connect \B 3'110
- connect \Y $eq$ls180.v:6324$2003_Y
+ connect \Y $eq$ls180.v:6320$2003_Y
end
- attribute \src "ls180.v:6326.106-6326.151"
- cell $eq $eq$ls180.v:6326$2006
+ attribute \src "ls180.v:6322.106-6322.151"
+ cell $eq $eq$ls180.v:6322$2006
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface11_bank_bus_adr [3:0]
connect \B 3'111
- connect \Y $eq$ls180.v:6326$2006_Y
+ connect \Y $eq$ls180.v:6322$2006_Y
end
- attribute \src "ls180.v:6327.109-6327.154"
- cell $eq $eq$ls180.v:6327$2010
+ attribute \src "ls180.v:6323.109-6323.154"
+ cell $eq $eq$ls180.v:6323$2010
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface11_bank_bus_adr [3:0]
connect \B 3'111
- connect \Y $eq$ls180.v:6327$2010_Y
+ connect \Y $eq$ls180.v:6323$2010_Y
end
- attribute \src "ls180.v:6329.106-6329.151"
- cell $eq $eq$ls180.v:6329$2013
+ attribute \src "ls180.v:6325.106-6325.151"
+ cell $eq $eq$ls180.v:6325$2013
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface11_bank_bus_adr [3:0]
connect \B 4'1000
- connect \Y $eq$ls180.v:6329$2013_Y
+ connect \Y $eq$ls180.v:6325$2013_Y
end
- attribute \src "ls180.v:6330.109-6330.154"
- cell $eq $eq$ls180.v:6330$2017
+ attribute \src "ls180.v:6326.109-6326.154"
+ cell $eq $eq$ls180.v:6326$2017
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface11_bank_bus_adr [3:0]
connect \B 4'1000
- connect \Y $eq$ls180.v:6330$2017_Y
+ connect \Y $eq$ls180.v:6326$2017_Y
end
- attribute \src "ls180.v:6351.33-6351.79"
- cell $eq $eq$ls180.v:6351$2020
+ attribute \src "ls180.v:6347.33-6347.79"
+ cell $eq $eq$ls180.v:6347$2020
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface12_bank_bus_adr [13:9]
connect \B 2'10
- connect \Y $eq$ls180.v:6351$2020_Y
+ connect \Y $eq$ls180.v:6347$2020_Y
end
- attribute \src "ls180.v:6353.99-6353.144"
- cell $eq $eq$ls180.v:6353$2022
+ attribute \src "ls180.v:6349.99-6349.144"
+ cell $eq $eq$ls180.v:6349$2022
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface12_bank_bus_adr [4:0]
connect \B 1'0
- connect \Y $eq$ls180.v:6353$2022_Y
+ connect \Y $eq$ls180.v:6349$2022_Y
end
- attribute \src "ls180.v:6354.102-6354.147"
- cell $eq $eq$ls180.v:6354$2026
+ attribute \src "ls180.v:6350.102-6350.147"
+ cell $eq $eq$ls180.v:6350$2026
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface12_bank_bus_adr [4:0]
connect \B 1'0
- connect \Y $eq$ls180.v:6354$2026_Y
+ connect \Y $eq$ls180.v:6350$2026_Y
end
- attribute \src "ls180.v:6356.99-6356.144"
- cell $eq $eq$ls180.v:6356$2029
+ attribute \src "ls180.v:6352.99-6352.144"
+ cell $eq $eq$ls180.v:6352$2029
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface12_bank_bus_adr [4:0]
connect \B 1'1
- connect \Y $eq$ls180.v:6356$2029_Y
+ connect \Y $eq$ls180.v:6352$2029_Y
end
- attribute \src "ls180.v:6357.102-6357.147"
- cell $eq $eq$ls180.v:6357$2033
+ attribute \src "ls180.v:6353.102-6353.147"
+ cell $eq $eq$ls180.v:6353$2033
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface12_bank_bus_adr [4:0]
connect \B 1'1
- connect \Y $eq$ls180.v:6357$2033_Y
+ connect \Y $eq$ls180.v:6353$2033_Y
end
- attribute \src "ls180.v:6359.99-6359.144"
- cell $eq $eq$ls180.v:6359$2036
+ attribute \src "ls180.v:6355.99-6355.144"
+ cell $eq $eq$ls180.v:6355$2036
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface12_bank_bus_adr [4:0]
connect \B 2'10
- connect \Y $eq$ls180.v:6359$2036_Y
+ connect \Y $eq$ls180.v:6355$2036_Y
end
- attribute \src "ls180.v:6360.102-6360.147"
- cell $eq $eq$ls180.v:6360$2040
+ attribute \src "ls180.v:6356.102-6356.147"
+ cell $eq $eq$ls180.v:6356$2040
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface12_bank_bus_adr [4:0]
connect \B 2'10
- connect \Y $eq$ls180.v:6360$2040_Y
+ connect \Y $eq$ls180.v:6356$2040_Y
end
- attribute \src "ls180.v:6362.99-6362.144"
- cell $eq $eq$ls180.v:6362$2043
+ attribute \src "ls180.v:6358.99-6358.144"
+ cell $eq $eq$ls180.v:6358$2043
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface12_bank_bus_adr [4:0]
connect \B 2'11
- connect \Y $eq$ls180.v:6362$2043_Y
+ connect \Y $eq$ls180.v:6358$2043_Y
end
- attribute \src "ls180.v:6363.102-6363.147"
- cell $eq $eq$ls180.v:6363$2047
+ attribute \src "ls180.v:6359.102-6359.147"
+ cell $eq $eq$ls180.v:6359$2047
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface12_bank_bus_adr [4:0]
connect \B 2'11
- connect \Y $eq$ls180.v:6363$2047_Y
+ connect \Y $eq$ls180.v:6359$2047_Y
end
- attribute \src "ls180.v:6365.101-6365.146"
- cell $eq $eq$ls180.v:6365$2050
+ attribute \src "ls180.v:6361.101-6361.146"
+ cell $eq $eq$ls180.v:6361$2050
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface12_bank_bus_adr [4:0]
connect \B 3'100
- connect \Y $eq$ls180.v:6365$2050_Y
+ connect \Y $eq$ls180.v:6361$2050_Y
end
- attribute \src "ls180.v:6366.104-6366.149"
- cell $eq $eq$ls180.v:6366$2054
+ attribute \src "ls180.v:6362.104-6362.149"
+ cell $eq $eq$ls180.v:6362$2054
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface12_bank_bus_adr [4:0]
connect \B 3'100
- connect \Y $eq$ls180.v:6366$2054_Y
+ connect \Y $eq$ls180.v:6362$2054_Y
end
- attribute \src "ls180.v:6368.101-6368.146"
- cell $eq $eq$ls180.v:6368$2057
+ attribute \src "ls180.v:6364.101-6364.146"
+ cell $eq $eq$ls180.v:6364$2057
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface12_bank_bus_adr [4:0]
connect \B 3'101
- connect \Y $eq$ls180.v:6368$2057_Y
+ connect \Y $eq$ls180.v:6364$2057_Y
end
- attribute \src "ls180.v:6369.104-6369.149"
- cell $eq $eq$ls180.v:6369$2061
+ attribute \src "ls180.v:6365.104-6365.149"
+ cell $eq $eq$ls180.v:6365$2061
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface12_bank_bus_adr [4:0]
connect \B 3'101
- connect \Y $eq$ls180.v:6369$2061_Y
+ connect \Y $eq$ls180.v:6365$2061_Y
end
- attribute \src "ls180.v:6371.101-6371.146"
- cell $eq $eq$ls180.v:6371$2064
+ attribute \src "ls180.v:6367.101-6367.146"
+ cell $eq $eq$ls180.v:6367$2064
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface12_bank_bus_adr [4:0]
connect \B 3'110
- connect \Y $eq$ls180.v:6371$2064_Y
+ connect \Y $eq$ls180.v:6367$2064_Y
end
- attribute \src "ls180.v:6372.104-6372.149"
- cell $eq $eq$ls180.v:6372$2068
+ attribute \src "ls180.v:6368.104-6368.149"
+ cell $eq $eq$ls180.v:6368$2068
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface12_bank_bus_adr [4:0]
connect \B 3'110
- connect \Y $eq$ls180.v:6372$2068_Y
+ connect \Y $eq$ls180.v:6368$2068_Y
end
- attribute \src "ls180.v:6374.101-6374.146"
- cell $eq $eq$ls180.v:6374$2071
+ attribute \src "ls180.v:6370.101-6370.146"
+ cell $eq $eq$ls180.v:6370$2071
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface12_bank_bus_adr [4:0]
connect \B 3'111
- connect \Y $eq$ls180.v:6374$2071_Y
+ connect \Y $eq$ls180.v:6370$2071_Y
end
- attribute \src "ls180.v:6375.104-6375.149"
- cell $eq $eq$ls180.v:6375$2075
+ attribute \src "ls180.v:6371.104-6371.149"
+ cell $eq $eq$ls180.v:6371$2075
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface12_bank_bus_adr [4:0]
connect \B 3'111
- connect \Y $eq$ls180.v:6375$2075_Y
+ connect \Y $eq$ls180.v:6371$2075_Y
end
- attribute \src "ls180.v:6377.97-6377.142"
- cell $eq $eq$ls180.v:6377$2078
+ attribute \src "ls180.v:6373.97-6373.142"
+ cell $eq $eq$ls180.v:6373$2078
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface12_bank_bus_adr [4:0]
connect \B 4'1000
- connect \Y $eq$ls180.v:6377$2078_Y
+ connect \Y $eq$ls180.v:6373$2078_Y
end
- attribute \src "ls180.v:6378.100-6378.145"
- cell $eq $eq$ls180.v:6378$2082
+ attribute \src "ls180.v:6374.100-6374.145"
+ cell $eq $eq$ls180.v:6374$2082
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface12_bank_bus_adr [4:0]
connect \B 4'1000
- connect \Y $eq$ls180.v:6378$2082_Y
+ connect \Y $eq$ls180.v:6374$2082_Y
end
- attribute \src "ls180.v:6380.107-6380.152"
- cell $eq $eq$ls180.v:6380$2085
+ attribute \src "ls180.v:6376.107-6376.152"
+ cell $eq $eq$ls180.v:6376$2085
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface12_bank_bus_adr [4:0]
connect \B 4'1001
- connect \Y $eq$ls180.v:6380$2085_Y
+ connect \Y $eq$ls180.v:6376$2085_Y
end
- attribute \src "ls180.v:6381.110-6381.155"
- cell $eq $eq$ls180.v:6381$2089
+ attribute \src "ls180.v:6377.110-6377.155"
+ cell $eq $eq$ls180.v:6377$2089
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface12_bank_bus_adr [4:0]
connect \B 4'1001
- connect \Y $eq$ls180.v:6381$2089_Y
+ connect \Y $eq$ls180.v:6377$2089_Y
end
- attribute \src "ls180.v:6383.100-6383.146"
- cell $eq $eq$ls180.v:6383$2092
+ attribute \src "ls180.v:6379.100-6379.146"
+ cell $eq $eq$ls180.v:6379$2092
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface12_bank_bus_adr [4:0]
connect \B 4'1010
- connect \Y $eq$ls180.v:6383$2092_Y
+ connect \Y $eq$ls180.v:6379$2092_Y
end
- attribute \src "ls180.v:6384.103-6384.149"
- cell $eq $eq$ls180.v:6384$2096
+ attribute \src "ls180.v:6380.103-6380.149"
+ cell $eq $eq$ls180.v:6380$2096
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface12_bank_bus_adr [4:0]
connect \B 4'1010
- connect \Y $eq$ls180.v:6384$2096_Y
+ connect \Y $eq$ls180.v:6380$2096_Y
end
- attribute \src "ls180.v:6386.100-6386.146"
- cell $eq $eq$ls180.v:6386$2099
+ attribute \src "ls180.v:6382.100-6382.146"
+ cell $eq $eq$ls180.v:6382$2099
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface12_bank_bus_adr [4:0]
connect \B 4'1011
- connect \Y $eq$ls180.v:6386$2099_Y
+ connect \Y $eq$ls180.v:6382$2099_Y
end
- attribute \src "ls180.v:6387.103-6387.149"
- cell $eq $eq$ls180.v:6387$2103
+ attribute \src "ls180.v:6383.103-6383.149"
+ cell $eq $eq$ls180.v:6383$2103
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface12_bank_bus_adr [4:0]
connect \B 4'1011
- connect \Y $eq$ls180.v:6387$2103_Y
+ connect \Y $eq$ls180.v:6383$2103_Y
end
- attribute \src "ls180.v:6389.100-6389.146"
- cell $eq $eq$ls180.v:6389$2106
+ attribute \src "ls180.v:6385.100-6385.146"
+ cell $eq $eq$ls180.v:6385$2106
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface12_bank_bus_adr [4:0]
connect \B 4'1100
- connect \Y $eq$ls180.v:6389$2106_Y
+ connect \Y $eq$ls180.v:6385$2106_Y
end
- attribute \src "ls180.v:6390.103-6390.149"
- cell $eq $eq$ls180.v:6390$2110
+ attribute \src "ls180.v:6386.103-6386.149"
+ cell $eq $eq$ls180.v:6386$2110
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface12_bank_bus_adr [4:0]
connect \B 4'1100
- connect \Y $eq$ls180.v:6390$2110_Y
+ connect \Y $eq$ls180.v:6386$2110_Y
end
- attribute \src "ls180.v:6392.100-6392.146"
- cell $eq $eq$ls180.v:6392$2113
+ attribute \src "ls180.v:6388.100-6388.146"
+ cell $eq $eq$ls180.v:6388$2113
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface12_bank_bus_adr [4:0]
connect \B 4'1101
- connect \Y $eq$ls180.v:6392$2113_Y
+ connect \Y $eq$ls180.v:6388$2113_Y
end
- attribute \src "ls180.v:6393.103-6393.149"
- cell $eq $eq$ls180.v:6393$2117
+ attribute \src "ls180.v:6389.103-6389.149"
+ cell $eq $eq$ls180.v:6389$2117
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface12_bank_bus_adr [4:0]
connect \B 4'1101
- connect \Y $eq$ls180.v:6393$2117_Y
+ connect \Y $eq$ls180.v:6389$2117_Y
end
- attribute \src "ls180.v:6395.112-6395.158"
- cell $eq $eq$ls180.v:6395$2120
+ attribute \src "ls180.v:6391.112-6391.158"
+ cell $eq $eq$ls180.v:6391$2120
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface12_bank_bus_adr [4:0]
connect \B 4'1110
- connect \Y $eq$ls180.v:6395$2120_Y
+ connect \Y $eq$ls180.v:6391$2120_Y
end
- attribute \src "ls180.v:6396.115-6396.161"
- cell $eq $eq$ls180.v:6396$2124
+ attribute \src "ls180.v:6392.115-6392.161"
+ cell $eq $eq$ls180.v:6392$2124
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface12_bank_bus_adr [4:0]
connect \B 4'1110
- connect \Y $eq$ls180.v:6396$2124_Y
+ connect \Y $eq$ls180.v:6392$2124_Y
end
- attribute \src "ls180.v:6398.113-6398.159"
- cell $eq $eq$ls180.v:6398$2127
+ attribute \src "ls180.v:6394.113-6394.159"
+ cell $eq $eq$ls180.v:6394$2127
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface12_bank_bus_adr [4:0]
connect \B 4'1111
- connect \Y $eq$ls180.v:6398$2127_Y
+ connect \Y $eq$ls180.v:6394$2127_Y
end
- attribute \src "ls180.v:6399.116-6399.162"
- cell $eq $eq$ls180.v:6399$2131
+ attribute \src "ls180.v:6395.116-6395.162"
+ cell $eq $eq$ls180.v:6395$2131
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface12_bank_bus_adr [4:0]
connect \B 4'1111
- connect \Y $eq$ls180.v:6399$2131_Y
+ connect \Y $eq$ls180.v:6395$2131_Y
end
- attribute \src "ls180.v:6401.104-6401.150"
- cell $eq $eq$ls180.v:6401$2134
+ attribute \src "ls180.v:6397.104-6397.150"
+ cell $eq $eq$ls180.v:6397$2134
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface12_bank_bus_adr [4:0]
connect \B 5'10000
- connect \Y $eq$ls180.v:6401$2134_Y
+ connect \Y $eq$ls180.v:6397$2134_Y
end
- attribute \src "ls180.v:6402.107-6402.153"
- cell $eq $eq$ls180.v:6402$2138
+ attribute \src "ls180.v:6398.107-6398.153"
+ cell $eq $eq$ls180.v:6398$2138
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface12_bank_bus_adr [4:0]
connect \B 5'10000
- connect \Y $eq$ls180.v:6402$2138_Y
+ connect \Y $eq$ls180.v:6398$2138_Y
end
- attribute \src "ls180.v:6419.33-6419.79"
- cell $eq $eq$ls180.v:6419$2140
+ attribute \src "ls180.v:6415.33-6415.79"
+ cell $eq $eq$ls180.v:6415$2140
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface13_bank_bus_adr [13:9]
connect \B 3'101
- connect \Y $eq$ls180.v:6419$2140_Y
+ connect \Y $eq$ls180.v:6415$2140_Y
end
- attribute \src "ls180.v:6421.90-6421.135"
- cell $eq $eq$ls180.v:6421$2142
+ attribute \src "ls180.v:6417.90-6417.135"
+ cell $eq $eq$ls180.v:6417$2142
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface13_bank_bus_adr [2:0]
connect \B 1'0
- connect \Y $eq$ls180.v:6421$2142_Y
+ connect \Y $eq$ls180.v:6417$2142_Y
end
- attribute \src "ls180.v:6422.93-6422.138"
- cell $eq $eq$ls180.v:6422$2146
+ attribute \src "ls180.v:6418.93-6418.138"
+ cell $eq $eq$ls180.v:6418$2146
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface13_bank_bus_adr [2:0]
connect \B 1'0
- connect \Y $eq$ls180.v:6422$2146_Y
+ connect \Y $eq$ls180.v:6418$2146_Y
end
- attribute \src "ls180.v:6424.100-6424.145"
- cell $eq $eq$ls180.v:6424$2149
+ attribute \src "ls180.v:6420.100-6420.145"
+ cell $eq $eq$ls180.v:6420$2149
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface13_bank_bus_adr [2:0]
connect \B 1'1
- connect \Y $eq$ls180.v:6424$2149_Y
+ connect \Y $eq$ls180.v:6420$2149_Y
end
- attribute \src "ls180.v:6425.103-6425.148"
- cell $eq $eq$ls180.v:6425$2153
+ attribute \src "ls180.v:6421.103-6421.148"
+ cell $eq $eq$ls180.v:6421$2153
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface13_bank_bus_adr [2:0]
connect \B 1'1
- connect \Y $eq$ls180.v:6425$2153_Y
+ connect \Y $eq$ls180.v:6421$2153_Y
end
- attribute \src "ls180.v:6427.101-6427.146"
- cell $eq $eq$ls180.v:6427$2156
+ attribute \src "ls180.v:6423.101-6423.146"
+ cell $eq $eq$ls180.v:6423$2156
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface13_bank_bus_adr [2:0]
connect \B 2'10
- connect \Y $eq$ls180.v:6427$2156_Y
+ connect \Y $eq$ls180.v:6423$2156_Y
end
- attribute \src "ls180.v:6428.104-6428.149"
- cell $eq $eq$ls180.v:6428$2160
+ attribute \src "ls180.v:6424.104-6424.149"
+ cell $eq $eq$ls180.v:6424$2160
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface13_bank_bus_adr [2:0]
connect \B 2'10
- connect \Y $eq$ls180.v:6428$2160_Y
+ connect \Y $eq$ls180.v:6424$2160_Y
end
- attribute \src "ls180.v:6430.105-6430.150"
- cell $eq $eq$ls180.v:6430$2163
+ attribute \src "ls180.v:6426.105-6426.150"
+ cell $eq $eq$ls180.v:6426$2163
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface13_bank_bus_adr [2:0]
connect \B 2'11
- connect \Y $eq$ls180.v:6430$2163_Y
+ connect \Y $eq$ls180.v:6426$2163_Y
end
- attribute \src "ls180.v:6431.108-6431.153"
- cell $eq $eq$ls180.v:6431$2167
+ attribute \src "ls180.v:6427.108-6427.153"
+ cell $eq $eq$ls180.v:6427$2167
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface13_bank_bus_adr [2:0]
connect \B 2'11
- connect \Y $eq$ls180.v:6431$2167_Y
+ connect \Y $eq$ls180.v:6427$2167_Y
end
- attribute \src "ls180.v:6433.106-6433.151"
- cell $eq $eq$ls180.v:6433$2170
+ attribute \src "ls180.v:6429.106-6429.151"
+ cell $eq $eq$ls180.v:6429$2170
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface13_bank_bus_adr [2:0]
connect \B 3'100
- connect \Y $eq$ls180.v:6433$2170_Y
+ connect \Y $eq$ls180.v:6429$2170_Y
end
- attribute \src "ls180.v:6434.109-6434.154"
- cell $eq $eq$ls180.v:6434$2174
+ attribute \src "ls180.v:6430.109-6430.154"
+ cell $eq $eq$ls180.v:6430$2174
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface13_bank_bus_adr [2:0]
connect \B 3'100
- connect \Y $eq$ls180.v:6434$2174_Y
+ connect \Y $eq$ls180.v:6430$2174_Y
end
- attribute \src "ls180.v:6436.104-6436.149"
- cell $eq $eq$ls180.v:6436$2177
+ attribute \src "ls180.v:6432.104-6432.149"
+ cell $eq $eq$ls180.v:6432$2177
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface13_bank_bus_adr [2:0]
connect \B 3'101
- connect \Y $eq$ls180.v:6436$2177_Y
+ connect \Y $eq$ls180.v:6432$2177_Y
end
- attribute \src "ls180.v:6437.107-6437.152"
- cell $eq $eq$ls180.v:6437$2181
+ attribute \src "ls180.v:6433.107-6433.152"
+ cell $eq $eq$ls180.v:6433$2181
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface13_bank_bus_adr [2:0]
connect \B 3'101
- connect \Y $eq$ls180.v:6437$2181_Y
+ connect \Y $eq$ls180.v:6433$2181_Y
end
- attribute \src "ls180.v:6439.101-6439.146"
- cell $eq $eq$ls180.v:6439$2184
+ attribute \src "ls180.v:6435.101-6435.146"
+ cell $eq $eq$ls180.v:6435$2184
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface13_bank_bus_adr [2:0]
connect \B 3'110
- connect \Y $eq$ls180.v:6439$2184_Y
+ connect \Y $eq$ls180.v:6435$2184_Y
end
- attribute \src "ls180.v:6440.104-6440.149"
- cell $eq $eq$ls180.v:6440$2188
+ attribute \src "ls180.v:6436.104-6436.149"
+ cell $eq $eq$ls180.v:6436$2188
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface13_bank_bus_adr [2:0]
connect \B 3'110
- connect \Y $eq$ls180.v:6440$2188_Y
+ connect \Y $eq$ls180.v:6436$2188_Y
end
- attribute \src "ls180.v:6442.100-6442.145"
- cell $eq $eq$ls180.v:6442$2191
+ attribute \src "ls180.v:6438.100-6438.145"
+ cell $eq $eq$ls180.v:6438$2191
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface13_bank_bus_adr [2:0]
connect \B 3'111
- connect \Y $eq$ls180.v:6442$2191_Y
+ connect \Y $eq$ls180.v:6438$2191_Y
end
- attribute \src "ls180.v:6443.103-6443.148"
- cell $eq $eq$ls180.v:6443$2195
+ attribute \src "ls180.v:6439.103-6439.148"
+ cell $eq $eq$ls180.v:6439$2195
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface13_bank_bus_adr [2:0]
connect \B 3'111
- connect \Y $eq$ls180.v:6443$2195_Y
+ connect \Y $eq$ls180.v:6439$2195_Y
end
- attribute \src "ls180.v:6453.33-6453.79"
- cell $eq $eq$ls180.v:6453$2197
+ attribute \src "ls180.v:6449.33-6449.79"
+ cell $eq $eq$ls180.v:6449$2197
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface14_bank_bus_adr [13:9]
connect \B 3'100
- connect \Y $eq$ls180.v:6453$2197_Y
+ connect \Y $eq$ls180.v:6449$2197_Y
end
- attribute \src "ls180.v:6455.106-6455.151"
- cell $eq $eq$ls180.v:6455$2199
+ attribute \src "ls180.v:6451.106-6451.151"
+ cell $eq $eq$ls180.v:6451$2199
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface14_bank_bus_adr [1:0]
connect \B 1'0
- connect \Y $eq$ls180.v:6455$2199_Y
+ connect \Y $eq$ls180.v:6451$2199_Y
end
- attribute \src "ls180.v:6456.109-6456.154"
- cell $eq $eq$ls180.v:6456$2203
+ attribute \src "ls180.v:6452.109-6452.154"
+ cell $eq $eq$ls180.v:6452$2203
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface14_bank_bus_adr [1:0]
connect \B 1'0
- connect \Y $eq$ls180.v:6456$2203_Y
+ connect \Y $eq$ls180.v:6452$2203_Y
end
- attribute \src "ls180.v:6458.106-6458.151"
- cell $eq $eq$ls180.v:6458$2206
+ attribute \src "ls180.v:6454.106-6454.151"
+ cell $eq $eq$ls180.v:6454$2206
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface14_bank_bus_adr [1:0]
connect \B 1'1
- connect \Y $eq$ls180.v:6458$2206_Y
+ connect \Y $eq$ls180.v:6454$2206_Y
end
- attribute \src "ls180.v:6459.109-6459.154"
- cell $eq $eq$ls180.v:6459$2210
+ attribute \src "ls180.v:6455.109-6455.154"
+ cell $eq $eq$ls180.v:6455$2210
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface14_bank_bus_adr [1:0]
connect \B 1'1
- connect \Y $eq$ls180.v:6459$2210_Y
+ connect \Y $eq$ls180.v:6455$2210_Y
end
- attribute \src "ls180.v:6461.106-6461.151"
- cell $eq $eq$ls180.v:6461$2213
+ attribute \src "ls180.v:6457.106-6457.151"
+ cell $eq $eq$ls180.v:6457$2213
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface14_bank_bus_adr [1:0]
connect \B 2'10
- connect \Y $eq$ls180.v:6461$2213_Y
+ connect \Y $eq$ls180.v:6457$2213_Y
end
- attribute \src "ls180.v:6462.109-6462.154"
- cell $eq $eq$ls180.v:6462$2217
+ attribute \src "ls180.v:6458.109-6458.154"
+ cell $eq $eq$ls180.v:6458$2217
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface14_bank_bus_adr [1:0]
connect \B 2'10
- connect \Y $eq$ls180.v:6462$2217_Y
+ connect \Y $eq$ls180.v:6458$2217_Y
end
- attribute \src "ls180.v:6464.106-6464.151"
- cell $eq $eq$ls180.v:6464$2220
+ attribute \src "ls180.v:6460.106-6460.151"
+ cell $eq $eq$ls180.v:6460$2220
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface14_bank_bus_adr [1:0]
connect \B 2'11
- connect \Y $eq$ls180.v:6464$2220_Y
+ connect \Y $eq$ls180.v:6460$2220_Y
end
- attribute \src "ls180.v:6465.109-6465.154"
- cell $eq $eq$ls180.v:6465$2224
+ attribute \src "ls180.v:6461.109-6461.154"
+ cell $eq $eq$ls180.v:6461$2224
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface14_bank_bus_adr [1:0]
connect \B 2'11
- connect \Y $eq$ls180.v:6465$2224_Y
+ connect \Y $eq$ls180.v:6461$2224_Y
end
- attribute \src "ls180.v:6846.41-6846.81"
- cell $eq $eq$ls180.v:6846$2261
+ attribute \src "ls180.v:6842.41-6842.81"
+ cell $eq $eq$ls180.v:6842$2261
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_port_cmd_payload_addr [10:9]
connect \B 1'0
- connect \Y $eq$ls180.v:6846$2261_Y
+ connect \Y $eq$ls180.v:6842$2261_Y
end
- attribute \src "ls180.v:6846.144-6846.177"
- cell $eq $eq$ls180.v:6846$2262
+ attribute \src "ls180.v:6842.144-6842.177"
+ cell $eq $eq$ls180.v:6842$2262
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_roundrobin1_grant
connect \B 1'0
- connect \Y $eq$ls180.v:6846$2262_Y
+ connect \Y $eq$ls180.v:6842$2262_Y
end
- attribute \src "ls180.v:6846.219-6846.252"
- cell $eq $eq$ls180.v:6846$2265
+ attribute \src "ls180.v:6842.219-6842.252"
+ cell $eq $eq$ls180.v:6842$2265
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_roundrobin2_grant
connect \B 1'0
- connect \Y $eq$ls180.v:6846$2265_Y
+ connect \Y $eq$ls180.v:6842$2265_Y
end
- attribute \src "ls180.v:6846.294-6846.327"
- cell $eq $eq$ls180.v:6846$2268
+ attribute \src "ls180.v:6842.294-6842.327"
+ cell $eq $eq$ls180.v:6842$2268
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_roundrobin3_grant
connect \B 1'0
- connect \Y $eq$ls180.v:6846$2268_Y
+ connect \Y $eq$ls180.v:6842$2268_Y
end
- attribute \src "ls180.v:6870.41-6870.81"
- cell $eq $eq$ls180.v:6870$2277
+ attribute \src "ls180.v:6866.41-6866.81"
+ cell $eq $eq$ls180.v:6866$2277
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_port_cmd_payload_addr [10:9]
connect \B 1'1
- connect \Y $eq$ls180.v:6870$2277_Y
+ connect \Y $eq$ls180.v:6866$2277_Y
end
- attribute \src "ls180.v:6870.144-6870.177"
- cell $eq $eq$ls180.v:6870$2278
+ attribute \src "ls180.v:6866.144-6866.177"
+ cell $eq $eq$ls180.v:6866$2278
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_roundrobin0_grant
connect \B 1'0
- connect \Y $eq$ls180.v:6870$2278_Y
+ connect \Y $eq$ls180.v:6866$2278_Y
end
- attribute \src "ls180.v:6870.219-6870.252"
- cell $eq $eq$ls180.v:6870$2281
+ attribute \src "ls180.v:6866.219-6866.252"
+ cell $eq $eq$ls180.v:6866$2281
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_roundrobin2_grant
connect \B 1'0
- connect \Y $eq$ls180.v:6870$2281_Y
+ connect \Y $eq$ls180.v:6866$2281_Y
end
- attribute \src "ls180.v:6870.294-6870.327"
- cell $eq $eq$ls180.v:6870$2284
+ attribute \src "ls180.v:6866.294-6866.327"
+ cell $eq $eq$ls180.v:6866$2284
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_roundrobin3_grant
connect \B 1'0
- connect \Y $eq$ls180.v:6870$2284_Y
+ connect \Y $eq$ls180.v:6866$2284_Y
end
- attribute \src "ls180.v:6894.41-6894.81"
- cell $eq $eq$ls180.v:6894$2293
+ attribute \src "ls180.v:6890.41-6890.81"
+ cell $eq $eq$ls180.v:6890$2293
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_port_cmd_payload_addr [10:9]
connect \B 2'10
- connect \Y $eq$ls180.v:6894$2293_Y
+ connect \Y $eq$ls180.v:6890$2293_Y
end
- attribute \src "ls180.v:6894.144-6894.177"
- cell $eq $eq$ls180.v:6894$2294
+ attribute \src "ls180.v:6890.144-6890.177"
+ cell $eq $eq$ls180.v:6890$2294
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_roundrobin0_grant
connect \B 1'0
- connect \Y $eq$ls180.v:6894$2294_Y
+ connect \Y $eq$ls180.v:6890$2294_Y
end
- attribute \src "ls180.v:6894.219-6894.252"
- cell $eq $eq$ls180.v:6894$2297
+ attribute \src "ls180.v:6890.219-6890.252"
+ cell $eq $eq$ls180.v:6890$2297
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_roundrobin1_grant
connect \B 1'0
- connect \Y $eq$ls180.v:6894$2297_Y
+ connect \Y $eq$ls180.v:6890$2297_Y
end
- attribute \src "ls180.v:6894.294-6894.327"
- cell $eq $eq$ls180.v:6894$2300
+ attribute \src "ls180.v:6890.294-6890.327"
+ cell $eq $eq$ls180.v:6890$2300
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_roundrobin3_grant
connect \B 1'0
- connect \Y $eq$ls180.v:6894$2300_Y
+ connect \Y $eq$ls180.v:6890$2300_Y
end
- attribute \src "ls180.v:6918.41-6918.81"
- cell $eq $eq$ls180.v:6918$2309
+ attribute \src "ls180.v:6914.41-6914.81"
+ cell $eq $eq$ls180.v:6914$2309
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_port_cmd_payload_addr [10:9]
connect \B 2'11
- connect \Y $eq$ls180.v:6918$2309_Y
+ connect \Y $eq$ls180.v:6914$2309_Y
end
- attribute \src "ls180.v:6918.144-6918.177"
- cell $eq $eq$ls180.v:6918$2310
+ attribute \src "ls180.v:6914.144-6914.177"
+ cell $eq $eq$ls180.v:6914$2310
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_roundrobin0_grant
connect \B 1'0
- connect \Y $eq$ls180.v:6918$2310_Y
+ connect \Y $eq$ls180.v:6914$2310_Y
end
- attribute \src "ls180.v:6918.219-6918.252"
- cell $eq $eq$ls180.v:6918$2313
+ attribute \src "ls180.v:6914.219-6914.252"
+ cell $eq $eq$ls180.v:6914$2313
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_roundrobin1_grant
connect \B 1'0
- connect \Y $eq$ls180.v:6918$2313_Y
+ connect \Y $eq$ls180.v:6914$2313_Y
end
- attribute \src "ls180.v:6918.294-6918.327"
- cell $eq $eq$ls180.v:6918$2316
+ attribute \src "ls180.v:6914.294-6914.327"
+ cell $eq $eq$ls180.v:6914$2316
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_roundrobin2_grant
connect \B 1'0
- connect \Y $eq$ls180.v:6918$2316_Y
+ connect \Y $eq$ls180.v:6914$2316_Y
end
- attribute \src "ls180.v:7499.8-7499.38"
- cell $eq $eq$ls180.v:7499$2407
+ attribute \src "ls180.v:7495.8-7495.38"
+ cell $eq $eq$ls180.v:7495$2407
parameter \A_SIGNED 0
parameter \A_WIDTH 32
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_libresocsim_value
connect \B 1'0
- connect \Y $eq$ls180.v:7499$2407_Y
+ connect \Y $eq$ls180.v:7495$2407_Y
end
- attribute \src "ls180.v:7530.8-7530.42"
- cell $eq $eq$ls180.v:7530$2415
+ attribute \src "ls180.v:7526.8-7526.42"
+ cell $eq $eq$ls180.v:7526$2415
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_postponer_count
connect \B 1'0
- connect \Y $eq$ls180.v:7530$2415_Y
+ connect \Y $eq$ls180.v:7526$2415_Y
end
- attribute \src "ls180.v:7550.38-7550.74"
- cell $eq $eq$ls180.v:7550$2418
+ attribute \src "ls180.v:7546.38-7546.74"
+ cell $eq $eq$ls180.v:7546$2418
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_sequencer_counter
connect \B 1'0
- connect \Y $eq$ls180.v:7550$2418_Y
+ connect \Y $eq$ls180.v:7546$2418_Y
end
- attribute \src "ls180.v:7557.7-7557.43"
- cell $eq $eq$ls180.v:7557$2420
+ attribute \src "ls180.v:7553.7-7553.43"
+ cell $eq $eq$ls180.v:7553$2420
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_sequencer_counter
connect \B 2'10
- connect \Y $eq$ls180.v:7557$2420_Y
+ connect \Y $eq$ls180.v:7553$2420_Y
end
- attribute \src "ls180.v:7564.7-7564.43"
- cell $eq $eq$ls180.v:7564$2421
+ attribute \src "ls180.v:7560.7-7560.43"
+ cell $eq $eq$ls180.v:7560$2421
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_sequencer_counter
connect \B 4'1000
- connect \Y $eq$ls180.v:7564$2421_Y
+ connect \Y $eq$ls180.v:7560$2421_Y
end
- attribute \src "ls180.v:7572.7-7572.43"
- cell $eq $eq$ls180.v:7572$2422
+ attribute \src "ls180.v:7568.7-7568.43"
+ cell $eq $eq$ls180.v:7568$2422
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_sequencer_counter
connect \B 4'1000
- connect \Y $eq$ls180.v:7572$2422_Y
+ connect \Y $eq$ls180.v:7568$2422_Y
end
- attribute \src "ls180.v:7624.9-7624.54"
- cell $eq $eq$ls180.v:7624$2440
+ attribute \src "ls180.v:7620.9-7620.54"
+ cell $eq $eq$ls180.v:7620$2440
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine0_twtpcon_count
connect \B 1'1
- connect \Y $eq$ls180.v:7624$2440_Y
+ connect \Y $eq$ls180.v:7620$2440_Y
end
- attribute \src "ls180.v:7670.9-7670.54"
- cell $eq $eq$ls180.v:7670$2456
+ attribute \src "ls180.v:7666.9-7666.54"
+ cell $eq $eq$ls180.v:7666$2456
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine1_twtpcon_count
connect \B 1'1
- connect \Y $eq$ls180.v:7670$2456_Y
+ connect \Y $eq$ls180.v:7666$2456_Y
end
- attribute \src "ls180.v:7716.9-7716.54"
- cell $eq $eq$ls180.v:7716$2472
+ attribute \src "ls180.v:7712.9-7712.54"
+ cell $eq $eq$ls180.v:7712$2472
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine2_twtpcon_count
connect \B 1'1
- connect \Y $eq$ls180.v:7716$2472_Y
+ connect \Y $eq$ls180.v:7712$2472_Y
end
- attribute \src "ls180.v:7762.9-7762.54"
- cell $eq $eq$ls180.v:7762$2488
+ attribute \src "ls180.v:7758.9-7758.54"
+ cell $eq $eq$ls180.v:7758$2488
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine3_twtpcon_count
connect \B 1'1
- connect \Y $eq$ls180.v:7762$2488_Y
+ connect \Y $eq$ls180.v:7758$2488_Y
end
- attribute \src "ls180.v:7912.9-7912.41"
- cell $eq $eq$ls180.v:7912$2500
+ attribute \src "ls180.v:7908.9-7908.41"
+ cell $eq $eq$ls180.v:7908$2500
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_tccdcon_count
connect \B 1'1
- connect \Y $eq$ls180.v:7912$2500_Y
+ connect \Y $eq$ls180.v:7908$2500_Y
end
- attribute \src "ls180.v:7927.9-7927.41"
- cell $eq $eq$ls180.v:7927$2503
+ attribute \src "ls180.v:7923.9-7923.41"
+ cell $eq $eq$ls180.v:7923$2503
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_twtrcon_count
connect \B 1'1
- connect \Y $eq$ls180.v:7927$2503_Y
+ connect \Y $eq$ls180.v:7923$2503_Y
end
- attribute \src "ls180.v:7933.49-7933.82"
- cell $eq $eq$ls180.v:7933$2504
+ attribute \src "ls180.v:7929.49-7929.82"
+ cell $eq $eq$ls180.v:7929$2504
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_roundrobin0_grant
connect \B 1'0
- connect \Y $eq$ls180.v:7933$2504_Y
+ connect \Y $eq$ls180.v:7929$2504_Y
end
- attribute \src "ls180.v:7933.131-7933.164"
- cell $eq $eq$ls180.v:7933$2507
+ attribute \src "ls180.v:7929.131-7929.164"
+ cell $eq $eq$ls180.v:7929$2507
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_roundrobin1_grant
connect \B 1'0
- connect \Y $eq$ls180.v:7933$2507_Y
+ connect \Y $eq$ls180.v:7929$2507_Y
end
- attribute \src "ls180.v:7933.213-7933.246"
- cell $eq $eq$ls180.v:7933$2510
+ attribute \src "ls180.v:7929.213-7929.246"
+ cell $eq $eq$ls180.v:7929$2510
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_roundrobin2_grant
connect \B 1'0
- connect \Y $eq$ls180.v:7933$2510_Y
+ connect \Y $eq$ls180.v:7929$2510_Y
end
- attribute \src "ls180.v:7933.295-7933.328"
- cell $eq $eq$ls180.v:7933$2513
+ attribute \src "ls180.v:7929.295-7929.328"
+ cell $eq $eq$ls180.v:7929$2513
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_roundrobin3_grant
connect \B 1'0
- connect \Y $eq$ls180.v:7933$2513_Y
+ connect \Y $eq$ls180.v:7929$2513_Y
end
- attribute \src "ls180.v:7934.50-7934.83"
- cell $eq $eq$ls180.v:7934$2516
+ attribute \src "ls180.v:7930.50-7930.83"
+ cell $eq $eq$ls180.v:7930$2516
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_roundrobin0_grant
connect \B 1'0
- connect \Y $eq$ls180.v:7934$2516_Y
+ connect \Y $eq$ls180.v:7930$2516_Y
end
- attribute \src "ls180.v:7934.132-7934.165"
- cell $eq $eq$ls180.v:7934$2519
+ attribute \src "ls180.v:7930.132-7930.165"
+ cell $eq $eq$ls180.v:7930$2519
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_roundrobin1_grant
connect \B 1'0
- connect \Y $eq$ls180.v:7934$2519_Y
+ connect \Y $eq$ls180.v:7930$2519_Y
end
- attribute \src "ls180.v:7934.214-7934.247"
- cell $eq $eq$ls180.v:7934$2522
+ attribute \src "ls180.v:7930.214-7930.247"
+ cell $eq $eq$ls180.v:7930$2522
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_roundrobin2_grant
connect \B 1'0
- connect \Y $eq$ls180.v:7934$2522_Y
+ connect \Y $eq$ls180.v:7930$2522_Y
end
- attribute \src "ls180.v:7934.296-7934.329"
- cell $eq $eq$ls180.v:7934$2525
+ attribute \src "ls180.v:7930.296-7930.329"
+ cell $eq $eq$ls180.v:7930$2525
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_roundrobin3_grant
connect \B 1'0
- connect \Y $eq$ls180.v:7934$2525_Y
+ connect \Y $eq$ls180.v:7930$2525_Y
end
- attribute \src "ls180.v:7969.9-7969.42"
- cell $eq $eq$ls180.v:7969$2537
+ attribute \src "ls180.v:7965.9-7965.42"
+ cell $eq $eq$ls180.v:7965$2537
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_uart_phy_tx_bitcount
connect \B 4'1000
- connect \Y $eq$ls180.v:7969$2537_Y
+ connect \Y $eq$ls180.v:7965$2537_Y
end
- attribute \src "ls180.v:7972.10-7972.43"
- cell $eq $eq$ls180.v:7972$2538
+ attribute \src "ls180.v:7968.10-7968.43"
+ cell $eq $eq$ls180.v:7968$2538
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_uart_phy_tx_bitcount
connect \B 4'1001
- connect \Y $eq$ls180.v:7972$2538_Y
+ connect \Y $eq$ls180.v:7968$2538_Y
end
- attribute \src "ls180.v:7998.9-7998.42"
- cell $eq $eq$ls180.v:7998$2544
+ attribute \src "ls180.v:7994.9-7994.42"
+ cell $eq $eq$ls180.v:7994$2544
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_uart_phy_rx_bitcount
connect \B 1'0
- connect \Y $eq$ls180.v:7998$2544_Y
+ connect \Y $eq$ls180.v:7994$2544_Y
end
- attribute \src "ls180.v:8003.10-8003.43"
- cell $eq $eq$ls180.v:8003$2545
+ attribute \src "ls180.v:7999.10-7999.43"
+ cell $eq $eq$ls180.v:7999$2545
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_uart_phy_rx_bitcount
connect \B 4'1001
- connect \Y $eq$ls180.v:8003$2545_Y
+ connect \Y $eq$ls180.v:7999$2545_Y
end
- attribute \src "ls180.v:8210.9-8210.53"
- cell $eq $eq$ls180.v:8210$2594
+ attribute \src "ls180.v:8206.9-8206.53"
+ cell $eq $eq$ls180.v:8206$2594
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdphy_cmdr_cmdr_converter_demux
connect \B 3'111
- connect \Y $eq$ls180.v:8210$2594_Y
+ connect \Y $eq$ls180.v:8206$2594_Y
end
- attribute \src "ls180.v:8291.9-8291.54"
- cell $eq $eq$ls180.v:8291$2606
+ attribute \src "ls180.v:8287.9-8287.54"
+ cell $eq $eq$ls180.v:8287$2606
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdphy_dataw_crcr_converter_demux
connect \B 3'111
- connect \Y $eq$ls180.v:8291$2606_Y
+ connect \Y $eq$ls180.v:8287$2606_Y
end
- attribute \src "ls180.v:8370.9-8370.55"
- cell $eq $eq$ls180.v:8370$2618
+ attribute \src "ls180.v:8366.9-8366.55"
+ cell $eq $eq$ls180.v:8366$2618
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdphy_datar_datar_converter_demux
connect \B 1'1
- connect \Y $eq$ls180.v:8370$2618_Y
+ connect \Y $eq$ls180.v:8366$2618_Y
end
- attribute \src "ls180.v:8593.9-8593.49"
- cell $eq $eq$ls180.v:8593$2651
+ attribute \src "ls180.v:8589.9-8589.49"
+ cell $eq $eq$ls180.v:8589$2651
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdblock2mem_converter_demux
connect \B 2'11
- connect \Y $eq$ls180.v:8593$2651_Y
+ connect \Y $eq$ls180.v:8589$2651_Y
end
- attribute \src "ls180.v:8169.8-8169.54"
- cell $ge $ge$ls180.v:8169$2586
+ attribute \src "ls180.v:8165.8-8165.54"
+ cell $ge $ge$ls180.v:8165$2586
parameter \A_SIGNED 0
parameter \A_WIDTH 32
parameter \B_SIGNED 0
parameter \B_WIDTH 32
parameter \Y_WIDTH 1
connect \A \main_pwm0_counter
- connect \B $sub$ls180.v:8169$2585_Y
- connect \Y $ge$ls180.v:8169$2586_Y
+ connect \B $sub$ls180.v:8165$2585_Y
+ connect \Y $ge$ls180.v:8165$2586_Y
end
- attribute \src "ls180.v:8183.8-8183.54"
- cell $ge $ge$ls180.v:8183$2590
+ attribute \src "ls180.v:8179.8-8179.54"
+ cell $ge $ge$ls180.v:8179$2590
parameter \A_SIGNED 0
parameter \A_WIDTH 32
parameter \B_SIGNED 0
parameter \B_WIDTH 32
parameter \Y_WIDTH 1
connect \A \main_pwm1_counter
- connect \B $sub$ls180.v:8183$2589_Y
- connect \Y $ge$ls180.v:8183$2590_Y
+ connect \B $sub$ls180.v:8179$2589_Y
+ connect \Y $ge$ls180.v:8179$2590_Y
end
- attribute \src "ls180.v:5155.47-5155.83"
- cell $gt $gt$ls180.v:5155$914
+ attribute \src "ls180.v:5151.47-5151.83"
+ cell $gt $gt$ls180.v:5151$914
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_checker_cnt
connect \B 3'111
- connect \Y $gt$ls180.v:5155$914_Y
+ connect \Y $gt$ls180.v:5151$914_Y
end
- attribute \src "ls180.v:5161.7-5161.43"
- cell $lt $lt$ls180.v:5161$917
+ attribute \src "ls180.v:5157.7-5157.43"
+ cell $lt $lt$ls180.v:5157$917
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_checker_cnt
connect \B 4'1000
- connect \Y $lt$ls180.v:5161$917_Y
+ connect \Y $lt$ls180.v:5157$917_Y
end
- attribute \src "ls180.v:8164.8-8164.43"
- cell $lt $lt$ls180.v:8164$2584
+ attribute \src "ls180.v:8160.8-8160.43"
+ cell $lt $lt$ls180.v:8160$2584
parameter \A_SIGNED 0
parameter \A_WIDTH 32
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_pwm0_counter
connect \B \main_pwm0_width
- connect \Y $lt$ls180.v:8164$2584_Y
+ connect \Y $lt$ls180.v:8160$2584_Y
end
- attribute \src "ls180.v:8178.8-8178.43"
- cell $lt $lt$ls180.v:8178$2588
+ attribute \src "ls180.v:8174.8-8174.43"
+ cell $lt $lt$ls180.v:8174$2588
parameter \A_SIGNED 0
parameter \A_WIDTH 32
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_pwm1_counter
connect \B \main_pwm1_width
- connect \Y $lt$ls180.v:8178$2588_Y
+ connect \Y $lt$ls180.v:8174$2588_Y
end
- attribute \src "ls180.v:10059.33-10059.36"
- cell $memrd $memrd$\mem$ls180.v:10059$2693
+ attribute \src "ls180.v:10055.33-10055.36"
+ cell $memrd $memrd$\mem$ls180.v:10055$2693
parameter \ABITS 7
parameter \CLK_ENABLE 0
parameter \CLK_POLARITY 0
parameter \WIDTH 32
connect \ADDR \memadr
connect \CLK 1'x
- connect \DATA $memrd$\mem$ls180.v:10059$2693_DATA
+ connect \DATA $memrd$\mem$ls180.v:10055$2693_DATA
connect \EN 1'x
end
- attribute \src "ls180.v:10070.12-10070.19"
- cell $memrd $memrd$\storage$ls180.v:10070$2698
+ attribute \src "ls180.v:10066.12-10066.19"
+ cell $memrd $memrd$\storage$ls180.v:10066$2698
parameter \ABITS 3
parameter \CLK_ENABLE 0
parameter \CLK_POLARITY 0
parameter \WIDTH 25
connect \ADDR \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr
connect \CLK 1'x
- connect \DATA $memrd$\storage$ls180.v:10070$2698_DATA
+ connect \DATA $memrd$\storage$ls180.v:10066$2698_DATA
connect \EN 1'x
end
- attribute \src "ls180.v:10077.68-10077.75"
- cell $memrd $memrd$\storage$ls180.v:10077$2700
+ attribute \src "ls180.v:10073.68-10073.75"
+ cell $memrd $memrd$\storage$ls180.v:10073$2700
parameter \ABITS 3
parameter \CLK_ENABLE 0
parameter \CLK_POLARITY 0
parameter \WIDTH 25
connect \ADDR \main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_adr
connect \CLK 1'x
- connect \DATA $memrd$\storage$ls180.v:10077$2700_DATA
+ connect \DATA $memrd$\storage$ls180.v:10073$2700_DATA
connect \EN 1'x
end
- attribute \src "ls180.v:10084.14-10084.23"
- cell $memrd $memrd$\storage_1$ls180.v:10084$2705
+ attribute \src "ls180.v:10080.14-10080.23"
+ cell $memrd $memrd$\storage_1$ls180.v:10080$2705
parameter \ABITS 3
parameter \CLK_ENABLE 0
parameter \CLK_POLARITY 0
parameter \WIDTH 25
connect \ADDR \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr
connect \CLK 1'x
- connect \DATA $memrd$\storage_1$ls180.v:10084$2705_DATA
+ connect \DATA $memrd$\storage_1$ls180.v:10080$2705_DATA
connect \EN 1'x
end
- attribute \src "ls180.v:10091.68-10091.77"
- cell $memrd $memrd$\storage_1$ls180.v:10091$2707
+ attribute \src "ls180.v:10087.68-10087.77"
+ cell $memrd $memrd$\storage_1$ls180.v:10087$2707
parameter \ABITS 3
parameter \CLK_ENABLE 0
parameter \CLK_POLARITY 0
parameter \WIDTH 25
connect \ADDR \main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_adr
connect \CLK 1'x
- connect \DATA $memrd$\storage_1$ls180.v:10091$2707_DATA
+ connect \DATA $memrd$\storage_1$ls180.v:10087$2707_DATA
connect \EN 1'x
end
- attribute \src "ls180.v:10098.14-10098.23"
- cell $memrd $memrd$\storage_2$ls180.v:10098$2712
+ attribute \src "ls180.v:10094.14-10094.23"
+ cell $memrd $memrd$\storage_2$ls180.v:10094$2712
parameter \ABITS 3
parameter \CLK_ENABLE 0
parameter \CLK_POLARITY 0
parameter \WIDTH 25
connect \ADDR \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr
connect \CLK 1'x
- connect \DATA $memrd$\storage_2$ls180.v:10098$2712_DATA
+ connect \DATA $memrd$\storage_2$ls180.v:10094$2712_DATA
connect \EN 1'x
end
- attribute \src "ls180.v:10105.68-10105.77"
- cell $memrd $memrd$\storage_2$ls180.v:10105$2714
+ attribute \src "ls180.v:10101.68-10101.77"
+ cell $memrd $memrd$\storage_2$ls180.v:10101$2714
parameter \ABITS 3
parameter \CLK_ENABLE 0
parameter \CLK_POLARITY 0
parameter \WIDTH 25
connect \ADDR \main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_adr
connect \CLK 1'x
- connect \DATA $memrd$\storage_2$ls180.v:10105$2714_DATA
+ connect \DATA $memrd$\storage_2$ls180.v:10101$2714_DATA
connect \EN 1'x
end
- attribute \src "ls180.v:10112.14-10112.23"
- cell $memrd $memrd$\storage_3$ls180.v:10112$2719
+ attribute \src "ls180.v:10108.14-10108.23"
+ cell $memrd $memrd$\storage_3$ls180.v:10108$2719
parameter \ABITS 3
parameter \CLK_ENABLE 0
parameter \CLK_POLARITY 0
parameter \WIDTH 25
connect \ADDR \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr
connect \CLK 1'x
- connect \DATA $memrd$\storage_3$ls180.v:10112$2719_DATA
+ connect \DATA $memrd$\storage_3$ls180.v:10108$2719_DATA
connect \EN 1'x
end
- attribute \src "ls180.v:10119.68-10119.77"
- cell $memrd $memrd$\storage_3$ls180.v:10119$2721
+ attribute \src "ls180.v:10115.68-10115.77"
+ cell $memrd $memrd$\storage_3$ls180.v:10115$2721
parameter \ABITS 3
parameter \CLK_ENABLE 0
parameter \CLK_POLARITY 0
parameter \WIDTH 25
connect \ADDR \main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_adr
connect \CLK 1'x
- connect \DATA $memrd$\storage_3$ls180.v:10119$2721_DATA
+ connect \DATA $memrd$\storage_3$ls180.v:10115$2721_DATA
connect \EN 1'x
end
- attribute \src "ls180.v:10127.14-10127.23"
- cell $memrd $memrd$\storage_4$ls180.v:10127$2726
+ attribute \src "ls180.v:10123.14-10123.23"
+ cell $memrd $memrd$\storage_4$ls180.v:10123$2726
parameter \ABITS 4
parameter \CLK_ENABLE 0
parameter \CLK_POLARITY 0
parameter \WIDTH 10
connect \ADDR \main_uart_tx_fifo_wrport_adr
connect \CLK 1'x
- connect \DATA $memrd$\storage_4$ls180.v:10127$2726_DATA
+ connect \DATA $memrd$\storage_4$ls180.v:10123$2726_DATA
connect \EN 1'x
end
- attribute \src "ls180.v:10132.15-10132.24"
- cell $memrd $memrd$\storage_4$ls180.v:10132$2728
+ attribute \src "ls180.v:10128.15-10128.24"
+ cell $memrd $memrd$\storage_4$ls180.v:10128$2728
parameter \ABITS 4
parameter \CLK_ENABLE 0
parameter \CLK_POLARITY 0
parameter \WIDTH 10
connect \ADDR \main_uart_tx_fifo_rdport_adr
connect \CLK 1'x
- connect \DATA $memrd$\storage_4$ls180.v:10132$2728_DATA
+ connect \DATA $memrd$\storage_4$ls180.v:10128$2728_DATA
connect \EN 1'x
end
- attribute \src "ls180.v:10144.14-10144.23"
- cell $memrd $memrd$\storage_5$ls180.v:10144$2733
+ attribute \src "ls180.v:10140.14-10140.23"
+ cell $memrd $memrd$\storage_5$ls180.v:10140$2733
parameter \ABITS 4
parameter \CLK_ENABLE 0
parameter \CLK_POLARITY 0
parameter \WIDTH 10
connect \ADDR \main_uart_rx_fifo_wrport_adr
connect \CLK 1'x
- connect \DATA $memrd$\storage_5$ls180.v:10144$2733_DATA
+ connect \DATA $memrd$\storage_5$ls180.v:10140$2733_DATA
connect \EN 1'x
end
- attribute \src "ls180.v:10149.15-10149.24"
- cell $memrd $memrd$\storage_5$ls180.v:10149$2735
+ attribute \src "ls180.v:10145.15-10145.24"
+ cell $memrd $memrd$\storage_5$ls180.v:10145$2735
parameter \ABITS 4
parameter \CLK_ENABLE 0
parameter \CLK_POLARITY 0
parameter \WIDTH 10
connect \ADDR \main_uart_rx_fifo_rdport_adr
connect \CLK 1'x
- connect \DATA $memrd$\storage_5$ls180.v:10149$2735_DATA
+ connect \DATA $memrd$\storage_5$ls180.v:10145$2735_DATA
connect \EN 1'x
end
- attribute \src "ls180.v:10160.14-10160.23"
- cell $memrd $memrd$\storage_6$ls180.v:10160$2740
+ attribute \src "ls180.v:10156.14-10156.23"
+ cell $memrd $memrd$\storage_6$ls180.v:10156$2740
parameter \ABITS 5
parameter \CLK_ENABLE 0
parameter \CLK_POLARITY 0
parameter \WIDTH 10
connect \ADDR \main_sdblock2mem_fifo_wrport_adr
connect \CLK 1'x
- connect \DATA $memrd$\storage_6$ls180.v:10160$2740_DATA
+ connect \DATA $memrd$\storage_6$ls180.v:10156$2740_DATA
connect \EN 1'x
end
- attribute \src "ls180.v:10167.45-10167.54"
- cell $memrd $memrd$\storage_6$ls180.v:10167$2742
+ attribute \src "ls180.v:10163.45-10163.54"
+ cell $memrd $memrd$\storage_6$ls180.v:10163$2742
parameter \ABITS 5
parameter \CLK_ENABLE 0
parameter \CLK_POLARITY 0
parameter \WIDTH 10
connect \ADDR \main_sdblock2mem_fifo_rdport_adr
connect \CLK 1'x
- connect \DATA $memrd$\storage_6$ls180.v:10167$2742_DATA
+ connect \DATA $memrd$\storage_6$ls180.v:10163$2742_DATA
connect \EN 1'x
end
- attribute \src "ls180.v:10174.14-10174.23"
- cell $memrd $memrd$\storage_7$ls180.v:10174$2747
+ attribute \src "ls180.v:10170.14-10170.23"
+ cell $memrd $memrd$\storage_7$ls180.v:10170$2747
parameter \ABITS 5
parameter \CLK_ENABLE 0
parameter \CLK_POLARITY 0
parameter \WIDTH 10
connect \ADDR \main_sdmem2block_fifo_wrport_adr
connect \CLK 1'x
- connect \DATA $memrd$\storage_7$ls180.v:10174$2747_DATA
+ connect \DATA $memrd$\storage_7$ls180.v:10170$2747_DATA
connect \EN 1'x
end
- attribute \src "ls180.v:10181.45-10181.54"
- cell $memrd $memrd$\storage_7$ls180.v:10181$2749
+ attribute \src "ls180.v:10177.45-10177.54"
+ cell $memrd $memrd$\storage_7$ls180.v:10177$2749
parameter \ABITS 5
parameter \CLK_ENABLE 0
parameter \CLK_POLARITY 0
parameter \WIDTH 10
connect \ADDR \main_sdmem2block_fifo_rdport_adr
connect \CLK 1'x
- connect \DATA $memrd$\storage_7$ls180.v:10181$2749_DATA
+ connect \DATA $memrd$\storage_7$ls180.v:10177$2749_DATA
connect \EN 1'x
end
attribute \src "ls180.v:0.0-0.0"
parameter \MEMID "\\mem"
parameter \PRIORITY 2751
parameter \WIDTH 32
- connect \ADDR $memwr$\mem$ls180.v:10049$1_ADDR
+ connect \ADDR $memwr$\mem$ls180.v:10045$1_ADDR
connect \CLK 1'x
- connect \DATA $memwr$\mem$ls180.v:10049$1_DATA
- connect \EN $memwr$\mem$ls180.v:10049$1_EN
+ connect \DATA $memwr$\mem$ls180.v:10045$1_DATA
+ connect \EN $memwr$\mem$ls180.v:10045$1_EN
end
attribute \src "ls180.v:0.0-0.0"
cell $memwr $memwr$\mem$ls180.v:0$2752
parameter \MEMID "\\mem"
parameter \PRIORITY 2752
parameter \WIDTH 32
- connect \ADDR $memwr$\mem$ls180.v:10051$2_ADDR
+ connect \ADDR $memwr$\mem$ls180.v:10047$2_ADDR
connect \CLK 1'x
- connect \DATA $memwr$\mem$ls180.v:10051$2_DATA
- connect \EN $memwr$\mem$ls180.v:10051$2_EN
+ connect \DATA $memwr$\mem$ls180.v:10047$2_DATA
+ connect \EN $memwr$\mem$ls180.v:10047$2_EN
end
attribute \src "ls180.v:0.0-0.0"
cell $memwr $memwr$\mem$ls180.v:0$2753
parameter \MEMID "\\mem"
parameter \PRIORITY 2753
parameter \WIDTH 32
- connect \ADDR $memwr$\mem$ls180.v:10053$3_ADDR
+ connect \ADDR $memwr$\mem$ls180.v:10049$3_ADDR
connect \CLK 1'x
- connect \DATA $memwr$\mem$ls180.v:10053$3_DATA
- connect \EN $memwr$\mem$ls180.v:10053$3_EN
+ connect \DATA $memwr$\mem$ls180.v:10049$3_DATA
+ connect \EN $memwr$\mem$ls180.v:10049$3_EN
end
attribute \src "ls180.v:0.0-0.0"
cell $memwr $memwr$\mem$ls180.v:0$2754
parameter \MEMID "\\mem"
parameter \PRIORITY 2754
parameter \WIDTH 32
- connect \ADDR $memwr$\mem$ls180.v:10055$4_ADDR
+ connect \ADDR $memwr$\mem$ls180.v:10051$4_ADDR
connect \CLK 1'x
- connect \DATA $memwr$\mem$ls180.v:10055$4_DATA
- connect \EN $memwr$\mem$ls180.v:10055$4_EN
+ connect \DATA $memwr$\mem$ls180.v:10051$4_DATA
+ connect \EN $memwr$\mem$ls180.v:10051$4_EN
end
attribute \src "ls180.v:0.0-0.0"
cell $memwr $memwr$\storage$ls180.v:0$2755
parameter \MEMID "\\storage"
parameter \PRIORITY 2755
parameter \WIDTH 25
- connect \ADDR $memwr$\storage$ls180.v:10069$5_ADDR
+ connect \ADDR $memwr$\storage$ls180.v:10065$5_ADDR
connect \CLK 1'x
- connect \DATA $memwr$\storage$ls180.v:10069$5_DATA
- connect \EN $memwr$\storage$ls180.v:10069$5_EN
+ connect \DATA $memwr$\storage$ls180.v:10065$5_DATA
+ connect \EN $memwr$\storage$ls180.v:10065$5_EN
end
attribute \src "ls180.v:0.0-0.0"
cell $memwr $memwr$\storage_1$ls180.v:0$2756
parameter \MEMID "\\storage_1"
parameter \PRIORITY 2756
parameter \WIDTH 25
- connect \ADDR $memwr$\storage_1$ls180.v:10083$6_ADDR
+ connect \ADDR $memwr$\storage_1$ls180.v:10079$6_ADDR
connect \CLK 1'x
- connect \DATA $memwr$\storage_1$ls180.v:10083$6_DATA
- connect \EN $memwr$\storage_1$ls180.v:10083$6_EN
+ connect \DATA $memwr$\storage_1$ls180.v:10079$6_DATA
+ connect \EN $memwr$\storage_1$ls180.v:10079$6_EN
end
attribute \src "ls180.v:0.0-0.0"
cell $memwr $memwr$\storage_2$ls180.v:0$2757
parameter \MEMID "\\storage_2"
parameter \PRIORITY 2757
parameter \WIDTH 25
- connect \ADDR $memwr$\storage_2$ls180.v:10097$7_ADDR
+ connect \ADDR $memwr$\storage_2$ls180.v:10093$7_ADDR
connect \CLK 1'x
- connect \DATA $memwr$\storage_2$ls180.v:10097$7_DATA
- connect \EN $memwr$\storage_2$ls180.v:10097$7_EN
+ connect \DATA $memwr$\storage_2$ls180.v:10093$7_DATA
+ connect \EN $memwr$\storage_2$ls180.v:10093$7_EN
end
attribute \src "ls180.v:0.0-0.0"
cell $memwr $memwr$\storage_3$ls180.v:0$2758
parameter \MEMID "\\storage_3"
parameter \PRIORITY 2758
parameter \WIDTH 25
- connect \ADDR $memwr$\storage_3$ls180.v:10111$8_ADDR
+ connect \ADDR $memwr$\storage_3$ls180.v:10107$8_ADDR
connect \CLK 1'x
- connect \DATA $memwr$\storage_3$ls180.v:10111$8_DATA
- connect \EN $memwr$\storage_3$ls180.v:10111$8_EN
+ connect \DATA $memwr$\storage_3$ls180.v:10107$8_DATA
+ connect \EN $memwr$\storage_3$ls180.v:10107$8_EN
end
attribute \src "ls180.v:0.0-0.0"
cell $memwr $memwr$\storage_4$ls180.v:0$2759
parameter \MEMID "\\storage_4"
parameter \PRIORITY 2759
parameter \WIDTH 10
- connect \ADDR $memwr$\storage_4$ls180.v:10126$9_ADDR
+ connect \ADDR $memwr$\storage_4$ls180.v:10122$9_ADDR
connect \CLK 1'x
- connect \DATA $memwr$\storage_4$ls180.v:10126$9_DATA
- connect \EN $memwr$\storage_4$ls180.v:10126$9_EN
+ connect \DATA $memwr$\storage_4$ls180.v:10122$9_DATA
+ connect \EN $memwr$\storage_4$ls180.v:10122$9_EN
end
attribute \src "ls180.v:0.0-0.0"
cell $memwr $memwr$\storage_5$ls180.v:0$2760
parameter \MEMID "\\storage_5"
parameter \PRIORITY 2760
parameter \WIDTH 10
- connect \ADDR $memwr$\storage_5$ls180.v:10143$10_ADDR
+ connect \ADDR $memwr$\storage_5$ls180.v:10139$10_ADDR
connect \CLK 1'x
- connect \DATA $memwr$\storage_5$ls180.v:10143$10_DATA
- connect \EN $memwr$\storage_5$ls180.v:10143$10_EN
+ connect \DATA $memwr$\storage_5$ls180.v:10139$10_DATA
+ connect \EN $memwr$\storage_5$ls180.v:10139$10_EN
end
attribute \src "ls180.v:0.0-0.0"
cell $memwr $memwr$\storage_6$ls180.v:0$2761
parameter \MEMID "\\storage_6"
parameter \PRIORITY 2761
parameter \WIDTH 10
- connect \ADDR $memwr$\storage_6$ls180.v:10159$11_ADDR
+ connect \ADDR $memwr$\storage_6$ls180.v:10155$11_ADDR
connect \CLK 1'x
- connect \DATA $memwr$\storage_6$ls180.v:10159$11_DATA
- connect \EN $memwr$\storage_6$ls180.v:10159$11_EN
+ connect \DATA $memwr$\storage_6$ls180.v:10155$11_DATA
+ connect \EN $memwr$\storage_6$ls180.v:10155$11_EN
end
attribute \src "ls180.v:0.0-0.0"
cell $memwr $memwr$\storage_7$ls180.v:0$2762
parameter \MEMID "\\storage_7"
parameter \PRIORITY 2762
parameter \WIDTH 10
- connect \ADDR $memwr$\storage_7$ls180.v:10173$12_ADDR
+ connect \ADDR $memwr$\storage_7$ls180.v:10169$12_ADDR
connect \CLK 1'x
- connect \DATA $memwr$\storage_7$ls180.v:10173$12_DATA
- connect \EN $memwr$\storage_7$ls180.v:10173$12_EN
+ connect \DATA $memwr$\storage_7$ls180.v:10169$12_DATA
+ connect \EN $memwr$\storage_7$ls180.v:10169$12_EN
end
- attribute \src "ls180.v:2969.41-2969.71"
- cell $ne $ne$ls180.v:2969$60
+ attribute \src "ls180.v:2965.41-2965.71"
+ cell $ne $ne$ls180.v:2965$60
parameter \A_SIGNED 0
parameter \A_WIDTH 32
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_libresocsim_value
connect \B 1'0
- connect \Y $ne$ls180.v:2969$60_Y
+ connect \Y $ne$ls180.v:2965$60_Y
end
- attribute \src "ls180.v:3130.70-3130.104"
- cell $ne $ne$ls180.v:3130$74
+ attribute \src "ls180.v:3126.70-3126.104"
+ cell $ne $ne$ls180.v:3126$74
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_sequencer_count
connect \B 1'0
- connect \Y $ne$ls180.v:3130$74_Y
+ connect \Y $ne$ls180.v:3126$74_Y
end
- attribute \src "ls180.v:3191.8-3191.142"
- cell $ne $ne$ls180.v:3191$93
+ attribute \src "ls180.v:3187.8-3187.142"
+ cell $ne $ne$ls180.v:3187$93
parameter \A_SIGNED 0
parameter \A_WIDTH 13
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr [21:9]
connect \B \main_sdram_bankmachine0_cmd_buffer_source_payload_addr [21:9]
- connect \Y $ne$ls180.v:3191$93_Y
+ connect \Y $ne$ls180.v:3187$93_Y
end
- attribute \src "ls180.v:3223.75-3223.133"
- cell $ne $ne$ls180.v:3223$100
+ attribute \src "ls180.v:3219.75-3219.133"
+ cell $ne $ne$ls180.v:3219$100
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_level
connect \B 4'1000
- connect \Y $ne$ls180.v:3223$100_Y
+ connect \Y $ne$ls180.v:3219$100_Y
end
- attribute \src "ls180.v:3224.75-3224.133"
- cell $ne $ne$ls180.v:3224$101
+ attribute \src "ls180.v:3220.75-3220.133"
+ cell $ne $ne$ls180.v:3220$101
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_level
connect \B 1'0
- connect \Y $ne$ls180.v:3224$101_Y
+ connect \Y $ne$ls180.v:3220$101_Y
end
- attribute \src "ls180.v:3348.8-3348.142"
- cell $ne $ne$ls180.v:3348$123
+ attribute \src "ls180.v:3344.8-3344.142"
+ cell $ne $ne$ls180.v:3344$123
parameter \A_SIGNED 0
parameter \A_WIDTH 13
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr [21:9]
connect \B \main_sdram_bankmachine1_cmd_buffer_source_payload_addr [21:9]
- connect \Y $ne$ls180.v:3348$123_Y
+ connect \Y $ne$ls180.v:3344$123_Y
end
- attribute \src "ls180.v:3380.75-3380.133"
- cell $ne $ne$ls180.v:3380$130
+ attribute \src "ls180.v:3376.75-3376.133"
+ cell $ne $ne$ls180.v:3376$130
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_level
connect \B 4'1000
- connect \Y $ne$ls180.v:3380$130_Y
+ connect \Y $ne$ls180.v:3376$130_Y
end
- attribute \src "ls180.v:3381.75-3381.133"
- cell $ne $ne$ls180.v:3381$131
+ attribute \src "ls180.v:3377.75-3377.133"
+ cell $ne $ne$ls180.v:3377$131
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_level
connect \B 1'0
- connect \Y $ne$ls180.v:3381$131_Y
+ connect \Y $ne$ls180.v:3377$131_Y
end
- attribute \src "ls180.v:3505.8-3505.142"
- cell $ne $ne$ls180.v:3505$153
+ attribute \src "ls180.v:3501.8-3501.142"
+ cell $ne $ne$ls180.v:3501$153
parameter \A_SIGNED 0
parameter \A_WIDTH 13
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr [21:9]
connect \B \main_sdram_bankmachine2_cmd_buffer_source_payload_addr [21:9]
- connect \Y $ne$ls180.v:3505$153_Y
+ connect \Y $ne$ls180.v:3501$153_Y
end
- attribute \src "ls180.v:3537.75-3537.133"
- cell $ne $ne$ls180.v:3537$160
+ attribute \src "ls180.v:3533.75-3533.133"
+ cell $ne $ne$ls180.v:3533$160
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_level
connect \B 4'1000
- connect \Y $ne$ls180.v:3537$160_Y
+ connect \Y $ne$ls180.v:3533$160_Y
end
- attribute \src "ls180.v:3538.75-3538.133"
- cell $ne $ne$ls180.v:3538$161
+ attribute \src "ls180.v:3534.75-3534.133"
+ cell $ne $ne$ls180.v:3534$161
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_level
connect \B 1'0
- connect \Y $ne$ls180.v:3538$161_Y
+ connect \Y $ne$ls180.v:3534$161_Y
end
- attribute \src "ls180.v:3662.8-3662.142"
- cell $ne $ne$ls180.v:3662$183
+ attribute \src "ls180.v:3658.8-3658.142"
+ cell $ne $ne$ls180.v:3658$183
parameter \A_SIGNED 0
parameter \A_WIDTH 13
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr [21:9]
connect \B \main_sdram_bankmachine3_cmd_buffer_source_payload_addr [21:9]
- connect \Y $ne$ls180.v:3662$183_Y
+ connect \Y $ne$ls180.v:3658$183_Y
end
- attribute \src "ls180.v:3694.75-3694.133"
- cell $ne $ne$ls180.v:3694$190
+ attribute \src "ls180.v:3690.75-3690.133"
+ cell $ne $ne$ls180.v:3690$190
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_level
connect \B 4'1000
- connect \Y $ne$ls180.v:3694$190_Y
+ connect \Y $ne$ls180.v:3690$190_Y
end
- attribute \src "ls180.v:3695.75-3695.133"
- cell $ne $ne$ls180.v:3695$191
+ attribute \src "ls180.v:3691.75-3691.133"
+ cell $ne $ne$ls180.v:3691$191
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_level
connect \B 1'0
- connect \Y $ne$ls180.v:3695$191_Y
+ connect \Y $ne$ls180.v:3691$191_Y
end
- attribute \src "ls180.v:4187.47-4187.80"
- cell $ne $ne$ls180.v:4187$589
+ attribute \src "ls180.v:4183.47-4183.80"
+ cell $ne $ne$ls180.v:4183$589
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_uart_tx_fifo_level0
connect \B 5'10000
- connect \Y $ne$ls180.v:4187$589_Y
+ connect \Y $ne$ls180.v:4183$589_Y
end
- attribute \src "ls180.v:4188.47-4188.79"
- cell $ne $ne$ls180.v:4188$590
+ attribute \src "ls180.v:4184.47-4184.79"
+ cell $ne $ne$ls180.v:4184$590
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_uart_tx_fifo_level0
connect \B 1'0
- connect \Y $ne$ls180.v:4188$590_Y
+ connect \Y $ne$ls180.v:4184$590_Y
end
- attribute \src "ls180.v:4217.47-4217.80"
- cell $ne $ne$ls180.v:4217$600
+ attribute \src "ls180.v:4213.47-4213.80"
+ cell $ne $ne$ls180.v:4213$600
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_uart_rx_fifo_level0
connect \B 5'10000
- connect \Y $ne$ls180.v:4217$600_Y
+ connect \Y $ne$ls180.v:4213$600_Y
end
- attribute \src "ls180.v:4218.47-4218.79"
- cell $ne $ne$ls180.v:4218$601
+ attribute \src "ls180.v:4214.47-4214.79"
+ cell $ne $ne$ls180.v:4214$601
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_uart_rx_fifo_level0
connect \B 1'0
- connect \Y $ne$ls180.v:4218$601_Y
+ connect \Y $ne$ls180.v:4214$601_Y
end
- attribute \src "ls180.v:4687.32-4687.89"
- cell $ne $ne$ls180.v:4687$681
+ attribute \src "ls180.v:4683.32-4683.89"
+ cell $ne $ne$ls180.v:4683$681
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdphy_dataw_crcr_source_source_payload_data0
connect \B 3'101
- connect \Y $ne$ls180.v:4687$681_Y
+ connect \Y $ne$ls180.v:4683$681_Y
end
- attribute \src "ls180.v:5334.10-5334.56"
- cell $ne $ne$ls180.v:5334$978
+ attribute \src "ls180.v:5330.10-5330.56"
+ cell $ne $ne$ls180.v:5330$978
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdphy_datar_source_payload_status
connect \B 2'10
- connect \Y $ne$ls180.v:5334$978_Y
+ connect \Y $ne$ls180.v:5330$978_Y
end
- attribute \src "ls180.v:5439.51-5439.87"
- cell $ne $ne$ls180.v:5439$992
+ attribute \src "ls180.v:5435.51-5435.87"
+ cell $ne $ne$ls180.v:5435$992
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdblock2mem_fifo_level
connect \B 6'100000
- connect \Y $ne$ls180.v:5439$992_Y
+ connect \Y $ne$ls180.v:5435$992_Y
end
- attribute \src "ls180.v:5440.51-5440.86"
- cell $ne $ne$ls180.v:5440$993
+ attribute \src "ls180.v:5436.51-5436.86"
+ cell $ne $ne$ls180.v:5436$993
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdblock2mem_fifo_level
connect \B 1'0
- connect \Y $ne$ls180.v:5440$993_Y
+ connect \Y $ne$ls180.v:5436$993_Y
end
- attribute \src "ls180.v:5647.51-5647.87"
- cell $ne $ne$ls180.v:5647$1023
+ attribute \src "ls180.v:5643.51-5643.87"
+ cell $ne $ne$ls180.v:5643$1023
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdmem2block_fifo_level
connect \B 6'100000
- connect \Y $ne$ls180.v:5647$1023_Y
+ connect \Y $ne$ls180.v:5643$1023_Y
end
- attribute \src "ls180.v:5648.51-5648.86"
- cell $ne $ne$ls180.v:5648$1024
+ attribute \src "ls180.v:5644.51-5644.86"
+ cell $ne $ne$ls180.v:5644$1024
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdmem2block_fifo_level
connect \B 1'0
- connect \Y $ne$ls180.v:5648$1024_Y
+ connect \Y $ne$ls180.v:5644$1024_Y
end
- attribute \src "ls180.v:5679.79-5679.119"
- cell $ne $ne$ls180.v:5679$1027
+ attribute \src "ls180.v:5675.79-5675.119"
+ cell $ne $ne$ls180.v:5675$1027
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_libresocsim_wishbone_sel
connect \B 1'0
- connect \Y $ne$ls180.v:5679$1027_Y
+ connect \Y $ne$ls180.v:5675$1027_Y
end
- attribute \src "ls180.v:7489.7-7489.52"
- cell $ne $ne$ls180.v:7489$2402
+ attribute \src "ls180.v:7485.7-7485.52"
+ cell $ne $ne$ls180.v:7485$2402
parameter \A_SIGNED 0
parameter \A_WIDTH 32
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_libresocsim_bus_errors
connect \B 32'11111111111111111111111111111111
- connect \Y $ne$ls180.v:7489$2402_Y
+ connect \Y $ne$ls180.v:7485$2402_Y
end
- attribute \src "ls180.v:7539.9-7539.43"
- cell $ne $ne$ls180.v:7539$2416
+ attribute \src "ls180.v:7535.9-7535.43"
+ cell $ne $ne$ls180.v:7535$2416
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_sequencer_count
connect \B 1'0
- connect \Y $ne$ls180.v:7539$2416_Y
+ connect \Y $ne$ls180.v:7535$2416_Y
end
- attribute \src "ls180.v:7575.8-7575.44"
- cell $ne $ne$ls180.v:7575$2423
+ attribute \src "ls180.v:7571.8-7571.44"
+ cell $ne $ne$ls180.v:7571$2423
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_sequencer_counter
connect \B 1'0
- connect \Y $ne$ls180.v:7575$2423_Y
+ connect \Y $ne$ls180.v:7571$2423_Y
end
- attribute \src "ls180.v:8513.9-8513.47"
- cell $ne $ne$ls180.v:8513$2638
+ attribute \src "ls180.v:8509.9-8509.47"
+ cell $ne $ne$ls180.v:8509$2638
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_checker_cnt
connect \B 4'1010
- connect \Y $ne$ls180.v:8513$2638_Y
+ connect \Y $ne$ls180.v:8509$2638_Y
end
- attribute \src "ls180.v:2777.45-2777.80"
- cell $not $not$ls180.v:2777$14
+ attribute \src "ls180.v:2773.45-2773.80"
+ cell $not $not$ls180.v:2773$14
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_libresocsim_libresoc_ibus_cyc
- connect \Y $not$ls180.v:2777$14_Y
+ connect \Y $not$ls180.v:2773$14_Y
end
- attribute \src "ls180.v:2816.61-2816.94"
- cell $not $not$ls180.v:2816$19
+ attribute \src "ls180.v:2812.61-2812.94"
+ cell $not $not$ls180.v:2812$19
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_libresocsim_converter0_skip
- connect \Y $not$ls180.v:2816$19_Y
+ connect \Y $not$ls180.v:2812$19_Y
end
- attribute \src "ls180.v:2817.61-2817.94"
- cell $not $not$ls180.v:2817$20
+ attribute \src "ls180.v:2813.61-2813.94"
+ cell $not $not$ls180.v:2813$20
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_libresocsim_converter0_skip
- connect \Y $not$ls180.v:2817$20_Y
+ connect \Y $not$ls180.v:2813$20_Y
end
- attribute \src "ls180.v:2837.45-2837.80"
- cell $not $not$ls180.v:2837$25
+ attribute \src "ls180.v:2833.45-2833.80"
+ cell $not $not$ls180.v:2833$25
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_libresocsim_libresoc_dbus_cyc
- connect \Y $not$ls180.v:2837$25_Y
+ connect \Y $not$ls180.v:2833$25_Y
end
- attribute \src "ls180.v:2876.61-2876.94"
- cell $not $not$ls180.v:2876$30
+ attribute \src "ls180.v:2872.61-2872.94"
+ cell $not $not$ls180.v:2872$30
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_libresocsim_converter1_skip
- connect \Y $not$ls180.v:2876$30_Y
+ connect \Y $not$ls180.v:2872$30_Y
end
- attribute \src "ls180.v:2877.61-2877.94"
- cell $not $not$ls180.v:2877$31
+ attribute \src "ls180.v:2873.61-2873.94"
+ cell $not $not$ls180.v:2873$31
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_libresocsim_converter1_skip
- connect \Y $not$ls180.v:2877$31_Y
+ connect \Y $not$ls180.v:2873$31_Y
end
- attribute \src "ls180.v:2897.45-2897.83"
- cell $not $not$ls180.v:2897$36
+ attribute \src "ls180.v:2893.45-2893.83"
+ cell $not $not$ls180.v:2893$36
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_libresocsim_libresoc_jtag_wb_cyc
- connect \Y $not$ls180.v:2897$36_Y
+ connect \Y $not$ls180.v:2893$36_Y
end
- attribute \src "ls180.v:2936.61-2936.94"
- cell $not $not$ls180.v:2936$41
+ attribute \src "ls180.v:2932.61-2932.94"
+ cell $not $not$ls180.v:2932$41
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_libresocsim_converter2_skip
- connect \Y $not$ls180.v:2936$41_Y
+ connect \Y $not$ls180.v:2932$41_Y
end
- attribute \src "ls180.v:2937.61-2937.94"
- cell $not $not$ls180.v:2937$42
+ attribute \src "ls180.v:2933.61-2933.94"
+ cell $not $not$ls180.v:2933$42
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_libresocsim_converter2_skip
- connect \Y $not$ls180.v:2937$42_Y
+ connect \Y $not$ls180.v:2933$42_Y
end
- attribute \src "ls180.v:3079.34-3079.64"
- cell $not $not$ls180.v:3079$66
+ attribute \src "ls180.v:3075.34-3075.64"
+ cell $not $not$ls180.v:3075$66
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_command_storage [0]
- connect \Y $not$ls180.v:3079$66_Y
+ connect \Y $not$ls180.v:3075$66_Y
end
- attribute \src "ls180.v:3080.31-3080.61"
- cell $not $not$ls180.v:3080$67
+ attribute \src "ls180.v:3076.31-3076.61"
+ cell $not $not$ls180.v:3076$67
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_command_storage [1]
- connect \Y $not$ls180.v:3080$67_Y
+ connect \Y $not$ls180.v:3076$67_Y
end
- attribute \src "ls180.v:3081.32-3081.62"
- cell $not $not$ls180.v:3081$68
+ attribute \src "ls180.v:3077.32-3077.62"
+ cell $not $not$ls180.v:3077$68
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_command_storage [2]
- connect \Y $not$ls180.v:3081$68_Y
+ connect \Y $not$ls180.v:3077$68_Y
end
- attribute \src "ls180.v:3082.32-3082.62"
- cell $not $not$ls180.v:3082$69
+ attribute \src "ls180.v:3078.32-3078.62"
+ cell $not $not$ls180.v:3078$69
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_command_storage [3]
- connect \Y $not$ls180.v:3082$69_Y
+ connect \Y $not$ls180.v:3078$69_Y
end
- attribute \src "ls180.v:3124.33-3124.56"
- cell $not $not$ls180.v:3124$72
+ attribute \src "ls180.v:3120.33-3120.56"
+ cell $not $not$ls180.v:3120$72
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_timer_done0
- connect \Y $not$ls180.v:3124$72_Y
+ connect \Y $not$ls180.v:3120$72_Y
end
- attribute \src "ls180.v:3225.58-3225.106"
- cell $not $not$ls180.v:3225$102
+ attribute \src "ls180.v:3221.58-3221.106"
+ cell $not $not$ls180.v:3221$102
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine0_cmd_buffer_source_valid
- connect \Y $not$ls180.v:3225$102_Y
+ connect \Y $not$ls180.v:3221$102_Y
end
- attribute \src "ls180.v:3279.9-3279.45"
- cell $not $not$ls180.v:3279$107
+ attribute \src "ls180.v:3275.9-3275.45"
+ cell $not $not$ls180.v:3275$107
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine0_refresh_req
- connect \Y $not$ls180.v:3279$107_Y
+ connect \Y $not$ls180.v:3275$107_Y
end
- attribute \src "ls180.v:3382.58-3382.106"
- cell $not $not$ls180.v:3382$132
+ attribute \src "ls180.v:3378.58-3378.106"
+ cell $not $not$ls180.v:3378$132
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine1_cmd_buffer_source_valid
- connect \Y $not$ls180.v:3382$132_Y
+ connect \Y $not$ls180.v:3378$132_Y
end
- attribute \src "ls180.v:3436.9-3436.45"
- cell $not $not$ls180.v:3436$137
+ attribute \src "ls180.v:3432.9-3432.45"
+ cell $not $not$ls180.v:3432$137
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine1_refresh_req
- connect \Y $not$ls180.v:3436$137_Y
+ connect \Y $not$ls180.v:3432$137_Y
end
- attribute \src "ls180.v:3539.58-3539.106"
- cell $not $not$ls180.v:3539$162
+ attribute \src "ls180.v:3535.58-3535.106"
+ cell $not $not$ls180.v:3535$162
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine2_cmd_buffer_source_valid
- connect \Y $not$ls180.v:3539$162_Y
+ connect \Y $not$ls180.v:3535$162_Y
end
- attribute \src "ls180.v:3593.9-3593.45"
- cell $not $not$ls180.v:3593$167
+ attribute \src "ls180.v:3589.9-3589.45"
+ cell $not $not$ls180.v:3589$167
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine2_refresh_req
- connect \Y $not$ls180.v:3593$167_Y
+ connect \Y $not$ls180.v:3589$167_Y
end
- attribute \src "ls180.v:3696.58-3696.106"
- cell $not $not$ls180.v:3696$192
+ attribute \src "ls180.v:3692.58-3692.106"
+ cell $not $not$ls180.v:3692$192
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine3_cmd_buffer_source_valid
- connect \Y $not$ls180.v:3696$192_Y
+ connect \Y $not$ls180.v:3692$192_Y
end
- attribute \src "ls180.v:3750.9-3750.45"
- cell $not $not$ls180.v:3750$197
+ attribute \src "ls180.v:3746.9-3746.45"
+ cell $not $not$ls180.v:3746$197
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine3_refresh_req
- connect \Y $not$ls180.v:3750$197_Y
+ connect \Y $not$ls180.v:3746$197_Y
end
- attribute \src "ls180.v:3792.149-3792.187"
- cell $not $not$ls180.v:3792$200
+ attribute \src "ls180.v:3788.149-3788.187"
+ cell $not $not$ls180.v:3788$200
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_choose_req_cmd_payload_cas
- connect \Y $not$ls180.v:3792$200_Y
+ connect \Y $not$ls180.v:3788$200_Y
end
- attribute \src "ls180.v:3792.193-3792.230"
- cell $not $not$ls180.v:3792$202
+ attribute \src "ls180.v:3788.193-3788.230"
+ cell $not $not$ls180.v:3788$202
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_choose_req_cmd_payload_we
- connect \Y $not$ls180.v:3792$202_Y
+ connect \Y $not$ls180.v:3788$202_Y
end
- attribute \src "ls180.v:3793.149-3793.187"
- cell $not $not$ls180.v:3793$206
+ attribute \src "ls180.v:3789.149-3789.187"
+ cell $not $not$ls180.v:3789$206
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_choose_req_cmd_payload_cas
- connect \Y $not$ls180.v:3793$206_Y
+ connect \Y $not$ls180.v:3789$206_Y
end
- attribute \src "ls180.v:3793.193-3793.230"
- cell $not $not$ls180.v:3793$208
+ attribute \src "ls180.v:3789.193-3789.230"
+ cell $not $not$ls180.v:3789$208
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_choose_req_cmd_payload_we
- connect \Y $not$ls180.v:3793$208_Y
+ connect \Y $not$ls180.v:3789$208_Y
end
- attribute \src "ls180.v:3809.43-3809.73"
- cell $not $not$ls180.v:3809$236
+ attribute \src "ls180.v:3805.43-3805.73"
+ cell $not $not$ls180.v:3805$236
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \Y_WIDTH 2
connect \A \main_sdram_interface_wdata_we
- connect \Y $not$ls180.v:3809$236_Y
+ connect \Y $not$ls180.v:3805$236_Y
end
- attribute \src "ls180.v:3812.205-3812.245"
- cell $not $not$ls180.v:3812$239
+ attribute \src "ls180.v:3808.205-3808.245"
+ cell $not $not$ls180.v:3808$239
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine0_cmd_payload_cas
- connect \Y $not$ls180.v:3812$239_Y
+ connect \Y $not$ls180.v:3808$239_Y
end
- attribute \src "ls180.v:3812.251-3812.290"
- cell $not $not$ls180.v:3812$241
+ attribute \src "ls180.v:3808.251-3808.290"
+ cell $not $not$ls180.v:3808$241
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine0_cmd_payload_we
- connect \Y $not$ls180.v:3812$241_Y
+ connect \Y $not$ls180.v:3808$241_Y
end
- attribute \src "ls180.v:3812.159-3812.292"
- cell $not $not$ls180.v:3812$243
+ attribute \src "ls180.v:3808.159-3808.292"
+ cell $not $not$ls180.v:3808$243
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3812$242_Y
- connect \Y $not$ls180.v:3812$243_Y
+ connect \A $and$ls180.v:3808$242_Y
+ connect \Y $not$ls180.v:3808$243_Y
end
- attribute \src "ls180.v:3813.205-3813.245"
- cell $not $not$ls180.v:3813$252
+ attribute \src "ls180.v:3809.205-3809.245"
+ cell $not $not$ls180.v:3809$252
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine1_cmd_payload_cas
- connect \Y $not$ls180.v:3813$252_Y
+ connect \Y $not$ls180.v:3809$252_Y
end
- attribute \src "ls180.v:3813.251-3813.290"
- cell $not $not$ls180.v:3813$254
+ attribute \src "ls180.v:3809.251-3809.290"
+ cell $not $not$ls180.v:3809$254
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine1_cmd_payload_we
- connect \Y $not$ls180.v:3813$254_Y
+ connect \Y $not$ls180.v:3809$254_Y
end
- attribute \src "ls180.v:3813.159-3813.292"
- cell $not $not$ls180.v:3813$256
+ attribute \src "ls180.v:3809.159-3809.292"
+ cell $not $not$ls180.v:3809$256
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3813$255_Y
- connect \Y $not$ls180.v:3813$256_Y
+ connect \A $and$ls180.v:3809$255_Y
+ connect \Y $not$ls180.v:3809$256_Y
end
- attribute \src "ls180.v:3814.205-3814.245"
- cell $not $not$ls180.v:3814$265
+ attribute \src "ls180.v:3810.205-3810.245"
+ cell $not $not$ls180.v:3810$265
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine2_cmd_payload_cas
- connect \Y $not$ls180.v:3814$265_Y
+ connect \Y $not$ls180.v:3810$265_Y
end
- attribute \src "ls180.v:3814.251-3814.290"
- cell $not $not$ls180.v:3814$267
+ attribute \src "ls180.v:3810.251-3810.290"
+ cell $not $not$ls180.v:3810$267
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine2_cmd_payload_we
- connect \Y $not$ls180.v:3814$267_Y
+ connect \Y $not$ls180.v:3810$267_Y
end
- attribute \src "ls180.v:3814.159-3814.292"
- cell $not $not$ls180.v:3814$269
+ attribute \src "ls180.v:3810.159-3810.292"
+ cell $not $not$ls180.v:3810$269
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3814$268_Y
- connect \Y $not$ls180.v:3814$269_Y
+ connect \A $and$ls180.v:3810$268_Y
+ connect \Y $not$ls180.v:3810$269_Y
end
- attribute \src "ls180.v:3815.205-3815.245"
- cell $not $not$ls180.v:3815$278
+ attribute \src "ls180.v:3811.205-3811.245"
+ cell $not $not$ls180.v:3811$278
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine3_cmd_payload_cas
- connect \Y $not$ls180.v:3815$278_Y
+ connect \Y $not$ls180.v:3811$278_Y
end
- attribute \src "ls180.v:3815.251-3815.290"
- cell $not $not$ls180.v:3815$280
+ attribute \src "ls180.v:3811.251-3811.290"
+ cell $not $not$ls180.v:3811$280
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine3_cmd_payload_we
- connect \Y $not$ls180.v:3815$280_Y
+ connect \Y $not$ls180.v:3811$280_Y
end
- attribute \src "ls180.v:3815.159-3815.292"
- cell $not $not$ls180.v:3815$282
+ attribute \src "ls180.v:3811.159-3811.292"
+ cell $not $not$ls180.v:3811$282
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3815$281_Y
- connect \Y $not$ls180.v:3815$282_Y
+ connect \A $and$ls180.v:3811$281_Y
+ connect \Y $not$ls180.v:3811$282_Y
end
- attribute \src "ls180.v:3842.71-3842.103"
- cell $not $not$ls180.v:3842$293
+ attribute \src "ls180.v:3838.71-3838.103"
+ cell $not $not$ls180.v:3838$293
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_choose_cmd_cmd_valid
- connect \Y $not$ls180.v:3842$293_Y
+ connect \Y $not$ls180.v:3838$293_Y
end
- attribute \src "ls180.v:3845.205-3845.245"
- cell $not $not$ls180.v:3845$297
+ attribute \src "ls180.v:3841.205-3841.245"
+ cell $not $not$ls180.v:3841$297
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine0_cmd_payload_cas
- connect \Y $not$ls180.v:3845$297_Y
+ connect \Y $not$ls180.v:3841$297_Y
end
- attribute \src "ls180.v:3845.251-3845.290"
- cell $not $not$ls180.v:3845$299
+ attribute \src "ls180.v:3841.251-3841.290"
+ cell $not $not$ls180.v:3841$299
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine0_cmd_payload_we
- connect \Y $not$ls180.v:3845$299_Y
+ connect \Y $not$ls180.v:3841$299_Y
end
- attribute \src "ls180.v:3845.159-3845.292"
- cell $not $not$ls180.v:3845$301
+ attribute \src "ls180.v:3841.159-3841.292"
+ cell $not $not$ls180.v:3841$301
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3845$300_Y
- connect \Y $not$ls180.v:3845$301_Y
+ connect \A $and$ls180.v:3841$300_Y
+ connect \Y $not$ls180.v:3841$301_Y
end
- attribute \src "ls180.v:3846.205-3846.245"
- cell $not $not$ls180.v:3846$310
+ attribute \src "ls180.v:3842.205-3842.245"
+ cell $not $not$ls180.v:3842$310
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine1_cmd_payload_cas
- connect \Y $not$ls180.v:3846$310_Y
+ connect \Y $not$ls180.v:3842$310_Y
end
- attribute \src "ls180.v:3846.251-3846.290"
- cell $not $not$ls180.v:3846$312
+ attribute \src "ls180.v:3842.251-3842.290"
+ cell $not $not$ls180.v:3842$312
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine1_cmd_payload_we
- connect \Y $not$ls180.v:3846$312_Y
+ connect \Y $not$ls180.v:3842$312_Y
end
- attribute \src "ls180.v:3846.159-3846.292"
- cell $not $not$ls180.v:3846$314
+ attribute \src "ls180.v:3842.159-3842.292"
+ cell $not $not$ls180.v:3842$314
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3846$313_Y
- connect \Y $not$ls180.v:3846$314_Y
+ connect \A $and$ls180.v:3842$313_Y
+ connect \Y $not$ls180.v:3842$314_Y
end
- attribute \src "ls180.v:3847.205-3847.245"
- cell $not $not$ls180.v:3847$323
+ attribute \src "ls180.v:3843.205-3843.245"
+ cell $not $not$ls180.v:3843$323
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine2_cmd_payload_cas
- connect \Y $not$ls180.v:3847$323_Y
+ connect \Y $not$ls180.v:3843$323_Y
end
- attribute \src "ls180.v:3847.251-3847.290"
- cell $not $not$ls180.v:3847$325
+ attribute \src "ls180.v:3843.251-3843.290"
+ cell $not $not$ls180.v:3843$325
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine2_cmd_payload_we
- connect \Y $not$ls180.v:3847$325_Y
+ connect \Y $not$ls180.v:3843$325_Y
end
- attribute \src "ls180.v:3847.159-3847.292"
- cell $not $not$ls180.v:3847$327
+ attribute \src "ls180.v:3843.159-3843.292"
+ cell $not $not$ls180.v:3843$327
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3847$326_Y
- connect \Y $not$ls180.v:3847$327_Y
+ connect \A $and$ls180.v:3843$326_Y
+ connect \Y $not$ls180.v:3843$327_Y
end
- attribute \src "ls180.v:3848.205-3848.245"
- cell $not $not$ls180.v:3848$336
+ attribute \src "ls180.v:3844.205-3844.245"
+ cell $not $not$ls180.v:3844$336
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine3_cmd_payload_cas
- connect \Y $not$ls180.v:3848$336_Y
+ connect \Y $not$ls180.v:3844$336_Y
end
- attribute \src "ls180.v:3848.251-3848.290"
- cell $not $not$ls180.v:3848$338
+ attribute \src "ls180.v:3844.251-3844.290"
+ cell $not $not$ls180.v:3844$338
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine3_cmd_payload_we
- connect \Y $not$ls180.v:3848$338_Y
+ connect \Y $not$ls180.v:3844$338_Y
end
- attribute \src "ls180.v:3848.159-3848.292"
- cell $not $not$ls180.v:3848$340
+ attribute \src "ls180.v:3844.159-3844.292"
+ cell $not $not$ls180.v:3844$340
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3848$339_Y
- connect \Y $not$ls180.v:3848$340_Y
+ connect \A $and$ls180.v:3844$339_Y
+ connect \Y $not$ls180.v:3844$340_Y
end
- attribute \src "ls180.v:3911.71-3911.103"
- cell $not $not$ls180.v:3911$379
+ attribute \src "ls180.v:3907.71-3907.103"
+ cell $not $not$ls180.v:3907$379
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_choose_req_cmd_valid
- connect \Y $not$ls180.v:3911$379_Y
+ connect \Y $not$ls180.v:3907$379_Y
end
- attribute \src "ls180.v:3932.112-3932.150"
- cell $not $not$ls180.v:3932$382
+ attribute \src "ls180.v:3928.112-3928.150"
+ cell $not $not$ls180.v:3928$382
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_choose_req_cmd_payload_cas
- connect \Y $not$ls180.v:3932$382_Y
+ connect \Y $not$ls180.v:3928$382_Y
end
- attribute \src "ls180.v:3932.156-3932.193"
- cell $not $not$ls180.v:3932$384
+ attribute \src "ls180.v:3928.156-3928.193"
+ cell $not $not$ls180.v:3928$384
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_choose_req_cmd_payload_we
- connect \Y $not$ls180.v:3932$384_Y
+ connect \Y $not$ls180.v:3928$384_Y
end
- attribute \src "ls180.v:3932.68-3932.195"
- cell $not $not$ls180.v:3932$386
+ attribute \src "ls180.v:3928.68-3928.195"
+ cell $not $not$ls180.v:3928$386
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3932$385_Y
- connect \Y $not$ls180.v:3932$386_Y
+ connect \A $and$ls180.v:3928$385_Y
+ connect \Y $not$ls180.v:3928$386_Y
end
- attribute \src "ls180.v:3940.11-3940.38"
- cell $not $not$ls180.v:3940$389
+ attribute \src "ls180.v:3936.11-3936.38"
+ cell $not $not$ls180.v:3936$389
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_write_available
- connect \Y $not$ls180.v:3940$389_Y
+ connect \Y $not$ls180.v:3936$389_Y
end
- attribute \src "ls180.v:3970.112-3970.150"
- cell $not $not$ls180.v:3970$391
+ attribute \src "ls180.v:3966.112-3966.150"
+ cell $not $not$ls180.v:3966$391
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_choose_req_cmd_payload_cas
- connect \Y $not$ls180.v:3970$391_Y
+ connect \Y $not$ls180.v:3966$391_Y
end
- attribute \src "ls180.v:3970.156-3970.193"
- cell $not $not$ls180.v:3970$393
+ attribute \src "ls180.v:3966.156-3966.193"
+ cell $not $not$ls180.v:3966$393
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_choose_req_cmd_payload_we
- connect \Y $not$ls180.v:3970$393_Y
+ connect \Y $not$ls180.v:3966$393_Y
end
- attribute \src "ls180.v:3970.68-3970.195"
- cell $not $not$ls180.v:3970$395
+ attribute \src "ls180.v:3966.68-3966.195"
+ cell $not $not$ls180.v:3966$395
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3970$394_Y
- connect \Y $not$ls180.v:3970$395_Y
+ connect \A $and$ls180.v:3966$394_Y
+ connect \Y $not$ls180.v:3966$395_Y
end
- attribute \src "ls180.v:3978.11-3978.37"
- cell $not $not$ls180.v:3978$398
+ attribute \src "ls180.v:3974.11-3974.37"
+ cell $not $not$ls180.v:3974$398
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_read_available
- connect \Y $not$ls180.v:3978$398_Y
+ connect \Y $not$ls180.v:3974$398_Y
end
- attribute \src "ls180.v:3988.87-3988.331"
- cell $not $not$ls180.v:3988$410
+ attribute \src "ls180.v:3984.87-3984.331"
+ cell $not $not$ls180.v:3984$410
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:3988$409_Y
- connect \Y $not$ls180.v:3988$410_Y
+ connect \A $or$ls180.v:3984$409_Y
+ connect \Y $not$ls180.v:3984$410_Y
end
- attribute \src "ls180.v:3989.35-3989.68"
- cell $not $not$ls180.v:3989$413
+ attribute \src "ls180.v:3985.35-3985.68"
+ cell $not $not$ls180.v:3985$413
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_interface_bank0_valid
- connect \Y $not$ls180.v:3989$413_Y
+ connect \Y $not$ls180.v:3985$413_Y
end
- attribute \src "ls180.v:3989.73-3989.105"
- cell $not $not$ls180.v:3989$414
+ attribute \src "ls180.v:3985.73-3985.105"
+ cell $not $not$ls180.v:3985$414
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_interface_bank0_lock
- connect \Y $not$ls180.v:3989$414_Y
+ connect \Y $not$ls180.v:3985$414_Y
end
- attribute \src "ls180.v:3993.87-3993.331"
- cell $not $not$ls180.v:3993$426
+ attribute \src "ls180.v:3989.87-3989.331"
+ cell $not $not$ls180.v:3989$426
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:3993$425_Y
- connect \Y $not$ls180.v:3993$426_Y
+ connect \A $or$ls180.v:3989$425_Y
+ connect \Y $not$ls180.v:3989$426_Y
end
- attribute \src "ls180.v:3994.35-3994.68"
- cell $not $not$ls180.v:3994$429
+ attribute \src "ls180.v:3990.35-3990.68"
+ cell $not $not$ls180.v:3990$429
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_interface_bank1_valid
- connect \Y $not$ls180.v:3994$429_Y
+ connect \Y $not$ls180.v:3990$429_Y
end
- attribute \src "ls180.v:3994.73-3994.105"
- cell $not $not$ls180.v:3994$430
+ attribute \src "ls180.v:3990.73-3990.105"
+ cell $not $not$ls180.v:3990$430
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_interface_bank1_lock
- connect \Y $not$ls180.v:3994$430_Y
+ connect \Y $not$ls180.v:3990$430_Y
end
- attribute \src "ls180.v:3998.87-3998.331"
- cell $not $not$ls180.v:3998$442
+ attribute \src "ls180.v:3994.87-3994.331"
+ cell $not $not$ls180.v:3994$442
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:3998$441_Y
- connect \Y $not$ls180.v:3998$442_Y
+ connect \A $or$ls180.v:3994$441_Y
+ connect \Y $not$ls180.v:3994$442_Y
end
- attribute \src "ls180.v:3999.35-3999.68"
- cell $not $not$ls180.v:3999$445
+ attribute \src "ls180.v:3995.35-3995.68"
+ cell $not $not$ls180.v:3995$445
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_interface_bank2_valid
- connect \Y $not$ls180.v:3999$445_Y
+ connect \Y $not$ls180.v:3995$445_Y
end
- attribute \src "ls180.v:3999.73-3999.105"
- cell $not $not$ls180.v:3999$446
+ attribute \src "ls180.v:3995.73-3995.105"
+ cell $not $not$ls180.v:3995$446
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_interface_bank2_lock
- connect \Y $not$ls180.v:3999$446_Y
+ connect \Y $not$ls180.v:3995$446_Y
end
- attribute \src "ls180.v:4003.87-4003.331"
- cell $not $not$ls180.v:4003$458
+ attribute \src "ls180.v:3999.87-3999.331"
+ cell $not $not$ls180.v:3999$458
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:4003$457_Y
- connect \Y $not$ls180.v:4003$458_Y
+ connect \A $or$ls180.v:3999$457_Y
+ connect \Y $not$ls180.v:3999$458_Y
end
- attribute \src "ls180.v:4004.35-4004.68"
- cell $not $not$ls180.v:4004$461
+ attribute \src "ls180.v:4000.35-4000.68"
+ cell $not $not$ls180.v:4000$461
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_interface_bank3_valid
- connect \Y $not$ls180.v:4004$461_Y
+ connect \Y $not$ls180.v:4000$461_Y
end
- attribute \src "ls180.v:4004.73-4004.105"
- cell $not $not$ls180.v:4004$462
+ attribute \src "ls180.v:4000.73-4000.105"
+ cell $not $not$ls180.v:4000$462
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_interface_bank3_lock
- connect \Y $not$ls180.v:4004$462_Y
+ connect \Y $not$ls180.v:4000$462_Y
end
- attribute \src "ls180.v:4008.128-4008.372"
- cell $not $not$ls180.v:4008$475
+ attribute \src "ls180.v:4004.128-4004.372"
+ cell $not $not$ls180.v:4004$475
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:4008$474_Y
- connect \Y $not$ls180.v:4008$475_Y
+ connect \A $or$ls180.v:4004$474_Y
+ connect \Y $not$ls180.v:4004$475_Y
end
- attribute \src "ls180.v:4008.502-4008.746"
- cell $not $not$ls180.v:4008$491
+ attribute \src "ls180.v:4004.502-4004.746"
+ cell $not $not$ls180.v:4004$491
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:4008$490_Y
- connect \Y $not$ls180.v:4008$491_Y
+ connect \A $or$ls180.v:4004$490_Y
+ connect \Y $not$ls180.v:4004$491_Y
end
- attribute \src "ls180.v:4008.876-4008.1120"
- cell $not $not$ls180.v:4008$507
+ attribute \src "ls180.v:4004.876-4004.1120"
+ cell $not $not$ls180.v:4004$507
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:4008$506_Y
- connect \Y $not$ls180.v:4008$507_Y
+ connect \A $or$ls180.v:4004$506_Y
+ connect \Y $not$ls180.v:4004$507_Y
end
- attribute \src "ls180.v:4008.1250-4008.1494"
- cell $not $not$ls180.v:4008$523
+ attribute \src "ls180.v:4004.1250-4004.1494"
+ cell $not $not$ls180.v:4004$523
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:4008$522_Y
- connect \Y $not$ls180.v:4008$523_Y
+ connect \A $or$ls180.v:4004$522_Y
+ connect \Y $not$ls180.v:4004$523_Y
end
- attribute \src "ls180.v:4030.32-4030.50"
- cell $not $not$ls180.v:4030$529
+ attribute \src "ls180.v:4026.32-4026.50"
+ cell $not $not$ls180.v:4026$529
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_wb_sdram_cyc
- connect \Y $not$ls180.v:4030$529_Y
+ connect \Y $not$ls180.v:4026$529_Y
end
- attribute \src "ls180.v:4069.30-4069.50"
- cell $not $not$ls180.v:4069$534
+ attribute \src "ls180.v:4065.30-4065.50"
+ cell $not $not$ls180.v:4065$534
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_converter_skip
- connect \Y $not$ls180.v:4069$534_Y
+ connect \Y $not$ls180.v:4065$534_Y
end
- attribute \src "ls180.v:4070.30-4070.50"
- cell $not $not$ls180.v:4070$535
+ attribute \src "ls180.v:4066.30-4066.50"
+ cell $not $not$ls180.v:4066$535
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_converter_skip
- connect \Y $not$ls180.v:4070$535_Y
+ connect \Y $not$ls180.v:4066$535_Y
end
- attribute \src "ls180.v:4095.27-4095.48"
- cell $not $not$ls180.v:4095$541
+ attribute \src "ls180.v:4091.27-4091.48"
+ cell $not $not$ls180.v:4091$541
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_litedram_wb_cyc
- connect \Y $not$ls180.v:4095$541_Y
+ connect \Y $not$ls180.v:4091$541_Y
end
- attribute \src "ls180.v:4096.30-4096.50"
- cell $not $not$ls180.v:4096$542
+ attribute \src "ls180.v:4092.30-4092.50"
+ cell $not $not$ls180.v:4092$542
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_litedram_wb_we
- connect \Y $not$ls180.v:4096$542_Y
+ connect \Y $not$ls180.v:4092$542_Y
end
- attribute \src "ls180.v:4097.80-4097.98"
- cell $not $not$ls180.v:4097$544
+ attribute \src "ls180.v:4093.80-4093.98"
+ cell $not $not$ls180.v:4093$544
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_cmd_consumed
- connect \Y $not$ls180.v:4097$544_Y
+ connect \Y $not$ls180.v:4093$544_Y
end
- attribute \src "ls180.v:4098.107-4098.127"
- cell $not $not$ls180.v:4098$548
+ attribute \src "ls180.v:4094.107-4094.127"
+ cell $not $not$ls180.v:4094$548
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_wdata_consumed
- connect \Y $not$ls180.v:4098$548_Y
+ connect \Y $not$ls180.v:4094$548_Y
end
- attribute \src "ls180.v:4099.78-4099.103"
- cell $not $not$ls180.v:4099$551
+ attribute \src "ls180.v:4095.78-4095.103"
+ cell $not $not$ls180.v:4095$551
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_port_cmd_payload_we
- connect \Y $not$ls180.v:4099$551_Y
+ connect \Y $not$ls180.v:4095$551_Y
end
- attribute \src "ls180.v:4100.91-4100.111"
- cell $not $not$ls180.v:4100$554
+ attribute \src "ls180.v:4096.91-4096.111"
+ cell $not $not$ls180.v:4096$554
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_litedram_wb_we
- connect \Y $not$ls180.v:4100$554_Y
+ connect \Y $not$ls180.v:4096$554_Y
end
- attribute \src "ls180.v:4116.35-4116.64"
- cell $not $not$ls180.v:4116$563
+ attribute \src "ls180.v:4112.35-4112.64"
+ cell $not $not$ls180.v:4112$563
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_uart_tx_fifo_sink_ready
- connect \Y $not$ls180.v:4116$563_Y
+ connect \Y $not$ls180.v:4112$563_Y
end
- attribute \src "ls180.v:4117.36-4117.67"
- cell $not $not$ls180.v:4117$564
+ attribute \src "ls180.v:4113.36-4113.67"
+ cell $not $not$ls180.v:4113$564
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_uart_tx_fifo_source_valid
- connect \Y $not$ls180.v:4117$564_Y
+ connect \Y $not$ls180.v:4113$564_Y
end
- attribute \src "ls180.v:4123.32-4123.61"
- cell $not $not$ls180.v:4123$565
+ attribute \src "ls180.v:4119.32-4119.61"
+ cell $not $not$ls180.v:4119$565
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_uart_tx_fifo_sink_ready
- connect \Y $not$ls180.v:4123$565_Y
+ connect \Y $not$ls180.v:4119$565_Y
end
- attribute \src "ls180.v:4129.36-4129.67"
- cell $not $not$ls180.v:4129$566
+ attribute \src "ls180.v:4125.36-4125.67"
+ cell $not $not$ls180.v:4125$566
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_uart_rx_fifo_source_valid
- connect \Y $not$ls180.v:4129$566_Y
+ connect \Y $not$ls180.v:4125$566_Y
end
- attribute \src "ls180.v:4130.35-4130.64"
- cell $not $not$ls180.v:4130$567
+ attribute \src "ls180.v:4126.35-4126.64"
+ cell $not $not$ls180.v:4126$567
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_uart_rx_fifo_sink_ready
- connect \Y $not$ls180.v:4130$567_Y
+ connect \Y $not$ls180.v:4126$567_Y
end
- attribute \src "ls180.v:4133.32-4133.63"
- cell $not $not$ls180.v:4133$570
+ attribute \src "ls180.v:4129.32-4129.63"
+ cell $not $not$ls180.v:4129$570
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_uart_rx_fifo_source_valid
- connect \Y $not$ls180.v:4133$570_Y
+ connect \Y $not$ls180.v:4129$570_Y
end
- attribute \src "ls180.v:4171.81-4171.108"
- cell $not $not$ls180.v:4171$580
+ attribute \src "ls180.v:4167.81-4167.108"
+ cell $not $not$ls180.v:4167$580
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_uart_tx_fifo_readable
- connect \Y $not$ls180.v:4171$580_Y
+ connect \Y $not$ls180.v:4167$580_Y
end
- attribute \src "ls180.v:4201.81-4201.108"
- cell $not $not$ls180.v:4201$591
+ attribute \src "ls180.v:4197.81-4197.108"
+ cell $not $not$ls180.v:4197$591
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_uart_rx_fifo_readable
- connect \Y $not$ls180.v:4201$591_Y
+ connect \Y $not$ls180.v:4197$591_Y
end
- attribute \src "ls180.v:4401.60-4401.85"
- cell $not $not$ls180.v:4401$640
+ attribute \src "ls180.v:4397.60-4397.85"
+ cell $not $not$ls180.v:4397$640
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdphy_clocker_clk_d
- connect \Y $not$ls180.v:4401$640_Y
+ connect \Y $not$ls180.v:4397$640_Y
end
- attribute \src "ls180.v:4542.54-4542.96"
- cell $not $not$ls180.v:4542$654
+ attribute \src "ls180.v:4538.54-4538.96"
+ cell $not $not$ls180.v:4538$654
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdphy_cmdr_cmdr_converter_strobe_all
- connect \Y $not$ls180.v:4542$654_Y
+ connect \Y $not$ls180.v:4538$654_Y
end
- attribute \src "ls180.v:4545.48-4545.86"
- cell $not $not$ls180.v:4545$657
+ attribute \src "ls180.v:4541.48-4541.86"
+ cell $not $not$ls180.v:4541$657
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdphy_cmdr_cmdr_buf_source_valid
- connect \Y $not$ls180.v:4545$657_Y
+ connect \Y $not$ls180.v:4541$657_Y
end
- attribute \src "ls180.v:4669.55-4669.98"
- cell $not $not$ls180.v:4669$675
+ attribute \src "ls180.v:4665.55-4665.98"
+ cell $not $not$ls180.v:4665$675
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdphy_dataw_crcr_converter_strobe_all
- connect \Y $not$ls180.v:4669$675_Y
+ connect \Y $not$ls180.v:4665$675_Y
end
- attribute \src "ls180.v:4672.49-4672.88"
- cell $not $not$ls180.v:4672$678
+ attribute \src "ls180.v:4668.49-4668.88"
+ cell $not $not$ls180.v:4668$678
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdphy_dataw_crcr_buf_source_valid
- connect \Y $not$ls180.v:4672$678_Y
+ connect \Y $not$ls180.v:4668$678_Y
end
- attribute \src "ls180.v:4722.30-4722.58"
- cell $not $not$ls180.v:4722$684
+ attribute \src "ls180.v:4718.30-4718.58"
+ cell $not $not$ls180.v:4718$684
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdphy_dataw_sink_valid
- connect \Y $not$ls180.v:4722$684_Y
+ connect \Y $not$ls180.v:4718$684_Y
end
- attribute \src "ls180.v:4803.56-4803.100"
- cell $not $not$ls180.v:4803$690
+ attribute \src "ls180.v:4799.56-4799.100"
+ cell $not $not$ls180.v:4799$690
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdphy_datar_datar_converter_strobe_all
- connect \Y $not$ls180.v:4803$690_Y
+ connect \Y $not$ls180.v:4799$690_Y
end
- attribute \src "ls180.v:4806.50-4806.90"
- cell $not $not$ls180.v:4806$693
+ attribute \src "ls180.v:4802.50-4802.90"
+ cell $not $not$ls180.v:4802$693
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdphy_datar_datar_buf_source_valid
- connect \Y $not$ls180.v:4806$693_Y
+ connect \Y $not$ls180.v:4802$693_Y
end
- attribute \src "ls180.v:4922.42-4922.74"
- cell $not $not$ls180.v:4922$709
+ attribute \src "ls180.v:4918.42-4918.74"
+ cell $not $not$ls180.v:4918$709
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_checker_valid
- connect \Y $not$ls180.v:4922$709_Y
+ connect \Y $not$ls180.v:4918$709_Y
end
- attribute \src "ls180.v:5446.50-5446.88"
- cell $not $not$ls180.v:5446$994
+ attribute \src "ls180.v:5442.50-5442.88"
+ cell $not $not$ls180.v:5442$994
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdblock2mem_converter_strobe_all
- connect \Y $not$ls180.v:5446$994_Y
+ connect \Y $not$ls180.v:5442$994_Y
end
- attribute \src "ls180.v:5458.52-5458.102"
- cell $not $not$ls180.v:5458$997
+ attribute \src "ls180.v:5454.52-5454.102"
+ cell $not $not$ls180.v:5454$997
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdblock2mem_wishbonedmawriter_enable_storage
- connect \Y $not$ls180.v:5458$997_Y
+ connect \Y $not$ls180.v:5454$997_Y
end
- attribute \src "ls180.v:5517.38-5517.74"
- cell $not $not$ls180.v:5517$1004
+ attribute \src "ls180.v:5513.38-5513.74"
+ cell $not $not$ls180.v:5513$1004
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdmem2block_dma_enable_storage
- connect \Y $not$ls180.v:5517$1004_Y
+ connect \Y $not$ls180.v:5513$1004_Y
end
- attribute \src "ls180.v:5759.69-5759.88"
- cell $not $not$ls180.v:5759$1065
+ attribute \src "ls180.v:5755.69-5755.88"
+ cell $not $not$ls180.v:5755$1065
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_shared_ack
- connect \Y $not$ls180.v:5759$1065_Y
+ connect \Y $not$ls180.v:5755$1065_Y
end
- attribute \src "ls180.v:5776.63-5776.94"
- cell $not $not$ls180.v:5776$1086
+ attribute \src "ls180.v:5772.63-5772.94"
+ cell $not $not$ls180.v:5772$1086
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface0_bank_bus_we
- connect \Y $not$ls180.v:5776$1086_Y
+ connect \Y $not$ls180.v:5772$1086_Y
end
- attribute \src "ls180.v:5779.65-5779.96"
- cell $not $not$ls180.v:5779$1093
+ attribute \src "ls180.v:5775.65-5775.96"
+ cell $not $not$ls180.v:5775$1093
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface0_bank_bus_we
- connect \Y $not$ls180.v:5779$1093_Y
+ connect \Y $not$ls180.v:5775$1093_Y
end
- attribute \src "ls180.v:5782.65-5782.96"
- cell $not $not$ls180.v:5782$1100
+ attribute \src "ls180.v:5778.65-5778.96"
+ cell $not $not$ls180.v:5778$1100
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface0_bank_bus_we
- connect \Y $not$ls180.v:5782$1100_Y
+ connect \Y $not$ls180.v:5778$1100_Y
end
- attribute \src "ls180.v:5785.65-5785.96"
- cell $not $not$ls180.v:5785$1107
+ attribute \src "ls180.v:5781.65-5781.96"
+ cell $not $not$ls180.v:5781$1107
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface0_bank_bus_we
- connect \Y $not$ls180.v:5785$1107_Y
+ connect \Y $not$ls180.v:5781$1107_Y
end
- attribute \src "ls180.v:5788.65-5788.96"
- cell $not $not$ls180.v:5788$1114
+ attribute \src "ls180.v:5784.65-5784.96"
+ cell $not $not$ls180.v:5784$1114
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface0_bank_bus_we
- connect \Y $not$ls180.v:5788$1114_Y
+ connect \Y $not$ls180.v:5784$1114_Y
end
- attribute \src "ls180.v:5791.68-5791.99"
- cell $not $not$ls180.v:5791$1121
+ attribute \src "ls180.v:5787.68-5787.99"
+ cell $not $not$ls180.v:5787$1121
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface0_bank_bus_we
- connect \Y $not$ls180.v:5791$1121_Y
+ connect \Y $not$ls180.v:5787$1121_Y
end
- attribute \src "ls180.v:5794.68-5794.99"
- cell $not $not$ls180.v:5794$1128
+ attribute \src "ls180.v:5790.68-5790.99"
+ cell $not $not$ls180.v:5790$1128
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface0_bank_bus_we
- connect \Y $not$ls180.v:5794$1128_Y
+ connect \Y $not$ls180.v:5790$1128_Y
end
- attribute \src "ls180.v:5797.68-5797.99"
- cell $not $not$ls180.v:5797$1135
+ attribute \src "ls180.v:5793.68-5793.99"
+ cell $not $not$ls180.v:5793$1135
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface0_bank_bus_we
- connect \Y $not$ls180.v:5797$1135_Y
+ connect \Y $not$ls180.v:5793$1135_Y
end
- attribute \src "ls180.v:5800.68-5800.99"
- cell $not $not$ls180.v:5800$1142
+ attribute \src "ls180.v:5796.68-5796.99"
+ cell $not $not$ls180.v:5796$1142
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface0_bank_bus_we
- connect \Y $not$ls180.v:5800$1142_Y
+ connect \Y $not$ls180.v:5796$1142_Y
end
- attribute \src "ls180.v:5814.60-5814.91"
- cell $not $not$ls180.v:5814$1150
+ attribute \src "ls180.v:5810.60-5810.91"
+ cell $not $not$ls180.v:5810$1150
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface1_bank_bus_we
- connect \Y $not$ls180.v:5814$1150_Y
+ connect \Y $not$ls180.v:5810$1150_Y
end
- attribute \src "ls180.v:5817.60-5817.91"
- cell $not $not$ls180.v:5817$1157
+ attribute \src "ls180.v:5813.60-5813.91"
+ cell $not $not$ls180.v:5813$1157
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface1_bank_bus_we
- connect \Y $not$ls180.v:5817$1157_Y
+ connect \Y $not$ls180.v:5813$1157_Y
end
- attribute \src "ls180.v:5820.60-5820.91"
- cell $not $not$ls180.v:5820$1164
+ attribute \src "ls180.v:5816.60-5816.91"
+ cell $not $not$ls180.v:5816$1164
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface1_bank_bus_we
- connect \Y $not$ls180.v:5820$1164_Y
+ connect \Y $not$ls180.v:5816$1164_Y
end
- attribute \src "ls180.v:5823.60-5823.91"
- cell $not $not$ls180.v:5823$1171
+ attribute \src "ls180.v:5819.60-5819.91"
+ cell $not $not$ls180.v:5819$1171
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface1_bank_bus_we
- connect \Y $not$ls180.v:5823$1171_Y
+ connect \Y $not$ls180.v:5819$1171_Y
end
- attribute \src "ls180.v:5826.61-5826.92"
- cell $not $not$ls180.v:5826$1178
+ attribute \src "ls180.v:5822.61-5822.92"
+ cell $not $not$ls180.v:5822$1178
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface1_bank_bus_we
- connect \Y $not$ls180.v:5826$1178_Y
+ connect \Y $not$ls180.v:5822$1178_Y
end
- attribute \src "ls180.v:5829.61-5829.92"
- cell $not $not$ls180.v:5829$1185
+ attribute \src "ls180.v:5825.61-5825.92"
+ cell $not $not$ls180.v:5825$1185
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface1_bank_bus_we
- connect \Y $not$ls180.v:5829$1185_Y
+ connect \Y $not$ls180.v:5825$1185_Y
end
- attribute \src "ls180.v:5840.59-5840.90"
- cell $not $not$ls180.v:5840$1193
+ attribute \src "ls180.v:5836.59-5836.90"
+ cell $not $not$ls180.v:5836$1193
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface2_bank_bus_we
- connect \Y $not$ls180.v:5840$1193_Y
+ connect \Y $not$ls180.v:5836$1193_Y
end
- attribute \src "ls180.v:5843.58-5843.89"
- cell $not $not$ls180.v:5843$1200
+ attribute \src "ls180.v:5839.58-5839.89"
+ cell $not $not$ls180.v:5839$1200
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface2_bank_bus_we
- connect \Y $not$ls180.v:5843$1200_Y
+ connect \Y $not$ls180.v:5839$1200_Y
end
- attribute \src "ls180.v:5854.64-5854.95"
- cell $not $not$ls180.v:5854$1208
+ attribute \src "ls180.v:5850.64-5850.95"
+ cell $not $not$ls180.v:5850$1208
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface3_bank_bus_we
- connect \Y $not$ls180.v:5854$1208_Y
+ connect \Y $not$ls180.v:5850$1208_Y
end
- attribute \src "ls180.v:5857.63-5857.94"
- cell $not $not$ls180.v:5857$1215
+ attribute \src "ls180.v:5853.63-5853.94"
+ cell $not $not$ls180.v:5853$1215
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface3_bank_bus_we
- connect \Y $not$ls180.v:5857$1215_Y
+ connect \Y $not$ls180.v:5853$1215_Y
end
- attribute \src "ls180.v:5860.63-5860.94"
- cell $not $not$ls180.v:5860$1222
+ attribute \src "ls180.v:5856.63-5856.94"
+ cell $not $not$ls180.v:5856$1222
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface3_bank_bus_we
- connect \Y $not$ls180.v:5860$1222_Y
+ connect \Y $not$ls180.v:5856$1222_Y
end
- attribute \src "ls180.v:5863.63-5863.94"
- cell $not $not$ls180.v:5863$1229
+ attribute \src "ls180.v:5859.63-5859.94"
+ cell $not $not$ls180.v:5859$1229
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface3_bank_bus_we
- connect \Y $not$ls180.v:5863$1229_Y
+ connect \Y $not$ls180.v:5859$1229_Y
end
- attribute \src "ls180.v:5866.63-5866.94"
- cell $not $not$ls180.v:5866$1236
+ attribute \src "ls180.v:5862.63-5862.94"
+ cell $not $not$ls180.v:5862$1236
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface3_bank_bus_we
- connect \Y $not$ls180.v:5866$1236_Y
+ connect \Y $not$ls180.v:5862$1236_Y
end
- attribute \src "ls180.v:5869.64-5869.95"
- cell $not $not$ls180.v:5869$1243
+ attribute \src "ls180.v:5865.64-5865.95"
+ cell $not $not$ls180.v:5865$1243
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface3_bank_bus_we
- connect \Y $not$ls180.v:5869$1243_Y
+ connect \Y $not$ls180.v:5865$1243_Y
end
- attribute \src "ls180.v:5872.64-5872.95"
- cell $not $not$ls180.v:5872$1250
+ attribute \src "ls180.v:5868.64-5868.95"
+ cell $not $not$ls180.v:5868$1250
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface3_bank_bus_we
- connect \Y $not$ls180.v:5872$1250_Y
+ connect \Y $not$ls180.v:5868$1250_Y
end
- attribute \src "ls180.v:5875.64-5875.95"
- cell $not $not$ls180.v:5875$1257
+ attribute \src "ls180.v:5871.64-5871.95"
+ cell $not $not$ls180.v:5871$1257
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface3_bank_bus_we
- connect \Y $not$ls180.v:5875$1257_Y
+ connect \Y $not$ls180.v:5871$1257_Y
end
- attribute \src "ls180.v:5878.64-5878.95"
- cell $not $not$ls180.v:5878$1264
+ attribute \src "ls180.v:5874.64-5874.95"
+ cell $not $not$ls180.v:5874$1264
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface3_bank_bus_we
- connect \Y $not$ls180.v:5878$1264_Y
+ connect \Y $not$ls180.v:5874$1264_Y
end
- attribute \src "ls180.v:5891.64-5891.95"
- cell $not $not$ls180.v:5891$1272
+ attribute \src "ls180.v:5887.64-5887.95"
+ cell $not $not$ls180.v:5887$1272
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface4_bank_bus_we
- connect \Y $not$ls180.v:5891$1272_Y
+ connect \Y $not$ls180.v:5887$1272_Y
end
- attribute \src "ls180.v:5894.63-5894.94"
- cell $not $not$ls180.v:5894$1279
+ attribute \src "ls180.v:5890.63-5890.94"
+ cell $not $not$ls180.v:5890$1279
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface4_bank_bus_we
- connect \Y $not$ls180.v:5894$1279_Y
+ connect \Y $not$ls180.v:5890$1279_Y
end
- attribute \src "ls180.v:5897.63-5897.94"
- cell $not $not$ls180.v:5897$1286
+ attribute \src "ls180.v:5893.63-5893.94"
+ cell $not $not$ls180.v:5893$1286
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface4_bank_bus_we
- connect \Y $not$ls180.v:5897$1286_Y
+ connect \Y $not$ls180.v:5893$1286_Y
end
- attribute \src "ls180.v:5900.63-5900.94"
- cell $not $not$ls180.v:5900$1293
+ attribute \src "ls180.v:5896.63-5896.94"
+ cell $not $not$ls180.v:5896$1293
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface4_bank_bus_we
- connect \Y $not$ls180.v:5900$1293_Y
+ connect \Y $not$ls180.v:5896$1293_Y
end
- attribute \src "ls180.v:5903.63-5903.94"
- cell $not $not$ls180.v:5903$1300
+ attribute \src "ls180.v:5899.63-5899.94"
+ cell $not $not$ls180.v:5899$1300
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface4_bank_bus_we
- connect \Y $not$ls180.v:5903$1300_Y
+ connect \Y $not$ls180.v:5899$1300_Y
end
- attribute \src "ls180.v:5906.64-5906.95"
- cell $not $not$ls180.v:5906$1307
+ attribute \src "ls180.v:5902.64-5902.95"
+ cell $not $not$ls180.v:5902$1307
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface4_bank_bus_we
- connect \Y $not$ls180.v:5906$1307_Y
+ connect \Y $not$ls180.v:5902$1307_Y
end
- attribute \src "ls180.v:5909.64-5909.95"
- cell $not $not$ls180.v:5909$1314
+ attribute \src "ls180.v:5905.64-5905.95"
+ cell $not $not$ls180.v:5905$1314
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface4_bank_bus_we
- connect \Y $not$ls180.v:5909$1314_Y
+ connect \Y $not$ls180.v:5905$1314_Y
end
- attribute \src "ls180.v:5912.64-5912.95"
- cell $not $not$ls180.v:5912$1321
+ attribute \src "ls180.v:5908.64-5908.95"
+ cell $not $not$ls180.v:5908$1321
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface4_bank_bus_we
- connect \Y $not$ls180.v:5912$1321_Y
+ connect \Y $not$ls180.v:5908$1321_Y
end
- attribute \src "ls180.v:5915.64-5915.95"
- cell $not $not$ls180.v:5915$1328
+ attribute \src "ls180.v:5911.64-5911.95"
+ cell $not $not$ls180.v:5911$1328
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface4_bank_bus_we
- connect \Y $not$ls180.v:5915$1328_Y
+ connect \Y $not$ls180.v:5911$1328_Y
end
- attribute \src "ls180.v:5928.66-5928.97"
- cell $not $not$ls180.v:5928$1336
+ attribute \src "ls180.v:5924.66-5924.97"
+ cell $not $not$ls180.v:5924$1336
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface5_bank_bus_we
- connect \Y $not$ls180.v:5928$1336_Y
+ connect \Y $not$ls180.v:5924$1336_Y
end
- attribute \src "ls180.v:5931.66-5931.97"
- cell $not $not$ls180.v:5931$1343
+ attribute \src "ls180.v:5927.66-5927.97"
+ cell $not $not$ls180.v:5927$1343
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface5_bank_bus_we
- connect \Y $not$ls180.v:5931$1343_Y
+ connect \Y $not$ls180.v:5927$1343_Y
end
- attribute \src "ls180.v:5934.66-5934.97"
- cell $not $not$ls180.v:5934$1350
+ attribute \src "ls180.v:5930.66-5930.97"
+ cell $not $not$ls180.v:5930$1350
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface5_bank_bus_we
- connect \Y $not$ls180.v:5934$1350_Y
+ connect \Y $not$ls180.v:5930$1350_Y
end
- attribute \src "ls180.v:5937.66-5937.97"
- cell $not $not$ls180.v:5937$1357
+ attribute \src "ls180.v:5933.66-5933.97"
+ cell $not $not$ls180.v:5933$1357
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface5_bank_bus_we
- connect \Y $not$ls180.v:5937$1357_Y
+ connect \Y $not$ls180.v:5933$1357_Y
end
- attribute \src "ls180.v:5940.66-5940.97"
- cell $not $not$ls180.v:5940$1364
+ attribute \src "ls180.v:5936.66-5936.97"
+ cell $not $not$ls180.v:5936$1364
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface5_bank_bus_we
- connect \Y $not$ls180.v:5940$1364_Y
+ connect \Y $not$ls180.v:5936$1364_Y
end
- attribute \src "ls180.v:5943.66-5943.97"
- cell $not $not$ls180.v:5943$1371
+ attribute \src "ls180.v:5939.66-5939.97"
+ cell $not $not$ls180.v:5939$1371
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface5_bank_bus_we
- connect \Y $not$ls180.v:5943$1371_Y
+ connect \Y $not$ls180.v:5939$1371_Y
end
- attribute \src "ls180.v:5946.66-5946.97"
- cell $not $not$ls180.v:5946$1378
+ attribute \src "ls180.v:5942.66-5942.97"
+ cell $not $not$ls180.v:5942$1378
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface5_bank_bus_we
- connect \Y $not$ls180.v:5946$1378_Y
+ connect \Y $not$ls180.v:5942$1378_Y
end
- attribute \src "ls180.v:5949.66-5949.97"
- cell $not $not$ls180.v:5949$1385
+ attribute \src "ls180.v:5945.66-5945.97"
+ cell $not $not$ls180.v:5945$1385
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface5_bank_bus_we
- connect \Y $not$ls180.v:5949$1385_Y
+ connect \Y $not$ls180.v:5945$1385_Y
end
- attribute \src "ls180.v:5952.68-5952.99"
- cell $not $not$ls180.v:5952$1392
+ attribute \src "ls180.v:5948.68-5948.99"
+ cell $not $not$ls180.v:5948$1392
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface5_bank_bus_we
- connect \Y $not$ls180.v:5952$1392_Y
+ connect \Y $not$ls180.v:5948$1392_Y
end
- attribute \src "ls180.v:5955.68-5955.99"
- cell $not $not$ls180.v:5955$1399
+ attribute \src "ls180.v:5951.68-5951.99"
+ cell $not $not$ls180.v:5951$1399
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface5_bank_bus_we
- connect \Y $not$ls180.v:5955$1399_Y
+ connect \Y $not$ls180.v:5951$1399_Y
end
- attribute \src "ls180.v:5958.68-5958.99"
- cell $not $not$ls180.v:5958$1406
+ attribute \src "ls180.v:5954.68-5954.99"
+ cell $not $not$ls180.v:5954$1406
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface5_bank_bus_we
- connect \Y $not$ls180.v:5958$1406_Y
+ connect \Y $not$ls180.v:5954$1406_Y
end
- attribute \src "ls180.v:5961.68-5961.99"
- cell $not $not$ls180.v:5961$1413
+ attribute \src "ls180.v:5957.68-5957.99"
+ cell $not $not$ls180.v:5957$1413
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface5_bank_bus_we
- connect \Y $not$ls180.v:5961$1413_Y
+ connect \Y $not$ls180.v:5957$1413_Y
end
- attribute \src "ls180.v:5964.68-5964.99"
- cell $not $not$ls180.v:5964$1420
+ attribute \src "ls180.v:5960.68-5960.99"
+ cell $not $not$ls180.v:5960$1420
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface5_bank_bus_we
- connect \Y $not$ls180.v:5964$1420_Y
+ connect \Y $not$ls180.v:5960$1420_Y
end
- attribute \src "ls180.v:5967.65-5967.96"
- cell $not $not$ls180.v:5967$1427
+ attribute \src "ls180.v:5963.65-5963.96"
+ cell $not $not$ls180.v:5963$1427
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface5_bank_bus_we
- connect \Y $not$ls180.v:5967$1427_Y
+ connect \Y $not$ls180.v:5963$1427_Y
end
- attribute \src "ls180.v:5970.66-5970.97"
- cell $not $not$ls180.v:5970$1434
+ attribute \src "ls180.v:5966.66-5966.97"
+ cell $not $not$ls180.v:5966$1434
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface5_bank_bus_we
- connect \Y $not$ls180.v:5970$1434_Y
+ connect \Y $not$ls180.v:5966$1434_Y
end
- attribute \src "ls180.v:5990.70-5990.101"
- cell $not $not$ls180.v:5990$1442
+ attribute \src "ls180.v:5986.70-5986.101"
+ cell $not $not$ls180.v:5986$1442
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface6_bank_bus_we
- connect \Y $not$ls180.v:5990$1442_Y
+ connect \Y $not$ls180.v:5986$1442_Y
end
- attribute \src "ls180.v:5993.70-5993.101"
- cell $not $not$ls180.v:5993$1449
+ attribute \src "ls180.v:5989.70-5989.101"
+ cell $not $not$ls180.v:5989$1449
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface6_bank_bus_we
- connect \Y $not$ls180.v:5993$1449_Y
+ connect \Y $not$ls180.v:5989$1449_Y
end
- attribute \src "ls180.v:5996.70-5996.101"
- cell $not $not$ls180.v:5996$1456
+ attribute \src "ls180.v:5992.70-5992.101"
+ cell $not $not$ls180.v:5992$1456
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface6_bank_bus_we
- connect \Y $not$ls180.v:5996$1456_Y
+ connect \Y $not$ls180.v:5992$1456_Y
end
- attribute \src "ls180.v:5999.70-5999.101"
- cell $not $not$ls180.v:5999$1463
+ attribute \src "ls180.v:5995.70-5995.101"
+ cell $not $not$ls180.v:5995$1463
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface6_bank_bus_we
- connect \Y $not$ls180.v:5999$1463_Y
+ connect \Y $not$ls180.v:5995$1463_Y
end
- attribute \src "ls180.v:6002.69-6002.100"
- cell $not $not$ls180.v:6002$1470
+ attribute \src "ls180.v:5998.69-5998.100"
+ cell $not $not$ls180.v:5998$1470
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface6_bank_bus_we
- connect \Y $not$ls180.v:6002$1470_Y
+ connect \Y $not$ls180.v:5998$1470_Y
end
- attribute \src "ls180.v:6005.69-6005.100"
- cell $not $not$ls180.v:6005$1477
+ attribute \src "ls180.v:6001.69-6001.100"
+ cell $not $not$ls180.v:6001$1477
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface6_bank_bus_we
- connect \Y $not$ls180.v:6005$1477_Y
+ connect \Y $not$ls180.v:6001$1477_Y
end
- attribute \src "ls180.v:6008.69-6008.100"
- cell $not $not$ls180.v:6008$1484
+ attribute \src "ls180.v:6004.69-6004.100"
+ cell $not $not$ls180.v:6004$1484
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface6_bank_bus_we
- connect \Y $not$ls180.v:6008$1484_Y
+ connect \Y $not$ls180.v:6004$1484_Y
end
- attribute \src "ls180.v:6011.69-6011.100"
- cell $not $not$ls180.v:6011$1491
+ attribute \src "ls180.v:6007.69-6007.100"
+ cell $not $not$ls180.v:6007$1491
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface6_bank_bus_we
- connect \Y $not$ls180.v:6011$1491_Y
+ connect \Y $not$ls180.v:6007$1491_Y
end
- attribute \src "ls180.v:6014.60-6014.91"
- cell $not $not$ls180.v:6014$1498
+ attribute \src "ls180.v:6010.60-6010.91"
+ cell $not $not$ls180.v:6010$1498
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface6_bank_bus_we
- connect \Y $not$ls180.v:6014$1498_Y
+ connect \Y $not$ls180.v:6010$1498_Y
end
- attribute \src "ls180.v:6017.71-6017.102"
- cell $not $not$ls180.v:6017$1505
+ attribute \src "ls180.v:6013.71-6013.102"
+ cell $not $not$ls180.v:6013$1505
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface6_bank_bus_we
- connect \Y $not$ls180.v:6017$1505_Y
+ connect \Y $not$ls180.v:6013$1505_Y
end
- attribute \src "ls180.v:6020.71-6020.102"
- cell $not $not$ls180.v:6020$1512
+ attribute \src "ls180.v:6016.71-6016.102"
+ cell $not $not$ls180.v:6016$1512
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface6_bank_bus_we
- connect \Y $not$ls180.v:6020$1512_Y
+ connect \Y $not$ls180.v:6016$1512_Y
end
- attribute \src "ls180.v:6023.71-6023.102"
- cell $not $not$ls180.v:6023$1519
+ attribute \src "ls180.v:6019.71-6019.102"
+ cell $not $not$ls180.v:6019$1519
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface6_bank_bus_we
- connect \Y $not$ls180.v:6023$1519_Y
+ connect \Y $not$ls180.v:6019$1519_Y
end
- attribute \src "ls180.v:6026.71-6026.102"
- cell $not $not$ls180.v:6026$1526
+ attribute \src "ls180.v:6022.71-6022.102"
+ cell $not $not$ls180.v:6022$1526
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface6_bank_bus_we
- connect \Y $not$ls180.v:6026$1526_Y
+ connect \Y $not$ls180.v:6022$1526_Y
end
- attribute \src "ls180.v:6029.71-6029.102"
- cell $not $not$ls180.v:6029$1533
+ attribute \src "ls180.v:6025.71-6025.102"
+ cell $not $not$ls180.v:6025$1533
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface6_bank_bus_we
- connect \Y $not$ls180.v:6029$1533_Y
+ connect \Y $not$ls180.v:6025$1533_Y
end
- attribute \src "ls180.v:6032.71-6032.102"
- cell $not $not$ls180.v:6032$1540
+ attribute \src "ls180.v:6028.71-6028.102"
+ cell $not $not$ls180.v:6028$1540
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface6_bank_bus_we
- connect \Y $not$ls180.v:6032$1540_Y
+ connect \Y $not$ls180.v:6028$1540_Y
end
- attribute \src "ls180.v:6035.70-6035.101"
- cell $not $not$ls180.v:6035$1547
+ attribute \src "ls180.v:6031.70-6031.101"
+ cell $not $not$ls180.v:6031$1547
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface6_bank_bus_we
- connect \Y $not$ls180.v:6035$1547_Y
+ connect \Y $not$ls180.v:6031$1547_Y
end
- attribute \src "ls180.v:6038.70-6038.101"
- cell $not $not$ls180.v:6038$1554
+ attribute \src "ls180.v:6034.70-6034.101"
+ cell $not $not$ls180.v:6034$1554
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface6_bank_bus_we
- connect \Y $not$ls180.v:6038$1554_Y
+ connect \Y $not$ls180.v:6034$1554_Y
end
- attribute \src "ls180.v:6041.70-6041.101"
- cell $not $not$ls180.v:6041$1561
+ attribute \src "ls180.v:6037.70-6037.101"
+ cell $not $not$ls180.v:6037$1561
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface6_bank_bus_we
- connect \Y $not$ls180.v:6041$1561_Y
+ connect \Y $not$ls180.v:6037$1561_Y
end
- attribute \src "ls180.v:6044.70-6044.101"
- cell $not $not$ls180.v:6044$1568
+ attribute \src "ls180.v:6040.70-6040.101"
+ cell $not $not$ls180.v:6040$1568
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface6_bank_bus_we
- connect \Y $not$ls180.v:6044$1568_Y
+ connect \Y $not$ls180.v:6040$1568_Y
end
- attribute \src "ls180.v:6047.70-6047.101"
- cell $not $not$ls180.v:6047$1575
+ attribute \src "ls180.v:6043.70-6043.101"
+ cell $not $not$ls180.v:6043$1575
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface6_bank_bus_we
- connect \Y $not$ls180.v:6047$1575_Y
+ connect \Y $not$ls180.v:6043$1575_Y
end
- attribute \src "ls180.v:6050.70-6050.101"
- cell $not $not$ls180.v:6050$1582
+ attribute \src "ls180.v:6046.70-6046.101"
+ cell $not $not$ls180.v:6046$1582
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface6_bank_bus_we
- connect \Y $not$ls180.v:6050$1582_Y
+ connect \Y $not$ls180.v:6046$1582_Y
end
- attribute \src "ls180.v:6053.70-6053.101"
- cell $not $not$ls180.v:6053$1589
+ attribute \src "ls180.v:6049.70-6049.101"
+ cell $not $not$ls180.v:6049$1589
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface6_bank_bus_we
- connect \Y $not$ls180.v:6053$1589_Y
+ connect \Y $not$ls180.v:6049$1589_Y
end
- attribute \src "ls180.v:6056.70-6056.101"
- cell $not $not$ls180.v:6056$1596
+ attribute \src "ls180.v:6052.70-6052.101"
+ cell $not $not$ls180.v:6052$1596
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface6_bank_bus_we
- connect \Y $not$ls180.v:6056$1596_Y
+ connect \Y $not$ls180.v:6052$1596_Y
end
- attribute \src "ls180.v:6059.70-6059.101"
- cell $not $not$ls180.v:6059$1603
+ attribute \src "ls180.v:6055.70-6055.101"
+ cell $not $not$ls180.v:6055$1603
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface6_bank_bus_we
- connect \Y $not$ls180.v:6059$1603_Y
+ connect \Y $not$ls180.v:6055$1603_Y
end
- attribute \src "ls180.v:6062.70-6062.101"
- cell $not $not$ls180.v:6062$1610
+ attribute \src "ls180.v:6058.70-6058.101"
+ cell $not $not$ls180.v:6058$1610
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface6_bank_bus_we
- connect \Y $not$ls180.v:6062$1610_Y
+ connect \Y $not$ls180.v:6058$1610_Y
end
- attribute \src "ls180.v:6065.66-6065.97"
- cell $not $not$ls180.v:6065$1617
+ attribute \src "ls180.v:6061.66-6061.97"
+ cell $not $not$ls180.v:6061$1617
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface6_bank_bus_we
- connect \Y $not$ls180.v:6065$1617_Y
+ connect \Y $not$ls180.v:6061$1617_Y
end
- attribute \src "ls180.v:6068.67-6068.98"
- cell $not $not$ls180.v:6068$1624
+ attribute \src "ls180.v:6064.67-6064.98"
+ cell $not $not$ls180.v:6064$1624
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface6_bank_bus_we
- connect \Y $not$ls180.v:6068$1624_Y
+ connect \Y $not$ls180.v:6064$1624_Y
end
- attribute \src "ls180.v:6071.70-6071.101"
- cell $not $not$ls180.v:6071$1631
+ attribute \src "ls180.v:6067.70-6067.101"
+ cell $not $not$ls180.v:6067$1631
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface6_bank_bus_we
- connect \Y $not$ls180.v:6071$1631_Y
+ connect \Y $not$ls180.v:6067$1631_Y
end
- attribute \src "ls180.v:6074.70-6074.101"
- cell $not $not$ls180.v:6074$1638
+ attribute \src "ls180.v:6070.70-6070.101"
+ cell $not $not$ls180.v:6070$1638
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface6_bank_bus_we
- connect \Y $not$ls180.v:6074$1638_Y
+ connect \Y $not$ls180.v:6070$1638_Y
end
- attribute \src "ls180.v:6077.69-6077.100"
- cell $not $not$ls180.v:6077$1645
+ attribute \src "ls180.v:6073.69-6073.100"
+ cell $not $not$ls180.v:6073$1645
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface6_bank_bus_we
- connect \Y $not$ls180.v:6077$1645_Y
+ connect \Y $not$ls180.v:6073$1645_Y
end
- attribute \src "ls180.v:6080.69-6080.100"
- cell $not $not$ls180.v:6080$1652
+ attribute \src "ls180.v:6076.69-6076.100"
+ cell $not $not$ls180.v:6076$1652
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface6_bank_bus_we
- connect \Y $not$ls180.v:6080$1652_Y
+ connect \Y $not$ls180.v:6076$1652_Y
end
- attribute \src "ls180.v:6083.69-6083.100"
- cell $not $not$ls180.v:6083$1659
+ attribute \src "ls180.v:6079.69-6079.100"
+ cell $not $not$ls180.v:6079$1659
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface6_bank_bus_we
- connect \Y $not$ls180.v:6083$1659_Y
+ connect \Y $not$ls180.v:6079$1659_Y
end
- attribute \src "ls180.v:6086.69-6086.100"
- cell $not $not$ls180.v:6086$1666
+ attribute \src "ls180.v:6082.69-6082.100"
+ cell $not $not$ls180.v:6082$1666
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface6_bank_bus_we
- connect \Y $not$ls180.v:6086$1666_Y
+ connect \Y $not$ls180.v:6082$1666_Y
end
- attribute \src "ls180.v:6125.66-6125.97"
- cell $not $not$ls180.v:6125$1674
+ attribute \src "ls180.v:6121.66-6121.97"
+ cell $not $not$ls180.v:6121$1674
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface7_bank_bus_we
- connect \Y $not$ls180.v:6125$1674_Y
+ connect \Y $not$ls180.v:6121$1674_Y
end
- attribute \src "ls180.v:6128.66-6128.97"
- cell $not $not$ls180.v:6128$1681
+ attribute \src "ls180.v:6124.66-6124.97"
+ cell $not $not$ls180.v:6124$1681
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface7_bank_bus_we
- connect \Y $not$ls180.v:6128$1681_Y
+ connect \Y $not$ls180.v:6124$1681_Y
end
- attribute \src "ls180.v:6131.66-6131.97"
- cell $not $not$ls180.v:6131$1688
+ attribute \src "ls180.v:6127.66-6127.97"
+ cell $not $not$ls180.v:6127$1688
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface7_bank_bus_we
- connect \Y $not$ls180.v:6131$1688_Y
+ connect \Y $not$ls180.v:6127$1688_Y
end
- attribute \src "ls180.v:6134.66-6134.97"
- cell $not $not$ls180.v:6134$1695
+ attribute \src "ls180.v:6130.66-6130.97"
+ cell $not $not$ls180.v:6130$1695
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface7_bank_bus_we
- connect \Y $not$ls180.v:6134$1695_Y
+ connect \Y $not$ls180.v:6130$1695_Y
end
- attribute \src "ls180.v:6137.66-6137.97"
- cell $not $not$ls180.v:6137$1702
+ attribute \src "ls180.v:6133.66-6133.97"
+ cell $not $not$ls180.v:6133$1702
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface7_bank_bus_we
- connect \Y $not$ls180.v:6137$1702_Y
+ connect \Y $not$ls180.v:6133$1702_Y
end
- attribute \src "ls180.v:6140.66-6140.97"
- cell $not $not$ls180.v:6140$1709
+ attribute \src "ls180.v:6136.66-6136.97"
+ cell $not $not$ls180.v:6136$1709
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface7_bank_bus_we
- connect \Y $not$ls180.v:6140$1709_Y
+ connect \Y $not$ls180.v:6136$1709_Y
end
- attribute \src "ls180.v:6143.66-6143.97"
- cell $not $not$ls180.v:6143$1716
+ attribute \src "ls180.v:6139.66-6139.97"
+ cell $not $not$ls180.v:6139$1716
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface7_bank_bus_we
- connect \Y $not$ls180.v:6143$1716_Y
+ connect \Y $not$ls180.v:6139$1716_Y
end
- attribute \src "ls180.v:6146.66-6146.97"
- cell $not $not$ls180.v:6146$1723
+ attribute \src "ls180.v:6142.66-6142.97"
+ cell $not $not$ls180.v:6142$1723
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface7_bank_bus_we
- connect \Y $not$ls180.v:6146$1723_Y
+ connect \Y $not$ls180.v:6142$1723_Y
end
- attribute \src "ls180.v:6149.68-6149.99"
- cell $not $not$ls180.v:6149$1730
+ attribute \src "ls180.v:6145.68-6145.99"
+ cell $not $not$ls180.v:6145$1730
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface7_bank_bus_we
- connect \Y $not$ls180.v:6149$1730_Y
+ connect \Y $not$ls180.v:6145$1730_Y
end
- attribute \src "ls180.v:6152.68-6152.99"
- cell $not $not$ls180.v:6152$1737
+ attribute \src "ls180.v:6148.68-6148.99"
+ cell $not $not$ls180.v:6148$1737
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface7_bank_bus_we
- connect \Y $not$ls180.v:6152$1737_Y
+ connect \Y $not$ls180.v:6148$1737_Y
end
- attribute \src "ls180.v:6155.68-6155.99"
- cell $not $not$ls180.v:6155$1744
+ attribute \src "ls180.v:6151.68-6151.99"
+ cell $not $not$ls180.v:6151$1744
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface7_bank_bus_we
- connect \Y $not$ls180.v:6155$1744_Y
+ connect \Y $not$ls180.v:6151$1744_Y
end
- attribute \src "ls180.v:6158.68-6158.99"
- cell $not $not$ls180.v:6158$1751
+ attribute \src "ls180.v:6154.68-6154.99"
+ cell $not $not$ls180.v:6154$1751
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface7_bank_bus_we
- connect \Y $not$ls180.v:6158$1751_Y
+ connect \Y $not$ls180.v:6154$1751_Y
end
- attribute \src "ls180.v:6161.68-6161.99"
- cell $not $not$ls180.v:6161$1758
+ attribute \src "ls180.v:6157.68-6157.99"
+ cell $not $not$ls180.v:6157$1758
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface7_bank_bus_we
- connect \Y $not$ls180.v:6161$1758_Y
+ connect \Y $not$ls180.v:6157$1758_Y
end
- attribute \src "ls180.v:6164.65-6164.96"
- cell $not $not$ls180.v:6164$1765
+ attribute \src "ls180.v:6160.65-6160.96"
+ cell $not $not$ls180.v:6160$1765
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface7_bank_bus_we
- connect \Y $not$ls180.v:6164$1765_Y
+ connect \Y $not$ls180.v:6160$1765_Y
end
- attribute \src "ls180.v:6167.66-6167.97"
- cell $not $not$ls180.v:6167$1772
+ attribute \src "ls180.v:6163.66-6163.97"
+ cell $not $not$ls180.v:6163$1772
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface7_bank_bus_we
- connect \Y $not$ls180.v:6167$1772_Y
+ connect \Y $not$ls180.v:6163$1772_Y
end
- attribute \src "ls180.v:6170.68-6170.99"
- cell $not $not$ls180.v:6170$1779
+ attribute \src "ls180.v:6166.68-6166.99"
+ cell $not $not$ls180.v:6166$1779
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface7_bank_bus_we
- connect \Y $not$ls180.v:6170$1779_Y
+ connect \Y $not$ls180.v:6166$1779_Y
end
- attribute \src "ls180.v:6173.68-6173.99"
- cell $not $not$ls180.v:6173$1786
+ attribute \src "ls180.v:6169.68-6169.99"
+ cell $not $not$ls180.v:6169$1786
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface7_bank_bus_we
- connect \Y $not$ls180.v:6173$1786_Y
+ connect \Y $not$ls180.v:6169$1786_Y
end
- attribute \src "ls180.v:6176.68-6176.99"
- cell $not $not$ls180.v:6176$1793
+ attribute \src "ls180.v:6172.68-6172.99"
+ cell $not $not$ls180.v:6172$1793
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface7_bank_bus_we
- connect \Y $not$ls180.v:6176$1793_Y
+ connect \Y $not$ls180.v:6172$1793_Y
end
- attribute \src "ls180.v:6179.68-6179.99"
- cell $not $not$ls180.v:6179$1800
+ attribute \src "ls180.v:6175.68-6175.99"
+ cell $not $not$ls180.v:6175$1800
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface7_bank_bus_we
- connect \Y $not$ls180.v:6179$1800_Y
+ connect \Y $not$ls180.v:6175$1800_Y
end
- attribute \src "ls180.v:6204.68-6204.99"
- cell $not $not$ls180.v:6204$1808
+ attribute \src "ls180.v:6200.68-6200.99"
+ cell $not $not$ls180.v:6200$1808
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface8_bank_bus_we
- connect \Y $not$ls180.v:6204$1808_Y
+ connect \Y $not$ls180.v:6200$1808_Y
end
- attribute \src "ls180.v:6207.73-6207.104"
- cell $not $not$ls180.v:6207$1815
+ attribute \src "ls180.v:6203.73-6203.104"
+ cell $not $not$ls180.v:6203$1815
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface8_bank_bus_we
- connect \Y $not$ls180.v:6207$1815_Y
+ connect \Y $not$ls180.v:6203$1815_Y
end
- attribute \src "ls180.v:6210.73-6210.104"
- cell $not $not$ls180.v:6210$1822
+ attribute \src "ls180.v:6206.73-6206.104"
+ cell $not $not$ls180.v:6206$1822
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface8_bank_bus_we
- connect \Y $not$ls180.v:6210$1822_Y
+ connect \Y $not$ls180.v:6206$1822_Y
end
- attribute \src "ls180.v:6213.66-6213.97"
- cell $not $not$ls180.v:6213$1829
+ attribute \src "ls180.v:6209.66-6209.97"
+ cell $not $not$ls180.v:6209$1829
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface8_bank_bus_we
- connect \Y $not$ls180.v:6213$1829_Y
+ connect \Y $not$ls180.v:6209$1829_Y
end
- attribute \src "ls180.v:6221.70-6221.101"
- cell $not $not$ls180.v:6221$1837
+ attribute \src "ls180.v:6217.70-6217.101"
+ cell $not $not$ls180.v:6217$1837
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface9_bank_bus_we
- connect \Y $not$ls180.v:6221$1837_Y
+ connect \Y $not$ls180.v:6217$1837_Y
end
- attribute \src "ls180.v:6224.74-6224.105"
- cell $not $not$ls180.v:6224$1844
+ attribute \src "ls180.v:6220.74-6220.105"
+ cell $not $not$ls180.v:6220$1844
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface9_bank_bus_we
- connect \Y $not$ls180.v:6224$1844_Y
+ connect \Y $not$ls180.v:6220$1844_Y
end
- attribute \src "ls180.v:6227.64-6227.95"
- cell $not $not$ls180.v:6227$1851
+ attribute \src "ls180.v:6223.64-6223.95"
+ cell $not $not$ls180.v:6223$1851
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface9_bank_bus_we
- connect \Y $not$ls180.v:6227$1851_Y
+ connect \Y $not$ls180.v:6223$1851_Y
end
- attribute \src "ls180.v:6230.74-6230.105"
- cell $not $not$ls180.v:6230$1858
+ attribute \src "ls180.v:6226.74-6226.105"
+ cell $not $not$ls180.v:6226$1858
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface9_bank_bus_we
- connect \Y $not$ls180.v:6230$1858_Y
+ connect \Y $not$ls180.v:6226$1858_Y
end
- attribute \src "ls180.v:6233.74-6233.105"
- cell $not $not$ls180.v:6233$1865
+ attribute \src "ls180.v:6229.74-6229.105"
+ cell $not $not$ls180.v:6229$1865
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface9_bank_bus_we
- connect \Y $not$ls180.v:6233$1865_Y
+ connect \Y $not$ls180.v:6229$1865_Y
end
- attribute \src "ls180.v:6236.75-6236.106"
- cell $not $not$ls180.v:6236$1872
+ attribute \src "ls180.v:6232.75-6232.106"
+ cell $not $not$ls180.v:6232$1872
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface9_bank_bus_we
- connect \Y $not$ls180.v:6236$1872_Y
+ connect \Y $not$ls180.v:6232$1872_Y
end
- attribute \src "ls180.v:6239.73-6239.104"
- cell $not $not$ls180.v:6239$1879
+ attribute \src "ls180.v:6235.73-6235.104"
+ cell $not $not$ls180.v:6235$1879
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface9_bank_bus_we
- connect \Y $not$ls180.v:6239$1879_Y
+ connect \Y $not$ls180.v:6235$1879_Y
end
- attribute \src "ls180.v:6242.73-6242.104"
- cell $not $not$ls180.v:6242$1886
+ attribute \src "ls180.v:6238.73-6238.104"
+ cell $not $not$ls180.v:6238$1886
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface9_bank_bus_we
- connect \Y $not$ls180.v:6242$1886_Y
+ connect \Y $not$ls180.v:6238$1886_Y
end
- attribute \src "ls180.v:6245.73-6245.104"
- cell $not $not$ls180.v:6245$1893
+ attribute \src "ls180.v:6241.73-6241.104"
+ cell $not $not$ls180.v:6241$1893
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface9_bank_bus_we
- connect \Y $not$ls180.v:6245$1893_Y
+ connect \Y $not$ls180.v:6241$1893_Y
end
- attribute \src "ls180.v:6248.73-6248.104"
- cell $not $not$ls180.v:6248$1900
+ attribute \src "ls180.v:6244.73-6244.104"
+ cell $not $not$ls180.v:6244$1900
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface9_bank_bus_we
- connect \Y $not$ls180.v:6248$1900_Y
+ connect \Y $not$ls180.v:6244$1900_Y
end
- attribute \src "ls180.v:6266.67-6266.99"
- cell $not $not$ls180.v:6266$1908
+ attribute \src "ls180.v:6262.67-6262.99"
+ cell $not $not$ls180.v:6262$1908
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface10_bank_bus_we
- connect \Y $not$ls180.v:6266$1908_Y
+ connect \Y $not$ls180.v:6262$1908_Y
end
- attribute \src "ls180.v:6269.67-6269.99"
- cell $not $not$ls180.v:6269$1915
+ attribute \src "ls180.v:6265.67-6265.99"
+ cell $not $not$ls180.v:6265$1915
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface10_bank_bus_we
- connect \Y $not$ls180.v:6269$1915_Y
+ connect \Y $not$ls180.v:6265$1915_Y
end
- attribute \src "ls180.v:6272.65-6272.97"
- cell $not $not$ls180.v:6272$1922
+ attribute \src "ls180.v:6268.65-6268.97"
+ cell $not $not$ls180.v:6268$1922
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface10_bank_bus_we
- connect \Y $not$ls180.v:6272$1922_Y
+ connect \Y $not$ls180.v:6268$1922_Y
end
- attribute \src "ls180.v:6275.64-6275.96"
- cell $not $not$ls180.v:6275$1929
+ attribute \src "ls180.v:6271.64-6271.96"
+ cell $not $not$ls180.v:6271$1929
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface10_bank_bus_we
- connect \Y $not$ls180.v:6275$1929_Y
+ connect \Y $not$ls180.v:6271$1929_Y
end
- attribute \src "ls180.v:6278.63-6278.95"
- cell $not $not$ls180.v:6278$1936
+ attribute \src "ls180.v:6274.63-6274.95"
+ cell $not $not$ls180.v:6274$1936
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface10_bank_bus_we
- connect \Y $not$ls180.v:6278$1936_Y
+ connect \Y $not$ls180.v:6274$1936_Y
end
- attribute \src "ls180.v:6281.62-6281.94"
- cell $not $not$ls180.v:6281$1943
+ attribute \src "ls180.v:6277.62-6277.94"
+ cell $not $not$ls180.v:6277$1943
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface10_bank_bus_we
- connect \Y $not$ls180.v:6281$1943_Y
+ connect \Y $not$ls180.v:6277$1943_Y
end
- attribute \src "ls180.v:6284.68-6284.100"
- cell $not $not$ls180.v:6284$1950
+ attribute \src "ls180.v:6280.68-6280.100"
+ cell $not $not$ls180.v:6280$1950
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface10_bank_bus_we
- connect \Y $not$ls180.v:6284$1950_Y
+ connect \Y $not$ls180.v:6280$1950_Y
end
- attribute \src "ls180.v:6306.67-6306.99"
- cell $not $not$ls180.v:6306$1959
+ attribute \src "ls180.v:6302.67-6302.99"
+ cell $not $not$ls180.v:6302$1959
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface11_bank_bus_we
- connect \Y $not$ls180.v:6306$1959_Y
+ connect \Y $not$ls180.v:6302$1959_Y
end
- attribute \src "ls180.v:6309.67-6309.99"
- cell $not $not$ls180.v:6309$1966
+ attribute \src "ls180.v:6305.67-6305.99"
+ cell $not $not$ls180.v:6305$1966
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface11_bank_bus_we
- connect \Y $not$ls180.v:6309$1966_Y
+ connect \Y $not$ls180.v:6305$1966_Y
end
- attribute \src "ls180.v:6312.65-6312.97"
- cell $not $not$ls180.v:6312$1973
+ attribute \src "ls180.v:6308.65-6308.97"
+ cell $not $not$ls180.v:6308$1973
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface11_bank_bus_we
- connect \Y $not$ls180.v:6312$1973_Y
+ connect \Y $not$ls180.v:6308$1973_Y
end
- attribute \src "ls180.v:6315.64-6315.96"
- cell $not $not$ls180.v:6315$1980
+ attribute \src "ls180.v:6311.64-6311.96"
+ cell $not $not$ls180.v:6311$1980
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface11_bank_bus_we
- connect \Y $not$ls180.v:6315$1980_Y
+ connect \Y $not$ls180.v:6311$1980_Y
end
- attribute \src "ls180.v:6318.63-6318.95"
- cell $not $not$ls180.v:6318$1987
+ attribute \src "ls180.v:6314.63-6314.95"
+ cell $not $not$ls180.v:6314$1987
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface11_bank_bus_we
- connect \Y $not$ls180.v:6318$1987_Y
+ connect \Y $not$ls180.v:6314$1987_Y
end
- attribute \src "ls180.v:6321.62-6321.94"
- cell $not $not$ls180.v:6321$1994
+ attribute \src "ls180.v:6317.62-6317.94"
+ cell $not $not$ls180.v:6317$1994
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface11_bank_bus_we
- connect \Y $not$ls180.v:6321$1994_Y
+ connect \Y $not$ls180.v:6317$1994_Y
end
- attribute \src "ls180.v:6324.68-6324.100"
- cell $not $not$ls180.v:6324$2001
+ attribute \src "ls180.v:6320.68-6320.100"
+ cell $not $not$ls180.v:6320$2001
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface11_bank_bus_we
- connect \Y $not$ls180.v:6324$2001_Y
+ connect \Y $not$ls180.v:6320$2001_Y
end
- attribute \src "ls180.v:6327.71-6327.103"
- cell $not $not$ls180.v:6327$2008
+ attribute \src "ls180.v:6323.71-6323.103"
+ cell $not $not$ls180.v:6323$2008
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface11_bank_bus_we
- connect \Y $not$ls180.v:6327$2008_Y
+ connect \Y $not$ls180.v:6323$2008_Y
end
- attribute \src "ls180.v:6330.71-6330.103"
- cell $not $not$ls180.v:6330$2015
+ attribute \src "ls180.v:6326.71-6326.103"
+ cell $not $not$ls180.v:6326$2015
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface11_bank_bus_we
- connect \Y $not$ls180.v:6330$2015_Y
+ connect \Y $not$ls180.v:6326$2015_Y
end
- attribute \src "ls180.v:6354.64-6354.96"
- cell $not $not$ls180.v:6354$2024
+ attribute \src "ls180.v:6350.64-6350.96"
+ cell $not $not$ls180.v:6350$2024
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface12_bank_bus_we
- connect \Y $not$ls180.v:6354$2024_Y
+ connect \Y $not$ls180.v:6350$2024_Y
end
- attribute \src "ls180.v:6357.64-6357.96"
- cell $not $not$ls180.v:6357$2031
+ attribute \src "ls180.v:6353.64-6353.96"
+ cell $not $not$ls180.v:6353$2031
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface12_bank_bus_we
- connect \Y $not$ls180.v:6357$2031_Y
+ connect \Y $not$ls180.v:6353$2031_Y
end
- attribute \src "ls180.v:6360.64-6360.96"
- cell $not $not$ls180.v:6360$2038
+ attribute \src "ls180.v:6356.64-6356.96"
+ cell $not $not$ls180.v:6356$2038
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface12_bank_bus_we
- connect \Y $not$ls180.v:6360$2038_Y
+ connect \Y $not$ls180.v:6356$2038_Y
end
- attribute \src "ls180.v:6363.64-6363.96"
- cell $not $not$ls180.v:6363$2045
+ attribute \src "ls180.v:6359.64-6359.96"
+ cell $not $not$ls180.v:6359$2045
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface12_bank_bus_we
- connect \Y $not$ls180.v:6363$2045_Y
+ connect \Y $not$ls180.v:6359$2045_Y
end
- attribute \src "ls180.v:6366.66-6366.98"
- cell $not $not$ls180.v:6366$2052
+ attribute \src "ls180.v:6362.66-6362.98"
+ cell $not $not$ls180.v:6362$2052
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface12_bank_bus_we
- connect \Y $not$ls180.v:6366$2052_Y
+ connect \Y $not$ls180.v:6362$2052_Y
end
- attribute \src "ls180.v:6369.66-6369.98"
- cell $not $not$ls180.v:6369$2059
+ attribute \src "ls180.v:6365.66-6365.98"
+ cell $not $not$ls180.v:6365$2059
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface12_bank_bus_we
- connect \Y $not$ls180.v:6369$2059_Y
+ connect \Y $not$ls180.v:6365$2059_Y
end
- attribute \src "ls180.v:6372.66-6372.98"
- cell $not $not$ls180.v:6372$2066
+ attribute \src "ls180.v:6368.66-6368.98"
+ cell $not $not$ls180.v:6368$2066
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface12_bank_bus_we
- connect \Y $not$ls180.v:6372$2066_Y
+ connect \Y $not$ls180.v:6368$2066_Y
end
- attribute \src "ls180.v:6375.66-6375.98"
- cell $not $not$ls180.v:6375$2073
+ attribute \src "ls180.v:6371.66-6371.98"
+ cell $not $not$ls180.v:6371$2073
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface12_bank_bus_we
- connect \Y $not$ls180.v:6375$2073_Y
+ connect \Y $not$ls180.v:6371$2073_Y
end
- attribute \src "ls180.v:6378.62-6378.94"
- cell $not $not$ls180.v:6378$2080
+ attribute \src "ls180.v:6374.62-6374.94"
+ cell $not $not$ls180.v:6374$2080
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface12_bank_bus_we
- connect \Y $not$ls180.v:6378$2080_Y
+ connect \Y $not$ls180.v:6374$2080_Y
end
- attribute \src "ls180.v:6381.72-6381.104"
- cell $not $not$ls180.v:6381$2087
+ attribute \src "ls180.v:6377.72-6377.104"
+ cell $not $not$ls180.v:6377$2087
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface12_bank_bus_we
- connect \Y $not$ls180.v:6381$2087_Y
+ connect \Y $not$ls180.v:6377$2087_Y
end
- attribute \src "ls180.v:6384.65-6384.97"
- cell $not $not$ls180.v:6384$2094
+ attribute \src "ls180.v:6380.65-6380.97"
+ cell $not $not$ls180.v:6380$2094
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface12_bank_bus_we
- connect \Y $not$ls180.v:6384$2094_Y
+ connect \Y $not$ls180.v:6380$2094_Y
end
- attribute \src "ls180.v:6387.65-6387.97"
- cell $not $not$ls180.v:6387$2101
+ attribute \src "ls180.v:6383.65-6383.97"
+ cell $not $not$ls180.v:6383$2101
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface12_bank_bus_we
- connect \Y $not$ls180.v:6387$2101_Y
+ connect \Y $not$ls180.v:6383$2101_Y
end
- attribute \src "ls180.v:6390.65-6390.97"
- cell $not $not$ls180.v:6390$2108
+ attribute \src "ls180.v:6386.65-6386.97"
+ cell $not $not$ls180.v:6386$2108
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface12_bank_bus_we
- connect \Y $not$ls180.v:6390$2108_Y
+ connect \Y $not$ls180.v:6386$2108_Y
end
- attribute \src "ls180.v:6393.65-6393.97"
- cell $not $not$ls180.v:6393$2115
+ attribute \src "ls180.v:6389.65-6389.97"
+ cell $not $not$ls180.v:6389$2115
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface12_bank_bus_we
- connect \Y $not$ls180.v:6393$2115_Y
+ connect \Y $not$ls180.v:6389$2115_Y
end
- attribute \src "ls180.v:6396.77-6396.109"
- cell $not $not$ls180.v:6396$2122
+ attribute \src "ls180.v:6392.77-6392.109"
+ cell $not $not$ls180.v:6392$2122
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface12_bank_bus_we
- connect \Y $not$ls180.v:6396$2122_Y
+ connect \Y $not$ls180.v:6392$2122_Y
end
- attribute \src "ls180.v:6399.78-6399.110"
- cell $not $not$ls180.v:6399$2129
+ attribute \src "ls180.v:6395.78-6395.110"
+ cell $not $not$ls180.v:6395$2129
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface12_bank_bus_we
- connect \Y $not$ls180.v:6399$2129_Y
+ connect \Y $not$ls180.v:6395$2129_Y
end
- attribute \src "ls180.v:6402.69-6402.101"
- cell $not $not$ls180.v:6402$2136
+ attribute \src "ls180.v:6398.69-6398.101"
+ cell $not $not$ls180.v:6398$2136
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface12_bank_bus_we
- connect \Y $not$ls180.v:6402$2136_Y
+ connect \Y $not$ls180.v:6398$2136_Y
end
- attribute \src "ls180.v:6422.55-6422.87"
- cell $not $not$ls180.v:6422$2144
+ attribute \src "ls180.v:6418.55-6418.87"
+ cell $not $not$ls180.v:6418$2144
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface13_bank_bus_we
- connect \Y $not$ls180.v:6422$2144_Y
+ connect \Y $not$ls180.v:6418$2144_Y
end
- attribute \src "ls180.v:6425.65-6425.97"
- cell $not $not$ls180.v:6425$2151
+ attribute \src "ls180.v:6421.65-6421.97"
+ cell $not $not$ls180.v:6421$2151
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface13_bank_bus_we
- connect \Y $not$ls180.v:6425$2151_Y
+ connect \Y $not$ls180.v:6421$2151_Y
end
- attribute \src "ls180.v:6428.66-6428.98"
- cell $not $not$ls180.v:6428$2158
+ attribute \src "ls180.v:6424.66-6424.98"
+ cell $not $not$ls180.v:6424$2158
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface13_bank_bus_we
- connect \Y $not$ls180.v:6428$2158_Y
+ connect \Y $not$ls180.v:6424$2158_Y
end
- attribute \src "ls180.v:6431.70-6431.102"
- cell $not $not$ls180.v:6431$2165
+ attribute \src "ls180.v:6427.70-6427.102"
+ cell $not $not$ls180.v:6427$2165
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface13_bank_bus_we
- connect \Y $not$ls180.v:6431$2165_Y
+ connect \Y $not$ls180.v:6427$2165_Y
end
- attribute \src "ls180.v:6434.71-6434.103"
- cell $not $not$ls180.v:6434$2172
+ attribute \src "ls180.v:6430.71-6430.103"
+ cell $not $not$ls180.v:6430$2172
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface13_bank_bus_we
- connect \Y $not$ls180.v:6434$2172_Y
+ connect \Y $not$ls180.v:6430$2172_Y
end
- attribute \src "ls180.v:6437.69-6437.101"
- cell $not $not$ls180.v:6437$2179
+ attribute \src "ls180.v:6433.69-6433.101"
+ cell $not $not$ls180.v:6433$2179
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface13_bank_bus_we
- connect \Y $not$ls180.v:6437$2179_Y
+ connect \Y $not$ls180.v:6433$2179_Y
end
- attribute \src "ls180.v:6440.66-6440.98"
- cell $not $not$ls180.v:6440$2186
+ attribute \src "ls180.v:6436.66-6436.98"
+ cell $not $not$ls180.v:6436$2186
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface13_bank_bus_we
- connect \Y $not$ls180.v:6440$2186_Y
+ connect \Y $not$ls180.v:6436$2186_Y
end
- attribute \src "ls180.v:6443.65-6443.97"
- cell $not $not$ls180.v:6443$2193
+ attribute \src "ls180.v:6439.65-6439.97"
+ cell $not $not$ls180.v:6439$2193
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface13_bank_bus_we
- connect \Y $not$ls180.v:6443$2193_Y
+ connect \Y $not$ls180.v:6439$2193_Y
end
- attribute \src "ls180.v:6456.71-6456.103"
- cell $not $not$ls180.v:6456$2201
+ attribute \src "ls180.v:6452.71-6452.103"
+ cell $not $not$ls180.v:6452$2201
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface14_bank_bus_we
- connect \Y $not$ls180.v:6456$2201_Y
+ connect \Y $not$ls180.v:6452$2201_Y
end
- attribute \src "ls180.v:6459.71-6459.103"
- cell $not $not$ls180.v:6459$2208
+ attribute \src "ls180.v:6455.71-6455.103"
+ cell $not $not$ls180.v:6455$2208
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface14_bank_bus_we
- connect \Y $not$ls180.v:6459$2208_Y
+ connect \Y $not$ls180.v:6455$2208_Y
end
- attribute \src "ls180.v:6462.71-6462.103"
- cell $not $not$ls180.v:6462$2215
+ attribute \src "ls180.v:6458.71-6458.103"
+ cell $not $not$ls180.v:6458$2215
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface14_bank_bus_we
- connect \Y $not$ls180.v:6462$2215_Y
+ connect \Y $not$ls180.v:6458$2215_Y
end
- attribute \src "ls180.v:6465.71-6465.103"
- cell $not $not$ls180.v:6465$2222
+ attribute \src "ls180.v:6461.71-6461.103"
+ cell $not $not$ls180.v:6461$2222
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface14_bank_bus_we
- connect \Y $not$ls180.v:6465$2222_Y
+ connect \Y $not$ls180.v:6461$2222_Y
end
- attribute \src "ls180.v:6846.86-6846.330"
- cell $not $not$ls180.v:6846$2271
+ attribute \src "ls180.v:6842.86-6842.330"
+ cell $not $not$ls180.v:6842$2271
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:6846$2270_Y
- connect \Y $not$ls180.v:6846$2271_Y
+ connect \A $or$ls180.v:6842$2270_Y
+ connect \Y $not$ls180.v:6842$2271_Y
end
- attribute \src "ls180.v:6870.86-6870.330"
- cell $not $not$ls180.v:6870$2287
+ attribute \src "ls180.v:6866.86-6866.330"
+ cell $not $not$ls180.v:6866$2287
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:6870$2286_Y
- connect \Y $not$ls180.v:6870$2287_Y
+ connect \A $or$ls180.v:6866$2286_Y
+ connect \Y $not$ls180.v:6866$2287_Y
end
- attribute \src "ls180.v:6894.86-6894.330"
- cell $not $not$ls180.v:6894$2303
+ attribute \src "ls180.v:6890.86-6890.330"
+ cell $not $not$ls180.v:6890$2303
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:6894$2302_Y
- connect \Y $not$ls180.v:6894$2303_Y
+ connect \A $or$ls180.v:6890$2302_Y
+ connect \Y $not$ls180.v:6890$2303_Y
end
- attribute \src "ls180.v:6918.86-6918.330"
- cell $not $not$ls180.v:6918$2319
+ attribute \src "ls180.v:6914.86-6914.330"
+ cell $not $not$ls180.v:6914$2319
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:6918$2318_Y
- connect \Y $not$ls180.v:6918$2319_Y
+ connect \A $or$ls180.v:6914$2318_Y
+ connect \Y $not$ls180.v:6914$2319_Y
end
- attribute \src "ls180.v:7416.18-7416.42"
- cell $not $not$ls180.v:7416$2372
+ attribute \src "ls180.v:7412.18-7412.42"
+ cell $not $not$ls180.v:7412$2372
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdphy_clocker_clk0
- connect \Y $not$ls180.v:7416$2372_Y
+ connect \Y $not$ls180.v:7412$2372_Y
end
- attribute \src "ls180.v:7495.72-7495.101"
- cell $not $not$ls180.v:7495$2405
+ attribute \src "ls180.v:7491.72-7491.101"
+ cell $not $not$ls180.v:7491$2405
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_libresocsim_ram_bus_ack
- connect \Y $not$ls180.v:7495$2405_Y
+ connect \Y $not$ls180.v:7491$2405_Y
end
- attribute \src "ls180.v:7514.8-7514.38"
- cell $not $not$ls180.v:7514$2409
+ attribute \src "ls180.v:7510.8-7510.38"
+ cell $not $not$ls180.v:7510$2409
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_libresocsim_zero_trigger
- connect \Y $not$ls180.v:7514$2409_Y
+ connect \Y $not$ls180.v:7510$2409_Y
end
- attribute \src "ls180.v:7522.32-7522.55"
- cell $not $not$ls180.v:7522$2411
+ attribute \src "ls180.v:7518.32-7518.55"
+ cell $not $not$ls180.v:7518$2411
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_timer_done0
- connect \Y $not$ls180.v:7522$2411_Y
+ connect \Y $not$ls180.v:7518$2411_Y
end
- attribute \src "ls180.v:7592.136-7592.189"
- cell $not $not$ls180.v:7592$2426
+ attribute \src "ls180.v:7588.136-7588.189"
+ cell $not $not$ls180.v:7588$2426
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_replace
- connect \Y $not$ls180.v:7592$2426_Y
+ connect \Y $not$ls180.v:7588$2426_Y
end
- attribute \src "ls180.v:7598.136-7598.189"
- cell $not $not$ls180.v:7598$2431
+ attribute \src "ls180.v:7594.136-7594.189"
+ cell $not $not$ls180.v:7594$2431
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_replace
- connect \Y $not$ls180.v:7598$2431_Y
+ connect \Y $not$ls180.v:7594$2431_Y
end
- attribute \src "ls180.v:7599.8-7599.61"
- cell $not $not$ls180.v:7599$2433
+ attribute \src "ls180.v:7595.8-7595.61"
+ cell $not $not$ls180.v:7595$2433
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_do_read
- connect \Y $not$ls180.v:7599$2433_Y
+ connect \Y $not$ls180.v:7595$2433_Y
end
- attribute \src "ls180.v:7607.8-7607.56"
- cell $not $not$ls180.v:7607$2436
+ attribute \src "ls180.v:7603.8-7603.56"
+ cell $not $not$ls180.v:7603$2436
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine0_cmd_buffer_source_valid
- connect \Y $not$ls180.v:7607$2436_Y
+ connect \Y $not$ls180.v:7603$2436_Y
end
- attribute \src "ls180.v:7622.8-7622.46"
- cell $not $not$ls180.v:7622$2438
+ attribute \src "ls180.v:7618.8-7618.46"
+ cell $not $not$ls180.v:7618$2438
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine0_twtpcon_ready
- connect \Y $not$ls180.v:7622$2438_Y
+ connect \Y $not$ls180.v:7618$2438_Y
end
- attribute \src "ls180.v:7638.136-7638.189"
- cell $not $not$ls180.v:7638$2442
+ attribute \src "ls180.v:7634.136-7634.189"
+ cell $not $not$ls180.v:7634$2442
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_replace
- connect \Y $not$ls180.v:7638$2442_Y
+ connect \Y $not$ls180.v:7634$2442_Y
end
- attribute \src "ls180.v:7644.136-7644.189"
- cell $not $not$ls180.v:7644$2447
+ attribute \src "ls180.v:7640.136-7640.189"
+ cell $not $not$ls180.v:7640$2447
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_replace
- connect \Y $not$ls180.v:7644$2447_Y
+ connect \Y $not$ls180.v:7640$2447_Y
end
- attribute \src "ls180.v:7645.8-7645.61"
- cell $not $not$ls180.v:7645$2449
+ attribute \src "ls180.v:7641.8-7641.61"
+ cell $not $not$ls180.v:7641$2449
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_do_read
- connect \Y $not$ls180.v:7645$2449_Y
+ connect \Y $not$ls180.v:7641$2449_Y
end
- attribute \src "ls180.v:7653.8-7653.56"
- cell $not $not$ls180.v:7653$2452
+ attribute \src "ls180.v:7649.8-7649.56"
+ cell $not $not$ls180.v:7649$2452
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine1_cmd_buffer_source_valid
- connect \Y $not$ls180.v:7653$2452_Y
+ connect \Y $not$ls180.v:7649$2452_Y
end
- attribute \src "ls180.v:7668.8-7668.46"
- cell $not $not$ls180.v:7668$2454
+ attribute \src "ls180.v:7664.8-7664.46"
+ cell $not $not$ls180.v:7664$2454
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine1_twtpcon_ready
- connect \Y $not$ls180.v:7668$2454_Y
+ connect \Y $not$ls180.v:7664$2454_Y
end
- attribute \src "ls180.v:7684.136-7684.189"
- cell $not $not$ls180.v:7684$2458
+ attribute \src "ls180.v:7680.136-7680.189"
+ cell $not $not$ls180.v:7680$2458
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_replace
- connect \Y $not$ls180.v:7684$2458_Y
+ connect \Y $not$ls180.v:7680$2458_Y
end
- attribute \src "ls180.v:7690.136-7690.189"
- cell $not $not$ls180.v:7690$2463
+ attribute \src "ls180.v:7686.136-7686.189"
+ cell $not $not$ls180.v:7686$2463
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_replace
- connect \Y $not$ls180.v:7690$2463_Y
+ connect \Y $not$ls180.v:7686$2463_Y
end
- attribute \src "ls180.v:7691.8-7691.61"
- cell $not $not$ls180.v:7691$2465
+ attribute \src "ls180.v:7687.8-7687.61"
+ cell $not $not$ls180.v:7687$2465
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_do_read
- connect \Y $not$ls180.v:7691$2465_Y
+ connect \Y $not$ls180.v:7687$2465_Y
end
- attribute \src "ls180.v:7699.8-7699.56"
- cell $not $not$ls180.v:7699$2468
+ attribute \src "ls180.v:7695.8-7695.56"
+ cell $not $not$ls180.v:7695$2468
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine2_cmd_buffer_source_valid
- connect \Y $not$ls180.v:7699$2468_Y
+ connect \Y $not$ls180.v:7695$2468_Y
end
- attribute \src "ls180.v:7714.8-7714.46"
- cell $not $not$ls180.v:7714$2470
+ attribute \src "ls180.v:7710.8-7710.46"
+ cell $not $not$ls180.v:7710$2470
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine2_twtpcon_ready
- connect \Y $not$ls180.v:7714$2470_Y
+ connect \Y $not$ls180.v:7710$2470_Y
end
- attribute \src "ls180.v:7730.136-7730.189"
- cell $not $not$ls180.v:7730$2474
+ attribute \src "ls180.v:7726.136-7726.189"
+ cell $not $not$ls180.v:7726$2474
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_replace
- connect \Y $not$ls180.v:7730$2474_Y
+ connect \Y $not$ls180.v:7726$2474_Y
end
- attribute \src "ls180.v:7736.136-7736.189"
- cell $not $not$ls180.v:7736$2479
+ attribute \src "ls180.v:7732.136-7732.189"
+ cell $not $not$ls180.v:7732$2479
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_replace
- connect \Y $not$ls180.v:7736$2479_Y
+ connect \Y $not$ls180.v:7732$2479_Y
end
- attribute \src "ls180.v:7737.8-7737.61"
- cell $not $not$ls180.v:7737$2481
+ attribute \src "ls180.v:7733.8-7733.61"
+ cell $not $not$ls180.v:7733$2481
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_do_read
- connect \Y $not$ls180.v:7737$2481_Y
+ connect \Y $not$ls180.v:7733$2481_Y
end
- attribute \src "ls180.v:7745.8-7745.56"
- cell $not $not$ls180.v:7745$2484
+ attribute \src "ls180.v:7741.8-7741.56"
+ cell $not $not$ls180.v:7741$2484
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine3_cmd_buffer_source_valid
- connect \Y $not$ls180.v:7745$2484_Y
+ connect \Y $not$ls180.v:7741$2484_Y
end
- attribute \src "ls180.v:7760.8-7760.46"
- cell $not $not$ls180.v:7760$2486
+ attribute \src "ls180.v:7756.8-7756.46"
+ cell $not $not$ls180.v:7756$2486
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine3_twtpcon_ready
- connect \Y $not$ls180.v:7760$2486_Y
+ connect \Y $not$ls180.v:7756$2486_Y
end
- attribute \src "ls180.v:7768.7-7768.22"
- cell $not $not$ls180.v:7768$2489
+ attribute \src "ls180.v:7764.7-7764.22"
+ cell $not $not$ls180.v:7764$2489
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_en0
- connect \Y $not$ls180.v:7768$2489_Y
+ connect \Y $not$ls180.v:7764$2489_Y
end
- attribute \src "ls180.v:7771.8-7771.29"
- cell $not $not$ls180.v:7771$2490
+ attribute \src "ls180.v:7767.8-7767.29"
+ cell $not $not$ls180.v:7767$2490
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_max_time0
- connect \Y $not$ls180.v:7771$2490_Y
+ connect \Y $not$ls180.v:7767$2490_Y
end
- attribute \src "ls180.v:7775.7-7775.22"
- cell $not $not$ls180.v:7775$2492
+ attribute \src "ls180.v:7771.7-7771.22"
+ cell $not $not$ls180.v:7771$2492
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_en1
- connect \Y $not$ls180.v:7775$2492_Y
+ connect \Y $not$ls180.v:7771$2492_Y
end
- attribute \src "ls180.v:7778.8-7778.29"
- cell $not $not$ls180.v:7778$2493
+ attribute \src "ls180.v:7774.8-7774.29"
+ cell $not $not$ls180.v:7774$2493
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_max_time1
- connect \Y $not$ls180.v:7778$2493_Y
+ connect \Y $not$ls180.v:7774$2493_Y
end
- attribute \src "ls180.v:7897.30-7897.60"
- cell $not $not$ls180.v:7897$2495
+ attribute \src "ls180.v:7893.30-7893.60"
+ cell $not $not$ls180.v:7893$2495
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_sync_rhs_array_muxed2
- connect \Y $not$ls180.v:7897$2495_Y
+ connect \Y $not$ls180.v:7893$2495_Y
end
- attribute \src "ls180.v:7898.30-7898.60"
- cell $not $not$ls180.v:7898$2496
+ attribute \src "ls180.v:7894.30-7894.60"
+ cell $not $not$ls180.v:7894$2496
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_sync_rhs_array_muxed3
- connect \Y $not$ls180.v:7898$2496_Y
+ connect \Y $not$ls180.v:7894$2496_Y
end
- attribute \src "ls180.v:7899.29-7899.59"
- cell $not $not$ls180.v:7899$2497
+ attribute \src "ls180.v:7895.29-7895.59"
+ cell $not $not$ls180.v:7895$2497
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_sync_rhs_array_muxed4
- connect \Y $not$ls180.v:7899$2497_Y
+ connect \Y $not$ls180.v:7895$2497_Y
end
- attribute \src "ls180.v:7910.8-7910.33"
- cell $not $not$ls180.v:7910$2498
+ attribute \src "ls180.v:7906.8-7906.33"
+ cell $not $not$ls180.v:7906$2498
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_tccdcon_ready
- connect \Y $not$ls180.v:7910$2498_Y
+ connect \Y $not$ls180.v:7906$2498_Y
end
- attribute \src "ls180.v:7925.8-7925.33"
- cell $not $not$ls180.v:7925$2501
+ attribute \src "ls180.v:7921.8-7921.33"
+ cell $not $not$ls180.v:7921$2501
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_twtrcon_ready
- connect \Y $not$ls180.v:7925$2501_Y
+ connect \Y $not$ls180.v:7921$2501_Y
end
- attribute \src "ls180.v:7961.36-7961.58"
- cell $not $not$ls180.v:7961$2531
+ attribute \src "ls180.v:7957.36-7957.58"
+ cell $not $not$ls180.v:7957$2531
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_uart_phy_tx_busy
- connect \Y $not$ls180.v:7961$2531_Y
+ connect \Y $not$ls180.v:7957$2531_Y
end
- attribute \src "ls180.v:7961.64-7961.89"
- cell $not $not$ls180.v:7961$2533
+ attribute \src "ls180.v:7957.64-7957.89"
+ cell $not $not$ls180.v:7957$2533
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_uart_phy_sink_ready
- connect \Y $not$ls180.v:7961$2533_Y
+ connect \Y $not$ls180.v:7957$2533_Y
end
- attribute \src "ls180.v:7990.7-7990.29"
- cell $not $not$ls180.v:7990$2540
+ attribute \src "ls180.v:7986.7-7986.29"
+ cell $not $not$ls180.v:7986$2540
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_uart_phy_rx_busy
- connect \Y $not$ls180.v:7990$2540_Y
+ connect \Y $not$ls180.v:7986$2540_Y
end
- attribute \src "ls180.v:7991.9-7991.26"
- cell $not $not$ls180.v:7991$2541
+ attribute \src "ls180.v:7987.9-7987.26"
+ cell $not $not$ls180.v:7987$2541
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_uart_phy_rx
- connect \Y $not$ls180.v:7991$2541_Y
+ connect \Y $not$ls180.v:7987$2541_Y
end
- attribute \src "ls180.v:8024.8-8024.29"
- cell $not $not$ls180.v:8024$2547
+ attribute \src "ls180.v:8020.8-8020.29"
+ cell $not $not$ls180.v:8020$2547
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_uart_tx_trigger
- connect \Y $not$ls180.v:8024$2547_Y
+ connect \Y $not$ls180.v:8020$2547_Y
end
- attribute \src "ls180.v:8031.8-8031.29"
- cell $not $not$ls180.v:8031$2549
+ attribute \src "ls180.v:8027.8-8027.29"
+ cell $not $not$ls180.v:8027$2549
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_uart_rx_trigger
- connect \Y $not$ls180.v:8031$2549_Y
+ connect \Y $not$ls180.v:8027$2549_Y
end
- attribute \src "ls180.v:8041.80-8041.106"
- cell $not $not$ls180.v:8041$2552
+ attribute \src "ls180.v:8037.80-8037.106"
+ cell $not $not$ls180.v:8037$2552
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_uart_tx_fifo_replace
- connect \Y $not$ls180.v:8041$2552_Y
+ connect \Y $not$ls180.v:8037$2552_Y
end
- attribute \src "ls180.v:8047.80-8047.106"
- cell $not $not$ls180.v:8047$2557
+ attribute \src "ls180.v:8043.80-8043.106"
+ cell $not $not$ls180.v:8043$2557
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_uart_tx_fifo_replace
- connect \Y $not$ls180.v:8047$2557_Y
+ connect \Y $not$ls180.v:8043$2557_Y
end
- attribute \src "ls180.v:8048.8-8048.34"
- cell $not $not$ls180.v:8048$2559
+ attribute \src "ls180.v:8044.8-8044.34"
+ cell $not $not$ls180.v:8044$2559
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_uart_tx_fifo_do_read
- connect \Y $not$ls180.v:8048$2559_Y
+ connect \Y $not$ls180.v:8044$2559_Y
end
- attribute \src "ls180.v:8063.80-8063.106"
- cell $not $not$ls180.v:8063$2563
+ attribute \src "ls180.v:8059.80-8059.106"
+ cell $not $not$ls180.v:8059$2563
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_uart_rx_fifo_replace
- connect \Y $not$ls180.v:8063$2563_Y
+ connect \Y $not$ls180.v:8059$2563_Y
end
- attribute \src "ls180.v:8069.80-8069.106"
- cell $not $not$ls180.v:8069$2568
+ attribute \src "ls180.v:8065.80-8065.106"
+ cell $not $not$ls180.v:8065$2568
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_uart_rx_fifo_replace
- connect \Y $not$ls180.v:8069$2568_Y
+ connect \Y $not$ls180.v:8065$2568_Y
end
- attribute \src "ls180.v:8070.8-8070.34"
- cell $not $not$ls180.v:8070$2570
+ attribute \src "ls180.v:8066.8-8066.34"
+ cell $not $not$ls180.v:8066$2570
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_uart_rx_fifo_do_read
- connect \Y $not$ls180.v:8070$2570_Y
+ connect \Y $not$ls180.v:8066$2570_Y
end
- attribute \src "ls180.v:8101.22-8101.41"
- cell $not $not$ls180.v:8101$2574
+ attribute \src "ls180.v:8097.22-8097.41"
+ cell $not $not$ls180.v:8097$2574
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_spimaster6_cs
- connect \Y $not$ls180.v:8101$2574_Y
+ connect \Y $not$ls180.v:8097$2574_Y
end
- attribute \src "ls180.v:8101.46-8101.73"
- cell $not $not$ls180.v:8101$2575
+ attribute \src "ls180.v:8097.46-8097.73"
+ cell $not $not$ls180.v:8097$2575
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_spimaster26_cs_enable
- connect \Y $not$ls180.v:8101$2575_Y
+ connect \Y $not$ls180.v:8097$2575_Y
end
- attribute \src "ls180.v:8136.22-8136.40"
- cell $not $not$ls180.v:8136$2579
+ attribute \src "ls180.v:8132.22-8132.40"
+ cell $not $not$ls180.v:8132$2579
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_spisdcard_cs
- connect \Y $not$ls180.v:8136$2579_Y
+ connect \Y $not$ls180.v:8132$2579_Y
end
- attribute \src "ls180.v:8136.45-8136.70"
- cell $not $not$ls180.v:8136$2580
+ attribute \src "ls180.v:8132.45-8132.70"
+ cell $not $not$ls180.v:8132$2580
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_spisdcard_cs_enable
- connect \Y $not$ls180.v:8136$2580_Y
+ connect \Y $not$ls180.v:8132$2580_Y
end
- attribute \src "ls180.v:8190.7-8190.31"
- cell $not $not$ls180.v:8190$2591
+ attribute \src "ls180.v:8186.7-8186.31"
+ cell $not $not$ls180.v:8186$2591
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdphy_clocker_stop
- connect \Y $not$ls180.v:8190$2591_Y
+ connect \Y $not$ls180.v:8186$2591_Y
end
- attribute \src "ls180.v:8262.8-8262.46"
- cell $not $not$ls180.v:8262$2603
+ attribute \src "ls180.v:8258.8-8258.46"
+ cell $not $not$ls180.v:8258$2603
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdphy_cmdr_cmdr_buf_source_valid
- connect \Y $not$ls180.v:8262$2603_Y
+ connect \Y $not$ls180.v:8258$2603_Y
end
- attribute \src "ls180.v:8343.8-8343.47"
- cell $not $not$ls180.v:8343$2615
+ attribute \src "ls180.v:8339.8-8339.47"
+ cell $not $not$ls180.v:8339$2615
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdphy_dataw_crcr_buf_source_valid
- connect \Y $not$ls180.v:8343$2615_Y
+ connect \Y $not$ls180.v:8339$2615_Y
end
- attribute \src "ls180.v:8404.8-8404.48"
- cell $not $not$ls180.v:8404$2627
+ attribute \src "ls180.v:8400.8-8400.48"
+ cell $not $not$ls180.v:8400$2627
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdphy_datar_datar_buf_source_valid
- connect \Y $not$ls180.v:8404$2627_Y
+ connect \Y $not$ls180.v:8400$2627_Y
end
- attribute \src "ls180.v:8574.88-8574.118"
- cell $not $not$ls180.v:8574$2641
+ attribute \src "ls180.v:8570.88-8570.118"
+ cell $not $not$ls180.v:8570$2641
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdblock2mem_fifo_replace
- connect \Y $not$ls180.v:8574$2641_Y
+ connect \Y $not$ls180.v:8570$2641_Y
end
- attribute \src "ls180.v:8580.88-8580.118"
- cell $not $not$ls180.v:8580$2646
+ attribute \src "ls180.v:8576.88-8576.118"
+ cell $not $not$ls180.v:8576$2646
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdblock2mem_fifo_replace
- connect \Y $not$ls180.v:8580$2646_Y
+ connect \Y $not$ls180.v:8576$2646_Y
end
- attribute \src "ls180.v:8581.8-8581.38"
- cell $not $not$ls180.v:8581$2648
+ attribute \src "ls180.v:8577.8-8577.38"
+ cell $not $not$ls180.v:8577$2648
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdblock2mem_fifo_do_read
- connect \Y $not$ls180.v:8581$2648_Y
+ connect \Y $not$ls180.v:8577$2648_Y
end
- attribute \src "ls180.v:8660.88-8660.118"
- cell $not $not$ls180.v:8660$2663
+ attribute \src "ls180.v:8656.88-8656.118"
+ cell $not $not$ls180.v:8656$2663
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdmem2block_fifo_replace
- connect \Y $not$ls180.v:8660$2663_Y
+ connect \Y $not$ls180.v:8656$2663_Y
end
- attribute \src "ls180.v:8666.88-8666.118"
- cell $not $not$ls180.v:8666$2668
+ attribute \src "ls180.v:8662.88-8662.118"
+ cell $not $not$ls180.v:8662$2668
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdmem2block_fifo_replace
- connect \Y $not$ls180.v:8666$2668_Y
+ connect \Y $not$ls180.v:8662$2668_Y
end
- attribute \src "ls180.v:8667.8-8667.38"
- cell $not $not$ls180.v:8667$2670
+ attribute \src "ls180.v:8663.8-8663.38"
+ cell $not $not$ls180.v:8663$2670
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdmem2block_fifo_do_read
- connect \Y $not$ls180.v:8667$2670_Y
+ connect \Y $not$ls180.v:8663$2670_Y
end
- attribute \src "ls180.v:8687.9-8687.28"
- cell $not $not$ls180.v:8687$2673
+ attribute \src "ls180.v:8683.9-8683.28"
+ cell $not $not$ls180.v:8683$2673
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_request [0]
- connect \Y $not$ls180.v:8687$2673_Y
+ connect \Y $not$ls180.v:8683$2673_Y
end
- attribute \src "ls180.v:8706.9-8706.28"
- cell $not $not$ls180.v:8706$2674
+ attribute \src "ls180.v:8702.9-8702.28"
+ cell $not $not$ls180.v:8702$2674
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_request [1]
- connect \Y $not$ls180.v:8706$2674_Y
+ connect \Y $not$ls180.v:8702$2674_Y
end
- attribute \src "ls180.v:8725.9-8725.28"
- cell $not $not$ls180.v:8725$2675
+ attribute \src "ls180.v:8721.9-8721.28"
+ cell $not $not$ls180.v:8721$2675
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_request [2]
- connect \Y $not$ls180.v:8725$2675_Y
+ connect \Y $not$ls180.v:8721$2675_Y
end
- attribute \src "ls180.v:8744.9-8744.28"
- cell $not $not$ls180.v:8744$2676
+ attribute \src "ls180.v:8740.9-8740.28"
+ cell $not $not$ls180.v:8740$2676
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_request [3]
- connect \Y $not$ls180.v:8744$2676_Y
+ connect \Y $not$ls180.v:8740$2676_Y
end
- attribute \src "ls180.v:8763.9-8763.28"
- cell $not $not$ls180.v:8763$2677
+ attribute \src "ls180.v:8759.9-8759.28"
+ cell $not $not$ls180.v:8759$2677
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_request [4]
- connect \Y $not$ls180.v:8763$2677_Y
+ connect \Y $not$ls180.v:8759$2677_Y
end
- attribute \src "ls180.v:8784.8-8784.21"
- cell $not $not$ls180.v:8784$2678
+ attribute \src "ls180.v:8780.8-8780.21"
+ cell $not $not$ls180.v:8780$2678
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_done
- connect \Y $not$ls180.v:8784$2678_Y
+ connect \Y $not$ls180.v:8780$2678_Y
end
- attribute \src "ls180.v:10283.8-10283.51"
- cell $or $or$ls180.v:10283$2750
+ attribute \src "ls180.v:10279.8-10279.51"
+ cell $or $or$ls180.v:10279$2750
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sys_rst_1
connect \B \main_libresocsim_libresoc_reset
- connect \Y $or$ls180.v:10283$2750_Y
+ connect \Y $or$ls180.v:10279$2750_Y
end
- attribute \src "ls180.v:2818.10-2818.96"
- cell $or $or$ls180.v:2818$21
+ attribute \src "ls180.v:2814.10-2814.96"
+ cell $or $or$ls180.v:2814$21
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_libresocsim_interface0_converted_interface_ack
connect \B \main_libresocsim_converter0_skip
- connect \Y $or$ls180.v:2818$21_Y
+ connect \Y $or$ls180.v:2814$21_Y
end
- attribute \src "ls180.v:2878.10-2878.96"
- cell $or $or$ls180.v:2878$32
+ attribute \src "ls180.v:2874.10-2874.96"
+ cell $or $or$ls180.v:2874$32
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_libresocsim_interface1_converted_interface_ack
connect \B \main_libresocsim_converter1_skip
- connect \Y $or$ls180.v:2878$32_Y
+ connect \Y $or$ls180.v:2874$32_Y
end
- attribute \src "ls180.v:2938.10-2938.96"
- cell $or $or$ls180.v:2938$43
+ attribute \src "ls180.v:2934.10-2934.96"
+ cell $or $or$ls180.v:2934$43
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_libresocsim_interface2_converted_interface_ack
connect \B \main_libresocsim_converter2_skip
- connect \Y $or$ls180.v:2938$43_Y
+ connect \Y $or$ls180.v:2934$43_Y
end
- attribute \src "ls180.v:3130.39-3130.105"
- cell $or $or$ls180.v:3130$75
+ attribute \src "ls180.v:3126.39-3126.105"
+ cell $or $or$ls180.v:3126$75
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_sequencer_start0
- connect \B $ne$ls180.v:3130$74_Y
- connect \Y $or$ls180.v:3130$75_Y
+ connect \B $ne$ls180.v:3126$74_Y
+ connect \Y $or$ls180.v:3126$75_Y
end
- attribute \src "ls180.v:3173.59-3173.140"
- cell $or $or$ls180.v:3173$79
+ attribute \src "ls180.v:3169.59-3169.140"
+ cell $or $or$ls180.v:3169$79
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine0_req_wdata_ready
connect \B \main_sdram_bankmachine0_req_rdata_valid
- connect \Y $or$ls180.v:3173$79_Y
+ connect \Y $or$ls180.v:3169$79_Y
end
- attribute \src "ls180.v:3174.44-3174.151"
- cell $or $or$ls180.v:3174$80
+ attribute \src "ls180.v:3170.44-3170.151"
+ cell $or $or$ls180.v:3170$80
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_source_valid
connect \B \main_sdram_bankmachine0_cmd_buffer_source_valid
- connect \Y $or$ls180.v:3174$80_Y
+ connect \Y $or$ls180.v:3170$80_Y
end
- attribute \src "ls180.v:3182.45-3182.170"
- cell $or $or$ls180.v:3182$84
+ attribute \src "ls180.v:3178.45-3178.170"
+ cell $or $or$ls180.v:3178$84
parameter \A_SIGNED 0
parameter \A_WIDTH 13
parameter \B_SIGNED 0
parameter \B_WIDTH 13
parameter \Y_WIDTH 13
- connect \A $sshl$ls180.v:3182$83_Y
+ connect \A $sshl$ls180.v:3178$83_Y
connect \B { 4'0000 \main_sdram_bankmachine0_cmd_buffer_source_payload_addr [8:0] }
- connect \Y $or$ls180.v:3182$84_Y
+ connect \Y $or$ls180.v:3178$84_Y
end
- attribute \src "ls180.v:3219.127-3219.245"
- cell $or $or$ls180.v:3219$97
+ attribute \src "ls180.v:3215.127-3215.245"
+ cell $or $or$ls180.v:3215$97
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable
connect \B \main_sdram_bankmachine0_cmd_buffer_lookahead_replace
- connect \Y $or$ls180.v:3219$97_Y
+ connect \Y $or$ls180.v:3215$97_Y
end
- attribute \src "ls180.v:3225.57-3225.157"
- cell $or $or$ls180.v:3225$103
+ attribute \src "ls180.v:3221.57-3221.157"
+ cell $or $or$ls180.v:3221$103
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $not$ls180.v:3225$102_Y
+ connect \A $not$ls180.v:3221$102_Y
connect \B \main_sdram_bankmachine0_cmd_buffer_source_ready
- connect \Y $or$ls180.v:3225$103_Y
+ connect \Y $or$ls180.v:3221$103_Y
end
- attribute \src "ls180.v:3330.59-3330.140"
- cell $or $or$ls180.v:3330$109
+ attribute \src "ls180.v:3326.59-3326.140"
+ cell $or $or$ls180.v:3326$109
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine1_req_wdata_ready
connect \B \main_sdram_bankmachine1_req_rdata_valid
- connect \Y $or$ls180.v:3330$109_Y
+ connect \Y $or$ls180.v:3326$109_Y
end
- attribute \src "ls180.v:3331.44-3331.151"
- cell $or $or$ls180.v:3331$110
+ attribute \src "ls180.v:3327.44-3327.151"
+ cell $or $or$ls180.v:3327$110
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_source_valid
connect \B \main_sdram_bankmachine1_cmd_buffer_source_valid
- connect \Y $or$ls180.v:3331$110_Y
+ connect \Y $or$ls180.v:3327$110_Y
end
- attribute \src "ls180.v:3339.45-3339.170"
- cell $or $or$ls180.v:3339$114
+ attribute \src "ls180.v:3335.45-3335.170"
+ cell $or $or$ls180.v:3335$114
parameter \A_SIGNED 0
parameter \A_WIDTH 13
parameter \B_SIGNED 0
parameter \B_WIDTH 13
parameter \Y_WIDTH 13
- connect \A $sshl$ls180.v:3339$113_Y
+ connect \A $sshl$ls180.v:3335$113_Y
connect \B { 4'0000 \main_sdram_bankmachine1_cmd_buffer_source_payload_addr [8:0] }
- connect \Y $or$ls180.v:3339$114_Y
+ connect \Y $or$ls180.v:3335$114_Y
end
- attribute \src "ls180.v:3376.127-3376.245"
- cell $or $or$ls180.v:3376$127
+ attribute \src "ls180.v:3372.127-3372.245"
+ cell $or $or$ls180.v:3372$127
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable
connect \B \main_sdram_bankmachine1_cmd_buffer_lookahead_replace
- connect \Y $or$ls180.v:3376$127_Y
+ connect \Y $or$ls180.v:3372$127_Y
end
- attribute \src "ls180.v:3382.57-3382.157"
- cell $or $or$ls180.v:3382$133
+ attribute \src "ls180.v:3378.57-3378.157"
+ cell $or $or$ls180.v:3378$133
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $not$ls180.v:3382$132_Y
+ connect \A $not$ls180.v:3378$132_Y
connect \B \main_sdram_bankmachine1_cmd_buffer_source_ready
- connect \Y $or$ls180.v:3382$133_Y
+ connect \Y $or$ls180.v:3378$133_Y
end
- attribute \src "ls180.v:3487.59-3487.140"
- cell $or $or$ls180.v:3487$139
+ attribute \src "ls180.v:3483.59-3483.140"
+ cell $or $or$ls180.v:3483$139
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine2_req_wdata_ready
connect \B \main_sdram_bankmachine2_req_rdata_valid
- connect \Y $or$ls180.v:3487$139_Y
+ connect \Y $or$ls180.v:3483$139_Y
end
- attribute \src "ls180.v:3488.44-3488.151"
- cell $or $or$ls180.v:3488$140
+ attribute \src "ls180.v:3484.44-3484.151"
+ cell $or $or$ls180.v:3484$140
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_source_valid
connect \B \main_sdram_bankmachine2_cmd_buffer_source_valid
- connect \Y $or$ls180.v:3488$140_Y
+ connect \Y $or$ls180.v:3484$140_Y
end
- attribute \src "ls180.v:3496.45-3496.170"
- cell $or $or$ls180.v:3496$144
+ attribute \src "ls180.v:3492.45-3492.170"
+ cell $or $or$ls180.v:3492$144
parameter \A_SIGNED 0
parameter \A_WIDTH 13
parameter \B_SIGNED 0
parameter \B_WIDTH 13
parameter \Y_WIDTH 13
- connect \A $sshl$ls180.v:3496$143_Y
+ connect \A $sshl$ls180.v:3492$143_Y
connect \B { 4'0000 \main_sdram_bankmachine2_cmd_buffer_source_payload_addr [8:0] }
- connect \Y $or$ls180.v:3496$144_Y
+ connect \Y $or$ls180.v:3492$144_Y
end
- attribute \src "ls180.v:3533.127-3533.245"
- cell $or $or$ls180.v:3533$157
+ attribute \src "ls180.v:3529.127-3529.245"
+ cell $or $or$ls180.v:3529$157
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable
connect \B \main_sdram_bankmachine2_cmd_buffer_lookahead_replace
- connect \Y $or$ls180.v:3533$157_Y
+ connect \Y $or$ls180.v:3529$157_Y
end
- attribute \src "ls180.v:3539.57-3539.157"
- cell $or $or$ls180.v:3539$163
+ attribute \src "ls180.v:3535.57-3535.157"
+ cell $or $or$ls180.v:3535$163
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $not$ls180.v:3539$162_Y
+ connect \A $not$ls180.v:3535$162_Y
connect \B \main_sdram_bankmachine2_cmd_buffer_source_ready
- connect \Y $or$ls180.v:3539$163_Y
+ connect \Y $or$ls180.v:3535$163_Y
end
- attribute \src "ls180.v:3644.59-3644.140"
- cell $or $or$ls180.v:3644$169
+ attribute \src "ls180.v:3640.59-3640.140"
+ cell $or $or$ls180.v:3640$169
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine3_req_wdata_ready
connect \B \main_sdram_bankmachine3_req_rdata_valid
- connect \Y $or$ls180.v:3644$169_Y
+ connect \Y $or$ls180.v:3640$169_Y
end
- attribute \src "ls180.v:3645.44-3645.151"
- cell $or $or$ls180.v:3645$170
+ attribute \src "ls180.v:3641.44-3641.151"
+ cell $or $or$ls180.v:3641$170
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_source_valid
connect \B \main_sdram_bankmachine3_cmd_buffer_source_valid
- connect \Y $or$ls180.v:3645$170_Y
+ connect \Y $or$ls180.v:3641$170_Y
end
- attribute \src "ls180.v:3653.45-3653.170"
- cell $or $or$ls180.v:3653$174
+ attribute \src "ls180.v:3649.45-3649.170"
+ cell $or $or$ls180.v:3649$174
parameter \A_SIGNED 0
parameter \A_WIDTH 13
parameter \B_SIGNED 0
parameter \B_WIDTH 13
parameter \Y_WIDTH 13
- connect \A $sshl$ls180.v:3653$173_Y
+ connect \A $sshl$ls180.v:3649$173_Y
connect \B { 4'0000 \main_sdram_bankmachine3_cmd_buffer_source_payload_addr [8:0] }
- connect \Y $or$ls180.v:3653$174_Y
+ connect \Y $or$ls180.v:3649$174_Y
end
- attribute \src "ls180.v:3690.127-3690.245"
- cell $or $or$ls180.v:3690$187
+ attribute \src "ls180.v:3686.127-3686.245"
+ cell $or $or$ls180.v:3686$187
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable
connect \B \main_sdram_bankmachine3_cmd_buffer_lookahead_replace
- connect \Y $or$ls180.v:3690$187_Y
+ connect \Y $or$ls180.v:3686$187_Y
end
- attribute \src "ls180.v:3696.57-3696.157"
- cell $or $or$ls180.v:3696$193
+ attribute \src "ls180.v:3692.57-3692.157"
+ cell $or $or$ls180.v:3692$193
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $not$ls180.v:3696$192_Y
+ connect \A $not$ls180.v:3692$192_Y
connect \B \main_sdram_bankmachine3_cmd_buffer_source_ready
- connect \Y $or$ls180.v:3696$193_Y
+ connect \Y $or$ls180.v:3692$193_Y
end
- attribute \src "ls180.v:3795.107-3795.193"
- cell $or $or$ls180.v:3795$213
+ attribute \src "ls180.v:3791.107-3791.193"
+ cell $or $or$ls180.v:3791$213
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_choose_req_cmd_payload_is_write
connect \B \main_sdram_choose_req_cmd_payload_is_read
- connect \Y $or$ls180.v:3795$213_Y
+ connect \Y $or$ls180.v:3791$213_Y
end
- attribute \src "ls180.v:3798.39-3798.204"
- cell $or $or$ls180.v:3798$219
+ attribute \src "ls180.v:3794.39-3794.204"
+ cell $or $or$ls180.v:3794$219
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3798$217_Y
- connect \B $and$ls180.v:3798$218_Y
- connect \Y $or$ls180.v:3798$219_Y
+ connect \A $and$ls180.v:3794$217_Y
+ connect \B $and$ls180.v:3794$218_Y
+ connect \Y $or$ls180.v:3794$219_Y
end
- attribute \src "ls180.v:3798.38-3798.289"
- cell $or $or$ls180.v:3798$221
+ attribute \src "ls180.v:3794.38-3794.289"
+ cell $or $or$ls180.v:3794$221
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:3798$219_Y
- connect \B $and$ls180.v:3798$220_Y
- connect \Y $or$ls180.v:3798$221_Y
+ connect \A $or$ls180.v:3794$219_Y
+ connect \B $and$ls180.v:3794$220_Y
+ connect \Y $or$ls180.v:3794$221_Y
end
- attribute \src "ls180.v:3798.37-3798.374"
- cell $or $or$ls180.v:3798$223
+ attribute \src "ls180.v:3794.37-3794.374"
+ cell $or $or$ls180.v:3794$223
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:3798$221_Y
- connect \B $and$ls180.v:3798$222_Y
- connect \Y $or$ls180.v:3798$223_Y
+ connect \A $or$ls180.v:3794$221_Y
+ connect \B $and$ls180.v:3794$222_Y
+ connect \Y $or$ls180.v:3794$223_Y
end
- attribute \src "ls180.v:3799.40-3799.207"
- cell $or $or$ls180.v:3799$226
+ attribute \src "ls180.v:3795.40-3795.207"
+ cell $or $or$ls180.v:3795$226
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3799$224_Y
- connect \B $and$ls180.v:3799$225_Y
- connect \Y $or$ls180.v:3799$226_Y
+ connect \A $and$ls180.v:3795$224_Y
+ connect \B $and$ls180.v:3795$225_Y
+ connect \Y $or$ls180.v:3795$226_Y
end
- attribute \src "ls180.v:3799.39-3799.293"
- cell $or $or$ls180.v:3799$228
+ attribute \src "ls180.v:3795.39-3795.293"
+ cell $or $or$ls180.v:3795$228
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:3799$226_Y
- connect \B $and$ls180.v:3799$227_Y
- connect \Y $or$ls180.v:3799$228_Y
+ connect \A $or$ls180.v:3795$226_Y
+ connect \B $and$ls180.v:3795$227_Y
+ connect \Y $or$ls180.v:3795$228_Y
end
- attribute \src "ls180.v:3799.38-3799.379"
- cell $or $or$ls180.v:3799$230
+ attribute \src "ls180.v:3795.38-3795.379"
+ cell $or $or$ls180.v:3795$230
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:3799$228_Y
- connect \B $and$ls180.v:3799$229_Y
- connect \Y $or$ls180.v:3799$230_Y
+ connect \A $or$ls180.v:3795$228_Y
+ connect \B $and$ls180.v:3795$229_Y
+ connect \Y $or$ls180.v:3795$230_Y
end
- attribute \src "ls180.v:3812.158-3812.332"
- cell $or $or$ls180.v:3812$244
+ attribute \src "ls180.v:3808.158-3808.332"
+ cell $or $or$ls180.v:3808$244
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $not$ls180.v:3812$243_Y
+ connect \A $not$ls180.v:3808$243_Y
connect \B \main_sdram_choose_cmd_want_activates
- connect \Y $or$ls180.v:3812$244_Y
+ connect \Y $or$ls180.v:3808$244_Y
end
- attribute \src "ls180.v:3812.75-3812.506"
- cell $or $or$ls180.v:3812$249
+ attribute \src "ls180.v:3808.75-3808.506"
+ cell $or $or$ls180.v:3808$249
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3812$245_Y
- connect \B $and$ls180.v:3812$248_Y
- connect \Y $or$ls180.v:3812$249_Y
+ connect \A $and$ls180.v:3808$245_Y
+ connect \B $and$ls180.v:3808$248_Y
+ connect \Y $or$ls180.v:3808$249_Y
end
- attribute \src "ls180.v:3813.158-3813.332"
- cell $or $or$ls180.v:3813$257
+ attribute \src "ls180.v:3809.158-3809.332"
+ cell $or $or$ls180.v:3809$257
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $not$ls180.v:3813$256_Y
+ connect \A $not$ls180.v:3809$256_Y
connect \B \main_sdram_choose_cmd_want_activates
- connect \Y $or$ls180.v:3813$257_Y
+ connect \Y $or$ls180.v:3809$257_Y
end
- attribute \src "ls180.v:3813.75-3813.506"
- cell $or $or$ls180.v:3813$262
+ attribute \src "ls180.v:3809.75-3809.506"
+ cell $or $or$ls180.v:3809$262
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3813$258_Y
- connect \B $and$ls180.v:3813$261_Y
- connect \Y $or$ls180.v:3813$262_Y
+ connect \A $and$ls180.v:3809$258_Y
+ connect \B $and$ls180.v:3809$261_Y
+ connect \Y $or$ls180.v:3809$262_Y
end
- attribute \src "ls180.v:3814.158-3814.332"
- cell $or $or$ls180.v:3814$270
+ attribute \src "ls180.v:3810.158-3810.332"
+ cell $or $or$ls180.v:3810$270
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $not$ls180.v:3814$269_Y
+ connect \A $not$ls180.v:3810$269_Y
connect \B \main_sdram_choose_cmd_want_activates
- connect \Y $or$ls180.v:3814$270_Y
+ connect \Y $or$ls180.v:3810$270_Y
end
- attribute \src "ls180.v:3814.75-3814.506"
- cell $or $or$ls180.v:3814$275
+ attribute \src "ls180.v:3810.75-3810.506"
+ cell $or $or$ls180.v:3810$275
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3814$271_Y
- connect \B $and$ls180.v:3814$274_Y
- connect \Y $or$ls180.v:3814$275_Y
+ connect \A $and$ls180.v:3810$271_Y
+ connect \B $and$ls180.v:3810$274_Y
+ connect \Y $or$ls180.v:3810$275_Y
end
- attribute \src "ls180.v:3815.158-3815.332"
- cell $or $or$ls180.v:3815$283
+ attribute \src "ls180.v:3811.158-3811.332"
+ cell $or $or$ls180.v:3811$283
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $not$ls180.v:3815$282_Y
+ connect \A $not$ls180.v:3811$282_Y
connect \B \main_sdram_choose_cmd_want_activates
- connect \Y $or$ls180.v:3815$283_Y
+ connect \Y $or$ls180.v:3811$283_Y
end
- attribute \src "ls180.v:3815.75-3815.506"
- cell $or $or$ls180.v:3815$288
+ attribute \src "ls180.v:3811.75-3811.506"
+ cell $or $or$ls180.v:3811$288
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3815$284_Y
- connect \B $and$ls180.v:3815$287_Y
- connect \Y $or$ls180.v:3815$288_Y
+ connect \A $and$ls180.v:3811$284_Y
+ connect \B $and$ls180.v:3811$287_Y
+ connect \Y $or$ls180.v:3811$288_Y
end
- attribute \src "ls180.v:3842.36-3842.104"
- cell $or $or$ls180.v:3842$294
+ attribute \src "ls180.v:3838.36-3838.104"
+ cell $or $or$ls180.v:3838$294
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_choose_cmd_cmd_ready
- connect \B $not$ls180.v:3842$293_Y
- connect \Y $or$ls180.v:3842$294_Y
+ connect \B $not$ls180.v:3838$293_Y
+ connect \Y $or$ls180.v:3838$294_Y
end
- attribute \src "ls180.v:3845.158-3845.332"
- cell $or $or$ls180.v:3845$302
+ attribute \src "ls180.v:3841.158-3841.332"
+ cell $or $or$ls180.v:3841$302
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $not$ls180.v:3845$301_Y
+ connect \A $not$ls180.v:3841$301_Y
connect \B \main_sdram_choose_req_want_activates
- connect \Y $or$ls180.v:3845$302_Y
+ connect \Y $or$ls180.v:3841$302_Y
end
- attribute \src "ls180.v:3845.75-3845.506"
- cell $or $or$ls180.v:3845$307
+ attribute \src "ls180.v:3841.75-3841.506"
+ cell $or $or$ls180.v:3841$307
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3845$303_Y
- connect \B $and$ls180.v:3845$306_Y
- connect \Y $or$ls180.v:3845$307_Y
+ connect \A $and$ls180.v:3841$303_Y
+ connect \B $and$ls180.v:3841$306_Y
+ connect \Y $or$ls180.v:3841$307_Y
end
- attribute \src "ls180.v:3846.158-3846.332"
- cell $or $or$ls180.v:3846$315
+ attribute \src "ls180.v:3842.158-3842.332"
+ cell $or $or$ls180.v:3842$315
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $not$ls180.v:3846$314_Y
+ connect \A $not$ls180.v:3842$314_Y
connect \B \main_sdram_choose_req_want_activates
- connect \Y $or$ls180.v:3846$315_Y
+ connect \Y $or$ls180.v:3842$315_Y
end
- attribute \src "ls180.v:3846.75-3846.506"
- cell $or $or$ls180.v:3846$320
+ attribute \src "ls180.v:3842.75-3842.506"
+ cell $or $or$ls180.v:3842$320
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3846$316_Y
- connect \B $and$ls180.v:3846$319_Y
- connect \Y $or$ls180.v:3846$320_Y
+ connect \A $and$ls180.v:3842$316_Y
+ connect \B $and$ls180.v:3842$319_Y
+ connect \Y $or$ls180.v:3842$320_Y
end
- attribute \src "ls180.v:3847.158-3847.332"
- cell $or $or$ls180.v:3847$328
+ attribute \src "ls180.v:3843.158-3843.332"
+ cell $or $or$ls180.v:3843$328
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $not$ls180.v:3847$327_Y
+ connect \A $not$ls180.v:3843$327_Y
connect \B \main_sdram_choose_req_want_activates
- connect \Y $or$ls180.v:3847$328_Y
+ connect \Y $or$ls180.v:3843$328_Y
end
- attribute \src "ls180.v:3847.75-3847.506"
- cell $or $or$ls180.v:3847$333
+ attribute \src "ls180.v:3843.75-3843.506"
+ cell $or $or$ls180.v:3843$333
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3847$329_Y
- connect \B $and$ls180.v:3847$332_Y
- connect \Y $or$ls180.v:3847$333_Y
+ connect \A $and$ls180.v:3843$329_Y
+ connect \B $and$ls180.v:3843$332_Y
+ connect \Y $or$ls180.v:3843$333_Y
end
- attribute \src "ls180.v:3848.158-3848.332"
- cell $or $or$ls180.v:3848$341
+ attribute \src "ls180.v:3844.158-3844.332"
+ cell $or $or$ls180.v:3844$341
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $not$ls180.v:3848$340_Y
+ connect \A $not$ls180.v:3844$340_Y
connect \B \main_sdram_choose_req_want_activates
- connect \Y $or$ls180.v:3848$341_Y
+ connect \Y $or$ls180.v:3844$341_Y
end
- attribute \src "ls180.v:3848.75-3848.506"
- cell $or $or$ls180.v:3848$346
+ attribute \src "ls180.v:3844.75-3844.506"
+ cell $or $or$ls180.v:3844$346
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3848$342_Y
- connect \B $and$ls180.v:3848$345_Y
- connect \Y $or$ls180.v:3848$346_Y
+ connect \A $and$ls180.v:3844$342_Y
+ connect \B $and$ls180.v:3844$345_Y
+ connect \Y $or$ls180.v:3844$346_Y
end
- attribute \src "ls180.v:3911.36-3911.104"
- cell $or $or$ls180.v:3911$380
+ attribute \src "ls180.v:3907.36-3907.104"
+ cell $or $or$ls180.v:3907$380
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_choose_req_cmd_ready
- connect \B $not$ls180.v:3911$379_Y
- connect \Y $or$ls180.v:3911$380_Y
+ connect \B $not$ls180.v:3907$379_Y
+ connect \Y $or$ls180.v:3907$380_Y
end
- attribute \src "ls180.v:3932.67-3932.221"
- cell $or $or$ls180.v:3932$387
+ attribute \src "ls180.v:3928.67-3928.221"
+ cell $or $or$ls180.v:3928$387
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $not$ls180.v:3932$386_Y
+ connect \A $not$ls180.v:3928$386_Y
connect \B \main_sdram_ras_allowed
- connect \Y $or$ls180.v:3932$387_Y
+ connect \Y $or$ls180.v:3928$387_Y
end
- attribute \src "ls180.v:3940.10-3940.62"
- cell $or $or$ls180.v:3940$390
+ attribute \src "ls180.v:3936.10-3936.62"
+ cell $or $or$ls180.v:3936$390
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $not$ls180.v:3940$389_Y
+ connect \A $not$ls180.v:3936$389_Y
connect \B \main_sdram_max_time1
- connect \Y $or$ls180.v:3940$390_Y
+ connect \Y $or$ls180.v:3936$390_Y
end
- attribute \src "ls180.v:3970.67-3970.221"
- cell $or $or$ls180.v:3970$396
+ attribute \src "ls180.v:3966.67-3966.221"
+ cell $or $or$ls180.v:3966$396
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $not$ls180.v:3970$395_Y
+ connect \A $not$ls180.v:3966$395_Y
connect \B \main_sdram_ras_allowed
- connect \Y $or$ls180.v:3970$396_Y
+ connect \Y $or$ls180.v:3966$396_Y
end
- attribute \src "ls180.v:3978.10-3978.61"
- cell $or $or$ls180.v:3978$399
+ attribute \src "ls180.v:3974.10-3974.61"
+ cell $or $or$ls180.v:3974$399
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $not$ls180.v:3978$398_Y
+ connect \A $not$ls180.v:3974$398_Y
connect \B \main_sdram_max_time0
- connect \Y $or$ls180.v:3978$399_Y
+ connect \Y $or$ls180.v:3974$399_Y
end
- attribute \src "ls180.v:3988.91-3988.180"
- cell $or $or$ls180.v:3988$403
+ attribute \src "ls180.v:3984.91-3984.180"
+ cell $or $or$ls180.v:3984$403
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_locked0
- connect \B $and$ls180.v:3988$402_Y
- connect \Y $or$ls180.v:3988$403_Y
+ connect \B $and$ls180.v:3984$402_Y
+ connect \Y $or$ls180.v:3984$403_Y
end
- attribute \src "ls180.v:3988.90-3988.255"
- cell $or $or$ls180.v:3988$406
+ attribute \src "ls180.v:3984.90-3984.255"
+ cell $or $or$ls180.v:3984$406
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:3988$403_Y
- connect \B $and$ls180.v:3988$405_Y
- connect \Y $or$ls180.v:3988$406_Y
+ connect \A $or$ls180.v:3984$403_Y
+ connect \B $and$ls180.v:3984$405_Y
+ connect \Y $or$ls180.v:3984$406_Y
end
- attribute \src "ls180.v:3988.89-3988.330"
- cell $or $or$ls180.v:3988$409
+ attribute \src "ls180.v:3984.89-3984.330"
+ cell $or $or$ls180.v:3984$409
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:3988$406_Y
- connect \B $and$ls180.v:3988$408_Y
- connect \Y $or$ls180.v:3988$409_Y
+ connect \A $or$ls180.v:3984$406_Y
+ connect \B $and$ls180.v:3984$408_Y
+ connect \Y $or$ls180.v:3984$409_Y
end
- attribute \src "ls180.v:3993.91-3993.180"
- cell $or $or$ls180.v:3993$419
+ attribute \src "ls180.v:3989.91-3989.180"
+ cell $or $or$ls180.v:3989$419
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_locked1
- connect \B $and$ls180.v:3993$418_Y
- connect \Y $or$ls180.v:3993$419_Y
+ connect \B $and$ls180.v:3989$418_Y
+ connect \Y $or$ls180.v:3989$419_Y
end
- attribute \src "ls180.v:3993.90-3993.255"
- cell $or $or$ls180.v:3993$422
+ attribute \src "ls180.v:3989.90-3989.255"
+ cell $or $or$ls180.v:3989$422
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:3993$419_Y
- connect \B $and$ls180.v:3993$421_Y
- connect \Y $or$ls180.v:3993$422_Y
+ connect \A $or$ls180.v:3989$419_Y
+ connect \B $and$ls180.v:3989$421_Y
+ connect \Y $or$ls180.v:3989$422_Y
end
- attribute \src "ls180.v:3993.89-3993.330"
- cell $or $or$ls180.v:3993$425
+ attribute \src "ls180.v:3989.89-3989.330"
+ cell $or $or$ls180.v:3989$425
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:3993$422_Y
- connect \B $and$ls180.v:3993$424_Y
- connect \Y $or$ls180.v:3993$425_Y
+ connect \A $or$ls180.v:3989$422_Y
+ connect \B $and$ls180.v:3989$424_Y
+ connect \Y $or$ls180.v:3989$425_Y
end
- attribute \src "ls180.v:3998.91-3998.180"
- cell $or $or$ls180.v:3998$435
+ attribute \src "ls180.v:3994.91-3994.180"
+ cell $or $or$ls180.v:3994$435
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_locked2
- connect \B $and$ls180.v:3998$434_Y
- connect \Y $or$ls180.v:3998$435_Y
+ connect \B $and$ls180.v:3994$434_Y
+ connect \Y $or$ls180.v:3994$435_Y
end
- attribute \src "ls180.v:3998.90-3998.255"
- cell $or $or$ls180.v:3998$438
+ attribute \src "ls180.v:3994.90-3994.255"
+ cell $or $or$ls180.v:3994$438
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:3998$435_Y
- connect \B $and$ls180.v:3998$437_Y
- connect \Y $or$ls180.v:3998$438_Y
+ connect \A $or$ls180.v:3994$435_Y
+ connect \B $and$ls180.v:3994$437_Y
+ connect \Y $or$ls180.v:3994$438_Y
end
- attribute \src "ls180.v:3998.89-3998.330"
- cell $or $or$ls180.v:3998$441
+ attribute \src "ls180.v:3994.89-3994.330"
+ cell $or $or$ls180.v:3994$441
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:3998$438_Y
- connect \B $and$ls180.v:3998$440_Y
- connect \Y $or$ls180.v:3998$441_Y
+ connect \A $or$ls180.v:3994$438_Y
+ connect \B $and$ls180.v:3994$440_Y
+ connect \Y $or$ls180.v:3994$441_Y
end
- attribute \src "ls180.v:4003.91-4003.180"
- cell $or $or$ls180.v:4003$451
+ attribute \src "ls180.v:3999.91-3999.180"
+ cell $or $or$ls180.v:3999$451
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_locked3
- connect \B $and$ls180.v:4003$450_Y
- connect \Y $or$ls180.v:4003$451_Y
+ connect \B $and$ls180.v:3999$450_Y
+ connect \Y $or$ls180.v:3999$451_Y
end
- attribute \src "ls180.v:4003.90-4003.255"
- cell $or $or$ls180.v:4003$454
+ attribute \src "ls180.v:3999.90-3999.255"
+ cell $or $or$ls180.v:3999$454
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:4003$451_Y
- connect \B $and$ls180.v:4003$453_Y
- connect \Y $or$ls180.v:4003$454_Y
+ connect \A $or$ls180.v:3999$451_Y
+ connect \B $and$ls180.v:3999$453_Y
+ connect \Y $or$ls180.v:3999$454_Y
end
- attribute \src "ls180.v:4003.89-4003.330"
- cell $or $or$ls180.v:4003$457
+ attribute \src "ls180.v:3999.89-3999.330"
+ cell $or $or$ls180.v:3999$457
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:4003$454_Y
- connect \B $and$ls180.v:4003$456_Y
- connect \Y $or$ls180.v:4003$457_Y
+ connect \A $or$ls180.v:3999$454_Y
+ connect \B $and$ls180.v:3999$456_Y
+ connect \Y $or$ls180.v:3999$457_Y
end
- attribute \src "ls180.v:4008.132-4008.221"
- cell $or $or$ls180.v:4008$468
+ attribute \src "ls180.v:4004.132-4004.221"
+ cell $or $or$ls180.v:4004$468
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_locked0
- connect \B $and$ls180.v:4008$467_Y
- connect \Y $or$ls180.v:4008$468_Y
+ connect \B $and$ls180.v:4004$467_Y
+ connect \Y $or$ls180.v:4004$468_Y
end
- attribute \src "ls180.v:4008.131-4008.296"
- cell $or $or$ls180.v:4008$471
+ attribute \src "ls180.v:4004.131-4004.296"
+ cell $or $or$ls180.v:4004$471
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:4008$468_Y
- connect \B $and$ls180.v:4008$470_Y
- connect \Y $or$ls180.v:4008$471_Y
+ connect \A $or$ls180.v:4004$468_Y
+ connect \B $and$ls180.v:4004$470_Y
+ connect \Y $or$ls180.v:4004$471_Y
end
- attribute \src "ls180.v:4008.130-4008.371"
- cell $or $or$ls180.v:4008$474
+ attribute \src "ls180.v:4004.130-4004.371"
+ cell $or $or$ls180.v:4004$474
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:4008$471_Y
- connect \B $and$ls180.v:4008$473_Y
- connect \Y $or$ls180.v:4008$474_Y
+ connect \A $or$ls180.v:4004$471_Y
+ connect \B $and$ls180.v:4004$473_Y
+ connect \Y $or$ls180.v:4004$474_Y
end
- attribute \src "ls180.v:4008.34-4008.411"
- cell $or $or$ls180.v:4008$479
+ attribute \src "ls180.v:4004.34-4004.411"
+ cell $or $or$ls180.v:4004$479
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A 1'0
- connect \B $and$ls180.v:4008$478_Y
- connect \Y $or$ls180.v:4008$479_Y
+ connect \B $and$ls180.v:4004$478_Y
+ connect \Y $or$ls180.v:4004$479_Y
end
- attribute \src "ls180.v:4008.506-4008.595"
- cell $or $or$ls180.v:4008$484
+ attribute \src "ls180.v:4004.506-4004.595"
+ cell $or $or$ls180.v:4004$484
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_locked1
- connect \B $and$ls180.v:4008$483_Y
- connect \Y $or$ls180.v:4008$484_Y
+ connect \B $and$ls180.v:4004$483_Y
+ connect \Y $or$ls180.v:4004$484_Y
end
- attribute \src "ls180.v:4008.505-4008.670"
- cell $or $or$ls180.v:4008$487
+ attribute \src "ls180.v:4004.505-4004.670"
+ cell $or $or$ls180.v:4004$487
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:4008$484_Y
- connect \B $and$ls180.v:4008$486_Y
- connect \Y $or$ls180.v:4008$487_Y
+ connect \A $or$ls180.v:4004$484_Y
+ connect \B $and$ls180.v:4004$486_Y
+ connect \Y $or$ls180.v:4004$487_Y
end
- attribute \src "ls180.v:4008.504-4008.745"
- cell $or $or$ls180.v:4008$490
+ attribute \src "ls180.v:4004.504-4004.745"
+ cell $or $or$ls180.v:4004$490
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:4008$487_Y
- connect \B $and$ls180.v:4008$489_Y
- connect \Y $or$ls180.v:4008$490_Y
+ connect \A $or$ls180.v:4004$487_Y
+ connect \B $and$ls180.v:4004$489_Y
+ connect \Y $or$ls180.v:4004$490_Y
end
- attribute \src "ls180.v:4008.33-4008.785"
- cell $or $or$ls180.v:4008$495
+ attribute \src "ls180.v:4004.33-4004.785"
+ cell $or $or$ls180.v:4004$495
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:4008$479_Y
- connect \B $and$ls180.v:4008$494_Y
- connect \Y $or$ls180.v:4008$495_Y
+ connect \A $or$ls180.v:4004$479_Y
+ connect \B $and$ls180.v:4004$494_Y
+ connect \Y $or$ls180.v:4004$495_Y
end
- attribute \src "ls180.v:4008.880-4008.969"
- cell $or $or$ls180.v:4008$500
+ attribute \src "ls180.v:4004.880-4004.969"
+ cell $or $or$ls180.v:4004$500
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_locked2
- connect \B $and$ls180.v:4008$499_Y
- connect \Y $or$ls180.v:4008$500_Y
+ connect \B $and$ls180.v:4004$499_Y
+ connect \Y $or$ls180.v:4004$500_Y
end
- attribute \src "ls180.v:4008.879-4008.1044"
- cell $or $or$ls180.v:4008$503
+ attribute \src "ls180.v:4004.879-4004.1044"
+ cell $or $or$ls180.v:4004$503
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:4008$500_Y
- connect \B $and$ls180.v:4008$502_Y
- connect \Y $or$ls180.v:4008$503_Y
+ connect \A $or$ls180.v:4004$500_Y
+ connect \B $and$ls180.v:4004$502_Y
+ connect \Y $or$ls180.v:4004$503_Y
end
- attribute \src "ls180.v:4008.878-4008.1119"
- cell $or $or$ls180.v:4008$506
+ attribute \src "ls180.v:4004.878-4004.1119"
+ cell $or $or$ls180.v:4004$506
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:4008$503_Y
- connect \B $and$ls180.v:4008$505_Y
- connect \Y $or$ls180.v:4008$506_Y
+ connect \A $or$ls180.v:4004$503_Y
+ connect \B $and$ls180.v:4004$505_Y
+ connect \Y $or$ls180.v:4004$506_Y
end
- attribute \src "ls180.v:4008.32-4008.1159"
- cell $or $or$ls180.v:4008$511
+ attribute \src "ls180.v:4004.32-4004.1159"
+ cell $or $or$ls180.v:4004$511
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:4008$495_Y
- connect \B $and$ls180.v:4008$510_Y
- connect \Y $or$ls180.v:4008$511_Y
+ connect \A $or$ls180.v:4004$495_Y
+ connect \B $and$ls180.v:4004$510_Y
+ connect \Y $or$ls180.v:4004$511_Y
end
- attribute \src "ls180.v:4008.1254-4008.1343"
- cell $or $or$ls180.v:4008$516
+ attribute \src "ls180.v:4004.1254-4004.1343"
+ cell $or $or$ls180.v:4004$516
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_locked3
- connect \B $and$ls180.v:4008$515_Y
- connect \Y $or$ls180.v:4008$516_Y
+ connect \B $and$ls180.v:4004$515_Y
+ connect \Y $or$ls180.v:4004$516_Y
end
- attribute \src "ls180.v:4008.1253-4008.1418"
- cell $or $or$ls180.v:4008$519
+ attribute \src "ls180.v:4004.1253-4004.1418"
+ cell $or $or$ls180.v:4004$519
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:4008$516_Y
- connect \B $and$ls180.v:4008$518_Y
- connect \Y $or$ls180.v:4008$519_Y
+ connect \A $or$ls180.v:4004$516_Y
+ connect \B $and$ls180.v:4004$518_Y
+ connect \Y $or$ls180.v:4004$519_Y
end
- attribute \src "ls180.v:4008.1252-4008.1493"
- cell $or $or$ls180.v:4008$522
+ attribute \src "ls180.v:4004.1252-4004.1493"
+ cell $or $or$ls180.v:4004$522
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:4008$519_Y
- connect \B $and$ls180.v:4008$521_Y
- connect \Y $or$ls180.v:4008$522_Y
+ connect \A $or$ls180.v:4004$519_Y
+ connect \B $and$ls180.v:4004$521_Y
+ connect \Y $or$ls180.v:4004$522_Y
end
- attribute \src "ls180.v:4008.31-4008.1533"
- cell $or $or$ls180.v:4008$527
+ attribute \src "ls180.v:4004.31-4004.1533"
+ cell $or $or$ls180.v:4004$527
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:4008$511_Y
- connect \B $and$ls180.v:4008$526_Y
- connect \Y $or$ls180.v:4008$527_Y
+ connect \A $or$ls180.v:4004$511_Y
+ connect \B $and$ls180.v:4004$526_Y
+ connect \Y $or$ls180.v:4004$527_Y
end
- attribute \src "ls180.v:4071.10-4071.52"
- cell $or $or$ls180.v:4071$536
+ attribute \src "ls180.v:4067.10-4067.52"
+ cell $or $or$ls180.v:4067$536
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_litedram_wb_ack
connect \B \main_converter_skip
- connect \Y $or$ls180.v:4071$536_Y
+ connect \Y $or$ls180.v:4067$536_Y
end
- attribute \src "ls180.v:4098.35-4098.74"
- cell $or $or$ls180.v:4098$546
+ attribute \src "ls180.v:4094.35-4094.74"
+ cell $or $or$ls180.v:4094$546
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_port_cmd_valid
connect \B \main_cmd_consumed
- connect \Y $or$ls180.v:4098$546_Y
+ connect \Y $or$ls180.v:4094$546_Y
end
- attribute \src "ls180.v:4099.34-4099.73"
- cell $or $or$ls180.v:4099$550
+ attribute \src "ls180.v:4095.34-4095.73"
+ cell $or $or$ls180.v:4095$550
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_port_cmd_valid
connect \B \main_cmd_consumed
- connect \Y $or$ls180.v:4099$550_Y
+ connect \Y $or$ls180.v:4095$550_Y
end
- attribute \src "ls180.v:4100.48-4100.130"
- cell $or $or$ls180.v:4100$556
+ attribute \src "ls180.v:4096.48-4096.130"
+ cell $or $or$ls180.v:4096$556
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:4100$553_Y
- connect \B $and$ls180.v:4100$555_Y
- connect \Y $or$ls180.v:4100$556_Y
+ connect \A $and$ls180.v:4096$553_Y
+ connect \B $and$ls180.v:4096$555_Y
+ connect \Y $or$ls180.v:4096$556_Y
end
- attribute \src "ls180.v:4101.24-4101.87"
- cell $or $or$ls180.v:4101$559
+ attribute \src "ls180.v:4097.24-4097.87"
+ cell $or $or$ls180.v:4097$559
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:4101$558_Y
+ connect \A $and$ls180.v:4097$558_Y
connect \B \main_cmd_consumed
- connect \Y $or$ls180.v:4101$559_Y
+ connect \Y $or$ls180.v:4097$559_Y
end
- attribute \src "ls180.v:4102.26-4102.95"
- cell $or $or$ls180.v:4102$561
+ attribute \src "ls180.v:4098.26-4098.95"
+ cell $or $or$ls180.v:4098$561
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:4102$560_Y
+ connect \A $and$ls180.v:4098$560_Y
connect \B \main_wdata_consumed
- connect \Y $or$ls180.v:4102$561_Y
+ connect \Y $or$ls180.v:4098$561_Y
end
- attribute \src "ls180.v:4132.42-4132.89"
- cell $or $or$ls180.v:4132$569
+ attribute \src "ls180.v:4128.42-4128.89"
+ cell $or $or$ls180.v:4128$569
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_uart_rx_clear
- connect \B $and$ls180.v:4132$568_Y
- connect \Y $or$ls180.v:4132$569_Y
+ connect \B $and$ls180.v:4128$568_Y
+ connect \Y $or$ls180.v:4128$569_Y
end
- attribute \src "ls180.v:4156.25-4156.174"
- cell $or $or$ls180.v:4156$579
+ attribute \src "ls180.v:4152.25-4152.174"
+ cell $or $or$ls180.v:4152$579
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:4156$577_Y
- connect \B $and$ls180.v:4156$578_Y
- connect \Y $or$ls180.v:4156$579_Y
+ connect \A $and$ls180.v:4152$577_Y
+ connect \B $and$ls180.v:4152$578_Y
+ connect \Y $or$ls180.v:4152$579_Y
end
- attribute \src "ls180.v:4171.80-4171.132"
- cell $or $or$ls180.v:4171$581
+ attribute \src "ls180.v:4167.80-4167.132"
+ cell $or $or$ls180.v:4167$581
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $not$ls180.v:4171$580_Y
+ connect \A $not$ls180.v:4167$580_Y
connect \B \main_uart_tx_fifo_re
- connect \Y $or$ls180.v:4171$581_Y
+ connect \Y $or$ls180.v:4167$581_Y
end
- attribute \src "ls180.v:4182.72-4182.135"
- cell $or $or$ls180.v:4182$586
+ attribute \src "ls180.v:4178.72-4178.135"
+ cell $or $or$ls180.v:4178$586
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_uart_tx_fifo_syncfifo_writable
connect \B \main_uart_tx_fifo_replace
- connect \Y $or$ls180.v:4182$586_Y
+ connect \Y $or$ls180.v:4178$586_Y
end
- attribute \src "ls180.v:4201.80-4201.132"
- cell $or $or$ls180.v:4201$592
+ attribute \src "ls180.v:4197.80-4197.132"
+ cell $or $or$ls180.v:4197$592
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $not$ls180.v:4201$591_Y
+ connect \A $not$ls180.v:4197$591_Y
connect \B \main_uart_rx_fifo_re
- connect \Y $or$ls180.v:4201$592_Y
+ connect \Y $or$ls180.v:4197$592_Y
end
- attribute \src "ls180.v:4212.72-4212.135"
- cell $or $or$ls180.v:4212$597
+ attribute \src "ls180.v:4208.72-4208.135"
+ cell $or $or$ls180.v:4208$597
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_uart_rx_fifo_syncfifo_writable
connect \B \main_uart_rx_fifo_replace
- connect \Y $or$ls180.v:4212$597_Y
+ connect \Y $or$ls180.v:4208$597_Y
end
- attribute \src "ls180.v:4346.36-4346.111"
- cell $or $or$ls180.v:4346$618
+ attribute \src "ls180.v:4342.36-4342.111"
+ cell $or $or$ls180.v:4342$618
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdphy_init_pads_out_payload_clk
connect \B \main_sdphy_cmdw_pads_out_payload_clk
- connect \Y $or$ls180.v:4346$618_Y
+ connect \Y $or$ls180.v:4342$618_Y
end
- attribute \src "ls180.v:4346.35-4346.151"
- cell $or $or$ls180.v:4346$619
+ attribute \src "ls180.v:4342.35-4342.151"
+ cell $or $or$ls180.v:4342$619
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:4346$618_Y
+ connect \A $or$ls180.v:4342$618_Y
connect \B \main_sdphy_cmdr_pads_out_payload_clk
- connect \Y $or$ls180.v:4346$619_Y
+ connect \Y $or$ls180.v:4342$619_Y
end
- attribute \src "ls180.v:4346.34-4346.192"
- cell $or $or$ls180.v:4346$620
+ attribute \src "ls180.v:4342.34-4342.192"
+ cell $or $or$ls180.v:4342$620
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:4346$619_Y
+ connect \A $or$ls180.v:4342$619_Y
connect \B \main_sdphy_dataw_pads_out_payload_clk
- connect \Y $or$ls180.v:4346$620_Y
+ connect \Y $or$ls180.v:4342$620_Y
end
- attribute \src "ls180.v:4346.33-4346.233"
- cell $or $or$ls180.v:4346$621
+ attribute \src "ls180.v:4342.33-4342.233"
+ cell $or $or$ls180.v:4342$621
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:4346$620_Y
+ connect \A $or$ls180.v:4342$620_Y
connect \B \main_sdphy_datar_pads_out_payload_clk
- connect \Y $or$ls180.v:4346$621_Y
+ connect \Y $or$ls180.v:4342$621_Y
end
- attribute \src "ls180.v:4347.39-4347.120"
- cell $or $or$ls180.v:4347$622
+ attribute \src "ls180.v:4343.39-4343.120"
+ cell $or $or$ls180.v:4343$622
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdphy_init_pads_out_payload_cmd_oe
connect \B \main_sdphy_cmdw_pads_out_payload_cmd_oe
- connect \Y $or$ls180.v:4347$622_Y
+ connect \Y $or$ls180.v:4343$622_Y
end
- attribute \src "ls180.v:4347.38-4347.163"
- cell $or $or$ls180.v:4347$623
+ attribute \src "ls180.v:4343.38-4343.163"
+ cell $or $or$ls180.v:4343$623
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:4347$622_Y
+ connect \A $or$ls180.v:4343$622_Y
connect \B \main_sdphy_cmdr_pads_out_payload_cmd_oe
- connect \Y $or$ls180.v:4347$623_Y
+ connect \Y $or$ls180.v:4343$623_Y
end
- attribute \src "ls180.v:4347.37-4347.207"
- cell $or $or$ls180.v:4347$624
+ attribute \src "ls180.v:4343.37-4343.207"
+ cell $or $or$ls180.v:4343$624
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:4347$623_Y
+ connect \A $or$ls180.v:4343$623_Y
connect \B \main_sdphy_dataw_pads_out_payload_cmd_oe
- connect \Y $or$ls180.v:4347$624_Y
+ connect \Y $or$ls180.v:4343$624_Y
end
- attribute \src "ls180.v:4347.36-4347.251"
- cell $or $or$ls180.v:4347$625
+ attribute \src "ls180.v:4343.36-4343.251"
+ cell $or $or$ls180.v:4343$625
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:4347$624_Y
+ connect \A $or$ls180.v:4343$624_Y
connect \B \main_sdphy_datar_pads_out_payload_cmd_oe
- connect \Y $or$ls180.v:4347$625_Y
+ connect \Y $or$ls180.v:4343$625_Y
end
- attribute \src "ls180.v:4348.38-4348.117"
- cell $or $or$ls180.v:4348$626
+ attribute \src "ls180.v:4344.38-4344.117"
+ cell $or $or$ls180.v:4344$626
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdphy_init_pads_out_payload_cmd_o
connect \B \main_sdphy_cmdw_pads_out_payload_cmd_o
- connect \Y $or$ls180.v:4348$626_Y
+ connect \Y $or$ls180.v:4344$626_Y
end
- attribute \src "ls180.v:4348.37-4348.159"
- cell $or $or$ls180.v:4348$627
+ attribute \src "ls180.v:4344.37-4344.159"
+ cell $or $or$ls180.v:4344$627
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:4348$626_Y
+ connect \A $or$ls180.v:4344$626_Y
connect \B \main_sdphy_cmdr_pads_out_payload_cmd_o
- connect \Y $or$ls180.v:4348$627_Y
+ connect \Y $or$ls180.v:4344$627_Y
end
- attribute \src "ls180.v:4348.36-4348.202"
- cell $or $or$ls180.v:4348$628
+ attribute \src "ls180.v:4344.36-4344.202"
+ cell $or $or$ls180.v:4344$628
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:4348$627_Y
+ connect \A $or$ls180.v:4344$627_Y
connect \B \main_sdphy_dataw_pads_out_payload_cmd_o
- connect \Y $or$ls180.v:4348$628_Y
+ connect \Y $or$ls180.v:4344$628_Y
end
- attribute \src "ls180.v:4348.35-4348.245"
- cell $or $or$ls180.v:4348$629
+ attribute \src "ls180.v:4344.35-4344.245"
+ cell $or $or$ls180.v:4344$629
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:4348$628_Y
+ connect \A $or$ls180.v:4344$628_Y
connect \B \main_sdphy_datar_pads_out_payload_cmd_o
- connect \Y $or$ls180.v:4348$629_Y
+ connect \Y $or$ls180.v:4344$629_Y
end
- attribute \src "ls180.v:4349.40-4349.123"
- cell $or $or$ls180.v:4349$630
+ attribute \src "ls180.v:4345.40-4345.123"
+ cell $or $or$ls180.v:4345$630
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdphy_init_pads_out_payload_data_oe
connect \B \main_sdphy_cmdw_pads_out_payload_data_oe
- connect \Y $or$ls180.v:4349$630_Y
+ connect \Y $or$ls180.v:4345$630_Y
end
- attribute \src "ls180.v:4349.39-4349.167"
- cell $or $or$ls180.v:4349$631
+ attribute \src "ls180.v:4345.39-4345.167"
+ cell $or $or$ls180.v:4345$631
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:4349$630_Y
+ connect \A $or$ls180.v:4345$630_Y
connect \B \main_sdphy_cmdr_pads_out_payload_data_oe
- connect \Y $or$ls180.v:4349$631_Y
+ connect \Y $or$ls180.v:4345$631_Y
end
- attribute \src "ls180.v:4349.38-4349.212"
- cell $or $or$ls180.v:4349$632
+ attribute \src "ls180.v:4345.38-4345.212"
+ cell $or $or$ls180.v:4345$632
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:4349$631_Y
+ connect \A $or$ls180.v:4345$631_Y
connect \B \main_sdphy_dataw_pads_out_payload_data_oe
- connect \Y $or$ls180.v:4349$632_Y
+ connect \Y $or$ls180.v:4345$632_Y
end
- attribute \src "ls180.v:4349.37-4349.257"
- cell $or $or$ls180.v:4349$633
+ attribute \src "ls180.v:4345.37-4345.257"
+ cell $or $or$ls180.v:4345$633
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:4349$632_Y
+ connect \A $or$ls180.v:4345$632_Y
connect \B \main_sdphy_datar_pads_out_payload_data_oe
- connect \Y $or$ls180.v:4349$633_Y
+ connect \Y $or$ls180.v:4345$633_Y
end
- attribute \src "ls180.v:4350.39-4350.120"
- cell $or $or$ls180.v:4350$634
+ attribute \src "ls180.v:4346.39-4346.120"
+ cell $or $or$ls180.v:4346$634
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \main_sdphy_init_pads_out_payload_data_o
connect \B \main_sdphy_cmdw_pads_out_payload_data_o
- connect \Y $or$ls180.v:4350$634_Y
+ connect \Y $or$ls180.v:4346$634_Y
end
- attribute \src "ls180.v:4350.38-4350.163"
- cell $or $or$ls180.v:4350$635
+ attribute \src "ls180.v:4346.38-4346.163"
+ cell $or $or$ls180.v:4346$635
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \B_WIDTH 4
parameter \Y_WIDTH 4
- connect \A $or$ls180.v:4350$634_Y
+ connect \A $or$ls180.v:4346$634_Y
connect \B \main_sdphy_cmdr_pads_out_payload_data_o
- connect \Y $or$ls180.v:4350$635_Y
+ connect \Y $or$ls180.v:4346$635_Y
end
- attribute \src "ls180.v:4350.37-4350.207"
- cell $or $or$ls180.v:4350$636
+ attribute \src "ls180.v:4346.37-4346.207"
+ cell $or $or$ls180.v:4346$636
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \B_WIDTH 4
parameter \Y_WIDTH 4
- connect \A $or$ls180.v:4350$635_Y
+ connect \A $or$ls180.v:4346$635_Y
connect \B \main_sdphy_dataw_pads_out_payload_data_o
- connect \Y $or$ls180.v:4350$636_Y
+ connect \Y $or$ls180.v:4346$636_Y
end
- attribute \src "ls180.v:4350.36-4350.251"
- cell $or $or$ls180.v:4350$637
+ attribute \src "ls180.v:4346.36-4346.251"
+ cell $or $or$ls180.v:4346$637
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \B_WIDTH 4
parameter \Y_WIDTH 4
- connect \A $or$ls180.v:4350$636_Y
+ connect \A $or$ls180.v:4346$636_Y
connect \B \main_sdphy_datar_pads_out_payload_data_o
- connect \Y $or$ls180.v:4350$637_Y
+ connect \Y $or$ls180.v:4346$637_Y
end
- attribute \src "ls180.v:4371.35-4371.80"
- cell $or $or$ls180.v:4371$638
+ attribute \src "ls180.v:4367.35-4367.80"
+ cell $or $or$ls180.v:4367$638
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdphy_dataw_stop
connect \B \main_sdphy_datar_stop
- connect \Y $or$ls180.v:4371$638_Y
+ connect \Y $or$ls180.v:4367$638_Y
end
- attribute \src "ls180.v:4525.91-4525.144"
- cell $or $or$ls180.v:4525$652
+ attribute \src "ls180.v:4521.91-4521.144"
+ cell $or $or$ls180.v:4521$652
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdphy_cmdr_cmdr_start
connect \B \main_sdphy_cmdr_cmdr_run
- connect \Y $or$ls180.v:4525$652_Y
+ connect \Y $or$ls180.v:4521$652_Y
end
- attribute \src "ls180.v:4542.53-4542.143"
- cell $or $or$ls180.v:4542$655
+ attribute \src "ls180.v:4538.53-4538.143"
+ cell $or $or$ls180.v:4538$655
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $not$ls180.v:4542$654_Y
+ connect \A $not$ls180.v:4538$654_Y
connect \B \main_sdphy_cmdr_cmdr_converter_source_ready
- connect \Y $or$ls180.v:4542$655_Y
+ connect \Y $or$ls180.v:4538$655_Y
end
- attribute \src "ls180.v:4545.47-4545.127"
- cell $or $or$ls180.v:4545$658
+ attribute \src "ls180.v:4541.47-4541.127"
+ cell $or $or$ls180.v:4541$658
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $not$ls180.v:4545$657_Y
+ connect \A $not$ls180.v:4541$657_Y
connect \B \main_sdphy_cmdr_cmdr_buf_source_ready
- connect \Y $or$ls180.v:4545$658_Y
+ connect \Y $or$ls180.v:4541$658_Y
end
- attribute \src "ls180.v:4669.54-4669.146"
- cell $or $or$ls180.v:4669$676
+ attribute \src "ls180.v:4665.54-4665.146"
+ cell $or $or$ls180.v:4665$676
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $not$ls180.v:4669$675_Y
+ connect \A $not$ls180.v:4665$675_Y
connect \B \main_sdphy_dataw_crcr_converter_source_ready
- connect \Y $or$ls180.v:4669$676_Y
+ connect \Y $or$ls180.v:4665$676_Y
end
- attribute \src "ls180.v:4672.48-4672.130"
- cell $or $or$ls180.v:4672$679
+ attribute \src "ls180.v:4668.48-4668.130"
+ cell $or $or$ls180.v:4668$679
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $not$ls180.v:4672$678_Y
+ connect \A $not$ls180.v:4668$678_Y
connect \B \main_sdphy_dataw_crcr_buf_source_ready
- connect \Y $or$ls180.v:4672$679_Y
+ connect \Y $or$ls180.v:4668$679_Y
end
- attribute \src "ls180.v:4803.55-4803.149"
- cell $or $or$ls180.v:4803$691
+ attribute \src "ls180.v:4799.55-4799.149"
+ cell $or $or$ls180.v:4799$691
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $not$ls180.v:4803$690_Y
+ connect \A $not$ls180.v:4799$690_Y
connect \B \main_sdphy_datar_datar_converter_source_ready
- connect \Y $or$ls180.v:4803$691_Y
+ connect \Y $or$ls180.v:4799$691_Y
end
- attribute \src "ls180.v:4806.49-4806.133"
- cell $or $or$ls180.v:4806$694
+ attribute \src "ls180.v:4802.49-4802.133"
+ cell $or $or$ls180.v:4802$694
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $not$ls180.v:4806$693_Y
+ connect \A $not$ls180.v:4802$693_Y
connect \B \main_sdphy_datar_datar_buf_source_ready
- connect \Y $or$ls180.v:4806$694_Y
+ connect \Y $or$ls180.v:4802$694_Y
end
- attribute \src "ls180.v:5435.80-5435.151"
- cell $or $or$ls180.v:5435$989
+ attribute \src "ls180.v:5431.80-5431.151"
+ cell $or $or$ls180.v:5431$989
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdblock2mem_fifo_syncfifo_writable
connect \B \main_sdblock2mem_fifo_replace
- connect \Y $or$ls180.v:5435$989_Y
+ connect \Y $or$ls180.v:5431$989_Y
end
- attribute \src "ls180.v:5446.49-5446.131"
- cell $or $or$ls180.v:5446$995
+ attribute \src "ls180.v:5442.49-5442.131"
+ cell $or $or$ls180.v:5442$995
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $not$ls180.v:5446$994_Y
+ connect \A $not$ls180.v:5442$994_Y
connect \B \main_sdblock2mem_converter_source_ready
- connect \Y $or$ls180.v:5446$995_Y
+ connect \Y $or$ls180.v:5442$995_Y
end
- attribute \src "ls180.v:5643.80-5643.151"
- cell $or $or$ls180.v:5643$1020
+ attribute \src "ls180.v:5639.80-5639.151"
+ cell $or $or$ls180.v:5639$1020
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdmem2block_fifo_syncfifo_writable
connect \B \main_sdmem2block_fifo_replace
- connect \Y $or$ls180.v:5643$1020_Y
+ connect \Y $or$ls180.v:5639$1020_Y
end
- attribute \src "ls180.v:5758.33-5758.102"
- cell $or $or$ls180.v:5758$1060
+ attribute \src "ls180.v:5754.33-5754.102"
+ cell $or $or$ls180.v:5754$1060
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_libresocsim_ram_bus_err
connect \B \main_libresocsim_libresoc_xics_icp_err
- connect \Y $or$ls180.v:5758$1060_Y
+ connect \Y $or$ls180.v:5754$1060_Y
end
- attribute \src "ls180.v:5758.32-5758.144"
- cell $or $or$ls180.v:5758$1061
+ attribute \src "ls180.v:5754.32-5754.144"
+ cell $or $or$ls180.v:5754$1061
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:5758$1060_Y
+ connect \A $or$ls180.v:5754$1060_Y
connect \B \main_libresocsim_libresoc_xics_ics_err
- connect \Y $or$ls180.v:5758$1061_Y
+ connect \Y $or$ls180.v:5754$1061_Y
end
- attribute \src "ls180.v:5758.31-5758.165"
- cell $or $or$ls180.v:5758$1062
+ attribute \src "ls180.v:5754.31-5754.165"
+ cell $or $or$ls180.v:5754$1062
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:5758$1061_Y
+ connect \A $or$ls180.v:5754$1061_Y
connect \B \main_wb_sdram_err
- connect \Y $or$ls180.v:5758$1062_Y
+ connect \Y $or$ls180.v:5754$1062_Y
end
- attribute \src "ls180.v:5758.30-5758.201"
- cell $or $or$ls180.v:5758$1063
+ attribute \src "ls180.v:5754.30-5754.201"
+ cell $or $or$ls180.v:5754$1063
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:5758$1062_Y
+ connect \A $or$ls180.v:5754$1062_Y
connect \B \builder_libresocsim_wishbone_err
- connect \Y $or$ls180.v:5758$1063_Y
+ connect \Y $or$ls180.v:5754$1063_Y
end
- attribute \src "ls180.v:5764.28-5764.97"
- cell $or $or$ls180.v:5764$1068
+ attribute \src "ls180.v:5760.28-5760.97"
+ cell $or $or$ls180.v:5760$1068
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_libresocsim_ram_bus_ack
connect \B \main_libresocsim_libresoc_xics_icp_ack
- connect \Y $or$ls180.v:5764$1068_Y
+ connect \Y $or$ls180.v:5760$1068_Y
end
- attribute \src "ls180.v:5764.27-5764.139"
- cell $or $or$ls180.v:5764$1069
+ attribute \src "ls180.v:5760.27-5760.139"
+ cell $or $or$ls180.v:5760$1069
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:5764$1068_Y
+ connect \A $or$ls180.v:5760$1068_Y
connect \B \main_libresocsim_libresoc_xics_ics_ack
- connect \Y $or$ls180.v:5764$1069_Y
+ connect \Y $or$ls180.v:5760$1069_Y
end
- attribute \src "ls180.v:5764.26-5764.160"
- cell $or $or$ls180.v:5764$1070
+ attribute \src "ls180.v:5760.26-5760.160"
+ cell $or $or$ls180.v:5760$1070
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:5764$1069_Y
+ connect \A $or$ls180.v:5760$1069_Y
connect \B \main_wb_sdram_ack
- connect \Y $or$ls180.v:5764$1070_Y
+ connect \Y $or$ls180.v:5760$1070_Y
end
- attribute \src "ls180.v:5764.25-5764.196"
- cell $or $or$ls180.v:5764$1071
+ attribute \src "ls180.v:5760.25-5760.196"
+ cell $or $or$ls180.v:5760$1071
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:5764$1070_Y
+ connect \A $or$ls180.v:5760$1070_Y
connect \B \builder_libresocsim_wishbone_ack
- connect \Y $or$ls180.v:5764$1071_Y
+ connect \Y $or$ls180.v:5760$1071_Y
end
- attribute \src "ls180.v:5765.30-5765.169"
- cell $or $or$ls180.v:5765$1074
+ attribute \src "ls180.v:5761.30-5761.169"
+ cell $or $or$ls180.v:5761$1074
parameter \A_SIGNED 0
parameter \A_WIDTH 32
parameter \B_SIGNED 0
parameter \B_WIDTH 32
parameter \Y_WIDTH 32
- connect \A $and$ls180.v:5765$1072_Y
- connect \B $and$ls180.v:5765$1073_Y
- connect \Y $or$ls180.v:5765$1074_Y
+ connect \A $and$ls180.v:5761$1072_Y
+ connect \B $and$ls180.v:5761$1073_Y
+ connect \Y $or$ls180.v:5761$1074_Y
end
- attribute \src "ls180.v:5765.29-5765.246"
- cell $or $or$ls180.v:5765$1076
+ attribute \src "ls180.v:5761.29-5761.246"
+ cell $or $or$ls180.v:5761$1076
parameter \A_SIGNED 0
parameter \A_WIDTH 32
parameter \B_SIGNED 0
parameter \B_WIDTH 32
parameter \Y_WIDTH 32
- connect \A $or$ls180.v:5765$1074_Y
- connect \B $and$ls180.v:5765$1075_Y
- connect \Y $or$ls180.v:5765$1076_Y
+ connect \A $or$ls180.v:5761$1074_Y
+ connect \B $and$ls180.v:5761$1075_Y
+ connect \Y $or$ls180.v:5761$1076_Y
end
- attribute \src "ls180.v:5765.28-5765.302"
- cell $or $or$ls180.v:5765$1078
+ attribute \src "ls180.v:5761.28-5761.302"
+ cell $or $or$ls180.v:5761$1078
parameter \A_SIGNED 0
parameter \A_WIDTH 32
parameter \B_SIGNED 0
parameter \B_WIDTH 32
parameter \Y_WIDTH 32
- connect \A $or$ls180.v:5765$1076_Y
- connect \B $and$ls180.v:5765$1077_Y
- connect \Y $or$ls180.v:5765$1078_Y
+ connect \A $or$ls180.v:5761$1076_Y
+ connect \B $and$ls180.v:5761$1077_Y
+ connect \Y $or$ls180.v:5761$1078_Y
end
- attribute \src "ls180.v:5765.27-5765.373"
- cell $or $or$ls180.v:5765$1080
+ attribute \src "ls180.v:5761.27-5761.373"
+ cell $or $or$ls180.v:5761$1080
parameter \A_SIGNED 0
parameter \A_WIDTH 32
parameter \B_SIGNED 0
parameter \B_WIDTH 32
parameter \Y_WIDTH 32
- connect \A $or$ls180.v:5765$1078_Y
- connect \B $and$ls180.v:5765$1079_Y
- connect \Y $or$ls180.v:5765$1080_Y
+ connect \A $or$ls180.v:5761$1078_Y
+ connect \B $and$ls180.v:5761$1079_Y
+ connect \Y $or$ls180.v:5761$1080_Y
end
- attribute \src "ls180.v:6519.55-6519.124"
- cell $or $or$ls180.v:6519$2226
+ attribute \src "ls180.v:6515.55-6515.124"
+ cell $or $or$ls180.v:6515$2226
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 8
connect \A \builder_interface0_bank_bus_dat_r
connect \B \builder_interface1_bank_bus_dat_r
- connect \Y $or$ls180.v:6519$2226_Y
+ connect \Y $or$ls180.v:6515$2226_Y
end
- attribute \src "ls180.v:6519.54-6519.161"
- cell $or $or$ls180.v:6519$2227
+ attribute \src "ls180.v:6515.54-6515.161"
+ cell $or $or$ls180.v:6515$2227
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \B_WIDTH 8
parameter \Y_WIDTH 8
- connect \A $or$ls180.v:6519$2226_Y
+ connect \A $or$ls180.v:6515$2226_Y
connect \B \builder_interface2_bank_bus_dat_r
- connect \Y $or$ls180.v:6519$2227_Y
+ connect \Y $or$ls180.v:6515$2227_Y
end
- attribute \src "ls180.v:6519.53-6519.198"
- cell $or $or$ls180.v:6519$2228
+ attribute \src "ls180.v:6515.53-6515.198"
+ cell $or $or$ls180.v:6515$2228
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \B_WIDTH 8
parameter \Y_WIDTH 8
- connect \A $or$ls180.v:6519$2227_Y
+ connect \A $or$ls180.v:6515$2227_Y
connect \B \builder_interface3_bank_bus_dat_r
- connect \Y $or$ls180.v:6519$2228_Y
+ connect \Y $or$ls180.v:6515$2228_Y
end
- attribute \src "ls180.v:6519.52-6519.235"
- cell $or $or$ls180.v:6519$2229
+ attribute \src "ls180.v:6515.52-6515.235"
+ cell $or $or$ls180.v:6515$2229
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \B_WIDTH 8
parameter \Y_WIDTH 8
- connect \A $or$ls180.v:6519$2228_Y
+ connect \A $or$ls180.v:6515$2228_Y
connect \B \builder_interface4_bank_bus_dat_r
- connect \Y $or$ls180.v:6519$2229_Y
+ connect \Y $or$ls180.v:6515$2229_Y
end
- attribute \src "ls180.v:6519.51-6519.272"
- cell $or $or$ls180.v:6519$2230
+ attribute \src "ls180.v:6515.51-6515.272"
+ cell $or $or$ls180.v:6515$2230
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \B_WIDTH 8
parameter \Y_WIDTH 8
- connect \A $or$ls180.v:6519$2229_Y
+ connect \A $or$ls180.v:6515$2229_Y
connect \B \builder_interface5_bank_bus_dat_r
- connect \Y $or$ls180.v:6519$2230_Y
+ connect \Y $or$ls180.v:6515$2230_Y
end
- attribute \src "ls180.v:6519.50-6519.309"
- cell $or $or$ls180.v:6519$2231
+ attribute \src "ls180.v:6515.50-6515.309"
+ cell $or $or$ls180.v:6515$2231
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \B_WIDTH 8
parameter \Y_WIDTH 8
- connect \A $or$ls180.v:6519$2230_Y
+ connect \A $or$ls180.v:6515$2230_Y
connect \B \builder_interface6_bank_bus_dat_r
- connect \Y $or$ls180.v:6519$2231_Y
+ connect \Y $or$ls180.v:6515$2231_Y
end
- attribute \src "ls180.v:6519.49-6519.346"
- cell $or $or$ls180.v:6519$2232
+ attribute \src "ls180.v:6515.49-6515.346"
+ cell $or $or$ls180.v:6515$2232
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \B_WIDTH 8
parameter \Y_WIDTH 8
- connect \A $or$ls180.v:6519$2231_Y
+ connect \A $or$ls180.v:6515$2231_Y
connect \B \builder_interface7_bank_bus_dat_r
- connect \Y $or$ls180.v:6519$2232_Y
+ connect \Y $or$ls180.v:6515$2232_Y
end
- attribute \src "ls180.v:6519.48-6519.383"
- cell $or $or$ls180.v:6519$2233
+ attribute \src "ls180.v:6515.48-6515.383"
+ cell $or $or$ls180.v:6515$2233
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \B_WIDTH 8
parameter \Y_WIDTH 8
- connect \A $or$ls180.v:6519$2232_Y
+ connect \A $or$ls180.v:6515$2232_Y
connect \B \builder_interface8_bank_bus_dat_r
- connect \Y $or$ls180.v:6519$2233_Y
+ connect \Y $or$ls180.v:6515$2233_Y
end
- attribute \src "ls180.v:6519.47-6519.420"
- cell $or $or$ls180.v:6519$2234
+ attribute \src "ls180.v:6515.47-6515.420"
+ cell $or $or$ls180.v:6515$2234
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \B_WIDTH 8
parameter \Y_WIDTH 8
- connect \A $or$ls180.v:6519$2233_Y
+ connect \A $or$ls180.v:6515$2233_Y
connect \B \builder_interface9_bank_bus_dat_r
- connect \Y $or$ls180.v:6519$2234_Y
+ connect \Y $or$ls180.v:6515$2234_Y
end
- attribute \src "ls180.v:6519.46-6519.458"
- cell $or $or$ls180.v:6519$2235
+ attribute \src "ls180.v:6515.46-6515.458"
+ cell $or $or$ls180.v:6515$2235
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \B_WIDTH 8
parameter \Y_WIDTH 8
- connect \A $or$ls180.v:6519$2234_Y
+ connect \A $or$ls180.v:6515$2234_Y
connect \B \builder_interface10_bank_bus_dat_r
- connect \Y $or$ls180.v:6519$2235_Y
+ connect \Y $or$ls180.v:6515$2235_Y
end
- attribute \src "ls180.v:6519.45-6519.496"
- cell $or $or$ls180.v:6519$2236
+ attribute \src "ls180.v:6515.45-6515.496"
+ cell $or $or$ls180.v:6515$2236
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \B_WIDTH 8
parameter \Y_WIDTH 8
- connect \A $or$ls180.v:6519$2235_Y
+ connect \A $or$ls180.v:6515$2235_Y
connect \B \builder_interface11_bank_bus_dat_r
- connect \Y $or$ls180.v:6519$2236_Y
+ connect \Y $or$ls180.v:6515$2236_Y
end
- attribute \src "ls180.v:6519.44-6519.534"
- cell $or $or$ls180.v:6519$2237
+ attribute \src "ls180.v:6515.44-6515.534"
+ cell $or $or$ls180.v:6515$2237
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \B_WIDTH 8
parameter \Y_WIDTH 8
- connect \A $or$ls180.v:6519$2236_Y
+ connect \A $or$ls180.v:6515$2236_Y
connect \B \builder_interface12_bank_bus_dat_r
- connect \Y $or$ls180.v:6519$2237_Y
+ connect \Y $or$ls180.v:6515$2237_Y
end
- attribute \src "ls180.v:6519.43-6519.572"
- cell $or $or$ls180.v:6519$2238
+ attribute \src "ls180.v:6515.43-6515.572"
+ cell $or $or$ls180.v:6515$2238
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \B_WIDTH 8
parameter \Y_WIDTH 8
- connect \A $or$ls180.v:6519$2237_Y
+ connect \A $or$ls180.v:6515$2237_Y
connect \B \builder_interface13_bank_bus_dat_r
- connect \Y $or$ls180.v:6519$2238_Y
+ connect \Y $or$ls180.v:6515$2238_Y
end
- attribute \src "ls180.v:6519.42-6519.610"
- cell $or $or$ls180.v:6519$2239
+ attribute \src "ls180.v:6515.42-6515.610"
+ cell $or $or$ls180.v:6515$2239
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \B_WIDTH 8
parameter \Y_WIDTH 8
- connect \A $or$ls180.v:6519$2238_Y
+ connect \A $or$ls180.v:6515$2238_Y
connect \B \builder_interface14_bank_bus_dat_r
- connect \Y $or$ls180.v:6519$2239_Y
+ connect \Y $or$ls180.v:6515$2239_Y
end
- attribute \src "ls180.v:6846.90-6846.179"
- cell $or $or$ls180.v:6846$2264
+ attribute \src "ls180.v:6842.90-6842.179"
+ cell $or $or$ls180.v:6842$2264
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_locked0
- connect \B $and$ls180.v:6846$2263_Y
- connect \Y $or$ls180.v:6846$2264_Y
+ connect \B $and$ls180.v:6842$2263_Y
+ connect \Y $or$ls180.v:6842$2264_Y
end
- attribute \src "ls180.v:6846.89-6846.254"
- cell $or $or$ls180.v:6846$2267
+ attribute \src "ls180.v:6842.89-6842.254"
+ cell $or $or$ls180.v:6842$2267
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:6846$2264_Y
- connect \B $and$ls180.v:6846$2266_Y
- connect \Y $or$ls180.v:6846$2267_Y
+ connect \A $or$ls180.v:6842$2264_Y
+ connect \B $and$ls180.v:6842$2266_Y
+ connect \Y $or$ls180.v:6842$2267_Y
end
- attribute \src "ls180.v:6846.88-6846.329"
- cell $or $or$ls180.v:6846$2270
+ attribute \src "ls180.v:6842.88-6842.329"
+ cell $or $or$ls180.v:6842$2270
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:6846$2267_Y
- connect \B $and$ls180.v:6846$2269_Y
- connect \Y $or$ls180.v:6846$2270_Y
+ connect \A $or$ls180.v:6842$2267_Y
+ connect \B $and$ls180.v:6842$2269_Y
+ connect \Y $or$ls180.v:6842$2270_Y
end
- attribute \src "ls180.v:6870.90-6870.179"
- cell $or $or$ls180.v:6870$2280
+ attribute \src "ls180.v:6866.90-6866.179"
+ cell $or $or$ls180.v:6866$2280
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_locked1
- connect \B $and$ls180.v:6870$2279_Y
- connect \Y $or$ls180.v:6870$2280_Y
+ connect \B $and$ls180.v:6866$2279_Y
+ connect \Y $or$ls180.v:6866$2280_Y
end
- attribute \src "ls180.v:6870.89-6870.254"
- cell $or $or$ls180.v:6870$2283
+ attribute \src "ls180.v:6866.89-6866.254"
+ cell $or $or$ls180.v:6866$2283
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:6870$2280_Y
- connect \B $and$ls180.v:6870$2282_Y
- connect \Y $or$ls180.v:6870$2283_Y
+ connect \A $or$ls180.v:6866$2280_Y
+ connect \B $and$ls180.v:6866$2282_Y
+ connect \Y $or$ls180.v:6866$2283_Y
end
- attribute \src "ls180.v:6870.88-6870.329"
- cell $or $or$ls180.v:6870$2286
+ attribute \src "ls180.v:6866.88-6866.329"
+ cell $or $or$ls180.v:6866$2286
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:6870$2283_Y
- connect \B $and$ls180.v:6870$2285_Y
- connect \Y $or$ls180.v:6870$2286_Y
+ connect \A $or$ls180.v:6866$2283_Y
+ connect \B $and$ls180.v:6866$2285_Y
+ connect \Y $or$ls180.v:6866$2286_Y
end
- attribute \src "ls180.v:6894.90-6894.179"
- cell $or $or$ls180.v:6894$2296
+ attribute \src "ls180.v:6890.90-6890.179"
+ cell $or $or$ls180.v:6890$2296
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_locked2
- connect \B $and$ls180.v:6894$2295_Y
- connect \Y $or$ls180.v:6894$2296_Y
+ connect \B $and$ls180.v:6890$2295_Y
+ connect \Y $or$ls180.v:6890$2296_Y
end
- attribute \src "ls180.v:6894.89-6894.254"
- cell $or $or$ls180.v:6894$2299
+ attribute \src "ls180.v:6890.89-6890.254"
+ cell $or $or$ls180.v:6890$2299
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:6894$2296_Y
- connect \B $and$ls180.v:6894$2298_Y
- connect \Y $or$ls180.v:6894$2299_Y
+ connect \A $or$ls180.v:6890$2296_Y
+ connect \B $and$ls180.v:6890$2298_Y
+ connect \Y $or$ls180.v:6890$2299_Y
end
- attribute \src "ls180.v:6894.88-6894.329"
- cell $or $or$ls180.v:6894$2302
+ attribute \src "ls180.v:6890.88-6890.329"
+ cell $or $or$ls180.v:6890$2302
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:6894$2299_Y
- connect \B $and$ls180.v:6894$2301_Y
- connect \Y $or$ls180.v:6894$2302_Y
+ connect \A $or$ls180.v:6890$2299_Y
+ connect \B $and$ls180.v:6890$2301_Y
+ connect \Y $or$ls180.v:6890$2302_Y
end
- attribute \src "ls180.v:6918.90-6918.179"
- cell $or $or$ls180.v:6918$2312
+ attribute \src "ls180.v:6914.90-6914.179"
+ cell $or $or$ls180.v:6914$2312
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_locked3
- connect \B $and$ls180.v:6918$2311_Y
- connect \Y $or$ls180.v:6918$2312_Y
+ connect \B $and$ls180.v:6914$2311_Y
+ connect \Y $or$ls180.v:6914$2312_Y
end
- attribute \src "ls180.v:6918.89-6918.254"
- cell $or $or$ls180.v:6918$2315
+ attribute \src "ls180.v:6914.89-6914.254"
+ cell $or $or$ls180.v:6914$2315
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:6918$2312_Y
- connect \B $and$ls180.v:6918$2314_Y
- connect \Y $or$ls180.v:6918$2315_Y
+ connect \A $or$ls180.v:6914$2312_Y
+ connect \B $and$ls180.v:6914$2314_Y
+ connect \Y $or$ls180.v:6914$2315_Y
end
- attribute \src "ls180.v:6918.88-6918.329"
- cell $or $or$ls180.v:6918$2318
+ attribute \src "ls180.v:6914.88-6914.329"
+ cell $or $or$ls180.v:6914$2318
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:6918$2315_Y
- connect \B $and$ls180.v:6918$2317_Y
- connect \Y $or$ls180.v:6918$2318_Y
+ connect \A $or$ls180.v:6914$2315_Y
+ connect \B $and$ls180.v:6914$2317_Y
+ connect \Y $or$ls180.v:6914$2318_Y
end
- attribute \src "ls180.v:7432.20-7432.71"
- cell $or $or$ls180.v:7432$2375
+ attribute \src "ls180.v:7428.20-7428.71"
+ cell $or $or$ls180.v:7428$2375
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_nc [0]
connect \B \main_libresocsim_libresoc_interrupt [0]
- connect \Y $or$ls180.v:7432$2375_Y
+ connect \Y $or$ls180.v:7428$2375_Y
end
- attribute \src "ls180.v:7433.20-7433.71"
- cell $or $or$ls180.v:7433$2376
+ attribute \src "ls180.v:7429.20-7429.71"
+ cell $or $or$ls180.v:7429$2376
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_nc [1]
connect \B \main_libresocsim_libresoc_interrupt [0]
- connect \Y $or$ls180.v:7433$2376_Y
+ connect \Y $or$ls180.v:7429$2376_Y
end
- attribute \src "ls180.v:7434.20-7434.71"
- cell $or $or$ls180.v:7434$2377
+ attribute \src "ls180.v:7430.20-7430.71"
+ cell $or $or$ls180.v:7430$2377
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_nc [2]
connect \B \main_libresocsim_libresoc_interrupt [0]
- connect \Y $or$ls180.v:7434$2377_Y
+ connect \Y $or$ls180.v:7430$2377_Y
end
- attribute \src "ls180.v:7435.20-7435.71"
- cell $or $or$ls180.v:7435$2378
+ attribute \src "ls180.v:7431.20-7431.71"
+ cell $or $or$ls180.v:7431$2378
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_nc [3]
connect \B \main_libresocsim_libresoc_interrupt [0]
- connect \Y $or$ls180.v:7435$2378_Y
+ connect \Y $or$ls180.v:7431$2378_Y
end
- attribute \src "ls180.v:7436.20-7436.71"
- cell $or $or$ls180.v:7436$2379
+ attribute \src "ls180.v:7432.20-7432.71"
+ cell $or $or$ls180.v:7432$2379
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_nc [4]
connect \B \main_libresocsim_libresoc_interrupt [0]
- connect \Y $or$ls180.v:7436$2379_Y
+ connect \Y $or$ls180.v:7432$2379_Y
end
- attribute \src "ls180.v:7437.20-7437.71"
- cell $or $or$ls180.v:7437$2380
+ attribute \src "ls180.v:7433.20-7433.71"
+ cell $or $or$ls180.v:7433$2380
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_nc [5]
connect \B \main_libresocsim_libresoc_interrupt [0]
- connect \Y $or$ls180.v:7437$2380_Y
+ connect \Y $or$ls180.v:7433$2380_Y
end
- attribute \src "ls180.v:7438.20-7438.71"
- cell $or $or$ls180.v:7438$2381
+ attribute \src "ls180.v:7434.20-7434.71"
+ cell $or $or$ls180.v:7434$2381
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_nc [6]
connect \B \main_libresocsim_libresoc_interrupt [0]
- connect \Y $or$ls180.v:7438$2381_Y
+ connect \Y $or$ls180.v:7434$2381_Y
end
- attribute \src "ls180.v:7439.20-7439.71"
- cell $or $or$ls180.v:7439$2382
+ attribute \src "ls180.v:7435.20-7435.71"
+ cell $or $or$ls180.v:7435$2382
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_nc [7]
connect \B \main_libresocsim_libresoc_interrupt [0]
- connect \Y $or$ls180.v:7439$2382_Y
+ connect \Y $or$ls180.v:7435$2382_Y
end
- attribute \src "ls180.v:7440.20-7440.71"
- cell $or $or$ls180.v:7440$2383
+ attribute \src "ls180.v:7436.20-7436.71"
+ cell $or $or$ls180.v:7436$2383
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_nc [8]
connect \B \main_libresocsim_libresoc_interrupt [0]
- connect \Y $or$ls180.v:7440$2383_Y
+ connect \Y $or$ls180.v:7436$2383_Y
end
- attribute \src "ls180.v:7441.20-7441.71"
- cell $or $or$ls180.v:7441$2384
+ attribute \src "ls180.v:7437.20-7437.71"
+ cell $or $or$ls180.v:7437$2384
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_nc [9]
connect \B \main_libresocsim_libresoc_interrupt [0]
- connect \Y $or$ls180.v:7441$2384_Y
+ connect \Y $or$ls180.v:7437$2384_Y
end
- attribute \src "ls180.v:7442.21-7442.73"
- cell $or $or$ls180.v:7442$2385
+ attribute \src "ls180.v:7438.21-7438.73"
+ cell $or $or$ls180.v:7438$2385
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_nc [10]
connect \B \main_libresocsim_libresoc_interrupt [0]
- connect \Y $or$ls180.v:7442$2385_Y
+ connect \Y $or$ls180.v:7438$2385_Y
end
- attribute \src "ls180.v:7443.21-7443.73"
- cell $or $or$ls180.v:7443$2386
+ attribute \src "ls180.v:7439.21-7439.73"
+ cell $or $or$ls180.v:7439$2386
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_nc [11]
connect \B \main_libresocsim_libresoc_interrupt [0]
- connect \Y $or$ls180.v:7443$2386_Y
+ connect \Y $or$ls180.v:7439$2386_Y
end
- attribute \src "ls180.v:7444.21-7444.73"
- cell $or $or$ls180.v:7444$2387
+ attribute \src "ls180.v:7440.21-7440.73"
+ cell $or $or$ls180.v:7440$2387
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_nc [12]
connect \B \main_libresocsim_libresoc_interrupt [0]
- connect \Y $or$ls180.v:7444$2387_Y
+ connect \Y $or$ls180.v:7440$2387_Y
end
- attribute \src "ls180.v:7445.21-7445.73"
- cell $or $or$ls180.v:7445$2388
+ attribute \src "ls180.v:7441.21-7441.73"
+ cell $or $or$ls180.v:7441$2388
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_nc [13]
connect \B \main_libresocsim_libresoc_interrupt [0]
- connect \Y $or$ls180.v:7445$2388_Y
+ connect \Y $or$ls180.v:7441$2388_Y
end
- attribute \src "ls180.v:7446.21-7446.73"
- cell $or $or$ls180.v:7446$2389
+ attribute \src "ls180.v:7442.21-7442.73"
+ cell $or $or$ls180.v:7442$2389
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_nc [14]
connect \B \main_libresocsim_libresoc_interrupt [0]
- connect \Y $or$ls180.v:7446$2389_Y
+ connect \Y $or$ls180.v:7442$2389_Y
end
- attribute \src "ls180.v:7447.21-7447.73"
- cell $or $or$ls180.v:7447$2390
+ attribute \src "ls180.v:7443.21-7443.73"
+ cell $or $or$ls180.v:7443$2390
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_nc [15]
connect \B \main_libresocsim_libresoc_interrupt [0]
- connect \Y $or$ls180.v:7447$2390_Y
+ connect \Y $or$ls180.v:7443$2390_Y
end
- attribute \src "ls180.v:7448.21-7448.73"
- cell $or $or$ls180.v:7448$2391
+ attribute \src "ls180.v:7444.21-7444.73"
+ cell $or $or$ls180.v:7444$2391
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_nc [16]
connect \B \main_libresocsim_libresoc_interrupt [0]
- connect \Y $or$ls180.v:7448$2391_Y
+ connect \Y $or$ls180.v:7444$2391_Y
end
- attribute \src "ls180.v:7449.21-7449.73"
- cell $or $or$ls180.v:7449$2392
+ attribute \src "ls180.v:7445.21-7445.73"
+ cell $or $or$ls180.v:7445$2392
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_nc [17]
connect \B \main_libresocsim_libresoc_interrupt [0]
- connect \Y $or$ls180.v:7449$2392_Y
+ connect \Y $or$ls180.v:7445$2392_Y
end
- attribute \src "ls180.v:7450.21-7450.73"
- cell $or $or$ls180.v:7450$2393
+ attribute \src "ls180.v:7446.21-7446.73"
+ cell $or $or$ls180.v:7446$2393
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_nc [18]
connect \B \main_libresocsim_libresoc_interrupt [0]
- connect \Y $or$ls180.v:7450$2393_Y
+ connect \Y $or$ls180.v:7446$2393_Y
end
- attribute \src "ls180.v:7451.21-7451.73"
- cell $or $or$ls180.v:7451$2394
+ attribute \src "ls180.v:7447.21-7447.73"
+ cell $or $or$ls180.v:7447$2394
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_nc [19]
connect \B \main_libresocsim_libresoc_interrupt [0]
- connect \Y $or$ls180.v:7451$2394_Y
+ connect \Y $or$ls180.v:7447$2394_Y
end
- attribute \src "ls180.v:7452.21-7452.73"
- cell $or $or$ls180.v:7452$2395
+ attribute \src "ls180.v:7448.21-7448.73"
+ cell $or $or$ls180.v:7448$2395
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_nc [20]
connect \B \main_libresocsim_libresoc_interrupt [0]
- connect \Y $or$ls180.v:7452$2395_Y
+ connect \Y $or$ls180.v:7448$2395_Y
end
- attribute \src "ls180.v:7453.21-7453.73"
- cell $or $or$ls180.v:7453$2396
+ attribute \src "ls180.v:7449.21-7449.73"
+ cell $or $or$ls180.v:7449$2396
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_nc [21]
connect \B \main_libresocsim_libresoc_interrupt [0]
- connect \Y $or$ls180.v:7453$2396_Y
+ connect \Y $or$ls180.v:7449$2396_Y
end
- attribute \src "ls180.v:7454.21-7454.73"
- cell $or $or$ls180.v:7454$2397
+ attribute \src "ls180.v:7450.21-7450.73"
+ cell $or $or$ls180.v:7450$2397
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_nc [22]
connect \B \main_libresocsim_libresoc_interrupt [0]
- connect \Y $or$ls180.v:7454$2397_Y
+ connect \Y $or$ls180.v:7450$2397_Y
end
- attribute \src "ls180.v:7455.21-7455.73"
- cell $or $or$ls180.v:7455$2398
+ attribute \src "ls180.v:7451.21-7451.73"
+ cell $or $or$ls180.v:7451$2398
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_nc [23]
connect \B \main_libresocsim_libresoc_interrupt [0]
- connect \Y $or$ls180.v:7455$2398_Y
+ connect \Y $or$ls180.v:7451$2398_Y
end
- attribute \src "ls180.v:7456.7-7456.93"
- cell $or $or$ls180.v:7456$2399
+ attribute \src "ls180.v:7452.7-7452.93"
+ cell $or $or$ls180.v:7452$2399
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_libresocsim_interface0_converted_interface_ack
connect \B \main_libresocsim_converter0_skip
- connect \Y $or$ls180.v:7456$2399_Y
+ connect \Y $or$ls180.v:7452$2399_Y
end
- attribute \src "ls180.v:7467.7-7467.93"
- cell $or $or$ls180.v:7467$2400
+ attribute \src "ls180.v:7463.7-7463.93"
+ cell $or $or$ls180.v:7463$2400
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_libresocsim_interface1_converted_interface_ack
connect \B \main_libresocsim_converter1_skip
- connect \Y $or$ls180.v:7467$2400_Y
+ connect \Y $or$ls180.v:7463$2400_Y
end
- attribute \src "ls180.v:7478.7-7478.93"
- cell $or $or$ls180.v:7478$2401
+ attribute \src "ls180.v:7474.7-7474.93"
+ cell $or $or$ls180.v:7474$2401
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_libresocsim_interface2_converted_interface_ack
connect \B \main_libresocsim_converter2_skip
- connect \Y $or$ls180.v:7478$2401_Y
+ connect \Y $or$ls180.v:7474$2401_Y
end
- attribute \src "ls180.v:7607.7-7607.107"
- cell $or $or$ls180.v:7607$2437
+ attribute \src "ls180.v:7603.7-7603.107"
+ cell $or $or$ls180.v:7603$2437
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $not$ls180.v:7607$2436_Y
+ connect \A $not$ls180.v:7603$2436_Y
connect \B \main_sdram_bankmachine0_cmd_buffer_source_ready
- connect \Y $or$ls180.v:7607$2437_Y
+ connect \Y $or$ls180.v:7603$2437_Y
end
- attribute \src "ls180.v:7653.7-7653.107"
- cell $or $or$ls180.v:7653$2453
+ attribute \src "ls180.v:7649.7-7649.107"
+ cell $or $or$ls180.v:7649$2453
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $not$ls180.v:7653$2452_Y
+ connect \A $not$ls180.v:7649$2452_Y
connect \B \main_sdram_bankmachine1_cmd_buffer_source_ready
- connect \Y $or$ls180.v:7653$2453_Y
+ connect \Y $or$ls180.v:7649$2453_Y
end
- attribute \src "ls180.v:7699.7-7699.107"
- cell $or $or$ls180.v:7699$2469
+ attribute \src "ls180.v:7695.7-7695.107"
+ cell $or $or$ls180.v:7695$2469
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $not$ls180.v:7699$2468_Y
+ connect \A $not$ls180.v:7695$2468_Y
connect \B \main_sdram_bankmachine2_cmd_buffer_source_ready
- connect \Y $or$ls180.v:7699$2469_Y
+ connect \Y $or$ls180.v:7695$2469_Y
end
- attribute \src "ls180.v:7745.7-7745.107"
- cell $or $or$ls180.v:7745$2485
+ attribute \src "ls180.v:7741.7-7741.107"
+ cell $or $or$ls180.v:7741$2485
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $not$ls180.v:7745$2484_Y
+ connect \A $not$ls180.v:7741$2484_Y
connect \B \main_sdram_bankmachine3_cmd_buffer_source_ready
- connect \Y $or$ls180.v:7745$2485_Y
+ connect \Y $or$ls180.v:7741$2485_Y
end
- attribute \src "ls180.v:7933.40-7933.125"
- cell $or $or$ls180.v:7933$2506
+ attribute \src "ls180.v:7929.40-7929.125"
+ cell $or $or$ls180.v:7929$2506
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A 1'0
- connect \B $and$ls180.v:7933$2505_Y
- connect \Y $or$ls180.v:7933$2506_Y
+ connect \B $and$ls180.v:7929$2505_Y
+ connect \Y $or$ls180.v:7929$2506_Y
end
- attribute \src "ls180.v:7933.39-7933.207"
- cell $or $or$ls180.v:7933$2509
+ attribute \src "ls180.v:7929.39-7929.207"
+ cell $or $or$ls180.v:7929$2509
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:7933$2506_Y
- connect \B $and$ls180.v:7933$2508_Y
- connect \Y $or$ls180.v:7933$2509_Y
+ connect \A $or$ls180.v:7929$2506_Y
+ connect \B $and$ls180.v:7929$2508_Y
+ connect \Y $or$ls180.v:7929$2509_Y
end
- attribute \src "ls180.v:7933.38-7933.289"
- cell $or $or$ls180.v:7933$2512
+ attribute \src "ls180.v:7929.38-7929.289"
+ cell $or $or$ls180.v:7929$2512
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:7933$2509_Y
- connect \B $and$ls180.v:7933$2511_Y
- connect \Y $or$ls180.v:7933$2512_Y
+ connect \A $or$ls180.v:7929$2509_Y
+ connect \B $and$ls180.v:7929$2511_Y
+ connect \Y $or$ls180.v:7929$2512_Y
end
- attribute \src "ls180.v:7933.37-7933.371"
- cell $or $or$ls180.v:7933$2515
+ attribute \src "ls180.v:7929.37-7929.371"
+ cell $or $or$ls180.v:7929$2515
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:7933$2512_Y
- connect \B $and$ls180.v:7933$2514_Y
- connect \Y $or$ls180.v:7933$2515_Y
+ connect \A $or$ls180.v:7929$2512_Y
+ connect \B $and$ls180.v:7929$2514_Y
+ connect \Y $or$ls180.v:7929$2515_Y
end
- attribute \src "ls180.v:7934.41-7934.126"
- cell $or $or$ls180.v:7934$2518
+ attribute \src "ls180.v:7930.41-7930.126"
+ cell $or $or$ls180.v:7930$2518
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A 1'0
- connect \B $and$ls180.v:7934$2517_Y
- connect \Y $or$ls180.v:7934$2518_Y
+ connect \B $and$ls180.v:7930$2517_Y
+ connect \Y $or$ls180.v:7930$2518_Y
end
- attribute \src "ls180.v:7934.40-7934.208"
- cell $or $or$ls180.v:7934$2521
+ attribute \src "ls180.v:7930.40-7930.208"
+ cell $or $or$ls180.v:7930$2521
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:7934$2518_Y
- connect \B $and$ls180.v:7934$2520_Y
- connect \Y $or$ls180.v:7934$2521_Y
+ connect \A $or$ls180.v:7930$2518_Y
+ connect \B $and$ls180.v:7930$2520_Y
+ connect \Y $or$ls180.v:7930$2521_Y
end
- attribute \src "ls180.v:7934.39-7934.290"
- cell $or $or$ls180.v:7934$2524
+ attribute \src "ls180.v:7930.39-7930.290"
+ cell $or $or$ls180.v:7930$2524
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:7934$2521_Y
- connect \B $and$ls180.v:7934$2523_Y
- connect \Y $or$ls180.v:7934$2524_Y
+ connect \A $or$ls180.v:7930$2521_Y
+ connect \B $and$ls180.v:7930$2523_Y
+ connect \Y $or$ls180.v:7930$2524_Y
end
- attribute \src "ls180.v:7934.38-7934.372"
- cell $or $or$ls180.v:7934$2527
+ attribute \src "ls180.v:7930.38-7930.372"
+ cell $or $or$ls180.v:7930$2527
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:7934$2524_Y
- connect \B $and$ls180.v:7934$2526_Y
- connect \Y $or$ls180.v:7934$2527_Y
+ connect \A $or$ls180.v:7930$2524_Y
+ connect \B $and$ls180.v:7930$2526_Y
+ connect \Y $or$ls180.v:7930$2527_Y
end
- attribute \src "ls180.v:7938.7-7938.49"
- cell $or $or$ls180.v:7938$2528
+ attribute \src "ls180.v:7934.7-7934.49"
+ cell $or $or$ls180.v:7934$2528
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_litedram_wb_ack
connect \B \main_converter_skip
- connect \Y $or$ls180.v:7938$2528_Y
+ connect \Y $or$ls180.v:7934$2528_Y
end
- attribute \src "ls180.v:8101.21-8101.74"
- cell $or $or$ls180.v:8101$2576
+ attribute \src "ls180.v:8097.21-8097.74"
+ cell $or $or$ls180.v:8097$2576
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $not$ls180.v:8101$2574_Y
- connect \B $not$ls180.v:8101$2575_Y
- connect \Y $or$ls180.v:8101$2576_Y
+ connect \A $not$ls180.v:8097$2574_Y
+ connect \B $not$ls180.v:8097$2575_Y
+ connect \Y $or$ls180.v:8097$2576_Y
end
- attribute \src "ls180.v:8136.21-8136.71"
- cell $or $or$ls180.v:8136$2581
+ attribute \src "ls180.v:8132.21-8132.71"
+ cell $or $or$ls180.v:8132$2581
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $not$ls180.v:8136$2579_Y
- connect \B $not$ls180.v:8136$2580_Y
- connect \Y $or$ls180.v:8136$2581_Y
+ connect \A $not$ls180.v:8132$2579_Y
+ connect \B $not$ls180.v:8132$2580_Y
+ connect \Y $or$ls180.v:8132$2581_Y
end
- attribute \src "ls180.v:8204.32-8204.85"
- cell $or $or$ls180.v:8204$2593
+ attribute \src "ls180.v:8200.32-8200.85"
+ cell $or $or$ls180.v:8200$2593
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdphy_cmdr_cmdr_start
connect \B \main_sdphy_cmdr_cmdr_run
- connect \Y $or$ls180.v:8204$2593_Y
+ connect \Y $or$ls180.v:8200$2593_Y
end
- attribute \src "ls180.v:8210.8-8210.97"
- cell $or $or$ls180.v:8210$2595
+ attribute \src "ls180.v:8206.8-8206.97"
+ cell $or $or$ls180.v:8206$2595
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $eq$ls180.v:8210$2594_Y
+ connect \A $eq$ls180.v:8206$2594_Y
connect \B \main_sdphy_cmdr_cmdr_converter_sink_last
- connect \Y $or$ls180.v:8210$2595_Y
+ connect \Y $or$ls180.v:8206$2595_Y
end
- attribute \src "ls180.v:8227.52-8227.139"
- cell $or $or$ls180.v:8227$2600
+ attribute \src "ls180.v:8223.52-8223.139"
+ cell $or $or$ls180.v:8223$2600
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdphy_cmdr_cmdr_converter_sink_first
connect \B \main_sdphy_cmdr_cmdr_converter_source_first
- connect \Y $or$ls180.v:8227$2600_Y
+ connect \Y $or$ls180.v:8223$2600_Y
end
- attribute \src "ls180.v:8228.51-8228.136"
- cell $or $or$ls180.v:8228$2601
+ attribute \src "ls180.v:8224.51-8224.136"
+ cell $or $or$ls180.v:8224$2601
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdphy_cmdr_cmdr_converter_sink_last
connect \B \main_sdphy_cmdr_cmdr_converter_source_last
- connect \Y $or$ls180.v:8228$2601_Y
+ connect \Y $or$ls180.v:8224$2601_Y
end
- attribute \src "ls180.v:8262.7-8262.87"
- cell $or $or$ls180.v:8262$2604
+ attribute \src "ls180.v:8258.7-8258.87"
+ cell $or $or$ls180.v:8258$2604
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $not$ls180.v:8262$2603_Y
+ connect \A $not$ls180.v:8258$2603_Y
connect \B \main_sdphy_cmdr_cmdr_buf_source_ready
- connect \Y $or$ls180.v:8262$2604_Y
+ connect \Y $or$ls180.v:8258$2604_Y
end
- attribute \src "ls180.v:8285.33-8285.88"
- cell $or $or$ls180.v:8285$2605
+ attribute \src "ls180.v:8281.33-8281.88"
+ cell $or $or$ls180.v:8281$2605
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdphy_dataw_crcr_start
connect \B \main_sdphy_dataw_crcr_run
- connect \Y $or$ls180.v:8285$2605_Y
+ connect \Y $or$ls180.v:8281$2605_Y
end
- attribute \src "ls180.v:8291.8-8291.99"
- cell $or $or$ls180.v:8291$2607
+ attribute \src "ls180.v:8287.8-8287.99"
+ cell $or $or$ls180.v:8287$2607
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $eq$ls180.v:8291$2606_Y
+ connect \A $eq$ls180.v:8287$2606_Y
connect \B \main_sdphy_dataw_crcr_converter_sink_last
- connect \Y $or$ls180.v:8291$2607_Y
+ connect \Y $or$ls180.v:8287$2607_Y
end
- attribute \src "ls180.v:8308.53-8308.142"
- cell $or $or$ls180.v:8308$2612
+ attribute \src "ls180.v:8304.53-8304.142"
+ cell $or $or$ls180.v:8304$2612
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdphy_dataw_crcr_converter_sink_first
connect \B \main_sdphy_dataw_crcr_converter_source_first
- connect \Y $or$ls180.v:8308$2612_Y
+ connect \Y $or$ls180.v:8304$2612_Y
end
- attribute \src "ls180.v:8309.52-8309.139"
- cell $or $or$ls180.v:8309$2613
+ attribute \src "ls180.v:8305.52-8305.139"
+ cell $or $or$ls180.v:8305$2613
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdphy_dataw_crcr_converter_sink_last
connect \B \main_sdphy_dataw_crcr_converter_source_last
- connect \Y $or$ls180.v:8309$2613_Y
+ connect \Y $or$ls180.v:8305$2613_Y
end
- attribute \src "ls180.v:8343.7-8343.89"
- cell $or $or$ls180.v:8343$2616
+ attribute \src "ls180.v:8339.7-8339.89"
+ cell $or $or$ls180.v:8339$2616
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $not$ls180.v:8343$2615_Y
+ connect \A $not$ls180.v:8339$2615_Y
connect \B \main_sdphy_dataw_crcr_buf_source_ready
- connect \Y $or$ls180.v:8343$2616_Y
+ connect \Y $or$ls180.v:8339$2616_Y
end
- attribute \src "ls180.v:8364.34-8364.91"
- cell $or $or$ls180.v:8364$2617
+ attribute \src "ls180.v:8360.34-8360.91"
+ cell $or $or$ls180.v:8360$2617
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdphy_datar_datar_start
connect \B \main_sdphy_datar_datar_run
- connect \Y $or$ls180.v:8364$2617_Y
+ connect \Y $or$ls180.v:8360$2617_Y
end
- attribute \src "ls180.v:8370.8-8370.101"
- cell $or $or$ls180.v:8370$2619
+ attribute \src "ls180.v:8366.8-8366.101"
+ cell $or $or$ls180.v:8366$2619
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $eq$ls180.v:8370$2618_Y
+ connect \A $eq$ls180.v:8366$2618_Y
connect \B \main_sdphy_datar_datar_converter_sink_last
- connect \Y $or$ls180.v:8370$2619_Y
+ connect \Y $or$ls180.v:8366$2619_Y
end
- attribute \src "ls180.v:8387.54-8387.145"
- cell $or $or$ls180.v:8387$2624
+ attribute \src "ls180.v:8383.54-8383.145"
+ cell $or $or$ls180.v:8383$2624
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdphy_datar_datar_converter_sink_first
connect \B \main_sdphy_datar_datar_converter_source_first
- connect \Y $or$ls180.v:8387$2624_Y
+ connect \Y $or$ls180.v:8383$2624_Y
end
- attribute \src "ls180.v:8388.53-8388.142"
- cell $or $or$ls180.v:8388$2625
+ attribute \src "ls180.v:8384.53-8384.142"
+ cell $or $or$ls180.v:8384$2625
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdphy_datar_datar_converter_sink_last
connect \B \main_sdphy_datar_datar_converter_source_last
- connect \Y $or$ls180.v:8388$2625_Y
+ connect \Y $or$ls180.v:8384$2625_Y
end
- attribute \src "ls180.v:8404.7-8404.91"
- cell $or $or$ls180.v:8404$2628
+ attribute \src "ls180.v:8400.7-8400.91"
+ cell $or $or$ls180.v:8400$2628
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $not$ls180.v:8404$2627_Y
+ connect \A $not$ls180.v:8400$2627_Y
connect \B \main_sdphy_datar_datar_buf_source_ready
- connect \Y $or$ls180.v:8404$2628_Y
+ connect \Y $or$ls180.v:8400$2628_Y
end
- attribute \src "ls180.v:8593.8-8593.89"
- cell $or $or$ls180.v:8593$2652
+ attribute \src "ls180.v:8589.8-8589.89"
+ cell $or $or$ls180.v:8589$2652
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $eq$ls180.v:8593$2651_Y
+ connect \A $eq$ls180.v:8589$2651_Y
connect \B \main_sdblock2mem_converter_sink_last
- connect \Y $or$ls180.v:8593$2652_Y
+ connect \Y $or$ls180.v:8589$2652_Y
end
- attribute \src "ls180.v:8610.48-8610.127"
- cell $or $or$ls180.v:8610$2657
+ attribute \src "ls180.v:8606.48-8606.127"
+ cell $or $or$ls180.v:8606$2657
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdblock2mem_converter_sink_first
connect \B \main_sdblock2mem_converter_source_first
- connect \Y $or$ls180.v:8610$2657_Y
+ connect \Y $or$ls180.v:8606$2657_Y
end
- attribute \src "ls180.v:8611.47-8611.124"
- cell $or $or$ls180.v:8611$2658
+ attribute \src "ls180.v:8607.47-8607.124"
+ cell $or $or$ls180.v:8607$2658
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdblock2mem_converter_sink_last
connect \B \main_sdblock2mem_converter_source_last
- connect \Y $or$ls180.v:8611$2658_Y
+ connect \Y $or$ls180.v:8607$2658_Y
end
- attribute \src "ls180.v:3182.46-3182.94"
- cell $sshl $sshl$ls180.v:3182$83
+ attribute \src "ls180.v:3178.46-3178.94"
+ cell $sshl $sshl$ls180.v:3178$83
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 13
connect \A \main_sdram_bankmachine0_auto_precharge
connect \B 4'1010
- connect \Y $sshl$ls180.v:3182$83_Y
+ connect \Y $sshl$ls180.v:3178$83_Y
end
- attribute \src "ls180.v:3339.46-3339.94"
- cell $sshl $sshl$ls180.v:3339$113
+ attribute \src "ls180.v:3335.46-3335.94"
+ cell $sshl $sshl$ls180.v:3335$113
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 13
connect \A \main_sdram_bankmachine1_auto_precharge
connect \B 4'1010
- connect \Y $sshl$ls180.v:3339$113_Y
+ connect \Y $sshl$ls180.v:3335$113_Y
end
- attribute \src "ls180.v:3496.46-3496.94"
- cell $sshl $sshl$ls180.v:3496$143
+ attribute \src "ls180.v:3492.46-3492.94"
+ cell $sshl $sshl$ls180.v:3492$143
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 13
connect \A \main_sdram_bankmachine2_auto_precharge
connect \B 4'1010
- connect \Y $sshl$ls180.v:3496$143_Y
+ connect \Y $sshl$ls180.v:3492$143_Y
end
- attribute \src "ls180.v:3653.46-3653.94"
- cell $sshl $sshl$ls180.v:3653$173
+ attribute \src "ls180.v:3649.46-3649.94"
+ cell $sshl $sshl$ls180.v:3649$173
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 13
connect \A \main_sdram_bankmachine3_auto_precharge
connect \B 4'1010
- connect \Y $sshl$ls180.v:3653$173_Y
+ connect \Y $sshl$ls180.v:3649$173_Y
end
- attribute \src "ls180.v:3213.63-3213.122"
- cell $sub $sub$ls180.v:3213$96
+ attribute \src "ls180.v:3209.63-3209.122"
+ cell $sub $sub$ls180.v:3209$96
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_produce
connect \B 1'1
- connect \Y $sub$ls180.v:3213$96_Y
+ connect \Y $sub$ls180.v:3209$96_Y
end
- attribute \src "ls180.v:3370.63-3370.122"
- cell $sub $sub$ls180.v:3370$126
+ attribute \src "ls180.v:3366.63-3366.122"
+ cell $sub $sub$ls180.v:3366$126
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_produce
connect \B 1'1
- connect \Y $sub$ls180.v:3370$126_Y
+ connect \Y $sub$ls180.v:3366$126_Y
end
- attribute \src "ls180.v:3527.63-3527.122"
- cell $sub $sub$ls180.v:3527$156
+ attribute \src "ls180.v:3523.63-3523.122"
+ cell $sub $sub$ls180.v:3523$156
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_produce
connect \B 1'1
- connect \Y $sub$ls180.v:3527$156_Y
+ connect \Y $sub$ls180.v:3523$156_Y
end
- attribute \src "ls180.v:3684.63-3684.122"
- cell $sub $sub$ls180.v:3684$186
+ attribute \src "ls180.v:3680.63-3680.122"
+ cell $sub $sub$ls180.v:3680$186
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_produce
connect \B 1'1
- connect \Y $sub$ls180.v:3684$186_Y
+ connect \Y $sub$ls180.v:3680$186_Y
end
- attribute \src "ls180.v:4090.38-4090.75"
- cell $sub $sub$ls180.v:4090$540
+ attribute \src "ls180.v:4086.38-4086.75"
+ cell $sub $sub$ls180.v:4086$540
parameter \A_SIGNED 0
parameter \A_WIDTH 30
parameter \B_SIGNED 0
parameter \Y_WIDTH 31
connect \A \main_litedram_wb_adr
connect \B 31'1001000000000000000000000000000
- connect \Y $sub$ls180.v:4090$540_Y
+ connect \Y $sub$ls180.v:4086$540_Y
end
- attribute \src "ls180.v:4176.36-4176.68"
- cell $sub $sub$ls180.v:4176$585
+ attribute \src "ls180.v:4172.36-4172.68"
+ cell $sub $sub$ls180.v:4172$585
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \main_uart_tx_fifo_produce
connect \B 1'1
- connect \Y $sub$ls180.v:4176$585_Y
+ connect \Y $sub$ls180.v:4172$585_Y
end
- attribute \src "ls180.v:4206.36-4206.68"
- cell $sub $sub$ls180.v:4206$596
+ attribute \src "ls180.v:4202.36-4202.68"
+ cell $sub $sub$ls180.v:4202$596
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \main_uart_rx_fifo_produce
connect \B 1'1
- connect \Y $sub$ls180.v:4206$596_Y
+ connect \Y $sub$ls180.v:4202$596_Y
end
- attribute \src "ls180.v:4231.70-4231.110"
- cell $sub $sub$ls180.v:4231$602
+ attribute \src "ls180.v:4227.70-4227.110"
+ cell $sub $sub$ls180.v:4227$602
parameter \A_SIGNED 0
parameter \A_WIDTH 15
parameter \B_SIGNED 0
parameter \Y_WIDTH 16
connect \A \main_spimaster8_clk_divider [15:1]
connect \B 1'1
- connect \Y $sub$ls180.v:4231$602_Y
+ connect \Y $sub$ls180.v:4227$602_Y
end
- attribute \src "ls180.v:4232.70-4232.104"
- cell $sub $sub$ls180.v:4232$604
+ attribute \src "ls180.v:4228.70-4228.104"
+ cell $sub $sub$ls180.v:4228$604
parameter \A_SIGNED 0
parameter \A_WIDTH 16
parameter \B_SIGNED 0
parameter \Y_WIDTH 16
connect \A \main_spimaster8_clk_divider
connect \B 1'1
- connect \Y $sub$ls180.v:4232$604_Y
+ connect \Y $sub$ls180.v:4228$604_Y
end
- attribute \src "ls180.v:4259.37-4259.66"
- cell $sub $sub$ls180.v:4259$608
+ attribute \src "ls180.v:4255.37-4255.66"
+ cell $sub $sub$ls180.v:4255$608
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 8
connect \A \main_spimaster1_length
connect \B 1'1
- connect \Y $sub$ls180.v:4259$608_Y
+ connect \Y $sub$ls180.v:4255$608_Y
end
- attribute \src "ls180.v:4289.67-4289.107"
- cell $sub $sub$ls180.v:4289$610
+ attribute \src "ls180.v:4285.67-4285.107"
+ cell $sub $sub$ls180.v:4285$610
parameter \A_SIGNED 0
parameter \A_WIDTH 15
parameter \B_SIGNED 0
parameter \Y_WIDTH 16
connect \A \main_spisdcard_clk_divider0 [15:1]
connect \B 1'1
- connect \Y $sub$ls180.v:4289$610_Y
+ connect \Y $sub$ls180.v:4285$610_Y
end
- attribute \src "ls180.v:4290.67-4290.101"
- cell $sub $sub$ls180.v:4290$612
+ attribute \src "ls180.v:4286.67-4286.101"
+ cell $sub $sub$ls180.v:4286$612
parameter \A_SIGNED 0
parameter \A_WIDTH 16
parameter \B_SIGNED 0
parameter \Y_WIDTH 16
connect \A \main_spisdcard_clk_divider0
connect \B 1'1
- connect \Y $sub$ls180.v:4290$612_Y
+ connect \Y $sub$ls180.v:4286$612_Y
end
- attribute \src "ls180.v:4318.35-4318.64"
- cell $sub $sub$ls180.v:4318$616
+ attribute \src "ls180.v:4314.35-4314.64"
+ cell $sub $sub$ls180.v:4314$616
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 8
connect \A \main_spisdcard_length0
connect \B 1'1
- connect \Y $sub$ls180.v:4318$616_Y
+ connect \Y $sub$ls180.v:4314$616_Y
end
- attribute \src "ls180.v:4572.60-4572.90"
- cell $sub $sub$ls180.v:4572$660
+ attribute \src "ls180.v:4568.60-4568.90"
+ cell $sub $sub$ls180.v:4568$660
parameter \A_SIGNED 0
parameter \A_WIDTH 32
parameter \B_SIGNED 0
parameter \Y_WIDTH 32
connect \A \main_sdphy_cmdr_timeout
connect \B 1'1
- connect \Y $sub$ls180.v:4572$660_Y
+ connect \Y $sub$ls180.v:4568$660_Y
end
- attribute \src "ls180.v:4583.62-4583.104"
- cell $sub $sub$ls180.v:4583$662
+ attribute \src "ls180.v:4579.62-4579.104"
+ cell $sub $sub$ls180.v:4579$662
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 8
connect \A \main_sdphy_cmdr_sink_payload_length
connect \B 1'1
- connect \Y $sub$ls180.v:4583$662_Y
+ connect \Y $sub$ls180.v:4579$662_Y
end
- attribute \src "ls180.v:4600.60-4600.90"
- cell $sub $sub$ls180.v:4600$666
+ attribute \src "ls180.v:4596.60-4596.90"
+ cell $sub $sub$ls180.v:4596$666
parameter \A_SIGNED 0
parameter \A_WIDTH 32
parameter \B_SIGNED 0
parameter \Y_WIDTH 32
connect \A \main_sdphy_cmdr_timeout
connect \B 1'1
- connect \Y $sub$ls180.v:4600$666_Y
+ connect \Y $sub$ls180.v:4596$666_Y
end
- attribute \src "ls180.v:4829.62-4829.93"
- cell $sub $sub$ls180.v:4829$696
+ attribute \src "ls180.v:4825.62-4825.93"
+ cell $sub $sub$ls180.v:4825$696
parameter \A_SIGNED 0
parameter \A_WIDTH 32
parameter \B_SIGNED 0
parameter \Y_WIDTH 32
connect \A \main_sdphy_datar_timeout
connect \B 1'1
- connect \Y $sub$ls180.v:4829$696_Y
+ connect \Y $sub$ls180.v:4825$696_Y
end
- attribute \src "ls180.v:4834.62-4834.93"
- cell $sub $sub$ls180.v:4834$697
+ attribute \src "ls180.v:4830.62-4830.93"
+ cell $sub $sub$ls180.v:4830$697
parameter \A_SIGNED 0
parameter \A_WIDTH 32
parameter \B_SIGNED 0
parameter \Y_WIDTH 32
connect \A \main_sdphy_datar_timeout
connect \B 1'1
- connect \Y $sub$ls180.v:4834$697_Y
+ connect \Y $sub$ls180.v:4830$697_Y
end
- attribute \src "ls180.v:4845.64-4845.122"
- cell $sub $sub$ls180.v:4845$700
+ attribute \src "ls180.v:4841.64-4841.122"
+ cell $sub $sub$ls180.v:4841$700
parameter \A_SIGNED 0
parameter \A_WIDTH 10
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 10
- connect \A $add$ls180.v:4845$699_Y
+ connect \A $add$ls180.v:4841$699_Y
connect \B 1'1
- connect \Y $sub$ls180.v:4845$700_Y
+ connect \Y $sub$ls180.v:4841$700_Y
end
- attribute \src "ls180.v:4866.62-4866.93"
- cell $sub $sub$ls180.v:4866$703
+ attribute \src "ls180.v:4862.62-4862.93"
+ cell $sub $sub$ls180.v:4862$703
parameter \A_SIGNED 0
parameter \A_WIDTH 32
parameter \B_SIGNED 0
parameter \Y_WIDTH 32
connect \A \main_sdphy_datar_timeout
connect \B 1'1
- connect \Y $sub$ls180.v:4866$703_Y
+ connect \Y $sub$ls180.v:4862$703_Y
end
- attribute \src "ls180.v:5328.37-5328.75"
- cell $sub $sub$ls180.v:5328$976
+ attribute \src "ls180.v:5324.37-5324.75"
+ cell $sub $sub$ls180.v:5324$976
parameter \A_SIGNED 0
parameter \A_WIDTH 32
parameter \B_SIGNED 0
parameter \Y_WIDTH 32
connect \A \main_sdcore_block_count_storage
connect \B 1'1
- connect \Y $sub$ls180.v:5328$976_Y
+ connect \Y $sub$ls180.v:5324$976_Y
end
- attribute \src "ls180.v:5343.62-5343.100"
- cell $sub $sub$ls180.v:5343$979
+ attribute \src "ls180.v:5339.62-5339.100"
+ cell $sub $sub$ls180.v:5339$979
parameter \A_SIGNED 0
parameter \A_WIDTH 32
parameter \B_SIGNED 0
parameter \Y_WIDTH 32
connect \A \main_sdcore_block_count_storage
connect \B 1'1
- connect \Y $sub$ls180.v:5343$979_Y
+ connect \Y $sub$ls180.v:5339$979_Y
end
- attribute \src "ls180.v:5354.39-5354.77"
- cell $sub $sub$ls180.v:5354$984
+ attribute \src "ls180.v:5350.39-5350.77"
+ cell $sub $sub$ls180.v:5350$984
parameter \A_SIGNED 0
parameter \A_WIDTH 32
parameter \B_SIGNED 0
parameter \Y_WIDTH 32
connect \A \main_sdcore_block_count_storage
connect \B 1'1
- connect \Y $sub$ls180.v:5354$984_Y
+ connect \Y $sub$ls180.v:5350$984_Y
end
- attribute \src "ls180.v:5429.40-5429.76"
- cell $sub $sub$ls180.v:5429$988
+ attribute \src "ls180.v:5425.40-5425.76"
+ cell $sub $sub$ls180.v:5425$988
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 5
connect \A \main_sdblock2mem_fifo_produce
connect \B 1'1
- connect \Y $sub$ls180.v:5429$988_Y
+ connect \Y $sub$ls180.v:5425$988_Y
end
- attribute \src "ls180.v:5478.56-5478.104"
- cell $sub $sub$ls180.v:5478$1002
+ attribute \src "ls180.v:5474.56-5474.104"
+ cell $sub $sub$ls180.v:5474$1002
parameter \A_SIGNED 0
parameter \A_WIDTH 32
parameter \B_SIGNED 0
parameter \Y_WIDTH 32
connect \A \main_sdblock2mem_wishbonedmawriter_length
connect \B 1'1
- connect \Y $sub$ls180.v:5478$1002_Y
+ connect \Y $sub$ls180.v:5474$1002_Y
end
- attribute \src "ls180.v:5568.71-5568.105"
- cell $sub $sub$ls180.v:5568$1008
+ attribute \src "ls180.v:5564.71-5564.105"
+ cell $sub $sub$ls180.v:5564$1008
parameter \A_SIGNED 0
parameter \A_WIDTH 32
parameter \B_SIGNED 0
parameter \Y_WIDTH 32
connect \A \main_sdmem2block_dma_length
connect \B 1'1
- connect \Y $sub$ls180.v:5568$1008_Y
+ connect \Y $sub$ls180.v:5564$1008_Y
end
- attribute \src "ls180.v:5637.40-5637.76"
- cell $sub $sub$ls180.v:5637$1019
+ attribute \src "ls180.v:5633.40-5633.76"
+ cell $sub $sub$ls180.v:5633$1019
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 5
connect \A \main_sdmem2block_fifo_produce
connect \B 1'1
- connect \Y $sub$ls180.v:5637$1019_Y
+ connect \Y $sub$ls180.v:5633$1019_Y
end
- attribute \src "ls180.v:7502.31-7502.60"
- cell $sub $sub$ls180.v:7502$2408
+ attribute \src "ls180.v:7498.31-7498.60"
+ cell $sub $sub$ls180.v:7498$2408
parameter \A_SIGNED 0
parameter \A_WIDTH 32
parameter \B_SIGNED 0
parameter \Y_WIDTH 32
connect \A \main_libresocsim_value
connect \B 1'1
- connect \Y $sub$ls180.v:7502$2408_Y
+ connect \Y $sub$ls180.v:7498$2408_Y
end
- attribute \src "ls180.v:7523.31-7523.61"
- cell $sub $sub$ls180.v:7523$2413
+ attribute \src "ls180.v:7519.31-7519.61"
+ cell $sub $sub$ls180.v:7519$2413
parameter \A_SIGNED 0
parameter \A_WIDTH 10
parameter \B_SIGNED 0
parameter \Y_WIDTH 10
connect \A \main_sdram_timer_count1
connect \B 1'1
- connect \Y $sub$ls180.v:7523$2413_Y
+ connect \Y $sub$ls180.v:7519$2413_Y
end
- attribute \src "ls180.v:7529.34-7529.67"
- cell $sub $sub$ls180.v:7529$2414
+ attribute \src "ls180.v:7525.34-7525.67"
+ cell $sub $sub$ls180.v:7525$2414
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_postponer_count
connect \B 1'1
- connect \Y $sub$ls180.v:7529$2414_Y
+ connect \Y $sub$ls180.v:7525$2414_Y
end
- attribute \src "ls180.v:7540.36-7540.69"
- cell $sub $sub$ls180.v:7540$2417
+ attribute \src "ls180.v:7536.36-7536.69"
+ cell $sub $sub$ls180.v:7536$2417
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_sequencer_count
connect \B 1'1
- connect \Y $sub$ls180.v:7540$2417_Y
+ connect \Y $sub$ls180.v:7536$2417_Y
end
- attribute \src "ls180.v:7604.59-7604.116"
- cell $sub $sub$ls180.v:7604$2435
+ attribute \src "ls180.v:7600.59-7600.116"
+ cell $sub $sub$ls180.v:7600$2435
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_level
connect \B 1'1
- connect \Y $sub$ls180.v:7604$2435_Y
+ connect \Y $sub$ls180.v:7600$2435_Y
end
- attribute \src "ls180.v:7623.46-7623.90"
- cell $sub $sub$ls180.v:7623$2439
+ attribute \src "ls180.v:7619.46-7619.90"
+ cell $sub $sub$ls180.v:7619$2439
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \main_sdram_bankmachine0_twtpcon_count
connect \B 1'1
- connect \Y $sub$ls180.v:7623$2439_Y
+ connect \Y $sub$ls180.v:7619$2439_Y
end
- attribute \src "ls180.v:7650.59-7650.116"
- cell $sub $sub$ls180.v:7650$2451
+ attribute \src "ls180.v:7646.59-7646.116"
+ cell $sub $sub$ls180.v:7646$2451
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_level
connect \B 1'1
- connect \Y $sub$ls180.v:7650$2451_Y
+ connect \Y $sub$ls180.v:7646$2451_Y
end
- attribute \src "ls180.v:7669.46-7669.90"
- cell $sub $sub$ls180.v:7669$2455
+ attribute \src "ls180.v:7665.46-7665.90"
+ cell $sub $sub$ls180.v:7665$2455
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \main_sdram_bankmachine1_twtpcon_count
connect \B 1'1
- connect \Y $sub$ls180.v:7669$2455_Y
+ connect \Y $sub$ls180.v:7665$2455_Y
end
- attribute \src "ls180.v:7696.59-7696.116"
- cell $sub $sub$ls180.v:7696$2467
+ attribute \src "ls180.v:7692.59-7692.116"
+ cell $sub $sub$ls180.v:7692$2467
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_level
connect \B 1'1
- connect \Y $sub$ls180.v:7696$2467_Y
+ connect \Y $sub$ls180.v:7692$2467_Y
end
- attribute \src "ls180.v:7715.46-7715.90"
- cell $sub $sub$ls180.v:7715$2471
+ attribute \src "ls180.v:7711.46-7711.90"
+ cell $sub $sub$ls180.v:7711$2471
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \main_sdram_bankmachine2_twtpcon_count
connect \B 1'1
- connect \Y $sub$ls180.v:7715$2471_Y
+ connect \Y $sub$ls180.v:7711$2471_Y
end
- attribute \src "ls180.v:7742.59-7742.116"
- cell $sub $sub$ls180.v:7742$2483
+ attribute \src "ls180.v:7738.59-7738.116"
+ cell $sub $sub$ls180.v:7738$2483
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_level
connect \B 1'1
- connect \Y $sub$ls180.v:7742$2483_Y
+ connect \Y $sub$ls180.v:7738$2483_Y
end
- attribute \src "ls180.v:7761.46-7761.90"
- cell $sub $sub$ls180.v:7761$2487
+ attribute \src "ls180.v:7757.46-7757.90"
+ cell $sub $sub$ls180.v:7757$2487
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \main_sdram_bankmachine3_twtpcon_count
connect \B 1'1
- connect \Y $sub$ls180.v:7761$2487_Y
+ connect \Y $sub$ls180.v:7757$2487_Y
end
- attribute \src "ls180.v:7772.25-7772.48"
- cell $sub $sub$ls180.v:7772$2491
+ attribute \src "ls180.v:7768.25-7768.48"
+ cell $sub $sub$ls180.v:7768$2491
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 5
connect \A \main_sdram_time0
connect \B 1'1
- connect \Y $sub$ls180.v:7772$2491_Y
+ connect \Y $sub$ls180.v:7768$2491_Y
end
- attribute \src "ls180.v:7779.25-7779.48"
- cell $sub $sub$ls180.v:7779$2494
+ attribute \src "ls180.v:7775.25-7775.48"
+ cell $sub $sub$ls180.v:7775$2494
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \main_sdram_time1
connect \B 1'1
- connect \Y $sub$ls180.v:7779$2494_Y
+ connect \Y $sub$ls180.v:7775$2494_Y
end
- attribute \src "ls180.v:7911.33-7911.64"
- cell $sub $sub$ls180.v:7911$2499
+ attribute \src "ls180.v:7907.33-7907.64"
+ cell $sub $sub$ls180.v:7907$2499
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_tccdcon_count
connect \B 1'1
- connect \Y $sub$ls180.v:7911$2499_Y
+ connect \Y $sub$ls180.v:7907$2499_Y
end
- attribute \src "ls180.v:7926.33-7926.64"
- cell $sub $sub$ls180.v:7926$2502
+ attribute \src "ls180.v:7922.33-7922.64"
+ cell $sub $sub$ls180.v:7922$2502
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \main_sdram_twtrcon_count
connect \B 1'1
- connect \Y $sub$ls180.v:7926$2502_Y
+ connect \Y $sub$ls180.v:7922$2502_Y
end
- attribute \src "ls180.v:8053.33-8053.64"
- cell $sub $sub$ls180.v:8053$2561
+ attribute \src "ls180.v:8049.33-8049.64"
+ cell $sub $sub$ls180.v:8049$2561
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 5
connect \A \main_uart_tx_fifo_level0
connect \B 1'1
- connect \Y $sub$ls180.v:8053$2561_Y
+ connect \Y $sub$ls180.v:8049$2561_Y
end
- attribute \src "ls180.v:8075.33-8075.64"
- cell $sub $sub$ls180.v:8075$2572
+ attribute \src "ls180.v:8071.33-8071.64"
+ cell $sub $sub$ls180.v:8071$2572
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 5
connect \A \main_uart_rx_fifo_level0
connect \B 1'1
- connect \Y $sub$ls180.v:8075$2572_Y
+ connect \Y $sub$ls180.v:8071$2572_Y
end
- attribute \src "ls180.v:8110.34-8110.66"
- cell $sub $sub$ls180.v:8110$2577
+ attribute \src "ls180.v:8106.34-8106.66"
+ cell $sub $sub$ls180.v:8106$2577
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \main_spimaster34_mosi_sel
connect \B 1'1
- connect \Y $sub$ls180.v:8110$2577_Y
+ connect \Y $sub$ls180.v:8106$2577_Y
end
- attribute \src "ls180.v:8145.32-8145.62"
- cell $sub $sub$ls180.v:8145$2582
+ attribute \src "ls180.v:8141.32-8141.62"
+ cell $sub $sub$ls180.v:8141$2582
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \main_spisdcard_mosi_sel
connect \B 1'1
- connect \Y $sub$ls180.v:8145$2582_Y
+ connect \Y $sub$ls180.v:8141$2582_Y
end
- attribute \src "ls180.v:8169.30-8169.53"
- cell $sub $sub$ls180.v:8169$2585
+ attribute \src "ls180.v:8165.30-8165.53"
+ cell $sub $sub$ls180.v:8165$2585
parameter \A_SIGNED 0
parameter \A_WIDTH 32
parameter \B_SIGNED 0
parameter \Y_WIDTH 32
connect \A \main_pwm0_period
connect \B 1'1
- connect \Y $sub$ls180.v:8169$2585_Y
+ connect \Y $sub$ls180.v:8165$2585_Y
end
- attribute \src "ls180.v:8183.30-8183.53"
- cell $sub $sub$ls180.v:8183$2589
+ attribute \src "ls180.v:8179.30-8179.53"
+ cell $sub $sub$ls180.v:8179$2589
parameter \A_SIGNED 0
parameter \A_WIDTH 32
parameter \B_SIGNED 0
parameter \Y_WIDTH 32
connect \A \main_pwm1_period
connect \B 1'1
- connect \Y $sub$ls180.v:8183$2589_Y
+ connect \Y $sub$ls180.v:8179$2589_Y
end
- attribute \src "ls180.v:8586.36-8586.70"
- cell $sub $sub$ls180.v:8586$2650
+ attribute \src "ls180.v:8582.36-8582.70"
+ cell $sub $sub$ls180.v:8582$2650
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 6
connect \A \main_sdblock2mem_fifo_level
connect \B 1'1
- connect \Y $sub$ls180.v:8586$2650_Y
+ connect \Y $sub$ls180.v:8582$2650_Y
end
- attribute \src "ls180.v:8672.36-8672.70"
- cell $sub $sub$ls180.v:8672$2672
+ attribute \src "ls180.v:8668.36-8668.70"
+ cell $sub $sub$ls180.v:8668$2672
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 6
connect \A \main_sdmem2block_fifo_level
connect \B 1'1
- connect \Y $sub$ls180.v:8672$2672_Y
+ connect \Y $sub$ls180.v:8668$2672_Y
end
- attribute \src "ls180.v:8785.22-8785.42"
- cell $sub $sub$ls180.v:8785$2679
+ attribute \src "ls180.v:8781.22-8781.42"
+ cell $sub $sub$ls180.v:8781$2679
parameter \A_SIGNED 0
parameter \A_WIDTH 20
parameter \B_SIGNED 0
parameter \Y_WIDTH 20
connect \A \builder_count
connect \B 1'1
- connect \Y $sub$ls180.v:8785$2679_Y
+ connect \Y $sub$ls180.v:8781$2679_Y
end
- attribute \src "ls180.v:4926.353-4926.425"
- cell $xor $xor$ls180.v:4926$710
+ attribute \src "ls180.v:4922.353-4922.425"
+ cell $xor $xor$ls180.v:4922$710
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_val [39]
connect \B \main_sdcore_crc7_inserter_crcreg0 [6]
- connect \Y $xor$ls180.v:4926$710_Y
+ connect \Y $xor$ls180.v:4922$710_Y
end
- attribute \src "ls180.v:4926.200-4926.272"
- cell $xor $xor$ls180.v:4926$711
+ attribute \src "ls180.v:4922.200-4922.272"
+ cell $xor $xor$ls180.v:4922$711
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_val [39]
connect \B \main_sdcore_crc7_inserter_crcreg0 [6]
- connect \Y $xor$ls180.v:4926$711_Y
+ connect \Y $xor$ls180.v:4922$711_Y
end
- attribute \src "ls180.v:4926.160-4926.273"
- cell $xor $xor$ls180.v:4926$712
+ attribute \src "ls180.v:4922.160-4922.273"
+ cell $xor $xor$ls180.v:4922$712
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_crcreg0 [2]
- connect \B $xor$ls180.v:4926$711_Y
- connect \Y $xor$ls180.v:4926$712_Y
+ connect \B $xor$ls180.v:4922$711_Y
+ connect \Y $xor$ls180.v:4922$712_Y
end
- attribute \src "ls180.v:4927.353-4927.425"
- cell $xor $xor$ls180.v:4927$713
+ attribute \src "ls180.v:4923.353-4923.425"
+ cell $xor $xor$ls180.v:4923$713
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_val [38]
connect \B \main_sdcore_crc7_inserter_crcreg1 [6]
- connect \Y $xor$ls180.v:4927$713_Y
+ connect \Y $xor$ls180.v:4923$713_Y
end
- attribute \src "ls180.v:4927.200-4927.272"
- cell $xor $xor$ls180.v:4927$714
+ attribute \src "ls180.v:4923.200-4923.272"
+ cell $xor $xor$ls180.v:4923$714
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_val [38]
connect \B \main_sdcore_crc7_inserter_crcreg1 [6]
- connect \Y $xor$ls180.v:4927$714_Y
+ connect \Y $xor$ls180.v:4923$714_Y
end
- attribute \src "ls180.v:4927.160-4927.273"
- cell $xor $xor$ls180.v:4927$715
+ attribute \src "ls180.v:4923.160-4923.273"
+ cell $xor $xor$ls180.v:4923$715
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_crcreg1 [2]
- connect \B $xor$ls180.v:4927$714_Y
- connect \Y $xor$ls180.v:4927$715_Y
+ connect \B $xor$ls180.v:4923$714_Y
+ connect \Y $xor$ls180.v:4923$715_Y
end
- attribute \src "ls180.v:4928.353-4928.425"
- cell $xor $xor$ls180.v:4928$716
+ attribute \src "ls180.v:4924.353-4924.425"
+ cell $xor $xor$ls180.v:4924$716
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_val [37]
connect \B \main_sdcore_crc7_inserter_crcreg2 [6]
- connect \Y $xor$ls180.v:4928$716_Y
+ connect \Y $xor$ls180.v:4924$716_Y
end
- attribute \src "ls180.v:4928.200-4928.272"
- cell $xor $xor$ls180.v:4928$717
+ attribute \src "ls180.v:4924.200-4924.272"
+ cell $xor $xor$ls180.v:4924$717
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_val [37]
connect \B \main_sdcore_crc7_inserter_crcreg2 [6]
- connect \Y $xor$ls180.v:4928$717_Y
+ connect \Y $xor$ls180.v:4924$717_Y
end
- attribute \src "ls180.v:4928.160-4928.273"
- cell $xor $xor$ls180.v:4928$718
+ attribute \src "ls180.v:4924.160-4924.273"
+ cell $xor $xor$ls180.v:4924$718
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_crcreg2 [2]
- connect \B $xor$ls180.v:4928$717_Y
- connect \Y $xor$ls180.v:4928$718_Y
+ connect \B $xor$ls180.v:4924$717_Y
+ connect \Y $xor$ls180.v:4924$718_Y
end
- attribute \src "ls180.v:4929.353-4929.425"
- cell $xor $xor$ls180.v:4929$719
+ attribute \src "ls180.v:4925.353-4925.425"
+ cell $xor $xor$ls180.v:4925$719
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_val [36]
connect \B \main_sdcore_crc7_inserter_crcreg3 [6]
- connect \Y $xor$ls180.v:4929$719_Y
+ connect \Y $xor$ls180.v:4925$719_Y
end
- attribute \src "ls180.v:4929.200-4929.272"
- cell $xor $xor$ls180.v:4929$720
+ attribute \src "ls180.v:4925.200-4925.272"
+ cell $xor $xor$ls180.v:4925$720
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_val [36]
connect \B \main_sdcore_crc7_inserter_crcreg3 [6]
- connect \Y $xor$ls180.v:4929$720_Y
+ connect \Y $xor$ls180.v:4925$720_Y
end
- attribute \src "ls180.v:4929.160-4929.273"
- cell $xor $xor$ls180.v:4929$721
+ attribute \src "ls180.v:4925.160-4925.273"
+ cell $xor $xor$ls180.v:4925$721
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_crcreg3 [2]
- connect \B $xor$ls180.v:4929$720_Y
- connect \Y $xor$ls180.v:4929$721_Y
+ connect \B $xor$ls180.v:4925$720_Y
+ connect \Y $xor$ls180.v:4925$721_Y
end
- attribute \src "ls180.v:4930.353-4930.425"
- cell $xor $xor$ls180.v:4930$722
+ attribute \src "ls180.v:4926.353-4926.425"
+ cell $xor $xor$ls180.v:4926$722
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_val [35]
connect \B \main_sdcore_crc7_inserter_crcreg4 [6]
- connect \Y $xor$ls180.v:4930$722_Y
+ connect \Y $xor$ls180.v:4926$722_Y
end
- attribute \src "ls180.v:4930.200-4930.272"
- cell $xor $xor$ls180.v:4930$723
+ attribute \src "ls180.v:4926.200-4926.272"
+ cell $xor $xor$ls180.v:4926$723
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_val [35]
connect \B \main_sdcore_crc7_inserter_crcreg4 [6]
- connect \Y $xor$ls180.v:4930$723_Y
+ connect \Y $xor$ls180.v:4926$723_Y
end
- attribute \src "ls180.v:4930.160-4930.273"
- cell $xor $xor$ls180.v:4930$724
+ attribute \src "ls180.v:4926.160-4926.273"
+ cell $xor $xor$ls180.v:4926$724
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_crcreg4 [2]
- connect \B $xor$ls180.v:4930$723_Y
- connect \Y $xor$ls180.v:4930$724_Y
+ connect \B $xor$ls180.v:4926$723_Y
+ connect \Y $xor$ls180.v:4926$724_Y
end
- attribute \src "ls180.v:4931.353-4931.425"
- cell $xor $xor$ls180.v:4931$725
+ attribute \src "ls180.v:4927.353-4927.425"
+ cell $xor $xor$ls180.v:4927$725
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_val [34]
connect \B \main_sdcore_crc7_inserter_crcreg5 [6]
- connect \Y $xor$ls180.v:4931$725_Y
+ connect \Y $xor$ls180.v:4927$725_Y
end
- attribute \src "ls180.v:4931.200-4931.272"
- cell $xor $xor$ls180.v:4931$726
+ attribute \src "ls180.v:4927.200-4927.272"
+ cell $xor $xor$ls180.v:4927$726
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_val [34]
connect \B \main_sdcore_crc7_inserter_crcreg5 [6]
- connect \Y $xor$ls180.v:4931$726_Y
+ connect \Y $xor$ls180.v:4927$726_Y
end
- attribute \src "ls180.v:4931.160-4931.273"
- cell $xor $xor$ls180.v:4931$727
+ attribute \src "ls180.v:4927.160-4927.273"
+ cell $xor $xor$ls180.v:4927$727
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_crcreg5 [2]
- connect \B $xor$ls180.v:4931$726_Y
- connect \Y $xor$ls180.v:4931$727_Y
+ connect \B $xor$ls180.v:4927$726_Y
+ connect \Y $xor$ls180.v:4927$727_Y
end
- attribute \src "ls180.v:4932.353-4932.425"
- cell $xor $xor$ls180.v:4932$728
+ attribute \src "ls180.v:4928.353-4928.425"
+ cell $xor $xor$ls180.v:4928$728
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_val [33]
connect \B \main_sdcore_crc7_inserter_crcreg6 [6]
- connect \Y $xor$ls180.v:4932$728_Y
+ connect \Y $xor$ls180.v:4928$728_Y
end
- attribute \src "ls180.v:4932.200-4932.272"
- cell $xor $xor$ls180.v:4932$729
+ attribute \src "ls180.v:4928.200-4928.272"
+ cell $xor $xor$ls180.v:4928$729
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_val [33]
connect \B \main_sdcore_crc7_inserter_crcreg6 [6]
- connect \Y $xor$ls180.v:4932$729_Y
+ connect \Y $xor$ls180.v:4928$729_Y
end
- attribute \src "ls180.v:4932.160-4932.273"
- cell $xor $xor$ls180.v:4932$730
+ attribute \src "ls180.v:4928.160-4928.273"
+ cell $xor $xor$ls180.v:4928$730
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_crcreg6 [2]
- connect \B $xor$ls180.v:4932$729_Y
- connect \Y $xor$ls180.v:4932$730_Y
+ connect \B $xor$ls180.v:4928$729_Y
+ connect \Y $xor$ls180.v:4928$730_Y
end
- attribute \src "ls180.v:4933.353-4933.425"
- cell $xor $xor$ls180.v:4933$731
+ attribute \src "ls180.v:4929.353-4929.425"
+ cell $xor $xor$ls180.v:4929$731
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_val [32]
connect \B \main_sdcore_crc7_inserter_crcreg7 [6]
- connect \Y $xor$ls180.v:4933$731_Y
+ connect \Y $xor$ls180.v:4929$731_Y
end
- attribute \src "ls180.v:4933.200-4933.272"
- cell $xor $xor$ls180.v:4933$732
+ attribute \src "ls180.v:4929.200-4929.272"
+ cell $xor $xor$ls180.v:4929$732
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_val [32]
connect \B \main_sdcore_crc7_inserter_crcreg7 [6]
- connect \Y $xor$ls180.v:4933$732_Y
+ connect \Y $xor$ls180.v:4929$732_Y
end
- attribute \src "ls180.v:4933.160-4933.273"
- cell $xor $xor$ls180.v:4933$733
+ attribute \src "ls180.v:4929.160-4929.273"
+ cell $xor $xor$ls180.v:4929$733
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_crcreg7 [2]
- connect \B $xor$ls180.v:4933$732_Y
- connect \Y $xor$ls180.v:4933$733_Y
+ connect \B $xor$ls180.v:4929$732_Y
+ connect \Y $xor$ls180.v:4929$733_Y
end
- attribute \src "ls180.v:4934.353-4934.425"
- cell $xor $xor$ls180.v:4934$734
+ attribute \src "ls180.v:4930.353-4930.425"
+ cell $xor $xor$ls180.v:4930$734
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_val [31]
connect \B \main_sdcore_crc7_inserter_crcreg8 [6]
- connect \Y $xor$ls180.v:4934$734_Y
+ connect \Y $xor$ls180.v:4930$734_Y
end
- attribute \src "ls180.v:4934.200-4934.272"
- cell $xor $xor$ls180.v:4934$735
+ attribute \src "ls180.v:4930.200-4930.272"
+ cell $xor $xor$ls180.v:4930$735
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_val [31]
connect \B \main_sdcore_crc7_inserter_crcreg8 [6]
- connect \Y $xor$ls180.v:4934$735_Y
+ connect \Y $xor$ls180.v:4930$735_Y
end
- attribute \src "ls180.v:4934.160-4934.273"
- cell $xor $xor$ls180.v:4934$736
+ attribute \src "ls180.v:4930.160-4930.273"
+ cell $xor $xor$ls180.v:4930$736
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_crcreg8 [2]
- connect \B $xor$ls180.v:4934$735_Y
- connect \Y $xor$ls180.v:4934$736_Y
+ connect \B $xor$ls180.v:4930$735_Y
+ connect \Y $xor$ls180.v:4930$736_Y
end
- attribute \src "ls180.v:4935.354-4935.426"
- cell $xor $xor$ls180.v:4935$737
+ attribute \src "ls180.v:4931.354-4931.426"
+ cell $xor $xor$ls180.v:4931$737
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_val [30]
connect \B \main_sdcore_crc7_inserter_crcreg9 [6]
- connect \Y $xor$ls180.v:4935$737_Y
+ connect \Y $xor$ls180.v:4931$737_Y
end
- attribute \src "ls180.v:4935.201-4935.273"
- cell $xor $xor$ls180.v:4935$738
+ attribute \src "ls180.v:4931.201-4931.273"
+ cell $xor $xor$ls180.v:4931$738
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_val [30]
connect \B \main_sdcore_crc7_inserter_crcreg9 [6]
- connect \Y $xor$ls180.v:4935$738_Y
+ connect \Y $xor$ls180.v:4931$738_Y
end
- attribute \src "ls180.v:4935.161-4935.274"
- cell $xor $xor$ls180.v:4935$739
+ attribute \src "ls180.v:4931.161-4931.274"
+ cell $xor $xor$ls180.v:4931$739
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_crcreg9 [2]
- connect \B $xor$ls180.v:4935$738_Y
- connect \Y $xor$ls180.v:4935$739_Y
+ connect \B $xor$ls180.v:4931$738_Y
+ connect \Y $xor$ls180.v:4931$739_Y
end
- attribute \src "ls180.v:4936.361-4936.434"
- cell $xor $xor$ls180.v:4936$740
+ attribute \src "ls180.v:4932.361-4932.434"
+ cell $xor $xor$ls180.v:4932$740
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_val [29]
connect \B \main_sdcore_crc7_inserter_crcreg10 [6]
- connect \Y $xor$ls180.v:4936$740_Y
+ connect \Y $xor$ls180.v:4932$740_Y
end
- attribute \src "ls180.v:4936.205-4936.278"
- cell $xor $xor$ls180.v:4936$741
+ attribute \src "ls180.v:4932.205-4932.278"
+ cell $xor $xor$ls180.v:4932$741
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_val [29]
connect \B \main_sdcore_crc7_inserter_crcreg10 [6]
- connect \Y $xor$ls180.v:4936$741_Y
+ connect \Y $xor$ls180.v:4932$741_Y
end
- attribute \src "ls180.v:4936.164-4936.279"
- cell $xor $xor$ls180.v:4936$742
+ attribute \src "ls180.v:4932.164-4932.279"
+ cell $xor $xor$ls180.v:4932$742
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_crcreg10 [2]
- connect \B $xor$ls180.v:4936$741_Y
- connect \Y $xor$ls180.v:4936$742_Y
+ connect \B $xor$ls180.v:4932$741_Y
+ connect \Y $xor$ls180.v:4932$742_Y
end
- attribute \src "ls180.v:4937.361-4937.434"
- cell $xor $xor$ls180.v:4937$743
+ attribute \src "ls180.v:4933.361-4933.434"
+ cell $xor $xor$ls180.v:4933$743
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_val [28]
connect \B \main_sdcore_crc7_inserter_crcreg11 [6]
- connect \Y $xor$ls180.v:4937$743_Y
+ connect \Y $xor$ls180.v:4933$743_Y
end
- attribute \src "ls180.v:4937.205-4937.278"
- cell $xor $xor$ls180.v:4937$744
+ attribute \src "ls180.v:4933.205-4933.278"
+ cell $xor $xor$ls180.v:4933$744
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_val [28]
connect \B \main_sdcore_crc7_inserter_crcreg11 [6]
- connect \Y $xor$ls180.v:4937$744_Y
+ connect \Y $xor$ls180.v:4933$744_Y
end
- attribute \src "ls180.v:4937.164-4937.279"
- cell $xor $xor$ls180.v:4937$745
+ attribute \src "ls180.v:4933.164-4933.279"
+ cell $xor $xor$ls180.v:4933$745
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_crcreg11 [2]
- connect \B $xor$ls180.v:4937$744_Y
- connect \Y $xor$ls180.v:4937$745_Y
+ connect \B $xor$ls180.v:4933$744_Y
+ connect \Y $xor$ls180.v:4933$745_Y
end
- attribute \src "ls180.v:4938.361-4938.434"
- cell $xor $xor$ls180.v:4938$746
+ attribute \src "ls180.v:4934.361-4934.434"
+ cell $xor $xor$ls180.v:4934$746
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_val [27]
connect \B \main_sdcore_crc7_inserter_crcreg12 [6]
- connect \Y $xor$ls180.v:4938$746_Y
+ connect \Y $xor$ls180.v:4934$746_Y
end
- attribute \src "ls180.v:4938.205-4938.278"
- cell $xor $xor$ls180.v:4938$747
+ attribute \src "ls180.v:4934.205-4934.278"
+ cell $xor $xor$ls180.v:4934$747
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_val [27]
connect \B \main_sdcore_crc7_inserter_crcreg12 [6]
- connect \Y $xor$ls180.v:4938$747_Y
+ connect \Y $xor$ls180.v:4934$747_Y
end
- attribute \src "ls180.v:4938.164-4938.279"
- cell $xor $xor$ls180.v:4938$748
+ attribute \src "ls180.v:4934.164-4934.279"
+ cell $xor $xor$ls180.v:4934$748
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_crcreg12 [2]
- connect \B $xor$ls180.v:4938$747_Y
- connect \Y $xor$ls180.v:4938$748_Y
+ connect \B $xor$ls180.v:4934$747_Y
+ connect \Y $xor$ls180.v:4934$748_Y
end
- attribute \src "ls180.v:4939.361-4939.434"
- cell $xor $xor$ls180.v:4939$749
+ attribute \src "ls180.v:4935.361-4935.434"
+ cell $xor $xor$ls180.v:4935$749
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_val [26]
connect \B \main_sdcore_crc7_inserter_crcreg13 [6]
- connect \Y $xor$ls180.v:4939$749_Y
+ connect \Y $xor$ls180.v:4935$749_Y
end
- attribute \src "ls180.v:4939.205-4939.278"
- cell $xor $xor$ls180.v:4939$750
+ attribute \src "ls180.v:4935.205-4935.278"
+ cell $xor $xor$ls180.v:4935$750
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_val [26]
connect \B \main_sdcore_crc7_inserter_crcreg13 [6]
- connect \Y $xor$ls180.v:4939$750_Y
+ connect \Y $xor$ls180.v:4935$750_Y
end
- attribute \src "ls180.v:4939.164-4939.279"
- cell $xor $xor$ls180.v:4939$751
+ attribute \src "ls180.v:4935.164-4935.279"
+ cell $xor $xor$ls180.v:4935$751
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_crcreg13 [2]
- connect \B $xor$ls180.v:4939$750_Y
- connect \Y $xor$ls180.v:4939$751_Y
+ connect \B $xor$ls180.v:4935$750_Y
+ connect \Y $xor$ls180.v:4935$751_Y
end
- attribute \src "ls180.v:4940.361-4940.434"
- cell $xor $xor$ls180.v:4940$752
+ attribute \src "ls180.v:4936.361-4936.434"
+ cell $xor $xor$ls180.v:4936$752
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_val [25]
connect \B \main_sdcore_crc7_inserter_crcreg14 [6]
- connect \Y $xor$ls180.v:4940$752_Y
+ connect \Y $xor$ls180.v:4936$752_Y
end
- attribute \src "ls180.v:4940.205-4940.278"
- cell $xor $xor$ls180.v:4940$753
+ attribute \src "ls180.v:4936.205-4936.278"
+ cell $xor $xor$ls180.v:4936$753
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_val [25]
connect \B \main_sdcore_crc7_inserter_crcreg14 [6]
- connect \Y $xor$ls180.v:4940$753_Y
+ connect \Y $xor$ls180.v:4936$753_Y
end
- attribute \src "ls180.v:4940.164-4940.279"
- cell $xor $xor$ls180.v:4940$754
+ attribute \src "ls180.v:4936.164-4936.279"
+ cell $xor $xor$ls180.v:4936$754
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_crcreg14 [2]
- connect \B $xor$ls180.v:4940$753_Y
- connect \Y $xor$ls180.v:4940$754_Y
+ connect \B $xor$ls180.v:4936$753_Y
+ connect \Y $xor$ls180.v:4936$754_Y
end
- attribute \src "ls180.v:4941.361-4941.434"
- cell $xor $xor$ls180.v:4941$755
+ attribute \src "ls180.v:4937.361-4937.434"
+ cell $xor $xor$ls180.v:4937$755
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_val [24]
connect \B \main_sdcore_crc7_inserter_crcreg15 [6]
- connect \Y $xor$ls180.v:4941$755_Y
+ connect \Y $xor$ls180.v:4937$755_Y
end
- attribute \src "ls180.v:4941.205-4941.278"
- cell $xor $xor$ls180.v:4941$756
+ attribute \src "ls180.v:4937.205-4937.278"
+ cell $xor $xor$ls180.v:4937$756
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_val [24]
connect \B \main_sdcore_crc7_inserter_crcreg15 [6]
- connect \Y $xor$ls180.v:4941$756_Y
+ connect \Y $xor$ls180.v:4937$756_Y
end
- attribute \src "ls180.v:4941.164-4941.279"
- cell $xor $xor$ls180.v:4941$757
+ attribute \src "ls180.v:4937.164-4937.279"
+ cell $xor $xor$ls180.v:4937$757
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_crcreg15 [2]
- connect \B $xor$ls180.v:4941$756_Y
- connect \Y $xor$ls180.v:4941$757_Y
+ connect \B $xor$ls180.v:4937$756_Y
+ connect \Y $xor$ls180.v:4937$757_Y
end
- attribute \src "ls180.v:4942.361-4942.434"
- cell $xor $xor$ls180.v:4942$758
+ attribute \src "ls180.v:4938.361-4938.434"
+ cell $xor $xor$ls180.v:4938$758
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_val [23]
connect \B \main_sdcore_crc7_inserter_crcreg16 [6]
- connect \Y $xor$ls180.v:4942$758_Y
+ connect \Y $xor$ls180.v:4938$758_Y
end
- attribute \src "ls180.v:4942.205-4942.278"
- cell $xor $xor$ls180.v:4942$759
+ attribute \src "ls180.v:4938.205-4938.278"
+ cell $xor $xor$ls180.v:4938$759
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_val [23]
connect \B \main_sdcore_crc7_inserter_crcreg16 [6]
- connect \Y $xor$ls180.v:4942$759_Y
+ connect \Y $xor$ls180.v:4938$759_Y
end
- attribute \src "ls180.v:4942.164-4942.279"
- cell $xor $xor$ls180.v:4942$760
+ attribute \src "ls180.v:4938.164-4938.279"
+ cell $xor $xor$ls180.v:4938$760
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_crcreg16 [2]
- connect \B $xor$ls180.v:4942$759_Y
- connect \Y $xor$ls180.v:4942$760_Y
+ connect \B $xor$ls180.v:4938$759_Y
+ connect \Y $xor$ls180.v:4938$760_Y
end
- attribute \src "ls180.v:4943.361-4943.434"
- cell $xor $xor$ls180.v:4943$761
+ attribute \src "ls180.v:4939.361-4939.434"
+ cell $xor $xor$ls180.v:4939$761
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_val [22]
connect \B \main_sdcore_crc7_inserter_crcreg17 [6]
- connect \Y $xor$ls180.v:4943$761_Y
+ connect \Y $xor$ls180.v:4939$761_Y
end
- attribute \src "ls180.v:4943.205-4943.278"
- cell $xor $xor$ls180.v:4943$762
+ attribute \src "ls180.v:4939.205-4939.278"
+ cell $xor $xor$ls180.v:4939$762
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_val [22]
connect \B \main_sdcore_crc7_inserter_crcreg17 [6]
- connect \Y $xor$ls180.v:4943$762_Y
+ connect \Y $xor$ls180.v:4939$762_Y
end
- attribute \src "ls180.v:4943.164-4943.279"
- cell $xor $xor$ls180.v:4943$763
+ attribute \src "ls180.v:4939.164-4939.279"
+ cell $xor $xor$ls180.v:4939$763
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_crcreg17 [2]
- connect \B $xor$ls180.v:4943$762_Y
- connect \Y $xor$ls180.v:4943$763_Y
+ connect \B $xor$ls180.v:4939$762_Y
+ connect \Y $xor$ls180.v:4939$763_Y
end
- attribute \src "ls180.v:4944.361-4944.434"
- cell $xor $xor$ls180.v:4944$764
+ attribute \src "ls180.v:4940.361-4940.434"
+ cell $xor $xor$ls180.v:4940$764
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_val [21]
connect \B \main_sdcore_crc7_inserter_crcreg18 [6]
- connect \Y $xor$ls180.v:4944$764_Y
+ connect \Y $xor$ls180.v:4940$764_Y
end
- attribute \src "ls180.v:4944.205-4944.278"
- cell $xor $xor$ls180.v:4944$765
+ attribute \src "ls180.v:4940.205-4940.278"
+ cell $xor $xor$ls180.v:4940$765
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_val [21]
connect \B \main_sdcore_crc7_inserter_crcreg18 [6]
- connect \Y $xor$ls180.v:4944$765_Y
+ connect \Y $xor$ls180.v:4940$765_Y
end
- attribute \src "ls180.v:4944.164-4944.279"
- cell $xor $xor$ls180.v:4944$766
+ attribute \src "ls180.v:4940.164-4940.279"
+ cell $xor $xor$ls180.v:4940$766
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_crcreg18 [2]
- connect \B $xor$ls180.v:4944$765_Y
- connect \Y $xor$ls180.v:4944$766_Y
+ connect \B $xor$ls180.v:4940$765_Y
+ connect \Y $xor$ls180.v:4940$766_Y
end
- attribute \src "ls180.v:4945.361-4945.434"
- cell $xor $xor$ls180.v:4945$767
+ attribute \src "ls180.v:4941.361-4941.434"
+ cell $xor $xor$ls180.v:4941$767
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_val [20]
connect \B \main_sdcore_crc7_inserter_crcreg19 [6]
- connect \Y $xor$ls180.v:4945$767_Y
+ connect \Y $xor$ls180.v:4941$767_Y
end
- attribute \src "ls180.v:4945.205-4945.278"
- cell $xor $xor$ls180.v:4945$768
+ attribute \src "ls180.v:4941.205-4941.278"
+ cell $xor $xor$ls180.v:4941$768
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_val [20]
connect \B \main_sdcore_crc7_inserter_crcreg19 [6]
- connect \Y $xor$ls180.v:4945$768_Y
+ connect \Y $xor$ls180.v:4941$768_Y
end
- attribute \src "ls180.v:4945.164-4945.279"
- cell $xor $xor$ls180.v:4945$769
+ attribute \src "ls180.v:4941.164-4941.279"
+ cell $xor $xor$ls180.v:4941$769
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_crcreg19 [2]
- connect \B $xor$ls180.v:4945$768_Y
- connect \Y $xor$ls180.v:4945$769_Y
+ connect \B $xor$ls180.v:4941$768_Y
+ connect \Y $xor$ls180.v:4941$769_Y
end
- attribute \src "ls180.v:4946.361-4946.434"
- cell $xor $xor$ls180.v:4946$770
+ attribute \src "ls180.v:4942.361-4942.434"
+ cell $xor $xor$ls180.v:4942$770
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_val [19]
connect \B \main_sdcore_crc7_inserter_crcreg20 [6]
- connect \Y $xor$ls180.v:4946$770_Y
+ connect \Y $xor$ls180.v:4942$770_Y
end
- attribute \src "ls180.v:4946.205-4946.278"
- cell $xor $xor$ls180.v:4946$771
+ attribute \src "ls180.v:4942.205-4942.278"
+ cell $xor $xor$ls180.v:4942$771
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_val [19]
connect \B \main_sdcore_crc7_inserter_crcreg20 [6]
- connect \Y $xor$ls180.v:4946$771_Y
+ connect \Y $xor$ls180.v:4942$771_Y
end
- attribute \src "ls180.v:4946.164-4946.279"
- cell $xor $xor$ls180.v:4946$772
+ attribute \src "ls180.v:4942.164-4942.279"
+ cell $xor $xor$ls180.v:4942$772
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_crcreg20 [2]
- connect \B $xor$ls180.v:4946$771_Y
- connect \Y $xor$ls180.v:4946$772_Y
+ connect \B $xor$ls180.v:4942$771_Y
+ connect \Y $xor$ls180.v:4942$772_Y
end
- attribute \src "ls180.v:4947.361-4947.434"
- cell $xor $xor$ls180.v:4947$773
+ attribute \src "ls180.v:4943.361-4943.434"
+ cell $xor $xor$ls180.v:4943$773
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_val [18]
connect \B \main_sdcore_crc7_inserter_crcreg21 [6]
- connect \Y $xor$ls180.v:4947$773_Y
+ connect \Y $xor$ls180.v:4943$773_Y
end
- attribute \src "ls180.v:4947.205-4947.278"
- cell $xor $xor$ls180.v:4947$774
+ attribute \src "ls180.v:4943.205-4943.278"
+ cell $xor $xor$ls180.v:4943$774
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_val [18]
connect \B \main_sdcore_crc7_inserter_crcreg21 [6]
- connect \Y $xor$ls180.v:4947$774_Y
+ connect \Y $xor$ls180.v:4943$774_Y
end
- attribute \src "ls180.v:4947.164-4947.279"
- cell $xor $xor$ls180.v:4947$775
+ attribute \src "ls180.v:4943.164-4943.279"
+ cell $xor $xor$ls180.v:4943$775
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_crcreg21 [2]
- connect \B $xor$ls180.v:4947$774_Y
- connect \Y $xor$ls180.v:4947$775_Y
+ connect \B $xor$ls180.v:4943$774_Y
+ connect \Y $xor$ls180.v:4943$775_Y
end
- attribute \src "ls180.v:4948.361-4948.434"
- cell $xor $xor$ls180.v:4948$776
+ attribute \src "ls180.v:4944.361-4944.434"
+ cell $xor $xor$ls180.v:4944$776
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_val [17]
connect \B \main_sdcore_crc7_inserter_crcreg22 [6]
- connect \Y $xor$ls180.v:4948$776_Y
+ connect \Y $xor$ls180.v:4944$776_Y
end
- attribute \src "ls180.v:4948.205-4948.278"
- cell $xor $xor$ls180.v:4948$777
+ attribute \src "ls180.v:4944.205-4944.278"
+ cell $xor $xor$ls180.v:4944$777
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_val [17]
connect \B \main_sdcore_crc7_inserter_crcreg22 [6]
- connect \Y $xor$ls180.v:4948$777_Y
+ connect \Y $xor$ls180.v:4944$777_Y
end
- attribute \src "ls180.v:4948.164-4948.279"
- cell $xor $xor$ls180.v:4948$778
+ attribute \src "ls180.v:4944.164-4944.279"
+ cell $xor $xor$ls180.v:4944$778
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_crcreg22 [2]
- connect \B $xor$ls180.v:4948$777_Y
- connect \Y $xor$ls180.v:4948$778_Y
+ connect \B $xor$ls180.v:4944$777_Y
+ connect \Y $xor$ls180.v:4944$778_Y
end
- attribute \src "ls180.v:4949.361-4949.434"
- cell $xor $xor$ls180.v:4949$779
+ attribute \src "ls180.v:4945.361-4945.434"
+ cell $xor $xor$ls180.v:4945$779
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_val [16]
connect \B \main_sdcore_crc7_inserter_crcreg23 [6]
- connect \Y $xor$ls180.v:4949$779_Y
+ connect \Y $xor$ls180.v:4945$779_Y
end
- attribute \src "ls180.v:4949.205-4949.278"
- cell $xor $xor$ls180.v:4949$780
+ attribute \src "ls180.v:4945.205-4945.278"
+ cell $xor $xor$ls180.v:4945$780
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_val [16]
connect \B \main_sdcore_crc7_inserter_crcreg23 [6]
- connect \Y $xor$ls180.v:4949$780_Y
+ connect \Y $xor$ls180.v:4945$780_Y
end
- attribute \src "ls180.v:4949.164-4949.279"
- cell $xor $xor$ls180.v:4949$781
+ attribute \src "ls180.v:4945.164-4945.279"
+ cell $xor $xor$ls180.v:4945$781
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_crcreg23 [2]
- connect \B $xor$ls180.v:4949$780_Y
- connect \Y $xor$ls180.v:4949$781_Y
+ connect \B $xor$ls180.v:4945$780_Y
+ connect \Y $xor$ls180.v:4945$781_Y
end
- attribute \src "ls180.v:4950.361-4950.434"
- cell $xor $xor$ls180.v:4950$782
+ attribute \src "ls180.v:4946.361-4946.434"
+ cell $xor $xor$ls180.v:4946$782
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_val [15]
connect \B \main_sdcore_crc7_inserter_crcreg24 [6]
- connect \Y $xor$ls180.v:4950$782_Y
+ connect \Y $xor$ls180.v:4946$782_Y
end
- attribute \src "ls180.v:4950.205-4950.278"
- cell $xor $xor$ls180.v:4950$783
+ attribute \src "ls180.v:4946.205-4946.278"
+ cell $xor $xor$ls180.v:4946$783
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_val [15]
connect \B \main_sdcore_crc7_inserter_crcreg24 [6]
- connect \Y $xor$ls180.v:4950$783_Y
+ connect \Y $xor$ls180.v:4946$783_Y
end
- attribute \src "ls180.v:4950.164-4950.279"
- cell $xor $xor$ls180.v:4950$784
+ attribute \src "ls180.v:4946.164-4946.279"
+ cell $xor $xor$ls180.v:4946$784
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_crcreg24 [2]
- connect \B $xor$ls180.v:4950$783_Y
- connect \Y $xor$ls180.v:4950$784_Y
+ connect \B $xor$ls180.v:4946$783_Y
+ connect \Y $xor$ls180.v:4946$784_Y
end
- attribute \src "ls180.v:4951.361-4951.434"
- cell $xor $xor$ls180.v:4951$785
+ attribute \src "ls180.v:4947.361-4947.434"
+ cell $xor $xor$ls180.v:4947$785
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_val [14]
connect \B \main_sdcore_crc7_inserter_crcreg25 [6]
- connect \Y $xor$ls180.v:4951$785_Y
+ connect \Y $xor$ls180.v:4947$785_Y
end
- attribute \src "ls180.v:4951.205-4951.278"
- cell $xor $xor$ls180.v:4951$786
+ attribute \src "ls180.v:4947.205-4947.278"
+ cell $xor $xor$ls180.v:4947$786
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_val [14]
connect \B \main_sdcore_crc7_inserter_crcreg25 [6]
- connect \Y $xor$ls180.v:4951$786_Y
+ connect \Y $xor$ls180.v:4947$786_Y
end
- attribute \src "ls180.v:4951.164-4951.279"
- cell $xor $xor$ls180.v:4951$787
+ attribute \src "ls180.v:4947.164-4947.279"
+ cell $xor $xor$ls180.v:4947$787
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_crcreg25 [2]
- connect \B $xor$ls180.v:4951$786_Y
- connect \Y $xor$ls180.v:4951$787_Y
+ connect \B $xor$ls180.v:4947$786_Y
+ connect \Y $xor$ls180.v:4947$787_Y
end
- attribute \src "ls180.v:4952.361-4952.434"
- cell $xor $xor$ls180.v:4952$788
+ attribute \src "ls180.v:4948.361-4948.434"
+ cell $xor $xor$ls180.v:4948$788
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_val [13]
connect \B \main_sdcore_crc7_inserter_crcreg26 [6]
- connect \Y $xor$ls180.v:4952$788_Y
+ connect \Y $xor$ls180.v:4948$788_Y
end
- attribute \src "ls180.v:4952.205-4952.278"
- cell $xor $xor$ls180.v:4952$789
+ attribute \src "ls180.v:4948.205-4948.278"
+ cell $xor $xor$ls180.v:4948$789
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_val [13]
connect \B \main_sdcore_crc7_inserter_crcreg26 [6]
- connect \Y $xor$ls180.v:4952$789_Y
+ connect \Y $xor$ls180.v:4948$789_Y
end
- attribute \src "ls180.v:4952.164-4952.279"
- cell $xor $xor$ls180.v:4952$790
+ attribute \src "ls180.v:4948.164-4948.279"
+ cell $xor $xor$ls180.v:4948$790
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_crcreg26 [2]
- connect \B $xor$ls180.v:4952$789_Y
- connect \Y $xor$ls180.v:4952$790_Y
+ connect \B $xor$ls180.v:4948$789_Y
+ connect \Y $xor$ls180.v:4948$790_Y
end
- attribute \src "ls180.v:4953.361-4953.434"
- cell $xor $xor$ls180.v:4953$791
+ attribute \src "ls180.v:4949.361-4949.434"
+ cell $xor $xor$ls180.v:4949$791
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_val [12]
connect \B \main_sdcore_crc7_inserter_crcreg27 [6]
- connect \Y $xor$ls180.v:4953$791_Y
+ connect \Y $xor$ls180.v:4949$791_Y
end
- attribute \src "ls180.v:4953.205-4953.278"
- cell $xor $xor$ls180.v:4953$792
+ attribute \src "ls180.v:4949.205-4949.278"
+ cell $xor $xor$ls180.v:4949$792
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_val [12]
connect \B \main_sdcore_crc7_inserter_crcreg27 [6]
- connect \Y $xor$ls180.v:4953$792_Y
+ connect \Y $xor$ls180.v:4949$792_Y
end
- attribute \src "ls180.v:4953.164-4953.279"
- cell $xor $xor$ls180.v:4953$793
+ attribute \src "ls180.v:4949.164-4949.279"
+ cell $xor $xor$ls180.v:4949$793
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_crcreg27 [2]
- connect \B $xor$ls180.v:4953$792_Y
- connect \Y $xor$ls180.v:4953$793_Y
+ connect \B $xor$ls180.v:4949$792_Y
+ connect \Y $xor$ls180.v:4949$793_Y
end
- attribute \src "ls180.v:4954.361-4954.434"
- cell $xor $xor$ls180.v:4954$794
+ attribute \src "ls180.v:4950.361-4950.434"
+ cell $xor $xor$ls180.v:4950$794
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_val [11]
connect \B \main_sdcore_crc7_inserter_crcreg28 [6]
- connect \Y $xor$ls180.v:4954$794_Y
+ connect \Y $xor$ls180.v:4950$794_Y
end
- attribute \src "ls180.v:4954.205-4954.278"
- cell $xor $xor$ls180.v:4954$795
+ attribute \src "ls180.v:4950.205-4950.278"
+ cell $xor $xor$ls180.v:4950$795
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_val [11]
connect \B \main_sdcore_crc7_inserter_crcreg28 [6]
- connect \Y $xor$ls180.v:4954$795_Y
+ connect \Y $xor$ls180.v:4950$795_Y
end
- attribute \src "ls180.v:4954.164-4954.279"
- cell $xor $xor$ls180.v:4954$796
+ attribute \src "ls180.v:4950.164-4950.279"
+ cell $xor $xor$ls180.v:4950$796
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_crcreg28 [2]
- connect \B $xor$ls180.v:4954$795_Y
- connect \Y $xor$ls180.v:4954$796_Y
+ connect \B $xor$ls180.v:4950$795_Y
+ connect \Y $xor$ls180.v:4950$796_Y
end
- attribute \src "ls180.v:4955.361-4955.434"
- cell $xor $xor$ls180.v:4955$797
+ attribute \src "ls180.v:4951.361-4951.434"
+ cell $xor $xor$ls180.v:4951$797
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_val [10]
connect \B \main_sdcore_crc7_inserter_crcreg29 [6]
- connect \Y $xor$ls180.v:4955$797_Y
+ connect \Y $xor$ls180.v:4951$797_Y
end
- attribute \src "ls180.v:4955.205-4955.278"
- cell $xor $xor$ls180.v:4955$798
+ attribute \src "ls180.v:4951.205-4951.278"
+ cell $xor $xor$ls180.v:4951$798
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_val [10]
connect \B \main_sdcore_crc7_inserter_crcreg29 [6]
- connect \Y $xor$ls180.v:4955$798_Y
+ connect \Y $xor$ls180.v:4951$798_Y
end
- attribute \src "ls180.v:4955.164-4955.279"
- cell $xor $xor$ls180.v:4955$799
+ attribute \src "ls180.v:4951.164-4951.279"
+ cell $xor $xor$ls180.v:4951$799
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_crcreg29 [2]
- connect \B $xor$ls180.v:4955$798_Y
- connect \Y $xor$ls180.v:4955$799_Y
+ connect \B $xor$ls180.v:4951$798_Y
+ connect \Y $xor$ls180.v:4951$799_Y
end
- attribute \src "ls180.v:4956.360-4956.432"
- cell $xor $xor$ls180.v:4956$800
+ attribute \src "ls180.v:4952.360-4952.432"
+ cell $xor $xor$ls180.v:4952$800
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_val [9]
connect \B \main_sdcore_crc7_inserter_crcreg30 [6]
- connect \Y $xor$ls180.v:4956$800_Y
+ connect \Y $xor$ls180.v:4952$800_Y
end
- attribute \src "ls180.v:4956.205-4956.277"
- cell $xor $xor$ls180.v:4956$801
+ attribute \src "ls180.v:4952.205-4952.277"
+ cell $xor $xor$ls180.v:4952$801
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_val [9]
connect \B \main_sdcore_crc7_inserter_crcreg30 [6]
- connect \Y $xor$ls180.v:4956$801_Y
+ connect \Y $xor$ls180.v:4952$801_Y
end
- attribute \src "ls180.v:4956.164-4956.278"
- cell $xor $xor$ls180.v:4956$802
+ attribute \src "ls180.v:4952.164-4952.278"
+ cell $xor $xor$ls180.v:4952$802
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_crcreg30 [2]
- connect \B $xor$ls180.v:4956$801_Y
- connect \Y $xor$ls180.v:4956$802_Y
+ connect \B $xor$ls180.v:4952$801_Y
+ connect \Y $xor$ls180.v:4952$802_Y
end
- attribute \src "ls180.v:4957.360-4957.432"
- cell $xor $xor$ls180.v:4957$803
+ attribute \src "ls180.v:4953.360-4953.432"
+ cell $xor $xor$ls180.v:4953$803
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_val [8]
connect \B \main_sdcore_crc7_inserter_crcreg31 [6]
- connect \Y $xor$ls180.v:4957$803_Y
+ connect \Y $xor$ls180.v:4953$803_Y
end
- attribute \src "ls180.v:4957.205-4957.277"
- cell $xor $xor$ls180.v:4957$804
+ attribute \src "ls180.v:4953.205-4953.277"
+ cell $xor $xor$ls180.v:4953$804
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_val [8]
connect \B \main_sdcore_crc7_inserter_crcreg31 [6]
- connect \Y $xor$ls180.v:4957$804_Y
+ connect \Y $xor$ls180.v:4953$804_Y
end
- attribute \src "ls180.v:4957.164-4957.278"
- cell $xor $xor$ls180.v:4957$805
+ attribute \src "ls180.v:4953.164-4953.278"
+ cell $xor $xor$ls180.v:4953$805
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_crcreg31 [2]
- connect \B $xor$ls180.v:4957$804_Y
- connect \Y $xor$ls180.v:4957$805_Y
+ connect \B $xor$ls180.v:4953$804_Y
+ connect \Y $xor$ls180.v:4953$805_Y
end
- attribute \src "ls180.v:4958.360-4958.432"
- cell $xor $xor$ls180.v:4958$806
+ attribute \src "ls180.v:4954.360-4954.432"
+ cell $xor $xor$ls180.v:4954$806
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_val [7]
connect \B \main_sdcore_crc7_inserter_crcreg32 [6]
- connect \Y $xor$ls180.v:4958$806_Y
+ connect \Y $xor$ls180.v:4954$806_Y
end
- attribute \src "ls180.v:4958.205-4958.277"
- cell $xor $xor$ls180.v:4958$807
+ attribute \src "ls180.v:4954.205-4954.277"
+ cell $xor $xor$ls180.v:4954$807
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_val [7]
connect \B \main_sdcore_crc7_inserter_crcreg32 [6]
- connect \Y $xor$ls180.v:4958$807_Y
+ connect \Y $xor$ls180.v:4954$807_Y
end
- attribute \src "ls180.v:4958.164-4958.278"
- cell $xor $xor$ls180.v:4958$808
+ attribute \src "ls180.v:4954.164-4954.278"
+ cell $xor $xor$ls180.v:4954$808
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_crcreg32 [2]
- connect \B $xor$ls180.v:4958$807_Y
- connect \Y $xor$ls180.v:4958$808_Y
+ connect \B $xor$ls180.v:4954$807_Y
+ connect \Y $xor$ls180.v:4954$808_Y
end
- attribute \src "ls180.v:4959.360-4959.432"
- cell $xor $xor$ls180.v:4959$809
+ attribute \src "ls180.v:4955.360-4955.432"
+ cell $xor $xor$ls180.v:4955$809
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_val [6]
connect \B \main_sdcore_crc7_inserter_crcreg33 [6]
- connect \Y $xor$ls180.v:4959$809_Y
+ connect \Y $xor$ls180.v:4955$809_Y
end
- attribute \src "ls180.v:4959.205-4959.277"
- cell $xor $xor$ls180.v:4959$810
+ attribute \src "ls180.v:4955.205-4955.277"
+ cell $xor $xor$ls180.v:4955$810
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_val [6]
connect \B \main_sdcore_crc7_inserter_crcreg33 [6]
- connect \Y $xor$ls180.v:4959$810_Y
+ connect \Y $xor$ls180.v:4955$810_Y
end
- attribute \src "ls180.v:4959.164-4959.278"
- cell $xor $xor$ls180.v:4959$811
+ attribute \src "ls180.v:4955.164-4955.278"
+ cell $xor $xor$ls180.v:4955$811
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_crcreg33 [2]
- connect \B $xor$ls180.v:4959$810_Y
- connect \Y $xor$ls180.v:4959$811_Y
+ connect \B $xor$ls180.v:4955$810_Y
+ connect \Y $xor$ls180.v:4955$811_Y
end
- attribute \src "ls180.v:4960.360-4960.432"
- cell $xor $xor$ls180.v:4960$812
+ attribute \src "ls180.v:4956.360-4956.432"
+ cell $xor $xor$ls180.v:4956$812
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_val [5]
connect \B \main_sdcore_crc7_inserter_crcreg34 [6]
- connect \Y $xor$ls180.v:4960$812_Y
+ connect \Y $xor$ls180.v:4956$812_Y
end
- attribute \src "ls180.v:4960.205-4960.277"
- cell $xor $xor$ls180.v:4960$813
+ attribute \src "ls180.v:4956.205-4956.277"
+ cell $xor $xor$ls180.v:4956$813
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_val [5]
connect \B \main_sdcore_crc7_inserter_crcreg34 [6]
- connect \Y $xor$ls180.v:4960$813_Y
+ connect \Y $xor$ls180.v:4956$813_Y
end
- attribute \src "ls180.v:4960.164-4960.278"
- cell $xor $xor$ls180.v:4960$814
+ attribute \src "ls180.v:4956.164-4956.278"
+ cell $xor $xor$ls180.v:4956$814
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_crcreg34 [2]
- connect \B $xor$ls180.v:4960$813_Y
- connect \Y $xor$ls180.v:4960$814_Y
+ connect \B $xor$ls180.v:4956$813_Y
+ connect \Y $xor$ls180.v:4956$814_Y
end
- attribute \src "ls180.v:4961.360-4961.432"
- cell $xor $xor$ls180.v:4961$815
+ attribute \src "ls180.v:4957.360-4957.432"
+ cell $xor $xor$ls180.v:4957$815
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_val [4]
connect \B \main_sdcore_crc7_inserter_crcreg35 [6]
- connect \Y $xor$ls180.v:4961$815_Y
+ connect \Y $xor$ls180.v:4957$815_Y
end
- attribute \src "ls180.v:4961.205-4961.277"
- cell $xor $xor$ls180.v:4961$816
+ attribute \src "ls180.v:4957.205-4957.277"
+ cell $xor $xor$ls180.v:4957$816
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_val [4]
connect \B \main_sdcore_crc7_inserter_crcreg35 [6]
- connect \Y $xor$ls180.v:4961$816_Y
+ connect \Y $xor$ls180.v:4957$816_Y
end
- attribute \src "ls180.v:4961.164-4961.278"
- cell $xor $xor$ls180.v:4961$817
+ attribute \src "ls180.v:4957.164-4957.278"
+ cell $xor $xor$ls180.v:4957$817
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_crcreg35 [2]
- connect \B $xor$ls180.v:4961$816_Y
- connect \Y $xor$ls180.v:4961$817_Y
+ connect \B $xor$ls180.v:4957$816_Y
+ connect \Y $xor$ls180.v:4957$817_Y
end
- attribute \src "ls180.v:4962.360-4962.432"
- cell $xor $xor$ls180.v:4962$818
+ attribute \src "ls180.v:4958.360-4958.432"
+ cell $xor $xor$ls180.v:4958$818
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_val [3]
connect \B \main_sdcore_crc7_inserter_crcreg36 [6]
- connect \Y $xor$ls180.v:4962$818_Y
+ connect \Y $xor$ls180.v:4958$818_Y
end
- attribute \src "ls180.v:4962.205-4962.277"
- cell $xor $xor$ls180.v:4962$819
+ attribute \src "ls180.v:4958.205-4958.277"
+ cell $xor $xor$ls180.v:4958$819
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_val [3]
connect \B \main_sdcore_crc7_inserter_crcreg36 [6]
- connect \Y $xor$ls180.v:4962$819_Y
+ connect \Y $xor$ls180.v:4958$819_Y
end
- attribute \src "ls180.v:4962.164-4962.278"
- cell $xor $xor$ls180.v:4962$820
+ attribute \src "ls180.v:4958.164-4958.278"
+ cell $xor $xor$ls180.v:4958$820
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_crcreg36 [2]
- connect \B $xor$ls180.v:4962$819_Y
- connect \Y $xor$ls180.v:4962$820_Y
+ connect \B $xor$ls180.v:4958$819_Y
+ connect \Y $xor$ls180.v:4958$820_Y
end
- attribute \src "ls180.v:4963.360-4963.432"
- cell $xor $xor$ls180.v:4963$821
+ attribute \src "ls180.v:4959.360-4959.432"
+ cell $xor $xor$ls180.v:4959$821
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_val [2]
connect \B \main_sdcore_crc7_inserter_crcreg37 [6]
- connect \Y $xor$ls180.v:4963$821_Y
+ connect \Y $xor$ls180.v:4959$821_Y
end
- attribute \src "ls180.v:4963.205-4963.277"
- cell $xor $xor$ls180.v:4963$822
+ attribute \src "ls180.v:4959.205-4959.277"
+ cell $xor $xor$ls180.v:4959$822
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_val [2]
connect \B \main_sdcore_crc7_inserter_crcreg37 [6]
- connect \Y $xor$ls180.v:4963$822_Y
+ connect \Y $xor$ls180.v:4959$822_Y
end
- attribute \src "ls180.v:4963.164-4963.278"
- cell $xor $xor$ls180.v:4963$823
+ attribute \src "ls180.v:4959.164-4959.278"
+ cell $xor $xor$ls180.v:4959$823
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_crcreg37 [2]
- connect \B $xor$ls180.v:4963$822_Y
- connect \Y $xor$ls180.v:4963$823_Y
+ connect \B $xor$ls180.v:4959$822_Y
+ connect \Y $xor$ls180.v:4959$823_Y
end
- attribute \src "ls180.v:4964.360-4964.432"
- cell $xor $xor$ls180.v:4964$824
+ attribute \src "ls180.v:4960.360-4960.432"
+ cell $xor $xor$ls180.v:4960$824
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_val [1]
connect \B \main_sdcore_crc7_inserter_crcreg38 [6]
- connect \Y $xor$ls180.v:4964$824_Y
+ connect \Y $xor$ls180.v:4960$824_Y
end
- attribute \src "ls180.v:4964.205-4964.277"
- cell $xor $xor$ls180.v:4964$825
+ attribute \src "ls180.v:4960.205-4960.277"
+ cell $xor $xor$ls180.v:4960$825
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_val [1]
connect \B \main_sdcore_crc7_inserter_crcreg38 [6]
- connect \Y $xor$ls180.v:4964$825_Y
+ connect \Y $xor$ls180.v:4960$825_Y
end
- attribute \src "ls180.v:4964.164-4964.278"
- cell $xor $xor$ls180.v:4964$826
+ attribute \src "ls180.v:4960.164-4960.278"
+ cell $xor $xor$ls180.v:4960$826
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_crcreg38 [2]
- connect \B $xor$ls180.v:4964$825_Y
- connect \Y $xor$ls180.v:4964$826_Y
+ connect \B $xor$ls180.v:4960$825_Y
+ connect \Y $xor$ls180.v:4960$826_Y
end
- attribute \src "ls180.v:4965.360-4965.432"
- cell $xor $xor$ls180.v:4965$827
+ attribute \src "ls180.v:4961.360-4961.432"
+ cell $xor $xor$ls180.v:4961$827
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_val [0]
connect \B \main_sdcore_crc7_inserter_crcreg39 [6]
- connect \Y $xor$ls180.v:4965$827_Y
+ connect \Y $xor$ls180.v:4961$827_Y
end
- attribute \src "ls180.v:4965.205-4965.277"
- cell $xor $xor$ls180.v:4965$828
+ attribute \src "ls180.v:4961.205-4961.277"
+ cell $xor $xor$ls180.v:4961$828
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_val [0]
connect \B \main_sdcore_crc7_inserter_crcreg39 [6]
- connect \Y $xor$ls180.v:4965$828_Y
+ connect \Y $xor$ls180.v:4961$828_Y
end
- attribute \src "ls180.v:4965.164-4965.278"
- cell $xor $xor$ls180.v:4965$829
+ attribute \src "ls180.v:4961.164-4961.278"
+ cell $xor $xor$ls180.v:4961$829
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_crcreg39 [2]
- connect \B $xor$ls180.v:4965$828_Y
- connect \Y $xor$ls180.v:4965$829_Y
+ connect \B $xor$ls180.v:4961$828_Y
+ connect \Y $xor$ls180.v:4961$829_Y
end
- attribute \src "ls180.v:4986.899-4986.983"
- cell $xor $xor$ls180.v:4986$843
+ attribute \src "ls180.v:4982.899-4982.983"
+ cell $xor $xor$ls180.v:4982$843
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_inserter_crc0_val [1]
connect \B \main_sdcore_crc16_inserter_crc0_crcreg0 [15]
- connect \Y $xor$ls180.v:4986$843_Y
+ connect \Y $xor$ls180.v:4982$843_Y
end
- attribute \src "ls180.v:4986.634-4986.718"
- cell $xor $xor$ls180.v:4986$844
+ attribute \src "ls180.v:4982.634-4982.718"
+ cell $xor $xor$ls180.v:4982$844
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_inserter_crc0_val [1]
connect \B \main_sdcore_crc16_inserter_crc0_crcreg0 [15]
- connect \Y $xor$ls180.v:4986$844_Y
+ connect \Y $xor$ls180.v:4982$844_Y
end
- attribute \src "ls180.v:4986.588-4986.719"
- cell $xor $xor$ls180.v:4986$845
+ attribute \src "ls180.v:4982.588-4982.719"
+ cell $xor $xor$ls180.v:4982$845
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_inserter_crc0_crcreg0 [4]
- connect \B $xor$ls180.v:4986$844_Y
- connect \Y $xor$ls180.v:4986$845_Y
+ connect \B $xor$ls180.v:4982$844_Y
+ connect \Y $xor$ls180.v:4982$845_Y
end
- attribute \src "ls180.v:4986.234-4986.318"
- cell $xor $xor$ls180.v:4986$846
+ attribute \src "ls180.v:4982.234-4982.318"
+ cell $xor $xor$ls180.v:4982$846
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_inserter_crc0_val [1]
connect \B \main_sdcore_crc16_inserter_crc0_crcreg0 [15]
- connect \Y $xor$ls180.v:4986$846_Y
+ connect \Y $xor$ls180.v:4982$846_Y
end
- attribute \src "ls180.v:4986.187-4986.319"
- cell $xor $xor$ls180.v:4986$847
+ attribute \src "ls180.v:4982.187-4982.319"
+ cell $xor $xor$ls180.v:4982$847
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_inserter_crc0_crcreg0 [11]
- connect \B $xor$ls180.v:4986$846_Y
- connect \Y $xor$ls180.v:4986$847_Y
+ connect \B $xor$ls180.v:4982$846_Y
+ connect \Y $xor$ls180.v:4982$847_Y
end
- attribute \src "ls180.v:4987.899-4987.983"
- cell $xor $xor$ls180.v:4987$848
+ attribute \src "ls180.v:4983.899-4983.983"
+ cell $xor $xor$ls180.v:4983$848
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_inserter_crc0_val [0]
connect \B \main_sdcore_crc16_inserter_crc0_crcreg1 [15]
- connect \Y $xor$ls180.v:4987$848_Y
+ connect \Y $xor$ls180.v:4983$848_Y
end
- attribute \src "ls180.v:4987.634-4987.718"
- cell $xor $xor$ls180.v:4987$849
+ attribute \src "ls180.v:4983.634-4983.718"
+ cell $xor $xor$ls180.v:4983$849
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_inserter_crc0_val [0]
connect \B \main_sdcore_crc16_inserter_crc0_crcreg1 [15]
- connect \Y $xor$ls180.v:4987$849_Y
+ connect \Y $xor$ls180.v:4983$849_Y
end
- attribute \src "ls180.v:4987.588-4987.719"
- cell $xor $xor$ls180.v:4987$850
+ attribute \src "ls180.v:4983.588-4983.719"
+ cell $xor $xor$ls180.v:4983$850
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_inserter_crc0_crcreg1 [4]
- connect \B $xor$ls180.v:4987$849_Y
- connect \Y $xor$ls180.v:4987$850_Y
+ connect \B $xor$ls180.v:4983$849_Y
+ connect \Y $xor$ls180.v:4983$850_Y
end
- attribute \src "ls180.v:4987.234-4987.318"
- cell $xor $xor$ls180.v:4987$851
+ attribute \src "ls180.v:4983.234-4983.318"
+ cell $xor $xor$ls180.v:4983$851
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_inserter_crc0_val [0]
connect \B \main_sdcore_crc16_inserter_crc0_crcreg1 [15]
- connect \Y $xor$ls180.v:4987$851_Y
+ connect \Y $xor$ls180.v:4983$851_Y
end
- attribute \src "ls180.v:4987.187-4987.319"
- cell $xor $xor$ls180.v:4987$852
+ attribute \src "ls180.v:4983.187-4983.319"
+ cell $xor $xor$ls180.v:4983$852
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_inserter_crc0_crcreg1 [11]
- connect \B $xor$ls180.v:4987$851_Y
- connect \Y $xor$ls180.v:4987$852_Y
+ connect \B $xor$ls180.v:4983$851_Y
+ connect \Y $xor$ls180.v:4983$852_Y
end
- attribute \src "ls180.v:4996.899-4996.983"
- cell $xor $xor$ls180.v:4996$854
+ attribute \src "ls180.v:4992.899-4992.983"
+ cell $xor $xor$ls180.v:4992$854
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_inserter_crc1_val [1]
connect \B \main_sdcore_crc16_inserter_crc1_crcreg0 [15]
- connect \Y $xor$ls180.v:4996$854_Y
+ connect \Y $xor$ls180.v:4992$854_Y
end
- attribute \src "ls180.v:4996.634-4996.718"
- cell $xor $xor$ls180.v:4996$855
+ attribute \src "ls180.v:4992.634-4992.718"
+ cell $xor $xor$ls180.v:4992$855
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_inserter_crc1_val [1]
connect \B \main_sdcore_crc16_inserter_crc1_crcreg0 [15]
- connect \Y $xor$ls180.v:4996$855_Y
+ connect \Y $xor$ls180.v:4992$855_Y
end
- attribute \src "ls180.v:4996.588-4996.719"
- cell $xor $xor$ls180.v:4996$856
+ attribute \src "ls180.v:4992.588-4992.719"
+ cell $xor $xor$ls180.v:4992$856
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_inserter_crc1_crcreg0 [4]
- connect \B $xor$ls180.v:4996$855_Y
- connect \Y $xor$ls180.v:4996$856_Y
+ connect \B $xor$ls180.v:4992$855_Y
+ connect \Y $xor$ls180.v:4992$856_Y
end
- attribute \src "ls180.v:4996.234-4996.318"
- cell $xor $xor$ls180.v:4996$857
+ attribute \src "ls180.v:4992.234-4992.318"
+ cell $xor $xor$ls180.v:4992$857
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_inserter_crc1_val [1]
connect \B \main_sdcore_crc16_inserter_crc1_crcreg0 [15]
- connect \Y $xor$ls180.v:4996$857_Y
+ connect \Y $xor$ls180.v:4992$857_Y
end
- attribute \src "ls180.v:4996.187-4996.319"
- cell $xor $xor$ls180.v:4996$858
+ attribute \src "ls180.v:4992.187-4992.319"
+ cell $xor $xor$ls180.v:4992$858
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_inserter_crc1_crcreg0 [11]
- connect \B $xor$ls180.v:4996$857_Y
- connect \Y $xor$ls180.v:4996$858_Y
+ connect \B $xor$ls180.v:4992$857_Y
+ connect \Y $xor$ls180.v:4992$858_Y
end
- attribute \src "ls180.v:4997.899-4997.983"
- cell $xor $xor$ls180.v:4997$859
+ attribute \src "ls180.v:4993.899-4993.983"
+ cell $xor $xor$ls180.v:4993$859
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_inserter_crc1_val [0]
connect \B \main_sdcore_crc16_inserter_crc1_crcreg1 [15]
- connect \Y $xor$ls180.v:4997$859_Y
+ connect \Y $xor$ls180.v:4993$859_Y
end
- attribute \src "ls180.v:4997.634-4997.718"
- cell $xor $xor$ls180.v:4997$860
+ attribute \src "ls180.v:4993.634-4993.718"
+ cell $xor $xor$ls180.v:4993$860
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_inserter_crc1_val [0]
connect \B \main_sdcore_crc16_inserter_crc1_crcreg1 [15]
- connect \Y $xor$ls180.v:4997$860_Y
+ connect \Y $xor$ls180.v:4993$860_Y
end
- attribute \src "ls180.v:4997.588-4997.719"
- cell $xor $xor$ls180.v:4997$861
+ attribute \src "ls180.v:4993.588-4993.719"
+ cell $xor $xor$ls180.v:4993$861
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_inserter_crc1_crcreg1 [4]
- connect \B $xor$ls180.v:4997$860_Y
- connect \Y $xor$ls180.v:4997$861_Y
+ connect \B $xor$ls180.v:4993$860_Y
+ connect \Y $xor$ls180.v:4993$861_Y
end
- attribute \src "ls180.v:4997.234-4997.318"
- cell $xor $xor$ls180.v:4997$862
+ attribute \src "ls180.v:4993.234-4993.318"
+ cell $xor $xor$ls180.v:4993$862
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_inserter_crc1_val [0]
connect \B \main_sdcore_crc16_inserter_crc1_crcreg1 [15]
- connect \Y $xor$ls180.v:4997$862_Y
+ connect \Y $xor$ls180.v:4993$862_Y
end
- attribute \src "ls180.v:4997.187-4997.319"
- cell $xor $xor$ls180.v:4997$863
+ attribute \src "ls180.v:4993.187-4993.319"
+ cell $xor $xor$ls180.v:4993$863
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_inserter_crc1_crcreg1 [11]
- connect \B $xor$ls180.v:4997$862_Y
- connect \Y $xor$ls180.v:4997$863_Y
+ connect \B $xor$ls180.v:4993$862_Y
+ connect \Y $xor$ls180.v:4993$863_Y
end
- attribute \src "ls180.v:5006.899-5006.983"
- cell $xor $xor$ls180.v:5006$865
+ attribute \src "ls180.v:5002.899-5002.983"
+ cell $xor $xor$ls180.v:5002$865
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_inserter_crc2_val [1]
connect \B \main_sdcore_crc16_inserter_crc2_crcreg0 [15]
- connect \Y $xor$ls180.v:5006$865_Y
+ connect \Y $xor$ls180.v:5002$865_Y
end
- attribute \src "ls180.v:5006.634-5006.718"
- cell $xor $xor$ls180.v:5006$866
+ attribute \src "ls180.v:5002.634-5002.718"
+ cell $xor $xor$ls180.v:5002$866
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_inserter_crc2_val [1]
connect \B \main_sdcore_crc16_inserter_crc2_crcreg0 [15]
- connect \Y $xor$ls180.v:5006$866_Y
+ connect \Y $xor$ls180.v:5002$866_Y
end
- attribute \src "ls180.v:5006.588-5006.719"
- cell $xor $xor$ls180.v:5006$867
+ attribute \src "ls180.v:5002.588-5002.719"
+ cell $xor $xor$ls180.v:5002$867
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_inserter_crc2_crcreg0 [4]
- connect \B $xor$ls180.v:5006$866_Y
- connect \Y $xor$ls180.v:5006$867_Y
+ connect \B $xor$ls180.v:5002$866_Y
+ connect \Y $xor$ls180.v:5002$867_Y
end
- attribute \src "ls180.v:5006.234-5006.318"
- cell $xor $xor$ls180.v:5006$868
+ attribute \src "ls180.v:5002.234-5002.318"
+ cell $xor $xor$ls180.v:5002$868
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_inserter_crc2_val [1]
connect \B \main_sdcore_crc16_inserter_crc2_crcreg0 [15]
- connect \Y $xor$ls180.v:5006$868_Y
+ connect \Y $xor$ls180.v:5002$868_Y
end
- attribute \src "ls180.v:5006.187-5006.319"
- cell $xor $xor$ls180.v:5006$869
+ attribute \src "ls180.v:5002.187-5002.319"
+ cell $xor $xor$ls180.v:5002$869
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_inserter_crc2_crcreg0 [11]
- connect \B $xor$ls180.v:5006$868_Y
- connect \Y $xor$ls180.v:5006$869_Y
+ connect \B $xor$ls180.v:5002$868_Y
+ connect \Y $xor$ls180.v:5002$869_Y
end
- attribute \src "ls180.v:5007.899-5007.983"
- cell $xor $xor$ls180.v:5007$870
+ attribute \src "ls180.v:5003.899-5003.983"
+ cell $xor $xor$ls180.v:5003$870
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_inserter_crc2_val [0]
connect \B \main_sdcore_crc16_inserter_crc2_crcreg1 [15]
- connect \Y $xor$ls180.v:5007$870_Y
+ connect \Y $xor$ls180.v:5003$870_Y
end
- attribute \src "ls180.v:5007.634-5007.718"
- cell $xor $xor$ls180.v:5007$871
+ attribute \src "ls180.v:5003.634-5003.718"
+ cell $xor $xor$ls180.v:5003$871
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_inserter_crc2_val [0]
connect \B \main_sdcore_crc16_inserter_crc2_crcreg1 [15]
- connect \Y $xor$ls180.v:5007$871_Y
+ connect \Y $xor$ls180.v:5003$871_Y
end
- attribute \src "ls180.v:5007.588-5007.719"
- cell $xor $xor$ls180.v:5007$872
+ attribute \src "ls180.v:5003.588-5003.719"
+ cell $xor $xor$ls180.v:5003$872
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_inserter_crc2_crcreg1 [4]
- connect \B $xor$ls180.v:5007$871_Y
- connect \Y $xor$ls180.v:5007$872_Y
+ connect \B $xor$ls180.v:5003$871_Y
+ connect \Y $xor$ls180.v:5003$872_Y
end
- attribute \src "ls180.v:5007.234-5007.318"
- cell $xor $xor$ls180.v:5007$873
+ attribute \src "ls180.v:5003.234-5003.318"
+ cell $xor $xor$ls180.v:5003$873
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_inserter_crc2_val [0]
connect \B \main_sdcore_crc16_inserter_crc2_crcreg1 [15]
- connect \Y $xor$ls180.v:5007$873_Y
+ connect \Y $xor$ls180.v:5003$873_Y
end
- attribute \src "ls180.v:5007.187-5007.319"
- cell $xor $xor$ls180.v:5007$874
+ attribute \src "ls180.v:5003.187-5003.319"
+ cell $xor $xor$ls180.v:5003$874
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_inserter_crc2_crcreg1 [11]
- connect \B $xor$ls180.v:5007$873_Y
- connect \Y $xor$ls180.v:5007$874_Y
+ connect \B $xor$ls180.v:5003$873_Y
+ connect \Y $xor$ls180.v:5003$874_Y
end
- attribute \src "ls180.v:5016.899-5016.983"
- cell $xor $xor$ls180.v:5016$876
+ attribute \src "ls180.v:5012.899-5012.983"
+ cell $xor $xor$ls180.v:5012$876
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_inserter_crc3_val [1]
connect \B \main_sdcore_crc16_inserter_crc3_crcreg0 [15]
- connect \Y $xor$ls180.v:5016$876_Y
+ connect \Y $xor$ls180.v:5012$876_Y
end
- attribute \src "ls180.v:5016.634-5016.718"
- cell $xor $xor$ls180.v:5016$877
+ attribute \src "ls180.v:5012.634-5012.718"
+ cell $xor $xor$ls180.v:5012$877
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_inserter_crc3_val [1]
connect \B \main_sdcore_crc16_inserter_crc3_crcreg0 [15]
- connect \Y $xor$ls180.v:5016$877_Y
+ connect \Y $xor$ls180.v:5012$877_Y
end
- attribute \src "ls180.v:5016.588-5016.719"
- cell $xor $xor$ls180.v:5016$878
+ attribute \src "ls180.v:5012.588-5012.719"
+ cell $xor $xor$ls180.v:5012$878
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_inserter_crc3_crcreg0 [4]
- connect \B $xor$ls180.v:5016$877_Y
- connect \Y $xor$ls180.v:5016$878_Y
+ connect \B $xor$ls180.v:5012$877_Y
+ connect \Y $xor$ls180.v:5012$878_Y
end
- attribute \src "ls180.v:5016.234-5016.318"
- cell $xor $xor$ls180.v:5016$879
+ attribute \src "ls180.v:5012.234-5012.318"
+ cell $xor $xor$ls180.v:5012$879
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_inserter_crc3_val [1]
connect \B \main_sdcore_crc16_inserter_crc3_crcreg0 [15]
- connect \Y $xor$ls180.v:5016$879_Y
+ connect \Y $xor$ls180.v:5012$879_Y
end
- attribute \src "ls180.v:5016.187-5016.319"
- cell $xor $xor$ls180.v:5016$880
+ attribute \src "ls180.v:5012.187-5012.319"
+ cell $xor $xor$ls180.v:5012$880
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_inserter_crc3_crcreg0 [11]
- connect \B $xor$ls180.v:5016$879_Y
- connect \Y $xor$ls180.v:5016$880_Y
+ connect \B $xor$ls180.v:5012$879_Y
+ connect \Y $xor$ls180.v:5012$880_Y
end
- attribute \src "ls180.v:5017.899-5017.983"
- cell $xor $xor$ls180.v:5017$881
+ attribute \src "ls180.v:5013.899-5013.983"
+ cell $xor $xor$ls180.v:5013$881
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_inserter_crc3_val [0]
connect \B \main_sdcore_crc16_inserter_crc3_crcreg1 [15]
- connect \Y $xor$ls180.v:5017$881_Y
+ connect \Y $xor$ls180.v:5013$881_Y
end
- attribute \src "ls180.v:5017.634-5017.718"
- cell $xor $xor$ls180.v:5017$882
+ attribute \src "ls180.v:5013.634-5013.718"
+ cell $xor $xor$ls180.v:5013$882
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_inserter_crc3_val [0]
connect \B \main_sdcore_crc16_inserter_crc3_crcreg1 [15]
- connect \Y $xor$ls180.v:5017$882_Y
+ connect \Y $xor$ls180.v:5013$882_Y
end
- attribute \src "ls180.v:5017.588-5017.719"
- cell $xor $xor$ls180.v:5017$883
+ attribute \src "ls180.v:5013.588-5013.719"
+ cell $xor $xor$ls180.v:5013$883
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_inserter_crc3_crcreg1 [4]
- connect \B $xor$ls180.v:5017$882_Y
- connect \Y $xor$ls180.v:5017$883_Y
+ connect \B $xor$ls180.v:5013$882_Y
+ connect \Y $xor$ls180.v:5013$883_Y
end
- attribute \src "ls180.v:5017.234-5017.318"
- cell $xor $xor$ls180.v:5017$884
+ attribute \src "ls180.v:5013.234-5013.318"
+ cell $xor $xor$ls180.v:5013$884
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_inserter_crc3_val [0]
connect \B \main_sdcore_crc16_inserter_crc3_crcreg1 [15]
- connect \Y $xor$ls180.v:5017$884_Y
+ connect \Y $xor$ls180.v:5013$884_Y
end
- attribute \src "ls180.v:5017.187-5017.319"
- cell $xor $xor$ls180.v:5017$885
+ attribute \src "ls180.v:5013.187-5013.319"
+ cell $xor $xor$ls180.v:5013$885
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_inserter_crc3_crcreg1 [11]
- connect \B $xor$ls180.v:5017$884_Y
- connect \Y $xor$ls180.v:5017$885_Y
+ connect \B $xor$ls180.v:5013$884_Y
+ connect \Y $xor$ls180.v:5013$885_Y
end
- attribute \src "ls180.v:5168.879-5168.961"
- cell $xor $xor$ls180.v:5168$918
+ attribute \src "ls180.v:5164.879-5164.961"
+ cell $xor $xor$ls180.v:5164$918
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_checker_crc0_val [1]
connect \B \main_sdcore_crc16_checker_crc0_crcreg0 [15]
- connect \Y $xor$ls180.v:5168$918_Y
+ connect \Y $xor$ls180.v:5164$918_Y
end
- attribute \src "ls180.v:5168.620-5168.702"
- cell $xor $xor$ls180.v:5168$919
+ attribute \src "ls180.v:5164.620-5164.702"
+ cell $xor $xor$ls180.v:5164$919
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_checker_crc0_val [1]
connect \B \main_sdcore_crc16_checker_crc0_crcreg0 [15]
- connect \Y $xor$ls180.v:5168$919_Y
+ connect \Y $xor$ls180.v:5164$919_Y
end
- attribute \src "ls180.v:5168.575-5168.703"
- cell $xor $xor$ls180.v:5168$920
+ attribute \src "ls180.v:5164.575-5164.703"
+ cell $xor $xor$ls180.v:5164$920
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_checker_crc0_crcreg0 [4]
- connect \B $xor$ls180.v:5168$919_Y
- connect \Y $xor$ls180.v:5168$920_Y
+ connect \B $xor$ls180.v:5164$919_Y
+ connect \Y $xor$ls180.v:5164$920_Y
end
- attribute \src "ls180.v:5168.229-5168.311"
- cell $xor $xor$ls180.v:5168$921
+ attribute \src "ls180.v:5164.229-5164.311"
+ cell $xor $xor$ls180.v:5164$921
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_checker_crc0_val [1]
connect \B \main_sdcore_crc16_checker_crc0_crcreg0 [15]
- connect \Y $xor$ls180.v:5168$921_Y
+ connect \Y $xor$ls180.v:5164$921_Y
end
- attribute \src "ls180.v:5168.183-5168.312"
- cell $xor $xor$ls180.v:5168$922
+ attribute \src "ls180.v:5164.183-5164.312"
+ cell $xor $xor$ls180.v:5164$922
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_checker_crc0_crcreg0 [11]
- connect \B $xor$ls180.v:5168$921_Y
- connect \Y $xor$ls180.v:5168$922_Y
+ connect \B $xor$ls180.v:5164$921_Y
+ connect \Y $xor$ls180.v:5164$922_Y
end
- attribute \src "ls180.v:5169.879-5169.961"
- cell $xor $xor$ls180.v:5169$923
+ attribute \src "ls180.v:5165.879-5165.961"
+ cell $xor $xor$ls180.v:5165$923
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_checker_crc0_val [0]
connect \B \main_sdcore_crc16_checker_crc0_crcreg1 [15]
- connect \Y $xor$ls180.v:5169$923_Y
+ connect \Y $xor$ls180.v:5165$923_Y
end
- attribute \src "ls180.v:5169.620-5169.702"
- cell $xor $xor$ls180.v:5169$924
+ attribute \src "ls180.v:5165.620-5165.702"
+ cell $xor $xor$ls180.v:5165$924
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_checker_crc0_val [0]
connect \B \main_sdcore_crc16_checker_crc0_crcreg1 [15]
- connect \Y $xor$ls180.v:5169$924_Y
+ connect \Y $xor$ls180.v:5165$924_Y
end
- attribute \src "ls180.v:5169.575-5169.703"
- cell $xor $xor$ls180.v:5169$925
+ attribute \src "ls180.v:5165.575-5165.703"
+ cell $xor $xor$ls180.v:5165$925
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_checker_crc0_crcreg1 [4]
- connect \B $xor$ls180.v:5169$924_Y
- connect \Y $xor$ls180.v:5169$925_Y
+ connect \B $xor$ls180.v:5165$924_Y
+ connect \Y $xor$ls180.v:5165$925_Y
end
- attribute \src "ls180.v:5169.229-5169.311"
- cell $xor $xor$ls180.v:5169$926
+ attribute \src "ls180.v:5165.229-5165.311"
+ cell $xor $xor$ls180.v:5165$926
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_checker_crc0_val [0]
connect \B \main_sdcore_crc16_checker_crc0_crcreg1 [15]
- connect \Y $xor$ls180.v:5169$926_Y
+ connect \Y $xor$ls180.v:5165$926_Y
end
- attribute \src "ls180.v:5169.183-5169.312"
- cell $xor $xor$ls180.v:5169$927
+ attribute \src "ls180.v:5165.183-5165.312"
+ cell $xor $xor$ls180.v:5165$927
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_checker_crc0_crcreg1 [11]
- connect \B $xor$ls180.v:5169$926_Y
- connect \Y $xor$ls180.v:5169$927_Y
+ connect \B $xor$ls180.v:5165$926_Y
+ connect \Y $xor$ls180.v:5165$927_Y
end
- attribute \src "ls180.v:5178.879-5178.961"
- cell $xor $xor$ls180.v:5178$929
+ attribute \src "ls180.v:5174.879-5174.961"
+ cell $xor $xor$ls180.v:5174$929
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_checker_crc1_val [1]
connect \B \main_sdcore_crc16_checker_crc1_crcreg0 [15]
- connect \Y $xor$ls180.v:5178$929_Y
+ connect \Y $xor$ls180.v:5174$929_Y
end
- attribute \src "ls180.v:5178.620-5178.702"
- cell $xor $xor$ls180.v:5178$930
+ attribute \src "ls180.v:5174.620-5174.702"
+ cell $xor $xor$ls180.v:5174$930
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_checker_crc1_val [1]
connect \B \main_sdcore_crc16_checker_crc1_crcreg0 [15]
- connect \Y $xor$ls180.v:5178$930_Y
+ connect \Y $xor$ls180.v:5174$930_Y
end
- attribute \src "ls180.v:5178.575-5178.703"
- cell $xor $xor$ls180.v:5178$931
+ attribute \src "ls180.v:5174.575-5174.703"
+ cell $xor $xor$ls180.v:5174$931
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_checker_crc1_crcreg0 [4]
- connect \B $xor$ls180.v:5178$930_Y
- connect \Y $xor$ls180.v:5178$931_Y
+ connect \B $xor$ls180.v:5174$930_Y
+ connect \Y $xor$ls180.v:5174$931_Y
end
- attribute \src "ls180.v:5178.229-5178.311"
- cell $xor $xor$ls180.v:5178$932
+ attribute \src "ls180.v:5174.229-5174.311"
+ cell $xor $xor$ls180.v:5174$932
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_checker_crc1_val [1]
connect \B \main_sdcore_crc16_checker_crc1_crcreg0 [15]
- connect \Y $xor$ls180.v:5178$932_Y
+ connect \Y $xor$ls180.v:5174$932_Y
end
- attribute \src "ls180.v:5178.183-5178.312"
- cell $xor $xor$ls180.v:5178$933
+ attribute \src "ls180.v:5174.183-5174.312"
+ cell $xor $xor$ls180.v:5174$933
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_checker_crc1_crcreg0 [11]
- connect \B $xor$ls180.v:5178$932_Y
- connect \Y $xor$ls180.v:5178$933_Y
+ connect \B $xor$ls180.v:5174$932_Y
+ connect \Y $xor$ls180.v:5174$933_Y
end
- attribute \src "ls180.v:5179.879-5179.961"
- cell $xor $xor$ls180.v:5179$934
+ attribute \src "ls180.v:5175.879-5175.961"
+ cell $xor $xor$ls180.v:5175$934
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_checker_crc1_val [0]
connect \B \main_sdcore_crc16_checker_crc1_crcreg1 [15]
- connect \Y $xor$ls180.v:5179$934_Y
+ connect \Y $xor$ls180.v:5175$934_Y
end
- attribute \src "ls180.v:5179.620-5179.702"
- cell $xor $xor$ls180.v:5179$935
+ attribute \src "ls180.v:5175.620-5175.702"
+ cell $xor $xor$ls180.v:5175$935
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_checker_crc1_val [0]
connect \B \main_sdcore_crc16_checker_crc1_crcreg1 [15]
- connect \Y $xor$ls180.v:5179$935_Y
+ connect \Y $xor$ls180.v:5175$935_Y
end
- attribute \src "ls180.v:5179.575-5179.703"
- cell $xor $xor$ls180.v:5179$936
+ attribute \src "ls180.v:5175.575-5175.703"
+ cell $xor $xor$ls180.v:5175$936
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_checker_crc1_crcreg1 [4]
- connect \B $xor$ls180.v:5179$935_Y
- connect \Y $xor$ls180.v:5179$936_Y
+ connect \B $xor$ls180.v:5175$935_Y
+ connect \Y $xor$ls180.v:5175$936_Y
end
- attribute \src "ls180.v:5179.229-5179.311"
- cell $xor $xor$ls180.v:5179$937
+ attribute \src "ls180.v:5175.229-5175.311"
+ cell $xor $xor$ls180.v:5175$937
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_checker_crc1_val [0]
connect \B \main_sdcore_crc16_checker_crc1_crcreg1 [15]
- connect \Y $xor$ls180.v:5179$937_Y
+ connect \Y $xor$ls180.v:5175$937_Y
end
- attribute \src "ls180.v:5179.183-5179.312"
- cell $xor $xor$ls180.v:5179$938
+ attribute \src "ls180.v:5175.183-5175.312"
+ cell $xor $xor$ls180.v:5175$938
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_checker_crc1_crcreg1 [11]
- connect \B $xor$ls180.v:5179$937_Y
- connect \Y $xor$ls180.v:5179$938_Y
+ connect \B $xor$ls180.v:5175$937_Y
+ connect \Y $xor$ls180.v:5175$938_Y
end
- attribute \src "ls180.v:5188.879-5188.961"
- cell $xor $xor$ls180.v:5188$940
+ attribute \src "ls180.v:5184.879-5184.961"
+ cell $xor $xor$ls180.v:5184$940
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_checker_crc2_val [1]
connect \B \main_sdcore_crc16_checker_crc2_crcreg0 [15]
- connect \Y $xor$ls180.v:5188$940_Y
+ connect \Y $xor$ls180.v:5184$940_Y
end
- attribute \src "ls180.v:5188.620-5188.702"
- cell $xor $xor$ls180.v:5188$941
+ attribute \src "ls180.v:5184.620-5184.702"
+ cell $xor $xor$ls180.v:5184$941
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_checker_crc2_val [1]
connect \B \main_sdcore_crc16_checker_crc2_crcreg0 [15]
- connect \Y $xor$ls180.v:5188$941_Y
+ connect \Y $xor$ls180.v:5184$941_Y
end
- attribute \src "ls180.v:5188.575-5188.703"
- cell $xor $xor$ls180.v:5188$942
+ attribute \src "ls180.v:5184.575-5184.703"
+ cell $xor $xor$ls180.v:5184$942
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_checker_crc2_crcreg0 [4]
- connect \B $xor$ls180.v:5188$941_Y
- connect \Y $xor$ls180.v:5188$942_Y
+ connect \B $xor$ls180.v:5184$941_Y
+ connect \Y $xor$ls180.v:5184$942_Y
end
- attribute \src "ls180.v:5188.229-5188.311"
- cell $xor $xor$ls180.v:5188$943
+ attribute \src "ls180.v:5184.229-5184.311"
+ cell $xor $xor$ls180.v:5184$943
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_checker_crc2_val [1]
connect \B \main_sdcore_crc16_checker_crc2_crcreg0 [15]
- connect \Y $xor$ls180.v:5188$943_Y
+ connect \Y $xor$ls180.v:5184$943_Y
end
- attribute \src "ls180.v:5188.183-5188.312"
- cell $xor $xor$ls180.v:5188$944
+ attribute \src "ls180.v:5184.183-5184.312"
+ cell $xor $xor$ls180.v:5184$944
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_checker_crc2_crcreg0 [11]
- connect \B $xor$ls180.v:5188$943_Y
- connect \Y $xor$ls180.v:5188$944_Y
+ connect \B $xor$ls180.v:5184$943_Y
+ connect \Y $xor$ls180.v:5184$944_Y
end
- attribute \src "ls180.v:5189.879-5189.961"
- cell $xor $xor$ls180.v:5189$945
+ attribute \src "ls180.v:5185.879-5185.961"
+ cell $xor $xor$ls180.v:5185$945
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_checker_crc2_val [0]
connect \B \main_sdcore_crc16_checker_crc2_crcreg1 [15]
- connect \Y $xor$ls180.v:5189$945_Y
+ connect \Y $xor$ls180.v:5185$945_Y
end
- attribute \src "ls180.v:5189.620-5189.702"
- cell $xor $xor$ls180.v:5189$946
+ attribute \src "ls180.v:5185.620-5185.702"
+ cell $xor $xor$ls180.v:5185$946
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_checker_crc2_val [0]
connect \B \main_sdcore_crc16_checker_crc2_crcreg1 [15]
- connect \Y $xor$ls180.v:5189$946_Y
+ connect \Y $xor$ls180.v:5185$946_Y
end
- attribute \src "ls180.v:5189.575-5189.703"
- cell $xor $xor$ls180.v:5189$947
+ attribute \src "ls180.v:5185.575-5185.703"
+ cell $xor $xor$ls180.v:5185$947
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_checker_crc2_crcreg1 [4]
- connect \B $xor$ls180.v:5189$946_Y
- connect \Y $xor$ls180.v:5189$947_Y
+ connect \B $xor$ls180.v:5185$946_Y
+ connect \Y $xor$ls180.v:5185$947_Y
end
- attribute \src "ls180.v:5189.229-5189.311"
- cell $xor $xor$ls180.v:5189$948
+ attribute \src "ls180.v:5185.229-5185.311"
+ cell $xor $xor$ls180.v:5185$948
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_checker_crc2_val [0]
connect \B \main_sdcore_crc16_checker_crc2_crcreg1 [15]
- connect \Y $xor$ls180.v:5189$948_Y
+ connect \Y $xor$ls180.v:5185$948_Y
end
- attribute \src "ls180.v:5189.183-5189.312"
- cell $xor $xor$ls180.v:5189$949
+ attribute \src "ls180.v:5185.183-5185.312"
+ cell $xor $xor$ls180.v:5185$949
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_checker_crc2_crcreg1 [11]
- connect \B $xor$ls180.v:5189$948_Y
- connect \Y $xor$ls180.v:5189$949_Y
+ connect \B $xor$ls180.v:5185$948_Y
+ connect \Y $xor$ls180.v:5185$949_Y
end
- attribute \src "ls180.v:5198.879-5198.961"
- cell $xor $xor$ls180.v:5198$951
+ attribute \src "ls180.v:5194.879-5194.961"
+ cell $xor $xor$ls180.v:5194$951
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_checker_crc3_val [1]
connect \B \main_sdcore_crc16_checker_crc3_crcreg0 [15]
- connect \Y $xor$ls180.v:5198$951_Y
+ connect \Y $xor$ls180.v:5194$951_Y
end
- attribute \src "ls180.v:5198.620-5198.702"
- cell $xor $xor$ls180.v:5198$952
+ attribute \src "ls180.v:5194.620-5194.702"
+ cell $xor $xor$ls180.v:5194$952
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_checker_crc3_val [1]
connect \B \main_sdcore_crc16_checker_crc3_crcreg0 [15]
- connect \Y $xor$ls180.v:5198$952_Y
+ connect \Y $xor$ls180.v:5194$952_Y
end
- attribute \src "ls180.v:5198.575-5198.703"
- cell $xor $xor$ls180.v:5198$953
+ attribute \src "ls180.v:5194.575-5194.703"
+ cell $xor $xor$ls180.v:5194$953
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_checker_crc3_crcreg0 [4]
- connect \B $xor$ls180.v:5198$952_Y
- connect \Y $xor$ls180.v:5198$953_Y
+ connect \B $xor$ls180.v:5194$952_Y
+ connect \Y $xor$ls180.v:5194$953_Y
end
- attribute \src "ls180.v:5198.229-5198.311"
- cell $xor $xor$ls180.v:5198$954
+ attribute \src "ls180.v:5194.229-5194.311"
+ cell $xor $xor$ls180.v:5194$954
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_checker_crc3_val [1]
connect \B \main_sdcore_crc16_checker_crc3_crcreg0 [15]
- connect \Y $xor$ls180.v:5198$954_Y
+ connect \Y $xor$ls180.v:5194$954_Y
end
- attribute \src "ls180.v:5198.183-5198.312"
- cell $xor $xor$ls180.v:5198$955
+ attribute \src "ls180.v:5194.183-5194.312"
+ cell $xor $xor$ls180.v:5194$955
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_checker_crc3_crcreg0 [11]
- connect \B $xor$ls180.v:5198$954_Y
- connect \Y $xor$ls180.v:5198$955_Y
+ connect \B $xor$ls180.v:5194$954_Y
+ connect \Y $xor$ls180.v:5194$955_Y
end
- attribute \src "ls180.v:5199.879-5199.961"
- cell $xor $xor$ls180.v:5199$956
+ attribute \src "ls180.v:5195.879-5195.961"
+ cell $xor $xor$ls180.v:5195$956
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_checker_crc3_val [0]
connect \B \main_sdcore_crc16_checker_crc3_crcreg1 [15]
- connect \Y $xor$ls180.v:5199$956_Y
+ connect \Y $xor$ls180.v:5195$956_Y
end
- attribute \src "ls180.v:5199.620-5199.702"
- cell $xor $xor$ls180.v:5199$957
+ attribute \src "ls180.v:5195.620-5195.702"
+ cell $xor $xor$ls180.v:5195$957
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_checker_crc3_val [0]
connect \B \main_sdcore_crc16_checker_crc3_crcreg1 [15]
- connect \Y $xor$ls180.v:5199$957_Y
+ connect \Y $xor$ls180.v:5195$957_Y
end
- attribute \src "ls180.v:5199.575-5199.703"
- cell $xor $xor$ls180.v:5199$958
+ attribute \src "ls180.v:5195.575-5195.703"
+ cell $xor $xor$ls180.v:5195$958
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_checker_crc3_crcreg1 [4]
- connect \B $xor$ls180.v:5199$957_Y
- connect \Y $xor$ls180.v:5199$958_Y
+ connect \B $xor$ls180.v:5195$957_Y
+ connect \Y $xor$ls180.v:5195$958_Y
end
- attribute \src "ls180.v:5199.229-5199.311"
- cell $xor $xor$ls180.v:5199$959
+ attribute \src "ls180.v:5195.229-5195.311"
+ cell $xor $xor$ls180.v:5195$959
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_checker_crc3_val [0]
connect \B \main_sdcore_crc16_checker_crc3_crcreg1 [15]
- connect \Y $xor$ls180.v:5199$959_Y
+ connect \Y $xor$ls180.v:5195$959_Y
end
- attribute \src "ls180.v:5199.183-5199.312"
- cell $xor $xor$ls180.v:5199$960
+ attribute \src "ls180.v:5195.183-5195.312"
+ cell $xor $xor$ls180.v:5195$960
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_checker_crc3_crcreg1 [11]
- connect \B $xor$ls180.v:5199$959_Y
- connect \Y $xor$ls180.v:5199$960_Y
+ connect \B $xor$ls180.v:5195$959_Y
+ connect \Y $xor$ls180.v:5195$960_Y
end
attribute \module_not_derived 1
- attribute \src "ls180.v:10183.13-10561.2"
+ attribute \src "ls180.v:10179.13-10553.2"
cell \test_issuer \test_issuer
connect \TAP_bus__tck \main_libresocsim_libresoc_jtag_tck
connect \TAP_bus__tdi \main_libresocsim_libresoc_jtag_tdi
connect \core_bigendian_i 1'0
connect \dbus__ack \main_libresocsim_libresoc_dbus_ack
connect \dbus__adr \main_libresocsim_libresoc_dbus_adr
- connect \dbus__bte \main_libresocsim_libresoc_dbus_bte
- connect \dbus__cti \main_libresocsim_libresoc_dbus_cti
+ connect \dbus__bte 1'0
+ connect \dbus__cti 1'0
connect \dbus__cyc \main_libresocsim_libresoc_dbus_cyc
connect \dbus__dat_r \main_libresocsim_libresoc_dbus_dat_r
connect \dbus__dat_w \main_libresocsim_libresoc_dbus_dat_w
connect \gpio_s7__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [7]
connect \ibus__ack \main_libresocsim_libresoc_ibus_ack
connect \ibus__adr \main_libresocsim_libresoc_ibus_adr
- connect \ibus__bte \main_libresocsim_libresoc_ibus_bte
- connect \ibus__cti \main_libresocsim_libresoc_ibus_cti
+ connect \ibus__bte 1'0
+ connect \ibus__cti 1'0
connect \ibus__cyc \main_libresocsim_libresoc_ibus_cyc
connect \ibus__dat_r \main_libresocsim_libresoc_ibus_dat_r
connect \ibus__dat_w \main_libresocsim_libresoc_ibus_dat_w
connect \ibus__we \main_libresocsim_libresoc_ibus_we
connect \icp_wb__ack \main_libresocsim_libresoc_xics_icp_ack
connect \icp_wb__adr \main_libresocsim_libresoc_xics_icp_adr
- connect \icp_wb__bte \main_libresocsim_libresoc_xics_icp_bte
- connect \icp_wb__cti \main_libresocsim_libresoc_xics_icp_cti
connect \icp_wb__cyc \main_libresocsim_libresoc_xics_icp_cyc
connect \icp_wb__dat_r \main_libresocsim_libresoc_xics_icp_dat_r
connect \icp_wb__dat_w \main_libresocsim_libresoc_xics_icp_dat_w
connect \icp_wb__we \main_libresocsim_libresoc_xics_icp_we
connect \ics_wb__ack \main_libresocsim_libresoc_xics_ics_ack
connect \ics_wb__adr \main_libresocsim_libresoc_xics_ics_adr
- connect \ics_wb__bte \main_libresocsim_libresoc_xics_ics_bte
- connect \ics_wb__cti \main_libresocsim_libresoc_xics_ics_cti
connect \ics_wb__cyc \main_libresocsim_libresoc_xics_ics_cyc
connect \ics_wb__dat_r \main_libresocsim_libresoc_xics_ics_dat_r
connect \ics_wb__dat_w \main_libresocsim_libresoc_xics_ics_dat_w
connect \pwm_0__pad__o \pwm_1 [0]
connect \pwm_1__core__o \pwm [1]
connect \pwm_1__pad__o \pwm_1 [1]
- connect \rst $or$ls180.v:10283$2750_Y
+ connect \rst $or$ls180.v:10279$2750_Y
connect \sd0_clk__core__o \sdcard_clk
connect \sd0_clk__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdcard_clk
connect \sd0_cmd__core__i \sdcard_cmd_i
sync always
sync init
end
- attribute \src "ls180.v:1000.12-1000.47"
- process $proc$ls180.v:1000$3127
+ attribute \src "ls180.v:1000.5-1000.31"
+ process $proc$ls180.v:1000$3130
assign { } { }
- assign $0\main_spimaster8_clk_divider[15:0] 16'0000000000000111
- sync always
- update \main_spimaster8_clk_divider $0\main_spimaster8_clk_divider[15:0]
- sync init
- end
- attribute \src "ls180.v:1001.5-1001.33"
- process $proc$ls180.v:1001$3128
- assign { } { }
- assign $1\main_spimaster9_start[0:0] 1'0
- sync always
- sync init
- update \main_spimaster9_start $1\main_spimaster9_start[0:0]
- end
- attribute \src "ls180.v:1003.12-1003.44"
- process $proc$ls180.v:1003$3129
- assign { } { }
- assign $1\main_spimaster11_storage[15:0] 16'0000000000000000
+ assign $1\main_spimaster12_re[0:0] 1'0
sync always
sync init
- update \main_spimaster11_storage $1\main_spimaster11_storage[15:0]
+ update \main_spimaster12_re $1\main_spimaster12_re[0:0]
end
- attribute \src "ls180.v:1004.5-1004.31"
- process $proc$ls180.v:1004$3130
+ attribute \src "ls180.v:1004.11-1004.42"
+ process $proc$ls180.v:1004$3131
assign { } { }
- assign $1\main_spimaster12_re[0:0] 1'0
+ assign $1\main_spimaster16_storage[7:0] 8'00000000
sync always
sync init
- update \main_spimaster12_re $1\main_spimaster12_re[0:0]
+ update \main_spimaster16_storage $1\main_spimaster16_storage[7:0]
end
- attribute \src "ls180.v:10047.1-10057.4"
- process $proc$ls180.v:10047$2680
+ attribute \src "ls180.v:10043.1-10053.4"
+ process $proc$ls180.v:10043$2680
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0$memwr$\mem$ls180.v:10055$4_ADDR[6:0]$2690 7'xxxxxxx
- assign $0$memwr$\mem$ls180.v:10055$4_DATA[31:0]$2691 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
- assign $0$memwr$\mem$ls180.v:10055$4_EN[31:0]$2692 0
- assign $0$memwr$\mem$ls180.v:10053$3_ADDR[6:0]$2687 7'xxxxxxx
- assign $0$memwr$\mem$ls180.v:10053$3_DATA[31:0]$2688 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
- assign $0$memwr$\mem$ls180.v:10053$3_EN[31:0]$2689 0
- assign $0$memwr$\mem$ls180.v:10051$2_ADDR[6:0]$2684 7'xxxxxxx
- assign $0$memwr$\mem$ls180.v:10051$2_DATA[31:0]$2685 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
- assign $0$memwr$\mem$ls180.v:10051$2_EN[31:0]$2686 0
- assign $0$memwr$\mem$ls180.v:10049$1_ADDR[6:0]$2681 7'xxxxxxx
- assign $0$memwr$\mem$ls180.v:10049$1_DATA[31:0]$2682 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
- assign $0$memwr$\mem$ls180.v:10049$1_EN[31:0]$2683 0
+ assign $0$memwr$\mem$ls180.v:10051$4_ADDR[6:0]$2690 7'xxxxxxx
+ assign $0$memwr$\mem$ls180.v:10051$4_DATA[31:0]$2691 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ assign $0$memwr$\mem$ls180.v:10051$4_EN[31:0]$2692 0
+ assign $0$memwr$\mem$ls180.v:10049$3_ADDR[6:0]$2687 7'xxxxxxx
+ assign $0$memwr$\mem$ls180.v:10049$3_DATA[31:0]$2688 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ assign $0$memwr$\mem$ls180.v:10049$3_EN[31:0]$2689 0
+ assign $0$memwr$\mem$ls180.v:10047$2_ADDR[6:0]$2684 7'xxxxxxx
+ assign $0$memwr$\mem$ls180.v:10047$2_DATA[31:0]$2685 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ assign $0$memwr$\mem$ls180.v:10047$2_EN[31:0]$2686 0
+ assign $0$memwr$\mem$ls180.v:10045$1_ADDR[6:0]$2681 7'xxxxxxx
+ assign $0$memwr$\mem$ls180.v:10045$1_DATA[31:0]$2682 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ assign $0$memwr$\mem$ls180.v:10045$1_EN[31:0]$2683 0
assign $0\memadr[6:0] \main_libresocsim_adr
- attribute \src "ls180.v:10048.2-10049.65"
+ attribute \src "ls180.v:10044.2-10045.65"
switch \main_libresocsim_we [0]
- attribute \src "ls180.v:10048.6-10048.28"
+ attribute \src "ls180.v:10044.6-10044.28"
case 1'1
- assign $0$memwr$\mem$ls180.v:10049$1_ADDR[6:0]$2681 \main_libresocsim_adr
- assign $0$memwr$\mem$ls180.v:10049$1_DATA[31:0]$2682 { 24'000000000000000000000000 \main_libresocsim_dat_w [7:0] }
- assign $0$memwr$\mem$ls180.v:10049$1_EN[31:0]$2683 255
+ assign $0$memwr$\mem$ls180.v:10045$1_ADDR[6:0]$2681 \main_libresocsim_adr
+ assign $0$memwr$\mem$ls180.v:10045$1_DATA[31:0]$2682 { 24'000000000000000000000000 \main_libresocsim_dat_w [7:0] }
+ assign $0$memwr$\mem$ls180.v:10045$1_EN[31:0]$2683 255
case
end
- attribute \src "ls180.v:10050.2-10051.67"
+ attribute \src "ls180.v:10046.2-10047.67"
switch \main_libresocsim_we [1]
- attribute \src "ls180.v:10050.6-10050.28"
+ attribute \src "ls180.v:10046.6-10046.28"
case 1'1
- assign $0$memwr$\mem$ls180.v:10051$2_ADDR[6:0]$2684 \main_libresocsim_adr
- assign $0$memwr$\mem$ls180.v:10051$2_DATA[31:0]$2685 { 16'0000000000000000 \main_libresocsim_dat_w [15:8] 8'xxxxxxxx }
- assign $0$memwr$\mem$ls180.v:10051$2_EN[31:0]$2686 65280
+ assign $0$memwr$\mem$ls180.v:10047$2_ADDR[6:0]$2684 \main_libresocsim_adr
+ assign $0$memwr$\mem$ls180.v:10047$2_DATA[31:0]$2685 { 16'0000000000000000 \main_libresocsim_dat_w [15:8] 8'xxxxxxxx }
+ assign $0$memwr$\mem$ls180.v:10047$2_EN[31:0]$2686 65280
case
end
- attribute \src "ls180.v:10052.2-10053.69"
+ attribute \src "ls180.v:10048.2-10049.69"
switch \main_libresocsim_we [2]
- attribute \src "ls180.v:10052.6-10052.28"
+ attribute \src "ls180.v:10048.6-10048.28"
case 1'1
- assign $0$memwr$\mem$ls180.v:10053$3_ADDR[6:0]$2687 \main_libresocsim_adr
- assign $0$memwr$\mem$ls180.v:10053$3_DATA[31:0]$2688 { 8'00000000 \main_libresocsim_dat_w [23:16] 16'xxxxxxxxxxxxxxxx }
- assign $0$memwr$\mem$ls180.v:10053$3_EN[31:0]$2689 16711680
+ assign $0$memwr$\mem$ls180.v:10049$3_ADDR[6:0]$2687 \main_libresocsim_adr
+ assign $0$memwr$\mem$ls180.v:10049$3_DATA[31:0]$2688 { 8'00000000 \main_libresocsim_dat_w [23:16] 16'xxxxxxxxxxxxxxxx }
+ assign $0$memwr$\mem$ls180.v:10049$3_EN[31:0]$2689 16711680
case
end
- attribute \src "ls180.v:10054.2-10055.69"
+ attribute \src "ls180.v:10050.2-10051.69"
switch \main_libresocsim_we [3]
- attribute \src "ls180.v:10054.6-10054.28"
+ attribute \src "ls180.v:10050.6-10050.28"
case 1'1
- assign $0$memwr$\mem$ls180.v:10055$4_ADDR[6:0]$2690 \main_libresocsim_adr
- assign $0$memwr$\mem$ls180.v:10055$4_DATA[31:0]$2691 { \main_libresocsim_dat_w [31:24] 24'xxxxxxxxxxxxxxxxxxxxxxxx }
- assign $0$memwr$\mem$ls180.v:10055$4_EN[31:0]$2692 32'11111111000000000000000000000000
+ assign $0$memwr$\mem$ls180.v:10051$4_ADDR[6:0]$2690 \main_libresocsim_adr
+ assign $0$memwr$\mem$ls180.v:10051$4_DATA[31:0]$2691 { \main_libresocsim_dat_w [31:24] 24'xxxxxxxxxxxxxxxxxxxxxxxx }
+ assign $0$memwr$\mem$ls180.v:10051$4_EN[31:0]$2692 32'11111111000000000000000000000000
case
end
sync posedge \sys_clk_1
update \memadr $0\memadr[6:0]
- update $memwr$\mem$ls180.v:10049$1_ADDR $0$memwr$\mem$ls180.v:10049$1_ADDR[6:0]$2681
- update $memwr$\mem$ls180.v:10049$1_DATA $0$memwr$\mem$ls180.v:10049$1_DATA[31:0]$2682
- update $memwr$\mem$ls180.v:10049$1_EN $0$memwr$\mem$ls180.v:10049$1_EN[31:0]$2683
- update $memwr$\mem$ls180.v:10051$2_ADDR $0$memwr$\mem$ls180.v:10051$2_ADDR[6:0]$2684
- update $memwr$\mem$ls180.v:10051$2_DATA $0$memwr$\mem$ls180.v:10051$2_DATA[31:0]$2685
- update $memwr$\mem$ls180.v:10051$2_EN $0$memwr$\mem$ls180.v:10051$2_EN[31:0]$2686
- update $memwr$\mem$ls180.v:10053$3_ADDR $0$memwr$\mem$ls180.v:10053$3_ADDR[6:0]$2687
- update $memwr$\mem$ls180.v:10053$3_DATA $0$memwr$\mem$ls180.v:10053$3_DATA[31:0]$2688
- update $memwr$\mem$ls180.v:10053$3_EN $0$memwr$\mem$ls180.v:10053$3_EN[31:0]$2689
- update $memwr$\mem$ls180.v:10055$4_ADDR $0$memwr$\mem$ls180.v:10055$4_ADDR[6:0]$2690
- update $memwr$\mem$ls180.v:10055$4_DATA $0$memwr$\mem$ls180.v:10055$4_DATA[31:0]$2691
- update $memwr$\mem$ls180.v:10055$4_EN $0$memwr$\mem$ls180.v:10055$4_EN[31:0]$2692
- end
- attribute \src "ls180.v:10067.1-10071.4"
- process $proc$ls180.v:10067$2694
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign $0$memwr$\storage$ls180.v:10069$5_ADDR[2:0]$2695 3'xxx
- assign $0$memwr$\storage$ls180.v:10069$5_DATA[24:0]$2696 25'xxxxxxxxxxxxxxxxxxxxxxxxx
- assign $0$memwr$\storage$ls180.v:10069$5_EN[24:0]$2697 25'0000000000000000000000000
- assign $0\memdat[24:0] $memrd$\storage$ls180.v:10070$2698_DATA
- attribute \src "ls180.v:10068.2-10069.129"
+ update $memwr$\mem$ls180.v:10045$1_ADDR $0$memwr$\mem$ls180.v:10045$1_ADDR[6:0]$2681
+ update $memwr$\mem$ls180.v:10045$1_DATA $0$memwr$\mem$ls180.v:10045$1_DATA[31:0]$2682
+ update $memwr$\mem$ls180.v:10045$1_EN $0$memwr$\mem$ls180.v:10045$1_EN[31:0]$2683
+ update $memwr$\mem$ls180.v:10047$2_ADDR $0$memwr$\mem$ls180.v:10047$2_ADDR[6:0]$2684
+ update $memwr$\mem$ls180.v:10047$2_DATA $0$memwr$\mem$ls180.v:10047$2_DATA[31:0]$2685
+ update $memwr$\mem$ls180.v:10047$2_EN $0$memwr$\mem$ls180.v:10047$2_EN[31:0]$2686
+ update $memwr$\mem$ls180.v:10049$3_ADDR $0$memwr$\mem$ls180.v:10049$3_ADDR[6:0]$2687
+ update $memwr$\mem$ls180.v:10049$3_DATA $0$memwr$\mem$ls180.v:10049$3_DATA[31:0]$2688
+ update $memwr$\mem$ls180.v:10049$3_EN $0$memwr$\mem$ls180.v:10049$3_EN[31:0]$2689
+ update $memwr$\mem$ls180.v:10051$4_ADDR $0$memwr$\mem$ls180.v:10051$4_ADDR[6:0]$2690
+ update $memwr$\mem$ls180.v:10051$4_DATA $0$memwr$\mem$ls180.v:10051$4_DATA[31:0]$2691
+ update $memwr$\mem$ls180.v:10051$4_EN $0$memwr$\mem$ls180.v:10051$4_EN[31:0]$2692
+ end
+ attribute \src "ls180.v:1005.5-1005.31"
+ process $proc$ls180.v:1005$3132
+ assign { } { }
+ assign $1\main_spimaster17_re[0:0] 1'0
+ sync always
+ sync init
+ update \main_spimaster17_re $1\main_spimaster17_re[0:0]
+ end
+ attribute \src "ls180.v:10063.1-10067.4"
+ process $proc$ls180.v:10063$2694
+ assign { } { }
+ assign { } { }
+ assign { } { }
+ assign { } { }
+ assign $0$memwr$\storage$ls180.v:10065$5_ADDR[2:0]$2695 3'xxx
+ assign $0$memwr$\storage$ls180.v:10065$5_DATA[24:0]$2696 25'xxxxxxxxxxxxxxxxxxxxxxxxx
+ assign $0$memwr$\storage$ls180.v:10065$5_EN[24:0]$2697 25'0000000000000000000000000
+ assign $0\memdat[24:0] $memrd$\storage$ls180.v:10066$2698_DATA
+ attribute \src "ls180.v:10064.2-10065.129"
switch \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_we
- attribute \src "ls180.v:10068.6-10068.60"
+ attribute \src "ls180.v:10064.6-10064.60"
case 1'1
- assign $0$memwr$\storage$ls180.v:10069$5_ADDR[2:0]$2695 \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr
- assign $0$memwr$\storage$ls180.v:10069$5_DATA[24:0]$2696 \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w
- assign $0$memwr$\storage$ls180.v:10069$5_EN[24:0]$2697 25'1111111111111111111111111
+ assign $0$memwr$\storage$ls180.v:10065$5_ADDR[2:0]$2695 \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr
+ assign $0$memwr$\storage$ls180.v:10065$5_DATA[24:0]$2696 \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w
+ assign $0$memwr$\storage$ls180.v:10065$5_EN[24:0]$2697 25'1111111111111111111111111
case
end
sync posedge \sys_clk_1
update \memdat $0\memdat[24:0]
- update $memwr$\storage$ls180.v:10069$5_ADDR $0$memwr$\storage$ls180.v:10069$5_ADDR[2:0]$2695
- update $memwr$\storage$ls180.v:10069$5_DATA $0$memwr$\storage$ls180.v:10069$5_DATA[24:0]$2696
- update $memwr$\storage$ls180.v:10069$5_EN $0$memwr$\storage$ls180.v:10069$5_EN[24:0]$2697
+ update $memwr$\storage$ls180.v:10065$5_ADDR $0$memwr$\storage$ls180.v:10065$5_ADDR[2:0]$2695
+ update $memwr$\storage$ls180.v:10065$5_DATA $0$memwr$\storage$ls180.v:10065$5_DATA[24:0]$2696
+ update $memwr$\storage$ls180.v:10065$5_EN $0$memwr$\storage$ls180.v:10065$5_EN[24:0]$2697
end
- attribute \src "ls180.v:10073.1-10074.4"
- process $proc$ls180.v:10073$2699
+ attribute \src "ls180.v:10069.1-10070.4"
+ process $proc$ls180.v:10069$2699
sync posedge \sys_clk_1
end
- attribute \src "ls180.v:1008.11-1008.42"
- process $proc$ls180.v:1008$3131
- assign { } { }
- assign $1\main_spimaster16_storage[7:0] 8'00000000
- sync always
- sync init
- update \main_spimaster16_storage $1\main_spimaster16_storage[7:0]
- end
- attribute \src "ls180.v:10081.1-10085.4"
- process $proc$ls180.v:10081$2701
+ attribute \src "ls180.v:10077.1-10081.4"
+ process $proc$ls180.v:10077$2701
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0$memwr$\storage_1$ls180.v:10083$6_ADDR[2:0]$2702 3'xxx
- assign $0$memwr$\storage_1$ls180.v:10083$6_DATA[24:0]$2703 25'xxxxxxxxxxxxxxxxxxxxxxxxx
- assign $0$memwr$\storage_1$ls180.v:10083$6_EN[24:0]$2704 25'0000000000000000000000000
- assign $0\memdat_1[24:0] $memrd$\storage_1$ls180.v:10084$2705_DATA
- attribute \src "ls180.v:10082.2-10083.131"
+ assign $0$memwr$\storage_1$ls180.v:10079$6_ADDR[2:0]$2702 3'xxx
+ assign $0$memwr$\storage_1$ls180.v:10079$6_DATA[24:0]$2703 25'xxxxxxxxxxxxxxxxxxxxxxxxx
+ assign $0$memwr$\storage_1$ls180.v:10079$6_EN[24:0]$2704 25'0000000000000000000000000
+ assign $0\memdat_1[24:0] $memrd$\storage_1$ls180.v:10080$2705_DATA
+ attribute \src "ls180.v:10078.2-10079.131"
switch \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_we
- attribute \src "ls180.v:10082.6-10082.60"
+ attribute \src "ls180.v:10078.6-10078.60"
case 1'1
- assign $0$memwr$\storage_1$ls180.v:10083$6_ADDR[2:0]$2702 \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr
- assign $0$memwr$\storage_1$ls180.v:10083$6_DATA[24:0]$2703 \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w
- assign $0$memwr$\storage_1$ls180.v:10083$6_EN[24:0]$2704 25'1111111111111111111111111
+ assign $0$memwr$\storage_1$ls180.v:10079$6_ADDR[2:0]$2702 \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr
+ assign $0$memwr$\storage_1$ls180.v:10079$6_DATA[24:0]$2703 \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w
+ assign $0$memwr$\storage_1$ls180.v:10079$6_EN[24:0]$2704 25'1111111111111111111111111
case
end
sync posedge \sys_clk_1
update \memdat_1 $0\memdat_1[24:0]
- update $memwr$\storage_1$ls180.v:10083$6_ADDR $0$memwr$\storage_1$ls180.v:10083$6_ADDR[2:0]$2702
- update $memwr$\storage_1$ls180.v:10083$6_DATA $0$memwr$\storage_1$ls180.v:10083$6_DATA[24:0]$2703
- update $memwr$\storage_1$ls180.v:10083$6_EN $0$memwr$\storage_1$ls180.v:10083$6_EN[24:0]$2704
+ update $memwr$\storage_1$ls180.v:10079$6_ADDR $0$memwr$\storage_1$ls180.v:10079$6_ADDR[2:0]$2702
+ update $memwr$\storage_1$ls180.v:10079$6_DATA $0$memwr$\storage_1$ls180.v:10079$6_DATA[24:0]$2703
+ update $memwr$\storage_1$ls180.v:10079$6_EN $0$memwr$\storage_1$ls180.v:10079$6_EN[24:0]$2704
end
- attribute \src "ls180.v:10087.1-10088.4"
- process $proc$ls180.v:10087$2706
+ attribute \src "ls180.v:10083.1-10084.4"
+ process $proc$ls180.v:10083$2706
sync posedge \sys_clk_1
end
- attribute \src "ls180.v:1009.5-1009.31"
- process $proc$ls180.v:1009$3132
+ attribute \src "ls180.v:1009.5-1009.36"
+ process $proc$ls180.v:1009$3133
assign { } { }
- assign $1\main_spimaster17_re[0:0] 1'0
+ assign $1\main_spimaster21_storage[0:0] 1'1
sync always
sync init
- update \main_spimaster17_re $1\main_spimaster17_re[0:0]
+ update \main_spimaster21_storage $1\main_spimaster21_storage[0:0]
end
- attribute \src "ls180.v:10095.1-10099.4"
- process $proc$ls180.v:10095$2708
+ attribute \src "ls180.v:10091.1-10095.4"
+ process $proc$ls180.v:10091$2708
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0$memwr$\storage_2$ls180.v:10097$7_ADDR[2:0]$2709 3'xxx
- assign $0$memwr$\storage_2$ls180.v:10097$7_DATA[24:0]$2710 25'xxxxxxxxxxxxxxxxxxxxxxxxx
- assign $0$memwr$\storage_2$ls180.v:10097$7_EN[24:0]$2711 25'0000000000000000000000000
- assign $0\memdat_2[24:0] $memrd$\storage_2$ls180.v:10098$2712_DATA
- attribute \src "ls180.v:10096.2-10097.131"
+ assign $0$memwr$\storage_2$ls180.v:10093$7_ADDR[2:0]$2709 3'xxx
+ assign $0$memwr$\storage_2$ls180.v:10093$7_DATA[24:0]$2710 25'xxxxxxxxxxxxxxxxxxxxxxxxx
+ assign $0$memwr$\storage_2$ls180.v:10093$7_EN[24:0]$2711 25'0000000000000000000000000
+ assign $0\memdat_2[24:0] $memrd$\storage_2$ls180.v:10094$2712_DATA
+ attribute \src "ls180.v:10092.2-10093.131"
switch \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_we
- attribute \src "ls180.v:10096.6-10096.60"
+ attribute \src "ls180.v:10092.6-10092.60"
case 1'1
- assign $0$memwr$\storage_2$ls180.v:10097$7_ADDR[2:0]$2709 \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr
- assign $0$memwr$\storage_2$ls180.v:10097$7_DATA[24:0]$2710 \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w
- assign $0$memwr$\storage_2$ls180.v:10097$7_EN[24:0]$2711 25'1111111111111111111111111
+ assign $0$memwr$\storage_2$ls180.v:10093$7_ADDR[2:0]$2709 \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr
+ assign $0$memwr$\storage_2$ls180.v:10093$7_DATA[24:0]$2710 \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w
+ assign $0$memwr$\storage_2$ls180.v:10093$7_EN[24:0]$2711 25'1111111111111111111111111
case
end
sync posedge \sys_clk_1
update \memdat_2 $0\memdat_2[24:0]
- update $memwr$\storage_2$ls180.v:10097$7_ADDR $0$memwr$\storage_2$ls180.v:10097$7_ADDR[2:0]$2709
- update $memwr$\storage_2$ls180.v:10097$7_DATA $0$memwr$\storage_2$ls180.v:10097$7_DATA[24:0]$2710
- update $memwr$\storage_2$ls180.v:10097$7_EN $0$memwr$\storage_2$ls180.v:10097$7_EN[24:0]$2711
+ update $memwr$\storage_2$ls180.v:10093$7_ADDR $0$memwr$\storage_2$ls180.v:10093$7_ADDR[2:0]$2709
+ update $memwr$\storage_2$ls180.v:10093$7_DATA $0$memwr$\storage_2$ls180.v:10093$7_DATA[24:0]$2710
+ update $memwr$\storage_2$ls180.v:10093$7_EN $0$memwr$\storage_2$ls180.v:10093$7_EN[24:0]$2711
end
- attribute \src "ls180.v:10101.1-10102.4"
- process $proc$ls180.v:10101$2713
+ attribute \src "ls180.v:10097.1-10098.4"
+ process $proc$ls180.v:10097$2713
sync posedge \sys_clk_1
end
- attribute \src "ls180.v:10109.1-10113.4"
- process $proc$ls180.v:10109$2715
+ attribute \src "ls180.v:1010.5-1010.31"
+ process $proc$ls180.v:1010$3134
assign { } { }
+ assign $1\main_spimaster22_re[0:0] 1'0
+ sync always
+ sync init
+ update \main_spimaster22_re $1\main_spimaster22_re[0:0]
+ end
+ attribute \src "ls180.v:10105.1-10109.4"
+ process $proc$ls180.v:10105$2715
assign { } { }
assign { } { }
assign { } { }
- assign $0$memwr$\storage_3$ls180.v:10111$8_ADDR[2:0]$2716 3'xxx
- assign $0$memwr$\storage_3$ls180.v:10111$8_DATA[24:0]$2717 25'xxxxxxxxxxxxxxxxxxxxxxxxx
- assign $0$memwr$\storage_3$ls180.v:10111$8_EN[24:0]$2718 25'0000000000000000000000000
- assign $0\memdat_3[24:0] $memrd$\storage_3$ls180.v:10112$2719_DATA
- attribute \src "ls180.v:10110.2-10111.131"
+ assign { } { }
+ assign $0$memwr$\storage_3$ls180.v:10107$8_ADDR[2:0]$2716 3'xxx
+ assign $0$memwr$\storage_3$ls180.v:10107$8_DATA[24:0]$2717 25'xxxxxxxxxxxxxxxxxxxxxxxxx
+ assign $0$memwr$\storage_3$ls180.v:10107$8_EN[24:0]$2718 25'0000000000000000000000000
+ assign $0\memdat_3[24:0] $memrd$\storage_3$ls180.v:10108$2719_DATA
+ attribute \src "ls180.v:10106.2-10107.131"
switch \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_we
- attribute \src "ls180.v:10110.6-10110.60"
+ attribute \src "ls180.v:10106.6-10106.60"
case 1'1
- assign $0$memwr$\storage_3$ls180.v:10111$8_ADDR[2:0]$2716 \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr
- assign $0$memwr$\storage_3$ls180.v:10111$8_DATA[24:0]$2717 \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w
- assign $0$memwr$\storage_3$ls180.v:10111$8_EN[24:0]$2718 25'1111111111111111111111111
+ assign $0$memwr$\storage_3$ls180.v:10107$8_ADDR[2:0]$2716 \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr
+ assign $0$memwr$\storage_3$ls180.v:10107$8_DATA[24:0]$2717 \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w
+ assign $0$memwr$\storage_3$ls180.v:10107$8_EN[24:0]$2718 25'1111111111111111111111111
case
end
sync posedge \sys_clk_1
update \memdat_3 $0\memdat_3[24:0]
- update $memwr$\storage_3$ls180.v:10111$8_ADDR $0$memwr$\storage_3$ls180.v:10111$8_ADDR[2:0]$2716
- update $memwr$\storage_3$ls180.v:10111$8_DATA $0$memwr$\storage_3$ls180.v:10111$8_DATA[24:0]$2717
- update $memwr$\storage_3$ls180.v:10111$8_EN $0$memwr$\storage_3$ls180.v:10111$8_EN[24:0]$2718
+ update $memwr$\storage_3$ls180.v:10107$8_ADDR $0$memwr$\storage_3$ls180.v:10107$8_ADDR[2:0]$2716
+ update $memwr$\storage_3$ls180.v:10107$8_DATA $0$memwr$\storage_3$ls180.v:10107$8_DATA[24:0]$2717
+ update $memwr$\storage_3$ls180.v:10107$8_EN $0$memwr$\storage_3$ls180.v:10107$8_EN[24:0]$2718
+ end
+ attribute \src "ls180.v:1011.5-1011.36"
+ process $proc$ls180.v:1011$3135
+ assign { } { }
+ assign $1\main_spimaster23_storage[0:0] 1'0
+ sync always
+ sync init
+ update \main_spimaster23_storage $1\main_spimaster23_storage[0:0]
end
- attribute \src "ls180.v:10115.1-10116.4"
- process $proc$ls180.v:10115$2720
+ attribute \src "ls180.v:10111.1-10112.4"
+ process $proc$ls180.v:10111$2720
sync posedge \sys_clk_1
end
- attribute \src "ls180.v:10124.1-10128.4"
- process $proc$ls180.v:10124$2722
+ attribute \src "ls180.v:1012.5-1012.31"
+ process $proc$ls180.v:1012$3136
+ assign { } { }
+ assign $1\main_spimaster24_re[0:0] 1'0
+ sync always
+ sync init
+ update \main_spimaster24_re $1\main_spimaster24_re[0:0]
+ end
+ attribute \src "ls180.v:10120.1-10124.4"
+ process $proc$ls180.v:10120$2722
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0$memwr$\storage_4$ls180.v:10126$9_ADDR[3:0]$2723 4'xxxx
- assign $0$memwr$\storage_4$ls180.v:10126$9_DATA[9:0]$2724 10'xxxxxxxxxx
- assign $0$memwr$\storage_4$ls180.v:10126$9_EN[9:0]$2725 10'0000000000
- assign $0\memdat_4[9:0] $memrd$\storage_4$ls180.v:10127$2726_DATA
- attribute \src "ls180.v:10125.2-10126.77"
+ assign $0$memwr$\storage_4$ls180.v:10122$9_ADDR[3:0]$2723 4'xxxx
+ assign $0$memwr$\storage_4$ls180.v:10122$9_DATA[9:0]$2724 10'xxxxxxxxxx
+ assign $0$memwr$\storage_4$ls180.v:10122$9_EN[9:0]$2725 10'0000000000
+ assign $0\memdat_4[9:0] $memrd$\storage_4$ls180.v:10123$2726_DATA
+ attribute \src "ls180.v:10121.2-10122.77"
switch \main_uart_tx_fifo_wrport_we
- attribute \src "ls180.v:10125.6-10125.33"
+ attribute \src "ls180.v:10121.6-10121.33"
case 1'1
- assign $0$memwr$\storage_4$ls180.v:10126$9_ADDR[3:0]$2723 \main_uart_tx_fifo_wrport_adr
- assign $0$memwr$\storage_4$ls180.v:10126$9_DATA[9:0]$2724 \main_uart_tx_fifo_wrport_dat_w
- assign $0$memwr$\storage_4$ls180.v:10126$9_EN[9:0]$2725 10'1111111111
+ assign $0$memwr$\storage_4$ls180.v:10122$9_ADDR[3:0]$2723 \main_uart_tx_fifo_wrport_adr
+ assign $0$memwr$\storage_4$ls180.v:10122$9_DATA[9:0]$2724 \main_uart_tx_fifo_wrport_dat_w
+ assign $0$memwr$\storage_4$ls180.v:10122$9_EN[9:0]$2725 10'1111111111
case
end
sync posedge \sys_clk_1
update \memdat_4 $0\memdat_4[9:0]
- update $memwr$\storage_4$ls180.v:10126$9_ADDR $0$memwr$\storage_4$ls180.v:10126$9_ADDR[3:0]$2723
- update $memwr$\storage_4$ls180.v:10126$9_DATA $0$memwr$\storage_4$ls180.v:10126$9_DATA[9:0]$2724
- update $memwr$\storage_4$ls180.v:10126$9_EN $0$memwr$\storage_4$ls180.v:10126$9_EN[9:0]$2725
- end
- attribute \src "ls180.v:1013.5-1013.36"
- process $proc$ls180.v:1013$3133
- assign { } { }
- assign $1\main_spimaster21_storage[0:0] 1'1
- sync always
- sync init
- update \main_spimaster21_storage $1\main_spimaster21_storage[0:0]
+ update $memwr$\storage_4$ls180.v:10122$9_ADDR $0$memwr$\storage_4$ls180.v:10122$9_ADDR[3:0]$2723
+ update $memwr$\storage_4$ls180.v:10122$9_DATA $0$memwr$\storage_4$ls180.v:10122$9_DATA[9:0]$2724
+ update $memwr$\storage_4$ls180.v:10122$9_EN $0$memwr$\storage_4$ls180.v:10122$9_EN[9:0]$2725
end
- attribute \src "ls180.v:10130.1-10133.4"
- process $proc$ls180.v:10130$2727
+ attribute \src "ls180.v:10126.1-10129.4"
+ process $proc$ls180.v:10126$2727
assign $0\memdat_5[9:0] \memdat_5
- attribute \src "ls180.v:10131.2-10132.55"
+ attribute \src "ls180.v:10127.2-10128.55"
switch \main_uart_tx_fifo_rdport_re
- attribute \src "ls180.v:10131.6-10131.33"
+ attribute \src "ls180.v:10127.6-10127.33"
case 1'1
- assign $0\memdat_5[9:0] $memrd$\storage_4$ls180.v:10132$2728_DATA
+ assign $0\memdat_5[9:0] $memrd$\storage_4$ls180.v:10128$2728_DATA
case
end
sync posedge \sys_clk_1
update \memdat_5 $0\memdat_5[9:0]
end
- attribute \src "ls180.v:1014.5-1014.31"
- process $proc$ls180.v:1014$3134
+ attribute \src "ls180.v:1013.5-1013.39"
+ process $proc$ls180.v:1013$3137
assign { } { }
- assign $1\main_spimaster22_re[0:0] 1'0
+ assign $1\main_spimaster25_clk_enable[0:0] 1'0
sync always
sync init
- update \main_spimaster22_re $1\main_spimaster22_re[0:0]
+ update \main_spimaster25_clk_enable $1\main_spimaster25_clk_enable[0:0]
end
- attribute \src "ls180.v:10141.1-10145.4"
- process $proc$ls180.v:10141$2729
+ attribute \src "ls180.v:10137.1-10141.4"
+ process $proc$ls180.v:10137$2729
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0$memwr$\storage_5$ls180.v:10143$10_ADDR[3:0]$2730 4'xxxx
- assign $0$memwr$\storage_5$ls180.v:10143$10_DATA[9:0]$2731 10'xxxxxxxxxx
- assign $0$memwr$\storage_5$ls180.v:10143$10_EN[9:0]$2732 10'0000000000
- assign $0\memdat_6[9:0] $memrd$\storage_5$ls180.v:10144$2733_DATA
- attribute \src "ls180.v:10142.2-10143.77"
+ assign $0$memwr$\storage_5$ls180.v:10139$10_ADDR[3:0]$2730 4'xxxx
+ assign $0$memwr$\storage_5$ls180.v:10139$10_DATA[9:0]$2731 10'xxxxxxxxxx
+ assign $0$memwr$\storage_5$ls180.v:10139$10_EN[9:0]$2732 10'0000000000
+ assign $0\memdat_6[9:0] $memrd$\storage_5$ls180.v:10140$2733_DATA
+ attribute \src "ls180.v:10138.2-10139.77"
switch \main_uart_rx_fifo_wrport_we
- attribute \src "ls180.v:10142.6-10142.33"
+ attribute \src "ls180.v:10138.6-10138.33"
case 1'1
- assign $0$memwr$\storage_5$ls180.v:10143$10_ADDR[3:0]$2730 \main_uart_rx_fifo_wrport_adr
- assign $0$memwr$\storage_5$ls180.v:10143$10_DATA[9:0]$2731 \main_uart_rx_fifo_wrport_dat_w
- assign $0$memwr$\storage_5$ls180.v:10143$10_EN[9:0]$2732 10'1111111111
+ assign $0$memwr$\storage_5$ls180.v:10139$10_ADDR[3:0]$2730 \main_uart_rx_fifo_wrport_adr
+ assign $0$memwr$\storage_5$ls180.v:10139$10_DATA[9:0]$2731 \main_uart_rx_fifo_wrport_dat_w
+ assign $0$memwr$\storage_5$ls180.v:10139$10_EN[9:0]$2732 10'1111111111
case
end
sync posedge \sys_clk_1
update \memdat_6 $0\memdat_6[9:0]
- update $memwr$\storage_5$ls180.v:10143$10_ADDR $0$memwr$\storage_5$ls180.v:10143$10_ADDR[3:0]$2730
- update $memwr$\storage_5$ls180.v:10143$10_DATA $0$memwr$\storage_5$ls180.v:10143$10_DATA[9:0]$2731
- update $memwr$\storage_5$ls180.v:10143$10_EN $0$memwr$\storage_5$ls180.v:10143$10_EN[9:0]$2732
+ update $memwr$\storage_5$ls180.v:10139$10_ADDR $0$memwr$\storage_5$ls180.v:10139$10_ADDR[3:0]$2730
+ update $memwr$\storage_5$ls180.v:10139$10_DATA $0$memwr$\storage_5$ls180.v:10139$10_DATA[9:0]$2731
+ update $memwr$\storage_5$ls180.v:10139$10_EN $0$memwr$\storage_5$ls180.v:10139$10_EN[9:0]$2732
end
- attribute \src "ls180.v:10147.1-10150.4"
- process $proc$ls180.v:10147$2734
+ attribute \src "ls180.v:1014.5-1014.38"
+ process $proc$ls180.v:1014$3138
+ assign { } { }
+ assign $1\main_spimaster26_cs_enable[0:0] 1'0
+ sync always
+ sync init
+ update \main_spimaster26_cs_enable $1\main_spimaster26_cs_enable[0:0]
+ end
+ attribute \src "ls180.v:10143.1-10146.4"
+ process $proc$ls180.v:10143$2734
assign $0\memdat_7[9:0] \memdat_7
- attribute \src "ls180.v:10148.2-10149.55"
+ attribute \src "ls180.v:10144.2-10145.55"
switch \main_uart_rx_fifo_rdport_re
- attribute \src "ls180.v:10148.6-10148.33"
+ attribute \src "ls180.v:10144.6-10144.33"
case 1'1
- assign $0\memdat_7[9:0] $memrd$\storage_5$ls180.v:10149$2735_DATA
+ assign $0\memdat_7[9:0] $memrd$\storage_5$ls180.v:10145$2735_DATA
case
end
sync posedge \sys_clk_1
update \memdat_7 $0\memdat_7[9:0]
end
- attribute \src "ls180.v:1015.5-1015.36"
- process $proc$ls180.v:1015$3135
+ attribute \src "ls180.v:1015.11-1015.40"
+ process $proc$ls180.v:1015$3139
assign { } { }
- assign $1\main_spimaster23_storage[0:0] 1'0
+ assign $1\main_spimaster27_count[2:0] 3'000
sync always
sync init
- update \main_spimaster23_storage $1\main_spimaster23_storage[0:0]
+ update \main_spimaster27_count $1\main_spimaster27_count[2:0]
end
- attribute \src "ls180.v:10157.1-10161.4"
- process $proc$ls180.v:10157$2736
+ attribute \src "ls180.v:10153.1-10157.4"
+ process $proc$ls180.v:10153$2736
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0$memwr$\storage_6$ls180.v:10159$11_ADDR[4:0]$2737 5'xxxxx
- assign $0$memwr$\storage_6$ls180.v:10159$11_DATA[9:0]$2738 10'xxxxxxxxxx
- assign $0$memwr$\storage_6$ls180.v:10159$11_EN[9:0]$2739 10'0000000000
- assign $0\memdat_8[9:0] $memrd$\storage_6$ls180.v:10160$2740_DATA
- attribute \src "ls180.v:10158.2-10159.85"
+ assign $0$memwr$\storage_6$ls180.v:10155$11_ADDR[4:0]$2737 5'xxxxx
+ assign $0$memwr$\storage_6$ls180.v:10155$11_DATA[9:0]$2738 10'xxxxxxxxxx
+ assign $0$memwr$\storage_6$ls180.v:10155$11_EN[9:0]$2739 10'0000000000
+ assign $0\memdat_8[9:0] $memrd$\storage_6$ls180.v:10156$2740_DATA
+ attribute \src "ls180.v:10154.2-10155.85"
switch \main_sdblock2mem_fifo_wrport_we
- attribute \src "ls180.v:10158.6-10158.37"
+ attribute \src "ls180.v:10154.6-10154.37"
case 1'1
- assign $0$memwr$\storage_6$ls180.v:10159$11_ADDR[4:0]$2737 \main_sdblock2mem_fifo_wrport_adr
- assign $0$memwr$\storage_6$ls180.v:10159$11_DATA[9:0]$2738 \main_sdblock2mem_fifo_wrport_dat_w
- assign $0$memwr$\storage_6$ls180.v:10159$11_EN[9:0]$2739 10'1111111111
+ assign $0$memwr$\storage_6$ls180.v:10155$11_ADDR[4:0]$2737 \main_sdblock2mem_fifo_wrport_adr
+ assign $0$memwr$\storage_6$ls180.v:10155$11_DATA[9:0]$2738 \main_sdblock2mem_fifo_wrport_dat_w
+ assign $0$memwr$\storage_6$ls180.v:10155$11_EN[9:0]$2739 10'1111111111
case
end
sync posedge \sys_clk_1
update \memdat_8 $0\memdat_8[9:0]
- update $memwr$\storage_6$ls180.v:10159$11_ADDR $0$memwr$\storage_6$ls180.v:10159$11_ADDR[4:0]$2737
- update $memwr$\storage_6$ls180.v:10159$11_DATA $0$memwr$\storage_6$ls180.v:10159$11_DATA[9:0]$2738
- update $memwr$\storage_6$ls180.v:10159$11_EN $0$memwr$\storage_6$ls180.v:10159$11_EN[9:0]$2739
- end
- attribute \src "ls180.v:1016.5-1016.31"
- process $proc$ls180.v:1016$3136
- assign { } { }
- assign $1\main_spimaster24_re[0:0] 1'0
- sync always
- sync init
- update \main_spimaster24_re $1\main_spimaster24_re[0:0]
+ update $memwr$\storage_6$ls180.v:10155$11_ADDR $0$memwr$\storage_6$ls180.v:10155$11_ADDR[4:0]$2737
+ update $memwr$\storage_6$ls180.v:10155$11_DATA $0$memwr$\storage_6$ls180.v:10155$11_DATA[9:0]$2738
+ update $memwr$\storage_6$ls180.v:10155$11_EN $0$memwr$\storage_6$ls180.v:10155$11_EN[9:0]$2739
end
- attribute \src "ls180.v:10163.1-10164.4"
- process $proc$ls180.v:10163$2741
+ attribute \src "ls180.v:10159.1-10160.4"
+ process $proc$ls180.v:10159$2741
sync posedge \sys_clk_1
end
- attribute \src "ls180.v:1017.5-1017.39"
- process $proc$ls180.v:1017$3137
+ attribute \src "ls180.v:1016.5-1016.39"
+ process $proc$ls180.v:1016$3140
assign { } { }
- assign $1\main_spimaster25_clk_enable[0:0] 1'0
+ assign $1\main_spimaster28_mosi_latch[0:0] 1'0
sync always
sync init
- update \main_spimaster25_clk_enable $1\main_spimaster25_clk_enable[0:0]
+ update \main_spimaster28_mosi_latch $1\main_spimaster28_mosi_latch[0:0]
end
- attribute \src "ls180.v:10171.1-10175.4"
- process $proc$ls180.v:10171$2743
+ attribute \src "ls180.v:10167.1-10171.4"
+ process $proc$ls180.v:10167$2743
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0$memwr$\storage_7$ls180.v:10173$12_ADDR[4:0]$2744 5'xxxxx
- assign $0$memwr$\storage_7$ls180.v:10173$12_DATA[9:0]$2745 10'xxxxxxxxxx
- assign $0$memwr$\storage_7$ls180.v:10173$12_EN[9:0]$2746 10'0000000000
- assign $0\memdat_9[9:0] $memrd$\storage_7$ls180.v:10174$2747_DATA
- attribute \src "ls180.v:10172.2-10173.85"
+ assign $0$memwr$\storage_7$ls180.v:10169$12_ADDR[4:0]$2744 5'xxxxx
+ assign $0$memwr$\storage_7$ls180.v:10169$12_DATA[9:0]$2745 10'xxxxxxxxxx
+ assign $0$memwr$\storage_7$ls180.v:10169$12_EN[9:0]$2746 10'0000000000
+ assign $0\memdat_9[9:0] $memrd$\storage_7$ls180.v:10170$2747_DATA
+ attribute \src "ls180.v:10168.2-10169.85"
switch \main_sdmem2block_fifo_wrport_we
- attribute \src "ls180.v:10172.6-10172.37"
+ attribute \src "ls180.v:10168.6-10168.37"
case 1'1
- assign $0$memwr$\storage_7$ls180.v:10173$12_ADDR[4:0]$2744 \main_sdmem2block_fifo_wrport_adr
- assign $0$memwr$\storage_7$ls180.v:10173$12_DATA[9:0]$2745 \main_sdmem2block_fifo_wrport_dat_w
- assign $0$memwr$\storage_7$ls180.v:10173$12_EN[9:0]$2746 10'1111111111
+ assign $0$memwr$\storage_7$ls180.v:10169$12_ADDR[4:0]$2744 \main_sdmem2block_fifo_wrport_adr
+ assign $0$memwr$\storage_7$ls180.v:10169$12_DATA[9:0]$2745 \main_sdmem2block_fifo_wrport_dat_w
+ assign $0$memwr$\storage_7$ls180.v:10169$12_EN[9:0]$2746 10'1111111111
case
end
sync posedge \sys_clk_1
update \memdat_9 $0\memdat_9[9:0]
- update $memwr$\storage_7$ls180.v:10173$12_ADDR $0$memwr$\storage_7$ls180.v:10173$12_ADDR[4:0]$2744
- update $memwr$\storage_7$ls180.v:10173$12_DATA $0$memwr$\storage_7$ls180.v:10173$12_DATA[9:0]$2745
- update $memwr$\storage_7$ls180.v:10173$12_EN $0$memwr$\storage_7$ls180.v:10173$12_EN[9:0]$2746
- end
- attribute \src "ls180.v:10177.1-10178.4"
- process $proc$ls180.v:10177$2748
- sync posedge \sys_clk_1
+ update $memwr$\storage_7$ls180.v:10169$12_ADDR $0$memwr$\storage_7$ls180.v:10169$12_ADDR[4:0]$2744
+ update $memwr$\storage_7$ls180.v:10169$12_DATA $0$memwr$\storage_7$ls180.v:10169$12_DATA[9:0]$2745
+ update $memwr$\storage_7$ls180.v:10169$12_EN $0$memwr$\storage_7$ls180.v:10169$12_EN[9:0]$2746
end
- attribute \src "ls180.v:1018.5-1018.38"
- process $proc$ls180.v:1018$3138
- assign { } { }
- assign $1\main_spimaster26_cs_enable[0:0] 1'0
- sync always
- sync init
- update \main_spimaster26_cs_enable $1\main_spimaster26_cs_enable[0:0]
- end
- attribute \src "ls180.v:1019.11-1019.40"
- process $proc$ls180.v:1019$3139
- assign { } { }
- assign $1\main_spimaster27_count[2:0] 3'000
- sync always
- sync init
- update \main_spimaster27_count $1\main_spimaster27_count[2:0]
- end
- attribute \src "ls180.v:1020.5-1020.39"
- process $proc$ls180.v:1020$3140
- assign { } { }
- assign $1\main_spimaster28_mosi_latch[0:0] 1'0
- sync always
- sync init
- update \main_spimaster28_mosi_latch $1\main_spimaster28_mosi_latch[0:0]
- end
- attribute \src "ls180.v:1021.5-1021.39"
- process $proc$ls180.v:1021$3141
+ attribute \src "ls180.v:1017.5-1017.39"
+ process $proc$ls180.v:1017$3141
assign { } { }
assign $1\main_spimaster29_miso_latch[0:0] 1'0
sync always
sync init
update \main_spimaster29_miso_latch $1\main_spimaster29_miso_latch[0:0]
end
- attribute \src "ls180.v:1022.12-1022.48"
- process $proc$ls180.v:1022$3142
+ attribute \src "ls180.v:10173.1-10174.4"
+ process $proc$ls180.v:10173$2748
+ sync posedge \sys_clk_1
+ end
+ attribute \src "ls180.v:1018.12-1018.48"
+ process $proc$ls180.v:1018$3142
assign { } { }
assign $1\main_spimaster30_clk_divider[15:0] 16'0000000000000000
sync always
sync init
update \main_spimaster30_clk_divider $1\main_spimaster30_clk_divider[15:0]
end
- attribute \src "ls180.v:1025.11-1025.44"
- process $proc$ls180.v:1025$3143
+ attribute \src "ls180.v:1021.11-1021.44"
+ process $proc$ls180.v:1021$3143
assign { } { }
assign $1\main_spimaster33_mosi_data[7:0] 8'00000000
sync always
sync init
update \main_spimaster33_mosi_data $1\main_spimaster33_mosi_data[7:0]
end
- attribute \src "ls180.v:1026.11-1026.43"
- process $proc$ls180.v:1026$3144
+ attribute \src "ls180.v:1022.11-1022.43"
+ process $proc$ls180.v:1022$3144
assign { } { }
assign $1\main_spimaster34_mosi_sel[2:0] 3'000
sync always
sync init
update \main_spimaster34_mosi_sel $1\main_spimaster34_mosi_sel[2:0]
end
- attribute \src "ls180.v:1027.11-1027.44"
- process $proc$ls180.v:1027$3145
+ attribute \src "ls180.v:1023.11-1023.44"
+ process $proc$ls180.v:1023$3145
assign { } { }
assign $1\main_spimaster35_miso_data[7:0] 8'00000000
sync always
sync init
update \main_spimaster35_miso_data $1\main_spimaster35_miso_data[7:0]
end
- attribute \src "ls180.v:1030.5-1030.32"
- process $proc$ls180.v:1030$3146
+ attribute \src "ls180.v:1026.5-1026.32"
+ process $proc$ls180.v:1026$3146
assign { } { }
assign $1\main_spisdcard_done0[0:0] 1'0
sync always
sync init
update \main_spisdcard_done0 $1\main_spisdcard_done0[0:0]
end
- attribute \src "ls180.v:1031.5-1031.30"
- process $proc$ls180.v:1031$3147
+ attribute \src "ls180.v:1027.5-1027.30"
+ process $proc$ls180.v:1027$3147
assign { } { }
assign $1\main_spisdcard_irq[0:0] 1'0
sync always
sync init
update \main_spisdcard_irq $1\main_spisdcard_irq[0:0]
end
- attribute \src "ls180.v:1033.11-1033.37"
- process $proc$ls180.v:1033$3148
+ attribute \src "ls180.v:1029.11-1029.37"
+ process $proc$ls180.v:1029$3148
assign { } { }
assign $1\main_spisdcard_miso[7:0] 8'00000000
sync always
sync init
update \main_spisdcard_miso $1\main_spisdcard_miso[7:0]
end
- attribute \src "ls180.v:1037.5-1037.33"
- process $proc$ls180.v:1037$3149
+ attribute \src "ls180.v:1033.5-1033.33"
+ process $proc$ls180.v:1033$3149
assign { } { }
assign $1\main_spisdcard_start1[0:0] 1'0
sync always
sync init
update \main_spisdcard_start1 $1\main_spisdcard_start1[0:0]
end
- attribute \src "ls180.v:1039.12-1039.50"
- process $proc$ls180.v:1039$3150
+ attribute \src "ls180.v:1035.12-1035.50"
+ process $proc$ls180.v:1035$3150
assign { } { }
assign $1\main_spisdcard_control_storage[15:0] 16'0000000000000000
sync always
sync init
update \main_spisdcard_control_storage $1\main_spisdcard_control_storage[15:0]
end
- attribute \src "ls180.v:1040.5-1040.37"
- process $proc$ls180.v:1040$3151
+ attribute \src "ls180.v:1036.5-1036.37"
+ process $proc$ls180.v:1036$3151
assign { } { }
assign $1\main_spisdcard_control_re[0:0] 1'0
sync always
sync init
update \main_spisdcard_control_re $1\main_spisdcard_control_re[0:0]
end
- attribute \src "ls180.v:1044.11-1044.45"
- process $proc$ls180.v:1044$3152
+ attribute \src "ls180.v:1040.11-1040.45"
+ process $proc$ls180.v:1040$3152
assign { } { }
assign $1\main_spisdcard_mosi_storage[7:0] 8'00000000
sync always
sync init
update \main_spisdcard_mosi_storage $1\main_spisdcard_mosi_storage[7:0]
end
- attribute \src "ls180.v:1045.5-1045.34"
- process $proc$ls180.v:1045$3153
+ attribute \src "ls180.v:1041.5-1041.34"
+ process $proc$ls180.v:1041$3153
assign { } { }
assign $1\main_spisdcard_mosi_re[0:0] 1'0
sync always
sync init
update \main_spisdcard_mosi_re $1\main_spisdcard_mosi_re[0:0]
end
- attribute \src "ls180.v:1049.5-1049.37"
- process $proc$ls180.v:1049$3154
+ attribute \src "ls180.v:1045.5-1045.37"
+ process $proc$ls180.v:1045$3154
assign { } { }
assign $1\main_spisdcard_cs_storage[0:0] 1'1
sync always
sync init
update \main_spisdcard_cs_storage $1\main_spisdcard_cs_storage[0:0]
end
- attribute \src "ls180.v:1050.5-1050.32"
- process $proc$ls180.v:1050$3155
+ attribute \src "ls180.v:1046.5-1046.32"
+ process $proc$ls180.v:1046$3155
assign { } { }
assign $1\main_spisdcard_cs_re[0:0] 1'0
sync always
sync init
update \main_spisdcard_cs_re $1\main_spisdcard_cs_re[0:0]
end
- attribute \src "ls180.v:1051.5-1051.43"
- process $proc$ls180.v:1051$3156
+ attribute \src "ls180.v:1047.5-1047.43"
+ process $proc$ls180.v:1047$3156
assign { } { }
assign $1\main_spisdcard_loopback_storage[0:0] 1'0
sync always
sync init
update \main_spisdcard_loopback_storage $1\main_spisdcard_loopback_storage[0:0]
end
- attribute \src "ls180.v:1052.5-1052.38"
- process $proc$ls180.v:1052$3157
+ attribute \src "ls180.v:1048.5-1048.38"
+ process $proc$ls180.v:1048$3157
assign { } { }
assign $1\main_spisdcard_loopback_re[0:0] 1'0
sync always
sync init
update \main_spisdcard_loopback_re $1\main_spisdcard_loopback_re[0:0]
end
- attribute \src "ls180.v:1053.5-1053.37"
- process $proc$ls180.v:1053$3158
+ attribute \src "ls180.v:1049.5-1049.37"
+ process $proc$ls180.v:1049$3158
assign { } { }
assign $1\main_spisdcard_clk_enable[0:0] 1'0
sync always
sync init
update \main_spisdcard_clk_enable $1\main_spisdcard_clk_enable[0:0]
end
- attribute \src "ls180.v:1054.5-1054.36"
- process $proc$ls180.v:1054$3159
+ attribute \src "ls180.v:1050.5-1050.36"
+ process $proc$ls180.v:1050$3159
assign { } { }
assign $1\main_spisdcard_cs_enable[0:0] 1'0
sync always
sync init
update \main_spisdcard_cs_enable $1\main_spisdcard_cs_enable[0:0]
end
- attribute \src "ls180.v:1055.11-1055.38"
- process $proc$ls180.v:1055$3160
+ attribute \src "ls180.v:1051.11-1051.38"
+ process $proc$ls180.v:1051$3160
assign { } { }
assign $1\main_spisdcard_count[2:0] 3'000
sync always
sync init
update \main_spisdcard_count $1\main_spisdcard_count[2:0]
end
- attribute \src "ls180.v:1056.5-1056.37"
- process $proc$ls180.v:1056$3161
+ attribute \src "ls180.v:1052.5-1052.37"
+ process $proc$ls180.v:1052$3161
assign { } { }
assign $1\main_spisdcard_mosi_latch[0:0] 1'0
sync always
sync init
update \main_spisdcard_mosi_latch $1\main_spisdcard_mosi_latch[0:0]
end
- attribute \src "ls180.v:1057.5-1057.37"
- process $proc$ls180.v:1057$3162
+ attribute \src "ls180.v:1053.5-1053.37"
+ process $proc$ls180.v:1053$3162
assign { } { }
assign $1\main_spisdcard_miso_latch[0:0] 1'0
sync always
sync init
update \main_spisdcard_miso_latch $1\main_spisdcard_miso_latch[0:0]
end
- attribute \src "ls180.v:1058.12-1058.47"
- process $proc$ls180.v:1058$3163
+ attribute \src "ls180.v:1054.12-1054.47"
+ process $proc$ls180.v:1054$3163
assign { } { }
assign $1\main_spisdcard_clk_divider1[15:0] 16'0000000000000000
sync always
sync init
update \main_spisdcard_clk_divider1 $1\main_spisdcard_clk_divider1[15:0]
end
- attribute \src "ls180.v:1061.11-1061.42"
- process $proc$ls180.v:1061$3164
+ attribute \src "ls180.v:1057.11-1057.42"
+ process $proc$ls180.v:1057$3164
assign { } { }
assign $1\main_spisdcard_mosi_data[7:0] 8'00000000
sync always
sync init
update \main_spisdcard_mosi_data $1\main_spisdcard_mosi_data[7:0]
end
- attribute \src "ls180.v:1062.11-1062.41"
- process $proc$ls180.v:1062$3165
+ attribute \src "ls180.v:1058.11-1058.41"
+ process $proc$ls180.v:1058$3165
assign { } { }
assign $1\main_spisdcard_mosi_sel[2:0] 3'000
sync always
sync init
update \main_spisdcard_mosi_sel $1\main_spisdcard_mosi_sel[2:0]
end
- attribute \src "ls180.v:1063.11-1063.42"
- process $proc$ls180.v:1063$3166
+ attribute \src "ls180.v:1059.11-1059.42"
+ process $proc$ls180.v:1059$3166
assign { } { }
assign $1\main_spisdcard_miso_data[7:0] 8'00000000
sync always
sync init
update \main_spisdcard_miso_data $1\main_spisdcard_miso_data[7:0]
end
- attribute \src "ls180.v:1064.12-1064.45"
- process $proc$ls180.v:1064$3167
+ attribute \src "ls180.v:1060.12-1060.45"
+ process $proc$ls180.v:1060$3167
assign { } { }
assign $1\main_spimaster1_storage[15:0] 16'0000000001111101
sync always
sync init
update \main_spimaster1_storage $1\main_spimaster1_storage[15:0]
end
- attribute \src "ls180.v:1065.5-1065.30"
- process $proc$ls180.v:1065$3168
+ attribute \src "ls180.v:1061.5-1061.30"
+ process $proc$ls180.v:1061$3168
assign { } { }
assign $1\main_spimaster1_re[0:0] 1'0
sync always
sync init
update \main_spimaster1_re $1\main_spimaster1_re[0:0]
end
- attribute \src "ls180.v:1067.12-1067.30"
- process $proc$ls180.v:1067$3169
+ attribute \src "ls180.v:1063.12-1063.30"
+ process $proc$ls180.v:1063$3169
assign { } { }
assign $1\main_dummy[23:0] 24'000000000000000000000000
sync always
sync init
update \main_dummy $1\main_dummy[23:0]
end
- attribute \src "ls180.v:1071.12-1071.37"
- process $proc$ls180.v:1071$3170
+ attribute \src "ls180.v:1067.12-1067.37"
+ process $proc$ls180.v:1067$3170
assign { } { }
assign $1\main_pwm0_counter[31:0] 0
sync always
sync init
update \main_pwm0_counter $1\main_pwm0_counter[31:0]
end
- attribute \src "ls180.v:1072.5-1072.36"
- process $proc$ls180.v:1072$3171
+ attribute \src "ls180.v:1068.5-1068.36"
+ process $proc$ls180.v:1068$3171
assign { } { }
assign $1\main_pwm0_enable_storage[0:0] 1'0
sync always
sync init
update \main_pwm0_enable_storage $1\main_pwm0_enable_storage[0:0]
end
- attribute \src "ls180.v:1073.5-1073.31"
- process $proc$ls180.v:1073$3172
+ attribute \src "ls180.v:1069.5-1069.31"
+ process $proc$ls180.v:1069$3172
assign { } { }
assign $1\main_pwm0_enable_re[0:0] 1'0
sync always
sync init
update \main_pwm0_enable_re $1\main_pwm0_enable_re[0:0]
end
- attribute \src "ls180.v:1074.12-1074.43"
- process $proc$ls180.v:1074$3173
+ attribute \src "ls180.v:1070.12-1070.43"
+ process $proc$ls180.v:1070$3173
assign { } { }
assign $1\main_pwm0_width_storage[31:0] 0
sync always
sync init
update \main_pwm0_width_storage $1\main_pwm0_width_storage[31:0]
end
- attribute \src "ls180.v:1075.5-1075.30"
- process $proc$ls180.v:1075$3174
+ attribute \src "ls180.v:1071.5-1071.30"
+ process $proc$ls180.v:1071$3174
assign { } { }
assign $1\main_pwm0_width_re[0:0] 1'0
sync always
sync init
update \main_pwm0_width_re $1\main_pwm0_width_re[0:0]
end
- attribute \src "ls180.v:1076.12-1076.44"
- process $proc$ls180.v:1076$3175
+ attribute \src "ls180.v:1072.12-1072.44"
+ process $proc$ls180.v:1072$3175
assign { } { }
assign $1\main_pwm0_period_storage[31:0] 0
sync always
sync init
update \main_pwm0_period_storage $1\main_pwm0_period_storage[31:0]
end
- attribute \src "ls180.v:1077.5-1077.31"
- process $proc$ls180.v:1077$3176
+ attribute \src "ls180.v:1073.5-1073.31"
+ process $proc$ls180.v:1073$3176
assign { } { }
assign $1\main_pwm0_period_re[0:0] 1'0
sync always
sync init
update \main_pwm0_period_re $1\main_pwm0_period_re[0:0]
end
- attribute \src "ls180.v:1081.12-1081.37"
- process $proc$ls180.v:1081$3177
+ attribute \src "ls180.v:1077.12-1077.37"
+ process $proc$ls180.v:1077$3177
assign { } { }
assign $1\main_pwm1_counter[31:0] 0
sync always
sync init
update \main_pwm1_counter $1\main_pwm1_counter[31:0]
end
- attribute \src "ls180.v:1082.5-1082.36"
- process $proc$ls180.v:1082$3178
+ attribute \src "ls180.v:1078.5-1078.36"
+ process $proc$ls180.v:1078$3178
assign { } { }
assign $1\main_pwm1_enable_storage[0:0] 1'0
sync always
sync init
update \main_pwm1_enable_storage $1\main_pwm1_enable_storage[0:0]
end
- attribute \src "ls180.v:1083.5-1083.31"
- process $proc$ls180.v:1083$3179
+ attribute \src "ls180.v:1079.5-1079.31"
+ process $proc$ls180.v:1079$3179
assign { } { }
assign $1\main_pwm1_enable_re[0:0] 1'0
sync always
sync init
update \main_pwm1_enable_re $1\main_pwm1_enable_re[0:0]
end
- attribute \src "ls180.v:1084.12-1084.43"
- process $proc$ls180.v:1084$3180
+ attribute \src "ls180.v:1080.12-1080.43"
+ process $proc$ls180.v:1080$3180
assign { } { }
assign $1\main_pwm1_width_storage[31:0] 0
sync always
sync init
update \main_pwm1_width_storage $1\main_pwm1_width_storage[31:0]
end
- attribute \src "ls180.v:1085.5-1085.30"
- process $proc$ls180.v:1085$3181
+ attribute \src "ls180.v:1081.5-1081.30"
+ process $proc$ls180.v:1081$3181
assign { } { }
assign $1\main_pwm1_width_re[0:0] 1'0
sync always
sync init
update \main_pwm1_width_re $1\main_pwm1_width_re[0:0]
end
- attribute \src "ls180.v:1086.12-1086.44"
- process $proc$ls180.v:1086$3182
+ attribute \src "ls180.v:1082.12-1082.44"
+ process $proc$ls180.v:1082$3182
assign { } { }
assign $1\main_pwm1_period_storage[31:0] 0
sync always
sync init
update \main_pwm1_period_storage $1\main_pwm1_period_storage[31:0]
end
- attribute \src "ls180.v:1087.5-1087.31"
- process $proc$ls180.v:1087$3183
+ attribute \src "ls180.v:1083.5-1083.31"
+ process $proc$ls180.v:1083$3183
assign { } { }
assign $1\main_pwm1_period_re[0:0] 1'0
sync always
sync init
update \main_pwm1_period_re $1\main_pwm1_period_re[0:0]
end
- attribute \src "ls180.v:1091.11-1091.34"
- process $proc$ls180.v:1091$3184
+ attribute \src "ls180.v:1087.11-1087.34"
+ process $proc$ls180.v:1087$3184
assign { } { }
assign $1\main_i2c_storage[2:0] 3'000
sync always
sync init
update \main_i2c_storage $1\main_i2c_storage[2:0]
end
- attribute \src "ls180.v:1092.5-1092.23"
- process $proc$ls180.v:1092$3185
+ attribute \src "ls180.v:1088.5-1088.23"
+ process $proc$ls180.v:1088$3185
assign { } { }
assign $1\main_i2c_re[0:0] 1'0
sync always
sync init
update \main_i2c_re $1\main_i2c_re[0:0]
end
- attribute \src "ls180.v:1098.11-1098.46"
- process $proc$ls180.v:1098$3186
+ attribute \src "ls180.v:1094.11-1094.46"
+ process $proc$ls180.v:1094$3186
assign { } { }
assign $1\main_sdphy_clocker_storage[8:0] 9'100000000
sync always
sync init
update \main_sdphy_clocker_storage $1\main_sdphy_clocker_storage[8:0]
end
- attribute \src "ls180.v:1099.5-1099.33"
- process $proc$ls180.v:1099$3187
+ attribute \src "ls180.v:1095.5-1095.33"
+ process $proc$ls180.v:1095$3187
assign { } { }
assign $1\main_sdphy_clocker_re[0:0] 1'0
sync always
sync init
update \main_sdphy_clocker_re $1\main_sdphy_clocker_re[0:0]
end
- attribute \src "ls180.v:1101.5-1101.35"
- process $proc$ls180.v:1101$3188
+ attribute \src "ls180.v:1097.5-1097.35"
+ process $proc$ls180.v:1097$3188
assign { } { }
assign $1\main_sdphy_clocker_clk0[0:0] 1'0
sync always
sync init
update \main_sdphy_clocker_clk0 $1\main_sdphy_clocker_clk0[0:0]
end
- attribute \src "ls180.v:1103.11-1103.41"
- process $proc$ls180.v:1103$3189
+ attribute \src "ls180.v:1099.11-1099.41"
+ process $proc$ls180.v:1099$3189
assign { } { }
assign $1\main_sdphy_clocker_clks[8:0] 9'000000000
sync always
sync init
update \main_sdphy_clocker_clks $1\main_sdphy_clocker_clks[8:0]
end
- attribute \src "ls180.v:1104.5-1104.35"
- process $proc$ls180.v:1104$3190
+ attribute \src "ls180.v:1100.5-1100.35"
+ process $proc$ls180.v:1100$3190
assign { } { }
assign $1\main_sdphy_clocker_clk1[0:0] 1'0
sync always
sync init
update \main_sdphy_clocker_clk1 $1\main_sdphy_clocker_clk1[0:0]
end
- attribute \src "ls180.v:1105.5-1105.36"
- process $proc$ls180.v:1105$3191
+ attribute \src "ls180.v:1101.5-1101.36"
+ process $proc$ls180.v:1101$3191
assign { } { }
assign $1\main_sdphy_clocker_clk_d[0:0] 1'0
sync always
sync init
update \main_sdphy_clocker_clk_d $1\main_sdphy_clocker_clk_d[0:0]
end
- attribute \src "ls180.v:1109.5-1109.40"
- process $proc$ls180.v:1109$3192
+ attribute \src "ls180.v:1105.5-1105.40"
+ process $proc$ls180.v:1105$3192
assign { } { }
assign $0\main_sdphy_init_initialize_w[0:0] 1'0
sync always
update \main_sdphy_init_initialize_w $0\main_sdphy_init_initialize_w[0:0]
sync init
end
- attribute \src "ls180.v:1114.5-1114.48"
- process $proc$ls180.v:1114$3193
+ attribute \src "ls180.v:1110.5-1110.48"
+ process $proc$ls180.v:1110$3193
assign { } { }
assign $1\main_sdphy_init_pads_out_payload_clk[0:0] 1'0
sync always
sync init
update \main_sdphy_init_pads_out_payload_clk $1\main_sdphy_init_pads_out_payload_clk[0:0]
end
- attribute \src "ls180.v:1115.5-1115.50"
- process $proc$ls180.v:1115$3194
+ attribute \src "ls180.v:1111.5-1111.50"
+ process $proc$ls180.v:1111$3194
assign { } { }
assign $1\main_sdphy_init_pads_out_payload_cmd_o[0:0] 1'0
sync always
sync init
update \main_sdphy_init_pads_out_payload_cmd_o $1\main_sdphy_init_pads_out_payload_cmd_o[0:0]
end
- attribute \src "ls180.v:1116.5-1116.51"
- process $proc$ls180.v:1116$3195
+ attribute \src "ls180.v:1112.5-1112.51"
+ process $proc$ls180.v:1112$3195
assign { } { }
assign $1\main_sdphy_init_pads_out_payload_cmd_oe[0:0] 1'0
sync always
sync init
update \main_sdphy_init_pads_out_payload_cmd_oe $1\main_sdphy_init_pads_out_payload_cmd_oe[0:0]
end
- attribute \src "ls180.v:1117.11-1117.57"
- process $proc$ls180.v:1117$3196
+ attribute \src "ls180.v:1113.11-1113.57"
+ process $proc$ls180.v:1113$3196
assign { } { }
assign $1\main_sdphy_init_pads_out_payload_data_o[3:0] 4'0000
sync always
sync init
update \main_sdphy_init_pads_out_payload_data_o $1\main_sdphy_init_pads_out_payload_data_o[3:0]
end
- attribute \src "ls180.v:1118.5-1118.52"
- process $proc$ls180.v:1118$3197
+ attribute \src "ls180.v:1114.5-1114.52"
+ process $proc$ls180.v:1114$3197
assign { } { }
assign $1\main_sdphy_init_pads_out_payload_data_oe[0:0] 1'0
sync always
sync init
update \main_sdphy_init_pads_out_payload_data_oe $1\main_sdphy_init_pads_out_payload_data_oe[0:0]
end
- attribute \src "ls180.v:1119.11-1119.39"
- process $proc$ls180.v:1119$3198
+ attribute \src "ls180.v:1115.11-1115.39"
+ process $proc$ls180.v:1115$3198
assign { } { }
assign $1\main_sdphy_init_count[7:0] 8'00000000
sync always
sync init
update \main_sdphy_init_count $1\main_sdphy_init_count[7:0]
end
- attribute \src "ls180.v:1124.5-1124.48"
- process $proc$ls180.v:1124$3199
+ attribute \src "ls180.v:112.5-112.49"
+ process $proc$ls180.v:112$2773
+ assign { } { }
+ assign $1\main_libresocsim_libresoc_jtag_wb_ack[0:0] 1'0
+ sync always
+ sync init
+ update \main_libresocsim_libresoc_jtag_wb_ack $1\main_libresocsim_libresoc_jtag_wb_ack[0:0]
+ end
+ attribute \src "ls180.v:1120.5-1120.48"
+ process $proc$ls180.v:1120$3199
assign { } { }
assign $1\main_sdphy_cmdw_pads_out_payload_clk[0:0] 1'0
sync always
sync init
update \main_sdphy_cmdw_pads_out_payload_clk $1\main_sdphy_cmdw_pads_out_payload_clk[0:0]
end
- attribute \src "ls180.v:1125.5-1125.50"
- process $proc$ls180.v:1125$3200
+ attribute \src "ls180.v:1121.5-1121.50"
+ process $proc$ls180.v:1121$3200
assign { } { }
assign $1\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] 1'0
sync always
sync init
update \main_sdphy_cmdw_pads_out_payload_cmd_o $1\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0]
end
- attribute \src "ls180.v:1126.5-1126.51"
- process $proc$ls180.v:1126$3201
+ attribute \src "ls180.v:1122.5-1122.51"
+ process $proc$ls180.v:1122$3201
assign { } { }
assign $1\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] 1'0
sync always
sync init
update \main_sdphy_cmdw_pads_out_payload_cmd_oe $1\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0]
end
- attribute \src "ls180.v:1127.11-1127.57"
- process $proc$ls180.v:1127$3202
+ attribute \src "ls180.v:1123.11-1123.57"
+ process $proc$ls180.v:1123$3202
assign { } { }
assign $0\main_sdphy_cmdw_pads_out_payload_data_o[3:0] 4'0000
sync always
update \main_sdphy_cmdw_pads_out_payload_data_o $0\main_sdphy_cmdw_pads_out_payload_data_o[3:0]
sync init
end
- attribute \src "ls180.v:1128.5-1128.52"
- process $proc$ls180.v:1128$3203
+ attribute \src "ls180.v:1124.5-1124.52"
+ process $proc$ls180.v:1124$3203
assign { } { }
assign $0\main_sdphy_cmdw_pads_out_payload_data_oe[0:0] 1'0
sync always
update \main_sdphy_cmdw_pads_out_payload_data_oe $0\main_sdphy_cmdw_pads_out_payload_data_oe[0:0]
sync init
end
- attribute \src "ls180.v:1129.5-1129.38"
- process $proc$ls180.v:1129$3204
+ attribute \src "ls180.v:1125.5-1125.38"
+ process $proc$ls180.v:1125$3204
assign { } { }
assign $1\main_sdphy_cmdw_sink_valid[0:0] 1'0
sync always
sync init
update \main_sdphy_cmdw_sink_valid $1\main_sdphy_cmdw_sink_valid[0:0]
end
- attribute \src "ls180.v:1130.5-1130.38"
- process $proc$ls180.v:1130$3205
+ attribute \src "ls180.v:1126.5-1126.38"
+ process $proc$ls180.v:1126$3205
assign { } { }
assign $1\main_sdphy_cmdw_sink_ready[0:0] 1'0
sync always
sync init
update \main_sdphy_cmdw_sink_ready $1\main_sdphy_cmdw_sink_ready[0:0]
end
- attribute \src "ls180.v:1131.5-1131.37"
- process $proc$ls180.v:1131$3206
+ attribute \src "ls180.v:1127.5-1127.37"
+ process $proc$ls180.v:1127$3206
assign { } { }
assign $1\main_sdphy_cmdw_sink_last[0:0] 1'0
sync always
sync init
update \main_sdphy_cmdw_sink_last $1\main_sdphy_cmdw_sink_last[0:0]
end
- attribute \src "ls180.v:1132.11-1132.51"
- process $proc$ls180.v:1132$3207
+ attribute \src "ls180.v:1128.11-1128.51"
+ process $proc$ls180.v:1128$3207
assign { } { }
assign $1\main_sdphy_cmdw_sink_payload_data[7:0] 8'00000000
sync always
sync init
update \main_sdphy_cmdw_sink_payload_data $1\main_sdphy_cmdw_sink_payload_data[7:0]
end
- attribute \src "ls180.v:1133.5-1133.32"
- process $proc$ls180.v:1133$3208
+ attribute \src "ls180.v:1129.5-1129.32"
+ process $proc$ls180.v:1129$3208
assign { } { }
assign $1\main_sdphy_cmdw_done[0:0] 1'0
sync always
sync init
update \main_sdphy_cmdw_done $1\main_sdphy_cmdw_done[0:0]
end
- attribute \src "ls180.v:1134.11-1134.39"
- process $proc$ls180.v:1134$3209
+ attribute \src "ls180.v:1130.11-1130.39"
+ process $proc$ls180.v:1130$3209
assign { } { }
assign $1\main_sdphy_cmdw_count[7:0] 8'00000000
sync always
sync init
update \main_sdphy_cmdw_count $1\main_sdphy_cmdw_count[7:0]
end
- attribute \src "ls180.v:1137.5-1137.49"
- process $proc$ls180.v:1137$3210
+ attribute \src "ls180.v:1133.5-1133.49"
+ process $proc$ls180.v:1133$3210
assign { } { }
assign $0\main_sdphy_cmdr_pads_in_pads_in_first[0:0] 1'0
sync always
update \main_sdphy_cmdr_pads_in_pads_in_first $0\main_sdphy_cmdr_pads_in_pads_in_first[0:0]
sync init
end
- attribute \src "ls180.v:1138.5-1138.48"
- process $proc$ls180.v:1138$3211
+ attribute \src "ls180.v:1134.5-1134.48"
+ process $proc$ls180.v:1134$3211
assign { } { }
assign $0\main_sdphy_cmdr_pads_in_pads_in_last[0:0] 1'0
sync always
update \main_sdphy_cmdr_pads_in_pads_in_last $0\main_sdphy_cmdr_pads_in_pads_in_last[0:0]
sync init
end
- attribute \src "ls180.v:1139.5-1139.55"
- process $proc$ls180.v:1139$3212
+ attribute \src "ls180.v:1135.5-1135.55"
+ process $proc$ls180.v:1135$3212
assign { } { }
assign $0\main_sdphy_cmdr_pads_in_pads_in_payload_clk[0:0] 1'0
sync always
update \main_sdphy_cmdr_pads_in_pads_in_payload_clk $0\main_sdphy_cmdr_pads_in_pads_in_payload_clk[0:0]
sync init
end
- attribute \src "ls180.v:1141.5-1141.57"
- process $proc$ls180.v:1141$3213
+ attribute \src "ls180.v:1137.5-1137.57"
+ process $proc$ls180.v:1137$3213
assign { } { }
assign $0\main_sdphy_cmdr_pads_in_pads_in_payload_cmd_o[0:0] 1'0
sync always
update \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_o $0\main_sdphy_cmdr_pads_in_pads_in_payload_cmd_o[0:0]
sync init
end
- attribute \src "ls180.v:1142.5-1142.58"
- process $proc$ls180.v:1142$3214
+ attribute \src "ls180.v:1138.5-1138.58"
+ process $proc$ls180.v:1138$3214
assign { } { }
assign $0\main_sdphy_cmdr_pads_in_pads_in_payload_cmd_oe[0:0] 1'0
sync always
update \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_oe $0\main_sdphy_cmdr_pads_in_pads_in_payload_cmd_oe[0:0]
sync init
end
- attribute \src "ls180.v:1144.11-1144.64"
- process $proc$ls180.v:1144$3215
+ attribute \src "ls180.v:114.5-114.49"
+ process $proc$ls180.v:114$2774
+ assign { } { }
+ assign $0\main_libresocsim_libresoc_jtag_wb_err[0:0] 1'0
+ sync always
+ update \main_libresocsim_libresoc_jtag_wb_err $0\main_libresocsim_libresoc_jtag_wb_err[0:0]
+ sync init
+ end
+ attribute \src "ls180.v:1140.11-1140.64"
+ process $proc$ls180.v:1140$3215
assign { } { }
assign $0\main_sdphy_cmdr_pads_in_pads_in_payload_data_o[3:0] 4'0000
sync always
update \main_sdphy_cmdr_pads_in_pads_in_payload_data_o $0\main_sdphy_cmdr_pads_in_pads_in_payload_data_o[3:0]
sync init
end
- attribute \src "ls180.v:1145.5-1145.59"
- process $proc$ls180.v:1145$3216
+ attribute \src "ls180.v:1141.5-1141.59"
+ process $proc$ls180.v:1141$3216
assign { } { }
assign $0\main_sdphy_cmdr_pads_in_pads_in_payload_data_oe[0:0] 1'0
sync always
update \main_sdphy_cmdr_pads_in_pads_in_payload_data_oe $0\main_sdphy_cmdr_pads_in_pads_in_payload_data_oe[0:0]
sync init
end
- attribute \src "ls180.v:1147.5-1147.48"
- process $proc$ls180.v:1147$3217
+ attribute \src "ls180.v:1143.5-1143.48"
+ process $proc$ls180.v:1143$3217
assign { } { }
assign $1\main_sdphy_cmdr_pads_out_payload_clk[0:0] 1'0
sync always
sync init
update \main_sdphy_cmdr_pads_out_payload_clk $1\main_sdphy_cmdr_pads_out_payload_clk[0:0]
end
- attribute \src "ls180.v:1148.5-1148.50"
- process $proc$ls180.v:1148$3218
+ attribute \src "ls180.v:1144.5-1144.50"
+ process $proc$ls180.v:1144$3218
assign { } { }
assign $1\main_sdphy_cmdr_pads_out_payload_cmd_o[0:0] 1'0
sync always
sync init
update \main_sdphy_cmdr_pads_out_payload_cmd_o $1\main_sdphy_cmdr_pads_out_payload_cmd_o[0:0]
end
- attribute \src "ls180.v:1149.5-1149.51"
- process $proc$ls180.v:1149$3219
+ attribute \src "ls180.v:1145.5-1145.51"
+ process $proc$ls180.v:1145$3219
assign { } { }
assign $1\main_sdphy_cmdr_pads_out_payload_cmd_oe[0:0] 1'0
sync always
sync init
update \main_sdphy_cmdr_pads_out_payload_cmd_oe $1\main_sdphy_cmdr_pads_out_payload_cmd_oe[0:0]
end
- attribute \src "ls180.v:1150.11-1150.57"
- process $proc$ls180.v:1150$3220
+ attribute \src "ls180.v:1146.11-1146.57"
+ process $proc$ls180.v:1146$3220
assign { } { }
assign $0\main_sdphy_cmdr_pads_out_payload_data_o[3:0] 4'0000
sync always
update \main_sdphy_cmdr_pads_out_payload_data_o $0\main_sdphy_cmdr_pads_out_payload_data_o[3:0]
sync init
end
- attribute \src "ls180.v:1151.5-1151.52"
- process $proc$ls180.v:1151$3221
+ attribute \src "ls180.v:1147.5-1147.52"
+ process $proc$ls180.v:1147$3221
assign { } { }
assign $0\main_sdphy_cmdr_pads_out_payload_data_oe[0:0] 1'0
sync always
update \main_sdphy_cmdr_pads_out_payload_data_oe $0\main_sdphy_cmdr_pads_out_payload_data_oe[0:0]
sync init
end
- attribute \src "ls180.v:1152.5-1152.38"
- process $proc$ls180.v:1152$3222
+ attribute \src "ls180.v:1148.5-1148.38"
+ process $proc$ls180.v:1148$3222
assign { } { }
assign $1\main_sdphy_cmdr_sink_valid[0:0] 1'0
sync always
sync init
update \main_sdphy_cmdr_sink_valid $1\main_sdphy_cmdr_sink_valid[0:0]
end
- attribute \src "ls180.v:1153.5-1153.38"
- process $proc$ls180.v:1153$3223
+ attribute \src "ls180.v:1149.5-1149.38"
+ process $proc$ls180.v:1149$3223
assign { } { }
assign $1\main_sdphy_cmdr_sink_ready[0:0] 1'0
sync always
sync init
update \main_sdphy_cmdr_sink_ready $1\main_sdphy_cmdr_sink_ready[0:0]
end
- attribute \src "ls180.v:1154.5-1154.37"
- process $proc$ls180.v:1154$3224
+ attribute \src "ls180.v:1150.5-1150.37"
+ process $proc$ls180.v:1150$3224
assign { } { }
assign $1\main_sdphy_cmdr_sink_last[0:0] 1'0
sync always
sync init
update \main_sdphy_cmdr_sink_last $1\main_sdphy_cmdr_sink_last[0:0]
end
- attribute \src "ls180.v:1155.11-1155.53"
- process $proc$ls180.v:1155$3225
+ attribute \src "ls180.v:1151.11-1151.53"
+ process $proc$ls180.v:1151$3225
assign { } { }
assign $1\main_sdphy_cmdr_sink_payload_length[7:0] 8'00000000
sync always
sync init
update \main_sdphy_cmdr_sink_payload_length $1\main_sdphy_cmdr_sink_payload_length[7:0]
end
- attribute \src "ls180.v:1156.5-1156.40"
- process $proc$ls180.v:1156$3226
+ attribute \src "ls180.v:1152.5-1152.40"
+ process $proc$ls180.v:1152$3226
assign { } { }
assign $1\main_sdphy_cmdr_source_valid[0:0] 1'0
sync always
sync init
update \main_sdphy_cmdr_source_valid $1\main_sdphy_cmdr_source_valid[0:0]
end
- attribute \src "ls180.v:1157.5-1157.40"
- process $proc$ls180.v:1157$3227
+ attribute \src "ls180.v:1153.5-1153.40"
+ process $proc$ls180.v:1153$3227
assign { } { }
assign $1\main_sdphy_cmdr_source_ready[0:0] 1'0
sync always
sync init
update \main_sdphy_cmdr_source_ready $1\main_sdphy_cmdr_source_ready[0:0]
end
- attribute \src "ls180.v:1158.5-1158.39"
- process $proc$ls180.v:1158$3228
+ attribute \src "ls180.v:1154.5-1154.39"
+ process $proc$ls180.v:1154$3228
assign { } { }
assign $1\main_sdphy_cmdr_source_last[0:0] 1'0
sync always
sync init
update \main_sdphy_cmdr_source_last $1\main_sdphy_cmdr_source_last[0:0]
end
- attribute \src "ls180.v:1159.11-1159.53"
- process $proc$ls180.v:1159$3229
+ attribute \src "ls180.v:1155.11-1155.53"
+ process $proc$ls180.v:1155$3229
assign { } { }
assign $1\main_sdphy_cmdr_source_payload_data[7:0] 8'00000000
sync always
sync init
update \main_sdphy_cmdr_source_payload_data $1\main_sdphy_cmdr_source_payload_data[7:0]
end
- attribute \src "ls180.v:116.5-116.49"
- process $proc$ls180.v:116$2773
- assign { } { }
- assign $1\main_libresocsim_libresoc_jtag_wb_ack[0:0] 1'0
- sync always
- sync init
- update \main_libresocsim_libresoc_jtag_wb_ack $1\main_libresocsim_libresoc_jtag_wb_ack[0:0]
- end
- attribute \src "ls180.v:1160.11-1160.55"
- process $proc$ls180.v:1160$3230
+ attribute \src "ls180.v:1156.11-1156.55"
+ process $proc$ls180.v:1156$3230
assign { } { }
assign $1\main_sdphy_cmdr_source_payload_status[2:0] 3'000
sync always
sync init
update \main_sdphy_cmdr_source_payload_status $1\main_sdphy_cmdr_source_payload_status[2:0]
end
- attribute \src "ls180.v:1161.12-1161.48"
- process $proc$ls180.v:1161$3231
+ attribute \src "ls180.v:1157.12-1157.48"
+ process $proc$ls180.v:1157$3231
assign { } { }
assign $1\main_sdphy_cmdr_timeout[31:0] 500000
sync always
sync init
update \main_sdphy_cmdr_timeout $1\main_sdphy_cmdr_timeout[31:0]
end
- attribute \src "ls180.v:1162.11-1162.39"
- process $proc$ls180.v:1162$3232
+ attribute \src "ls180.v:1158.11-1158.39"
+ process $proc$ls180.v:1158$3232
assign { } { }
assign $1\main_sdphy_cmdr_count[7:0] 8'00000000
sync always
sync init
update \main_sdphy_cmdr_count $1\main_sdphy_cmdr_count[7:0]
end
- attribute \src "ls180.v:1164.5-1164.46"
- process $proc$ls180.v:1164$3233
+ attribute \src "ls180.v:1160.5-1160.46"
+ process $proc$ls180.v:1160$3233
assign { } { }
assign $0\main_sdphy_cmdr_cmdr_pads_in_ready[0:0] 1'0
sync always
update \main_sdphy_cmdr_cmdr_pads_in_ready $0\main_sdphy_cmdr_cmdr_pads_in_ready[0:0]
sync init
end
- attribute \src "ls180.v:1175.5-1175.53"
- process $proc$ls180.v:1175$3234
+ attribute \src "ls180.v:1171.5-1171.53"
+ process $proc$ls180.v:1171$3234
assign { } { }
assign $1\main_sdphy_cmdr_cmdr_source_source_ready0[0:0] 1'0
sync always
sync init
update \main_sdphy_cmdr_cmdr_source_source_ready0 $1\main_sdphy_cmdr_cmdr_source_source_ready0[0:0]
end
- attribute \src "ls180.v:118.5-118.49"
- process $proc$ls180.v:118$2774
- assign { } { }
- assign $0\main_libresocsim_libresoc_jtag_wb_err[0:0] 1'0
- sync always
- update \main_libresocsim_libresoc_jtag_wb_err $0\main_libresocsim_libresoc_jtag_wb_err[0:0]
- sync init
- end
- attribute \src "ls180.v:1180.5-1180.36"
- process $proc$ls180.v:1180$3235
+ attribute \src "ls180.v:1176.5-1176.36"
+ process $proc$ls180.v:1176$3235
assign { } { }
assign $1\main_sdphy_cmdr_cmdr_run[0:0] 1'0
sync always
sync init
update \main_sdphy_cmdr_cmdr_run $1\main_sdphy_cmdr_cmdr_run[0:0]
end
- attribute \src "ls180.v:1183.5-1183.53"
- process $proc$ls180.v:1183$3236
+ attribute \src "ls180.v:1179.5-1179.53"
+ process $proc$ls180.v:1179$3236
assign { } { }
assign $0\main_sdphy_cmdr_cmdr_converter_sink_first[0:0] 1'0
sync always
update \main_sdphy_cmdr_cmdr_converter_sink_first $0\main_sdphy_cmdr_cmdr_converter_sink_first[0:0]
sync init
end
- attribute \src "ls180.v:1184.5-1184.52"
- process $proc$ls180.v:1184$3237
+ attribute \src "ls180.v:1180.5-1180.52"
+ process $proc$ls180.v:1180$3237
assign { } { }
assign $0\main_sdphy_cmdr_cmdr_converter_sink_last[0:0] 1'0
sync always
update \main_sdphy_cmdr_cmdr_converter_sink_last $0\main_sdphy_cmdr_cmdr_converter_sink_last[0:0]
sync init
end
- attribute \src "ls180.v:1188.5-1188.55"
- process $proc$ls180.v:1188$3238
+ attribute \src "ls180.v:1184.5-1184.55"
+ process $proc$ls180.v:1184$3238
assign { } { }
assign $1\main_sdphy_cmdr_cmdr_converter_source_first[0:0] 1'0
sync always
sync init
update \main_sdphy_cmdr_cmdr_converter_source_first $1\main_sdphy_cmdr_cmdr_converter_source_first[0:0]
end
- attribute \src "ls180.v:1189.5-1189.54"
- process $proc$ls180.v:1189$3239
+ attribute \src "ls180.v:1185.5-1185.54"
+ process $proc$ls180.v:1185$3239
assign { } { }
assign $1\main_sdphy_cmdr_cmdr_converter_source_last[0:0] 1'0
sync always
sync init
update \main_sdphy_cmdr_cmdr_converter_source_last $1\main_sdphy_cmdr_cmdr_converter_source_last[0:0]
end
- attribute \src "ls180.v:1190.11-1190.68"
- process $proc$ls180.v:1190$3240
+ attribute \src "ls180.v:1186.11-1186.68"
+ process $proc$ls180.v:1186$3240
assign { } { }
assign $1\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] 8'00000000
sync always
sync init
update \main_sdphy_cmdr_cmdr_converter_source_payload_data $1\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0]
end
- attribute \src "ls180.v:1191.11-1191.81"
- process $proc$ls180.v:1191$3241
+ attribute \src "ls180.v:1187.11-1187.81"
+ process $proc$ls180.v:1187$3241
assign { } { }
assign $1\main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count[3:0] 4'0000
sync always
sync init
update \main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count $1\main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count[3:0]
end
- attribute \src "ls180.v:1192.11-1192.54"
- process $proc$ls180.v:1192$3242
+ attribute \src "ls180.v:1188.11-1188.54"
+ process $proc$ls180.v:1188$3242
assign { } { }
assign $1\main_sdphy_cmdr_cmdr_converter_demux[2:0] 3'000
sync always
sync init
update \main_sdphy_cmdr_cmdr_converter_demux $1\main_sdphy_cmdr_cmdr_converter_demux[2:0]
end
- attribute \src "ls180.v:1194.5-1194.53"
- process $proc$ls180.v:1194$3243
+ attribute \src "ls180.v:1190.5-1190.53"
+ process $proc$ls180.v:1190$3243
assign { } { }
assign $1\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] 1'0
sync always
sync init
update \main_sdphy_cmdr_cmdr_converter_strobe_all $1\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0]
end
- attribute \src "ls180.v:1205.5-1205.49"
- process $proc$ls180.v:1205$3244
+ attribute \src "ls180.v:1201.5-1201.49"
+ process $proc$ls180.v:1201$3244
assign { } { }
assign $1\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] 1'0
sync always
sync init
update \main_sdphy_cmdr_cmdr_buf_source_valid $1\main_sdphy_cmdr_cmdr_buf_source_valid[0:0]
end
- attribute \src "ls180.v:1207.5-1207.49"
- process $proc$ls180.v:1207$3245
+ attribute \src "ls180.v:1203.5-1203.49"
+ process $proc$ls180.v:1203$3245
assign { } { }
assign $1\main_sdphy_cmdr_cmdr_buf_source_first[0:0] 1'0
sync always
sync init
update \main_sdphy_cmdr_cmdr_buf_source_first $1\main_sdphy_cmdr_cmdr_buf_source_first[0:0]
end
- attribute \src "ls180.v:1208.5-1208.48"
- process $proc$ls180.v:1208$3246
+ attribute \src "ls180.v:1204.5-1204.48"
+ process $proc$ls180.v:1204$3246
assign { } { }
assign $1\main_sdphy_cmdr_cmdr_buf_source_last[0:0] 1'0
sync always
sync init
update \main_sdphy_cmdr_cmdr_buf_source_last $1\main_sdphy_cmdr_cmdr_buf_source_last[0:0]
end
- attribute \src "ls180.v:1209.11-1209.62"
- process $proc$ls180.v:1209$3247
+ attribute \src "ls180.v:1205.11-1205.62"
+ process $proc$ls180.v:1205$3247
assign { } { }
assign $1\main_sdphy_cmdr_cmdr_buf_source_payload_data[7:0] 8'00000000
sync always
sync init
update \main_sdphy_cmdr_cmdr_buf_source_payload_data $1\main_sdphy_cmdr_cmdr_buf_source_payload_data[7:0]
end
- attribute \src "ls180.v:1210.5-1210.38"
- process $proc$ls180.v:1210$3248
+ attribute \src "ls180.v:1206.5-1206.38"
+ process $proc$ls180.v:1206$3248
assign { } { }
assign $1\main_sdphy_cmdr_cmdr_reset[0:0] 1'0
sync always
sync init
update \main_sdphy_cmdr_cmdr_reset $1\main_sdphy_cmdr_cmdr_reset[0:0]
end
- attribute \src "ls180.v:1215.5-1215.49"
- process $proc$ls180.v:1215$3249
+ attribute \src "ls180.v:1211.5-1211.49"
+ process $proc$ls180.v:1211$3249
assign { } { }
assign $1\main_sdphy_dataw_pads_out_payload_clk[0:0] 1'0
sync always
sync init
update \main_sdphy_dataw_pads_out_payload_clk $1\main_sdphy_dataw_pads_out_payload_clk[0:0]
end
- attribute \src "ls180.v:1216.5-1216.51"
- process $proc$ls180.v:1216$3250
+ attribute \src "ls180.v:1212.5-1212.51"
+ process $proc$ls180.v:1212$3250
assign { } { }
assign $0\main_sdphy_dataw_pads_out_payload_cmd_o[0:0] 1'0
sync always
update \main_sdphy_dataw_pads_out_payload_cmd_o $0\main_sdphy_dataw_pads_out_payload_cmd_o[0:0]
sync init
end
- attribute \src "ls180.v:1217.5-1217.52"
- process $proc$ls180.v:1217$3251
+ attribute \src "ls180.v:1213.5-1213.52"
+ process $proc$ls180.v:1213$3251
assign { } { }
assign $0\main_sdphy_dataw_pads_out_payload_cmd_oe[0:0] 1'0
sync always
update \main_sdphy_dataw_pads_out_payload_cmd_oe $0\main_sdphy_dataw_pads_out_payload_cmd_oe[0:0]
sync init
end
- attribute \src "ls180.v:1218.11-1218.58"
- process $proc$ls180.v:1218$3252
+ attribute \src "ls180.v:1214.11-1214.58"
+ process $proc$ls180.v:1214$3252
assign { } { }
assign $1\main_sdphy_dataw_pads_out_payload_data_o[3:0] 4'0000
sync always
sync init
update \main_sdphy_dataw_pads_out_payload_data_o $1\main_sdphy_dataw_pads_out_payload_data_o[3:0]
end
- attribute \src "ls180.v:1219.5-1219.53"
- process $proc$ls180.v:1219$3253
+ attribute \src "ls180.v:1215.5-1215.53"
+ process $proc$ls180.v:1215$3253
assign { } { }
assign $1\main_sdphy_dataw_pads_out_payload_data_oe[0:0] 1'0
sync always
sync init
update \main_sdphy_dataw_pads_out_payload_data_oe $1\main_sdphy_dataw_pads_out_payload_data_oe[0:0]
end
- attribute \src "ls180.v:1220.5-1220.39"
- process $proc$ls180.v:1220$3254
+ attribute \src "ls180.v:1216.5-1216.39"
+ process $proc$ls180.v:1216$3254
assign { } { }
assign $1\main_sdphy_dataw_sink_valid[0:0] 1'0
sync always
sync init
update \main_sdphy_dataw_sink_valid $1\main_sdphy_dataw_sink_valid[0:0]
end
- attribute \src "ls180.v:1221.5-1221.39"
- process $proc$ls180.v:1221$3255
+ attribute \src "ls180.v:1217.5-1217.39"
+ process $proc$ls180.v:1217$3255
assign { } { }
assign $1\main_sdphy_dataw_sink_ready[0:0] 1'0
sync always
sync init
update \main_sdphy_dataw_sink_ready $1\main_sdphy_dataw_sink_ready[0:0]
end
- attribute \src "ls180.v:1222.5-1222.39"
- process $proc$ls180.v:1222$3256
+ attribute \src "ls180.v:1218.5-1218.39"
+ process $proc$ls180.v:1218$3256
assign { } { }
assign $1\main_sdphy_dataw_sink_first[0:0] 1'0
sync always
sync init
update \main_sdphy_dataw_sink_first $1\main_sdphy_dataw_sink_first[0:0]
end
- attribute \src "ls180.v:1223.5-1223.38"
- process $proc$ls180.v:1223$3257
+ attribute \src "ls180.v:1219.5-1219.38"
+ process $proc$ls180.v:1219$3257
assign { } { }
assign $1\main_sdphy_dataw_sink_last[0:0] 1'0
sync always
sync init
update \main_sdphy_dataw_sink_last $1\main_sdphy_dataw_sink_last[0:0]
end
- attribute \src "ls180.v:1224.11-1224.52"
- process $proc$ls180.v:1224$3258
+ attribute \src "ls180.v:1220.11-1220.52"
+ process $proc$ls180.v:1220$3258
assign { } { }
assign $1\main_sdphy_dataw_sink_payload_data[7:0] 8'00000000
sync always
sync init
update \main_sdphy_dataw_sink_payload_data $1\main_sdphy_dataw_sink_payload_data[7:0]
end
- attribute \src "ls180.v:1225.5-1225.33"
- process $proc$ls180.v:1225$3259
+ attribute \src "ls180.v:1221.5-1221.33"
+ process $proc$ls180.v:1221$3259
assign { } { }
assign $1\main_sdphy_dataw_stop[0:0] 1'0
sync always
sync init
update \main_sdphy_dataw_stop $1\main_sdphy_dataw_stop[0:0]
end
- attribute \src "ls180.v:1226.11-1226.40"
- process $proc$ls180.v:1226$3260
+ attribute \src "ls180.v:1222.11-1222.40"
+ process $proc$ls180.v:1222$3260
assign { } { }
assign $1\main_sdphy_dataw_count[7:0] 8'00000000
sync always
sync init
update \main_sdphy_dataw_count $1\main_sdphy_dataw_count[7:0]
end
- attribute \src "ls180.v:1227.5-1227.50"
- process $proc$ls180.v:1227$3261
+ attribute \src "ls180.v:1223.5-1223.50"
+ process $proc$ls180.v:1223$3261
assign { } { }
assign $0\main_sdphy_dataw_pads_in_pads_in_valid[0:0] 1'0
sync always
update \main_sdphy_dataw_pads_in_pads_in_valid $0\main_sdphy_dataw_pads_in_pads_in_valid[0:0]
sync init
end
- attribute \src "ls180.v:1229.5-1229.50"
- process $proc$ls180.v:1229$3262
+ attribute \src "ls180.v:1225.5-1225.50"
+ process $proc$ls180.v:1225$3262
assign { } { }
assign $0\main_sdphy_dataw_pads_in_pads_in_first[0:0] 1'0
sync always
update \main_sdphy_dataw_pads_in_pads_in_first $0\main_sdphy_dataw_pads_in_pads_in_first[0:0]
sync init
end
- attribute \src "ls180.v:1230.5-1230.49"
- process $proc$ls180.v:1230$3263
+ attribute \src "ls180.v:1226.5-1226.49"
+ process $proc$ls180.v:1226$3263
assign { } { }
assign $0\main_sdphy_dataw_pads_in_pads_in_last[0:0] 1'0
sync always
update \main_sdphy_dataw_pads_in_pads_in_last $0\main_sdphy_dataw_pads_in_pads_in_last[0:0]
sync init
end
- attribute \src "ls180.v:1231.5-1231.56"
- process $proc$ls180.v:1231$3264
+ attribute \src "ls180.v:1227.5-1227.56"
+ process $proc$ls180.v:1227$3264
assign { } { }
assign $0\main_sdphy_dataw_pads_in_pads_in_payload_clk[0:0] 1'0
sync always
update \main_sdphy_dataw_pads_in_pads_in_payload_clk $0\main_sdphy_dataw_pads_in_pads_in_payload_clk[0:0]
sync init
end
- attribute \src "ls180.v:1232.5-1232.58"
- process $proc$ls180.v:1232$3265
+ attribute \src "ls180.v:1228.5-1228.58"
+ process $proc$ls180.v:1228$3265
assign { } { }
assign $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_i[0:0] 1'0
sync always
update \main_sdphy_dataw_pads_in_pads_in_payload_cmd_i $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_i[0:0]
sync init
end
- attribute \src "ls180.v:1233.5-1233.58"
- process $proc$ls180.v:1233$3266
+ attribute \src "ls180.v:1229.5-1229.58"
+ process $proc$ls180.v:1229$3266
assign { } { }
assign $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_o[0:0] 1'0
sync always
update \main_sdphy_dataw_pads_in_pads_in_payload_cmd_o $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_o[0:0]
sync init
end
- attribute \src "ls180.v:1234.5-1234.59"
- process $proc$ls180.v:1234$3267
+ attribute \src "ls180.v:1230.5-1230.59"
+ process $proc$ls180.v:1230$3267
assign { } { }
assign $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_oe[0:0] 1'0
sync always
update \main_sdphy_dataw_pads_in_pads_in_payload_cmd_oe $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_oe[0:0]
sync init
end
- attribute \src "ls180.v:1235.11-1235.65"
- process $proc$ls180.v:1235$3268
+ attribute \src "ls180.v:1231.11-1231.65"
+ process $proc$ls180.v:1231$3268
assign { } { }
assign $0\main_sdphy_dataw_pads_in_pads_in_payload_data_i[3:0] 4'0000
sync always
update \main_sdphy_dataw_pads_in_pads_in_payload_data_i $0\main_sdphy_dataw_pads_in_pads_in_payload_data_i[3:0]
sync init
end
- attribute \src "ls180.v:1236.11-1236.65"
- process $proc$ls180.v:1236$3269
+ attribute \src "ls180.v:1232.11-1232.65"
+ process $proc$ls180.v:1232$3269
assign { } { }
assign $0\main_sdphy_dataw_pads_in_pads_in_payload_data_o[3:0] 4'0000
sync always
update \main_sdphy_dataw_pads_in_pads_in_payload_data_o $0\main_sdphy_dataw_pads_in_pads_in_payload_data_o[3:0]
sync init
end
- attribute \src "ls180.v:1237.5-1237.60"
- process $proc$ls180.v:1237$3270
+ attribute \src "ls180.v:1233.5-1233.60"
+ process $proc$ls180.v:1233$3270
assign { } { }
assign $0\main_sdphy_dataw_pads_in_pads_in_payload_data_oe[0:0] 1'0
sync always
update \main_sdphy_dataw_pads_in_pads_in_payload_data_oe $0\main_sdphy_dataw_pads_in_pads_in_payload_data_oe[0:0]
sync init
end
- attribute \src "ls180.v:1238.5-1238.34"
- process $proc$ls180.v:1238$3271
+ attribute \src "ls180.v:1234.5-1234.34"
+ process $proc$ls180.v:1234$3271
assign { } { }
assign $1\main_sdphy_dataw_start[0:0] 1'0
sync always
sync init
update \main_sdphy_dataw_start $1\main_sdphy_dataw_start[0:0]
end
- attribute \src "ls180.v:1239.5-1239.34"
- process $proc$ls180.v:1239$3272
+ attribute \src "ls180.v:1235.5-1235.34"
+ process $proc$ls180.v:1235$3272
assign { } { }
assign $1\main_sdphy_dataw_valid[0:0] 1'0
sync always
sync init
update \main_sdphy_dataw_valid $1\main_sdphy_dataw_valid[0:0]
end
- attribute \src "ls180.v:1240.5-1240.34"
- process $proc$ls180.v:1240$3273
+ attribute \src "ls180.v:1236.5-1236.34"
+ process $proc$ls180.v:1236$3273
assign { } { }
assign $1\main_sdphy_dataw_error[0:0] 1'0
sync always
sync init
update \main_sdphy_dataw_error $1\main_sdphy_dataw_error[0:0]
end
- attribute \src "ls180.v:1242.5-1242.47"
- process $proc$ls180.v:1242$3274
+ attribute \src "ls180.v:1238.5-1238.47"
+ process $proc$ls180.v:1238$3274
assign { } { }
assign $0\main_sdphy_dataw_crcr_pads_in_ready[0:0] 1'0
sync always
update \main_sdphy_dataw_crcr_pads_in_ready $0\main_sdphy_dataw_crcr_pads_in_ready[0:0]
sync init
end
- attribute \src "ls180.v:1253.5-1253.54"
- process $proc$ls180.v:1253$3275
+ attribute \src "ls180.v:1249.5-1249.54"
+ process $proc$ls180.v:1249$3275
assign { } { }
assign $1\main_sdphy_dataw_crcr_source_source_ready0[0:0] 1'0
sync always
sync init
update \main_sdphy_dataw_crcr_source_source_ready0 $1\main_sdphy_dataw_crcr_source_source_ready0[0:0]
end
- attribute \src "ls180.v:1258.5-1258.37"
- process $proc$ls180.v:1258$3276
+ attribute \src "ls180.v:1254.5-1254.37"
+ process $proc$ls180.v:1254$3276
assign { } { }
assign $1\main_sdphy_dataw_crcr_run[0:0] 1'0
sync always
sync init
update \main_sdphy_dataw_crcr_run $1\main_sdphy_dataw_crcr_run[0:0]
end
- attribute \src "ls180.v:1261.5-1261.54"
- process $proc$ls180.v:1261$3277
+ attribute \src "ls180.v:1257.5-1257.54"
+ process $proc$ls180.v:1257$3277
assign { } { }
assign $0\main_sdphy_dataw_crcr_converter_sink_first[0:0] 1'0
sync always
update \main_sdphy_dataw_crcr_converter_sink_first $0\main_sdphy_dataw_crcr_converter_sink_first[0:0]
sync init
end
- attribute \src "ls180.v:1262.5-1262.53"
- process $proc$ls180.v:1262$3278
+ attribute \src "ls180.v:1258.5-1258.53"
+ process $proc$ls180.v:1258$3278
assign { } { }
assign $0\main_sdphy_dataw_crcr_converter_sink_last[0:0] 1'0
sync always
update \main_sdphy_dataw_crcr_converter_sink_last $0\main_sdphy_dataw_crcr_converter_sink_last[0:0]
sync init
end
- attribute \src "ls180.v:1266.5-1266.56"
- process $proc$ls180.v:1266$3279
+ attribute \src "ls180.v:1262.5-1262.56"
+ process $proc$ls180.v:1262$3279
assign { } { }
assign $1\main_sdphy_dataw_crcr_converter_source_first[0:0] 1'0
sync always
sync init
update \main_sdphy_dataw_crcr_converter_source_first $1\main_sdphy_dataw_crcr_converter_source_first[0:0]
end
- attribute \src "ls180.v:1267.5-1267.55"
- process $proc$ls180.v:1267$3280
+ attribute \src "ls180.v:1263.5-1263.55"
+ process $proc$ls180.v:1263$3280
assign { } { }
assign $1\main_sdphy_dataw_crcr_converter_source_last[0:0] 1'0
sync always
sync init
update \main_sdphy_dataw_crcr_converter_source_last $1\main_sdphy_dataw_crcr_converter_source_last[0:0]
end
- attribute \src "ls180.v:1268.11-1268.69"
- process $proc$ls180.v:1268$3281
+ attribute \src "ls180.v:1264.11-1264.69"
+ process $proc$ls180.v:1264$3281
assign { } { }
assign $1\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] 8'00000000
sync always
sync init
update \main_sdphy_dataw_crcr_converter_source_payload_data $1\main_sdphy_dataw_crcr_converter_source_payload_data[7:0]
end
- attribute \src "ls180.v:1269.11-1269.82"
- process $proc$ls180.v:1269$3282
+ attribute \src "ls180.v:1265.11-1265.82"
+ process $proc$ls180.v:1265$3282
assign { } { }
assign $1\main_sdphy_dataw_crcr_converter_source_payload_valid_token_count[3:0] 4'0000
sync always
sync init
update \main_sdphy_dataw_crcr_converter_source_payload_valid_token_count $1\main_sdphy_dataw_crcr_converter_source_payload_valid_token_count[3:0]
end
- attribute \src "ls180.v:1270.11-1270.55"
- process $proc$ls180.v:1270$3283
+ attribute \src "ls180.v:1266.11-1266.55"
+ process $proc$ls180.v:1266$3283
assign { } { }
assign $1\main_sdphy_dataw_crcr_converter_demux[2:0] 3'000
sync always
sync init
update \main_sdphy_dataw_crcr_converter_demux $1\main_sdphy_dataw_crcr_converter_demux[2:0]
end
- attribute \src "ls180.v:1272.5-1272.54"
- process $proc$ls180.v:1272$3284
+ attribute \src "ls180.v:1268.5-1268.54"
+ process $proc$ls180.v:1268$3284
assign { } { }
assign $1\main_sdphy_dataw_crcr_converter_strobe_all[0:0] 1'0
sync always
sync init
update \main_sdphy_dataw_crcr_converter_strobe_all $1\main_sdphy_dataw_crcr_converter_strobe_all[0:0]
end
- attribute \src "ls180.v:1283.5-1283.50"
- process $proc$ls180.v:1283$3285
+ attribute \src "ls180.v:1279.5-1279.50"
+ process $proc$ls180.v:1279$3285
assign { } { }
assign $1\main_sdphy_dataw_crcr_buf_source_valid[0:0] 1'0
sync always
sync init
update \main_sdphy_dataw_crcr_buf_source_valid $1\main_sdphy_dataw_crcr_buf_source_valid[0:0]
end
- attribute \src "ls180.v:1285.5-1285.50"
- process $proc$ls180.v:1285$3286
+ attribute \src "ls180.v:1281.5-1281.50"
+ process $proc$ls180.v:1281$3286
assign { } { }
assign $1\main_sdphy_dataw_crcr_buf_source_first[0:0] 1'0
sync always
sync init
update \main_sdphy_dataw_crcr_buf_source_first $1\main_sdphy_dataw_crcr_buf_source_first[0:0]
end
- attribute \src "ls180.v:1286.5-1286.49"
- process $proc$ls180.v:1286$3287
+ attribute \src "ls180.v:1282.5-1282.49"
+ process $proc$ls180.v:1282$3287
assign { } { }
assign $1\main_sdphy_dataw_crcr_buf_source_last[0:0] 1'0
sync always
sync init
update \main_sdphy_dataw_crcr_buf_source_last $1\main_sdphy_dataw_crcr_buf_source_last[0:0]
end
- attribute \src "ls180.v:1287.11-1287.63"
- process $proc$ls180.v:1287$3288
+ attribute \src "ls180.v:1283.11-1283.63"
+ process $proc$ls180.v:1283$3288
assign { } { }
assign $1\main_sdphy_dataw_crcr_buf_source_payload_data[7:0] 8'00000000
sync always
sync init
update \main_sdphy_dataw_crcr_buf_source_payload_data $1\main_sdphy_dataw_crcr_buf_source_payload_data[7:0]
end
- attribute \src "ls180.v:1288.5-1288.39"
- process $proc$ls180.v:1288$3289
+ attribute \src "ls180.v:1284.5-1284.39"
+ process $proc$ls180.v:1284$3289
assign { } { }
assign $1\main_sdphy_dataw_crcr_reset[0:0] 1'0
sync always
sync init
update \main_sdphy_dataw_crcr_reset $1\main_sdphy_dataw_crcr_reset[0:0]
end
- attribute \src "ls180.v:1291.5-1291.50"
- process $proc$ls180.v:1291$3290
+ attribute \src "ls180.v:1287.5-1287.50"
+ process $proc$ls180.v:1287$3290
assign { } { }
assign $0\main_sdphy_datar_pads_in_pads_in_first[0:0] 1'0
sync always
update \main_sdphy_datar_pads_in_pads_in_first $0\main_sdphy_datar_pads_in_pads_in_first[0:0]
sync init
end
- attribute \src "ls180.v:1292.5-1292.49"
- process $proc$ls180.v:1292$3291
+ attribute \src "ls180.v:1288.5-1288.49"
+ process $proc$ls180.v:1288$3291
assign { } { }
assign $0\main_sdphy_datar_pads_in_pads_in_last[0:0] 1'0
sync always
update \main_sdphy_datar_pads_in_pads_in_last $0\main_sdphy_datar_pads_in_pads_in_last[0:0]
sync init
end
- attribute \src "ls180.v:1293.5-1293.56"
- process $proc$ls180.v:1293$3292
+ attribute \src "ls180.v:1289.5-1289.56"
+ process $proc$ls180.v:1289$3292
assign { } { }
assign $0\main_sdphy_datar_pads_in_pads_in_payload_clk[0:0] 1'0
sync always
update \main_sdphy_datar_pads_in_pads_in_payload_clk $0\main_sdphy_datar_pads_in_pads_in_payload_clk[0:0]
sync init
end
- attribute \src "ls180.v:1295.5-1295.58"
- process $proc$ls180.v:1295$3293
+ attribute \src "ls180.v:1291.5-1291.58"
+ process $proc$ls180.v:1291$3293
assign { } { }
assign $0\main_sdphy_datar_pads_in_pads_in_payload_cmd_o[0:0] 1'0
sync always
update \main_sdphy_datar_pads_in_pads_in_payload_cmd_o $0\main_sdphy_datar_pads_in_pads_in_payload_cmd_o[0:0]
sync init
end
- attribute \src "ls180.v:1296.5-1296.59"
- process $proc$ls180.v:1296$3294
+ attribute \src "ls180.v:1292.5-1292.59"
+ process $proc$ls180.v:1292$3294
assign { } { }
assign $0\main_sdphy_datar_pads_in_pads_in_payload_cmd_oe[0:0] 1'0
sync always
update \main_sdphy_datar_pads_in_pads_in_payload_cmd_oe $0\main_sdphy_datar_pads_in_pads_in_payload_cmd_oe[0:0]
sync init
end
- attribute \src "ls180.v:1298.11-1298.65"
- process $proc$ls180.v:1298$3295
+ attribute \src "ls180.v:1294.11-1294.65"
+ process $proc$ls180.v:1294$3295
assign { } { }
assign $0\main_sdphy_datar_pads_in_pads_in_payload_data_o[3:0] 4'0000
sync always
update \main_sdphy_datar_pads_in_pads_in_payload_data_o $0\main_sdphy_datar_pads_in_pads_in_payload_data_o[3:0]
sync init
end
- attribute \src "ls180.v:1299.5-1299.60"
- process $proc$ls180.v:1299$3296
+ attribute \src "ls180.v:1295.5-1295.60"
+ process $proc$ls180.v:1295$3296
assign { } { }
assign $0\main_sdphy_datar_pads_in_pads_in_payload_data_oe[0:0] 1'0
sync always
update \main_sdphy_datar_pads_in_pads_in_payload_data_oe $0\main_sdphy_datar_pads_in_pads_in_payload_data_oe[0:0]
sync init
end
- attribute \src "ls180.v:1301.5-1301.49"
- process $proc$ls180.v:1301$3297
+ attribute \src "ls180.v:1297.5-1297.49"
+ process $proc$ls180.v:1297$3297
assign { } { }
assign $1\main_sdphy_datar_pads_out_payload_clk[0:0] 1'0
sync always
sync init
update \main_sdphy_datar_pads_out_payload_clk $1\main_sdphy_datar_pads_out_payload_clk[0:0]
end
- attribute \src "ls180.v:1302.5-1302.51"
- process $proc$ls180.v:1302$3298
+ attribute \src "ls180.v:1298.5-1298.51"
+ process $proc$ls180.v:1298$3298
assign { } { }
assign $0\main_sdphy_datar_pads_out_payload_cmd_o[0:0] 1'0
sync always
update \main_sdphy_datar_pads_out_payload_cmd_o $0\main_sdphy_datar_pads_out_payload_cmd_o[0:0]
sync init
end
- attribute \src "ls180.v:1303.5-1303.52"
- process $proc$ls180.v:1303$3299
+ attribute \src "ls180.v:1299.5-1299.52"
+ process $proc$ls180.v:1299$3299
assign { } { }
assign $0\main_sdphy_datar_pads_out_payload_cmd_oe[0:0] 1'0
sync always
update \main_sdphy_datar_pads_out_payload_cmd_oe $0\main_sdphy_datar_pads_out_payload_cmd_oe[0:0]
sync init
end
- attribute \src "ls180.v:1304.11-1304.58"
- process $proc$ls180.v:1304$3300
+ attribute \src "ls180.v:1300.11-1300.58"
+ process $proc$ls180.v:1300$3300
assign { } { }
assign $0\main_sdphy_datar_pads_out_payload_data_o[3:0] 4'0000
sync always
update \main_sdphy_datar_pads_out_payload_data_o $0\main_sdphy_datar_pads_out_payload_data_o[3:0]
sync init
end
- attribute \src "ls180.v:1305.5-1305.53"
- process $proc$ls180.v:1305$3301
+ attribute \src "ls180.v:1301.5-1301.53"
+ process $proc$ls180.v:1301$3301
assign { } { }
assign $0\main_sdphy_datar_pads_out_payload_data_oe[0:0] 1'0
sync always
update \main_sdphy_datar_pads_out_payload_data_oe $0\main_sdphy_datar_pads_out_payload_data_oe[0:0]
sync init
end
- attribute \src "ls180.v:1306.5-1306.39"
- process $proc$ls180.v:1306$3302
+ attribute \src "ls180.v:1302.5-1302.39"
+ process $proc$ls180.v:1302$3302
assign { } { }
assign $1\main_sdphy_datar_sink_valid[0:0] 1'0
sync always
sync init
update \main_sdphy_datar_sink_valid $1\main_sdphy_datar_sink_valid[0:0]
end
- attribute \src "ls180.v:1307.5-1307.39"
- process $proc$ls180.v:1307$3303
+ attribute \src "ls180.v:1303.5-1303.39"
+ process $proc$ls180.v:1303$3303
assign { } { }
assign $1\main_sdphy_datar_sink_ready[0:0] 1'0
sync always
sync init
update \main_sdphy_datar_sink_ready $1\main_sdphy_datar_sink_ready[0:0]
end
- attribute \src "ls180.v:1308.5-1308.38"
- process $proc$ls180.v:1308$3304
+ attribute \src "ls180.v:1304.5-1304.38"
+ process $proc$ls180.v:1304$3304
assign { } { }
assign $1\main_sdphy_datar_sink_last[0:0] 1'0
sync always
sync init
update \main_sdphy_datar_sink_last $1\main_sdphy_datar_sink_last[0:0]
end
- attribute \src "ls180.v:1309.11-1309.61"
- process $proc$ls180.v:1309$3305
+ attribute \src "ls180.v:1305.11-1305.61"
+ process $proc$ls180.v:1305$3305
assign { } { }
assign $1\main_sdphy_datar_sink_payload_block_length[9:0] 10'0000000000
sync always
sync init
update \main_sdphy_datar_sink_payload_block_length $1\main_sdphy_datar_sink_payload_block_length[9:0]
end
- attribute \src "ls180.v:1310.5-1310.41"
- process $proc$ls180.v:1310$3306
+ attribute \src "ls180.v:1306.5-1306.41"
+ process $proc$ls180.v:1306$3306
assign { } { }
assign $1\main_sdphy_datar_source_valid[0:0] 1'0
sync always
sync init
update \main_sdphy_datar_source_valid $1\main_sdphy_datar_source_valid[0:0]
end
- attribute \src "ls180.v:1311.5-1311.41"
- process $proc$ls180.v:1311$3307
+ attribute \src "ls180.v:1307.5-1307.41"
+ process $proc$ls180.v:1307$3307
assign { } { }
assign $1\main_sdphy_datar_source_ready[0:0] 1'0
sync always
sync init
update \main_sdphy_datar_source_ready $1\main_sdphy_datar_source_ready[0:0]
end
- attribute \src "ls180.v:1312.5-1312.41"
- process $proc$ls180.v:1312$3308
+ attribute \src "ls180.v:1308.5-1308.41"
+ process $proc$ls180.v:1308$3308
assign { } { }
assign $0\main_sdphy_datar_source_first[0:0] 1'0
sync always
update \main_sdphy_datar_source_first $0\main_sdphy_datar_source_first[0:0]
sync init
end
- attribute \src "ls180.v:1313.5-1313.40"
- process $proc$ls180.v:1313$3309
+ attribute \src "ls180.v:1309.5-1309.40"
+ process $proc$ls180.v:1309$3309
assign { } { }
assign $1\main_sdphy_datar_source_last[0:0] 1'0
sync always
sync init
update \main_sdphy_datar_source_last $1\main_sdphy_datar_source_last[0:0]
end
- attribute \src "ls180.v:1314.11-1314.54"
- process $proc$ls180.v:1314$3310
+ attribute \src "ls180.v:1310.11-1310.54"
+ process $proc$ls180.v:1310$3310
assign { } { }
assign $1\main_sdphy_datar_source_payload_data[7:0] 8'00000000
sync always
sync init
update \main_sdphy_datar_source_payload_data $1\main_sdphy_datar_source_payload_data[7:0]
end
- attribute \src "ls180.v:1315.11-1315.56"
- process $proc$ls180.v:1315$3311
+ attribute \src "ls180.v:1311.11-1311.56"
+ process $proc$ls180.v:1311$3311
assign { } { }
assign $1\main_sdphy_datar_source_payload_status[2:0] 3'000
sync always
sync init
update \main_sdphy_datar_source_payload_status $1\main_sdphy_datar_source_payload_status[2:0]
end
- attribute \src "ls180.v:1316.5-1316.33"
- process $proc$ls180.v:1316$3312
+ attribute \src "ls180.v:1312.5-1312.33"
+ process $proc$ls180.v:1312$3312
assign { } { }
assign $1\main_sdphy_datar_stop[0:0] 1'0
sync always
sync init
update \main_sdphy_datar_stop $1\main_sdphy_datar_stop[0:0]
end
- attribute \src "ls180.v:1317.12-1317.49"
- process $proc$ls180.v:1317$3313
+ attribute \src "ls180.v:1313.12-1313.49"
+ process $proc$ls180.v:1313$3313
assign { } { }
assign $1\main_sdphy_datar_timeout[31:0] 500000
sync always
sync init
update \main_sdphy_datar_timeout $1\main_sdphy_datar_timeout[31:0]
end
- attribute \src "ls180.v:1318.11-1318.41"
- process $proc$ls180.v:1318$3314
+ attribute \src "ls180.v:1314.11-1314.41"
+ process $proc$ls180.v:1314$3314
assign { } { }
assign $1\main_sdphy_datar_count[9:0] 10'0000000000
sync always
sync init
update \main_sdphy_datar_count $1\main_sdphy_datar_count[9:0]
end
- attribute \src "ls180.v:1320.5-1320.48"
- process $proc$ls180.v:1320$3315
+ attribute \src "ls180.v:1316.5-1316.48"
+ process $proc$ls180.v:1316$3315
assign { } { }
assign $0\main_sdphy_datar_datar_pads_in_ready[0:0] 1'0
sync always
update \main_sdphy_datar_datar_pads_in_ready $0\main_sdphy_datar_datar_pads_in_ready[0:0]
sync init
end
- attribute \src "ls180.v:1331.5-1331.55"
- process $proc$ls180.v:1331$3316
+ attribute \src "ls180.v:1327.5-1327.55"
+ process $proc$ls180.v:1327$3316
assign { } { }
assign $1\main_sdphy_datar_datar_source_source_ready0[0:0] 1'0
sync always
sync init
update \main_sdphy_datar_datar_source_source_ready0 $1\main_sdphy_datar_datar_source_source_ready0[0:0]
end
- attribute \src "ls180.v:1336.5-1336.38"
- process $proc$ls180.v:1336$3317
+ attribute \src "ls180.v:1332.5-1332.38"
+ process $proc$ls180.v:1332$3317
assign { } { }
assign $1\main_sdphy_datar_datar_run[0:0] 1'0
sync always
sync init
update \main_sdphy_datar_datar_run $1\main_sdphy_datar_datar_run[0:0]
end
- attribute \src "ls180.v:1339.5-1339.55"
- process $proc$ls180.v:1339$3318
+ attribute \src "ls180.v:1335.5-1335.55"
+ process $proc$ls180.v:1335$3318
assign { } { }
assign $0\main_sdphy_datar_datar_converter_sink_first[0:0] 1'0
sync always
update \main_sdphy_datar_datar_converter_sink_first $0\main_sdphy_datar_datar_converter_sink_first[0:0]
sync init
end
- attribute \src "ls180.v:1340.5-1340.54"
- process $proc$ls180.v:1340$3319
+ attribute \src "ls180.v:1336.5-1336.54"
+ process $proc$ls180.v:1336$3319
assign { } { }
assign $0\main_sdphy_datar_datar_converter_sink_last[0:0] 1'0
sync always
update \main_sdphy_datar_datar_converter_sink_last $0\main_sdphy_datar_datar_converter_sink_last[0:0]
sync init
end
- attribute \src "ls180.v:1344.5-1344.57"
- process $proc$ls180.v:1344$3320
+ attribute \src "ls180.v:1340.5-1340.57"
+ process $proc$ls180.v:1340$3320
assign { } { }
assign $1\main_sdphy_datar_datar_converter_source_first[0:0] 1'0
sync always
sync init
update \main_sdphy_datar_datar_converter_source_first $1\main_sdphy_datar_datar_converter_source_first[0:0]
end
- attribute \src "ls180.v:1345.5-1345.56"
- process $proc$ls180.v:1345$3321
+ attribute \src "ls180.v:1341.5-1341.56"
+ process $proc$ls180.v:1341$3321
assign { } { }
assign $1\main_sdphy_datar_datar_converter_source_last[0:0] 1'0
sync always
sync init
update \main_sdphy_datar_datar_converter_source_last $1\main_sdphy_datar_datar_converter_source_last[0:0]
end
- attribute \src "ls180.v:1346.11-1346.70"
- process $proc$ls180.v:1346$3322
+ attribute \src "ls180.v:1342.11-1342.70"
+ process $proc$ls180.v:1342$3322
assign { } { }
assign $1\main_sdphy_datar_datar_converter_source_payload_data[7:0] 8'00000000
sync always
sync init
update \main_sdphy_datar_datar_converter_source_payload_data $1\main_sdphy_datar_datar_converter_source_payload_data[7:0]
end
- attribute \src "ls180.v:1347.11-1347.83"
- process $proc$ls180.v:1347$3323
+ attribute \src "ls180.v:1343.11-1343.83"
+ process $proc$ls180.v:1343$3323
assign { } { }
assign $1\main_sdphy_datar_datar_converter_source_payload_valid_token_count[1:0] 2'00
sync always
sync init
update \main_sdphy_datar_datar_converter_source_payload_valid_token_count $1\main_sdphy_datar_datar_converter_source_payload_valid_token_count[1:0]
end
- attribute \src "ls180.v:1348.5-1348.50"
- process $proc$ls180.v:1348$3324
+ attribute \src "ls180.v:1344.5-1344.50"
+ process $proc$ls180.v:1344$3324
assign { } { }
assign $1\main_sdphy_datar_datar_converter_demux[0:0] 1'0
sync always
sync init
update \main_sdphy_datar_datar_converter_demux $1\main_sdphy_datar_datar_converter_demux[0:0]
end
- attribute \src "ls180.v:1350.5-1350.55"
- process $proc$ls180.v:1350$3325
+ attribute \src "ls180.v:1346.5-1346.55"
+ process $proc$ls180.v:1346$3325
assign { } { }
assign $1\main_sdphy_datar_datar_converter_strobe_all[0:0] 1'0
sync always
sync init
update \main_sdphy_datar_datar_converter_strobe_all $1\main_sdphy_datar_datar_converter_strobe_all[0:0]
end
- attribute \src "ls180.v:1361.5-1361.51"
- process $proc$ls180.v:1361$3326
+ attribute \src "ls180.v:1357.5-1357.51"
+ process $proc$ls180.v:1357$3326
assign { } { }
assign $1\main_sdphy_datar_datar_buf_source_valid[0:0] 1'0
sync always
sync init
update \main_sdphy_datar_datar_buf_source_valid $1\main_sdphy_datar_datar_buf_source_valid[0:0]
end
- attribute \src "ls180.v:1363.5-1363.51"
- process $proc$ls180.v:1363$3327
+ attribute \src "ls180.v:1359.5-1359.51"
+ process $proc$ls180.v:1359$3327
assign { } { }
assign $1\main_sdphy_datar_datar_buf_source_first[0:0] 1'0
sync always
sync init
update \main_sdphy_datar_datar_buf_source_first $1\main_sdphy_datar_datar_buf_source_first[0:0]
end
- attribute \src "ls180.v:1364.5-1364.50"
- process $proc$ls180.v:1364$3328
+ attribute \src "ls180.v:1360.5-1360.50"
+ process $proc$ls180.v:1360$3328
assign { } { }
assign $1\main_sdphy_datar_datar_buf_source_last[0:0] 1'0
sync always
sync init
update \main_sdphy_datar_datar_buf_source_last $1\main_sdphy_datar_datar_buf_source_last[0:0]
end
- attribute \src "ls180.v:1365.11-1365.64"
- process $proc$ls180.v:1365$3329
+ attribute \src "ls180.v:1361.11-1361.64"
+ process $proc$ls180.v:1361$3329
assign { } { }
assign $1\main_sdphy_datar_datar_buf_source_payload_data[7:0] 8'00000000
sync always
sync init
update \main_sdphy_datar_datar_buf_source_payload_data $1\main_sdphy_datar_datar_buf_source_payload_data[7:0]
end
- attribute \src "ls180.v:1366.5-1366.40"
- process $proc$ls180.v:1366$3330
+ attribute \src "ls180.v:1362.5-1362.40"
+ process $proc$ls180.v:1362$3330
assign { } { }
assign $1\main_sdphy_datar_datar_reset[0:0] 1'0
sync always
sync init
update \main_sdphy_datar_datar_reset $1\main_sdphy_datar_datar_reset[0:0]
end
- attribute \src "ls180.v:1368.5-1368.35"
- process $proc$ls180.v:1368$3331
+ attribute \src "ls180.v:1364.5-1364.35"
+ process $proc$ls180.v:1364$3331
assign { } { }
assign $1\main_sdphy_sdpads_cmd_i[0:0] 1'0
sync always
sync init
update \main_sdphy_sdpads_cmd_i $1\main_sdphy_sdpads_cmd_i[0:0]
end
- attribute \src "ls180.v:1371.11-1371.42"
- process $proc$ls180.v:1371$3332
+ attribute \src "ls180.v:1367.11-1367.42"
+ process $proc$ls180.v:1367$3332
assign { } { }
assign $1\main_sdphy_sdpads_data_i[3:0] 4'0000
sync always
sync init
update \main_sdphy_sdpads_data_i $1\main_sdphy_sdpads_data_i[3:0]
end
- attribute \src "ls180.v:1384.12-1384.52"
- process $proc$ls180.v:1384$3333
+ attribute \src "ls180.v:1380.12-1380.52"
+ process $proc$ls180.v:1380$3333
assign { } { }
assign $1\main_sdcore_cmd_argument_storage[31:0] 0
sync always
sync init
update \main_sdcore_cmd_argument_storage $1\main_sdcore_cmd_argument_storage[31:0]
end
- attribute \src "ls180.v:1385.5-1385.39"
- process $proc$ls180.v:1385$3334
+ attribute \src "ls180.v:1381.5-1381.39"
+ process $proc$ls180.v:1381$3334
assign { } { }
assign $1\main_sdcore_cmd_argument_re[0:0] 1'0
sync always
sync init
update \main_sdcore_cmd_argument_re $1\main_sdcore_cmd_argument_re[0:0]
end
- attribute \src "ls180.v:1386.12-1386.51"
- process $proc$ls180.v:1386$3335
+ attribute \src "ls180.v:1382.12-1382.51"
+ process $proc$ls180.v:1382$3335
assign { } { }
assign $1\main_sdcore_cmd_command_storage[31:0] 0
sync always
sync init
update \main_sdcore_cmd_command_storage $1\main_sdcore_cmd_command_storage[31:0]
end
- attribute \src "ls180.v:1387.5-1387.38"
- process $proc$ls180.v:1387$3336
+ attribute \src "ls180.v:1383.5-1383.38"
+ process $proc$ls180.v:1383$3336
assign { } { }
assign $1\main_sdcore_cmd_command_re[0:0] 1'0
sync always
sync init
update \main_sdcore_cmd_command_re $1\main_sdcore_cmd_command_re[0:0]
end
- attribute \src "ls180.v:1391.5-1391.34"
- process $proc$ls180.v:1391$3337
+ attribute \src "ls180.v:1387.5-1387.34"
+ process $proc$ls180.v:1387$3337
assign { } { }
assign $0\main_sdcore_cmd_send_w[0:0] 1'0
sync always
update \main_sdcore_cmd_send_w $0\main_sdcore_cmd_send_w[0:0]
sync init
end
- attribute \src "ls180.v:1392.13-1392.53"
- process $proc$ls180.v:1392$3338
+ attribute \src "ls180.v:1388.13-1388.53"
+ process $proc$ls180.v:1388$3338
assign { } { }
assign $1\main_sdcore_cmd_response_status[127:0] 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \main_sdcore_cmd_response_status $1\main_sdcore_cmd_response_status[127:0]
end
- attribute \src "ls180.v:1398.11-1398.51"
- process $proc$ls180.v:1398$3339
+ attribute \src "ls180.v:1394.11-1394.51"
+ process $proc$ls180.v:1394$3339
assign { } { }
assign $1\main_sdcore_block_length_storage[9:0] 10'0000000000
sync always
sync init
update \main_sdcore_block_length_storage $1\main_sdcore_block_length_storage[9:0]
end
- attribute \src "ls180.v:1399.5-1399.39"
- process $proc$ls180.v:1399$3340
+ attribute \src "ls180.v:1395.5-1395.39"
+ process $proc$ls180.v:1395$3340
assign { } { }
assign $1\main_sdcore_block_length_re[0:0] 1'0
sync always
sync init
update \main_sdcore_block_length_re $1\main_sdcore_block_length_re[0:0]
end
- attribute \src "ls180.v:1400.12-1400.51"
- process $proc$ls180.v:1400$3341
+ attribute \src "ls180.v:1396.12-1396.51"
+ process $proc$ls180.v:1396$3341
assign { } { }
assign $1\main_sdcore_block_count_storage[31:0] 0
sync always
sync init
update \main_sdcore_block_count_storage $1\main_sdcore_block_count_storage[31:0]
end
- attribute \src "ls180.v:1401.5-1401.38"
- process $proc$ls180.v:1401$3342
+ attribute \src "ls180.v:1397.5-1397.38"
+ process $proc$ls180.v:1397$3342
assign { } { }
assign $1\main_sdcore_block_count_re[0:0] 1'0
sync always
sync init
update \main_sdcore_block_count_re $1\main_sdcore_block_count_re[0:0]
end
- attribute \src "ls180.v:1402.11-1402.51"
- process $proc$ls180.v:1402$3343
+ attribute \src "ls180.v:1398.11-1398.51"
+ process $proc$ls180.v:1398$3343
assign { } { }
assign $1\main_sdcore_crc7_inserter_crcreg0[6:0] 7'0000000
sync always
sync init
update \main_sdcore_crc7_inserter_crcreg0 $1\main_sdcore_crc7_inserter_crcreg0[6:0]
end
- attribute \src "ls180.v:1444.11-1444.47"
- process $proc$ls180.v:1444$3344
+ attribute \src "ls180.v:1440.11-1440.47"
+ process $proc$ls180.v:1440$3344
assign { } { }
assign $1\main_sdcore_crc7_inserter_crc[6:0] 7'0000000
sync always
sync init
update \main_sdcore_crc7_inserter_crc $1\main_sdcore_crc7_inserter_crc[6:0]
end
- attribute \src "ls180.v:1448.5-1448.49"
- process $proc$ls180.v:1448$3345
+ attribute \src "ls180.v:1444.5-1444.49"
+ process $proc$ls180.v:1444$3345
assign { } { }
assign $1\main_sdcore_crc16_inserter_sink_ready[0:0] 1'0
sync always
sync init
update \main_sdcore_crc16_inserter_sink_ready $1\main_sdcore_crc16_inserter_sink_ready[0:0]
end
- attribute \src "ls180.v:1452.5-1452.51"
- process $proc$ls180.v:1452$3346
+ attribute \src "ls180.v:1448.5-1448.51"
+ process $proc$ls180.v:1448$3346
assign { } { }
assign $1\main_sdcore_crc16_inserter_source_valid[0:0] 1'0
sync always
sync init
update \main_sdcore_crc16_inserter_source_valid $1\main_sdcore_crc16_inserter_source_valid[0:0]
end
- attribute \src "ls180.v:1453.5-1453.51"
- process $proc$ls180.v:1453$3347
+ attribute \src "ls180.v:1449.5-1449.51"
+ process $proc$ls180.v:1449$3347
assign { } { }
assign $1\main_sdcore_crc16_inserter_source_ready[0:0] 1'0
sync always
sync init
update \main_sdcore_crc16_inserter_source_ready $1\main_sdcore_crc16_inserter_source_ready[0:0]
end
- attribute \src "ls180.v:1454.5-1454.51"
- process $proc$ls180.v:1454$3348
+ attribute \src "ls180.v:1450.5-1450.51"
+ process $proc$ls180.v:1450$3348
assign { } { }
assign $0\main_sdcore_crc16_inserter_source_first[0:0] 1'0
sync always
update \main_sdcore_crc16_inserter_source_first $0\main_sdcore_crc16_inserter_source_first[0:0]
sync init
end
- attribute \src "ls180.v:1455.5-1455.50"
- process $proc$ls180.v:1455$3349
+ attribute \src "ls180.v:1451.5-1451.50"
+ process $proc$ls180.v:1451$3349
assign { } { }
assign $1\main_sdcore_crc16_inserter_source_last[0:0] 1'0
sync always
sync init
update \main_sdcore_crc16_inserter_source_last $1\main_sdcore_crc16_inserter_source_last[0:0]
end
- attribute \src "ls180.v:1456.11-1456.64"
- process $proc$ls180.v:1456$3350
+ attribute \src "ls180.v:1452.11-1452.64"
+ process $proc$ls180.v:1452$3350
assign { } { }
assign $1\main_sdcore_crc16_inserter_source_payload_data[7:0] 8'00000000
sync always
sync init
update \main_sdcore_crc16_inserter_source_payload_data $1\main_sdcore_crc16_inserter_source_payload_data[7:0]
end
- attribute \src "ls180.v:1457.11-1457.48"
- process $proc$ls180.v:1457$3351
+ attribute \src "ls180.v:1453.11-1453.48"
+ process $proc$ls180.v:1453$3351
assign { } { }
assign $1\main_sdcore_crc16_inserter_cnt[2:0] 3'000
sync always
sync init
update \main_sdcore_crc16_inserter_cnt $1\main_sdcore_crc16_inserter_cnt[2:0]
end
- attribute \src "ls180.v:1458.12-1458.59"
- process $proc$ls180.v:1458$3352
+ attribute \src "ls180.v:1454.12-1454.59"
+ process $proc$ls180.v:1454$3352
assign { } { }
assign $1\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] 16'0000000000000000
sync always
sync init
update \main_sdcore_crc16_inserter_crc0_crcreg0 $1\main_sdcore_crc16_inserter_crc0_crcreg0[15:0]
end
- attribute \src "ls180.v:1462.12-1462.55"
- process $proc$ls180.v:1462$3353
+ attribute \src "ls180.v:1458.12-1458.55"
+ process $proc$ls180.v:1458$3353
assign { } { }
assign $1\main_sdcore_crc16_inserter_crc0_crc[15:0] 16'0000000000000000
sync always
sync init
update \main_sdcore_crc16_inserter_crc0_crc $1\main_sdcore_crc16_inserter_crc0_crc[15:0]
end
- attribute \src "ls180.v:1465.12-1465.59"
- process $proc$ls180.v:1465$3354
+ attribute \src "ls180.v:1461.12-1461.59"
+ process $proc$ls180.v:1461$3354
assign { } { }
assign $1\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] 16'0000000000000000
sync always
sync init
update \main_sdcore_crc16_inserter_crc1_crcreg0 $1\main_sdcore_crc16_inserter_crc1_crcreg0[15:0]
end
- attribute \src "ls180.v:1469.12-1469.55"
- process $proc$ls180.v:1469$3355
+ attribute \src "ls180.v:1465.12-1465.55"
+ process $proc$ls180.v:1465$3355
assign { } { }
assign $1\main_sdcore_crc16_inserter_crc1_crc[15:0] 16'0000000000000000
sync always
sync init
update \main_sdcore_crc16_inserter_crc1_crc $1\main_sdcore_crc16_inserter_crc1_crc[15:0]
end
- attribute \src "ls180.v:1472.12-1472.59"
- process $proc$ls180.v:1472$3356
+ attribute \src "ls180.v:1468.12-1468.59"
+ process $proc$ls180.v:1468$3356
assign { } { }
assign $1\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] 16'0000000000000000
sync always
sync init
update \main_sdcore_crc16_inserter_crc2_crcreg0 $1\main_sdcore_crc16_inserter_crc2_crcreg0[15:0]
end
- attribute \src "ls180.v:1476.12-1476.55"
- process $proc$ls180.v:1476$3357
+ attribute \src "ls180.v:1472.12-1472.55"
+ process $proc$ls180.v:1472$3357
assign { } { }
assign $1\main_sdcore_crc16_inserter_crc2_crc[15:0] 16'0000000000000000
sync always
sync init
update \main_sdcore_crc16_inserter_crc2_crc $1\main_sdcore_crc16_inserter_crc2_crc[15:0]
end
- attribute \src "ls180.v:1479.12-1479.59"
- process $proc$ls180.v:1479$3358
+ attribute \src "ls180.v:1475.12-1475.59"
+ process $proc$ls180.v:1475$3358
assign { } { }
assign $1\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] 16'0000000000000000
sync always
sync init
update \main_sdcore_crc16_inserter_crc3_crcreg0 $1\main_sdcore_crc16_inserter_crc3_crcreg0[15:0]
end
- attribute \src "ls180.v:1483.12-1483.55"
- process $proc$ls180.v:1483$3359
+ attribute \src "ls180.v:1479.12-1479.55"
+ process $proc$ls180.v:1479$3359
assign { } { }
assign $1\main_sdcore_crc16_inserter_crc3_crc[15:0] 16'0000000000000000
sync always
sync init
update \main_sdcore_crc16_inserter_crc3_crc $1\main_sdcore_crc16_inserter_crc3_crc[15:0]
end
- attribute \src "ls180.v:1486.12-1486.54"
- process $proc$ls180.v:1486$3360
+ attribute \src "ls180.v:1482.12-1482.54"
+ process $proc$ls180.v:1482$3360
assign { } { }
assign $1\main_sdcore_crc16_inserter_crctmp0[15:0] 16'0000000000000000
sync always
sync init
update \main_sdcore_crc16_inserter_crctmp0 $1\main_sdcore_crc16_inserter_crctmp0[15:0]
end
- attribute \src "ls180.v:1487.12-1487.54"
- process $proc$ls180.v:1487$3361
+ attribute \src "ls180.v:1483.12-1483.54"
+ process $proc$ls180.v:1483$3361
assign { } { }
assign $1\main_sdcore_crc16_inserter_crctmp1[15:0] 16'0000000000000000
sync always
sync init
update \main_sdcore_crc16_inserter_crctmp1 $1\main_sdcore_crc16_inserter_crctmp1[15:0]
end
- attribute \src "ls180.v:1488.12-1488.54"
- process $proc$ls180.v:1488$3362
+ attribute \src "ls180.v:1484.12-1484.54"
+ process $proc$ls180.v:1484$3362
assign { } { }
assign $1\main_sdcore_crc16_inserter_crctmp2[15:0] 16'0000000000000000
sync always
sync init
update \main_sdcore_crc16_inserter_crctmp2 $1\main_sdcore_crc16_inserter_crctmp2[15:0]
end
- attribute \src "ls180.v:1489.12-1489.54"
- process $proc$ls180.v:1489$3363
+ attribute \src "ls180.v:1485.12-1485.54"
+ process $proc$ls180.v:1485$3363
assign { } { }
assign $1\main_sdcore_crc16_inserter_crctmp3[15:0] 16'0000000000000000
sync always
sync init
update \main_sdcore_crc16_inserter_crctmp3 $1\main_sdcore_crc16_inserter_crctmp3[15:0]
end
- attribute \src "ls180.v:1490.5-1490.48"
- process $proc$ls180.v:1490$3364
+ attribute \src "ls180.v:1486.5-1486.48"
+ process $proc$ls180.v:1486$3364
assign { } { }
assign $1\main_sdcore_crc16_checker_sink_valid[0:0] 1'0
sync always
sync init
update \main_sdcore_crc16_checker_sink_valid $1\main_sdcore_crc16_checker_sink_valid[0:0]
end
- attribute \src "ls180.v:1491.5-1491.48"
- process $proc$ls180.v:1491$3365
+ attribute \src "ls180.v:1487.5-1487.48"
+ process $proc$ls180.v:1487$3365
assign { } { }
assign $1\main_sdcore_crc16_checker_sink_ready[0:0] 1'0
sync always
sync init
update \main_sdcore_crc16_checker_sink_ready $1\main_sdcore_crc16_checker_sink_ready[0:0]
end
- attribute \src "ls180.v:1492.5-1492.48"
- process $proc$ls180.v:1492$3366
+ attribute \src "ls180.v:1488.5-1488.48"
+ process $proc$ls180.v:1488$3366
assign { } { }
assign $1\main_sdcore_crc16_checker_sink_first[0:0] 1'0
sync always
sync init
update \main_sdcore_crc16_checker_sink_first $1\main_sdcore_crc16_checker_sink_first[0:0]
end
- attribute \src "ls180.v:1493.5-1493.47"
- process $proc$ls180.v:1493$3367
+ attribute \src "ls180.v:1489.5-1489.47"
+ process $proc$ls180.v:1489$3367
assign { } { }
assign $1\main_sdcore_crc16_checker_sink_last[0:0] 1'0
sync always
sync init
update \main_sdcore_crc16_checker_sink_last $1\main_sdcore_crc16_checker_sink_last[0:0]
end
- attribute \src "ls180.v:1494.11-1494.61"
- process $proc$ls180.v:1494$3368
+ attribute \src "ls180.v:1490.11-1490.61"
+ process $proc$ls180.v:1490$3368
assign { } { }
assign $1\main_sdcore_crc16_checker_sink_payload_data[7:0] 8'00000000
sync always
sync init
update \main_sdcore_crc16_checker_sink_payload_data $1\main_sdcore_crc16_checker_sink_payload_data[7:0]
end
- attribute \src "ls180.v:1495.5-1495.50"
- process $proc$ls180.v:1495$3369
+ attribute \src "ls180.v:1491.5-1491.50"
+ process $proc$ls180.v:1491$3369
assign { } { }
assign $1\main_sdcore_crc16_checker_source_valid[0:0] 1'0
sync always
sync init
update \main_sdcore_crc16_checker_source_valid $1\main_sdcore_crc16_checker_source_valid[0:0]
end
- attribute \src "ls180.v:1497.5-1497.50"
- process $proc$ls180.v:1497$3370
+ attribute \src "ls180.v:1493.5-1493.50"
+ process $proc$ls180.v:1493$3370
assign { } { }
assign $0\main_sdcore_crc16_checker_source_first[0:0] 1'0
sync always
update \main_sdcore_crc16_checker_source_first $0\main_sdcore_crc16_checker_source_first[0:0]
sync init
end
- attribute \src "ls180.v:1500.11-1500.47"
- process $proc$ls180.v:1500$3371
+ attribute \src "ls180.v:1496.11-1496.47"
+ process $proc$ls180.v:1496$3371
assign { } { }
assign $1\main_sdcore_crc16_checker_val[7:0] 8'00000000
sync always
sync init
update \main_sdcore_crc16_checker_val $1\main_sdcore_crc16_checker_val[7:0]
end
- attribute \src "ls180.v:1501.11-1501.47"
- process $proc$ls180.v:1501$3372
+ attribute \src "ls180.v:1497.11-1497.47"
+ process $proc$ls180.v:1497$3372
assign { } { }
assign $1\main_sdcore_crc16_checker_cnt[3:0] 4'0000
sync always
sync init
update \main_sdcore_crc16_checker_cnt $1\main_sdcore_crc16_checker_cnt[3:0]
end
- attribute \src "ls180.v:1502.12-1502.58"
- process $proc$ls180.v:1502$3373
+ attribute \src "ls180.v:1498.12-1498.58"
+ process $proc$ls180.v:1498$3373
assign { } { }
assign $1\main_sdcore_crc16_checker_crc0_crcreg0[15:0] 16'0000000000000000
sync always
sync init
update \main_sdcore_crc16_checker_crc0_crcreg0 $1\main_sdcore_crc16_checker_crc0_crcreg0[15:0]
end
- attribute \src "ls180.v:1506.12-1506.54"
- process $proc$ls180.v:1506$3374
+ attribute \src "ls180.v:1502.12-1502.54"
+ process $proc$ls180.v:1502$3374
assign { } { }
assign $1\main_sdcore_crc16_checker_crc0_crc[15:0] 16'0000000000000000
sync always
sync init
update \main_sdcore_crc16_checker_crc0_crc $1\main_sdcore_crc16_checker_crc0_crc[15:0]
end
- attribute \src "ls180.v:1507.5-1507.46"
- process $proc$ls180.v:1507$3375
+ attribute \src "ls180.v:1503.5-1503.46"
+ process $proc$ls180.v:1503$3375
assign { } { }
assign $1\main_sdcore_crc16_checker_crc0_clr[0:0] 1'0
sync always
sync init
update \main_sdcore_crc16_checker_crc0_clr $1\main_sdcore_crc16_checker_crc0_clr[0:0]
end
- attribute \src "ls180.v:1509.12-1509.58"
- process $proc$ls180.v:1509$3376
+ attribute \src "ls180.v:1505.12-1505.58"
+ process $proc$ls180.v:1505$3376
assign { } { }
assign $1\main_sdcore_crc16_checker_crc1_crcreg0[15:0] 16'0000000000000000
sync always
sync init
update \main_sdcore_crc16_checker_crc1_crcreg0 $1\main_sdcore_crc16_checker_crc1_crcreg0[15:0]
end
- attribute \src "ls180.v:1513.12-1513.54"
- process $proc$ls180.v:1513$3377
+ attribute \src "ls180.v:1509.12-1509.54"
+ process $proc$ls180.v:1509$3377
assign { } { }
assign $1\main_sdcore_crc16_checker_crc1_crc[15:0] 16'0000000000000000
sync always
sync init
update \main_sdcore_crc16_checker_crc1_crc $1\main_sdcore_crc16_checker_crc1_crc[15:0]
end
- attribute \src "ls180.v:1514.5-1514.46"
- process $proc$ls180.v:1514$3378
+ attribute \src "ls180.v:1510.5-1510.46"
+ process $proc$ls180.v:1510$3378
assign { } { }
assign $1\main_sdcore_crc16_checker_crc1_clr[0:0] 1'0
sync always
sync init
update \main_sdcore_crc16_checker_crc1_clr $1\main_sdcore_crc16_checker_crc1_clr[0:0]
end
- attribute \src "ls180.v:1516.12-1516.58"
- process $proc$ls180.v:1516$3379
+ attribute \src "ls180.v:1512.12-1512.58"
+ process $proc$ls180.v:1512$3379
assign { } { }
assign $1\main_sdcore_crc16_checker_crc2_crcreg0[15:0] 16'0000000000000000
sync always
sync init
update \main_sdcore_crc16_checker_crc2_crcreg0 $1\main_sdcore_crc16_checker_crc2_crcreg0[15:0]
end
- attribute \src "ls180.v:1520.12-1520.54"
- process $proc$ls180.v:1520$3380
+ attribute \src "ls180.v:1516.12-1516.54"
+ process $proc$ls180.v:1516$3380
assign { } { }
assign $1\main_sdcore_crc16_checker_crc2_crc[15:0] 16'0000000000000000
sync always
sync init
update \main_sdcore_crc16_checker_crc2_crc $1\main_sdcore_crc16_checker_crc2_crc[15:0]
end
- attribute \src "ls180.v:1521.5-1521.46"
- process $proc$ls180.v:1521$3381
+ attribute \src "ls180.v:1517.5-1517.46"
+ process $proc$ls180.v:1517$3381
assign { } { }
assign $1\main_sdcore_crc16_checker_crc2_clr[0:0] 1'0
sync always
sync init
update \main_sdcore_crc16_checker_crc2_clr $1\main_sdcore_crc16_checker_crc2_clr[0:0]
end
- attribute \src "ls180.v:1523.12-1523.58"
- process $proc$ls180.v:1523$3382
+ attribute \src "ls180.v:1519.12-1519.58"
+ process $proc$ls180.v:1519$3382
assign { } { }
assign $1\main_sdcore_crc16_checker_crc3_crcreg0[15:0] 16'0000000000000000
sync always
sync init
update \main_sdcore_crc16_checker_crc3_crcreg0 $1\main_sdcore_crc16_checker_crc3_crcreg0[15:0]
end
- attribute \src "ls180.v:1527.12-1527.54"
- process $proc$ls180.v:1527$3383
+ attribute \src "ls180.v:1523.12-1523.54"
+ process $proc$ls180.v:1523$3383
assign { } { }
assign $1\main_sdcore_crc16_checker_crc3_crc[15:0] 16'0000000000000000
sync always
sync init
update \main_sdcore_crc16_checker_crc3_crc $1\main_sdcore_crc16_checker_crc3_crc[15:0]
end
- attribute \src "ls180.v:1528.5-1528.46"
- process $proc$ls180.v:1528$3384
+ attribute \src "ls180.v:1524.5-1524.46"
+ process $proc$ls180.v:1524$3384
assign { } { }
assign $1\main_sdcore_crc16_checker_crc3_clr[0:0] 1'0
sync always
sync init
update \main_sdcore_crc16_checker_crc3_clr $1\main_sdcore_crc16_checker_crc3_clr[0:0]
end
- attribute \src "ls180.v:1530.12-1530.53"
- process $proc$ls180.v:1530$3385
+ attribute \src "ls180.v:1526.12-1526.53"
+ process $proc$ls180.v:1526$3385
assign { } { }
assign $1\main_sdcore_crc16_checker_crctmp0[15:0] 16'0000000000000000
sync always
sync init
update \main_sdcore_crc16_checker_crctmp0 $1\main_sdcore_crc16_checker_crctmp0[15:0]
end
- attribute \src "ls180.v:1531.12-1531.53"
- process $proc$ls180.v:1531$3386
+ attribute \src "ls180.v:1527.12-1527.53"
+ process $proc$ls180.v:1527$3386
assign { } { }
assign $1\main_sdcore_crc16_checker_crctmp1[15:0] 16'0000000000000000
sync always
sync init
update \main_sdcore_crc16_checker_crctmp1 $1\main_sdcore_crc16_checker_crctmp1[15:0]
end
- attribute \src "ls180.v:1532.12-1532.53"
- process $proc$ls180.v:1532$3387
+ attribute \src "ls180.v:1528.12-1528.53"
+ process $proc$ls180.v:1528$3387
assign { } { }
assign $1\main_sdcore_crc16_checker_crctmp2[15:0] 16'0000000000000000
sync always
sync init
update \main_sdcore_crc16_checker_crctmp2 $1\main_sdcore_crc16_checker_crctmp2[15:0]
end
- attribute \src "ls180.v:1533.12-1533.53"
- process $proc$ls180.v:1533$3388
+ attribute \src "ls180.v:1529.12-1529.53"
+ process $proc$ls180.v:1529$3388
assign { } { }
assign $1\main_sdcore_crc16_checker_crctmp3[15:0] 16'0000000000000000
sync always
sync init
update \main_sdcore_crc16_checker_crctmp3 $1\main_sdcore_crc16_checker_crctmp3[15:0]
end
- attribute \src "ls180.v:1534.5-1534.43"
- process $proc$ls180.v:1534$3389
+ attribute \src "ls180.v:1530.5-1530.43"
+ process $proc$ls180.v:1530$3389
assign { } { }
assign $1\main_sdcore_crc16_checker_valid[0:0] 1'0
sync always
sync init
update \main_sdcore_crc16_checker_valid $1\main_sdcore_crc16_checker_valid[0:0]
end
- attribute \src "ls180.v:1535.12-1535.51"
- process $proc$ls180.v:1535$3390
+ attribute \src "ls180.v:1531.12-1531.51"
+ process $proc$ls180.v:1531$3390
assign { } { }
assign $1\main_sdcore_crc16_checker_fifo0[15:0] 16'0000000000000000
sync always
sync init
update \main_sdcore_crc16_checker_fifo0 $1\main_sdcore_crc16_checker_fifo0[15:0]
end
- attribute \src "ls180.v:1536.12-1536.51"
- process $proc$ls180.v:1536$3391
+ attribute \src "ls180.v:1532.12-1532.51"
+ process $proc$ls180.v:1532$3391
assign { } { }
assign $1\main_sdcore_crc16_checker_fifo1[15:0] 16'0000000000000000
sync always
sync init
update \main_sdcore_crc16_checker_fifo1 $1\main_sdcore_crc16_checker_fifo1[15:0]
end
- attribute \src "ls180.v:1537.12-1537.51"
- process $proc$ls180.v:1537$3392
+ attribute \src "ls180.v:1533.12-1533.51"
+ process $proc$ls180.v:1533$3392
assign { } { }
assign $1\main_sdcore_crc16_checker_fifo2[15:0] 16'0000000000000000
sync always
sync init
update \main_sdcore_crc16_checker_fifo2 $1\main_sdcore_crc16_checker_fifo2[15:0]
end
- attribute \src "ls180.v:1538.12-1538.51"
- process $proc$ls180.v:1538$3393
+ attribute \src "ls180.v:1534.12-1534.51"
+ process $proc$ls180.v:1534$3393
assign { } { }
assign $1\main_sdcore_crc16_checker_fifo3[15:0] 16'0000000000000000
sync always
sync init
update \main_sdcore_crc16_checker_fifo3 $1\main_sdcore_crc16_checker_fifo3[15:0]
end
- attribute \src "ls180.v:1540.11-1540.39"
- process $proc$ls180.v:1540$3394
+ attribute \src "ls180.v:1536.11-1536.39"
+ process $proc$ls180.v:1536$3394
assign { } { }
assign $1\main_sdcore_cmd_count[2:0] 3'000
sync always
sync init
update \main_sdcore_cmd_count $1\main_sdcore_cmd_count[2:0]
end
- attribute \src "ls180.v:1541.5-1541.32"
- process $proc$ls180.v:1541$3395
+ attribute \src "ls180.v:1537.5-1537.32"
+ process $proc$ls180.v:1537$3395
assign { } { }
assign $1\main_sdcore_cmd_done[0:0] 1'0
sync always
sync init
update \main_sdcore_cmd_done $1\main_sdcore_cmd_done[0:0]
end
- attribute \src "ls180.v:1542.5-1542.33"
- process $proc$ls180.v:1542$3396
+ attribute \src "ls180.v:1538.5-1538.33"
+ process $proc$ls180.v:1538$3396
assign { } { }
assign $1\main_sdcore_cmd_error[0:0] 1'0
sync always
sync init
update \main_sdcore_cmd_error $1\main_sdcore_cmd_error[0:0]
end
- attribute \src "ls180.v:1543.5-1543.35"
- process $proc$ls180.v:1543$3397
+ attribute \src "ls180.v:1539.5-1539.35"
+ process $proc$ls180.v:1539$3397
assign { } { }
assign $1\main_sdcore_cmd_timeout[0:0] 1'0
sync always
sync init
update \main_sdcore_cmd_timeout $1\main_sdcore_cmd_timeout[0:0]
end
- attribute \src "ls180.v:1545.12-1545.42"
- process $proc$ls180.v:1545$3398
+ attribute \src "ls180.v:1541.12-1541.42"
+ process $proc$ls180.v:1541$3398
assign { } { }
assign $1\main_sdcore_data_count[31:0] 0
sync always
sync init
update \main_sdcore_data_count $1\main_sdcore_data_count[31:0]
end
- attribute \src "ls180.v:1546.5-1546.33"
- process $proc$ls180.v:1546$3399
+ attribute \src "ls180.v:1542.5-1542.33"
+ process $proc$ls180.v:1542$3399
assign { } { }
assign $1\main_sdcore_data_done[0:0] 1'0
sync always
sync init
update \main_sdcore_data_done $1\main_sdcore_data_done[0:0]
end
- attribute \src "ls180.v:1547.5-1547.34"
- process $proc$ls180.v:1547$3400
+ attribute \src "ls180.v:1543.5-1543.34"
+ process $proc$ls180.v:1543$3400
assign { } { }
assign $1\main_sdcore_data_error[0:0] 1'0
sync always
sync init
update \main_sdcore_data_error $1\main_sdcore_data_error[0:0]
end
- attribute \src "ls180.v:1548.5-1548.36"
- process $proc$ls180.v:1548$3401
+ attribute \src "ls180.v:1544.5-1544.36"
+ process $proc$ls180.v:1544$3401
assign { } { }
assign $1\main_sdcore_data_timeout[0:0] 1'0
sync always
sync init
update \main_sdcore_data_timeout $1\main_sdcore_data_timeout[0:0]
end
- attribute \src "ls180.v:1557.11-1557.41"
- process $proc$ls180.v:1557$3402
+ attribute \src "ls180.v:1553.11-1553.41"
+ process $proc$ls180.v:1553$3402
assign { } { }
assign $0\main_interface0_bus_cti[2:0] 3'000
sync always
update \main_interface0_bus_cti $0\main_interface0_bus_cti[2:0]
sync init
end
- attribute \src "ls180.v:1558.11-1558.41"
- process $proc$ls180.v:1558$3403
+ attribute \src "ls180.v:1554.11-1554.41"
+ process $proc$ls180.v:1554$3403
assign { } { }
assign $0\main_interface0_bus_bte[1:0] 2'00
sync always
update \main_interface0_bus_bte $0\main_interface0_bus_bte[1:0]
sync init
end
- attribute \src "ls180.v:1581.11-1581.45"
- process $proc$ls180.v:1581$3404
+ attribute \src "ls180.v:1577.11-1577.45"
+ process $proc$ls180.v:1577$3404
assign { } { }
assign $1\main_sdblock2mem_fifo_level[5:0] 6'000000
sync always
sync init
update \main_sdblock2mem_fifo_level $1\main_sdblock2mem_fifo_level[5:0]
end
- attribute \src "ls180.v:1582.5-1582.41"
- process $proc$ls180.v:1582$3405
+ attribute \src "ls180.v:1578.5-1578.41"
+ process $proc$ls180.v:1578$3405
assign { } { }
assign $0\main_sdblock2mem_fifo_replace[0:0] 1'0
sync always
update \main_sdblock2mem_fifo_replace $0\main_sdblock2mem_fifo_replace[0:0]
sync init
end
- attribute \src "ls180.v:1583.11-1583.47"
- process $proc$ls180.v:1583$3406
+ attribute \src "ls180.v:1579.11-1579.47"
+ process $proc$ls180.v:1579$3406
assign { } { }
assign $1\main_sdblock2mem_fifo_produce[4:0] 5'00000
sync always
sync init
update \main_sdblock2mem_fifo_produce $1\main_sdblock2mem_fifo_produce[4:0]
end
- attribute \src "ls180.v:1584.11-1584.47"
- process $proc$ls180.v:1584$3407
+ attribute \src "ls180.v:158.12-158.71"
+ process $proc$ls180.v:158$2775
+ assign { } { }
+ assign $1\main_libresocsim_interface0_converted_interface_adr[29:0] 30'000000000000000000000000000000
+ sync always
+ sync init
+ update \main_libresocsim_interface0_converted_interface_adr $1\main_libresocsim_interface0_converted_interface_adr[29:0]
+ end
+ attribute \src "ls180.v:1580.11-1580.47"
+ process $proc$ls180.v:1580$3407
assign { } { }
assign $1\main_sdblock2mem_fifo_consume[4:0] 5'00000
sync always
sync init
update \main_sdblock2mem_fifo_consume $1\main_sdblock2mem_fifo_consume[4:0]
end
- attribute \src "ls180.v:1585.11-1585.50"
- process $proc$ls180.v:1585$3408
+ attribute \src "ls180.v:1581.11-1581.50"
+ process $proc$ls180.v:1581$3408
assign { } { }
assign $1\main_sdblock2mem_fifo_wrport_adr[4:0] 5'00000
sync always
sync init
update \main_sdblock2mem_fifo_wrport_adr $1\main_sdblock2mem_fifo_wrport_adr[4:0]
end
- attribute \src "ls180.v:1605.5-1605.51"
- process $proc$ls180.v:1605$3409
+ attribute \src "ls180.v:159.12-159.73"
+ process $proc$ls180.v:159$2776
+ assign { } { }
+ assign $1\main_libresocsim_interface0_converted_interface_dat_w[31:0] 0
+ sync always
+ sync init
+ update \main_libresocsim_interface0_converted_interface_dat_w $1\main_libresocsim_interface0_converted_interface_dat_w[31:0]
+ end
+ attribute \src "ls180.v:1601.5-1601.51"
+ process $proc$ls180.v:1601$3409
assign { } { }
assign $1\main_sdblock2mem_converter_source_first[0:0] 1'0
sync always
sync init
update \main_sdblock2mem_converter_source_first $1\main_sdblock2mem_converter_source_first[0:0]
end
- attribute \src "ls180.v:1606.5-1606.50"
- process $proc$ls180.v:1606$3410
+ attribute \src "ls180.v:1602.5-1602.50"
+ process $proc$ls180.v:1602$3410
assign { } { }
assign $1\main_sdblock2mem_converter_source_last[0:0] 1'0
sync always
sync init
update \main_sdblock2mem_converter_source_last $1\main_sdblock2mem_converter_source_last[0:0]
end
- attribute \src "ls180.v:1607.12-1607.66"
- process $proc$ls180.v:1607$3411
+ attribute \src "ls180.v:1603.12-1603.66"
+ process $proc$ls180.v:1603$3411
assign { } { }
assign $1\main_sdblock2mem_converter_source_payload_data[31:0] 0
sync always
sync init
update \main_sdblock2mem_converter_source_payload_data $1\main_sdblock2mem_converter_source_payload_data[31:0]
end
- attribute \src "ls180.v:1608.11-1608.77"
- process $proc$ls180.v:1608$3412
+ attribute \src "ls180.v:1604.11-1604.77"
+ process $proc$ls180.v:1604$3412
assign { } { }
assign $1\main_sdblock2mem_converter_source_payload_valid_token_count[2:0] 3'000
sync always
sync init
update \main_sdblock2mem_converter_source_payload_valid_token_count $1\main_sdblock2mem_converter_source_payload_valid_token_count[2:0]
end
- attribute \src "ls180.v:1609.11-1609.50"
- process $proc$ls180.v:1609$3413
+ attribute \src "ls180.v:1605.11-1605.50"
+ process $proc$ls180.v:1605$3413
assign { } { }
assign $1\main_sdblock2mem_converter_demux[1:0] 2'00
sync always
sync init
update \main_sdblock2mem_converter_demux $1\main_sdblock2mem_converter_demux[1:0]
end
- attribute \src "ls180.v:1611.5-1611.49"
- process $proc$ls180.v:1611$3414
+ attribute \src "ls180.v:1607.5-1607.49"
+ process $proc$ls180.v:1607$3414
assign { } { }
assign $1\main_sdblock2mem_converter_strobe_all[0:0] 1'0
sync always
sync init
update \main_sdblock2mem_converter_strobe_all $1\main_sdblock2mem_converter_strobe_all[0:0]
end
- attribute \src "ls180.v:1617.5-1617.45"
- process $proc$ls180.v:1617$3415
+ attribute \src "ls180.v:161.11-161.69"
+ process $proc$ls180.v:161$2777
assign { } { }
- assign $1\main_sdblock2mem_sink_sink_valid1[0:0] 1'0
+ assign $1\main_libresocsim_interface0_converted_interface_sel[3:0] 4'0000
sync always
sync init
- update \main_sdblock2mem_sink_sink_valid1 $1\main_sdblock2mem_sink_sink_valid1[0:0]
+ update \main_libresocsim_interface0_converted_interface_sel $1\main_libresocsim_interface0_converted_interface_sel[3:0]
end
- attribute \src "ls180.v:1619.12-1619.62"
- process $proc$ls180.v:1619$3416
+ attribute \src "ls180.v:1613.5-1613.45"
+ process $proc$ls180.v:1613$3415
assign { } { }
- assign $1\main_sdblock2mem_sink_sink_payload_address[31:0] 0
+ assign $1\main_sdblock2mem_sink_sink_valid1[0:0] 1'0
sync always
sync init
- update \main_sdblock2mem_sink_sink_payload_address $1\main_sdblock2mem_sink_sink_payload_address[31:0]
+ update \main_sdblock2mem_sink_sink_valid1 $1\main_sdblock2mem_sink_sink_valid1[0:0]
end
- attribute \src "ls180.v:162.12-162.71"
- process $proc$ls180.v:162$2775
+ attribute \src "ls180.v:1615.12-1615.62"
+ process $proc$ls180.v:1615$3416
assign { } { }
- assign $1\main_libresocsim_interface0_converted_interface_adr[29:0] 30'000000000000000000000000000000
+ assign $1\main_sdblock2mem_sink_sink_payload_address[31:0] 0
sync always
sync init
- update \main_libresocsim_interface0_converted_interface_adr $1\main_libresocsim_interface0_converted_interface_adr[29:0]
+ update \main_sdblock2mem_sink_sink_payload_address $1\main_sdblock2mem_sink_sink_payload_address[31:0]
end
- attribute \src "ls180.v:1620.12-1620.60"
- process $proc$ls180.v:1620$3417
+ attribute \src "ls180.v:1616.12-1616.60"
+ process $proc$ls180.v:1616$3417
assign { } { }
assign $1\main_sdblock2mem_sink_sink_payload_data1[31:0] 0
sync always
sync init
update \main_sdblock2mem_sink_sink_payload_data1 $1\main_sdblock2mem_sink_sink_payload_data1[31:0]
end
- attribute \src "ls180.v:1622.5-1622.57"
- process $proc$ls180.v:1622$3418
+ attribute \src "ls180.v:1618.5-1618.57"
+ process $proc$ls180.v:1618$3418
assign { } { }
assign $1\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0] 1'0
sync always
sync init
update \main_sdblock2mem_wishbonedmawriter_sink_ready $1\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0]
end
- attribute \src "ls180.v:1626.12-1626.67"
- process $proc$ls180.v:1626$3419
+ attribute \src "ls180.v:162.5-162.63"
+ process $proc$ls180.v:162$2778
+ assign { } { }
+ assign $1\main_libresocsim_interface0_converted_interface_cyc[0:0] 1'0
+ sync always
+ sync init
+ update \main_libresocsim_interface0_converted_interface_cyc $1\main_libresocsim_interface0_converted_interface_cyc[0:0]
+ end
+ attribute \src "ls180.v:1622.12-1622.67"
+ process $proc$ls180.v:1622$3419
assign { } { }
assign $1\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \main_sdblock2mem_wishbonedmawriter_base_storage $1\main_sdblock2mem_wishbonedmawriter_base_storage[63:0]
end
- attribute \src "ls180.v:1627.5-1627.54"
- process $proc$ls180.v:1627$3420
+ attribute \src "ls180.v:1623.5-1623.54"
+ process $proc$ls180.v:1623$3420
assign { } { }
assign $1\main_sdblock2mem_wishbonedmawriter_base_re[0:0] 1'0
sync always
sync init
update \main_sdblock2mem_wishbonedmawriter_base_re $1\main_sdblock2mem_wishbonedmawriter_base_re[0:0]
end
- attribute \src "ls180.v:1628.12-1628.69"
- process $proc$ls180.v:1628$3421
+ attribute \src "ls180.v:1624.12-1624.69"
+ process $proc$ls180.v:1624$3421
assign { } { }
assign $1\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] 0
sync always
sync init
update \main_sdblock2mem_wishbonedmawriter_length_storage $1\main_sdblock2mem_wishbonedmawriter_length_storage[31:0]
end
- attribute \src "ls180.v:1629.5-1629.56"
- process $proc$ls180.v:1629$3422
+ attribute \src "ls180.v:1625.5-1625.56"
+ process $proc$ls180.v:1625$3422
assign { } { }
assign $1\main_sdblock2mem_wishbonedmawriter_length_re[0:0] 1'0
sync always
sync init
update \main_sdblock2mem_wishbonedmawriter_length_re $1\main_sdblock2mem_wishbonedmawriter_length_re[0:0]
end
- attribute \src "ls180.v:163.12-163.73"
- process $proc$ls180.v:163$2776
- assign { } { }
- assign $1\main_libresocsim_interface0_converted_interface_dat_w[31:0] 0
- sync always
- sync init
- update \main_libresocsim_interface0_converted_interface_dat_w $1\main_libresocsim_interface0_converted_interface_dat_w[31:0]
- end
- attribute \src "ls180.v:1630.5-1630.61"
- process $proc$ls180.v:1630$3423
+ attribute \src "ls180.v:1626.5-1626.61"
+ process $proc$ls180.v:1626$3423
assign { } { }
assign $1\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0] 1'0
sync always
sync init
update \main_sdblock2mem_wishbonedmawriter_enable_storage $1\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0]
end
- attribute \src "ls180.v:1631.5-1631.56"
- process $proc$ls180.v:1631$3424
+ attribute \src "ls180.v:1627.5-1627.56"
+ process $proc$ls180.v:1627$3424
assign { } { }
assign $1\main_sdblock2mem_wishbonedmawriter_enable_re[0:0] 1'0
sync always
sync init
update \main_sdblock2mem_wishbonedmawriter_enable_re $1\main_sdblock2mem_wishbonedmawriter_enable_re[0:0]
end
- attribute \src "ls180.v:1632.5-1632.53"
- process $proc$ls180.v:1632$3425
+ attribute \src "ls180.v:1628.5-1628.53"
+ process $proc$ls180.v:1628$3425
assign { } { }
assign $1\main_sdblock2mem_wishbonedmawriter_status[0:0] 1'0
sync always
sync init
update \main_sdblock2mem_wishbonedmawriter_status $1\main_sdblock2mem_wishbonedmawriter_status[0:0]
end
- attribute \src "ls180.v:1634.5-1634.59"
- process $proc$ls180.v:1634$3426
+ attribute \src "ls180.v:163.5-163.63"
+ process $proc$ls180.v:163$2779
+ assign { } { }
+ assign $1\main_libresocsim_interface0_converted_interface_stb[0:0] 1'0
+ sync always
+ sync init
+ update \main_libresocsim_interface0_converted_interface_stb $1\main_libresocsim_interface0_converted_interface_stb[0:0]
+ end
+ attribute \src "ls180.v:1630.5-1630.59"
+ process $proc$ls180.v:1630$3426
assign { } { }
assign $1\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0] 1'0
sync always
sync init
update \main_sdblock2mem_wishbonedmawriter_loop_storage $1\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0]
end
- attribute \src "ls180.v:1635.5-1635.54"
- process $proc$ls180.v:1635$3427
+ attribute \src "ls180.v:1631.5-1631.54"
+ process $proc$ls180.v:1631$3427
assign { } { }
assign $1\main_sdblock2mem_wishbonedmawriter_loop_re[0:0] 1'0
sync always
sync init
update \main_sdblock2mem_wishbonedmawriter_loop_re $1\main_sdblock2mem_wishbonedmawriter_loop_re[0:0]
end
- attribute \src "ls180.v:1637.12-1637.61"
- process $proc$ls180.v:1637$3428
+ attribute \src "ls180.v:1633.12-1633.61"
+ process $proc$ls180.v:1633$3428
assign { } { }
assign $1\main_sdblock2mem_wishbonedmawriter_offset[31:0] 0
sync always
sync init
update \main_sdblock2mem_wishbonedmawriter_offset $1\main_sdblock2mem_wishbonedmawriter_offset[31:0]
end
- attribute \src "ls180.v:1640.12-1640.43"
- process $proc$ls180.v:1640$3429
+ attribute \src "ls180.v:1636.12-1636.43"
+ process $proc$ls180.v:1636$3429
assign { } { }
assign $1\main_interface1_bus_adr[31:0] 0
sync always
sync init
update \main_interface1_bus_adr $1\main_interface1_bus_adr[31:0]
end
- attribute \src "ls180.v:1641.12-1641.45"
- process $proc$ls180.v:1641$3430
+ attribute \src "ls180.v:1637.12-1637.45"
+ process $proc$ls180.v:1637$3430
assign { } { }
assign $0\main_interface1_bus_dat_w[31:0] 0
sync always
update \main_interface1_bus_dat_w $0\main_interface1_bus_dat_w[31:0]
sync init
end
- attribute \src "ls180.v:1643.11-1643.41"
- process $proc$ls180.v:1643$3431
+ attribute \src "ls180.v:1639.11-1639.41"
+ process $proc$ls180.v:1639$3431
assign { } { }
assign $1\main_interface1_bus_sel[3:0] 4'0000
sync always
sync init
update \main_interface1_bus_sel $1\main_interface1_bus_sel[3:0]
end
- attribute \src "ls180.v:1644.5-1644.35"
- process $proc$ls180.v:1644$3432
+ attribute \src "ls180.v:1640.5-1640.35"
+ process $proc$ls180.v:1640$3432
assign { } { }
assign $1\main_interface1_bus_cyc[0:0] 1'0
sync always
sync init
update \main_interface1_bus_cyc $1\main_interface1_bus_cyc[0:0]
end
- attribute \src "ls180.v:1645.5-1645.35"
- process $proc$ls180.v:1645$3433
+ attribute \src "ls180.v:1641.5-1641.35"
+ process $proc$ls180.v:1641$3433
assign { } { }
assign $1\main_interface1_bus_stb[0:0] 1'0
sync always
sync init
update \main_interface1_bus_stb $1\main_interface1_bus_stb[0:0]
end
- attribute \src "ls180.v:1647.5-1647.34"
- process $proc$ls180.v:1647$3434
+ attribute \src "ls180.v:1643.5-1643.34"
+ process $proc$ls180.v:1643$3434
assign { } { }
assign $1\main_interface1_bus_we[0:0] 1'0
sync always
sync init
update \main_interface1_bus_we $1\main_interface1_bus_we[0:0]
end
- attribute \src "ls180.v:1648.11-1648.41"
- process $proc$ls180.v:1648$3435
+ attribute \src "ls180.v:1644.11-1644.41"
+ process $proc$ls180.v:1644$3435
assign { } { }
assign $0\main_interface1_bus_cti[2:0] 3'000
sync always
update \main_interface1_bus_cti $0\main_interface1_bus_cti[2:0]
sync init
end
- attribute \src "ls180.v:1649.11-1649.41"
- process $proc$ls180.v:1649$3436
+ attribute \src "ls180.v:1645.11-1645.41"
+ process $proc$ls180.v:1645$3436
assign { } { }
assign $0\main_interface1_bus_bte[1:0] 2'00
sync always
update \main_interface1_bus_bte $0\main_interface1_bus_bte[1:0]
sync init
end
- attribute \src "ls180.v:165.11-165.69"
- process $proc$ls180.v:165$2777
+ attribute \src "ls180.v:165.5-165.62"
+ process $proc$ls180.v:165$2780
assign { } { }
- assign $1\main_libresocsim_interface0_converted_interface_sel[3:0] 4'0000
+ assign $1\main_libresocsim_interface0_converted_interface_we[0:0] 1'0
sync always
sync init
- update \main_libresocsim_interface0_converted_interface_sel $1\main_libresocsim_interface0_converted_interface_sel[3:0]
+ update \main_libresocsim_interface0_converted_interface_we $1\main_libresocsim_interface0_converted_interface_we[0:0]
end
- attribute \src "ls180.v:1656.5-1656.43"
- process $proc$ls180.v:1656$3437
+ attribute \src "ls180.v:1652.5-1652.43"
+ process $proc$ls180.v:1652$3437
assign { } { }
assign $1\main_sdmem2block_dma_sink_valid[0:0] 1'0
sync always
sync init
update \main_sdmem2block_dma_sink_valid $1\main_sdmem2block_dma_sink_valid[0:0]
end
- attribute \src "ls180.v:1657.5-1657.43"
- process $proc$ls180.v:1657$3438
+ attribute \src "ls180.v:1653.5-1653.43"
+ process $proc$ls180.v:1653$3438
assign { } { }
assign $1\main_sdmem2block_dma_sink_ready[0:0] 1'0
sync always
sync init
update \main_sdmem2block_dma_sink_ready $1\main_sdmem2block_dma_sink_ready[0:0]
end
- attribute \src "ls180.v:1658.5-1658.42"
- process $proc$ls180.v:1658$3439
+ attribute \src "ls180.v:1654.5-1654.42"
+ process $proc$ls180.v:1654$3439
assign { } { }
assign $1\main_sdmem2block_dma_sink_last[0:0] 1'0
sync always
sync init
update \main_sdmem2block_dma_sink_last $1\main_sdmem2block_dma_sink_last[0:0]
end
- attribute \src "ls180.v:1659.12-1659.61"
- process $proc$ls180.v:1659$3440
+ attribute \src "ls180.v:1655.12-1655.61"
+ process $proc$ls180.v:1655$3440
assign { } { }
assign $1\main_sdmem2block_dma_sink_payload_address[31:0] 0
sync always
sync init
update \main_sdmem2block_dma_sink_payload_address $1\main_sdmem2block_dma_sink_payload_address[31:0]
end
- attribute \src "ls180.v:166.5-166.63"
- process $proc$ls180.v:166$2778
- assign { } { }
- assign $1\main_libresocsim_interface0_converted_interface_cyc[0:0] 1'0
- sync always
- sync init
- update \main_libresocsim_interface0_converted_interface_cyc $1\main_libresocsim_interface0_converted_interface_cyc[0:0]
- end
- attribute \src "ls180.v:1660.5-1660.45"
- process $proc$ls180.v:1660$3441
+ attribute \src "ls180.v:1656.5-1656.45"
+ process $proc$ls180.v:1656$3441
assign { } { }
assign $1\main_sdmem2block_dma_source_valid[0:0] 1'0
sync always
sync init
update \main_sdmem2block_dma_source_valid $1\main_sdmem2block_dma_source_valid[0:0]
end
- attribute \src "ls180.v:1662.5-1662.45"
- process $proc$ls180.v:1662$3442
+ attribute \src "ls180.v:1658.5-1658.45"
+ process $proc$ls180.v:1658$3442
assign { } { }
assign $0\main_sdmem2block_dma_source_first[0:0] 1'0
sync always
update \main_sdmem2block_dma_source_first $0\main_sdmem2block_dma_source_first[0:0]
sync init
end
- attribute \src "ls180.v:1663.5-1663.44"
- process $proc$ls180.v:1663$3443
+ attribute \src "ls180.v:1659.5-1659.44"
+ process $proc$ls180.v:1659$3443
assign { } { }
assign $1\main_sdmem2block_dma_source_last[0:0] 1'0
sync always
sync init
update \main_sdmem2block_dma_source_last $1\main_sdmem2block_dma_source_last[0:0]
end
- attribute \src "ls180.v:1664.12-1664.60"
- process $proc$ls180.v:1664$3444
+ attribute \src "ls180.v:166.11-166.69"
+ process $proc$ls180.v:166$2781
+ assign { } { }
+ assign $0\main_libresocsim_interface0_converted_interface_cti[2:0] 3'000
+ sync always
+ update \main_libresocsim_interface0_converted_interface_cti $0\main_libresocsim_interface0_converted_interface_cti[2:0]
+ sync init
+ end
+ attribute \src "ls180.v:1660.12-1660.60"
+ process $proc$ls180.v:1660$3444
assign { } { }
assign $1\main_sdmem2block_dma_source_payload_data[31:0] 0
sync always
sync init
update \main_sdmem2block_dma_source_payload_data $1\main_sdmem2block_dma_source_payload_data[31:0]
end
- attribute \src "ls180.v:1665.12-1665.45"
- process $proc$ls180.v:1665$3445
+ attribute \src "ls180.v:1661.12-1661.45"
+ process $proc$ls180.v:1661$3445
assign { } { }
assign $1\main_sdmem2block_dma_data[31:0] 0
sync always
sync init
update \main_sdmem2block_dma_data $1\main_sdmem2block_dma_data[31:0]
end
- attribute \src "ls180.v:1666.12-1666.53"
- process $proc$ls180.v:1666$3446
+ attribute \src "ls180.v:1662.12-1662.53"
+ process $proc$ls180.v:1662$3446
assign { } { }
assign $1\main_sdmem2block_dma_base_storage[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \main_sdmem2block_dma_base_storage $1\main_sdmem2block_dma_base_storage[63:0]
end
- attribute \src "ls180.v:1667.5-1667.40"
- process $proc$ls180.v:1667$3447
+ attribute \src "ls180.v:1663.5-1663.40"
+ process $proc$ls180.v:1663$3447
assign { } { }
assign $1\main_sdmem2block_dma_base_re[0:0] 1'0
sync always
sync init
update \main_sdmem2block_dma_base_re $1\main_sdmem2block_dma_base_re[0:0]
end
- attribute \src "ls180.v:1668.12-1668.55"
- process $proc$ls180.v:1668$3448
+ attribute \src "ls180.v:1664.12-1664.55"
+ process $proc$ls180.v:1664$3448
assign { } { }
assign $1\main_sdmem2block_dma_length_storage[31:0] 0
sync always
sync init
update \main_sdmem2block_dma_length_storage $1\main_sdmem2block_dma_length_storage[31:0]
end
- attribute \src "ls180.v:1669.5-1669.42"
- process $proc$ls180.v:1669$3449
+ attribute \src "ls180.v:1665.5-1665.42"
+ process $proc$ls180.v:1665$3449
assign { } { }
assign $1\main_sdmem2block_dma_length_re[0:0] 1'0
sync always
sync init
update \main_sdmem2block_dma_length_re $1\main_sdmem2block_dma_length_re[0:0]
end
- attribute \src "ls180.v:167.5-167.63"
- process $proc$ls180.v:167$2779
- assign { } { }
- assign $1\main_libresocsim_interface0_converted_interface_stb[0:0] 1'0
- sync always
- sync init
- update \main_libresocsim_interface0_converted_interface_stb $1\main_libresocsim_interface0_converted_interface_stb[0:0]
- end
- attribute \src "ls180.v:1670.5-1670.47"
- process $proc$ls180.v:1670$3450
+ attribute \src "ls180.v:1666.5-1666.47"
+ process $proc$ls180.v:1666$3450
assign { } { }
assign $1\main_sdmem2block_dma_enable_storage[0:0] 1'0
sync always
sync init
update \main_sdmem2block_dma_enable_storage $1\main_sdmem2block_dma_enable_storage[0:0]
end
- attribute \src "ls180.v:1671.5-1671.42"
- process $proc$ls180.v:1671$3451
+ attribute \src "ls180.v:1667.5-1667.42"
+ process $proc$ls180.v:1667$3451
assign { } { }
assign $1\main_sdmem2block_dma_enable_re[0:0] 1'0
sync always
sync init
update \main_sdmem2block_dma_enable_re $1\main_sdmem2block_dma_enable_re[0:0]
end
- attribute \src "ls180.v:1672.5-1672.44"
- process $proc$ls180.v:1672$3452
+ attribute \src "ls180.v:1668.5-1668.44"
+ process $proc$ls180.v:1668$3452
assign { } { }
assign $1\main_sdmem2block_dma_done_status[0:0] 1'0
sync always
sync init
update \main_sdmem2block_dma_done_status $1\main_sdmem2block_dma_done_status[0:0]
end
- attribute \src "ls180.v:1674.5-1674.45"
- process $proc$ls180.v:1674$3453
+ attribute \src "ls180.v:167.11-167.69"
+ process $proc$ls180.v:167$2782
+ assign { } { }
+ assign $0\main_libresocsim_interface0_converted_interface_bte[1:0] 2'00
+ sync always
+ update \main_libresocsim_interface0_converted_interface_bte $0\main_libresocsim_interface0_converted_interface_bte[1:0]
+ sync init
+ end
+ attribute \src "ls180.v:1670.5-1670.45"
+ process $proc$ls180.v:1670$3453
assign { } { }
assign $1\main_sdmem2block_dma_loop_storage[0:0] 1'0
sync always
sync init
update \main_sdmem2block_dma_loop_storage $1\main_sdmem2block_dma_loop_storage[0:0]
end
- attribute \src "ls180.v:1675.5-1675.40"
- process $proc$ls180.v:1675$3454
+ attribute \src "ls180.v:1671.5-1671.40"
+ process $proc$ls180.v:1671$3454
assign { } { }
assign $1\main_sdmem2block_dma_loop_re[0:0] 1'0
sync always
sync init
update \main_sdmem2block_dma_loop_re $1\main_sdmem2block_dma_loop_re[0:0]
end
- attribute \src "ls180.v:1679.12-1679.47"
- process $proc$ls180.v:1679$3455
+ attribute \src "ls180.v:1675.12-1675.47"
+ process $proc$ls180.v:1675$3455
assign { } { }
assign $1\main_sdmem2block_dma_offset[31:0] 0
sync always
sync init
update \main_sdmem2block_dma_offset $1\main_sdmem2block_dma_offset[31:0]
end
- attribute \src "ls180.v:169.5-169.62"
- process $proc$ls180.v:169$2780
- assign { } { }
- assign $1\main_libresocsim_interface0_converted_interface_we[0:0] 1'0
- sync always
- sync init
- update \main_libresocsim_interface0_converted_interface_we $1\main_libresocsim_interface0_converted_interface_we[0:0]
- end
- attribute \src "ls180.v:1691.11-1691.64"
- process $proc$ls180.v:1691$3456
+ attribute \src "ls180.v:1687.11-1687.64"
+ process $proc$ls180.v:1687$3456
assign { } { }
assign $1\main_sdmem2block_converter_source_payload_data[7:0] 8'00000000
sync always
sync init
update \main_sdmem2block_converter_source_payload_data $1\main_sdmem2block_converter_source_payload_data[7:0]
end
- attribute \src "ls180.v:1693.11-1693.48"
- process $proc$ls180.v:1693$3457
+ attribute \src "ls180.v:1689.11-1689.48"
+ process $proc$ls180.v:1689$3457
assign { } { }
assign $1\main_sdmem2block_converter_mux[1:0] 2'00
sync always
sync init
update \main_sdmem2block_converter_mux $1\main_sdmem2block_converter_mux[1:0]
end
- attribute \src "ls180.v:170.11-170.69"
- process $proc$ls180.v:170$2781
+ attribute \src "ls180.v:169.5-169.44"
+ process $proc$ls180.v:169$2783
assign { } { }
- assign $0\main_libresocsim_interface0_converted_interface_cti[2:0] 3'000
+ assign $1\main_libresocsim_converter0_skip[0:0] 1'0
sync always
- update \main_libresocsim_interface0_converted_interface_cti $0\main_libresocsim_interface0_converted_interface_cti[2:0]
sync init
+ update \main_libresocsim_converter0_skip $1\main_libresocsim_converter0_skip[0:0]
end
- attribute \src "ls180.v:171.11-171.69"
- process $proc$ls180.v:171$2782
+ attribute \src "ls180.v:170.5-170.47"
+ process $proc$ls180.v:170$2784
assign { } { }
- assign $0\main_libresocsim_interface0_converted_interface_bte[1:0] 2'00
+ assign $1\main_libresocsim_converter0_counter[0:0] 1'0
sync always
- update \main_libresocsim_interface0_converted_interface_bte $0\main_libresocsim_interface0_converted_interface_bte[1:0]
sync init
+ update \main_libresocsim_converter0_counter $1\main_libresocsim_converter0_counter[0:0]
end
- attribute \src "ls180.v:1717.11-1717.45"
- process $proc$ls180.v:1717$3458
+ attribute \src "ls180.v:1713.11-1713.45"
+ process $proc$ls180.v:1713$3458
assign { } { }
assign $1\main_sdmem2block_fifo_level[5:0] 6'000000
sync always
sync init
update \main_sdmem2block_fifo_level $1\main_sdmem2block_fifo_level[5:0]
end
- attribute \src "ls180.v:1718.5-1718.41"
- process $proc$ls180.v:1718$3459
+ attribute \src "ls180.v:1714.5-1714.41"
+ process $proc$ls180.v:1714$3459
assign { } { }
assign $0\main_sdmem2block_fifo_replace[0:0] 1'0
sync always
update \main_sdmem2block_fifo_replace $0\main_sdmem2block_fifo_replace[0:0]
sync init
end
- attribute \src "ls180.v:1719.11-1719.47"
- process $proc$ls180.v:1719$3460
+ attribute \src "ls180.v:1715.11-1715.47"
+ process $proc$ls180.v:1715$3460
assign { } { }
assign $1\main_sdmem2block_fifo_produce[4:0] 5'00000
sync always
sync init
update \main_sdmem2block_fifo_produce $1\main_sdmem2block_fifo_produce[4:0]
end
- attribute \src "ls180.v:1720.11-1720.47"
- process $proc$ls180.v:1720$3461
+ attribute \src "ls180.v:1716.11-1716.47"
+ process $proc$ls180.v:1716$3461
assign { } { }
assign $1\main_sdmem2block_fifo_consume[4:0] 5'00000
sync always
sync init
update \main_sdmem2block_fifo_consume $1\main_sdmem2block_fifo_consume[4:0]
end
- attribute \src "ls180.v:1721.11-1721.50"
- process $proc$ls180.v:1721$3462
+ attribute \src "ls180.v:1717.11-1717.50"
+ process $proc$ls180.v:1717$3462
assign { } { }
assign $1\main_sdmem2block_fifo_wrport_adr[4:0] 5'00000
sync always
sync init
update \main_sdmem2block_fifo_wrport_adr $1\main_sdmem2block_fifo_wrport_adr[4:0]
end
- attribute \src "ls180.v:173.5-173.44"
- process $proc$ls180.v:173$2783
+ attribute \src "ls180.v:172.12-172.53"
+ process $proc$ls180.v:172$2785
assign { } { }
- assign $1\main_libresocsim_converter0_skip[0:0] 1'0
+ assign $1\main_libresocsim_converter0_dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
- update \main_libresocsim_converter0_skip $1\main_libresocsim_converter0_skip[0:0]
+ update \main_libresocsim_converter0_dat_r $1\main_libresocsim_converter0_dat_r[63:0]
end
- attribute \src "ls180.v:1734.5-1734.36"
- process $proc$ls180.v:1734$3463
+ attribute \src "ls180.v:173.12-173.71"
+ process $proc$ls180.v:173$2786
+ assign { } { }
+ assign $1\main_libresocsim_interface1_converted_interface_adr[29:0] 30'000000000000000000000000000000
+ sync always
+ sync init
+ update \main_libresocsim_interface1_converted_interface_adr $1\main_libresocsim_interface1_converted_interface_adr[29:0]
+ end
+ attribute \src "ls180.v:1730.5-1730.36"
+ process $proc$ls180.v:1730$3463
assign { } { }
assign $1\builder_converter0_state[0:0] 1'0
sync always
sync init
update \builder_converter0_state $1\builder_converter0_state[0:0]
end
- attribute \src "ls180.v:1735.5-1735.41"
- process $proc$ls180.v:1735$3464
+ attribute \src "ls180.v:1731.5-1731.41"
+ process $proc$ls180.v:1731$3464
assign { } { }
assign $1\builder_converter0_next_state[0:0] 1'0
sync always
sync init
update \builder_converter0_next_state $1\builder_converter0_next_state[0:0]
end
- attribute \src "ls180.v:1736.5-1736.69"
- process $proc$ls180.v:1736$3465
+ attribute \src "ls180.v:1732.5-1732.69"
+ process $proc$ls180.v:1732$3465
assign { } { }
assign $1\main_libresocsim_converter0_counter_converter0_next_value[0:0] 1'0
sync always
sync init
update \main_libresocsim_converter0_counter_converter0_next_value $1\main_libresocsim_converter0_counter_converter0_next_value[0:0]
end
- attribute \src "ls180.v:1737.5-1737.72"
- process $proc$ls180.v:1737$3466
+ attribute \src "ls180.v:1733.5-1733.72"
+ process $proc$ls180.v:1733$3466
assign { } { }
assign $1\main_libresocsim_converter0_counter_converter0_next_value_ce[0:0] 1'0
sync always
sync init
update \main_libresocsim_converter0_counter_converter0_next_value_ce $1\main_libresocsim_converter0_counter_converter0_next_value_ce[0:0]
end
- attribute \src "ls180.v:1738.5-1738.36"
- process $proc$ls180.v:1738$3467
+ attribute \src "ls180.v:1734.5-1734.36"
+ process $proc$ls180.v:1734$3467
assign { } { }
assign $1\builder_converter1_state[0:0] 1'0
sync always
sync init
update \builder_converter1_state $1\builder_converter1_state[0:0]
end
- attribute \src "ls180.v:1739.5-1739.41"
- process $proc$ls180.v:1739$3468
+ attribute \src "ls180.v:1735.5-1735.41"
+ process $proc$ls180.v:1735$3468
assign { } { }
assign $1\builder_converter1_next_state[0:0] 1'0
sync always
sync init
update \builder_converter1_next_state $1\builder_converter1_next_state[0:0]
end
- attribute \src "ls180.v:174.5-174.47"
- process $proc$ls180.v:174$2784
- assign { } { }
- assign $1\main_libresocsim_converter0_counter[0:0] 1'0
- sync always
- sync init
- update \main_libresocsim_converter0_counter $1\main_libresocsim_converter0_counter[0:0]
- end
- attribute \src "ls180.v:1740.5-1740.69"
- process $proc$ls180.v:1740$3469
+ attribute \src "ls180.v:1736.5-1736.69"
+ process $proc$ls180.v:1736$3469
assign { } { }
assign $1\main_libresocsim_converter1_counter_converter1_next_value[0:0] 1'0
sync always
sync init
update \main_libresocsim_converter1_counter_converter1_next_value $1\main_libresocsim_converter1_counter_converter1_next_value[0:0]
end
- attribute \src "ls180.v:1741.5-1741.72"
- process $proc$ls180.v:1741$3470
+ attribute \src "ls180.v:1737.5-1737.72"
+ process $proc$ls180.v:1737$3470
assign { } { }
assign $1\main_libresocsim_converter1_counter_converter1_next_value_ce[0:0] 1'0
sync always
sync init
update \main_libresocsim_converter1_counter_converter1_next_value_ce $1\main_libresocsim_converter1_counter_converter1_next_value_ce[0:0]
end
- attribute \src "ls180.v:1742.5-1742.36"
- process $proc$ls180.v:1742$3471
+ attribute \src "ls180.v:1738.5-1738.36"
+ process $proc$ls180.v:1738$3471
assign { } { }
assign $1\builder_converter2_state[0:0] 1'0
sync always
sync init
update \builder_converter2_state $1\builder_converter2_state[0:0]
end
- attribute \src "ls180.v:1743.5-1743.41"
- process $proc$ls180.v:1743$3472
+ attribute \src "ls180.v:1739.5-1739.41"
+ process $proc$ls180.v:1739$3472
assign { } { }
assign $1\builder_converter2_next_state[0:0] 1'0
sync always
sync init
update \builder_converter2_next_state $1\builder_converter2_next_state[0:0]
end
- attribute \src "ls180.v:1744.5-1744.69"
- process $proc$ls180.v:1744$3473
+ attribute \src "ls180.v:174.12-174.73"
+ process $proc$ls180.v:174$2787
+ assign { } { }
+ assign $1\main_libresocsim_interface1_converted_interface_dat_w[31:0] 0
+ sync always
+ sync init
+ update \main_libresocsim_interface1_converted_interface_dat_w $1\main_libresocsim_interface1_converted_interface_dat_w[31:0]
+ end
+ attribute \src "ls180.v:1740.5-1740.69"
+ process $proc$ls180.v:1740$3473
assign { } { }
assign $1\main_libresocsim_converter2_counter_converter2_next_value[0:0] 1'0
sync always
sync init
update \main_libresocsim_converter2_counter_converter2_next_value $1\main_libresocsim_converter2_counter_converter2_next_value[0:0]
end
- attribute \src "ls180.v:1745.5-1745.72"
- process $proc$ls180.v:1745$3474
+ attribute \src "ls180.v:1741.5-1741.72"
+ process $proc$ls180.v:1741$3474
assign { } { }
assign $1\main_libresocsim_converter2_counter_converter2_next_value_ce[0:0] 1'0
sync always
sync init
update \main_libresocsim_converter2_counter_converter2_next_value_ce $1\main_libresocsim_converter2_counter_converter2_next_value_ce[0:0]
end
- attribute \src "ls180.v:1746.11-1746.41"
- process $proc$ls180.v:1746$3475
+ attribute \src "ls180.v:1742.11-1742.41"
+ process $proc$ls180.v:1742$3475
assign { } { }
assign $1\builder_refresher_state[1:0] 2'00
sync always
sync init
update \builder_refresher_state $1\builder_refresher_state[1:0]
end
- attribute \src "ls180.v:1747.11-1747.46"
- process $proc$ls180.v:1747$3476
+ attribute \src "ls180.v:1743.11-1743.46"
+ process $proc$ls180.v:1743$3476
assign { } { }
assign $1\builder_refresher_next_state[1:0] 2'00
sync always
sync init
update \builder_refresher_next_state $1\builder_refresher_next_state[1:0]
end
- attribute \src "ls180.v:1748.11-1748.44"
- process $proc$ls180.v:1748$3477
+ attribute \src "ls180.v:1744.11-1744.44"
+ process $proc$ls180.v:1744$3477
assign { } { }
assign $1\builder_bankmachine0_state[2:0] 3'000
sync always
sync init
update \builder_bankmachine0_state $1\builder_bankmachine0_state[2:0]
end
- attribute \src "ls180.v:1749.11-1749.49"
- process $proc$ls180.v:1749$3478
+ attribute \src "ls180.v:1745.11-1745.49"
+ process $proc$ls180.v:1745$3478
assign { } { }
assign $1\builder_bankmachine0_next_state[2:0] 3'000
sync always
sync init
update \builder_bankmachine0_next_state $1\builder_bankmachine0_next_state[2:0]
end
- attribute \src "ls180.v:1750.11-1750.44"
- process $proc$ls180.v:1750$3479
+ attribute \src "ls180.v:1746.11-1746.44"
+ process $proc$ls180.v:1746$3479
assign { } { }
assign $1\builder_bankmachine1_state[2:0] 3'000
sync always
sync init
update \builder_bankmachine1_state $1\builder_bankmachine1_state[2:0]
end
- attribute \src "ls180.v:1751.11-1751.49"
- process $proc$ls180.v:1751$3480
+ attribute \src "ls180.v:1747.11-1747.49"
+ process $proc$ls180.v:1747$3480
assign { } { }
assign $1\builder_bankmachine1_next_state[2:0] 3'000
sync always
sync init
update \builder_bankmachine1_next_state $1\builder_bankmachine1_next_state[2:0]
end
- attribute \src "ls180.v:1752.11-1752.44"
- process $proc$ls180.v:1752$3481
+ attribute \src "ls180.v:1748.11-1748.44"
+ process $proc$ls180.v:1748$3481
assign { } { }
assign $1\builder_bankmachine2_state[2:0] 3'000
sync always
sync init
update \builder_bankmachine2_state $1\builder_bankmachine2_state[2:0]
end
- attribute \src "ls180.v:1753.11-1753.49"
- process $proc$ls180.v:1753$3482
+ attribute \src "ls180.v:1749.11-1749.49"
+ process $proc$ls180.v:1749$3482
assign { } { }
assign $1\builder_bankmachine2_next_state[2:0] 3'000
sync always
sync init
update \builder_bankmachine2_next_state $1\builder_bankmachine2_next_state[2:0]
end
- attribute \src "ls180.v:1754.11-1754.44"
- process $proc$ls180.v:1754$3483
+ attribute \src "ls180.v:1750.11-1750.44"
+ process $proc$ls180.v:1750$3483
assign { } { }
assign $1\builder_bankmachine3_state[2:0] 3'000
sync always
sync init
update \builder_bankmachine3_state $1\builder_bankmachine3_state[2:0]
end
- attribute \src "ls180.v:1755.11-1755.49"
- process $proc$ls180.v:1755$3484
+ attribute \src "ls180.v:1751.11-1751.49"
+ process $proc$ls180.v:1751$3484
assign { } { }
assign $1\builder_bankmachine3_next_state[2:0] 3'000
sync always
sync init
update \builder_bankmachine3_next_state $1\builder_bankmachine3_next_state[2:0]
end
- attribute \src "ls180.v:1756.11-1756.43"
- process $proc$ls180.v:1756$3485
+ attribute \src "ls180.v:1752.11-1752.43"
+ process $proc$ls180.v:1752$3485
assign { } { }
assign $1\builder_multiplexer_state[2:0] 3'000
sync always
sync init
update \builder_multiplexer_state $1\builder_multiplexer_state[2:0]
end
- attribute \src "ls180.v:1757.11-1757.48"
- process $proc$ls180.v:1757$3486
+ attribute \src "ls180.v:1753.11-1753.48"
+ process $proc$ls180.v:1753$3486
assign { } { }
assign $1\builder_multiplexer_next_state[2:0] 3'000
sync always
sync init
update \builder_multiplexer_next_state $1\builder_multiplexer_next_state[2:0]
end
- attribute \src "ls180.v:176.12-176.53"
- process $proc$ls180.v:176$2785
+ attribute \src "ls180.v:176.11-176.69"
+ process $proc$ls180.v:176$2788
assign { } { }
- assign $1\main_libresocsim_converter0_dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
- sync always
- sync init
- update \main_libresocsim_converter0_dat_r $1\main_libresocsim_converter0_dat_r[63:0]
- end
- attribute \src "ls180.v:177.12-177.71"
- process $proc$ls180.v:177$2786
- assign { } { }
- assign $1\main_libresocsim_interface1_converted_interface_adr[29:0] 30'000000000000000000000000000000
+ assign $1\main_libresocsim_interface1_converted_interface_sel[3:0] 4'0000
sync always
sync init
- update \main_libresocsim_interface1_converted_interface_adr $1\main_libresocsim_interface1_converted_interface_adr[29:0]
+ update \main_libresocsim_interface1_converted_interface_sel $1\main_libresocsim_interface1_converted_interface_sel[3:0]
end
- attribute \src "ls180.v:1770.5-1770.27"
- process $proc$ls180.v:1770$3487
+ attribute \src "ls180.v:1766.5-1766.27"
+ process $proc$ls180.v:1766$3487
assign { } { }
assign $0\builder_locked0[0:0] 1'0
sync always
update \builder_locked0 $0\builder_locked0[0:0]
sync init
end
- attribute \src "ls180.v:1771.5-1771.27"
- process $proc$ls180.v:1771$3488
+ attribute \src "ls180.v:1767.5-1767.27"
+ process $proc$ls180.v:1767$3488
assign { } { }
assign $0\builder_locked1[0:0] 1'0
sync always
update \builder_locked1 $0\builder_locked1[0:0]
sync init
end
- attribute \src "ls180.v:1772.5-1772.27"
- process $proc$ls180.v:1772$3489
+ attribute \src "ls180.v:1768.5-1768.27"
+ process $proc$ls180.v:1768$3489
assign { } { }
assign $0\builder_locked2[0:0] 1'0
sync always
update \builder_locked2 $0\builder_locked2[0:0]
sync init
end
- attribute \src "ls180.v:1773.5-1773.27"
- process $proc$ls180.v:1773$3490
+ attribute \src "ls180.v:1769.5-1769.27"
+ process $proc$ls180.v:1769$3490
assign { } { }
assign $0\builder_locked3[0:0] 1'0
sync always
update \builder_locked3 $0\builder_locked3[0:0]
sync init
end
- attribute \src "ls180.v:1774.5-1774.42"
- process $proc$ls180.v:1774$3491
+ attribute \src "ls180.v:177.5-177.63"
+ process $proc$ls180.v:177$2789
+ assign { } { }
+ assign $1\main_libresocsim_interface1_converted_interface_cyc[0:0] 1'0
+ sync always
+ sync init
+ update \main_libresocsim_interface1_converted_interface_cyc $1\main_libresocsim_interface1_converted_interface_cyc[0:0]
+ end
+ attribute \src "ls180.v:1770.5-1770.42"
+ process $proc$ls180.v:1770$3491
assign { } { }
assign $1\builder_new_master_wdata_ready[0:0] 1'0
sync always
sync init
update \builder_new_master_wdata_ready $1\builder_new_master_wdata_ready[0:0]
end
- attribute \src "ls180.v:1775.5-1775.43"
- process $proc$ls180.v:1775$3492
+ attribute \src "ls180.v:1771.5-1771.43"
+ process $proc$ls180.v:1771$3492
assign { } { }
assign $1\builder_new_master_rdata_valid0[0:0] 1'0
sync always
sync init
update \builder_new_master_rdata_valid0 $1\builder_new_master_rdata_valid0[0:0]
end
- attribute \src "ls180.v:1776.5-1776.43"
- process $proc$ls180.v:1776$3493
+ attribute \src "ls180.v:1772.5-1772.43"
+ process $proc$ls180.v:1772$3493
assign { } { }
assign $1\builder_new_master_rdata_valid1[0:0] 1'0
sync always
sync init
update \builder_new_master_rdata_valid1 $1\builder_new_master_rdata_valid1[0:0]
end
- attribute \src "ls180.v:1777.5-1777.43"
- process $proc$ls180.v:1777$3494
+ attribute \src "ls180.v:1773.5-1773.43"
+ process $proc$ls180.v:1773$3494
assign { } { }
assign $1\builder_new_master_rdata_valid2[0:0] 1'0
sync always
sync init
update \builder_new_master_rdata_valid2 $1\builder_new_master_rdata_valid2[0:0]
end
- attribute \src "ls180.v:1778.5-1778.43"
- process $proc$ls180.v:1778$3495
+ attribute \src "ls180.v:1774.5-1774.43"
+ process $proc$ls180.v:1774$3495
assign { } { }
assign $1\builder_new_master_rdata_valid3[0:0] 1'0
sync always
sync init
update \builder_new_master_rdata_valid3 $1\builder_new_master_rdata_valid3[0:0]
end
- attribute \src "ls180.v:1779.5-1779.35"
- process $proc$ls180.v:1779$3496
+ attribute \src "ls180.v:1775.5-1775.35"
+ process $proc$ls180.v:1775$3496
assign { } { }
assign $1\builder_converter_state[0:0] 1'0
sync always
sync init
update \builder_converter_state $1\builder_converter_state[0:0]
end
- attribute \src "ls180.v:178.12-178.73"
- process $proc$ls180.v:178$2787
- assign { } { }
- assign $1\main_libresocsim_interface1_converted_interface_dat_w[31:0] 0
- sync always
- sync init
- update \main_libresocsim_interface1_converted_interface_dat_w $1\main_libresocsim_interface1_converted_interface_dat_w[31:0]
- end
- attribute \src "ls180.v:1780.5-1780.40"
- process $proc$ls180.v:1780$3497
+ attribute \src "ls180.v:1776.5-1776.40"
+ process $proc$ls180.v:1776$3497
assign { } { }
assign $1\builder_converter_next_state[0:0] 1'0
sync always
sync init
update \builder_converter_next_state $1\builder_converter_next_state[0:0]
end
- attribute \src "ls180.v:1781.5-1781.55"
- process $proc$ls180.v:1781$3498
+ attribute \src "ls180.v:1777.5-1777.55"
+ process $proc$ls180.v:1777$3498
assign { } { }
assign $1\main_converter_counter_converter_next_value[0:0] 1'0
sync always
sync init
update \main_converter_counter_converter_next_value $1\main_converter_counter_converter_next_value[0:0]
end
- attribute \src "ls180.v:1782.5-1782.58"
- process $proc$ls180.v:1782$3499
+ attribute \src "ls180.v:1778.5-1778.58"
+ process $proc$ls180.v:1778$3499
assign { } { }
assign $1\main_converter_counter_converter_next_value_ce[0:0] 1'0
sync always
sync init
update \main_converter_counter_converter_next_value_ce $1\main_converter_counter_converter_next_value_ce[0:0]
end
- attribute \src "ls180.v:1783.11-1783.42"
- process $proc$ls180.v:1783$3500
+ attribute \src "ls180.v:1779.11-1779.42"
+ process $proc$ls180.v:1779$3500
assign { } { }
assign $1\builder_spimaster0_state[1:0] 2'00
sync always
sync init
update \builder_spimaster0_state $1\builder_spimaster0_state[1:0]
end
- attribute \src "ls180.v:1784.11-1784.47"
- process $proc$ls180.v:1784$3501
+ attribute \src "ls180.v:178.5-178.63"
+ process $proc$ls180.v:178$2790
+ assign { } { }
+ assign $1\main_libresocsim_interface1_converted_interface_stb[0:0] 1'0
+ sync always
+ sync init
+ update \main_libresocsim_interface1_converted_interface_stb $1\main_libresocsim_interface1_converted_interface_stb[0:0]
+ end
+ attribute \src "ls180.v:1780.11-1780.47"
+ process $proc$ls180.v:1780$3501
assign { } { }
assign $1\builder_spimaster0_next_state[1:0] 2'00
sync always
sync init
update \builder_spimaster0_next_state $1\builder_spimaster0_next_state[1:0]
end
- attribute \src "ls180.v:1785.11-1785.62"
- process $proc$ls180.v:1785$3502
+ attribute \src "ls180.v:1781.11-1781.62"
+ process $proc$ls180.v:1781$3502
assign { } { }
assign $1\main_spimaster27_count_spimaster0_next_value[2:0] 3'000
sync always
sync init
update \main_spimaster27_count_spimaster0_next_value $1\main_spimaster27_count_spimaster0_next_value[2:0]
end
- attribute \src "ls180.v:1786.5-1786.59"
- process $proc$ls180.v:1786$3503
+ attribute \src "ls180.v:1782.5-1782.59"
+ process $proc$ls180.v:1782$3503
assign { } { }
assign $1\main_spimaster27_count_spimaster0_next_value_ce[0:0] 1'0
sync always
sync init
update \main_spimaster27_count_spimaster0_next_value_ce $1\main_spimaster27_count_spimaster0_next_value_ce[0:0]
end
- attribute \src "ls180.v:1787.11-1787.42"
- process $proc$ls180.v:1787$3504
+ attribute \src "ls180.v:1783.11-1783.42"
+ process $proc$ls180.v:1783$3504
assign { } { }
assign $1\builder_spimaster1_state[1:0] 2'00
sync always
sync init
update \builder_spimaster1_state $1\builder_spimaster1_state[1:0]
end
- attribute \src "ls180.v:1788.11-1788.47"
- process $proc$ls180.v:1788$3505
+ attribute \src "ls180.v:1784.11-1784.47"
+ process $proc$ls180.v:1784$3505
assign { } { }
assign $1\builder_spimaster1_next_state[1:0] 2'00
sync always
sync init
update \builder_spimaster1_next_state $1\builder_spimaster1_next_state[1:0]
end
- attribute \src "ls180.v:1789.11-1789.60"
- process $proc$ls180.v:1789$3506
+ attribute \src "ls180.v:1785.11-1785.60"
+ process $proc$ls180.v:1785$3506
assign { } { }
assign $1\main_spisdcard_count_spimaster1_next_value[2:0] 3'000
sync always
sync init
update \main_spisdcard_count_spimaster1_next_value $1\main_spisdcard_count_spimaster1_next_value[2:0]
end
- attribute \src "ls180.v:1790.5-1790.57"
- process $proc$ls180.v:1790$3507
+ attribute \src "ls180.v:1786.5-1786.57"
+ process $proc$ls180.v:1786$3507
assign { } { }
assign $1\main_spisdcard_count_spimaster1_next_value_ce[0:0] 1'0
sync always
sync init
update \main_spisdcard_count_spimaster1_next_value_ce $1\main_spisdcard_count_spimaster1_next_value_ce[0:0]
end
- attribute \src "ls180.v:1791.5-1791.41"
- process $proc$ls180.v:1791$3508
+ attribute \src "ls180.v:1787.5-1787.41"
+ process $proc$ls180.v:1787$3508
assign { } { }
assign $1\builder_sdphy_sdphyinit_state[0:0] 1'0
sync always
sync init
update \builder_sdphy_sdphyinit_state $1\builder_sdphy_sdphyinit_state[0:0]
end
- attribute \src "ls180.v:1792.5-1792.46"
- process $proc$ls180.v:1792$3509
+ attribute \src "ls180.v:1788.5-1788.46"
+ process $proc$ls180.v:1788$3509
assign { } { }
assign $1\builder_sdphy_sdphyinit_next_state[0:0] 1'0
sync always
sync init
update \builder_sdphy_sdphyinit_next_state $1\builder_sdphy_sdphyinit_next_state[0:0]
end
- attribute \src "ls180.v:1793.11-1793.66"
- process $proc$ls180.v:1793$3510
+ attribute \src "ls180.v:1789.11-1789.66"
+ process $proc$ls180.v:1789$3510
assign { } { }
assign $1\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] 8'00000000
sync always
sync init
update \main_sdphy_init_count_sdphy_sdphyinit_next_value $1\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0]
end
- attribute \src "ls180.v:1794.5-1794.63"
- process $proc$ls180.v:1794$3511
+ attribute \src "ls180.v:1790.5-1790.63"
+ process $proc$ls180.v:1790$3511
assign { } { }
assign $1\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] 1'0
sync always
sync init
update \main_sdphy_init_count_sdphy_sdphyinit_next_value_ce $1\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0]
end
- attribute \src "ls180.v:1795.11-1795.47"
- process $proc$ls180.v:1795$3512
+ attribute \src "ls180.v:1791.11-1791.47"
+ process $proc$ls180.v:1791$3512
assign { } { }
assign $1\builder_sdphy_sdphycmdw_state[1:0] 2'00
sync always
sync init
update \builder_sdphy_sdphycmdw_state $1\builder_sdphy_sdphycmdw_state[1:0]
end
- attribute \src "ls180.v:1796.11-1796.52"
- process $proc$ls180.v:1796$3513
+ attribute \src "ls180.v:1792.11-1792.52"
+ process $proc$ls180.v:1792$3513
assign { } { }
assign $1\builder_sdphy_sdphycmdw_next_state[1:0] 2'00
sync always
sync init
update \builder_sdphy_sdphycmdw_next_state $1\builder_sdphy_sdphycmdw_next_state[1:0]
end
- attribute \src "ls180.v:1797.11-1797.66"
- process $proc$ls180.v:1797$3514
+ attribute \src "ls180.v:1793.11-1793.66"
+ process $proc$ls180.v:1793$3514
assign { } { }
assign $1\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] 8'00000000
sync always
sync init
update \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value $1\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0]
end
- attribute \src "ls180.v:1798.5-1798.63"
- process $proc$ls180.v:1798$3515
+ attribute \src "ls180.v:1794.5-1794.63"
+ process $proc$ls180.v:1794$3515
assign { } { }
assign $1\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] 1'0
sync always
sync init
update \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce $1\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0]
end
- attribute \src "ls180.v:1799.11-1799.47"
- process $proc$ls180.v:1799$3516
+ attribute \src "ls180.v:1795.11-1795.47"
+ process $proc$ls180.v:1795$3516
assign { } { }
assign $1\builder_sdphy_sdphycmdr_state[2:0] 3'000
sync always
sync init
update \builder_sdphy_sdphycmdr_state $1\builder_sdphy_sdphycmdr_state[2:0]
end
- attribute \src "ls180.v:180.11-180.69"
- process $proc$ls180.v:180$2788
- assign { } { }
- assign $1\main_libresocsim_interface1_converted_interface_sel[3:0] 4'0000
- sync always
- sync init
- update \main_libresocsim_interface1_converted_interface_sel $1\main_libresocsim_interface1_converted_interface_sel[3:0]
- end
- attribute \src "ls180.v:1800.11-1800.52"
- process $proc$ls180.v:1800$3517
+ attribute \src "ls180.v:1796.11-1796.52"
+ process $proc$ls180.v:1796$3517
assign { } { }
assign $1\builder_sdphy_sdphycmdr_next_state[2:0] 3'000
sync always
sync init
update \builder_sdphy_sdphycmdr_next_state $1\builder_sdphy_sdphycmdr_next_state[2:0]
end
- attribute \src "ls180.v:1801.11-1801.67"
- process $proc$ls180.v:1801$3518
+ attribute \src "ls180.v:1797.11-1797.67"
+ process $proc$ls180.v:1797$3518
assign { } { }
assign $1\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] 8'00000000
sync always
sync init
update \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0 $1\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0]
end
- attribute \src "ls180.v:1802.5-1802.64"
- process $proc$ls180.v:1802$3519
+ attribute \src "ls180.v:1798.5-1798.64"
+ process $proc$ls180.v:1798$3519
assign { } { }
assign $1\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] 1'0
sync always
sync init
update \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0 $1\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0]
end
- attribute \src "ls180.v:1803.12-1803.71"
- process $proc$ls180.v:1803$3520
+ attribute \src "ls180.v:1799.12-1799.71"
+ process $proc$ls180.v:1799$3520
assign { } { }
assign $1\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] 0
sync always
sync init
update \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1 $1\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0]
end
- attribute \src "ls180.v:1804.5-1804.66"
- process $proc$ls180.v:1804$3521
+ attribute \src "ls180.v:180.5-180.62"
+ process $proc$ls180.v:180$2791
+ assign { } { }
+ assign $1\main_libresocsim_interface1_converted_interface_we[0:0] 1'0
+ sync always
+ sync init
+ update \main_libresocsim_interface1_converted_interface_we $1\main_libresocsim_interface1_converted_interface_we[0:0]
+ end
+ attribute \src "ls180.v:1800.5-1800.66"
+ process $proc$ls180.v:1800$3521
assign { } { }
assign $1\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] 1'0
sync always
sync init
update \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1 $1\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0]
end
- attribute \src "ls180.v:1805.5-1805.66"
- process $proc$ls180.v:1805$3522
+ attribute \src "ls180.v:1801.5-1801.66"
+ process $proc$ls180.v:1801$3522
assign { } { }
assign $1\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] 1'0
sync always
sync init
update \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2 $1\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0]
end
- attribute \src "ls180.v:1806.5-1806.69"
- process $proc$ls180.v:1806$3523
+ attribute \src "ls180.v:1802.5-1802.69"
+ process $proc$ls180.v:1802$3523
assign { } { }
assign $1\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] 1'0
sync always
sync init
update \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2 $1\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0]
end
- attribute \src "ls180.v:1807.5-1807.41"
- process $proc$ls180.v:1807$3524
+ attribute \src "ls180.v:1803.5-1803.41"
+ process $proc$ls180.v:1803$3524
assign { } { }
assign $1\builder_sdphy_sdphycrcr_state[0:0] 1'0
sync always
sync init
update \builder_sdphy_sdphycrcr_state $1\builder_sdphy_sdphycrcr_state[0:0]
end
- attribute \src "ls180.v:1808.5-1808.46"
- process $proc$ls180.v:1808$3525
+ attribute \src "ls180.v:1804.5-1804.46"
+ process $proc$ls180.v:1804$3525
assign { } { }
assign $1\builder_sdphy_sdphycrcr_next_state[0:0] 1'0
sync always
sync init
update \builder_sdphy_sdphycrcr_next_state $1\builder_sdphy_sdphycrcr_next_state[0:0]
end
- attribute \src "ls180.v:1809.5-1809.66"
- process $proc$ls180.v:1809$3526
+ attribute \src "ls180.v:1805.5-1805.66"
+ process $proc$ls180.v:1805$3526
assign { } { }
assign $1\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] 1'0
sync always
sync init
update \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value $1\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0]
end
- attribute \src "ls180.v:181.5-181.63"
- process $proc$ls180.v:181$2789
- assign { } { }
- assign $1\main_libresocsim_interface1_converted_interface_cyc[0:0] 1'0
- sync always
- sync init
- update \main_libresocsim_interface1_converted_interface_cyc $1\main_libresocsim_interface1_converted_interface_cyc[0:0]
- end
- attribute \src "ls180.v:1810.5-1810.69"
- process $proc$ls180.v:1810$3527
+ attribute \src "ls180.v:1806.5-1806.69"
+ process $proc$ls180.v:1806$3527
assign { } { }
assign $1\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] 1'0
sync always
sync init
update \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce $1\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0]
end
- attribute \src "ls180.v:1811.11-1811.41"
- process $proc$ls180.v:1811$3528
+ attribute \src "ls180.v:1807.11-1807.41"
+ process $proc$ls180.v:1807$3528
assign { } { }
assign $1\builder_sdphy_fsm_state[2:0] 3'000
sync always
sync init
update \builder_sdphy_fsm_state $1\builder_sdphy_fsm_state[2:0]
end
- attribute \src "ls180.v:1812.11-1812.46"
- process $proc$ls180.v:1812$3529
+ attribute \src "ls180.v:1808.11-1808.46"
+ process $proc$ls180.v:1808$3529
assign { } { }
assign $1\builder_sdphy_fsm_next_state[2:0] 3'000
sync always
sync init
update \builder_sdphy_fsm_next_state $1\builder_sdphy_fsm_next_state[2:0]
end
- attribute \src "ls180.v:1813.11-1813.61"
- process $proc$ls180.v:1813$3530
+ attribute \src "ls180.v:1809.11-1809.61"
+ process $proc$ls180.v:1809$3530
assign { } { }
assign $1\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] 8'00000000
sync always
sync init
update \main_sdphy_dataw_count_sdphy_fsm_next_value $1\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0]
end
- attribute \src "ls180.v:1814.5-1814.58"
- process $proc$ls180.v:1814$3531
+ attribute \src "ls180.v:181.11-181.69"
+ process $proc$ls180.v:181$2792
+ assign { } { }
+ assign $0\main_libresocsim_interface1_converted_interface_cti[2:0] 3'000
+ sync always
+ update \main_libresocsim_interface1_converted_interface_cti $0\main_libresocsim_interface1_converted_interface_cti[2:0]
+ sync init
+ end
+ attribute \src "ls180.v:1810.5-1810.58"
+ process $proc$ls180.v:1810$3531
assign { } { }
assign $1\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] 1'0
sync always
sync init
update \main_sdphy_dataw_count_sdphy_fsm_next_value_ce $1\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0]
end
- attribute \src "ls180.v:1815.11-1815.48"
- process $proc$ls180.v:1815$3532
+ attribute \src "ls180.v:1811.11-1811.48"
+ process $proc$ls180.v:1811$3532
assign { } { }
assign $1\builder_sdphy_sdphydatar_state[2:0] 3'000
sync always
sync init
update \builder_sdphy_sdphydatar_state $1\builder_sdphy_sdphydatar_state[2:0]
end
- attribute \src "ls180.v:1816.11-1816.53"
- process $proc$ls180.v:1816$3533
+ attribute \src "ls180.v:1812.11-1812.53"
+ process $proc$ls180.v:1812$3533
assign { } { }
assign $1\builder_sdphy_sdphydatar_next_state[2:0] 3'000
sync always
sync init
update \builder_sdphy_sdphydatar_next_state $1\builder_sdphy_sdphydatar_next_state[2:0]
end
- attribute \src "ls180.v:1817.11-1817.70"
- process $proc$ls180.v:1817$3534
+ attribute \src "ls180.v:1813.11-1813.70"
+ process $proc$ls180.v:1813$3534
assign { } { }
assign $1\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] 10'0000000000
sync always
sync init
update \main_sdphy_datar_count_sdphy_sdphydatar_next_value0 $1\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0]
end
- attribute \src "ls180.v:1818.5-1818.66"
- process $proc$ls180.v:1818$3535
+ attribute \src "ls180.v:1814.5-1814.66"
+ process $proc$ls180.v:1814$3535
assign { } { }
assign $1\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'0
sync always
sync init
update \main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0 $1\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0]
end
- attribute \src "ls180.v:1819.12-1819.73"
- process $proc$ls180.v:1819$3536
+ attribute \src "ls180.v:1815.12-1815.73"
+ process $proc$ls180.v:1815$3536
assign { } { }
assign $1\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] 0
sync always
sync init
update \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1 $1\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0]
end
- attribute \src "ls180.v:182.5-182.63"
- process $proc$ls180.v:182$2790
- assign { } { }
- assign $1\main_libresocsim_interface1_converted_interface_stb[0:0] 1'0
- sync always
- sync init
- update \main_libresocsim_interface1_converted_interface_stb $1\main_libresocsim_interface1_converted_interface_stb[0:0]
- end
- attribute \src "ls180.v:1820.5-1820.68"
- process $proc$ls180.v:1820$3537
+ attribute \src "ls180.v:1816.5-1816.68"
+ process $proc$ls180.v:1816$3537
assign { } { }
assign $1\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] 1'0
sync always
sync init
update \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1 $1\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0]
end
- attribute \src "ls180.v:1821.5-1821.69"
- process $proc$ls180.v:1821$3538
+ attribute \src "ls180.v:1817.5-1817.69"
+ process $proc$ls180.v:1817$3538
assign { } { }
assign $1\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] 1'0
sync always
sync init
update \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2 $1\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0]
end
- attribute \src "ls180.v:1822.5-1822.72"
- process $proc$ls180.v:1822$3539
+ attribute \src "ls180.v:1818.5-1818.72"
+ process $proc$ls180.v:1818$3539
assign { } { }
assign $1\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] 1'0
sync always
sync init
update \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2 $1\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0]
end
- attribute \src "ls180.v:1823.5-1823.52"
- process $proc$ls180.v:1823$3540
+ attribute \src "ls180.v:1819.5-1819.52"
+ process $proc$ls180.v:1819$3540
assign { } { }
assign $1\builder_sdcore_crcupstreaminserter_state[0:0] 1'0
sync always
sync init
update \builder_sdcore_crcupstreaminserter_state $1\builder_sdcore_crcupstreaminserter_state[0:0]
end
- attribute \src "ls180.v:1824.5-1824.57"
- process $proc$ls180.v:1824$3541
+ attribute \src "ls180.v:182.11-182.69"
+ process $proc$ls180.v:182$2793
+ assign { } { }
+ assign $0\main_libresocsim_interface1_converted_interface_bte[1:0] 2'00
+ sync always
+ update \main_libresocsim_interface1_converted_interface_bte $0\main_libresocsim_interface1_converted_interface_bte[1:0]
+ sync init
+ end
+ attribute \src "ls180.v:1820.5-1820.57"
+ process $proc$ls180.v:1820$3541
assign { } { }
assign $1\builder_sdcore_crcupstreaminserter_next_state[0:0] 1'0
sync always
sync init
update \builder_sdcore_crcupstreaminserter_next_state $1\builder_sdcore_crcupstreaminserter_next_state[0:0]
end
- attribute \src "ls180.v:1825.12-1825.93"
- process $proc$ls180.v:1825$3542
+ attribute \src "ls180.v:1821.12-1821.93"
+ process $proc$ls180.v:1821$3542
assign { } { }
assign $1\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0] 16'0000000000000000
sync always
sync init
update \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0 $1\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0]
end
- attribute \src "ls180.v:1826.5-1826.88"
- process $proc$ls180.v:1826$3543
+ attribute \src "ls180.v:1822.5-1822.88"
+ process $proc$ls180.v:1822$3543
assign { } { }
assign $1\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0] 1'0
sync always
sync init
update \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0 $1\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0]
end
- attribute \src "ls180.v:1827.12-1827.93"
- process $proc$ls180.v:1827$3544
+ attribute \src "ls180.v:1823.12-1823.93"
+ process $proc$ls180.v:1823$3544
assign { } { }
assign $1\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0] 16'0000000000000000
sync always
sync init
update \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1 $1\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0]
end
- attribute \src "ls180.v:1828.5-1828.88"
- process $proc$ls180.v:1828$3545
+ attribute \src "ls180.v:1824.5-1824.88"
+ process $proc$ls180.v:1824$3545
assign { } { }
assign $1\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0] 1'0
sync always
sync init
update \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1 $1\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0]
end
- attribute \src "ls180.v:1829.12-1829.93"
- process $proc$ls180.v:1829$3546
+ attribute \src "ls180.v:1825.12-1825.93"
+ process $proc$ls180.v:1825$3546
assign { } { }
assign $1\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0] 16'0000000000000000
sync always
sync init
update \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2 $1\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0]
end
- attribute \src "ls180.v:1830.5-1830.88"
- process $proc$ls180.v:1830$3547
+ attribute \src "ls180.v:1826.5-1826.88"
+ process $proc$ls180.v:1826$3547
assign { } { }
assign $1\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0] 1'0
sync always
sync init
update \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2 $1\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0]
end
- attribute \src "ls180.v:1831.12-1831.93"
- process $proc$ls180.v:1831$3548
+ attribute \src "ls180.v:1827.12-1827.93"
+ process $proc$ls180.v:1827$3548
assign { } { }
assign $1\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] 16'0000000000000000
sync always
sync init
update \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3 $1\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0]
end
- attribute \src "ls180.v:1832.5-1832.88"
- process $proc$ls180.v:1832$3549
+ attribute \src "ls180.v:1828.5-1828.88"
+ process $proc$ls180.v:1828$3549
assign { } { }
assign $1\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] 1'0
sync always
sync init
update \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3 $1\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0]
end
- attribute \src "ls180.v:1833.11-1833.87"
- process $proc$ls180.v:1833$3550
+ attribute \src "ls180.v:1829.11-1829.87"
+ process $proc$ls180.v:1829$3550
assign { } { }
assign $1\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] 3'000
sync always
sync init
update \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4 $1\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0]
end
- attribute \src "ls180.v:1834.5-1834.84"
- process $proc$ls180.v:1834$3551
+ attribute \src "ls180.v:1830.5-1830.84"
+ process $proc$ls180.v:1830$3551
assign { } { }
assign $1\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] 1'0
sync always
sync init
update \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4 $1\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0]
end
- attribute \src "ls180.v:1835.11-1835.42"
- process $proc$ls180.v:1835$3552
+ attribute \src "ls180.v:1831.11-1831.42"
+ process $proc$ls180.v:1831$3552
assign { } { }
assign $1\builder_sdcore_fsm_state[2:0] 3'000
sync always
sync init
update \builder_sdcore_fsm_state $1\builder_sdcore_fsm_state[2:0]
end
- attribute \src "ls180.v:1836.11-1836.47"
- process $proc$ls180.v:1836$3553
+ attribute \src "ls180.v:1832.11-1832.47"
+ process $proc$ls180.v:1832$3553
assign { } { }
assign $1\builder_sdcore_fsm_next_state[2:0] 3'000
sync always
sync init
update \builder_sdcore_fsm_next_state $1\builder_sdcore_fsm_next_state[2:0]
end
- attribute \src "ls180.v:1837.5-1837.55"
- process $proc$ls180.v:1837$3554
+ attribute \src "ls180.v:1833.5-1833.55"
+ process $proc$ls180.v:1833$3554
assign { } { }
assign $1\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] 1'0
sync always
sync init
update \main_sdcore_cmd_done_sdcore_fsm_next_value0 $1\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0]
end
- attribute \src "ls180.v:1838.5-1838.58"
- process $proc$ls180.v:1838$3555
+ attribute \src "ls180.v:1834.5-1834.58"
+ process $proc$ls180.v:1834$3555
assign { } { }
assign $1\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] 1'0
sync always
sync init
update \main_sdcore_cmd_done_sdcore_fsm_next_value_ce0 $1\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0]
end
- attribute \src "ls180.v:1839.5-1839.56"
- process $proc$ls180.v:1839$3556
+ attribute \src "ls180.v:1835.5-1835.56"
+ process $proc$ls180.v:1835$3556
assign { } { }
assign $1\main_sdcore_data_done_sdcore_fsm_next_value1[0:0] 1'0
sync always
sync init
update \main_sdcore_data_done_sdcore_fsm_next_value1 $1\main_sdcore_data_done_sdcore_fsm_next_value1[0:0]
end
- attribute \src "ls180.v:184.5-184.62"
- process $proc$ls180.v:184$2791
- assign { } { }
- assign $1\main_libresocsim_interface1_converted_interface_we[0:0] 1'0
- sync always
- sync init
- update \main_libresocsim_interface1_converted_interface_we $1\main_libresocsim_interface1_converted_interface_we[0:0]
- end
- attribute \src "ls180.v:1840.5-1840.59"
- process $proc$ls180.v:1840$3557
+ attribute \src "ls180.v:1836.5-1836.59"
+ process $proc$ls180.v:1836$3557
assign { } { }
assign $1\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] 1'0
sync always
sync init
update \main_sdcore_data_done_sdcore_fsm_next_value_ce1 $1\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0]
end
- attribute \src "ls180.v:1841.11-1841.62"
- process $proc$ls180.v:1841$3558
+ attribute \src "ls180.v:1837.11-1837.62"
+ process $proc$ls180.v:1837$3558
assign { } { }
assign $1\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] 3'000
sync always
sync init
update \main_sdcore_cmd_count_sdcore_fsm_next_value2 $1\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0]
end
- attribute \src "ls180.v:1842.5-1842.59"
- process $proc$ls180.v:1842$3559
+ attribute \src "ls180.v:1838.5-1838.59"
+ process $proc$ls180.v:1838$3559
assign { } { }
assign $1\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] 1'0
sync always
sync init
update \main_sdcore_cmd_count_sdcore_fsm_next_value_ce2 $1\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0]
end
- attribute \src "ls180.v:1843.12-1843.65"
- process $proc$ls180.v:1843$3560
+ attribute \src "ls180.v:1839.12-1839.65"
+ process $proc$ls180.v:1839$3560
assign { } { }
assign $1\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] 0
sync always
sync init
update \main_sdcore_data_count_sdcore_fsm_next_value3 $1\main_sdcore_data_count_sdcore_fsm_next_value3[31:0]
end
- attribute \src "ls180.v:1844.5-1844.60"
- process $proc$ls180.v:1844$3561
+ attribute \src "ls180.v:184.5-184.44"
+ process $proc$ls180.v:184$2794
+ assign { } { }
+ assign $1\main_libresocsim_converter1_skip[0:0] 1'0
+ sync always
+ sync init
+ update \main_libresocsim_converter1_skip $1\main_libresocsim_converter1_skip[0:0]
+ end
+ attribute \src "ls180.v:1840.5-1840.60"
+ process $proc$ls180.v:1840$3561
assign { } { }
assign $1\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] 1'0
sync always
sync init
update \main_sdcore_data_count_sdcore_fsm_next_value_ce3 $1\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0]
end
- attribute \src "ls180.v:1845.5-1845.56"
- process $proc$ls180.v:1845$3562
+ attribute \src "ls180.v:1841.5-1841.56"
+ process $proc$ls180.v:1841$3562
assign { } { }
assign $1\main_sdcore_cmd_error_sdcore_fsm_next_value4[0:0] 1'0
sync always
sync init
update \main_sdcore_cmd_error_sdcore_fsm_next_value4 $1\main_sdcore_cmd_error_sdcore_fsm_next_value4[0:0]
end
- attribute \src "ls180.v:1846.5-1846.59"
- process $proc$ls180.v:1846$3563
+ attribute \src "ls180.v:1842.5-1842.59"
+ process $proc$ls180.v:1842$3563
assign { } { }
assign $1\main_sdcore_cmd_error_sdcore_fsm_next_value_ce4[0:0] 1'0
sync always
sync init
update \main_sdcore_cmd_error_sdcore_fsm_next_value_ce4 $1\main_sdcore_cmd_error_sdcore_fsm_next_value_ce4[0:0]
end
- attribute \src "ls180.v:1847.5-1847.58"
- process $proc$ls180.v:1847$3564
+ attribute \src "ls180.v:1843.5-1843.58"
+ process $proc$ls180.v:1843$3564
assign { } { }
assign $1\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] 1'0
sync always
sync init
update \main_sdcore_cmd_timeout_sdcore_fsm_next_value5 $1\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0]
end
- attribute \src "ls180.v:1848.5-1848.61"
- process $proc$ls180.v:1848$3565
+ attribute \src "ls180.v:1844.5-1844.61"
+ process $proc$ls180.v:1844$3565
assign { } { }
assign $1\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] 1'0
sync always
sync init
update \main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5 $1\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0]
end
- attribute \src "ls180.v:1849.5-1849.57"
- process $proc$ls180.v:1849$3566
+ attribute \src "ls180.v:1845.5-1845.57"
+ process $proc$ls180.v:1845$3566
assign { } { }
assign $1\main_sdcore_data_error_sdcore_fsm_next_value6[0:0] 1'0
sync always
sync init
update \main_sdcore_data_error_sdcore_fsm_next_value6 $1\main_sdcore_data_error_sdcore_fsm_next_value6[0:0]
end
- attribute \src "ls180.v:185.11-185.69"
- process $proc$ls180.v:185$2792
- assign { } { }
- assign $0\main_libresocsim_interface1_converted_interface_cti[2:0] 3'000
- sync always
- update \main_libresocsim_interface1_converted_interface_cti $0\main_libresocsim_interface1_converted_interface_cti[2:0]
- sync init
- end
- attribute \src "ls180.v:1850.5-1850.60"
- process $proc$ls180.v:1850$3567
+ attribute \src "ls180.v:1846.5-1846.60"
+ process $proc$ls180.v:1846$3567
assign { } { }
assign $1\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] 1'0
sync always
sync init
update \main_sdcore_data_error_sdcore_fsm_next_value_ce6 $1\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0]
end
- attribute \src "ls180.v:1851.5-1851.59"
- process $proc$ls180.v:1851$3568
+ attribute \src "ls180.v:1847.5-1847.59"
+ process $proc$ls180.v:1847$3568
assign { } { }
assign $1\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] 1'0
sync always
sync init
update \main_sdcore_data_timeout_sdcore_fsm_next_value7 $1\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0]
end
- attribute \src "ls180.v:1852.5-1852.62"
- process $proc$ls180.v:1852$3569
+ attribute \src "ls180.v:1848.5-1848.62"
+ process $proc$ls180.v:1848$3569
assign { } { }
assign $1\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] 1'0
sync always
sync init
update \main_sdcore_data_timeout_sdcore_fsm_next_value_ce7 $1\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0]
end
- attribute \src "ls180.v:1853.13-1853.76"
- process $proc$ls180.v:1853$3570
+ attribute \src "ls180.v:1849.13-1849.76"
+ process $proc$ls180.v:1849$3570
assign { } { }
assign $1\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \main_sdcore_cmd_response_status_sdcore_fsm_next_value8 $1\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0]
end
- attribute \src "ls180.v:1854.5-1854.69"
- process $proc$ls180.v:1854$3571
+ attribute \src "ls180.v:185.5-185.47"
+ process $proc$ls180.v:185$2795
+ assign { } { }
+ assign $1\main_libresocsim_converter1_counter[0:0] 1'0
+ sync always
+ sync init
+ update \main_libresocsim_converter1_counter $1\main_libresocsim_converter1_counter[0:0]
+ end
+ attribute \src "ls180.v:1850.5-1850.69"
+ process $proc$ls180.v:1850$3571
assign { } { }
assign $1\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] 1'0
sync always
sync init
update \main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8 $1\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0]
end
- attribute \src "ls180.v:1855.11-1855.46"
- process $proc$ls180.v:1855$3572
+ attribute \src "ls180.v:1851.11-1851.46"
+ process $proc$ls180.v:1851$3572
assign { } { }
assign $1\builder_sdblock2memdma_state[1:0] 2'00
sync always
sync init
update \builder_sdblock2memdma_state $1\builder_sdblock2memdma_state[1:0]
end
- attribute \src "ls180.v:1856.11-1856.51"
- process $proc$ls180.v:1856$3573
+ attribute \src "ls180.v:1852.11-1852.51"
+ process $proc$ls180.v:1852$3573
assign { } { }
assign $1\builder_sdblock2memdma_next_state[1:0] 2'00
sync always
sync init
update \builder_sdblock2memdma_next_state $1\builder_sdblock2memdma_next_state[1:0]
end
- attribute \src "ls180.v:1857.12-1857.87"
- process $proc$ls180.v:1857$3574
+ attribute \src "ls180.v:1853.12-1853.87"
+ process $proc$ls180.v:1853$3574
assign { } { }
assign $1\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] 0
sync always
sync init
update \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value $1\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0]
end
- attribute \src "ls180.v:1858.5-1858.82"
- process $proc$ls180.v:1858$3575
+ attribute \src "ls180.v:1854.5-1854.82"
+ process $proc$ls180.v:1854$3575
assign { } { }
assign $1\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] 1'0
sync always
sync init
update \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce $1\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0]
end
- attribute \src "ls180.v:1859.5-1859.44"
- process $proc$ls180.v:1859$3576
+ attribute \src "ls180.v:1855.5-1855.44"
+ process $proc$ls180.v:1855$3576
assign { } { }
assign $1\builder_sdmem2blockdma_fsm_state[0:0] 1'0
sync always
sync init
update \builder_sdmem2blockdma_fsm_state $1\builder_sdmem2blockdma_fsm_state[0:0]
end
- attribute \src "ls180.v:186.11-186.69"
- process $proc$ls180.v:186$2793
- assign { } { }
- assign $0\main_libresocsim_interface1_converted_interface_bte[1:0] 2'00
- sync always
- update \main_libresocsim_interface1_converted_interface_bte $0\main_libresocsim_interface1_converted_interface_bte[1:0]
- sync init
- end
- attribute \src "ls180.v:1860.5-1860.49"
- process $proc$ls180.v:1860$3577
+ attribute \src "ls180.v:1856.5-1856.49"
+ process $proc$ls180.v:1856$3577
assign { } { }
assign $1\builder_sdmem2blockdma_fsm_next_state[0:0] 1'0
sync always
sync init
update \builder_sdmem2blockdma_fsm_next_state $1\builder_sdmem2blockdma_fsm_next_state[0:0]
end
- attribute \src "ls180.v:1861.12-1861.75"
- process $proc$ls180.v:1861$3578
+ attribute \src "ls180.v:1857.12-1857.75"
+ process $proc$ls180.v:1857$3578
assign { } { }
assign $1\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[31:0] 0
sync always
sync init
update \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value $1\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[31:0]
end
- attribute \src "ls180.v:1862.5-1862.70"
- process $proc$ls180.v:1862$3579
+ attribute \src "ls180.v:1858.5-1858.70"
+ process $proc$ls180.v:1858$3579
assign { } { }
assign $1\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] 1'0
sync always
sync init
update \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce $1\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0]
end
- attribute \src "ls180.v:1863.11-1863.60"
- process $proc$ls180.v:1863$3580
+ attribute \src "ls180.v:1859.11-1859.60"
+ process $proc$ls180.v:1859$3580
assign { } { }
assign $1\builder_sdmem2blockdma_resetinserter_state[1:0] 2'00
sync always
sync init
update \builder_sdmem2blockdma_resetinserter_state $1\builder_sdmem2blockdma_resetinserter_state[1:0]
end
- attribute \src "ls180.v:1864.11-1864.65"
- process $proc$ls180.v:1864$3581
+ attribute \src "ls180.v:1860.11-1860.65"
+ process $proc$ls180.v:1860$3581
assign { } { }
assign $1\builder_sdmem2blockdma_resetinserter_next_state[1:0] 2'00
sync always
sync init
update \builder_sdmem2blockdma_resetinserter_next_state $1\builder_sdmem2blockdma_resetinserter_next_state[1:0]
end
- attribute \src "ls180.v:1865.12-1865.87"
- process $proc$ls180.v:1865$3582
+ attribute \src "ls180.v:1861.12-1861.87"
+ process $proc$ls180.v:1861$3582
assign { } { }
assign $1\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] 0
sync always
sync init
update \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value $1\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0]
end
- attribute \src "ls180.v:1866.5-1866.82"
- process $proc$ls180.v:1866$3583
+ attribute \src "ls180.v:1862.5-1862.82"
+ process $proc$ls180.v:1862$3583
assign { } { }
assign $1\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] 1'0
sync always
sync init
update \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce $1\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0]
end
- attribute \src "ls180.v:1867.12-1867.43"
- process $proc$ls180.v:1867$3584
+ attribute \src "ls180.v:1863.12-1863.43"
+ process $proc$ls180.v:1863$3584
assign { } { }
assign $1\builder_libresocsim_adr[13:0] 14'00000000000000
sync always
sync init
update \builder_libresocsim_adr $1\builder_libresocsim_adr[13:0]
end
- attribute \src "ls180.v:1868.5-1868.34"
- process $proc$ls180.v:1868$3585
+ attribute \src "ls180.v:1864.5-1864.34"
+ process $proc$ls180.v:1864$3585
assign { } { }
assign $1\builder_libresocsim_we[0:0] 1'0
sync always
sync init
update \builder_libresocsim_we $1\builder_libresocsim_we[0:0]
end
- attribute \src "ls180.v:1869.11-1869.43"
- process $proc$ls180.v:1869$3586
+ attribute \src "ls180.v:1865.11-1865.43"
+ process $proc$ls180.v:1865$3586
assign { } { }
assign $1\builder_libresocsim_dat_w[7:0] 8'00000000
sync always
sync init
update \builder_libresocsim_dat_w $1\builder_libresocsim_dat_w[7:0]
end
- attribute \src "ls180.v:1873.12-1873.54"
- process $proc$ls180.v:1873$3587
+ attribute \src "ls180.v:1869.12-1869.54"
+ process $proc$ls180.v:1869$3587
assign { } { }
assign $1\builder_libresocsim_wishbone_dat_r[31:0] 0
sync always
sync init
update \builder_libresocsim_wishbone_dat_r $1\builder_libresocsim_wishbone_dat_r[31:0]
end
- attribute \src "ls180.v:1877.5-1877.44"
- process $proc$ls180.v:1877$3588
+ attribute \src "ls180.v:187.12-187.53"
+ process $proc$ls180.v:187$2796
assign { } { }
- assign $1\builder_libresocsim_wishbone_ack[0:0] 1'0
+ assign $1\main_libresocsim_converter1_dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
- update \builder_libresocsim_wishbone_ack $1\builder_libresocsim_wishbone_ack[0:0]
+ update \main_libresocsim_converter1_dat_r $1\main_libresocsim_converter1_dat_r[63:0]
end
- attribute \src "ls180.v:188.5-188.44"
- process $proc$ls180.v:188$2794
+ attribute \src "ls180.v:1873.5-1873.44"
+ process $proc$ls180.v:1873$3588
assign { } { }
- assign $1\main_libresocsim_converter1_skip[0:0] 1'0
+ assign $1\builder_libresocsim_wishbone_ack[0:0] 1'0
sync always
sync init
- update \main_libresocsim_converter1_skip $1\main_libresocsim_converter1_skip[0:0]
+ update \builder_libresocsim_wishbone_ack $1\builder_libresocsim_wishbone_ack[0:0]
end
- attribute \src "ls180.v:1881.5-1881.44"
- process $proc$ls180.v:1881$3589
+ attribute \src "ls180.v:1877.5-1877.44"
+ process $proc$ls180.v:1877$3589
assign { } { }
assign $0\builder_libresocsim_wishbone_err[0:0] 1'0
sync always
update \builder_libresocsim_wishbone_err $0\builder_libresocsim_wishbone_err[0:0]
sync init
end
- attribute \src "ls180.v:1884.12-1884.40"
- process $proc$ls180.v:1884$3590
+ attribute \src "ls180.v:188.12-188.71"
+ process $proc$ls180.v:188$2797
+ assign { } { }
+ assign $1\main_libresocsim_interface2_converted_interface_adr[29:0] 30'000000000000000000000000000000
+ sync always
+ sync init
+ update \main_libresocsim_interface2_converted_interface_adr $1\main_libresocsim_interface2_converted_interface_adr[29:0]
+ end
+ attribute \src "ls180.v:1880.12-1880.40"
+ process $proc$ls180.v:1880$3590
assign { } { }
assign $1\builder_shared_dat_r[31:0] 0
sync always
sync init
update \builder_shared_dat_r $1\builder_shared_dat_r[31:0]
end
- attribute \src "ls180.v:1888.5-1888.30"
- process $proc$ls180.v:1888$3591
+ attribute \src "ls180.v:1884.5-1884.30"
+ process $proc$ls180.v:1884$3591
assign { } { }
assign $1\builder_shared_ack[0:0] 1'0
sync always
sync init
update \builder_shared_ack $1\builder_shared_ack[0:0]
end
- attribute \src "ls180.v:189.5-189.47"
- process $proc$ls180.v:189$2795
+ attribute \src "ls180.v:189.12-189.73"
+ process $proc$ls180.v:189$2798
assign { } { }
- assign $1\main_libresocsim_converter1_counter[0:0] 1'0
+ assign $1\main_libresocsim_interface2_converted_interface_dat_w[31:0] 0
sync always
sync init
- update \main_libresocsim_converter1_counter $1\main_libresocsim_converter1_counter[0:0]
+ update \main_libresocsim_interface2_converted_interface_dat_w $1\main_libresocsim_interface2_converted_interface_dat_w[31:0]
end
- attribute \src "ls180.v:1894.11-1894.31"
- process $proc$ls180.v:1894$3592
+ attribute \src "ls180.v:1890.11-1890.31"
+ process $proc$ls180.v:1890$3592
assign { } { }
assign $1\builder_grant[2:0] 3'000
sync always
sync init
update \builder_grant $1\builder_grant[2:0]
end
- attribute \src "ls180.v:1895.11-1895.35"
- process $proc$ls180.v:1895$3593
+ attribute \src "ls180.v:1891.11-1891.35"
+ process $proc$ls180.v:1891$3593
assign { } { }
assign $1\builder_slave_sel[4:0] 5'00000
sync always
sync init
update \builder_slave_sel $1\builder_slave_sel[4:0]
end
- attribute \src "ls180.v:1896.11-1896.37"
- process $proc$ls180.v:1896$3594
+ attribute \src "ls180.v:1892.11-1892.37"
+ process $proc$ls180.v:1892$3594
assign { } { }
assign $1\builder_slave_sel_r[4:0] 5'00000
sync always
sync init
update \builder_slave_sel_r $1\builder_slave_sel_r[4:0]
end
- attribute \src "ls180.v:1897.5-1897.25"
- process $proc$ls180.v:1897$3595
+ attribute \src "ls180.v:1893.5-1893.25"
+ process $proc$ls180.v:1893$3595
assign { } { }
assign $1\builder_error[0:0] 1'0
sync always
sync init
update \builder_error $1\builder_error[0:0]
end
- attribute \src "ls180.v:1900.12-1900.39"
- process $proc$ls180.v:1900$3596
+ attribute \src "ls180.v:1896.12-1896.39"
+ process $proc$ls180.v:1896$3596
assign { } { }
assign $1\builder_count[19:0] 20'11110100001001000000
sync always
sync init
update \builder_count $1\builder_count[19:0]
end
- attribute \src "ls180.v:1904.11-1904.51"
- process $proc$ls180.v:1904$3597
+ attribute \src "ls180.v:1900.11-1900.51"
+ process $proc$ls180.v:1900$3597
assign { } { }
assign $1\builder_interface0_bank_bus_dat_r[7:0] 8'00000000
sync always
sync init
update \builder_interface0_bank_bus_dat_r $1\builder_interface0_bank_bus_dat_r[7:0]
end
- attribute \src "ls180.v:191.12-191.53"
- process $proc$ls180.v:191$2796
- assign { } { }
- assign $1\main_libresocsim_converter1_dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
- sync always
- sync init
- update \main_libresocsim_converter1_dat_r $1\main_libresocsim_converter1_dat_r[63:0]
- end
- attribute \src "ls180.v:192.12-192.71"
- process $proc$ls180.v:192$2797
- assign { } { }
- assign $1\main_libresocsim_interface2_converted_interface_adr[29:0] 30'000000000000000000000000000000
- sync always
- sync init
- update \main_libresocsim_interface2_converted_interface_adr $1\main_libresocsim_interface2_converted_interface_adr[29:0]
- end
- attribute \src "ls180.v:193.12-193.73"
- process $proc$ls180.v:193$2798
- assign { } { }
- assign $1\main_libresocsim_interface2_converted_interface_dat_w[31:0] 0
- sync always
- sync init
- update \main_libresocsim_interface2_converted_interface_dat_w $1\main_libresocsim_interface2_converted_interface_dat_w[31:0]
- end
- attribute \src "ls180.v:1945.11-1945.51"
- process $proc$ls180.v:1945$3598
- assign { } { }
- assign $1\builder_interface1_bank_bus_dat_r[7:0] 8'00000000
- sync always
- sync init
- update \builder_interface1_bank_bus_dat_r $1\builder_interface1_bank_bus_dat_r[7:0]
- end
- attribute \src "ls180.v:195.11-195.69"
- process $proc$ls180.v:195$2799
+ attribute \src "ls180.v:191.11-191.69"
+ process $proc$ls180.v:191$2799
assign { } { }
assign $1\main_libresocsim_interface2_converted_interface_sel[3:0] 4'0000
sync always
sync init
update \main_libresocsim_interface2_converted_interface_sel $1\main_libresocsim_interface2_converted_interface_sel[3:0]
end
- attribute \src "ls180.v:196.5-196.63"
- process $proc$ls180.v:196$2800
+ attribute \src "ls180.v:192.5-192.63"
+ process $proc$ls180.v:192$2800
assign { } { }
assign $1\main_libresocsim_interface2_converted_interface_cyc[0:0] 1'0
sync always
sync init
update \main_libresocsim_interface2_converted_interface_cyc $1\main_libresocsim_interface2_converted_interface_cyc[0:0]
end
- attribute \src "ls180.v:197.5-197.63"
- process $proc$ls180.v:197$2801
+ attribute \src "ls180.v:193.5-193.63"
+ process $proc$ls180.v:193$2801
assign { } { }
assign $1\main_libresocsim_interface2_converted_interface_stb[0:0] 1'0
sync always
sync init
update \main_libresocsim_interface2_converted_interface_stb $1\main_libresocsim_interface2_converted_interface_stb[0:0]
end
- attribute \src "ls180.v:1974.11-1974.51"
- process $proc$ls180.v:1974$3599
+ attribute \src "ls180.v:1941.11-1941.51"
+ process $proc$ls180.v:1941$3598
assign { } { }
- assign $1\builder_interface2_bank_bus_dat_r[7:0] 8'00000000
- sync always
- sync init
- update \builder_interface2_bank_bus_dat_r $1\builder_interface2_bank_bus_dat_r[7:0]
- end
- attribute \src "ls180.v:1987.11-1987.51"
- process $proc$ls180.v:1987$3600
- assign { } { }
- assign $1\builder_interface3_bank_bus_dat_r[7:0] 8'00000000
+ assign $1\builder_interface1_bank_bus_dat_r[7:0] 8'00000000
sync always
sync init
- update \builder_interface3_bank_bus_dat_r $1\builder_interface3_bank_bus_dat_r[7:0]
+ update \builder_interface1_bank_bus_dat_r $1\builder_interface1_bank_bus_dat_r[7:0]
end
- attribute \src "ls180.v:199.5-199.62"
- process $proc$ls180.v:199$2802
+ attribute \src "ls180.v:195.5-195.62"
+ process $proc$ls180.v:195$2802
assign { } { }
assign $1\main_libresocsim_interface2_converted_interface_we[0:0] 1'0
sync always
sync init
update \main_libresocsim_interface2_converted_interface_we $1\main_libresocsim_interface2_converted_interface_we[0:0]
end
- attribute \src "ls180.v:200.11-200.69"
- process $proc$ls180.v:200$2803
+ attribute \src "ls180.v:196.11-196.69"
+ process $proc$ls180.v:196$2803
assign { } { }
assign $0\main_libresocsim_interface2_converted_interface_cti[2:0] 3'000
sync always
update \main_libresocsim_interface2_converted_interface_cti $0\main_libresocsim_interface2_converted_interface_cti[2:0]
sync init
end
- attribute \src "ls180.v:201.11-201.69"
- process $proc$ls180.v:201$2804
+ attribute \src "ls180.v:197.11-197.69"
+ process $proc$ls180.v:197$2804
assign { } { }
assign $0\main_libresocsim_interface2_converted_interface_bte[1:0] 2'00
sync always
update \main_libresocsim_interface2_converted_interface_bte $0\main_libresocsim_interface2_converted_interface_bte[1:0]
sync init
end
- attribute \src "ls180.v:2028.11-2028.51"
- process $proc$ls180.v:2028$3601
+ attribute \src "ls180.v:1970.11-1970.51"
+ process $proc$ls180.v:1970$3599
assign { } { }
- assign $1\builder_interface4_bank_bus_dat_r[7:0] 8'00000000
+ assign $1\builder_interface2_bank_bus_dat_r[7:0] 8'00000000
sync always
sync init
- update \builder_interface4_bank_bus_dat_r $1\builder_interface4_bank_bus_dat_r[7:0]
+ update \builder_interface2_bank_bus_dat_r $1\builder_interface2_bank_bus_dat_r[7:0]
end
- attribute \src "ls180.v:203.5-203.44"
- process $proc$ls180.v:203$2805
+ attribute \src "ls180.v:1983.11-1983.51"
+ process $proc$ls180.v:1983$3600
+ assign { } { }
+ assign $1\builder_interface3_bank_bus_dat_r[7:0] 8'00000000
+ sync always
+ sync init
+ update \builder_interface3_bank_bus_dat_r $1\builder_interface3_bank_bus_dat_r[7:0]
+ end
+ attribute \src "ls180.v:199.5-199.44"
+ process $proc$ls180.v:199$2805
assign { } { }
assign $1\main_libresocsim_converter2_skip[0:0] 1'0
sync always
sync init
update \main_libresocsim_converter2_skip $1\main_libresocsim_converter2_skip[0:0]
end
- attribute \src "ls180.v:204.5-204.47"
- process $proc$ls180.v:204$2806
+ attribute \src "ls180.v:200.5-200.47"
+ process $proc$ls180.v:200$2806
assign { } { }
assign $1\main_libresocsim_converter2_counter[0:0] 1'0
sync always
sync init
update \main_libresocsim_converter2_counter $1\main_libresocsim_converter2_counter[0:0]
end
- attribute \src "ls180.v:206.12-206.53"
- process $proc$ls180.v:206$2807
+ attribute \src "ls180.v:202.12-202.53"
+ process $proc$ls180.v:202$2807
assign { } { }
assign $1\main_libresocsim_converter2_dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \main_libresocsim_converter2_dat_r $1\main_libresocsim_converter2_dat_r[63:0]
end
- attribute \src "ls180.v:2069.11-2069.51"
- process $proc$ls180.v:2069$3602
+ attribute \src "ls180.v:2024.11-2024.51"
+ process $proc$ls180.v:2024$3601
+ assign { } { }
+ assign $1\builder_interface4_bank_bus_dat_r[7:0] 8'00000000
+ sync always
+ sync init
+ update \builder_interface4_bank_bus_dat_r $1\builder_interface4_bank_bus_dat_r[7:0]
+ end
+ attribute \src "ls180.v:2065.11-2065.51"
+ process $proc$ls180.v:2065$3602
assign { } { }
assign $1\builder_interface5_bank_bus_dat_r[7:0] 8'00000000
sync always
sync init
update \builder_interface5_bank_bus_dat_r $1\builder_interface5_bank_bus_dat_r[7:0]
end
- attribute \src "ls180.v:213.5-213.40"
- process $proc$ls180.v:213$2808
+ attribute \src "ls180.v:209.5-209.40"
+ process $proc$ls180.v:209$2808
assign { } { }
assign $1\main_libresocsim_ram_bus_ack[0:0] 1'0
sync always
sync init
update \main_libresocsim_ram_bus_ack $1\main_libresocsim_ram_bus_ack[0:0]
end
- attribute \src "ls180.v:2134.11-2134.51"
- process $proc$ls180.v:2134$3603
+ attribute \src "ls180.v:213.5-213.40"
+ process $proc$ls180.v:213$2809
assign { } { }
- assign $1\builder_interface6_bank_bus_dat_r[7:0] 8'00000000
+ assign $0\main_libresocsim_ram_bus_err[0:0] 1'0
sync always
+ update \main_libresocsim_ram_bus_err $0\main_libresocsim_ram_bus_err[0:0]
sync init
- update \builder_interface6_bank_bus_dat_r $1\builder_interface6_bank_bus_dat_r[7:0]
end
- attribute \src "ls180.v:217.5-217.40"
- process $proc$ls180.v:217$2809
+ attribute \src "ls180.v:2130.11-2130.51"
+ process $proc$ls180.v:2130$3603
assign { } { }
- assign $0\main_libresocsim_ram_bus_err[0:0] 1'0
+ assign $1\builder_interface6_bank_bus_dat_r[7:0] 8'00000000
sync always
- update \main_libresocsim_ram_bus_err $0\main_libresocsim_ram_bus_err[0:0]
sync init
+ update \builder_interface6_bank_bus_dat_r $1\builder_interface6_bank_bus_dat_r[7:0]
end
- attribute \src "ls180.v:220.11-220.37"
- process $proc$ls180.v:220$2810
+ attribute \src "ls180.v:216.11-216.37"
+ process $proc$ls180.v:216$2810
assign { } { }
assign $1\main_libresocsim_we[3:0] 4'0000
sync always
sync init
update \main_libresocsim_we $1\main_libresocsim_we[3:0]
end
- attribute \src "ls180.v:222.12-222.49"
- process $proc$ls180.v:222$2811
+ attribute \src "ls180.v:218.12-218.49"
+ process $proc$ls180.v:218$2811
assign { } { }
assign $1\main_libresocsim_load_storage[31:0] 0
sync always
sync init
update \main_libresocsim_load_storage $1\main_libresocsim_load_storage[31:0]
end
- attribute \src "ls180.v:223.5-223.36"
- process $proc$ls180.v:223$2812
+ attribute \src "ls180.v:219.5-219.36"
+ process $proc$ls180.v:219$2812
assign { } { }
assign $1\main_libresocsim_load_re[0:0] 1'0
sync always
sync init
update \main_libresocsim_load_re $1\main_libresocsim_load_re[0:0]
end
- attribute \src "ls180.v:224.12-224.51"
- process $proc$ls180.v:224$2813
+ attribute \src "ls180.v:220.12-220.51"
+ process $proc$ls180.v:220$2813
assign { } { }
assign $1\main_libresocsim_reload_storage[31:0] 0
sync always
sync init
update \main_libresocsim_reload_storage $1\main_libresocsim_reload_storage[31:0]
end
- attribute \src "ls180.v:225.5-225.38"
- process $proc$ls180.v:225$2814
+ attribute \src "ls180.v:221.5-221.38"
+ process $proc$ls180.v:221$2814
assign { } { }
assign $1\main_libresocsim_reload_re[0:0] 1'0
sync always
sync init
update \main_libresocsim_reload_re $1\main_libresocsim_reload_re[0:0]
end
- attribute \src "ls180.v:226.5-226.39"
- process $proc$ls180.v:226$2815
+ attribute \src "ls180.v:222.5-222.39"
+ process $proc$ls180.v:222$2815
assign { } { }
assign $1\main_libresocsim_en_storage[0:0] 1'0
sync always
sync init
update \main_libresocsim_en_storage $1\main_libresocsim_en_storage[0:0]
end
- attribute \src "ls180.v:2267.11-2267.51"
- process $proc$ls180.v:2267$3604
- assign { } { }
- assign $1\builder_interface7_bank_bus_dat_r[7:0] 8'00000000
- sync always
- sync init
- update \builder_interface7_bank_bus_dat_r $1\builder_interface7_bank_bus_dat_r[7:0]
- end
- attribute \src "ls180.v:227.5-227.34"
- process $proc$ls180.v:227$2816
+ attribute \src "ls180.v:223.5-223.34"
+ process $proc$ls180.v:223$2816
assign { } { }
assign $1\main_libresocsim_en_re[0:0] 1'0
sync always
sync init
update \main_libresocsim_en_re $1\main_libresocsim_en_re[0:0]
end
- attribute \src "ls180.v:228.5-228.49"
- process $proc$ls180.v:228$2817
+ attribute \src "ls180.v:224.5-224.49"
+ process $proc$ls180.v:224$2817
assign { } { }
assign $1\main_libresocsim_update_value_storage[0:0] 1'0
sync always
sync init
update \main_libresocsim_update_value_storage $1\main_libresocsim_update_value_storage[0:0]
end
- attribute \src "ls180.v:229.5-229.44"
- process $proc$ls180.v:229$2818
+ attribute \src "ls180.v:225.5-225.44"
+ process $proc$ls180.v:225$2818
assign { } { }
assign $1\main_libresocsim_update_value_re[0:0] 1'0
sync always
sync init
update \main_libresocsim_update_value_re $1\main_libresocsim_update_value_re[0:0]
end
- attribute \src "ls180.v:230.12-230.49"
- process $proc$ls180.v:230$2819
+ attribute \src "ls180.v:226.12-226.49"
+ process $proc$ls180.v:226$2819
assign { } { }
assign $1\main_libresocsim_value_status[31:0] 0
sync always
sync init
update \main_libresocsim_value_status $1\main_libresocsim_value_status[31:0]
end
- attribute \src "ls180.v:234.5-234.41"
- process $proc$ls180.v:234$2820
+ attribute \src "ls180.v:2263.11-2263.51"
+ process $proc$ls180.v:2263$3604
assign { } { }
- assign $1\main_libresocsim_zero_pending[0:0] 1'0
+ assign $1\builder_interface7_bank_bus_dat_r[7:0] 8'00000000
sync always
sync init
- update \main_libresocsim_zero_pending $1\main_libresocsim_zero_pending[0:0]
+ update \builder_interface7_bank_bus_dat_r $1\builder_interface7_bank_bus_dat_r[7:0]
end
- attribute \src "ls180.v:2348.11-2348.51"
- process $proc$ls180.v:2348$3605
+ attribute \src "ls180.v:230.5-230.41"
+ process $proc$ls180.v:230$2820
assign { } { }
- assign $1\builder_interface8_bank_bus_dat_r[7:0] 8'00000000
+ assign $1\main_libresocsim_zero_pending[0:0] 1'0
sync always
sync init
- update \builder_interface8_bank_bus_dat_r $1\builder_interface8_bank_bus_dat_r[7:0]
+ update \main_libresocsim_zero_pending $1\main_libresocsim_zero_pending[0:0]
end
- attribute \src "ls180.v:236.5-236.39"
- process $proc$ls180.v:236$2821
+ attribute \src "ls180.v:232.5-232.39"
+ process $proc$ls180.v:232$2821
assign { } { }
assign $1\main_libresocsim_zero_clear[0:0] 1'0
sync always
sync init
update \main_libresocsim_zero_clear $1\main_libresocsim_zero_clear[0:0]
end
- attribute \src "ls180.v:2365.11-2365.51"
- process $proc$ls180.v:2365$3606
+ attribute \src "ls180.v:233.5-233.45"
+ process $proc$ls180.v:233$2822
assign { } { }
- assign $1\builder_interface9_bank_bus_dat_r[7:0] 8'00000000
+ assign $1\main_libresocsim_zero_old_trigger[0:0] 1'0
sync always
sync init
- update \builder_interface9_bank_bus_dat_r $1\builder_interface9_bank_bus_dat_r[7:0]
+ update \main_libresocsim_zero_old_trigger $1\main_libresocsim_zero_old_trigger[0:0]
end
- attribute \src "ls180.v:237.5-237.45"
- process $proc$ls180.v:237$2822
+ attribute \src "ls180.v:2344.11-2344.51"
+ process $proc$ls180.v:2344$3605
assign { } { }
- assign $1\main_libresocsim_zero_old_trigger[0:0] 1'0
+ assign $1\builder_interface8_bank_bus_dat_r[7:0] 8'00000000
sync always
sync init
- update \main_libresocsim_zero_old_trigger $1\main_libresocsim_zero_old_trigger[0:0]
+ update \builder_interface8_bank_bus_dat_r $1\builder_interface8_bank_bus_dat_r[7:0]
end
- attribute \src "ls180.v:2406.11-2406.52"
- process $proc$ls180.v:2406$3607
+ attribute \src "ls180.v:2361.11-2361.51"
+ process $proc$ls180.v:2361$3606
assign { } { }
- assign $1\builder_interface10_bank_bus_dat_r[7:0] 8'00000000
+ assign $1\builder_interface9_bank_bus_dat_r[7:0] 8'00000000
sync always
sync init
- update \builder_interface10_bank_bus_dat_r $1\builder_interface10_bank_bus_dat_r[7:0]
+ update \builder_interface9_bank_bus_dat_r $1\builder_interface9_bank_bus_dat_r[7:0]
end
- attribute \src "ls180.v:2439.11-2439.52"
- process $proc$ls180.v:2439$3608
+ attribute \src "ls180.v:2402.11-2402.52"
+ process $proc$ls180.v:2402$3607
assign { } { }
- assign $1\builder_interface11_bank_bus_dat_r[7:0] 8'00000000
+ assign $1\builder_interface10_bank_bus_dat_r[7:0] 8'00000000
sync always
sync init
- update \builder_interface11_bank_bus_dat_r $1\builder_interface11_bank_bus_dat_r[7:0]
+ update \builder_interface10_bank_bus_dat_r $1\builder_interface10_bank_bus_dat_r[7:0]
end
- attribute \src "ls180.v:246.5-246.49"
- process $proc$ls180.v:246$2823
+ attribute \src "ls180.v:242.5-242.49"
+ process $proc$ls180.v:242$2823
assign { } { }
assign $1\main_libresocsim_eventmanager_storage[0:0] 1'0
sync always
sync init
update \main_libresocsim_eventmanager_storage $1\main_libresocsim_eventmanager_storage[0:0]
end
- attribute \src "ls180.v:247.5-247.44"
- process $proc$ls180.v:247$2824
+ attribute \src "ls180.v:243.5-243.44"
+ process $proc$ls180.v:243$2824
assign { } { }
assign $1\main_libresocsim_eventmanager_re[0:0] 1'0
sync always
sync init
update \main_libresocsim_eventmanager_re $1\main_libresocsim_eventmanager_re[0:0]
end
- attribute \src "ls180.v:248.12-248.42"
- process $proc$ls180.v:248$2825
+ attribute \src "ls180.v:2435.11-2435.52"
+ process $proc$ls180.v:2435$3608
+ assign { } { }
+ assign $1\builder_interface11_bank_bus_dat_r[7:0] 8'00000000
+ sync always
+ sync init
+ update \builder_interface11_bank_bus_dat_r $1\builder_interface11_bank_bus_dat_r[7:0]
+ end
+ attribute \src "ls180.v:244.12-244.42"
+ process $proc$ls180.v:244$2825
assign { } { }
assign $1\main_libresocsim_value[31:0] 0
sync always
sync init
update \main_libresocsim_value $1\main_libresocsim_value[31:0]
end
- attribute \src "ls180.v:2480.11-2480.52"
- process $proc$ls180.v:2480$3609
+ attribute \src "ls180.v:2476.11-2476.52"
+ process $proc$ls180.v:2476$3609
assign { } { }
assign $1\builder_interface12_bank_bus_dat_r[7:0] 8'00000000
sync always
sync init
update \builder_interface12_bank_bus_dat_r $1\builder_interface12_bank_bus_dat_r[7:0]
end
- attribute \src "ls180.v:252.5-252.24"
- process $proc$ls180.v:252$2826
+ attribute \src "ls180.v:248.5-248.24"
+ process $proc$ls180.v:248$2826
assign { } { }
assign $1\main_int_rst[0:0] 1'1
sync always
sync init
update \main_int_rst $1\main_int_rst[0:0]
end
- attribute \src "ls180.v:2545.11-2545.52"
- process $proc$ls180.v:2545$3610
+ attribute \src "ls180.v:2541.11-2541.52"
+ process $proc$ls180.v:2541$3610
assign { } { }
assign $1\builder_interface13_bank_bus_dat_r[7:0] 8'00000000
sync always
sync init
update \builder_interface13_bank_bus_dat_r $1\builder_interface13_bank_bus_dat_r[7:0]
end
- attribute \src "ls180.v:2570.11-2570.52"
- process $proc$ls180.v:2570$3611
+ attribute \src "ls180.v:2566.11-2566.52"
+ process $proc$ls180.v:2566$3611
assign { } { }
assign $1\builder_interface14_bank_bus_dat_r[7:0] 8'00000000
sync always
sync init
update \builder_interface14_bank_bus_dat_r $1\builder_interface14_bank_bus_dat_r[7:0]
end
- attribute \src "ls180.v:2592.11-2592.31"
- process $proc$ls180.v:2592$3612
+ attribute \src "ls180.v:2588.11-2588.31"
+ process $proc$ls180.v:2588$3612
assign { } { }
assign $1\builder_state[1:0] 2'00
sync always
sync init
update \builder_state $1\builder_state[1:0]
end
- attribute \src "ls180.v:2593.11-2593.36"
- process $proc$ls180.v:2593$3613
+ attribute \src "ls180.v:2589.11-2589.36"
+ process $proc$ls180.v:2589$3613
assign { } { }
assign $1\builder_next_state[1:0] 2'00
sync always
sync init
update \builder_next_state $1\builder_next_state[1:0]
end
- attribute \src "ls180.v:2594.11-2594.55"
- process $proc$ls180.v:2594$3614
+ attribute \src "ls180.v:2590.11-2590.55"
+ process $proc$ls180.v:2590$3614
assign { } { }
assign $1\builder_libresocsim_dat_w_next_value0[7:0] 8'00000000
sync always
sync init
update \builder_libresocsim_dat_w_next_value0 $1\builder_libresocsim_dat_w_next_value0[7:0]
end
- attribute \src "ls180.v:2595.5-2595.52"
- process $proc$ls180.v:2595$3615
+ attribute \src "ls180.v:2591.5-2591.52"
+ process $proc$ls180.v:2591$3615
assign { } { }
assign $1\builder_libresocsim_dat_w_next_value_ce0[0:0] 1'0
sync always
sync init
update \builder_libresocsim_dat_w_next_value_ce0 $1\builder_libresocsim_dat_w_next_value_ce0[0:0]
end
- attribute \src "ls180.v:2596.12-2596.55"
- process $proc$ls180.v:2596$3616
+ attribute \src "ls180.v:2592.12-2592.55"
+ process $proc$ls180.v:2592$3616
assign { } { }
assign $1\builder_libresocsim_adr_next_value1[13:0] 14'00000000000000
sync always
sync init
update \builder_libresocsim_adr_next_value1 $1\builder_libresocsim_adr_next_value1[13:0]
end
- attribute \src "ls180.v:2597.5-2597.50"
- process $proc$ls180.v:2597$3617
+ attribute \src "ls180.v:2593.5-2593.50"
+ process $proc$ls180.v:2593$3617
assign { } { }
assign $1\builder_libresocsim_adr_next_value_ce1[0:0] 1'0
sync always
sync init
update \builder_libresocsim_adr_next_value_ce1 $1\builder_libresocsim_adr_next_value_ce1[0:0]
end
- attribute \src "ls180.v:2598.5-2598.46"
- process $proc$ls180.v:2598$3618
+ attribute \src "ls180.v:2594.5-2594.46"
+ process $proc$ls180.v:2594$3618
assign { } { }
assign $1\builder_libresocsim_we_next_value2[0:0] 1'0
sync always
sync init
update \builder_libresocsim_we_next_value2 $1\builder_libresocsim_we_next_value2[0:0]
end
- attribute \src "ls180.v:2599.5-2599.49"
- process $proc$ls180.v:2599$3619
+ attribute \src "ls180.v:2595.5-2595.49"
+ process $proc$ls180.v:2595$3619
assign { } { }
assign $1\builder_libresocsim_we_next_value_ce2[0:0] 1'0
sync always
sync init
update \builder_libresocsim_we_next_value_ce2 $1\builder_libresocsim_we_next_value_ce2[0:0]
end
- attribute \src "ls180.v:2600.5-2600.41"
- process $proc$ls180.v:2600$3620
+ attribute \src "ls180.v:2596.5-2596.41"
+ process $proc$ls180.v:2596$3620
assign { } { }
assign $1\builder_comb_rhs_array_muxed0[0:0] 1'0
sync always
sync init
update \builder_comb_rhs_array_muxed0 $1\builder_comb_rhs_array_muxed0[0:0]
end
- attribute \src "ls180.v:2601.12-2601.49"
- process $proc$ls180.v:2601$3621
+ attribute \src "ls180.v:2597.12-2597.49"
+ process $proc$ls180.v:2597$3621
assign { } { }
assign $1\builder_comb_rhs_array_muxed1[12:0] 13'0000000000000
sync always
sync init
update \builder_comb_rhs_array_muxed1 $1\builder_comb_rhs_array_muxed1[12:0]
end
- attribute \src "ls180.v:2602.11-2602.47"
- process $proc$ls180.v:2602$3622
+ attribute \src "ls180.v:2598.11-2598.47"
+ process $proc$ls180.v:2598$3622
assign { } { }
assign $1\builder_comb_rhs_array_muxed2[1:0] 2'00
sync always
sync init
update \builder_comb_rhs_array_muxed2 $1\builder_comb_rhs_array_muxed2[1:0]
end
- attribute \src "ls180.v:2603.5-2603.41"
- process $proc$ls180.v:2603$3623
+ attribute \src "ls180.v:2599.5-2599.41"
+ process $proc$ls180.v:2599$3623
assign { } { }
assign $1\builder_comb_rhs_array_muxed3[0:0] 1'0
sync always
sync init
update \builder_comb_rhs_array_muxed3 $1\builder_comb_rhs_array_muxed3[0:0]
end
- attribute \src "ls180.v:2604.5-2604.41"
- process $proc$ls180.v:2604$3624
+ attribute \src "ls180.v:2600.5-2600.41"
+ process $proc$ls180.v:2600$3624
assign { } { }
assign $1\builder_comb_rhs_array_muxed4[0:0] 1'0
sync always
sync init
update \builder_comb_rhs_array_muxed4 $1\builder_comb_rhs_array_muxed4[0:0]
end
- attribute \src "ls180.v:2605.5-2605.41"
- process $proc$ls180.v:2605$3625
+ attribute \src "ls180.v:2601.5-2601.41"
+ process $proc$ls180.v:2601$3625
assign { } { }
assign $1\builder_comb_rhs_array_muxed5[0:0] 1'0
sync always
sync init
update \builder_comb_rhs_array_muxed5 $1\builder_comb_rhs_array_muxed5[0:0]
end
- attribute \src "ls180.v:2606.5-2606.39"
- process $proc$ls180.v:2606$3626
+ attribute \src "ls180.v:2602.5-2602.39"
+ process $proc$ls180.v:2602$3626
assign { } { }
assign $1\builder_comb_t_array_muxed0[0:0] 1'0
sync always
sync init
update \builder_comb_t_array_muxed0 $1\builder_comb_t_array_muxed0[0:0]
end
- attribute \src "ls180.v:2607.5-2607.39"
- process $proc$ls180.v:2607$3627
+ attribute \src "ls180.v:2603.5-2603.39"
+ process $proc$ls180.v:2603$3627
assign { } { }
assign $1\builder_comb_t_array_muxed1[0:0] 1'0
sync always
sync init
update \builder_comb_t_array_muxed1 $1\builder_comb_t_array_muxed1[0:0]
end
- attribute \src "ls180.v:2608.5-2608.39"
- process $proc$ls180.v:2608$3628
+ attribute \src "ls180.v:2604.5-2604.39"
+ process $proc$ls180.v:2604$3628
assign { } { }
assign $1\builder_comb_t_array_muxed2[0:0] 1'0
sync always
sync init
update \builder_comb_t_array_muxed2 $1\builder_comb_t_array_muxed2[0:0]
end
- attribute \src "ls180.v:2609.5-2609.41"
- process $proc$ls180.v:2609$3629
+ attribute \src "ls180.v:2605.5-2605.41"
+ process $proc$ls180.v:2605$3629
assign { } { }
assign $1\builder_comb_rhs_array_muxed6[0:0] 1'0
sync always
sync init
update \builder_comb_rhs_array_muxed6 $1\builder_comb_rhs_array_muxed6[0:0]
end
- attribute \src "ls180.v:2610.12-2610.49"
- process $proc$ls180.v:2610$3630
+ attribute \src "ls180.v:2606.12-2606.49"
+ process $proc$ls180.v:2606$3630
assign { } { }
assign $1\builder_comb_rhs_array_muxed7[12:0] 13'0000000000000
sync always
sync init
update \builder_comb_rhs_array_muxed7 $1\builder_comb_rhs_array_muxed7[12:0]
end
- attribute \src "ls180.v:2611.11-2611.47"
- process $proc$ls180.v:2611$3631
+ attribute \src "ls180.v:2607.11-2607.47"
+ process $proc$ls180.v:2607$3631
assign { } { }
assign $1\builder_comb_rhs_array_muxed8[1:0] 2'00
sync always
sync init
update \builder_comb_rhs_array_muxed8 $1\builder_comb_rhs_array_muxed8[1:0]
end
- attribute \src "ls180.v:2612.5-2612.41"
- process $proc$ls180.v:2612$3632
+ attribute \src "ls180.v:2608.5-2608.41"
+ process $proc$ls180.v:2608$3632
assign { } { }
assign $1\builder_comb_rhs_array_muxed9[0:0] 1'0
sync always
sync init
update \builder_comb_rhs_array_muxed9 $1\builder_comb_rhs_array_muxed9[0:0]
end
- attribute \src "ls180.v:2613.5-2613.42"
- process $proc$ls180.v:2613$3633
+ attribute \src "ls180.v:2609.5-2609.42"
+ process $proc$ls180.v:2609$3633
assign { } { }
assign $1\builder_comb_rhs_array_muxed10[0:0] 1'0
sync always
sync init
update \builder_comb_rhs_array_muxed10 $1\builder_comb_rhs_array_muxed10[0:0]
end
- attribute \src "ls180.v:2614.5-2614.42"
- process $proc$ls180.v:2614$3634
+ attribute \src "ls180.v:2610.5-2610.42"
+ process $proc$ls180.v:2610$3634
assign { } { }
assign $1\builder_comb_rhs_array_muxed11[0:0] 1'0
sync always
sync init
update \builder_comb_rhs_array_muxed11 $1\builder_comb_rhs_array_muxed11[0:0]
end
- attribute \src "ls180.v:2615.5-2615.39"
- process $proc$ls180.v:2615$3635
+ attribute \src "ls180.v:2611.5-2611.39"
+ process $proc$ls180.v:2611$3635
assign { } { }
assign $1\builder_comb_t_array_muxed3[0:0] 1'0
sync always
sync init
update \builder_comb_t_array_muxed3 $1\builder_comb_t_array_muxed3[0:0]
end
- attribute \src "ls180.v:2616.5-2616.39"
- process $proc$ls180.v:2616$3636
+ attribute \src "ls180.v:2612.5-2612.39"
+ process $proc$ls180.v:2612$3636
assign { } { }
assign $1\builder_comb_t_array_muxed4[0:0] 1'0
sync always
sync init
update \builder_comb_t_array_muxed4 $1\builder_comb_t_array_muxed4[0:0]
end
- attribute \src "ls180.v:2617.5-2617.39"
- process $proc$ls180.v:2617$3637
+ attribute \src "ls180.v:2613.5-2613.39"
+ process $proc$ls180.v:2613$3637
assign { } { }
assign $1\builder_comb_t_array_muxed5[0:0] 1'0
sync always
sync init
update \builder_comb_t_array_muxed5 $1\builder_comb_t_array_muxed5[0:0]
end
- attribute \src "ls180.v:2618.12-2618.50"
- process $proc$ls180.v:2618$3638
+ attribute \src "ls180.v:2614.12-2614.50"
+ process $proc$ls180.v:2614$3638
assign { } { }
assign $1\builder_comb_rhs_array_muxed12[21:0] 22'0000000000000000000000
sync always
sync init
update \builder_comb_rhs_array_muxed12 $1\builder_comb_rhs_array_muxed12[21:0]
end
- attribute \src "ls180.v:2619.5-2619.42"
- process $proc$ls180.v:2619$3639
+ attribute \src "ls180.v:2615.5-2615.42"
+ process $proc$ls180.v:2615$3639
assign { } { }
assign $1\builder_comb_rhs_array_muxed13[0:0] 1'0
sync always
sync init
update \builder_comb_rhs_array_muxed13 $1\builder_comb_rhs_array_muxed13[0:0]
end
- attribute \src "ls180.v:2620.5-2620.42"
- process $proc$ls180.v:2620$3640
+ attribute \src "ls180.v:2616.5-2616.42"
+ process $proc$ls180.v:2616$3640
assign { } { }
assign $1\builder_comb_rhs_array_muxed14[0:0] 1'0
sync always
sync init
update \builder_comb_rhs_array_muxed14 $1\builder_comb_rhs_array_muxed14[0:0]
end
- attribute \src "ls180.v:2621.12-2621.50"
- process $proc$ls180.v:2621$3641
+ attribute \src "ls180.v:2617.12-2617.50"
+ process $proc$ls180.v:2617$3641
assign { } { }
assign $1\builder_comb_rhs_array_muxed15[21:0] 22'0000000000000000000000
sync always
sync init
update \builder_comb_rhs_array_muxed15 $1\builder_comb_rhs_array_muxed15[21:0]
end
- attribute \src "ls180.v:2622.5-2622.42"
- process $proc$ls180.v:2622$3642
+ attribute \src "ls180.v:2618.5-2618.42"
+ process $proc$ls180.v:2618$3642
assign { } { }
assign $1\builder_comb_rhs_array_muxed16[0:0] 1'0
sync always
sync init
update \builder_comb_rhs_array_muxed16 $1\builder_comb_rhs_array_muxed16[0:0]
end
- attribute \src "ls180.v:2623.5-2623.42"
- process $proc$ls180.v:2623$3643
+ attribute \src "ls180.v:2619.5-2619.42"
+ process $proc$ls180.v:2619$3643
assign { } { }
assign $1\builder_comb_rhs_array_muxed17[0:0] 1'0
sync always
sync init
update \builder_comb_rhs_array_muxed17 $1\builder_comb_rhs_array_muxed17[0:0]
end
- attribute \src "ls180.v:2624.12-2624.50"
- process $proc$ls180.v:2624$3644
+ attribute \src "ls180.v:2620.12-2620.50"
+ process $proc$ls180.v:2620$3644
assign { } { }
assign $1\builder_comb_rhs_array_muxed18[21:0] 22'0000000000000000000000
sync always
sync init
update \builder_comb_rhs_array_muxed18 $1\builder_comb_rhs_array_muxed18[21:0]
end
- attribute \src "ls180.v:2625.5-2625.42"
- process $proc$ls180.v:2625$3645
+ attribute \src "ls180.v:2621.5-2621.42"
+ process $proc$ls180.v:2621$3645
assign { } { }
assign $1\builder_comb_rhs_array_muxed19[0:0] 1'0
sync always
sync init
update \builder_comb_rhs_array_muxed19 $1\builder_comb_rhs_array_muxed19[0:0]
end
- attribute \src "ls180.v:2626.5-2626.42"
- process $proc$ls180.v:2626$3646
+ attribute \src "ls180.v:2622.5-2622.42"
+ process $proc$ls180.v:2622$3646
assign { } { }
assign $1\builder_comb_rhs_array_muxed20[0:0] 1'0
sync always
sync init
update \builder_comb_rhs_array_muxed20 $1\builder_comb_rhs_array_muxed20[0:0]
end
- attribute \src "ls180.v:2627.12-2627.50"
- process $proc$ls180.v:2627$3647
+ attribute \src "ls180.v:2623.12-2623.50"
+ process $proc$ls180.v:2623$3647
assign { } { }
assign $1\builder_comb_rhs_array_muxed21[21:0] 22'0000000000000000000000
sync always
sync init
update \builder_comb_rhs_array_muxed21 $1\builder_comb_rhs_array_muxed21[21:0]
end
- attribute \src "ls180.v:2628.5-2628.42"
- process $proc$ls180.v:2628$3648
+ attribute \src "ls180.v:2624.5-2624.42"
+ process $proc$ls180.v:2624$3648
assign { } { }
assign $1\builder_comb_rhs_array_muxed22[0:0] 1'0
sync always
sync init
update \builder_comb_rhs_array_muxed22 $1\builder_comb_rhs_array_muxed22[0:0]
end
- attribute \src "ls180.v:2629.5-2629.42"
- process $proc$ls180.v:2629$3649
+ attribute \src "ls180.v:2625.5-2625.42"
+ process $proc$ls180.v:2625$3649
assign { } { }
assign $1\builder_comb_rhs_array_muxed23[0:0] 1'0
sync always
sync init
update \builder_comb_rhs_array_muxed23 $1\builder_comb_rhs_array_muxed23[0:0]
end
- attribute \src "ls180.v:2630.12-2630.50"
- process $proc$ls180.v:2630$3650
+ attribute \src "ls180.v:2626.12-2626.50"
+ process $proc$ls180.v:2626$3650
assign { } { }
assign $1\builder_comb_rhs_array_muxed24[31:0] 0
sync always
sync init
update \builder_comb_rhs_array_muxed24 $1\builder_comb_rhs_array_muxed24[31:0]
end
- attribute \src "ls180.v:2631.12-2631.50"
- process $proc$ls180.v:2631$3651
+ attribute \src "ls180.v:2627.12-2627.50"
+ process $proc$ls180.v:2627$3651
assign { } { }
assign $1\builder_comb_rhs_array_muxed25[31:0] 0
sync always
sync init
update \builder_comb_rhs_array_muxed25 $1\builder_comb_rhs_array_muxed25[31:0]
end
- attribute \src "ls180.v:2632.11-2632.48"
- process $proc$ls180.v:2632$3652
+ attribute \src "ls180.v:2628.11-2628.48"
+ process $proc$ls180.v:2628$3652
assign { } { }
assign $1\builder_comb_rhs_array_muxed26[3:0] 4'0000
sync always
sync init
update \builder_comb_rhs_array_muxed26 $1\builder_comb_rhs_array_muxed26[3:0]
end
- attribute \src "ls180.v:2633.5-2633.42"
- process $proc$ls180.v:2633$3653
+ attribute \src "ls180.v:2629.5-2629.42"
+ process $proc$ls180.v:2629$3653
assign { } { }
assign $1\builder_comb_rhs_array_muxed27[0:0] 1'0
sync always
sync init
update \builder_comb_rhs_array_muxed27 $1\builder_comb_rhs_array_muxed27[0:0]
end
- attribute \src "ls180.v:2634.5-2634.42"
- process $proc$ls180.v:2634$3654
+ attribute \src "ls180.v:263.12-263.38"
+ process $proc$ls180.v:263$2827
+ assign { } { }
+ assign $1\main_dfi_p0_rddata[15:0] 16'0000000000000000
+ sync always
+ sync init
+ update \main_dfi_p0_rddata $1\main_dfi_p0_rddata[15:0]
+ end
+ attribute \src "ls180.v:2630.5-2630.42"
+ process $proc$ls180.v:2630$3654
assign { } { }
assign $1\builder_comb_rhs_array_muxed28[0:0] 1'0
sync always
sync init
update \builder_comb_rhs_array_muxed28 $1\builder_comb_rhs_array_muxed28[0:0]
end
- attribute \src "ls180.v:2635.5-2635.42"
- process $proc$ls180.v:2635$3655
+ attribute \src "ls180.v:2631.5-2631.42"
+ process $proc$ls180.v:2631$3655
assign { } { }
assign $1\builder_comb_rhs_array_muxed29[0:0] 1'0
sync always
sync init
update \builder_comb_rhs_array_muxed29 $1\builder_comb_rhs_array_muxed29[0:0]
end
- attribute \src "ls180.v:2636.11-2636.48"
- process $proc$ls180.v:2636$3656
+ attribute \src "ls180.v:2632.11-2632.48"
+ process $proc$ls180.v:2632$3656
assign { } { }
assign $1\builder_comb_rhs_array_muxed30[2:0] 3'000
sync always
sync init
update \builder_comb_rhs_array_muxed30 $1\builder_comb_rhs_array_muxed30[2:0]
end
- attribute \src "ls180.v:2637.11-2637.48"
- process $proc$ls180.v:2637$3657
+ attribute \src "ls180.v:2633.11-2633.48"
+ process $proc$ls180.v:2633$3657
assign { } { }
assign $1\builder_comb_rhs_array_muxed31[1:0] 2'00
sync always
sync init
update \builder_comb_rhs_array_muxed31 $1\builder_comb_rhs_array_muxed31[1:0]
end
- attribute \src "ls180.v:2638.11-2638.47"
- process $proc$ls180.v:2638$3658
+ attribute \src "ls180.v:2634.11-2634.47"
+ process $proc$ls180.v:2634$3658
assign { } { }
assign $1\builder_sync_rhs_array_muxed0[1:0] 2'00
sync always
sync init
update \builder_sync_rhs_array_muxed0 $1\builder_sync_rhs_array_muxed0[1:0]
end
- attribute \src "ls180.v:2639.12-2639.49"
- process $proc$ls180.v:2639$3659
+ attribute \src "ls180.v:2635.12-2635.49"
+ process $proc$ls180.v:2635$3659
assign { } { }
assign $1\builder_sync_rhs_array_muxed1[12:0] 13'0000000000000
sync always
sync init
update \builder_sync_rhs_array_muxed1 $1\builder_sync_rhs_array_muxed1[12:0]
end
- attribute \src "ls180.v:2640.5-2640.41"
- process $proc$ls180.v:2640$3660
+ attribute \src "ls180.v:2636.5-2636.41"
+ process $proc$ls180.v:2636$3660
assign { } { }
assign $1\builder_sync_rhs_array_muxed2[0:0] 1'0
sync always
sync init
update \builder_sync_rhs_array_muxed2 $1\builder_sync_rhs_array_muxed2[0:0]
end
- attribute \src "ls180.v:2641.5-2641.41"
- process $proc$ls180.v:2641$3661
+ attribute \src "ls180.v:2637.5-2637.41"
+ process $proc$ls180.v:2637$3661
assign { } { }
assign $1\builder_sync_rhs_array_muxed3[0:0] 1'0
sync always
sync init
update \builder_sync_rhs_array_muxed3 $1\builder_sync_rhs_array_muxed3[0:0]
end
- attribute \src "ls180.v:2642.5-2642.41"
- process $proc$ls180.v:2642$3662
+ attribute \src "ls180.v:2638.5-2638.41"
+ process $proc$ls180.v:2638$3662
assign { } { }
assign $1\builder_sync_rhs_array_muxed4[0:0] 1'0
sync always
sync init
update \builder_sync_rhs_array_muxed4 $1\builder_sync_rhs_array_muxed4[0:0]
end
- attribute \src "ls180.v:2643.5-2643.41"
- process $proc$ls180.v:2643$3663
+ attribute \src "ls180.v:2639.5-2639.41"
+ process $proc$ls180.v:2639$3663
assign { } { }
assign $1\builder_sync_rhs_array_muxed5[0:0] 1'0
sync always
sync init
update \builder_sync_rhs_array_muxed5 $1\builder_sync_rhs_array_muxed5[0:0]
end
- attribute \src "ls180.v:2644.5-2644.41"
- process $proc$ls180.v:2644$3664
+ attribute \src "ls180.v:264.5-264.36"
+ process $proc$ls180.v:264$2828
+ assign { } { }
+ assign $1\main_dfi_p0_rddata_valid[0:0] 1'0
+ sync always
+ sync init
+ update \main_dfi_p0_rddata_valid $1\main_dfi_p0_rddata_valid[0:0]
+ end
+ attribute \src "ls180.v:2640.5-2640.41"
+ process $proc$ls180.v:2640$3664
assign { } { }
assign $1\builder_sync_rhs_array_muxed6[0:0] 1'0
sync always
sync init
update \builder_sync_rhs_array_muxed6 $1\builder_sync_rhs_array_muxed6[0:0]
end
- attribute \src "ls180.v:2645.5-2645.39"
- process $proc$ls180.v:2645$3665
+ attribute \src "ls180.v:2641.5-2641.39"
+ process $proc$ls180.v:2641$3665
assign { } { }
assign $1\builder_sync_f_array_muxed0[0:0] 1'0
sync always
sync init
update \builder_sync_f_array_muxed0 $1\builder_sync_f_array_muxed0[0:0]
end
- attribute \src "ls180.v:2646.5-2646.39"
- process $proc$ls180.v:2646$3666
+ attribute \src "ls180.v:2642.5-2642.39"
+ process $proc$ls180.v:2642$3666
assign { } { }
assign $1\builder_sync_f_array_muxed1[0:0] 1'0
sync always
sync init
update \builder_sync_f_array_muxed1 $1\builder_sync_f_array_muxed1[0:0]
end
- attribute \src "ls180.v:267.12-267.38"
- process $proc$ls180.v:267$2827
+ attribute \src "ls180.v:265.11-265.32"
+ process $proc$ls180.v:265$2829
assign { } { }
- assign $1\main_dfi_p0_rddata[15:0] 16'0000000000000000
+ assign $1\main_rddata_en[2:0] 3'000
sync always
sync init
- update \main_dfi_p0_rddata $1\main_dfi_p0_rddata[15:0]
+ update \main_rddata_en $1\main_rddata_en[2:0]
end
attribute \src "ls180.v:268.5-268.36"
- process $proc$ls180.v:268$2828
+ process $proc$ls180.v:268$2830
assign { } { }
- assign $1\main_dfi_p0_rddata_valid[0:0] 1'0
+ assign $1\main_sdram_inti_p0_cas_n[0:0] 1'1
sync always
sync init
- update \main_dfi_p0_rddata_valid $1\main_dfi_p0_rddata_valid[0:0]
+ update \main_sdram_inti_p0_cas_n $1\main_sdram_inti_p0_cas_n[0:0]
end
- attribute \src "ls180.v:269.11-269.32"
- process $proc$ls180.v:269$2829
+ attribute \src "ls180.v:269.5-269.35"
+ process $proc$ls180.v:269$2831
assign { } { }
- assign $1\main_rddata_en[2:0] 3'000
+ assign $1\main_sdram_inti_p0_cs_n[0:0] 1'1
sync always
sync init
- update \main_rddata_en $1\main_rddata_en[2:0]
+ update \main_sdram_inti_p0_cs_n $1\main_sdram_inti_p0_cs_n[0:0]
end
- attribute \src "ls180.v:2703.32-2703.66"
- process $proc$ls180.v:2703$3667
+ attribute \src "ls180.v:2699.32-2699.66"
+ process $proc$ls180.v:2699$3667
assign { } { }
assign $1\builder_multiregimpl0_regs0[0:0] 1'0
sync always
sync init
update \builder_multiregimpl0_regs0 $1\builder_multiregimpl0_regs0[0:0]
end
- attribute \src "ls180.v:2704.32-2704.66"
- process $proc$ls180.v:2704$3668
+ attribute \src "ls180.v:270.5-270.36"
+ process $proc$ls180.v:270$2832
+ assign { } { }
+ assign $1\main_sdram_inti_p0_ras_n[0:0] 1'1
+ sync always
+ sync init
+ update \main_sdram_inti_p0_ras_n $1\main_sdram_inti_p0_ras_n[0:0]
+ end
+ attribute \src "ls180.v:2700.32-2700.66"
+ process $proc$ls180.v:2700$3668
assign { } { }
assign $1\builder_multiregimpl0_regs1[0:0] 1'0
sync always
sync init
update \builder_multiregimpl0_regs1 $1\builder_multiregimpl0_regs1[0:0]
end
- attribute \src "ls180.v:2705.32-2705.66"
- process $proc$ls180.v:2705$3669
+ attribute \src "ls180.v:2701.32-2701.66"
+ process $proc$ls180.v:2701$3669
assign { } { }
assign $1\builder_multiregimpl1_regs0[0:0] 1'0
sync always
sync init
update \builder_multiregimpl1_regs0 $1\builder_multiregimpl1_regs0[0:0]
end
- attribute \src "ls180.v:2706.32-2706.66"
- process $proc$ls180.v:2706$3670
+ attribute \src "ls180.v:2702.32-2702.66"
+ process $proc$ls180.v:2702$3670
assign { } { }
assign $1\builder_multiregimpl1_regs1[0:0] 1'0
sync always
sync init
update \builder_multiregimpl1_regs1 $1\builder_multiregimpl1_regs1[0:0]
end
- attribute \src "ls180.v:2707.32-2707.66"
- process $proc$ls180.v:2707$3671
+ attribute \src "ls180.v:2703.32-2703.66"
+ process $proc$ls180.v:2703$3671
assign { } { }
assign $1\builder_multiregimpl2_regs0[0:0] 1'0
sync always
sync init
update \builder_multiregimpl2_regs0 $1\builder_multiregimpl2_regs0[0:0]
end
- attribute \src "ls180.v:2708.32-2708.66"
- process $proc$ls180.v:2708$3672
+ attribute \src "ls180.v:2704.32-2704.66"
+ process $proc$ls180.v:2704$3672
assign { } { }
assign $1\builder_multiregimpl2_regs1[0:0] 1'0
sync always
sync init
update \builder_multiregimpl2_regs1 $1\builder_multiregimpl2_regs1[0:0]
end
- attribute \src "ls180.v:2709.32-2709.66"
- process $proc$ls180.v:2709$3673
+ attribute \src "ls180.v:2705.32-2705.66"
+ process $proc$ls180.v:2705$3673
assign { } { }
assign $1\builder_multiregimpl3_regs0[0:0] 1'0
sync always
sync init
update \builder_multiregimpl3_regs0 $1\builder_multiregimpl3_regs0[0:0]
end
- attribute \src "ls180.v:2710.32-2710.66"
- process $proc$ls180.v:2710$3674
+ attribute \src "ls180.v:2706.32-2706.66"
+ process $proc$ls180.v:2706$3674
assign { } { }
assign $1\builder_multiregimpl3_regs1[0:0] 1'0
sync always
sync init
update \builder_multiregimpl3_regs1 $1\builder_multiregimpl3_regs1[0:0]
end
- attribute \src "ls180.v:2711.32-2711.66"
- process $proc$ls180.v:2711$3675
+ attribute \src "ls180.v:2707.32-2707.66"
+ process $proc$ls180.v:2707$3675
assign { } { }
assign $1\builder_multiregimpl4_regs0[0:0] 1'0
sync always
sync init
update \builder_multiregimpl4_regs0 $1\builder_multiregimpl4_regs0[0:0]
end
- attribute \src "ls180.v:2712.32-2712.66"
- process $proc$ls180.v:2712$3676
+ attribute \src "ls180.v:2708.32-2708.66"
+ process $proc$ls180.v:2708$3676
assign { } { }
assign $1\builder_multiregimpl4_regs1[0:0] 1'0
sync always
sync init
update \builder_multiregimpl4_regs1 $1\builder_multiregimpl4_regs1[0:0]
end
- attribute \src "ls180.v:2713.32-2713.66"
- process $proc$ls180.v:2713$3677
+ attribute \src "ls180.v:2709.32-2709.66"
+ process $proc$ls180.v:2709$3677
assign { } { }
assign $1\builder_multiregimpl5_regs0[0:0] 1'0
sync always
sync init
update \builder_multiregimpl5_regs0 $1\builder_multiregimpl5_regs0[0:0]
end
- attribute \src "ls180.v:2714.32-2714.66"
- process $proc$ls180.v:2714$3678
+ attribute \src "ls180.v:271.5-271.35"
+ process $proc$ls180.v:271$2833
+ assign { } { }
+ assign $1\main_sdram_inti_p0_we_n[0:0] 1'1
+ sync always
+ sync init
+ update \main_sdram_inti_p0_we_n $1\main_sdram_inti_p0_we_n[0:0]
+ end
+ attribute \src "ls180.v:2710.32-2710.66"
+ process $proc$ls180.v:2710$3678
assign { } { }
assign $1\builder_multiregimpl5_regs1[0:0] 1'0
sync always
sync init
update \builder_multiregimpl5_regs1 $1\builder_multiregimpl5_regs1[0:0]
end
- attribute \src "ls180.v:2715.32-2715.66"
- process $proc$ls180.v:2715$3679
+ attribute \src "ls180.v:2711.32-2711.66"
+ process $proc$ls180.v:2711$3679
assign { } { }
assign $1\builder_multiregimpl6_regs0[0:0] 1'0
sync always
sync init
update \builder_multiregimpl6_regs0 $1\builder_multiregimpl6_regs0[0:0]
end
- attribute \src "ls180.v:2716.32-2716.66"
- process $proc$ls180.v:2716$3680
+ attribute \src "ls180.v:2712.32-2712.66"
+ process $proc$ls180.v:2712$3680
assign { } { }
assign $1\builder_multiregimpl6_regs1[0:0] 1'0
sync always
sync init
update \builder_multiregimpl6_regs1 $1\builder_multiregimpl6_regs1[0:0]
end
- attribute \src "ls180.v:2717.32-2717.66"
- process $proc$ls180.v:2717$3681
+ attribute \src "ls180.v:2713.32-2713.66"
+ process $proc$ls180.v:2713$3681
assign { } { }
assign $1\builder_multiregimpl7_regs0[0:0] 1'0
sync always
sync init
update \builder_multiregimpl7_regs0 $1\builder_multiregimpl7_regs0[0:0]
end
- attribute \src "ls180.v:2718.32-2718.66"
- process $proc$ls180.v:2718$3682
+ attribute \src "ls180.v:2714.32-2714.66"
+ process $proc$ls180.v:2714$3682
assign { } { }
assign $1\builder_multiregimpl7_regs1[0:0] 1'0
sync always
sync init
update \builder_multiregimpl7_regs1 $1\builder_multiregimpl7_regs1[0:0]
end
- attribute \src "ls180.v:2719.32-2719.66"
- process $proc$ls180.v:2719$3683
+ attribute \src "ls180.v:2715.32-2715.66"
+ process $proc$ls180.v:2715$3683
assign { } { }
assign $1\builder_multiregimpl8_regs0[0:0] 1'0
sync always
sync init
update \builder_multiregimpl8_regs0 $1\builder_multiregimpl8_regs0[0:0]
end
- attribute \src "ls180.v:272.5-272.36"
- process $proc$ls180.v:272$2830
- assign { } { }
- assign $1\main_sdram_inti_p0_cas_n[0:0] 1'1
- sync always
- sync init
- update \main_sdram_inti_p0_cas_n $1\main_sdram_inti_p0_cas_n[0:0]
- end
- attribute \src "ls180.v:2720.32-2720.66"
- process $proc$ls180.v:2720$3684
+ attribute \src "ls180.v:2716.32-2716.66"
+ process $proc$ls180.v:2716$3684
assign { } { }
assign $1\builder_multiregimpl8_regs1[0:0] 1'0
sync always
sync init
update \builder_multiregimpl8_regs1 $1\builder_multiregimpl8_regs1[0:0]
end
- attribute \src "ls180.v:2721.32-2721.66"
- process $proc$ls180.v:2721$3685
+ attribute \src "ls180.v:2717.32-2717.66"
+ process $proc$ls180.v:2717$3685
assign { } { }
assign $1\builder_multiregimpl9_regs0[0:0] 1'0
sync always
sync init
update \builder_multiregimpl9_regs0 $1\builder_multiregimpl9_regs0[0:0]
end
- attribute \src "ls180.v:2722.32-2722.66"
- process $proc$ls180.v:2722$3686
+ attribute \src "ls180.v:2718.32-2718.66"
+ process $proc$ls180.v:2718$3686
assign { } { }
assign $1\builder_multiregimpl9_regs1[0:0] 1'0
sync always
sync init
update \builder_multiregimpl9_regs1 $1\builder_multiregimpl9_regs1[0:0]
end
- attribute \src "ls180.v:2723.32-2723.67"
- process $proc$ls180.v:2723$3687
+ attribute \src "ls180.v:2719.32-2719.67"
+ process $proc$ls180.v:2719$3687
assign { } { }
assign $1\builder_multiregimpl10_regs0[0:0] 1'0
sync always
sync init
update \builder_multiregimpl10_regs0 $1\builder_multiregimpl10_regs0[0:0]
end
- attribute \src "ls180.v:2724.32-2724.67"
- process $proc$ls180.v:2724$3688
+ attribute \src "ls180.v:2720.32-2720.67"
+ process $proc$ls180.v:2720$3688
assign { } { }
assign $1\builder_multiregimpl10_regs1[0:0] 1'0
sync always
sync init
update \builder_multiregimpl10_regs1 $1\builder_multiregimpl10_regs1[0:0]
end
- attribute \src "ls180.v:2725.32-2725.67"
- process $proc$ls180.v:2725$3689
+ attribute \src "ls180.v:2721.32-2721.67"
+ process $proc$ls180.v:2721$3689
assign { } { }
assign $1\builder_multiregimpl11_regs0[0:0] 1'0
sync always
sync init
update \builder_multiregimpl11_regs0 $1\builder_multiregimpl11_regs0[0:0]
end
- attribute \src "ls180.v:2726.32-2726.67"
- process $proc$ls180.v:2726$3690
+ attribute \src "ls180.v:2722.32-2722.67"
+ process $proc$ls180.v:2722$3690
assign { } { }
assign $1\builder_multiregimpl11_regs1[0:0] 1'0
sync always
sync init
update \builder_multiregimpl11_regs1 $1\builder_multiregimpl11_regs1[0:0]
end
- attribute \src "ls180.v:2727.32-2727.67"
- process $proc$ls180.v:2727$3691
+ attribute \src "ls180.v:2723.32-2723.67"
+ process $proc$ls180.v:2723$3691
assign { } { }
assign $1\builder_multiregimpl12_regs0[0:0] 1'0
sync always
sync init
update \builder_multiregimpl12_regs0 $1\builder_multiregimpl12_regs0[0:0]
end
- attribute \src "ls180.v:2728.32-2728.67"
- process $proc$ls180.v:2728$3692
+ attribute \src "ls180.v:2724.32-2724.67"
+ process $proc$ls180.v:2724$3692
assign { } { }
assign $1\builder_multiregimpl12_regs1[0:0] 1'0
sync always
sync init
update \builder_multiregimpl12_regs1 $1\builder_multiregimpl12_regs1[0:0]
end
- attribute \src "ls180.v:2729.32-2729.67"
- process $proc$ls180.v:2729$3693
+ attribute \src "ls180.v:2725.32-2725.67"
+ process $proc$ls180.v:2725$3693
assign { } { }
assign $1\builder_multiregimpl13_regs0[0:0] 1'0
sync always
sync init
update \builder_multiregimpl13_regs0 $1\builder_multiregimpl13_regs0[0:0]
end
- attribute \src "ls180.v:273.5-273.35"
- process $proc$ls180.v:273$2831
- assign { } { }
- assign $1\main_sdram_inti_p0_cs_n[0:0] 1'1
- sync always
- sync init
- update \main_sdram_inti_p0_cs_n $1\main_sdram_inti_p0_cs_n[0:0]
- end
- attribute \src "ls180.v:2730.32-2730.67"
- process $proc$ls180.v:2730$3694
+ attribute \src "ls180.v:2726.32-2726.67"
+ process $proc$ls180.v:2726$3694
assign { } { }
assign $1\builder_multiregimpl13_regs1[0:0] 1'0
sync always
sync init
update \builder_multiregimpl13_regs1 $1\builder_multiregimpl13_regs1[0:0]
end
- attribute \src "ls180.v:2731.32-2731.67"
- process $proc$ls180.v:2731$3695
+ attribute \src "ls180.v:2727.32-2727.67"
+ process $proc$ls180.v:2727$3695
assign { } { }
assign $1\builder_multiregimpl14_regs0[0:0] 1'0
sync always
sync init
update \builder_multiregimpl14_regs0 $1\builder_multiregimpl14_regs0[0:0]
end
- attribute \src "ls180.v:2732.32-2732.67"
- process $proc$ls180.v:2732$3696
+ attribute \src "ls180.v:2728.32-2728.67"
+ process $proc$ls180.v:2728$3696
assign { } { }
assign $1\builder_multiregimpl14_regs1[0:0] 1'0
sync always
sync init
update \builder_multiregimpl14_regs1 $1\builder_multiregimpl14_regs1[0:0]
end
- attribute \src "ls180.v:2733.32-2733.67"
- process $proc$ls180.v:2733$3697
+ attribute \src "ls180.v:2729.32-2729.67"
+ process $proc$ls180.v:2729$3697
assign { } { }
assign $1\builder_multiregimpl15_regs0[0:0] 1'0
sync always
sync init
update \builder_multiregimpl15_regs0 $1\builder_multiregimpl15_regs0[0:0]
end
- attribute \src "ls180.v:2734.32-2734.67"
- process $proc$ls180.v:2734$3698
+ attribute \src "ls180.v:2730.32-2730.67"
+ process $proc$ls180.v:2730$3698
assign { } { }
assign $1\builder_multiregimpl15_regs1[0:0] 1'0
sync always
sync init
update \builder_multiregimpl15_regs1 $1\builder_multiregimpl15_regs1[0:0]
end
- attribute \src "ls180.v:2735.32-2735.67"
- process $proc$ls180.v:2735$3699
+ attribute \src "ls180.v:2731.32-2731.67"
+ process $proc$ls180.v:2731$3699
assign { } { }
assign $1\builder_multiregimpl16_regs0[0:0] 1'0
sync always
sync init
update \builder_multiregimpl16_regs0 $1\builder_multiregimpl16_regs0[0:0]
end
- attribute \src "ls180.v:2736.32-2736.67"
- process $proc$ls180.v:2736$3700
+ attribute \src "ls180.v:2732.32-2732.67"
+ process $proc$ls180.v:2732$3700
assign { } { }
assign $1\builder_multiregimpl16_regs1[0:0] 1'0
sync always
sync init
update \builder_multiregimpl16_regs1 $1\builder_multiregimpl16_regs1[0:0]
end
- attribute \src "ls180.v:274.5-274.36"
- process $proc$ls180.v:274$2832
+ attribute \src "ls180.v:275.5-275.36"
+ process $proc$ls180.v:275$2834
assign { } { }
- assign $1\main_sdram_inti_p0_ras_n[0:0] 1'1
- sync always
- sync init
- update \main_sdram_inti_p0_ras_n $1\main_sdram_inti_p0_ras_n[0:0]
- end
- attribute \src "ls180.v:275.5-275.35"
- process $proc$ls180.v:275$2833
- assign { } { }
- assign $1\main_sdram_inti_p0_we_n[0:0] 1'1
+ assign $0\main_sdram_inti_p0_act_n[0:0] 1'1
sync always
+ update \main_sdram_inti_p0_act_n $0\main_sdram_inti_p0_act_n[0:0]
sync init
- update \main_sdram_inti_p0_we_n $1\main_sdram_inti_p0_we_n[0:0]
end
- attribute \src "ls180.v:2771.1-2776.4"
- process $proc$ls180.v:2771$13
+ attribute \src "ls180.v:2767.1-2772.4"
+ process $proc$ls180.v:2767$13
assign { } { }
assign $0\main_libresocsim_libresoc_interrupt[15:0] [11:2] 10'0000000000
assign $0\main_libresocsim_libresoc_interrupt[15:0] [15:12] { 1'0 \eint }
sync always
update \main_libresocsim_libresoc_interrupt $0\main_libresocsim_libresoc_interrupt[15:0]
end
- attribute \src "ls180.v:2778.1-2788.4"
- process $proc$ls180.v:2778$15
+ attribute \src "ls180.v:2774.1-2784.4"
+ process $proc$ls180.v:2774$15
assign { } { }
assign $0\main_libresocsim_interface0_converted_interface_dat_w[31:0] 0
- attribute \src "ls180.v:2780.2-2787.9"
+ attribute \src "ls180.v:2776.2-2783.9"
switch \main_libresocsim_converter0_counter
attribute \src "ls180.v:0.0-0.0"
case 1'0
sync always
update \main_libresocsim_interface0_converted_interface_dat_w $0\main_libresocsim_interface0_converted_interface_dat_w[31:0]
end
- attribute \src "ls180.v:279.5-279.36"
- process $proc$ls180.v:279$2834
- assign { } { }
- assign $0\main_sdram_inti_p0_act_n[0:0] 1'1
- sync always
- update \main_sdram_inti_p0_act_n $0\main_sdram_inti_p0_act_n[0:0]
- sync init
- end
- attribute \src "ls180.v:2790.1-2836.4"
- process $proc$ls180.v:2790$16
+ attribute \src "ls180.v:2786.1-2832.4"
+ process $proc$ls180.v:2786$16
assign { } { }
assign { } { }
assign { } { }
assign $0\main_libresocsim_interface0_converted_interface_cyc[0:0] 1'0
assign $0\main_libresocsim_interface0_converted_interface_stb[0:0] 1'0
assign $0\builder_converter0_next_state[0:0] \builder_converter0_state
- attribute \src "ls180.v:2802.2-2835.9"
+ attribute \src "ls180.v:2798.2-2831.9"
switch \builder_converter0_state
attribute \src "ls180.v:0.0-0.0"
case 1'1
assign $0\main_libresocsim_interface0_converted_interface_adr[29:0] { \main_libresocsim_libresoc_ibus_adr \main_libresocsim_converter0_counter }
- attribute \src "ls180.v:2805.4-2812.11"
+ attribute \src "ls180.v:2801.4-2808.11"
switch \main_libresocsim_converter0_counter
attribute \src "ls180.v:0.0-0.0"
case 1'0
assign $0\main_libresocsim_interface0_converted_interface_sel[3:0] \main_libresocsim_libresoc_ibus_sel [7:4]
case
end
- attribute \src "ls180.v:2813.4-2826.7"
- switch $and$ls180.v:2813$17_Y
- attribute \src "ls180.v:2813.8-2813.81"
+ attribute \src "ls180.v:2809.4-2822.7"
+ switch $and$ls180.v:2809$17_Y
+ attribute \src "ls180.v:2809.8-2809.81"
case 1'1
- assign $0\main_libresocsim_converter0_skip[0:0] $eq$ls180.v:2814$18_Y
+ assign $0\main_libresocsim_converter0_skip[0:0] $eq$ls180.v:2810$18_Y
assign $0\main_libresocsim_interface0_converted_interface_we[0:0] \main_libresocsim_libresoc_ibus_we
- assign $0\main_libresocsim_interface0_converted_interface_cyc[0:0] $not$ls180.v:2816$19_Y
- assign $0\main_libresocsim_interface0_converted_interface_stb[0:0] $not$ls180.v:2817$20_Y
- attribute \src "ls180.v:2818.5-2825.8"
- switch $or$ls180.v:2818$21_Y
- attribute \src "ls180.v:2818.9-2818.97"
+ assign $0\main_libresocsim_interface0_converted_interface_cyc[0:0] $not$ls180.v:2812$19_Y
+ assign $0\main_libresocsim_interface0_converted_interface_stb[0:0] $not$ls180.v:2813$20_Y
+ attribute \src "ls180.v:2814.5-2821.8"
+ switch $or$ls180.v:2814$21_Y
+ attribute \src "ls180.v:2814.9-2814.97"
case 1'1
- assign $0\main_libresocsim_converter0_counter_converter0_next_value[0:0] $add$ls180.v:2819$22_Y
+ assign $0\main_libresocsim_converter0_counter_converter0_next_value[0:0] $add$ls180.v:2815$22_Y
assign $0\main_libresocsim_converter0_counter_converter0_next_value_ce[0:0] 1'1
- attribute \src "ls180.v:2821.6-2824.9"
- switch $eq$ls180.v:2821$23_Y
- attribute \src "ls180.v:2821.10-2821.55"
+ attribute \src "ls180.v:2817.6-2820.9"
+ switch $eq$ls180.v:2817$23_Y
+ attribute \src "ls180.v:2817.10-2817.55"
case 1'1
assign $0\main_libresocsim_libresoc_ibus_ack[0:0] 1'1
assign $0\builder_converter0_next_state[0:0] 1'0
case
assign $0\main_libresocsim_converter0_counter_converter0_next_value[0:0] 1'0
assign $0\main_libresocsim_converter0_counter_converter0_next_value_ce[0:0] 1'1
- attribute \src "ls180.v:2831.4-2833.7"
- switch $and$ls180.v:2831$24_Y
- attribute \src "ls180.v:2831.8-2831.81"
+ attribute \src "ls180.v:2827.4-2829.7"
+ switch $and$ls180.v:2827$24_Y
+ attribute \src "ls180.v:2827.8-2827.81"
case 1'1
assign $0\builder_converter0_next_state[0:0] 1'1
case
update \main_libresocsim_converter0_counter_converter0_next_value $0\main_libresocsim_converter0_counter_converter0_next_value[0:0]
update \main_libresocsim_converter0_counter_converter0_next_value_ce $0\main_libresocsim_converter0_counter_converter0_next_value_ce[0:0]
end
- attribute \src "ls180.v:2838.1-2848.4"
- process $proc$ls180.v:2838$26
+ attribute \src "ls180.v:280.12-280.45"
+ process $proc$ls180.v:280$2835
+ assign { } { }
+ assign $1\main_sdram_inti_p0_rddata[15:0] 16'0000000000000000
+ sync always
+ sync init
+ update \main_sdram_inti_p0_rddata $1\main_sdram_inti_p0_rddata[15:0]
+ end
+ attribute \src "ls180.v:281.5-281.43"
+ process $proc$ls180.v:281$2836
+ assign { } { }
+ assign $1\main_sdram_inti_p0_rddata_valid[0:0] 1'0
+ sync always
+ sync init
+ update \main_sdram_inti_p0_rddata_valid $1\main_sdram_inti_p0_rddata_valid[0:0]
+ end
+ attribute \src "ls180.v:2834.1-2844.4"
+ process $proc$ls180.v:2834$26
assign { } { }
assign $0\main_libresocsim_interface1_converted_interface_dat_w[31:0] 0
- attribute \src "ls180.v:2840.2-2847.9"
+ attribute \src "ls180.v:2836.2-2843.9"
switch \main_libresocsim_converter1_counter
attribute \src "ls180.v:0.0-0.0"
case 1'0
sync always
update \main_libresocsim_interface1_converted_interface_dat_w $0\main_libresocsim_interface1_converted_interface_dat_w[31:0]
end
- attribute \src "ls180.v:284.12-284.45"
- process $proc$ls180.v:284$2835
- assign { } { }
- assign $1\main_sdram_inti_p0_rddata[15:0] 16'0000000000000000
- sync always
- sync init
- update \main_sdram_inti_p0_rddata $1\main_sdram_inti_p0_rddata[15:0]
- end
- attribute \src "ls180.v:285.5-285.43"
- process $proc$ls180.v:285$2836
- assign { } { }
- assign $1\main_sdram_inti_p0_rddata_valid[0:0] 1'0
- sync always
- sync init
- update \main_sdram_inti_p0_rddata_valid $1\main_sdram_inti_p0_rddata_valid[0:0]
- end
- attribute \src "ls180.v:2850.1-2896.4"
- process $proc$ls180.v:2850$27
+ attribute \src "ls180.v:2846.1-2892.4"
+ process $proc$ls180.v:2846$27
assign { } { }
assign { } { }
assign { } { }
assign $0\main_libresocsim_interface1_converted_interface_stb[0:0] 1'0
assign $0\main_libresocsim_interface1_converted_interface_we[0:0] 1'0
assign $0\builder_converter1_next_state[0:0] \builder_converter1_state
- attribute \src "ls180.v:2862.2-2895.9"
+ attribute \src "ls180.v:2858.2-2891.9"
switch \builder_converter1_state
attribute \src "ls180.v:0.0-0.0"
case 1'1
assign $0\main_libresocsim_interface1_converted_interface_adr[29:0] { \main_libresocsim_libresoc_dbus_adr \main_libresocsim_converter1_counter }
- attribute \src "ls180.v:2865.4-2872.11"
+ attribute \src "ls180.v:2861.4-2868.11"
switch \main_libresocsim_converter1_counter
attribute \src "ls180.v:0.0-0.0"
case 1'0
assign $0\main_libresocsim_interface1_converted_interface_sel[3:0] \main_libresocsim_libresoc_dbus_sel [7:4]
case
end
- attribute \src "ls180.v:2873.4-2886.7"
- switch $and$ls180.v:2873$28_Y
- attribute \src "ls180.v:2873.8-2873.81"
+ attribute \src "ls180.v:2869.4-2882.7"
+ switch $and$ls180.v:2869$28_Y
+ attribute \src "ls180.v:2869.8-2869.81"
case 1'1
- assign $0\main_libresocsim_converter1_skip[0:0] $eq$ls180.v:2874$29_Y
+ assign $0\main_libresocsim_converter1_skip[0:0] $eq$ls180.v:2870$29_Y
assign $0\main_libresocsim_interface1_converted_interface_we[0:0] \main_libresocsim_libresoc_dbus_we
- assign $0\main_libresocsim_interface1_converted_interface_cyc[0:0] $not$ls180.v:2876$30_Y
- assign $0\main_libresocsim_interface1_converted_interface_stb[0:0] $not$ls180.v:2877$31_Y
- attribute \src "ls180.v:2878.5-2885.8"
- switch $or$ls180.v:2878$32_Y
- attribute \src "ls180.v:2878.9-2878.97"
+ assign $0\main_libresocsim_interface1_converted_interface_cyc[0:0] $not$ls180.v:2872$30_Y
+ assign $0\main_libresocsim_interface1_converted_interface_stb[0:0] $not$ls180.v:2873$31_Y
+ attribute \src "ls180.v:2874.5-2881.8"
+ switch $or$ls180.v:2874$32_Y
+ attribute \src "ls180.v:2874.9-2874.97"
case 1'1
- assign $0\main_libresocsim_converter1_counter_converter1_next_value[0:0] $add$ls180.v:2879$33_Y
+ assign $0\main_libresocsim_converter1_counter_converter1_next_value[0:0] $add$ls180.v:2875$33_Y
assign $0\main_libresocsim_converter1_counter_converter1_next_value_ce[0:0] 1'1
- attribute \src "ls180.v:2881.6-2884.9"
- switch $eq$ls180.v:2881$34_Y
- attribute \src "ls180.v:2881.10-2881.55"
+ attribute \src "ls180.v:2877.6-2880.9"
+ switch $eq$ls180.v:2877$34_Y
+ attribute \src "ls180.v:2877.10-2877.55"
case 1'1
assign $0\main_libresocsim_libresoc_dbus_ack[0:0] 1'1
assign $0\builder_converter1_next_state[0:0] 1'0
case
assign $0\main_libresocsim_converter1_counter_converter1_next_value[0:0] 1'0
assign $0\main_libresocsim_converter1_counter_converter1_next_value_ce[0:0] 1'1
- attribute \src "ls180.v:2891.4-2893.7"
- switch $and$ls180.v:2891$35_Y
- attribute \src "ls180.v:2891.8-2891.81"
+ attribute \src "ls180.v:2887.4-2889.7"
+ switch $and$ls180.v:2887$35_Y
+ attribute \src "ls180.v:2887.8-2887.81"
case 1'1
assign $0\builder_converter1_next_state[0:0] 1'1
case
update \main_libresocsim_converter1_counter_converter1_next_value $0\main_libresocsim_converter1_counter_converter1_next_value[0:0]
update \main_libresocsim_converter1_counter_converter1_next_value_ce $0\main_libresocsim_converter1_counter_converter1_next_value_ce[0:0]
end
- attribute \src "ls180.v:2898.1-2908.4"
- process $proc$ls180.v:2898$37
+ attribute \src "ls180.v:2894.1-2904.4"
+ process $proc$ls180.v:2894$37
assign { } { }
assign $0\main_libresocsim_interface2_converted_interface_dat_w[31:0] 0
- attribute \src "ls180.v:2900.2-2907.9"
+ attribute \src "ls180.v:2896.2-2903.9"
switch \main_libresocsim_converter2_counter
attribute \src "ls180.v:0.0-0.0"
case 1'0
sync always
update \main_libresocsim_interface2_converted_interface_dat_w $0\main_libresocsim_interface2_converted_interface_dat_w[31:0]
end
- attribute \src "ls180.v:2910.1-2956.4"
- process $proc$ls180.v:2910$38
+ attribute \src "ls180.v:2906.1-2952.4"
+ process $proc$ls180.v:2906$38
assign { } { }
assign { } { }
assign { } { }
assign $0\main_libresocsim_interface2_converted_interface_we[0:0] 1'0
assign $0\main_libresocsim_converter2_skip[0:0] 1'0
assign $0\builder_converter2_next_state[0:0] \builder_converter2_state
- attribute \src "ls180.v:2922.2-2955.9"
+ attribute \src "ls180.v:2918.2-2951.9"
switch \builder_converter2_state
attribute \src "ls180.v:0.0-0.0"
case 1'1
assign $0\main_libresocsim_interface2_converted_interface_adr[29:0] { \main_libresocsim_libresoc_jtag_wb_adr \main_libresocsim_converter2_counter }
- attribute \src "ls180.v:2925.4-2932.11"
+ attribute \src "ls180.v:2921.4-2928.11"
switch \main_libresocsim_converter2_counter
attribute \src "ls180.v:0.0-0.0"
case 1'0
assign $0\main_libresocsim_interface2_converted_interface_sel[3:0] \main_libresocsim_libresoc_jtag_wb_sel [7:4]
case
end
- attribute \src "ls180.v:2933.4-2946.7"
- switch $and$ls180.v:2933$39_Y
- attribute \src "ls180.v:2933.8-2933.87"
+ attribute \src "ls180.v:2929.4-2942.7"
+ switch $and$ls180.v:2929$39_Y
+ attribute \src "ls180.v:2929.8-2929.87"
case 1'1
- assign $0\main_libresocsim_converter2_skip[0:0] $eq$ls180.v:2934$40_Y
+ assign $0\main_libresocsim_converter2_skip[0:0] $eq$ls180.v:2930$40_Y
assign $0\main_libresocsim_interface2_converted_interface_we[0:0] \main_libresocsim_libresoc_jtag_wb_we
- assign $0\main_libresocsim_interface2_converted_interface_cyc[0:0] $not$ls180.v:2936$41_Y
- assign $0\main_libresocsim_interface2_converted_interface_stb[0:0] $not$ls180.v:2937$42_Y
- attribute \src "ls180.v:2938.5-2945.8"
- switch $or$ls180.v:2938$43_Y
- attribute \src "ls180.v:2938.9-2938.97"
+ assign $0\main_libresocsim_interface2_converted_interface_cyc[0:0] $not$ls180.v:2932$41_Y
+ assign $0\main_libresocsim_interface2_converted_interface_stb[0:0] $not$ls180.v:2933$42_Y
+ attribute \src "ls180.v:2934.5-2941.8"
+ switch $or$ls180.v:2934$43_Y
+ attribute \src "ls180.v:2934.9-2934.97"
case 1'1
- assign $0\main_libresocsim_converter2_counter_converter2_next_value[0:0] $add$ls180.v:2939$44_Y
+ assign $0\main_libresocsim_converter2_counter_converter2_next_value[0:0] $add$ls180.v:2935$44_Y
assign $0\main_libresocsim_converter2_counter_converter2_next_value_ce[0:0] 1'1
- attribute \src "ls180.v:2941.6-2944.9"
- switch $eq$ls180.v:2941$45_Y
- attribute \src "ls180.v:2941.10-2941.55"
+ attribute \src "ls180.v:2937.6-2940.9"
+ switch $eq$ls180.v:2937$45_Y
+ attribute \src "ls180.v:2937.10-2937.55"
case 1'1
assign $0\main_libresocsim_libresoc_jtag_wb_ack[0:0] 1'1
assign $0\builder_converter2_next_state[0:0] 1'0
case
assign $0\main_libresocsim_converter2_counter_converter2_next_value[0:0] 1'0
assign $0\main_libresocsim_converter2_counter_converter2_next_value_ce[0:0] 1'1
- attribute \src "ls180.v:2951.4-2953.7"
- switch $and$ls180.v:2951$46_Y
- attribute \src "ls180.v:2951.8-2951.87"
+ attribute \src "ls180.v:2947.4-2949.7"
+ switch $and$ls180.v:2947$46_Y
+ attribute \src "ls180.v:2947.8-2947.87"
case 1'1
assign $0\builder_converter2_next_state[0:0] 1'1
case
update \main_libresocsim_converter2_counter_converter2_next_value $0\main_libresocsim_converter2_counter_converter2_next_value[0:0]
update \main_libresocsim_converter2_counter_converter2_next_value_ce $0\main_libresocsim_converter2_counter_converter2_next_value_ce[0:0]
end
- attribute \src "ls180.v:2959.1-2965.4"
- process $proc$ls180.v:2959$47
+ attribute \src "ls180.v:2955.1-2961.4"
+ process $proc$ls180.v:2955$47
assign { } { }
assign { } { }
- assign $0\main_libresocsim_we[3:0] [0] $and$ls180.v:2961$50_Y
- assign $0\main_libresocsim_we[3:0] [1] $and$ls180.v:2962$53_Y
- assign $0\main_libresocsim_we[3:0] [2] $and$ls180.v:2963$56_Y
- assign $0\main_libresocsim_we[3:0] [3] $and$ls180.v:2964$59_Y
+ assign $0\main_libresocsim_we[3:0] [0] $and$ls180.v:2957$50_Y
+ assign $0\main_libresocsim_we[3:0] [1] $and$ls180.v:2958$53_Y
+ assign $0\main_libresocsim_we[3:0] [2] $and$ls180.v:2959$56_Y
+ assign $0\main_libresocsim_we[3:0] [3] $and$ls180.v:2960$59_Y
sync always
update \main_libresocsim_we $0\main_libresocsim_we[3:0]
end
- attribute \src "ls180.v:2971.1-2976.4"
- process $proc$ls180.v:2971$61
+ attribute \src "ls180.v:296.12-296.46"
+ process $proc$ls180.v:296$2837
+ assign { } { }
+ assign $1\main_sdram_slave_p0_rddata[15:0] 16'0000000000000000
+ sync always
+ sync init
+ update \main_sdram_slave_p0_rddata $1\main_sdram_slave_p0_rddata[15:0]
+ end
+ attribute \src "ls180.v:2967.1-2972.4"
+ process $proc$ls180.v:2967$61
assign { } { }
assign $0\main_libresocsim_zero_clear[0:0] 1'0
- attribute \src "ls180.v:2973.2-2975.5"
- switch $and$ls180.v:2973$62_Y
- attribute \src "ls180.v:2973.6-2973.90"
+ attribute \src "ls180.v:2969.2-2971.5"
+ switch $and$ls180.v:2969$62_Y
+ attribute \src "ls180.v:2969.6-2969.90"
case 1'1
assign $0\main_libresocsim_zero_clear[0:0] 1'1
case
sync always
update \main_libresocsim_zero_clear $0\main_libresocsim_zero_clear[0:0]
end
- attribute \src "ls180.v:300.12-300.46"
- process $proc$ls180.v:300$2837
+ attribute \src "ls180.v:297.5-297.44"
+ process $proc$ls180.v:297$2838
assign { } { }
- assign $1\main_sdram_slave_p0_rddata[15:0] 16'0000000000000000
+ assign $1\main_sdram_slave_p0_rddata_valid[0:0] 1'0
sync always
sync init
- update \main_sdram_slave_p0_rddata $1\main_sdram_slave_p0_rddata[15:0]
+ update \main_sdram_slave_p0_rddata_valid $1\main_sdram_slave_p0_rddata_valid[0:0]
end
- attribute \src "ls180.v:301.5-301.44"
- process $proc$ls180.v:301$2838
+ attribute \src "ls180.v:298.12-298.48"
+ process $proc$ls180.v:298$2839
assign { } { }
- assign $1\main_sdram_slave_p0_rddata_valid[0:0] 1'0
+ assign $1\main_sdram_master_p0_address[12:0] 13'0000000000000
sync always
sync init
- update \main_sdram_slave_p0_rddata_valid $1\main_sdram_slave_p0_rddata_valid[0:0]
+ update \main_sdram_master_p0_address $1\main_sdram_master_p0_address[12:0]
+ end
+ attribute \src "ls180.v:299.11-299.43"
+ process $proc$ls180.v:299$2840
+ assign { } { }
+ assign $1\main_sdram_master_p0_bank[1:0] 2'00
+ sync always
+ sync init
+ update \main_sdram_master_p0_bank $1\main_sdram_master_p0_bank[1:0]
+ end
+ attribute \src "ls180.v:300.5-300.38"
+ process $proc$ls180.v:300$2841
+ assign { } { }
+ assign $1\main_sdram_master_p0_cas_n[0:0] 1'1
+ sync always
+ sync init
+ update \main_sdram_master_p0_cas_n $1\main_sdram_master_p0_cas_n[0:0]
+ end
+ attribute \src "ls180.v:301.5-301.37"
+ process $proc$ls180.v:301$2842
+ assign { } { }
+ assign $1\main_sdram_master_p0_cs_n[0:0] 1'1
+ sync always
+ sync init
+ update \main_sdram_master_p0_cs_n $1\main_sdram_master_p0_cs_n[0:0]
end
- attribute \src "ls180.v:3015.1-3069.4"
- process $proc$ls180.v:3015$64
+ attribute \src "ls180.v:3011.1-3065.4"
+ process $proc$ls180.v:3011$64
assign { } { }
assign { } { }
assign { } { }
assign $0\main_sdram_master_p0_odt[0:0] 1'0
assign $0\main_sdram_master_p0_reset_n[0:0] 1'0
assign $0\main_sdram_inti_p0_rddata[15:0] 16'0000000000000000
- attribute \src "ls180.v:3034.2-3068.5"
+ attribute \src "ls180.v:3030.2-3064.5"
switch \main_sdram_sel
- attribute \src "ls180.v:3034.6-3034.20"
+ attribute \src "ls180.v:3030.6-3030.20"
case 1'1
assign $0\main_sdram_master_p0_address[12:0] \main_sdram_slave_p0_address
assign $0\main_sdram_master_p0_bank[1:0] \main_sdram_slave_p0_bank
assign $0\main_sdram_master_p0_rddata_en[0:0] \main_sdram_slave_p0_rddata_en
assign $0\main_sdram_slave_p0_rddata[15:0] \main_sdram_master_p0_rddata
assign $0\main_sdram_slave_p0_rddata_valid[0:0] \main_sdram_master_p0_rddata_valid
- attribute \src "ls180.v:3051.6-3051.10"
+ attribute \src "ls180.v:3047.6-3047.10"
case
assign $0\main_sdram_master_p0_address[12:0] \main_sdram_inti_p0_address
assign $0\main_sdram_master_p0_bank[1:0] \main_sdram_inti_p0_bank
update \main_sdram_master_p0_wrdata_mask $0\main_sdram_master_p0_wrdata_mask[1:0]
update \main_sdram_master_p0_rddata_en $0\main_sdram_master_p0_rddata_en[0:0]
end
- attribute \src "ls180.v:302.12-302.48"
- process $proc$ls180.v:302$2839
- assign { } { }
- assign $1\main_sdram_master_p0_address[12:0] 13'0000000000000
- sync always
- sync init
- update \main_sdram_master_p0_address $1\main_sdram_master_p0_address[12:0]
- end
- attribute \src "ls180.v:303.11-303.43"
- process $proc$ls180.v:303$2840
+ attribute \src "ls180.v:302.5-302.38"
+ process $proc$ls180.v:302$2843
assign { } { }
- assign $1\main_sdram_master_p0_bank[1:0] 2'00
+ assign $1\main_sdram_master_p0_ras_n[0:0] 1'1
sync always
sync init
- update \main_sdram_master_p0_bank $1\main_sdram_master_p0_bank[1:0]
+ update \main_sdram_master_p0_ras_n $1\main_sdram_master_p0_ras_n[0:0]
end
- attribute \src "ls180.v:304.5-304.38"
- process $proc$ls180.v:304$2841
+ attribute \src "ls180.v:303.5-303.37"
+ process $proc$ls180.v:303$2844
assign { } { }
- assign $1\main_sdram_master_p0_cas_n[0:0] 1'1
+ assign $1\main_sdram_master_p0_we_n[0:0] 1'1
sync always
sync init
- update \main_sdram_master_p0_cas_n $1\main_sdram_master_p0_cas_n[0:0]
+ update \main_sdram_master_p0_we_n $1\main_sdram_master_p0_we_n[0:0]
end
- attribute \src "ls180.v:305.5-305.37"
- process $proc$ls180.v:305$2842
+ attribute \src "ls180.v:304.5-304.36"
+ process $proc$ls180.v:304$2845
assign { } { }
- assign $1\main_sdram_master_p0_cs_n[0:0] 1'1
+ assign $1\main_sdram_master_p0_cke[0:0] 1'0
sync always
sync init
- update \main_sdram_master_p0_cs_n $1\main_sdram_master_p0_cs_n[0:0]
+ update \main_sdram_master_p0_cke $1\main_sdram_master_p0_cke[0:0]
end
- attribute \src "ls180.v:306.5-306.38"
- process $proc$ls180.v:306$2843
+ attribute \src "ls180.v:305.5-305.36"
+ process $proc$ls180.v:305$2846
assign { } { }
- assign $1\main_sdram_master_p0_ras_n[0:0] 1'1
+ assign $1\main_sdram_master_p0_odt[0:0] 1'0
sync always
sync init
- update \main_sdram_master_p0_ras_n $1\main_sdram_master_p0_ras_n[0:0]
+ update \main_sdram_master_p0_odt $1\main_sdram_master_p0_odt[0:0]
end
- attribute \src "ls180.v:307.5-307.37"
- process $proc$ls180.v:307$2844
+ attribute \src "ls180.v:306.5-306.40"
+ process $proc$ls180.v:306$2847
assign { } { }
- assign $1\main_sdram_master_p0_we_n[0:0] 1'1
+ assign $1\main_sdram_master_p0_reset_n[0:0] 1'0
sync always
sync init
- update \main_sdram_master_p0_we_n $1\main_sdram_master_p0_we_n[0:0]
+ update \main_sdram_master_p0_reset_n $1\main_sdram_master_p0_reset_n[0:0]
end
- attribute \src "ls180.v:3073.1-3089.4"
- process $proc$ls180.v:3073$65
+ attribute \src "ls180.v:3069.1-3085.4"
+ process $proc$ls180.v:3069$65
assign { } { }
assign { } { }
assign { } { }
assign $0\main_sdram_inti_p0_ras_n[0:0] 1'1
assign $0\main_sdram_inti_p0_we_n[0:0] 1'1
assign $0\main_sdram_inti_p0_cas_n[0:0] 1'1
- attribute \src "ls180.v:3078.2-3088.5"
+ attribute \src "ls180.v:3074.2-3084.5"
switch \main_sdram_command_issue_re
- attribute \src "ls180.v:3078.6-3078.33"
+ attribute \src "ls180.v:3074.6-3074.33"
case 1'1
- assign $0\main_sdram_inti_p0_cs_n[0:0] $not$ls180.v:3079$66_Y
- assign $0\main_sdram_inti_p0_we_n[0:0] $not$ls180.v:3080$67_Y
- assign $0\main_sdram_inti_p0_cas_n[0:0] $not$ls180.v:3081$68_Y
- assign $0\main_sdram_inti_p0_ras_n[0:0] $not$ls180.v:3082$69_Y
- attribute \src "ls180.v:3083.6-3083.10"
+ assign $0\main_sdram_inti_p0_cs_n[0:0] $not$ls180.v:3075$66_Y
+ assign $0\main_sdram_inti_p0_we_n[0:0] $not$ls180.v:3076$67_Y
+ assign $0\main_sdram_inti_p0_cas_n[0:0] $not$ls180.v:3077$68_Y
+ assign $0\main_sdram_inti_p0_ras_n[0:0] $not$ls180.v:3078$69_Y
+ attribute \src "ls180.v:3079.6-3079.10"
case
assign $0\main_sdram_inti_p0_cs_n[0:0] 1'1
assign $0\main_sdram_inti_p0_we_n[0:0] 1'1
update \main_sdram_inti_p0_ras_n $0\main_sdram_inti_p0_ras_n[0:0]
update \main_sdram_inti_p0_we_n $0\main_sdram_inti_p0_we_n[0:0]
end
- attribute \src "ls180.v:308.5-308.36"
- process $proc$ls180.v:308$2845
- assign { } { }
- assign $1\main_sdram_master_p0_cke[0:0] 1'0
- sync always
- sync init
- update \main_sdram_master_p0_cke $1\main_sdram_master_p0_cke[0:0]
- end
- attribute \src "ls180.v:309.5-309.36"
- process $proc$ls180.v:309$2846
+ attribute \src "ls180.v:307.5-307.38"
+ process $proc$ls180.v:307$2848
assign { } { }
- assign $1\main_sdram_master_p0_odt[0:0] 1'0
+ assign $1\main_sdram_master_p0_act_n[0:0] 1'1
sync always
sync init
- update \main_sdram_master_p0_odt $1\main_sdram_master_p0_odt[0:0]
+ update \main_sdram_master_p0_act_n $1\main_sdram_master_p0_act_n[0:0]
end
- attribute \src "ls180.v:310.5-310.40"
- process $proc$ls180.v:310$2847
+ attribute \src "ls180.v:308.12-308.47"
+ process $proc$ls180.v:308$2849
assign { } { }
- assign $1\main_sdram_master_p0_reset_n[0:0] 1'0
+ assign $1\main_sdram_master_p0_wrdata[15:0] 16'0000000000000000
sync always
sync init
- update \main_sdram_master_p0_reset_n $1\main_sdram_master_p0_reset_n[0:0]
+ update \main_sdram_master_p0_wrdata $1\main_sdram_master_p0_wrdata[15:0]
end
- attribute \src "ls180.v:311.5-311.38"
- process $proc$ls180.v:311$2848
+ attribute \src "ls180.v:309.5-309.42"
+ process $proc$ls180.v:309$2850
assign { } { }
- assign $1\main_sdram_master_p0_act_n[0:0] 1'1
+ assign $1\main_sdram_master_p0_wrdata_en[0:0] 1'0
sync always
sync init
- update \main_sdram_master_p0_act_n $1\main_sdram_master_p0_act_n[0:0]
+ update \main_sdram_master_p0_wrdata_en $1\main_sdram_master_p0_wrdata_en[0:0]
end
- attribute \src "ls180.v:312.12-312.47"
- process $proc$ls180.v:312$2849
+ attribute \src "ls180.v:310.11-310.50"
+ process $proc$ls180.v:310$2851
assign { } { }
- assign $1\main_sdram_master_p0_wrdata[15:0] 16'0000000000000000
+ assign $1\main_sdram_master_p0_wrdata_mask[1:0] 2'00
sync always
sync init
- update \main_sdram_master_p0_wrdata $1\main_sdram_master_p0_wrdata[15:0]
+ update \main_sdram_master_p0_wrdata_mask $1\main_sdram_master_p0_wrdata_mask[1:0]
end
- attribute \src "ls180.v:313.5-313.42"
- process $proc$ls180.v:313$2850
+ attribute \src "ls180.v:311.5-311.42"
+ process $proc$ls180.v:311$2852
assign { } { }
- assign $1\main_sdram_master_p0_wrdata_en[0:0] 1'0
+ assign $1\main_sdram_master_p0_rddata_en[0:0] 1'0
sync always
sync init
- update \main_sdram_master_p0_wrdata_en $1\main_sdram_master_p0_wrdata_en[0:0]
+ update \main_sdram_master_p0_rddata_en $1\main_sdram_master_p0_rddata_en[0:0]
end
- attribute \src "ls180.v:3132.1-3162.4"
- process $proc$ls180.v:3132$78
+ attribute \src "ls180.v:3128.1-3158.4"
+ process $proc$ls180.v:3128$78
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign $0\main_sdram_cmd_valid[0:0] 1'0
assign $0\builder_refresher_next_state[1:0] \builder_refresher_state
- attribute \src "ls180.v:3138.2-3161.9"
+ attribute \src "ls180.v:3134.2-3157.9"
switch \builder_refresher_state
attribute \src "ls180.v:0.0-0.0"
case 2'01
assign $0\main_sdram_cmd_valid[0:0] 1'1
- attribute \src "ls180.v:3141.4-3144.7"
+ attribute \src "ls180.v:3137.4-3140.7"
switch \main_sdram_cmd_ready
- attribute \src "ls180.v:3141.8-3141.28"
+ attribute \src "ls180.v:3137.8-3137.28"
case 1'1
assign $0\main_sdram_sequencer_start0[0:0] 1'1
assign $0\builder_refresher_next_state[1:0] 2'10
attribute \src "ls180.v:0.0-0.0"
case 2'10
assign $0\main_sdram_cmd_valid[0:0] 1'1
- attribute \src "ls180.v:3148.4-3152.7"
+ attribute \src "ls180.v:3144.4-3148.7"
switch \main_sdram_sequencer_done0
- attribute \src "ls180.v:3148.8-3148.34"
+ attribute \src "ls180.v:3144.8-3144.34"
case 1'1
assign $0\main_sdram_cmd_valid[0:0] 1'0
assign $0\main_sdram_cmd_last[0:0] 1'1
end
attribute \src "ls180.v:0.0-0.0"
case
- attribute \src "ls180.v:3155.4-3159.7"
+ attribute \src "ls180.v:3151.4-3155.7"
switch 1'1
- attribute \src "ls180.v:3155.8-3155.12"
+ attribute \src "ls180.v:3151.8-3151.12"
case 1'1
- attribute \src "ls180.v:3156.5-3158.8"
+ attribute \src "ls180.v:3152.5-3154.8"
switch \main_sdram_wants_refresh
- attribute \src "ls180.v:3156.9-3156.33"
+ attribute \src "ls180.v:3152.9-3152.33"
case 1'1
assign $0\builder_refresher_next_state[1:0] 2'01
case
update \main_sdram_sequencer_start0 $0\main_sdram_sequencer_start0[0:0]
update \builder_refresher_next_state $0\builder_refresher_next_state[1:0]
end
- attribute \src "ls180.v:314.11-314.50"
- process $proc$ls180.v:314$2851
- assign { } { }
- assign $1\main_sdram_master_p0_wrdata_mask[1:0] 2'00
- sync always
- sync init
- update \main_sdram_master_p0_wrdata_mask $1\main_sdram_master_p0_wrdata_mask[1:0]
- end
- attribute \src "ls180.v:315.5-315.42"
- process $proc$ls180.v:315$2852
- assign { } { }
- assign $1\main_sdram_master_p0_rddata_en[0:0] 1'0
- sync always
- sync init
- update \main_sdram_master_p0_rddata_en $1\main_sdram_master_p0_rddata_en[0:0]
- end
- attribute \src "ls180.v:3177.1-3184.4"
- process $proc$ls180.v:3177$82
+ attribute \src "ls180.v:3173.1-3180.4"
+ process $proc$ls180.v:3173$82
assign { } { }
assign $0\main_sdram_bankmachine0_cmd_payload_a[12:0] 13'0000000000000
- attribute \src "ls180.v:3179.2-3183.5"
+ attribute \src "ls180.v:3175.2-3179.5"
switch \main_sdram_bankmachine0_row_col_n_addr_sel
- attribute \src "ls180.v:3179.6-3179.48"
+ attribute \src "ls180.v:3175.6-3175.48"
case 1'1
assign $0\main_sdram_bankmachine0_cmd_payload_a[12:0] \main_sdram_bankmachine0_cmd_buffer_source_payload_addr [21:9]
- attribute \src "ls180.v:3181.6-3181.10"
+ attribute \src "ls180.v:3177.6-3177.10"
case
- assign $0\main_sdram_bankmachine0_cmd_payload_a[12:0] $or$ls180.v:3182$84_Y
+ assign $0\main_sdram_bankmachine0_cmd_payload_a[12:0] $or$ls180.v:3178$84_Y
end
sync always
update \main_sdram_bankmachine0_cmd_payload_a $0\main_sdram_bankmachine0_cmd_payload_a[12:0]
end
- attribute \src "ls180.v:3188.1-3195.4"
- process $proc$ls180.v:3188$91
+ attribute \src "ls180.v:318.11-318.36"
+ process $proc$ls180.v:318$2853
+ assign { } { }
+ assign $1\main_sdram_storage[3:0] 4'0001
+ sync always
+ sync init
+ update \main_sdram_storage $1\main_sdram_storage[3:0]
+ end
+ attribute \src "ls180.v:3184.1-3191.4"
+ process $proc$ls180.v:3184$91
assign { } { }
assign $0\main_sdram_bankmachine0_auto_precharge[0:0] 1'0
- attribute \src "ls180.v:3190.2-3194.5"
- switch $and$ls180.v:3190$92_Y
- attribute \src "ls180.v:3190.6-3190.115"
+ attribute \src "ls180.v:3186.2-3190.5"
+ switch $and$ls180.v:3186$92_Y
+ attribute \src "ls180.v:3186.6-3186.115"
case 1'1
- attribute \src "ls180.v:3191.3-3193.6"
- switch $ne$ls180.v:3191$93_Y
- attribute \src "ls180.v:3191.7-3191.143"
+ attribute \src "ls180.v:3187.3-3189.6"
+ switch $ne$ls180.v:3187$93_Y
+ attribute \src "ls180.v:3187.7-3187.143"
case 1'1
- assign $0\main_sdram_bankmachine0_auto_precharge[0:0] $eq$ls180.v:3192$94_Y
+ assign $0\main_sdram_bankmachine0_auto_precharge[0:0] $eq$ls180.v:3188$94_Y
case
end
case
sync always
update \main_sdram_bankmachine0_auto_precharge $0\main_sdram_bankmachine0_auto_precharge[0:0]
end
- attribute \src "ls180.v:3210.1-3217.4"
- process $proc$ls180.v:3210$95
+ attribute \src "ls180.v:319.5-319.25"
+ process $proc$ls180.v:319$2854
+ assign { } { }
+ assign $1\main_sdram_re[0:0] 1'0
+ sync always
+ sync init
+ update \main_sdram_re $1\main_sdram_re[0:0]
+ end
+ attribute \src "ls180.v:320.11-320.44"
+ process $proc$ls180.v:320$2855
+ assign { } { }
+ assign $1\main_sdram_command_storage[5:0] 6'000000
+ sync always
+ sync init
+ update \main_sdram_command_storage $1\main_sdram_command_storage[5:0]
+ end
+ attribute \src "ls180.v:3206.1-3213.4"
+ process $proc$ls180.v:3206$95
assign { } { }
assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] 3'000
- attribute \src "ls180.v:3212.2-3216.5"
+ attribute \src "ls180.v:3208.2-3212.5"
switch \main_sdram_bankmachine0_cmd_buffer_lookahead_replace
- attribute \src "ls180.v:3212.6-3212.58"
+ attribute \src "ls180.v:3208.6-3208.58"
case 1'1
- assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:3213$96_Y
- attribute \src "ls180.v:3214.6-3214.10"
+ assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:3209$96_Y
+ attribute \src "ls180.v:3210.6-3210.10"
case
assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] \main_sdram_bankmachine0_cmd_buffer_lookahead_produce
end
sync always
update \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr $0\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0]
end
- attribute \src "ls180.v:322.11-322.36"
- process $proc$ls180.v:322$2853
+ attribute \src "ls180.v:321.5-321.33"
+ process $proc$ls180.v:321$2856
assign { } { }
- assign $1\main_sdram_storage[3:0] 4'0001
+ assign $1\main_sdram_command_re[0:0] 1'0
sync always
sync init
- update \main_sdram_storage $1\main_sdram_storage[3:0]
+ update \main_sdram_command_re $1\main_sdram_command_re[0:0]
end
- attribute \src "ls180.v:3226.1-3319.4"
- process $proc$ls180.v:3226$104
+ attribute \src "ls180.v:3222.1-3315.4"
+ process $proc$ls180.v:3222$104
assign { } { }
assign { } { }
assign { } { }
assign $0\main_sdram_bankmachine0_req_rdata_valid[0:0] 1'0
assign $0\main_sdram_bankmachine0_refresh_gnt[0:0] 1'0
assign $0\main_sdram_bankmachine0_cmd_valid[0:0] 1'0
+ assign $0\main_sdram_bankmachine0_cmd_payload_we[0:0] 1'0
assign $0\main_sdram_bankmachine0_row_open[0:0] 1'0
assign $0\main_sdram_bankmachine0_row_close[0:0] 1'0
assign $0\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] 1'0
- assign { } { }
assign $0\main_sdram_bankmachine0_cmd_payload_cas[0:0] 1'0
assign $0\main_sdram_bankmachine0_cmd_payload_ras[0:0] 1'0
- assign $0\main_sdram_bankmachine0_cmd_payload_we[0:0] 1'0
+ assign { } { }
assign $0\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'0
assign $0\main_sdram_bankmachine0_cmd_payload_is_read[0:0] 1'0
assign $0\main_sdram_bankmachine0_cmd_payload_is_write[0:0] 1'0
assign $0\builder_bankmachine0_next_state[2:0] \builder_bankmachine0_state
- attribute \src "ls180.v:3242.2-3318.9"
+ attribute \src "ls180.v:3238.2-3314.9"
switch \builder_bankmachine0_state
attribute \src "ls180.v:0.0-0.0"
case 3'001
assign $0\main_sdram_bankmachine0_row_close[0:0] 1'1
- attribute \src "ls180.v:3244.4-3252.7"
- switch $and$ls180.v:3244$105_Y
- attribute \src "ls180.v:3244.8-3244.87"
+ attribute \src "ls180.v:3240.4-3248.7"
+ switch $and$ls180.v:3240$105_Y
+ attribute \src "ls180.v:3240.8-3240.87"
case 1'1
assign $0\main_sdram_bankmachine0_cmd_valid[0:0] 1'1
assign $0\main_sdram_bankmachine0_cmd_payload_ras[0:0] 1'1
assign $0\main_sdram_bankmachine0_cmd_payload_we[0:0] 1'1
assign $0\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'1
- attribute \src "ls180.v:3246.5-3248.8"
+ attribute \src "ls180.v:3242.5-3244.8"
switch \main_sdram_bankmachine0_cmd_ready
- attribute \src "ls180.v:3246.9-3246.42"
+ attribute \src "ls180.v:3242.9-3242.42"
case 1'1
assign $0\builder_bankmachine0_next_state[2:0] 3'101
case
attribute \src "ls180.v:0.0-0.0"
case 3'010
assign $0\main_sdram_bankmachine0_row_close[0:0] 1'1
- attribute \src "ls180.v:3256.4-3258.7"
- switch $and$ls180.v:3256$106_Y
- attribute \src "ls180.v:3256.8-3256.87"
+ attribute \src "ls180.v:3252.4-3254.7"
+ switch $and$ls180.v:3252$106_Y
+ attribute \src "ls180.v:3252.8-3252.87"
case 1'1
assign $0\builder_bankmachine0_next_state[2:0] 3'101
case
end
attribute \src "ls180.v:0.0-0.0"
case 3'011
- attribute \src "ls180.v:3262.4-3271.7"
+ attribute \src "ls180.v:3258.4-3267.7"
switch \main_sdram_bankmachine0_trccon_ready
- attribute \src "ls180.v:3262.8-3262.44"
+ attribute \src "ls180.v:3258.8-3258.44"
case 1'1
assign $0\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] 1'1
assign $0\main_sdram_bankmachine0_row_open[0:0] 1'1
assign $0\main_sdram_bankmachine0_cmd_valid[0:0] 1'1
assign $0\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'1
assign $0\main_sdram_bankmachine0_cmd_payload_ras[0:0] 1'1
- attribute \src "ls180.v:3267.5-3269.8"
+ attribute \src "ls180.v:3263.5-3265.8"
switch \main_sdram_bankmachine0_cmd_ready
- attribute \src "ls180.v:3267.9-3267.42"
+ attribute \src "ls180.v:3263.9-3263.42"
case 1'1
assign $0\builder_bankmachine0_next_state[2:0] 3'110
case
case 3'100
assign $0\main_sdram_bankmachine0_row_close[0:0] 1'1
assign $0\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'1
- attribute \src "ls180.v:3274.4-3276.7"
+ attribute \src "ls180.v:3270.4-3272.7"
switch \main_sdram_bankmachine0_twtpcon_ready
- attribute \src "ls180.v:3274.8-3274.45"
+ attribute \src "ls180.v:3270.8-3270.45"
case 1'1
assign $0\main_sdram_bankmachine0_refresh_gnt[0:0] 1'1
case
end
- attribute \src "ls180.v:3279.4-3281.7"
- switch $not$ls180.v:3279$107_Y
- attribute \src "ls180.v:3279.8-3279.46"
+ attribute \src "ls180.v:3275.4-3277.7"
+ switch $not$ls180.v:3275$107_Y
+ attribute \src "ls180.v:3275.8-3275.46"
case 1'1
assign $0\builder_bankmachine0_next_state[2:0] 3'000
case
assign $0\builder_bankmachine0_next_state[2:0] 3'000
attribute \src "ls180.v:0.0-0.0"
case
- attribute \src "ls180.v:3290.4-3316.7"
+ attribute \src "ls180.v:3286.4-3312.7"
switch \main_sdram_bankmachine0_refresh_req
- attribute \src "ls180.v:3290.8-3290.43"
+ attribute \src "ls180.v:3286.8-3286.43"
case 1'1
assign $0\builder_bankmachine0_next_state[2:0] 3'100
- attribute \src "ls180.v:3292.8-3292.12"
+ attribute \src "ls180.v:3288.8-3288.12"
case
- attribute \src "ls180.v:3293.5-3315.8"
+ attribute \src "ls180.v:3289.5-3311.8"
switch \main_sdram_bankmachine0_cmd_buffer_source_valid
- attribute \src "ls180.v:3293.9-3293.56"
+ attribute \src "ls180.v:3289.9-3289.56"
case 1'1
- attribute \src "ls180.v:3294.6-3314.9"
+ attribute \src "ls180.v:3290.6-3310.9"
switch \main_sdram_bankmachine0_row_opened
- attribute \src "ls180.v:3294.10-3294.44"
+ attribute \src "ls180.v:3290.10-3290.44"
case 1'1
- attribute \src "ls180.v:3295.7-3311.10"
+ attribute \src "ls180.v:3291.7-3307.10"
switch \main_sdram_bankmachine0_row_hit
- attribute \src "ls180.v:3295.11-3295.42"
+ attribute \src "ls180.v:3291.11-3291.42"
case 1'1
assign $0\main_sdram_bankmachine0_cmd_valid[0:0] 1'1
assign $0\main_sdram_bankmachine0_cmd_payload_cas[0:0] 1'1
- attribute \src "ls180.v:3297.8-3304.11"
+ attribute \src "ls180.v:3293.8-3300.11"
switch \main_sdram_bankmachine0_cmd_buffer_source_payload_we
- attribute \src "ls180.v:3297.12-3297.64"
+ attribute \src "ls180.v:3293.12-3293.64"
case 1'1
assign $0\main_sdram_bankmachine0_req_wdata_ready[0:0] \main_sdram_bankmachine0_cmd_ready
assign $0\main_sdram_bankmachine0_cmd_payload_is_write[0:0] 1'1
assign $0\main_sdram_bankmachine0_cmd_payload_we[0:0] 1'1
- attribute \src "ls180.v:3301.12-3301.16"
+ attribute \src "ls180.v:3297.12-3297.16"
case
assign $0\main_sdram_bankmachine0_req_rdata_valid[0:0] \main_sdram_bankmachine0_cmd_ready
assign $0\main_sdram_bankmachine0_cmd_payload_is_read[0:0] 1'1
end
- attribute \src "ls180.v:3306.8-3308.11"
- switch $and$ls180.v:3306$108_Y
- attribute \src "ls180.v:3306.12-3306.88"
+ attribute \src "ls180.v:3302.8-3304.11"
+ switch $and$ls180.v:3302$108_Y
+ attribute \src "ls180.v:3302.12-3302.88"
case 1'1
assign $0\builder_bankmachine0_next_state[2:0] 3'010
case
end
- attribute \src "ls180.v:3309.11-3309.15"
+ attribute \src "ls180.v:3305.11-3305.15"
case
assign $0\builder_bankmachine0_next_state[2:0] 3'001
end
- attribute \src "ls180.v:3312.10-3312.14"
+ attribute \src "ls180.v:3308.10-3308.14"
case
assign $0\builder_bankmachine0_next_state[2:0] 3'011
end
update \main_sdram_bankmachine0_row_col_n_addr_sel $0\main_sdram_bankmachine0_row_col_n_addr_sel[0:0]
update \builder_bankmachine0_next_state $0\builder_bankmachine0_next_state[2:0]
end
- attribute \src "ls180.v:323.5-323.25"
- process $proc$ls180.v:323$2854
+ attribute \src "ls180.v:325.5-325.38"
+ process $proc$ls180.v:325$2857
assign { } { }
- assign $1\main_sdram_re[0:0] 1'0
+ assign $0\main_sdram_command_issue_w[0:0] 1'0
sync always
+ update \main_sdram_command_issue_w $0\main_sdram_command_issue_w[0:0]
sync init
- update \main_sdram_re $1\main_sdram_re[0:0]
end
- attribute \src "ls180.v:324.11-324.44"
- process $proc$ls180.v:324$2855
+ attribute \src "ls180.v:326.12-326.46"
+ process $proc$ls180.v:326$2858
assign { } { }
- assign $1\main_sdram_command_storage[5:0] 6'000000
+ assign $1\main_sdram_address_storage[12:0] 13'0000000000000
sync always
sync init
- update \main_sdram_command_storage $1\main_sdram_command_storage[5:0]
+ update \main_sdram_address_storage $1\main_sdram_address_storage[12:0]
end
- attribute \src "ls180.v:325.5-325.33"
- process $proc$ls180.v:325$2856
+ attribute \src "ls180.v:327.5-327.33"
+ process $proc$ls180.v:327$2859
assign { } { }
- assign $1\main_sdram_command_re[0:0] 1'0
+ assign $1\main_sdram_address_re[0:0] 1'0
sync always
sync init
- update \main_sdram_command_re $1\main_sdram_command_re[0:0]
+ update \main_sdram_address_re $1\main_sdram_address_re[0:0]
end
- attribute \src "ls180.v:329.5-329.38"
- process $proc$ls180.v:329$2857
+ attribute \src "ls180.v:328.11-328.45"
+ process $proc$ls180.v:328$2860
assign { } { }
- assign $0\main_sdram_command_issue_w[0:0] 1'0
+ assign $1\main_sdram_baddress_storage[1:0] 2'00
sync always
- update \main_sdram_command_issue_w $0\main_sdram_command_issue_w[0:0]
sync init
+ update \main_sdram_baddress_storage $1\main_sdram_baddress_storage[1:0]
end
- attribute \src "ls180.v:330.12-330.46"
- process $proc$ls180.v:330$2858
+ attribute \src "ls180.v:329.5-329.34"
+ process $proc$ls180.v:329$2861
assign { } { }
- assign $1\main_sdram_address_storage[12:0] 13'0000000000000
+ assign $1\main_sdram_baddress_re[0:0] 1'0
sync always
sync init
- update \main_sdram_address_storage $1\main_sdram_address_storage[12:0]
+ update \main_sdram_baddress_re $1\main_sdram_baddress_re[0:0]
end
- attribute \src "ls180.v:331.5-331.33"
- process $proc$ls180.v:331$2859
+ attribute \src "ls180.v:330.12-330.45"
+ process $proc$ls180.v:330$2862
assign { } { }
- assign $1\main_sdram_address_re[0:0] 1'0
+ assign $1\main_sdram_wrdata_storage[15:0] 16'0000000000000000
sync always
sync init
- update \main_sdram_address_re $1\main_sdram_address_re[0:0]
+ update \main_sdram_wrdata_storage $1\main_sdram_wrdata_storage[15:0]
end
- attribute \src "ls180.v:332.11-332.45"
- process $proc$ls180.v:332$2860
+ attribute \src "ls180.v:331.5-331.32"
+ process $proc$ls180.v:331$2863
assign { } { }
- assign $1\main_sdram_baddress_storage[1:0] 2'00
+ assign $1\main_sdram_wrdata_re[0:0] 1'0
sync always
sync init
- update \main_sdram_baddress_storage $1\main_sdram_baddress_storage[1:0]
+ update \main_sdram_wrdata_re $1\main_sdram_wrdata_re[0:0]
end
- attribute \src "ls180.v:333.5-333.34"
- process $proc$ls180.v:333$2861
+ attribute \src "ls180.v:332.12-332.37"
+ process $proc$ls180.v:332$2864
assign { } { }
- assign $1\main_sdram_baddress_re[0:0] 1'0
+ assign $1\main_sdram_status[15:0] 16'0000000000000000
sync always
sync init
- update \main_sdram_baddress_re $1\main_sdram_baddress_re[0:0]
+ update \main_sdram_status $1\main_sdram_status[15:0]
end
- attribute \src "ls180.v:3334.1-3341.4"
- process $proc$ls180.v:3334$112
+ attribute \src "ls180.v:3330.1-3337.4"
+ process $proc$ls180.v:3330$112
assign { } { }
assign $0\main_sdram_bankmachine1_cmd_payload_a[12:0] 13'0000000000000
- attribute \src "ls180.v:3336.2-3340.5"
+ attribute \src "ls180.v:3332.2-3336.5"
switch \main_sdram_bankmachine1_row_col_n_addr_sel
- attribute \src "ls180.v:3336.6-3336.48"
+ attribute \src "ls180.v:3332.6-3332.48"
case 1'1
assign $0\main_sdram_bankmachine1_cmd_payload_a[12:0] \main_sdram_bankmachine1_cmd_buffer_source_payload_addr [21:9]
- attribute \src "ls180.v:3338.6-3338.10"
+ attribute \src "ls180.v:3334.6-3334.10"
case
- assign $0\main_sdram_bankmachine1_cmd_payload_a[12:0] $or$ls180.v:3339$114_Y
+ assign $0\main_sdram_bankmachine1_cmd_payload_a[12:0] $or$ls180.v:3335$114_Y
end
sync always
update \main_sdram_bankmachine1_cmd_payload_a $0\main_sdram_bankmachine1_cmd_payload_a[12:0]
end
- attribute \src "ls180.v:334.12-334.45"
- process $proc$ls180.v:334$2862
- assign { } { }
- assign $1\main_sdram_wrdata_storage[15:0] 16'0000000000000000
- sync always
- sync init
- update \main_sdram_wrdata_storage $1\main_sdram_wrdata_storage[15:0]
- end
- attribute \src "ls180.v:3345.1-3352.4"
- process $proc$ls180.v:3345$121
+ attribute \src "ls180.v:3341.1-3348.4"
+ process $proc$ls180.v:3341$121
assign { } { }
assign $0\main_sdram_bankmachine1_auto_precharge[0:0] 1'0
- attribute \src "ls180.v:3347.2-3351.5"
- switch $and$ls180.v:3347$122_Y
- attribute \src "ls180.v:3347.6-3347.115"
+ attribute \src "ls180.v:3343.2-3347.5"
+ switch $and$ls180.v:3343$122_Y
+ attribute \src "ls180.v:3343.6-3343.115"
case 1'1
- attribute \src "ls180.v:3348.3-3350.6"
- switch $ne$ls180.v:3348$123_Y
- attribute \src "ls180.v:3348.7-3348.143"
+ attribute \src "ls180.v:3344.3-3346.6"
+ switch $ne$ls180.v:3344$123_Y
+ attribute \src "ls180.v:3344.7-3344.143"
case 1'1
- assign $0\main_sdram_bankmachine1_auto_precharge[0:0] $eq$ls180.v:3349$124_Y
+ assign $0\main_sdram_bankmachine1_auto_precharge[0:0] $eq$ls180.v:3345$124_Y
case
end
case
sync always
update \main_sdram_bankmachine1_auto_precharge $0\main_sdram_bankmachine1_auto_precharge[0:0]
end
- attribute \src "ls180.v:335.5-335.32"
- process $proc$ls180.v:335$2863
- assign { } { }
- assign $1\main_sdram_wrdata_re[0:0] 1'0
- sync always
- sync init
- update \main_sdram_wrdata_re $1\main_sdram_wrdata_re[0:0]
- end
- attribute \src "ls180.v:336.12-336.37"
- process $proc$ls180.v:336$2864
- assign { } { }
- assign $1\main_sdram_status[15:0] 16'0000000000000000
- sync always
- sync init
- update \main_sdram_status $1\main_sdram_status[15:0]
- end
- attribute \src "ls180.v:3367.1-3374.4"
- process $proc$ls180.v:3367$125
+ attribute \src "ls180.v:3363.1-3370.4"
+ process $proc$ls180.v:3363$125
assign { } { }
assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] 3'000
- attribute \src "ls180.v:3369.2-3373.5"
+ attribute \src "ls180.v:3365.2-3369.5"
switch \main_sdram_bankmachine1_cmd_buffer_lookahead_replace
- attribute \src "ls180.v:3369.6-3369.58"
+ attribute \src "ls180.v:3365.6-3365.58"
case 1'1
- assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:3370$126_Y
- attribute \src "ls180.v:3371.6-3371.10"
+ assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:3366$126_Y
+ attribute \src "ls180.v:3367.6-3367.10"
case
assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] \main_sdram_bankmachine1_cmd_buffer_lookahead_produce
end
sync always
update \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr $0\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0]
end
- attribute \src "ls180.v:3383.1-3476.4"
- process $proc$ls180.v:3383$134
+ attribute \src "ls180.v:3379.1-3472.4"
+ process $proc$ls180.v:3379$134
assign { } { }
assign { } { }
assign { } { }
assign $0\main_sdram_bankmachine1_req_wdata_ready[0:0] 1'0
assign $0\main_sdram_bankmachine1_req_rdata_valid[0:0] 1'0
assign $0\main_sdram_bankmachine1_refresh_gnt[0:0] 1'0
- assign { } { }
assign $0\main_sdram_bankmachine1_cmd_valid[0:0] 1'0
+ assign { } { }
assign $0\main_sdram_bankmachine1_row_open[0:0] 1'0
assign $0\main_sdram_bankmachine1_row_close[0:0] 1'0
assign $0\main_sdram_bankmachine1_cmd_payload_cas[0:0] 1'0
assign $0\main_sdram_bankmachine1_cmd_payload_ras[0:0] 1'0
assign $0\builder_bankmachine1_next_state[2:0] \builder_bankmachine1_state
- attribute \src "ls180.v:3399.2-3475.9"
+ attribute \src "ls180.v:3395.2-3471.9"
switch \builder_bankmachine1_state
attribute \src "ls180.v:0.0-0.0"
case 3'001
assign $0\main_sdram_bankmachine1_row_close[0:0] 1'1
- attribute \src "ls180.v:3401.4-3409.7"
- switch $and$ls180.v:3401$135_Y
- attribute \src "ls180.v:3401.8-3401.87"
+ attribute \src "ls180.v:3397.4-3405.7"
+ switch $and$ls180.v:3397$135_Y
+ attribute \src "ls180.v:3397.8-3397.87"
case 1'1
assign $0\main_sdram_bankmachine1_cmd_valid[0:0] 1'1
assign $0\main_sdram_bankmachine1_cmd_payload_ras[0:0] 1'1
assign $0\main_sdram_bankmachine1_cmd_payload_we[0:0] 1'1
assign $0\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] 1'1
- attribute \src "ls180.v:3403.5-3405.8"
+ attribute \src "ls180.v:3399.5-3401.8"
switch \main_sdram_bankmachine1_cmd_ready
- attribute \src "ls180.v:3403.9-3403.42"
+ attribute \src "ls180.v:3399.9-3399.42"
case 1'1
assign $0\builder_bankmachine1_next_state[2:0] 3'101
case
attribute \src "ls180.v:0.0-0.0"
case 3'010
assign $0\main_sdram_bankmachine1_row_close[0:0] 1'1
- attribute \src "ls180.v:3413.4-3415.7"
- switch $and$ls180.v:3413$136_Y
- attribute \src "ls180.v:3413.8-3413.87"
+ attribute \src "ls180.v:3409.4-3411.7"
+ switch $and$ls180.v:3409$136_Y
+ attribute \src "ls180.v:3409.8-3409.87"
case 1'1
assign $0\builder_bankmachine1_next_state[2:0] 3'101
case
end
attribute \src "ls180.v:0.0-0.0"
case 3'011
- attribute \src "ls180.v:3419.4-3428.7"
+ attribute \src "ls180.v:3415.4-3424.7"
switch \main_sdram_bankmachine1_trccon_ready
- attribute \src "ls180.v:3419.8-3419.44"
+ attribute \src "ls180.v:3415.8-3415.44"
case 1'1
assign $0\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] 1'1
assign $0\main_sdram_bankmachine1_row_open[0:0] 1'1
assign $0\main_sdram_bankmachine1_cmd_valid[0:0] 1'1
assign $0\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] 1'1
assign $0\main_sdram_bankmachine1_cmd_payload_ras[0:0] 1'1
- attribute \src "ls180.v:3424.5-3426.8"
+ attribute \src "ls180.v:3420.5-3422.8"
switch \main_sdram_bankmachine1_cmd_ready
- attribute \src "ls180.v:3424.9-3424.42"
+ attribute \src "ls180.v:3420.9-3420.42"
case 1'1
assign $0\builder_bankmachine1_next_state[2:0] 3'110
case
case 3'100
assign $0\main_sdram_bankmachine1_row_close[0:0] 1'1
assign $0\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] 1'1
- attribute \src "ls180.v:3431.4-3433.7"
+ attribute \src "ls180.v:3427.4-3429.7"
switch \main_sdram_bankmachine1_twtpcon_ready
- attribute \src "ls180.v:3431.8-3431.45"
+ attribute \src "ls180.v:3427.8-3427.45"
case 1'1
assign $0\main_sdram_bankmachine1_refresh_gnt[0:0] 1'1
case
end
- attribute \src "ls180.v:3436.4-3438.7"
- switch $not$ls180.v:3436$137_Y
- attribute \src "ls180.v:3436.8-3436.46"
+ attribute \src "ls180.v:3432.4-3434.7"
+ switch $not$ls180.v:3432$137_Y
+ attribute \src "ls180.v:3432.8-3432.46"
case 1'1
assign $0\builder_bankmachine1_next_state[2:0] 3'000
case
assign $0\builder_bankmachine1_next_state[2:0] 3'000
attribute \src "ls180.v:0.0-0.0"
case
- attribute \src "ls180.v:3447.4-3473.7"
+ attribute \src "ls180.v:3443.4-3469.7"
switch \main_sdram_bankmachine1_refresh_req
- attribute \src "ls180.v:3447.8-3447.43"
+ attribute \src "ls180.v:3443.8-3443.43"
case 1'1
assign $0\builder_bankmachine1_next_state[2:0] 3'100
- attribute \src "ls180.v:3449.8-3449.12"
+ attribute \src "ls180.v:3445.8-3445.12"
case
- attribute \src "ls180.v:3450.5-3472.8"
+ attribute \src "ls180.v:3446.5-3468.8"
switch \main_sdram_bankmachine1_cmd_buffer_source_valid
- attribute \src "ls180.v:3450.9-3450.56"
+ attribute \src "ls180.v:3446.9-3446.56"
case 1'1
- attribute \src "ls180.v:3451.6-3471.9"
+ attribute \src "ls180.v:3447.6-3467.9"
switch \main_sdram_bankmachine1_row_opened
- attribute \src "ls180.v:3451.10-3451.44"
+ attribute \src "ls180.v:3447.10-3447.44"
case 1'1
- attribute \src "ls180.v:3452.7-3468.10"
+ attribute \src "ls180.v:3448.7-3464.10"
switch \main_sdram_bankmachine1_row_hit
- attribute \src "ls180.v:3452.11-3452.42"
+ attribute \src "ls180.v:3448.11-3448.42"
case 1'1
assign $0\main_sdram_bankmachine1_cmd_valid[0:0] 1'1
assign $0\main_sdram_bankmachine1_cmd_payload_cas[0:0] 1'1
- attribute \src "ls180.v:3454.8-3461.11"
+ attribute \src "ls180.v:3450.8-3457.11"
switch \main_sdram_bankmachine1_cmd_buffer_source_payload_we
- attribute \src "ls180.v:3454.12-3454.64"
+ attribute \src "ls180.v:3450.12-3450.64"
case 1'1
assign $0\main_sdram_bankmachine1_req_wdata_ready[0:0] \main_sdram_bankmachine1_cmd_ready
assign $0\main_sdram_bankmachine1_cmd_payload_is_write[0:0] 1'1
assign $0\main_sdram_bankmachine1_cmd_payload_we[0:0] 1'1
- attribute \src "ls180.v:3458.12-3458.16"
+ attribute \src "ls180.v:3454.12-3454.16"
case
assign $0\main_sdram_bankmachine1_req_rdata_valid[0:0] \main_sdram_bankmachine1_cmd_ready
assign $0\main_sdram_bankmachine1_cmd_payload_is_read[0:0] 1'1
end
- attribute \src "ls180.v:3463.8-3465.11"
- switch $and$ls180.v:3463$138_Y
- attribute \src "ls180.v:3463.12-3463.88"
+ attribute \src "ls180.v:3459.8-3461.11"
+ switch $and$ls180.v:3459$138_Y
+ attribute \src "ls180.v:3459.12-3459.88"
case 1'1
assign $0\builder_bankmachine1_next_state[2:0] 3'010
case
end
- attribute \src "ls180.v:3466.11-3466.15"
+ attribute \src "ls180.v:3462.11-3462.15"
case
assign $0\builder_bankmachine1_next_state[2:0] 3'001
end
- attribute \src "ls180.v:3469.10-3469.14"
+ attribute \src "ls180.v:3465.10-3465.14"
case
assign $0\builder_bankmachine1_next_state[2:0] 3'011
end
update \main_sdram_bankmachine1_row_col_n_addr_sel $0\main_sdram_bankmachine1_row_col_n_addr_sel[0:0]
update \builder_bankmachine1_next_state $0\builder_bankmachine1_next_state[2:0]
end
- attribute \src "ls180.v:3491.1-3498.4"
- process $proc$ls180.v:3491$142
+ attribute \src "ls180.v:3487.1-3494.4"
+ process $proc$ls180.v:3487$142
assign { } { }
assign $0\main_sdram_bankmachine2_cmd_payload_a[12:0] 13'0000000000000
- attribute \src "ls180.v:3493.2-3497.5"
+ attribute \src "ls180.v:3489.2-3493.5"
switch \main_sdram_bankmachine2_row_col_n_addr_sel
- attribute \src "ls180.v:3493.6-3493.48"
+ attribute \src "ls180.v:3489.6-3489.48"
case 1'1
assign $0\main_sdram_bankmachine2_cmd_payload_a[12:0] \main_sdram_bankmachine2_cmd_buffer_source_payload_addr [21:9]
- attribute \src "ls180.v:3495.6-3495.10"
+ attribute \src "ls180.v:3491.6-3491.10"
case
- assign $0\main_sdram_bankmachine2_cmd_payload_a[12:0] $or$ls180.v:3496$144_Y
+ assign $0\main_sdram_bankmachine2_cmd_payload_a[12:0] $or$ls180.v:3492$144_Y
end
sync always
update \main_sdram_bankmachine2_cmd_payload_a $0\main_sdram_bankmachine2_cmd_payload_a[12:0]
end
- attribute \src "ls180.v:3502.1-3509.4"
- process $proc$ls180.v:3502$151
+ attribute \src "ls180.v:3498.1-3505.4"
+ process $proc$ls180.v:3498$151
assign { } { }
assign $0\main_sdram_bankmachine2_auto_precharge[0:0] 1'0
- attribute \src "ls180.v:3504.2-3508.5"
- switch $and$ls180.v:3504$152_Y
- attribute \src "ls180.v:3504.6-3504.115"
+ attribute \src "ls180.v:3500.2-3504.5"
+ switch $and$ls180.v:3500$152_Y
+ attribute \src "ls180.v:3500.6-3500.115"
case 1'1
- attribute \src "ls180.v:3505.3-3507.6"
- switch $ne$ls180.v:3505$153_Y
- attribute \src "ls180.v:3505.7-3505.143"
+ attribute \src "ls180.v:3501.3-3503.6"
+ switch $ne$ls180.v:3501$153_Y
+ attribute \src "ls180.v:3501.7-3501.143"
case 1'1
- assign $0\main_sdram_bankmachine2_auto_precharge[0:0] $eq$ls180.v:3506$154_Y
+ assign $0\main_sdram_bankmachine2_auto_precharge[0:0] $eq$ls180.v:3502$154_Y
case
end
case
sync always
update \main_sdram_bankmachine2_auto_precharge $0\main_sdram_bankmachine2_auto_precharge[0:0]
end
- attribute \src "ls180.v:3524.1-3531.4"
- process $proc$ls180.v:3524$155
+ attribute \src "ls180.v:3520.1-3527.4"
+ process $proc$ls180.v:3520$155
assign { } { }
assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] 3'000
- attribute \src "ls180.v:3526.2-3530.5"
+ attribute \src "ls180.v:3522.2-3526.5"
switch \main_sdram_bankmachine2_cmd_buffer_lookahead_replace
- attribute \src "ls180.v:3526.6-3526.58"
+ attribute \src "ls180.v:3522.6-3522.58"
case 1'1
- assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:3527$156_Y
- attribute \src "ls180.v:3528.6-3528.10"
+ assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:3523$156_Y
+ attribute \src "ls180.v:3524.6-3524.10"
case
assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] \main_sdram_bankmachine2_cmd_buffer_lookahead_produce
end
sync always
update \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr $0\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0]
end
- attribute \src "ls180.v:3540.1-3633.4"
- process $proc$ls180.v:3540$164
+ attribute \src "ls180.v:3536.1-3629.4"
+ process $proc$ls180.v:3536$164
assign { } { }
assign { } { }
assign { } { }
assign $0\main_sdram_bankmachine2_cmd_payload_we[0:0] 1'0
assign $0\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] 1'0
assign $0\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'0
- assign { } { }
assign $0\main_sdram_bankmachine2_cmd_payload_is_read[0:0] 1'0
assign $0\main_sdram_bankmachine2_cmd_payload_is_write[0:0] 1'0
+ assign { } { }
assign $0\main_sdram_bankmachine2_req_wdata_ready[0:0] 1'0
assign $0\main_sdram_bankmachine2_req_rdata_valid[0:0] 1'0
assign $0\main_sdram_bankmachine2_refresh_gnt[0:0] 1'0
assign $0\main_sdram_bankmachine2_cmd_valid[0:0] 1'0
assign $0\builder_bankmachine2_next_state[2:0] \builder_bankmachine2_state
- attribute \src "ls180.v:3556.2-3632.9"
+ attribute \src "ls180.v:3552.2-3628.9"
switch \builder_bankmachine2_state
attribute \src "ls180.v:0.0-0.0"
case 3'001
assign $0\main_sdram_bankmachine2_row_close[0:0] 1'1
- attribute \src "ls180.v:3558.4-3566.7"
- switch $and$ls180.v:3558$165_Y
- attribute \src "ls180.v:3558.8-3558.87"
+ attribute \src "ls180.v:3554.4-3562.7"
+ switch $and$ls180.v:3554$165_Y
+ attribute \src "ls180.v:3554.8-3554.87"
case 1'1
assign $0\main_sdram_bankmachine2_cmd_valid[0:0] 1'1
assign $0\main_sdram_bankmachine2_cmd_payload_ras[0:0] 1'1
assign $0\main_sdram_bankmachine2_cmd_payload_we[0:0] 1'1
assign $0\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'1
- attribute \src "ls180.v:3560.5-3562.8"
+ attribute \src "ls180.v:3556.5-3558.8"
switch \main_sdram_bankmachine2_cmd_ready
- attribute \src "ls180.v:3560.9-3560.42"
+ attribute \src "ls180.v:3556.9-3556.42"
case 1'1
assign $0\builder_bankmachine2_next_state[2:0] 3'101
case
attribute \src "ls180.v:0.0-0.0"
case 3'010
assign $0\main_sdram_bankmachine2_row_close[0:0] 1'1
- attribute \src "ls180.v:3570.4-3572.7"
- switch $and$ls180.v:3570$166_Y
- attribute \src "ls180.v:3570.8-3570.87"
+ attribute \src "ls180.v:3566.4-3568.7"
+ switch $and$ls180.v:3566$166_Y
+ attribute \src "ls180.v:3566.8-3566.87"
case 1'1
assign $0\builder_bankmachine2_next_state[2:0] 3'101
case
end
attribute \src "ls180.v:0.0-0.0"
case 3'011
- attribute \src "ls180.v:3576.4-3585.7"
+ attribute \src "ls180.v:3572.4-3581.7"
switch \main_sdram_bankmachine2_trccon_ready
- attribute \src "ls180.v:3576.8-3576.44"
+ attribute \src "ls180.v:3572.8-3572.44"
case 1'1
assign $0\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] 1'1
assign $0\main_sdram_bankmachine2_row_open[0:0] 1'1
assign $0\main_sdram_bankmachine2_cmd_valid[0:0] 1'1
assign $0\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'1
assign $0\main_sdram_bankmachine2_cmd_payload_ras[0:0] 1'1
- attribute \src "ls180.v:3581.5-3583.8"
+ attribute \src "ls180.v:3577.5-3579.8"
switch \main_sdram_bankmachine2_cmd_ready
- attribute \src "ls180.v:3581.9-3581.42"
+ attribute \src "ls180.v:3577.9-3577.42"
case 1'1
assign $0\builder_bankmachine2_next_state[2:0] 3'110
case
case 3'100
assign $0\main_sdram_bankmachine2_row_close[0:0] 1'1
assign $0\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'1
- attribute \src "ls180.v:3588.4-3590.7"
+ attribute \src "ls180.v:3584.4-3586.7"
switch \main_sdram_bankmachine2_twtpcon_ready
- attribute \src "ls180.v:3588.8-3588.45"
+ attribute \src "ls180.v:3584.8-3584.45"
case 1'1
assign $0\main_sdram_bankmachine2_refresh_gnt[0:0] 1'1
case
end
- attribute \src "ls180.v:3593.4-3595.7"
- switch $not$ls180.v:3593$167_Y
- attribute \src "ls180.v:3593.8-3593.46"
+ attribute \src "ls180.v:3589.4-3591.7"
+ switch $not$ls180.v:3589$167_Y
+ attribute \src "ls180.v:3589.8-3589.46"
case 1'1
assign $0\builder_bankmachine2_next_state[2:0] 3'000
case
assign $0\builder_bankmachine2_next_state[2:0] 3'000
attribute \src "ls180.v:0.0-0.0"
case
- attribute \src "ls180.v:3604.4-3630.7"
+ attribute \src "ls180.v:3600.4-3626.7"
switch \main_sdram_bankmachine2_refresh_req
- attribute \src "ls180.v:3604.8-3604.43"
+ attribute \src "ls180.v:3600.8-3600.43"
case 1'1
assign $0\builder_bankmachine2_next_state[2:0] 3'100
- attribute \src "ls180.v:3606.8-3606.12"
+ attribute \src "ls180.v:3602.8-3602.12"
case
- attribute \src "ls180.v:3607.5-3629.8"
+ attribute \src "ls180.v:3603.5-3625.8"
switch \main_sdram_bankmachine2_cmd_buffer_source_valid
- attribute \src "ls180.v:3607.9-3607.56"
+ attribute \src "ls180.v:3603.9-3603.56"
case 1'1
- attribute \src "ls180.v:3608.6-3628.9"
+ attribute \src "ls180.v:3604.6-3624.9"
switch \main_sdram_bankmachine2_row_opened
- attribute \src "ls180.v:3608.10-3608.44"
+ attribute \src "ls180.v:3604.10-3604.44"
case 1'1
- attribute \src "ls180.v:3609.7-3625.10"
+ attribute \src "ls180.v:3605.7-3621.10"
switch \main_sdram_bankmachine2_row_hit
- attribute \src "ls180.v:3609.11-3609.42"
+ attribute \src "ls180.v:3605.11-3605.42"
case 1'1
assign $0\main_sdram_bankmachine2_cmd_valid[0:0] 1'1
assign $0\main_sdram_bankmachine2_cmd_payload_cas[0:0] 1'1
- attribute \src "ls180.v:3611.8-3618.11"
+ attribute \src "ls180.v:3607.8-3614.11"
switch \main_sdram_bankmachine2_cmd_buffer_source_payload_we
- attribute \src "ls180.v:3611.12-3611.64"
+ attribute \src "ls180.v:3607.12-3607.64"
case 1'1
assign $0\main_sdram_bankmachine2_req_wdata_ready[0:0] \main_sdram_bankmachine2_cmd_ready
assign $0\main_sdram_bankmachine2_cmd_payload_is_write[0:0] 1'1
assign $0\main_sdram_bankmachine2_cmd_payload_we[0:0] 1'1
- attribute \src "ls180.v:3615.12-3615.16"
+ attribute \src "ls180.v:3611.12-3611.16"
case
assign $0\main_sdram_bankmachine2_req_rdata_valid[0:0] \main_sdram_bankmachine2_cmd_ready
assign $0\main_sdram_bankmachine2_cmd_payload_is_read[0:0] 1'1
end
- attribute \src "ls180.v:3620.8-3622.11"
- switch $and$ls180.v:3620$168_Y
- attribute \src "ls180.v:3620.12-3620.88"
+ attribute \src "ls180.v:3616.8-3618.11"
+ switch $and$ls180.v:3616$168_Y
+ attribute \src "ls180.v:3616.12-3616.88"
case 1'1
assign $0\builder_bankmachine2_next_state[2:0] 3'010
case
end
- attribute \src "ls180.v:3623.11-3623.15"
+ attribute \src "ls180.v:3619.11-3619.15"
case
assign $0\builder_bankmachine2_next_state[2:0] 3'001
end
- attribute \src "ls180.v:3626.10-3626.14"
+ attribute \src "ls180.v:3622.10-3622.14"
case
assign $0\builder_bankmachine2_next_state[2:0] 3'011
end
update \main_sdram_bankmachine2_row_col_n_addr_sel $0\main_sdram_bankmachine2_row_col_n_addr_sel[0:0]
update \builder_bankmachine2_next_state $0\builder_bankmachine2_next_state[2:0]
end
- attribute \src "ls180.v:3648.1-3655.4"
- process $proc$ls180.v:3648$172
+ attribute \src "ls180.v:362.12-362.46"
+ process $proc$ls180.v:362$2865
+ assign { } { }
+ assign $1\main_sdram_interface_wdata[15:0] 16'0000000000000000
+ sync always
+ sync init
+ update \main_sdram_interface_wdata $1\main_sdram_interface_wdata[15:0]
+ end
+ attribute \src "ls180.v:363.11-363.47"
+ process $proc$ls180.v:363$2866
+ assign { } { }
+ assign $1\main_sdram_interface_wdata_we[1:0] 2'00
+ sync always
+ sync init
+ update \main_sdram_interface_wdata_we $1\main_sdram_interface_wdata_we[1:0]
+ end
+ attribute \src "ls180.v:3644.1-3651.4"
+ process $proc$ls180.v:3644$172
assign { } { }
assign $0\main_sdram_bankmachine3_cmd_payload_a[12:0] 13'0000000000000
- attribute \src "ls180.v:3650.2-3654.5"
+ attribute \src "ls180.v:3646.2-3650.5"
switch \main_sdram_bankmachine3_row_col_n_addr_sel
- attribute \src "ls180.v:3650.6-3650.48"
+ attribute \src "ls180.v:3646.6-3646.48"
case 1'1
assign $0\main_sdram_bankmachine3_cmd_payload_a[12:0] \main_sdram_bankmachine3_cmd_buffer_source_payload_addr [21:9]
- attribute \src "ls180.v:3652.6-3652.10"
+ attribute \src "ls180.v:3648.6-3648.10"
case
- assign $0\main_sdram_bankmachine3_cmd_payload_a[12:0] $or$ls180.v:3653$174_Y
+ assign $0\main_sdram_bankmachine3_cmd_payload_a[12:0] $or$ls180.v:3649$174_Y
end
sync always
update \main_sdram_bankmachine3_cmd_payload_a $0\main_sdram_bankmachine3_cmd_payload_a[12:0]
end
- attribute \src "ls180.v:3659.1-3666.4"
- process $proc$ls180.v:3659$181
+ attribute \src "ls180.v:365.12-365.45"
+ process $proc$ls180.v:365$2867
+ assign { } { }
+ assign $1\main_sdram_dfi_p0_address[12:0] 13'0000000000000
+ sync always
+ sync init
+ update \main_sdram_dfi_p0_address $1\main_sdram_dfi_p0_address[12:0]
+ end
+ attribute \src "ls180.v:3655.1-3662.4"
+ process $proc$ls180.v:3655$181
assign { } { }
assign $0\main_sdram_bankmachine3_auto_precharge[0:0] 1'0
- attribute \src "ls180.v:3661.2-3665.5"
- switch $and$ls180.v:3661$182_Y
- attribute \src "ls180.v:3661.6-3661.115"
+ attribute \src "ls180.v:3657.2-3661.5"
+ switch $and$ls180.v:3657$182_Y
+ attribute \src "ls180.v:3657.6-3657.115"
case 1'1
- attribute \src "ls180.v:3662.3-3664.6"
- switch $ne$ls180.v:3662$183_Y
- attribute \src "ls180.v:3662.7-3662.143"
+ attribute \src "ls180.v:3658.3-3660.6"
+ switch $ne$ls180.v:3658$183_Y
+ attribute \src "ls180.v:3658.7-3658.143"
case 1'1
- assign $0\main_sdram_bankmachine3_auto_precharge[0:0] $eq$ls180.v:3663$184_Y
+ assign $0\main_sdram_bankmachine3_auto_precharge[0:0] $eq$ls180.v:3659$184_Y
case
end
case
sync always
update \main_sdram_bankmachine3_auto_precharge $0\main_sdram_bankmachine3_auto_precharge[0:0]
end
- attribute \src "ls180.v:366.12-366.46"
- process $proc$ls180.v:366$2865
+ attribute \src "ls180.v:366.11-366.40"
+ process $proc$ls180.v:366$2868
assign { } { }
- assign $1\main_sdram_interface_wdata[15:0] 16'0000000000000000
+ assign $1\main_sdram_dfi_p0_bank[1:0] 2'00
sync always
sync init
- update \main_sdram_interface_wdata $1\main_sdram_interface_wdata[15:0]
+ update \main_sdram_dfi_p0_bank $1\main_sdram_dfi_p0_bank[1:0]
end
- attribute \src "ls180.v:367.11-367.47"
- process $proc$ls180.v:367$2866
+ attribute \src "ls180.v:367.5-367.35"
+ process $proc$ls180.v:367$2869
assign { } { }
- assign $1\main_sdram_interface_wdata_we[1:0] 2'00
+ assign $1\main_sdram_dfi_p0_cas_n[0:0] 1'1
sync always
sync init
- update \main_sdram_interface_wdata_we $1\main_sdram_interface_wdata_we[1:0]
+ update \main_sdram_dfi_p0_cas_n $1\main_sdram_dfi_p0_cas_n[0:0]
end
- attribute \src "ls180.v:3681.1-3688.4"
- process $proc$ls180.v:3681$185
+ attribute \src "ls180.v:3677.1-3684.4"
+ process $proc$ls180.v:3677$185
assign { } { }
assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] 3'000
- attribute \src "ls180.v:3683.2-3687.5"
+ attribute \src "ls180.v:3679.2-3683.5"
switch \main_sdram_bankmachine3_cmd_buffer_lookahead_replace
- attribute \src "ls180.v:3683.6-3683.58"
+ attribute \src "ls180.v:3679.6-3679.58"
case 1'1
- assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:3684$186_Y
- attribute \src "ls180.v:3685.6-3685.10"
+ assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:3680$186_Y
+ attribute \src "ls180.v:3681.6-3681.10"
case
assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] \main_sdram_bankmachine3_cmd_buffer_lookahead_produce
end
sync always
update \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr $0\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0]
end
- attribute \src "ls180.v:369.12-369.45"
- process $proc$ls180.v:369$2867
+ attribute \src "ls180.v:368.5-368.34"
+ process $proc$ls180.v:368$2870
assign { } { }
- assign $1\main_sdram_dfi_p0_address[12:0] 13'0000000000000
+ assign $1\main_sdram_dfi_p0_cs_n[0:0] 1'1
sync always
sync init
- update \main_sdram_dfi_p0_address $1\main_sdram_dfi_p0_address[12:0]
+ update \main_sdram_dfi_p0_cs_n $1\main_sdram_dfi_p0_cs_n[0:0]
end
- attribute \src "ls180.v:3697.1-3790.4"
- process $proc$ls180.v:3697$194
+ attribute \src "ls180.v:369.5-369.35"
+ process $proc$ls180.v:369$2871
+ assign { } { }
+ assign $1\main_sdram_dfi_p0_ras_n[0:0] 1'1
+ sync always
+ sync init
+ update \main_sdram_dfi_p0_ras_n $1\main_sdram_dfi_p0_ras_n[0:0]
+ end
+ attribute \src "ls180.v:3693.1-3786.4"
+ process $proc$ls180.v:3693$194
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign $0\main_sdram_bankmachine3_cmd_valid[0:0] 1'0
assign $0\main_sdram_bankmachine3_row_open[0:0] 1'0
- assign { } { }
assign $0\main_sdram_bankmachine3_row_close[0:0] 1'0
+ assign { } { }
assign $0\main_sdram_bankmachine3_cmd_payload_cas[0:0] 1'0
assign $0\main_sdram_bankmachine3_cmd_payload_ras[0:0] 1'0
assign $0\main_sdram_bankmachine3_cmd_payload_we[0:0] 1'0
assign $0\main_sdram_bankmachine3_req_rdata_valid[0:0] 1'0
assign $0\main_sdram_bankmachine3_refresh_gnt[0:0] 1'0
assign $0\builder_bankmachine3_next_state[2:0] \builder_bankmachine3_state
- attribute \src "ls180.v:3713.2-3789.9"
+ attribute \src "ls180.v:3709.2-3785.9"
switch \builder_bankmachine3_state
attribute \src "ls180.v:0.0-0.0"
case 3'001
assign $0\main_sdram_bankmachine3_row_close[0:0] 1'1
- attribute \src "ls180.v:3715.4-3723.7"
- switch $and$ls180.v:3715$195_Y
- attribute \src "ls180.v:3715.8-3715.87"
+ attribute \src "ls180.v:3711.4-3719.7"
+ switch $and$ls180.v:3711$195_Y
+ attribute \src "ls180.v:3711.8-3711.87"
case 1'1
assign $0\main_sdram_bankmachine3_cmd_valid[0:0] 1'1
assign $0\main_sdram_bankmachine3_cmd_payload_ras[0:0] 1'1
assign $0\main_sdram_bankmachine3_cmd_payload_we[0:0] 1'1
assign $0\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] 1'1
- attribute \src "ls180.v:3717.5-3719.8"
+ attribute \src "ls180.v:3713.5-3715.8"
switch \main_sdram_bankmachine3_cmd_ready
- attribute \src "ls180.v:3717.9-3717.42"
+ attribute \src "ls180.v:3713.9-3713.42"
case 1'1
assign $0\builder_bankmachine3_next_state[2:0] 3'101
case
attribute \src "ls180.v:0.0-0.0"
case 3'010
assign $0\main_sdram_bankmachine3_row_close[0:0] 1'1
- attribute \src "ls180.v:3727.4-3729.7"
- switch $and$ls180.v:3727$196_Y
- attribute \src "ls180.v:3727.8-3727.87"
+ attribute \src "ls180.v:3723.4-3725.7"
+ switch $and$ls180.v:3723$196_Y
+ attribute \src "ls180.v:3723.8-3723.87"
case 1'1
assign $0\builder_bankmachine3_next_state[2:0] 3'101
case
end
attribute \src "ls180.v:0.0-0.0"
case 3'011
- attribute \src "ls180.v:3733.4-3742.7"
+ attribute \src "ls180.v:3729.4-3738.7"
switch \main_sdram_bankmachine3_trccon_ready
- attribute \src "ls180.v:3733.8-3733.44"
+ attribute \src "ls180.v:3729.8-3729.44"
case 1'1
assign $0\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] 1'1
assign $0\main_sdram_bankmachine3_row_open[0:0] 1'1
assign $0\main_sdram_bankmachine3_cmd_valid[0:0] 1'1
assign $0\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] 1'1
assign $0\main_sdram_bankmachine3_cmd_payload_ras[0:0] 1'1
- attribute \src "ls180.v:3738.5-3740.8"
+ attribute \src "ls180.v:3734.5-3736.8"
switch \main_sdram_bankmachine3_cmd_ready
- attribute \src "ls180.v:3738.9-3738.42"
+ attribute \src "ls180.v:3734.9-3734.42"
case 1'1
assign $0\builder_bankmachine3_next_state[2:0] 3'110
case
case 3'100
assign $0\main_sdram_bankmachine3_row_close[0:0] 1'1
assign $0\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] 1'1
- attribute \src "ls180.v:3745.4-3747.7"
+ attribute \src "ls180.v:3741.4-3743.7"
switch \main_sdram_bankmachine3_twtpcon_ready
- attribute \src "ls180.v:3745.8-3745.45"
+ attribute \src "ls180.v:3741.8-3741.45"
case 1'1
assign $0\main_sdram_bankmachine3_refresh_gnt[0:0] 1'1
case
end
- attribute \src "ls180.v:3750.4-3752.7"
- switch $not$ls180.v:3750$197_Y
- attribute \src "ls180.v:3750.8-3750.46"
+ attribute \src "ls180.v:3746.4-3748.7"
+ switch $not$ls180.v:3746$197_Y
+ attribute \src "ls180.v:3746.8-3746.46"
case 1'1
assign $0\builder_bankmachine3_next_state[2:0] 3'000
case
assign $0\builder_bankmachine3_next_state[2:0] 3'000
attribute \src "ls180.v:0.0-0.0"
case
- attribute \src "ls180.v:3761.4-3787.7"
+ attribute \src "ls180.v:3757.4-3783.7"
switch \main_sdram_bankmachine3_refresh_req
- attribute \src "ls180.v:3761.8-3761.43"
+ attribute \src "ls180.v:3757.8-3757.43"
case 1'1
assign $0\builder_bankmachine3_next_state[2:0] 3'100
- attribute \src "ls180.v:3763.8-3763.12"
+ attribute \src "ls180.v:3759.8-3759.12"
case
- attribute \src "ls180.v:3764.5-3786.8"
+ attribute \src "ls180.v:3760.5-3782.8"
switch \main_sdram_bankmachine3_cmd_buffer_source_valid
- attribute \src "ls180.v:3764.9-3764.56"
+ attribute \src "ls180.v:3760.9-3760.56"
case 1'1
- attribute \src "ls180.v:3765.6-3785.9"
+ attribute \src "ls180.v:3761.6-3781.9"
switch \main_sdram_bankmachine3_row_opened
- attribute \src "ls180.v:3765.10-3765.44"
+ attribute \src "ls180.v:3761.10-3761.44"
case 1'1
- attribute \src "ls180.v:3766.7-3782.10"
+ attribute \src "ls180.v:3762.7-3778.10"
switch \main_sdram_bankmachine3_row_hit
- attribute \src "ls180.v:3766.11-3766.42"
+ attribute \src "ls180.v:3762.11-3762.42"
case 1'1
assign $0\main_sdram_bankmachine3_cmd_valid[0:0] 1'1
assign $0\main_sdram_bankmachine3_cmd_payload_cas[0:0] 1'1
- attribute \src "ls180.v:3768.8-3775.11"
+ attribute \src "ls180.v:3764.8-3771.11"
switch \main_sdram_bankmachine3_cmd_buffer_source_payload_we
- attribute \src "ls180.v:3768.12-3768.64"
+ attribute \src "ls180.v:3764.12-3764.64"
case 1'1
assign $0\main_sdram_bankmachine3_req_wdata_ready[0:0] \main_sdram_bankmachine3_cmd_ready
assign $0\main_sdram_bankmachine3_cmd_payload_is_write[0:0] 1'1
assign $0\main_sdram_bankmachine3_cmd_payload_we[0:0] 1'1
- attribute \src "ls180.v:3772.12-3772.16"
+ attribute \src "ls180.v:3768.12-3768.16"
case
assign $0\main_sdram_bankmachine3_req_rdata_valid[0:0] \main_sdram_bankmachine3_cmd_ready
assign $0\main_sdram_bankmachine3_cmd_payload_is_read[0:0] 1'1
end
- attribute \src "ls180.v:3777.8-3779.11"
- switch $and$ls180.v:3777$198_Y
- attribute \src "ls180.v:3777.12-3777.88"
+ attribute \src "ls180.v:3773.8-3775.11"
+ switch $and$ls180.v:3773$198_Y
+ attribute \src "ls180.v:3773.12-3773.88"
case 1'1
assign $0\builder_bankmachine3_next_state[2:0] 3'010
case
end
- attribute \src "ls180.v:3780.11-3780.15"
+ attribute \src "ls180.v:3776.11-3776.15"
case
assign $0\builder_bankmachine3_next_state[2:0] 3'001
end
- attribute \src "ls180.v:3783.10-3783.14"
+ attribute \src "ls180.v:3779.10-3779.14"
case
assign $0\builder_bankmachine3_next_state[2:0] 3'011
end
update \main_sdram_bankmachine3_row_col_n_addr_sel $0\main_sdram_bankmachine3_row_col_n_addr_sel[0:0]
update \builder_bankmachine3_next_state $0\builder_bankmachine3_next_state[2:0]
end
- attribute \src "ls180.v:370.11-370.40"
- process $proc$ls180.v:370$2868
+ attribute \src "ls180.v:370.5-370.34"
+ process $proc$ls180.v:370$2872
assign { } { }
- assign $1\main_sdram_dfi_p0_bank[1:0] 2'00
+ assign $1\main_sdram_dfi_p0_we_n[0:0] 1'1
sync always
sync init
- update \main_sdram_dfi_p0_bank $1\main_sdram_dfi_p0_bank[1:0]
+ update \main_sdram_dfi_p0_we_n $1\main_sdram_dfi_p0_we_n[0:0]
end
- attribute \src "ls180.v:371.5-371.35"
- process $proc$ls180.v:371$2869
+ attribute \src "ls180.v:374.5-374.35"
+ process $proc$ls180.v:374$2873
assign { } { }
- assign $1\main_sdram_dfi_p0_cas_n[0:0] 1'1
+ assign $0\main_sdram_dfi_p0_act_n[0:0] 1'1
sync always
+ update \main_sdram_dfi_p0_act_n $0\main_sdram_dfi_p0_act_n[0:0]
sync init
- update \main_sdram_dfi_p0_cas_n $1\main_sdram_dfi_p0_cas_n[0:0]
end
- attribute \src "ls180.v:372.5-372.34"
- process $proc$ls180.v:372$2870
+ attribute \src "ls180.v:376.5-376.39"
+ process $proc$ls180.v:376$2874
assign { } { }
- assign $1\main_sdram_dfi_p0_cs_n[0:0] 1'1
+ assign $1\main_sdram_dfi_p0_wrdata_en[0:0] 1'0
sync always
sync init
- update \main_sdram_dfi_p0_cs_n $1\main_sdram_dfi_p0_cs_n[0:0]
+ update \main_sdram_dfi_p0_wrdata_en $1\main_sdram_dfi_p0_wrdata_en[0:0]
end
- attribute \src "ls180.v:373.5-373.35"
- process $proc$ls180.v:373$2871
+ attribute \src "ls180.v:378.5-378.39"
+ process $proc$ls180.v:378$2875
assign { } { }
- assign $1\main_sdram_dfi_p0_ras_n[0:0] 1'1
+ assign $1\main_sdram_dfi_p0_rddata_en[0:0] 1'0
sync always
sync init
- update \main_sdram_dfi_p0_ras_n $1\main_sdram_dfi_p0_ras_n[0:0]
+ update \main_sdram_dfi_p0_rddata_en $1\main_sdram_dfi_p0_rddata_en[0:0]
end
- attribute \src "ls180.v:374.5-374.34"
- process $proc$ls180.v:374$2872
+ attribute \src "ls180.v:3806.1-3812.4"
+ process $proc$ls180.v:3806$237
assign { } { }
- assign $1\main_sdram_dfi_p0_we_n[0:0] 1'1
- sync always
- sync init
- update \main_sdram_dfi_p0_we_n $1\main_sdram_dfi_p0_we_n[0:0]
- end
- attribute \src "ls180.v:378.5-378.35"
- process $proc$ls180.v:378$2873
assign { } { }
- assign $0\main_sdram_dfi_p0_act_n[0:0] 1'1
+ assign $0\main_sdram_choose_cmd_valids[3:0] [0] $and$ls180.v:3808$250_Y
+ assign $0\main_sdram_choose_cmd_valids[3:0] [1] $and$ls180.v:3809$263_Y
+ assign $0\main_sdram_choose_cmd_valids[3:0] [2] $and$ls180.v:3810$276_Y
+ assign $0\main_sdram_choose_cmd_valids[3:0] [3] $and$ls180.v:3811$289_Y
sync always
- update \main_sdram_dfi_p0_act_n $0\main_sdram_dfi_p0_act_n[0:0]
- sync init
+ update \main_sdram_choose_cmd_valids $0\main_sdram_choose_cmd_valids[3:0]
end
- attribute \src "ls180.v:380.5-380.39"
- process $proc$ls180.v:380$2874
+ attribute \src "ls180.v:381.5-381.32"
+ process $proc$ls180.v:381$2876
assign { } { }
- assign $1\main_sdram_dfi_p0_wrdata_en[0:0] 1'0
+ assign $1\main_sdram_cmd_valid[0:0] 1'0
sync always
sync init
- update \main_sdram_dfi_p0_wrdata_en $1\main_sdram_dfi_p0_wrdata_en[0:0]
- end
- attribute \src "ls180.v:3810.1-3816.4"
- process $proc$ls180.v:3810$237
- assign { } { }
- assign { } { }
- assign $0\main_sdram_choose_cmd_valids[3:0] [0] $and$ls180.v:3812$250_Y
- assign $0\main_sdram_choose_cmd_valids[3:0] [1] $and$ls180.v:3813$263_Y
- assign $0\main_sdram_choose_cmd_valids[3:0] [2] $and$ls180.v:3814$276_Y
- assign $0\main_sdram_choose_cmd_valids[3:0] [3] $and$ls180.v:3815$289_Y
- sync always
- update \main_sdram_choose_cmd_valids $0\main_sdram_choose_cmd_valids[3:0]
+ update \main_sdram_cmd_valid $1\main_sdram_cmd_valid[0:0]
end
- attribute \src "ls180.v:382.5-382.39"
- process $proc$ls180.v:382$2875
+ attribute \src "ls180.v:382.5-382.32"
+ process $proc$ls180.v:382$2877
assign { } { }
- assign $1\main_sdram_dfi_p0_rddata_en[0:0] 1'0
+ assign $1\main_sdram_cmd_ready[0:0] 1'0
sync always
sync init
- update \main_sdram_dfi_p0_rddata_en $1\main_sdram_dfi_p0_rddata_en[0:0]
+ update \main_sdram_cmd_ready $1\main_sdram_cmd_ready[0:0]
end
- attribute \src "ls180.v:3824.1-3829.4"
- process $proc$ls180.v:3824$290
+ attribute \src "ls180.v:3820.1-3825.4"
+ process $proc$ls180.v:3820$290
assign { } { }
assign $0\main_sdram_choose_cmd_cmd_payload_cas[0:0] 1'0
- attribute \src "ls180.v:3826.2-3828.5"
+ attribute \src "ls180.v:3822.2-3824.5"
switch \main_sdram_choose_cmd_cmd_valid
- attribute \src "ls180.v:3826.6-3826.37"
+ attribute \src "ls180.v:3822.6-3822.37"
case 1'1
assign $0\main_sdram_choose_cmd_cmd_payload_cas[0:0] \builder_comb_t_array_muxed0
case
sync always
update \main_sdram_choose_cmd_cmd_payload_cas $0\main_sdram_choose_cmd_cmd_payload_cas[0:0]
end
- attribute \src "ls180.v:3830.1-3835.4"
- process $proc$ls180.v:3830$291
+ attribute \src "ls180.v:3826.1-3831.4"
+ process $proc$ls180.v:3826$291
assign { } { }
assign $0\main_sdram_choose_cmd_cmd_payload_ras[0:0] 1'0
- attribute \src "ls180.v:3832.2-3834.5"
+ attribute \src "ls180.v:3828.2-3830.5"
switch \main_sdram_choose_cmd_cmd_valid
- attribute \src "ls180.v:3832.6-3832.37"
+ attribute \src "ls180.v:3828.6-3828.37"
case 1'1
assign $0\main_sdram_choose_cmd_cmd_payload_ras[0:0] \builder_comb_t_array_muxed1
case
sync always
update \main_sdram_choose_cmd_cmd_payload_ras $0\main_sdram_choose_cmd_cmd_payload_ras[0:0]
end
- attribute \src "ls180.v:3836.1-3841.4"
- process $proc$ls180.v:3836$292
+ attribute \src "ls180.v:383.5-383.31"
+ process $proc$ls180.v:383$2878
+ assign { } { }
+ assign $1\main_sdram_cmd_last[0:0] 1'0
+ sync always
+ sync init
+ update \main_sdram_cmd_last $1\main_sdram_cmd_last[0:0]
+ end
+ attribute \src "ls180.v:3832.1-3837.4"
+ process $proc$ls180.v:3832$292
assign { } { }
assign $0\main_sdram_choose_cmd_cmd_payload_we[0:0] 1'0
- attribute \src "ls180.v:3838.2-3840.5"
+ attribute \src "ls180.v:3834.2-3836.5"
switch \main_sdram_choose_cmd_cmd_valid
- attribute \src "ls180.v:3838.6-3838.37"
+ attribute \src "ls180.v:3834.6-3834.37"
case 1'1
assign $0\main_sdram_choose_cmd_cmd_payload_we[0:0] \builder_comb_t_array_muxed2
case
sync always
update \main_sdram_choose_cmd_cmd_payload_we $0\main_sdram_choose_cmd_cmd_payload_we[0:0]
end
- attribute \src "ls180.v:3843.1-3849.4"
- process $proc$ls180.v:3843$295
+ attribute \src "ls180.v:3839.1-3845.4"
+ process $proc$ls180.v:3839$295
assign { } { }
assign { } { }
- assign $0\main_sdram_choose_req_valids[3:0] [0] $and$ls180.v:3845$308_Y
- assign $0\main_sdram_choose_req_valids[3:0] [1] $and$ls180.v:3846$321_Y
- assign $0\main_sdram_choose_req_valids[3:0] [2] $and$ls180.v:3847$334_Y
- assign $0\main_sdram_choose_req_valids[3:0] [3] $and$ls180.v:3848$347_Y
+ assign $0\main_sdram_choose_req_valids[3:0] [0] $and$ls180.v:3841$308_Y
+ assign $0\main_sdram_choose_req_valids[3:0] [1] $and$ls180.v:3842$321_Y
+ assign $0\main_sdram_choose_req_valids[3:0] [2] $and$ls180.v:3843$334_Y
+ assign $0\main_sdram_choose_req_valids[3:0] [3] $and$ls180.v:3844$347_Y
sync always
update \main_sdram_choose_req_valids $0\main_sdram_choose_req_valids[3:0]
end
- attribute \src "ls180.v:385.5-385.32"
- process $proc$ls180.v:385$2876
+ attribute \src "ls180.v:384.12-384.44"
+ process $proc$ls180.v:384$2879
assign { } { }
- assign $1\main_sdram_cmd_valid[0:0] 1'0
+ assign $1\main_sdram_cmd_payload_a[12:0] 13'0000000000000
sync always
sync init
- update \main_sdram_cmd_valid $1\main_sdram_cmd_valid[0:0]
+ update \main_sdram_cmd_payload_a $1\main_sdram_cmd_payload_a[12:0]
end
- attribute \src "ls180.v:3857.1-3862.4"
- process $proc$ls180.v:3857$348
+ attribute \src "ls180.v:385.11-385.43"
+ process $proc$ls180.v:385$2880
+ assign { } { }
+ assign $1\main_sdram_cmd_payload_ba[1:0] 2'00
+ sync always
+ sync init
+ update \main_sdram_cmd_payload_ba $1\main_sdram_cmd_payload_ba[1:0]
+ end
+ attribute \src "ls180.v:3853.1-3858.4"
+ process $proc$ls180.v:3853$348
assign { } { }
assign $0\main_sdram_choose_req_cmd_payload_cas[0:0] 1'0
- attribute \src "ls180.v:3859.2-3861.5"
+ attribute \src "ls180.v:3855.2-3857.5"
switch \main_sdram_choose_req_cmd_valid
- attribute \src "ls180.v:3859.6-3859.37"
+ attribute \src "ls180.v:3855.6-3855.37"
case 1'1
assign $0\main_sdram_choose_req_cmd_payload_cas[0:0] \builder_comb_t_array_muxed3
case
sync always
update \main_sdram_choose_req_cmd_payload_cas $0\main_sdram_choose_req_cmd_payload_cas[0:0]
end
- attribute \src "ls180.v:386.5-386.32"
- process $proc$ls180.v:386$2877
- assign { } { }
- assign $1\main_sdram_cmd_ready[0:0] 1'0
- sync always
- sync init
- update \main_sdram_cmd_ready $1\main_sdram_cmd_ready[0:0]
- end
- attribute \src "ls180.v:3863.1-3868.4"
- process $proc$ls180.v:3863$349
+ attribute \src "ls180.v:3859.1-3864.4"
+ process $proc$ls180.v:3859$349
assign { } { }
assign $0\main_sdram_choose_req_cmd_payload_ras[0:0] 1'0
- attribute \src "ls180.v:3865.2-3867.5"
+ attribute \src "ls180.v:3861.2-3863.5"
switch \main_sdram_choose_req_cmd_valid
- attribute \src "ls180.v:3865.6-3865.37"
+ attribute \src "ls180.v:3861.6-3861.37"
case 1'1
assign $0\main_sdram_choose_req_cmd_payload_ras[0:0] \builder_comb_t_array_muxed4
case
sync always
update \main_sdram_choose_req_cmd_payload_ras $0\main_sdram_choose_req_cmd_payload_ras[0:0]
end
- attribute \src "ls180.v:3869.1-3874.4"
- process $proc$ls180.v:3869$350
+ attribute \src "ls180.v:386.5-386.38"
+ process $proc$ls180.v:386$2881
+ assign { } { }
+ assign $1\main_sdram_cmd_payload_cas[0:0] 1'0
+ sync always
+ sync init
+ update \main_sdram_cmd_payload_cas $1\main_sdram_cmd_payload_cas[0:0]
+ end
+ attribute \src "ls180.v:3865.1-3870.4"
+ process $proc$ls180.v:3865$350
assign { } { }
assign $0\main_sdram_choose_req_cmd_payload_we[0:0] 1'0
- attribute \src "ls180.v:3871.2-3873.5"
+ attribute \src "ls180.v:3867.2-3869.5"
switch \main_sdram_choose_req_cmd_valid
- attribute \src "ls180.v:3871.6-3871.37"
+ attribute \src "ls180.v:3867.6-3867.37"
case 1'1
assign $0\main_sdram_choose_req_cmd_payload_we[0:0] \builder_comb_t_array_muxed5
case
sync always
update \main_sdram_choose_req_cmd_payload_we $0\main_sdram_choose_req_cmd_payload_we[0:0]
end
- attribute \src "ls180.v:387.5-387.31"
- process $proc$ls180.v:387$2878
+ attribute \src "ls180.v:387.5-387.38"
+ process $proc$ls180.v:387$2882
assign { } { }
- assign $1\main_sdram_cmd_last[0:0] 1'0
+ assign $1\main_sdram_cmd_payload_ras[0:0] 1'0
sync always
sync init
- update \main_sdram_cmd_last $1\main_sdram_cmd_last[0:0]
+ update \main_sdram_cmd_payload_ras $1\main_sdram_cmd_payload_ras[0:0]
end
- attribute \src "ls180.v:3875.1-3883.4"
- process $proc$ls180.v:3875$351
+ attribute \src "ls180.v:3871.1-3879.4"
+ process $proc$ls180.v:3871$351
assign { } { }
assign $0\main_sdram_bankmachine0_cmd_ready[0:0] 1'0
- attribute \src "ls180.v:3877.2-3879.5"
- switch $and$ls180.v:3877$354_Y
- attribute \src "ls180.v:3877.6-3877.115"
+ attribute \src "ls180.v:3873.2-3875.5"
+ switch $and$ls180.v:3873$354_Y
+ attribute \src "ls180.v:3873.6-3873.115"
case 1'1
assign $0\main_sdram_bankmachine0_cmd_ready[0:0] 1'1
case
end
- attribute \src "ls180.v:3880.2-3882.5"
- switch $and$ls180.v:3880$357_Y
- attribute \src "ls180.v:3880.6-3880.115"
+ attribute \src "ls180.v:3876.2-3878.5"
+ switch $and$ls180.v:3876$357_Y
+ attribute \src "ls180.v:3876.6-3876.115"
case 1'1
assign $0\main_sdram_bankmachine0_cmd_ready[0:0] 1'1
case
sync always
update \main_sdram_bankmachine0_cmd_ready $0\main_sdram_bankmachine0_cmd_ready[0:0]
end
- attribute \src "ls180.v:388.12-388.44"
- process $proc$ls180.v:388$2879
+ attribute \src "ls180.v:388.5-388.37"
+ process $proc$ls180.v:388$2883
assign { } { }
- assign $1\main_sdram_cmd_payload_a[12:0] 13'0000000000000
+ assign $1\main_sdram_cmd_payload_we[0:0] 1'0
sync always
sync init
- update \main_sdram_cmd_payload_a $1\main_sdram_cmd_payload_a[12:0]
+ update \main_sdram_cmd_payload_we $1\main_sdram_cmd_payload_we[0:0]
end
- attribute \src "ls180.v:3884.1-3892.4"
- process $proc$ls180.v:3884$358
+ attribute \src "ls180.v:3880.1-3888.4"
+ process $proc$ls180.v:3880$358
assign { } { }
assign $0\main_sdram_bankmachine1_cmd_ready[0:0] 1'0
- attribute \src "ls180.v:3886.2-3888.5"
- switch $and$ls180.v:3886$361_Y
- attribute \src "ls180.v:3886.6-3886.115"
+ attribute \src "ls180.v:3882.2-3884.5"
+ switch $and$ls180.v:3882$361_Y
+ attribute \src "ls180.v:3882.6-3882.115"
case 1'1
assign $0\main_sdram_bankmachine1_cmd_ready[0:0] 1'1
case
end
- attribute \src "ls180.v:3889.2-3891.5"
- switch $and$ls180.v:3889$364_Y
- attribute \src "ls180.v:3889.6-3889.115"
+ attribute \src "ls180.v:3885.2-3887.5"
+ switch $and$ls180.v:3885$364_Y
+ attribute \src "ls180.v:3885.6-3885.115"
case 1'1
assign $0\main_sdram_bankmachine1_cmd_ready[0:0] 1'1
case
sync always
update \main_sdram_bankmachine1_cmd_ready $0\main_sdram_bankmachine1_cmd_ready[0:0]
end
- attribute \src "ls180.v:389.11-389.43"
- process $proc$ls180.v:389$2880
- assign { } { }
- assign $1\main_sdram_cmd_payload_ba[1:0] 2'00
- sync always
- sync init
- update \main_sdram_cmd_payload_ba $1\main_sdram_cmd_payload_ba[1:0]
- end
- attribute \src "ls180.v:3893.1-3901.4"
- process $proc$ls180.v:3893$365
+ attribute \src "ls180.v:3889.1-3897.4"
+ process $proc$ls180.v:3889$365
assign { } { }
assign $0\main_sdram_bankmachine2_cmd_ready[0:0] 1'0
- attribute \src "ls180.v:3895.2-3897.5"
- switch $and$ls180.v:3895$368_Y
- attribute \src "ls180.v:3895.6-3895.115"
+ attribute \src "ls180.v:3891.2-3893.5"
+ switch $and$ls180.v:3891$368_Y
+ attribute \src "ls180.v:3891.6-3891.115"
case 1'1
assign $0\main_sdram_bankmachine2_cmd_ready[0:0] 1'1
case
end
- attribute \src "ls180.v:3898.2-3900.5"
- switch $and$ls180.v:3898$371_Y
- attribute \src "ls180.v:3898.6-3898.115"
+ attribute \src "ls180.v:3894.2-3896.5"
+ switch $and$ls180.v:3894$371_Y
+ attribute \src "ls180.v:3894.6-3894.115"
case 1'1
assign $0\main_sdram_bankmachine2_cmd_ready[0:0] 1'1
case
sync always
update \main_sdram_bankmachine2_cmd_ready $0\main_sdram_bankmachine2_cmd_ready[0:0]
end
- attribute \src "ls180.v:390.5-390.38"
- process $proc$ls180.v:390$2881
+ attribute \src "ls180.v:389.5-389.42"
+ process $proc$ls180.v:389$2884
assign { } { }
- assign $1\main_sdram_cmd_payload_cas[0:0] 1'0
+ assign $0\main_sdram_cmd_payload_is_read[0:0] 1'0
sync always
+ update \main_sdram_cmd_payload_is_read $0\main_sdram_cmd_payload_is_read[0:0]
sync init
- update \main_sdram_cmd_payload_cas $1\main_sdram_cmd_payload_cas[0:0]
end
- attribute \src "ls180.v:3902.1-3910.4"
- process $proc$ls180.v:3902$372
+ attribute \src "ls180.v:3898.1-3906.4"
+ process $proc$ls180.v:3898$372
assign { } { }
assign $0\main_sdram_bankmachine3_cmd_ready[0:0] 1'0
- attribute \src "ls180.v:3904.2-3906.5"
- switch $and$ls180.v:3904$375_Y
- attribute \src "ls180.v:3904.6-3904.115"
+ attribute \src "ls180.v:3900.2-3902.5"
+ switch $and$ls180.v:3900$375_Y
+ attribute \src "ls180.v:3900.6-3900.115"
case 1'1
assign $0\main_sdram_bankmachine3_cmd_ready[0:0] 1'1
case
end
- attribute \src "ls180.v:3907.2-3909.5"
- switch $and$ls180.v:3907$378_Y
- attribute \src "ls180.v:3907.6-3907.115"
+ attribute \src "ls180.v:3903.2-3905.5"
+ switch $and$ls180.v:3903$378_Y
+ attribute \src "ls180.v:3903.6-3903.115"
case 1'1
assign $0\main_sdram_bankmachine3_cmd_ready[0:0] 1'1
case
sync always
update \main_sdram_bankmachine3_cmd_ready $0\main_sdram_bankmachine3_cmd_ready[0:0]
end
- attribute \src "ls180.v:391.5-391.38"
- process $proc$ls180.v:391$2882
+ attribute \src "ls180.v:390.5-390.43"
+ process $proc$ls180.v:390$2885
assign { } { }
- assign $1\main_sdram_cmd_payload_ras[0:0] 1'0
+ assign $0\main_sdram_cmd_payload_is_write[0:0] 1'0
sync always
+ update \main_sdram_cmd_payload_is_write $0\main_sdram_cmd_payload_is_write[0:0]
sync init
- update \main_sdram_cmd_payload_ras $1\main_sdram_cmd_payload_ras[0:0]
end
- attribute \src "ls180.v:3915.1-3987.4"
- process $proc$ls180.v:3915$381
+ attribute \src "ls180.v:3911.1-3983.4"
+ process $proc$ls180.v:3911$381
assign { } { }
assign { } { }
assign { } { }
assign $0\main_sdram_cmd_ready[0:0] 1'0
assign $0\main_sdram_choose_req_want_activates[0:0] \main_sdram_ras_allowed
assign $0\builder_multiplexer_next_state[2:0] \builder_multiplexer_state
- attribute \src "ls180.v:3927.2-3986.9"
+ attribute \src "ls180.v:3923.2-3982.9"
switch \builder_multiplexer_state
attribute \src "ls180.v:0.0-0.0"
case 3'001
assign $0\main_sdram_en1[0:0] 1'1
assign $0\main_sdram_choose_req_want_writes[0:0] 1'1
assign $0\main_sdram_steerer_sel[1:0] 2'10
- attribute \src "ls180.v:3931.4-3937.7"
+ attribute \src "ls180.v:3927.4-3933.7"
switch 1'1
- attribute \src "ls180.v:3931.8-3931.12"
+ attribute \src "ls180.v:3927.8-3927.12"
case 1'1
- assign $0\main_sdram_choose_req_cmd_ready[0:0] $and$ls180.v:3932$388_Y
+ assign $0\main_sdram_choose_req_cmd_ready[0:0] $and$ls180.v:3928$388_Y
case
end
- attribute \src "ls180.v:3939.4-3943.7"
+ attribute \src "ls180.v:3935.4-3939.7"
switch \main_sdram_read_available
- attribute \src "ls180.v:3939.8-3939.33"
+ attribute \src "ls180.v:3935.8-3935.33"
case 1'1
- attribute \src "ls180.v:3940.5-3942.8"
- switch $or$ls180.v:3940$390_Y
- attribute \src "ls180.v:3940.9-3940.63"
+ attribute \src "ls180.v:3936.5-3938.8"
+ switch $or$ls180.v:3936$390_Y
+ attribute \src "ls180.v:3936.9-3936.63"
case 1'1
assign $0\builder_multiplexer_next_state[2:0] 3'011
case
end
case
end
- attribute \src "ls180.v:3944.4-3946.7"
+ attribute \src "ls180.v:3940.4-3942.7"
switch \main_sdram_go_to_refresh
- attribute \src "ls180.v:3944.8-3944.32"
+ attribute \src "ls180.v:3940.8-3940.32"
case 1'1
assign $0\builder_multiplexer_next_state[2:0] 3'010
case
case 3'010
assign $0\main_sdram_steerer_sel[1:0] 2'11
assign $0\main_sdram_cmd_ready[0:0] 1'1
- attribute \src "ls180.v:3951.4-3953.7"
+ attribute \src "ls180.v:3947.4-3949.7"
switch \main_sdram_cmd_last
- attribute \src "ls180.v:3951.8-3951.27"
+ attribute \src "ls180.v:3947.8-3947.27"
case 1'1
assign $0\builder_multiplexer_next_state[2:0] 3'000
case
end
attribute \src "ls180.v:0.0-0.0"
case 3'011
- attribute \src "ls180.v:3956.4-3958.7"
+ attribute \src "ls180.v:3952.4-3954.7"
switch \main_sdram_twtrcon_ready
- attribute \src "ls180.v:3956.8-3956.32"
+ attribute \src "ls180.v:3952.8-3952.32"
case 1'1
assign $0\builder_multiplexer_next_state[2:0] 3'000
case
assign $0\main_sdram_en0[0:0] 1'1
assign $0\main_sdram_choose_req_want_reads[0:0] 1'1
assign $0\main_sdram_steerer_sel[1:0] 2'10
- attribute \src "ls180.v:3969.4-3975.7"
+ attribute \src "ls180.v:3965.4-3971.7"
switch 1'1
- attribute \src "ls180.v:3969.8-3969.12"
+ attribute \src "ls180.v:3965.8-3965.12"
case 1'1
- assign $0\main_sdram_choose_req_cmd_ready[0:0] $and$ls180.v:3970$397_Y
+ assign $0\main_sdram_choose_req_cmd_ready[0:0] $and$ls180.v:3966$397_Y
case
end
- attribute \src "ls180.v:3977.4-3981.7"
+ attribute \src "ls180.v:3973.4-3977.7"
switch \main_sdram_write_available
- attribute \src "ls180.v:3977.8-3977.34"
+ attribute \src "ls180.v:3973.8-3973.34"
case 1'1
- attribute \src "ls180.v:3978.5-3980.8"
- switch $or$ls180.v:3978$399_Y
- attribute \src "ls180.v:3978.9-3978.62"
+ attribute \src "ls180.v:3974.5-3976.8"
+ switch $or$ls180.v:3974$399_Y
+ attribute \src "ls180.v:3974.9-3974.62"
case 1'1
assign $0\builder_multiplexer_next_state[2:0] 3'100
case
end
case
end
- attribute \src "ls180.v:3982.4-3984.7"
+ attribute \src "ls180.v:3978.4-3980.7"
switch \main_sdram_go_to_refresh
- attribute \src "ls180.v:3982.8-3982.32"
+ attribute \src "ls180.v:3978.8-3978.32"
case 1'1
assign $0\builder_multiplexer_next_state[2:0] 3'010
case
update \main_sdram_en1 $0\main_sdram_en1[0:0]
update \builder_multiplexer_next_state $0\builder_multiplexer_next_state[2:0]
end
- attribute \src "ls180.v:392.5-392.37"
- process $proc$ls180.v:392$2883
+ attribute \src "ls180.v:396.11-396.44"
+ process $proc$ls180.v:396$2886
assign { } { }
- assign $1\main_sdram_cmd_payload_we[0:0] 1'0
+ assign $1\main_sdram_timer_count1[9:0] 10'1100001101
sync always
sync init
- update \main_sdram_cmd_payload_we $1\main_sdram_cmd_payload_we[0:0]
+ update \main_sdram_timer_count1 $1\main_sdram_timer_count1[9:0]
end
- attribute \src "ls180.v:393.5-393.42"
- process $proc$ls180.v:393$2884
+ attribute \src "ls180.v:398.5-398.38"
+ process $proc$ls180.v:398$2887
assign { } { }
- assign $0\main_sdram_cmd_payload_is_read[0:0] 1'0
+ assign $1\main_sdram_postponer_req_o[0:0] 1'0
sync always
- update \main_sdram_cmd_payload_is_read $0\main_sdram_cmd_payload_is_read[0:0]
sync init
+ update \main_sdram_postponer_req_o $1\main_sdram_postponer_req_o[0:0]
end
- attribute \src "ls180.v:394.5-394.43"
- process $proc$ls180.v:394$2885
+ attribute \src "ls180.v:399.5-399.38"
+ process $proc$ls180.v:399$2888
assign { } { }
- assign $0\main_sdram_cmd_payload_is_write[0:0] 1'0
+ assign $1\main_sdram_postponer_count[0:0] 1'0
sync always
- update \main_sdram_cmd_payload_is_write $0\main_sdram_cmd_payload_is_write[0:0]
sync init
+ update \main_sdram_postponer_count $1\main_sdram_postponer_count[0:0]
end
- attribute \src "ls180.v:400.11-400.44"
- process $proc$ls180.v:400$2886
+ attribute \src "ls180.v:400.5-400.39"
+ process $proc$ls180.v:400$2889
assign { } { }
- assign $1\main_sdram_timer_count1[9:0] 10'1100001101
+ assign $1\main_sdram_sequencer_start0[0:0] 1'0
sync always
sync init
- update \main_sdram_timer_count1 $1\main_sdram_timer_count1[9:0]
+ update \main_sdram_sequencer_start0 $1\main_sdram_sequencer_start0[0:0]
end
- attribute \src "ls180.v:4011.1-4024.4"
- process $proc$ls180.v:4011$528
+ attribute \src "ls180.v:4007.1-4020.4"
+ process $proc$ls180.v:4007$528
assign { } { }
assign { } { }
assign $0\main_sdram_interface_wdata[15:0] 16'0000000000000000
assign $0\main_sdram_interface_wdata_we[1:0] 2'00
- attribute \src "ls180.v:4014.2-4023.9"
+ attribute \src "ls180.v:4010.2-4019.9"
switch \builder_new_master_wdata_ready
attribute \src "ls180.v:0.0-0.0"
case 1'1
update \main_sdram_interface_wdata $0\main_sdram_interface_wdata[15:0]
update \main_sdram_interface_wdata_we $0\main_sdram_interface_wdata_we[1:0]
end
- attribute \src "ls180.v:402.5-402.38"
- process $proc$ls180.v:402$2887
- assign { } { }
- assign $1\main_sdram_postponer_req_o[0:0] 1'0
- sync always
- sync init
- update \main_sdram_postponer_req_o $1\main_sdram_postponer_req_o[0:0]
- end
- attribute \src "ls180.v:403.5-403.38"
- process $proc$ls180.v:403$2888
- assign { } { }
- assign $1\main_sdram_postponer_count[0:0] 1'0
- sync always
- sync init
- update \main_sdram_postponer_count $1\main_sdram_postponer_count[0:0]
- end
- attribute \src "ls180.v:4031.1-4041.4"
- process $proc$ls180.v:4031$530
+ attribute \src "ls180.v:4027.1-4037.4"
+ process $proc$ls180.v:4027$530
assign { } { }
assign $0\main_litedram_wb_dat_w[15:0] 16'0000000000000000
- attribute \src "ls180.v:4033.2-4040.9"
+ attribute \src "ls180.v:4029.2-4036.9"
switch \main_converter_counter
attribute \src "ls180.v:0.0-0.0"
case 1'0
sync always
update \main_litedram_wb_dat_w $0\main_litedram_wb_dat_w[15:0]
end
- attribute \src "ls180.v:404.5-404.39"
- process $proc$ls180.v:404$2889
+ attribute \src "ls180.v:403.5-403.38"
+ process $proc$ls180.v:403$2890
assign { } { }
- assign $1\main_sdram_sequencer_start0[0:0] 1'0
+ assign $1\main_sdram_sequencer_done1[0:0] 1'0
sync always
sync init
- update \main_sdram_sequencer_start0 $1\main_sdram_sequencer_start0[0:0]
+ update \main_sdram_sequencer_done1 $1\main_sdram_sequencer_done1[0:0]
end
- attribute \src "ls180.v:4043.1-4089.4"
- process $proc$ls180.v:4043$531
+ attribute \src "ls180.v:4039.1-4085.4"
+ process $proc$ls180.v:4039$531
assign { } { }
assign { } { }
assign { } { }
assign $0\main_wb_sdram_ack[0:0] 1'0
assign { } { }
assign $0\main_converter_counter_converter_next_value[0:0] 1'0
- assign $0\main_converter_counter_converter_next_value_ce[0:0] 1'0
assign $0\main_litedram_wb_adr[29:0] 30'000000000000000000000000000000
+ assign $0\main_converter_counter_converter_next_value_ce[0:0] 1'0
assign $0\main_litedram_wb_sel[1:0] 2'00
assign $0\main_litedram_wb_cyc[0:0] 1'0
assign $0\main_litedram_wb_stb[0:0] 1'0
assign $0\builder_converter_next_state[0:0] \builder_converter_state
- attribute \src "ls180.v:4055.2-4088.9"
+ attribute \src "ls180.v:4051.2-4084.9"
switch \builder_converter_state
attribute \src "ls180.v:0.0-0.0"
case 1'1
assign $0\main_litedram_wb_adr[29:0] { \main_wb_sdram_adr [28:0] \main_converter_counter }
- attribute \src "ls180.v:4058.4-4065.11"
+ attribute \src "ls180.v:4054.4-4061.11"
switch \main_converter_counter
attribute \src "ls180.v:0.0-0.0"
case 1'0
assign $0\main_litedram_wb_sel[1:0] \main_wb_sdram_sel [3:2]
case
end
- attribute \src "ls180.v:4066.4-4079.7"
- switch $and$ls180.v:4066$532_Y
- attribute \src "ls180.v:4066.8-4066.47"
+ attribute \src "ls180.v:4062.4-4075.7"
+ switch $and$ls180.v:4062$532_Y
+ attribute \src "ls180.v:4062.8-4062.47"
case 1'1
- assign $0\main_converter_skip[0:0] $eq$ls180.v:4067$533_Y
+ assign $0\main_converter_skip[0:0] $eq$ls180.v:4063$533_Y
assign $0\main_litedram_wb_we[0:0] \main_wb_sdram_we
- assign $0\main_litedram_wb_cyc[0:0] $not$ls180.v:4069$534_Y
- assign $0\main_litedram_wb_stb[0:0] $not$ls180.v:4070$535_Y
- attribute \src "ls180.v:4071.5-4078.8"
- switch $or$ls180.v:4071$536_Y
- attribute \src "ls180.v:4071.9-4071.53"
+ assign $0\main_litedram_wb_cyc[0:0] $not$ls180.v:4065$534_Y
+ assign $0\main_litedram_wb_stb[0:0] $not$ls180.v:4066$535_Y
+ attribute \src "ls180.v:4067.5-4074.8"
+ switch $or$ls180.v:4067$536_Y
+ attribute \src "ls180.v:4067.9-4067.53"
case 1'1
- assign $0\main_converter_counter_converter_next_value[0:0] $add$ls180.v:4072$537_Y
+ assign $0\main_converter_counter_converter_next_value[0:0] $add$ls180.v:4068$537_Y
assign $0\main_converter_counter_converter_next_value_ce[0:0] 1'1
- attribute \src "ls180.v:4074.6-4077.9"
- switch $eq$ls180.v:4074$538_Y
- attribute \src "ls180.v:4074.10-4074.42"
+ attribute \src "ls180.v:4070.6-4073.9"
+ switch $eq$ls180.v:4070$538_Y
+ attribute \src "ls180.v:4070.10-4070.42"
case 1'1
assign $0\main_wb_sdram_ack[0:0] 1'1
assign $0\builder_converter_next_state[0:0] 1'0
case
assign $0\main_converter_counter_converter_next_value[0:0] 1'0
assign $0\main_converter_counter_converter_next_value_ce[0:0] 1'1
- attribute \src "ls180.v:4084.4-4086.7"
- switch $and$ls180.v:4084$539_Y
- attribute \src "ls180.v:4084.8-4084.47"
+ attribute \src "ls180.v:4080.4-4082.7"
+ switch $and$ls180.v:4080$539_Y
+ attribute \src "ls180.v:4080.8-4080.47"
case 1'1
assign $0\builder_converter_next_state[0:0] 1'1
case
update \main_converter_counter_converter_next_value $0\main_converter_counter_converter_next_value[0:0]
update \main_converter_counter_converter_next_value_ce $0\main_converter_counter_converter_next_value_ce[0:0]
end
- attribute \src "ls180.v:407.5-407.38"
- process $proc$ls180.v:407$2890
- assign { } { }
- assign $1\main_sdram_sequencer_done1[0:0] 1'0
- sync always
- sync init
- update \main_sdram_sequencer_done1 $1\main_sdram_sequencer_done1[0:0]
- end
- attribute \src "ls180.v:408.11-408.46"
- process $proc$ls180.v:408$2891
+ attribute \src "ls180.v:404.11-404.46"
+ process $proc$ls180.v:404$2891
assign { } { }
assign $1\main_sdram_sequencer_counter[3:0] 4'0000
sync always
sync init
update \main_sdram_sequencer_counter $1\main_sdram_sequencer_counter[3:0]
end
- attribute \src "ls180.v:409.5-409.38"
- process $proc$ls180.v:409$2892
+ attribute \src "ls180.v:405.5-405.38"
+ process $proc$ls180.v:405$2892
assign { } { }
assign $1\main_sdram_sequencer_count[0:0] 1'0
sync always
sync init
update \main_sdram_sequencer_count $1\main_sdram_sequencer_count[0:0]
end
- attribute \src "ls180.v:4134.1-4139.4"
- process $proc$ls180.v:4134$571
+ attribute \src "ls180.v:411.5-411.51"
+ process $proc$ls180.v:411$2893
+ assign { } { }
+ assign $1\main_sdram_bankmachine0_req_wdata_ready[0:0] 1'0
+ sync always
+ sync init
+ update \main_sdram_bankmachine0_req_wdata_ready $1\main_sdram_bankmachine0_req_wdata_ready[0:0]
+ end
+ attribute \src "ls180.v:412.5-412.51"
+ process $proc$ls180.v:412$2894
+ assign { } { }
+ assign $1\main_sdram_bankmachine0_req_rdata_valid[0:0] 1'0
+ sync always
+ sync init
+ update \main_sdram_bankmachine0_req_rdata_valid $1\main_sdram_bankmachine0_req_rdata_valid[0:0]
+ end
+ attribute \src "ls180.v:4130.1-4135.4"
+ process $proc$ls180.v:4130$571
assign { } { }
assign $0\main_uart_tx_clear[0:0] 1'0
- attribute \src "ls180.v:4136.2-4138.5"
- switch $and$ls180.v:4136$572_Y
- attribute \src "ls180.v:4136.6-4136.79"
+ attribute \src "ls180.v:4132.2-4134.5"
+ switch $and$ls180.v:4132$572_Y
+ attribute \src "ls180.v:4132.6-4132.79"
case 1'1
assign $0\main_uart_tx_clear[0:0] 1'1
case
sync always
update \main_uart_tx_clear $0\main_uart_tx_clear[0:0]
end
- attribute \src "ls180.v:4140.1-4144.4"
- process $proc$ls180.v:4140$573
+ attribute \src "ls180.v:4136.1-4140.4"
+ process $proc$ls180.v:4136$573
assign { } { }
assign { } { }
assign $0\main_uart_eventmanager_status_w[1:0] [0] \main_uart_tx_status
sync always
update \main_uart_eventmanager_status_w $0\main_uart_eventmanager_status_w[1:0]
end
- attribute \src "ls180.v:4145.1-4150.4"
- process $proc$ls180.v:4145$574
+ attribute \src "ls180.v:414.5-414.47"
+ process $proc$ls180.v:414$2895
+ assign { } { }
+ assign $1\main_sdram_bankmachine0_refresh_gnt[0:0] 1'0
+ sync always
+ sync init
+ update \main_sdram_bankmachine0_refresh_gnt $1\main_sdram_bankmachine0_refresh_gnt[0:0]
+ end
+ attribute \src "ls180.v:4141.1-4146.4"
+ process $proc$ls180.v:4141$574
assign { } { }
assign $0\main_uart_rx_clear[0:0] 1'0
- attribute \src "ls180.v:4147.2-4149.5"
- switch $and$ls180.v:4147$575_Y
- attribute \src "ls180.v:4147.6-4147.79"
+ attribute \src "ls180.v:4143.2-4145.5"
+ switch $and$ls180.v:4143$575_Y
+ attribute \src "ls180.v:4143.6-4143.79"
case 1'1
assign $0\main_uart_rx_clear[0:0] 1'1
case
sync always
update \main_uart_rx_clear $0\main_uart_rx_clear[0:0]
end
- attribute \src "ls180.v:415.5-415.51"
- process $proc$ls180.v:415$2893
- assign { } { }
- assign $1\main_sdram_bankmachine0_req_wdata_ready[0:0] 1'0
- sync always
- sync init
- update \main_sdram_bankmachine0_req_wdata_ready $1\main_sdram_bankmachine0_req_wdata_ready[0:0]
- end
- attribute \src "ls180.v:4151.1-4155.4"
- process $proc$ls180.v:4151$576
+ attribute \src "ls180.v:4147.1-4151.4"
+ process $proc$ls180.v:4147$576
assign { } { }
assign { } { }
assign $0\main_uart_eventmanager_pending_w[1:0] [0] \main_uart_tx_pending
sync always
update \main_uart_eventmanager_pending_w $0\main_uart_eventmanager_pending_w[1:0]
end
- attribute \src "ls180.v:416.5-416.51"
- process $proc$ls180.v:416$2894
+ attribute \src "ls180.v:415.5-415.45"
+ process $proc$ls180.v:415$2896
assign { } { }
- assign $1\main_sdram_bankmachine0_req_rdata_valid[0:0] 1'0
+ assign $1\main_sdram_bankmachine0_cmd_valid[0:0] 1'0
sync always
sync init
- update \main_sdram_bankmachine0_req_rdata_valid $1\main_sdram_bankmachine0_req_rdata_valid[0:0]
+ update \main_sdram_bankmachine0_cmd_valid $1\main_sdram_bankmachine0_cmd_valid[0:0]
end
- attribute \src "ls180.v:4173.1-4180.4"
- process $proc$ls180.v:4173$584
+ attribute \src "ls180.v:416.5-416.45"
+ process $proc$ls180.v:416$2897
+ assign { } { }
+ assign $1\main_sdram_bankmachine0_cmd_ready[0:0] 1'0
+ sync always
+ sync init
+ update \main_sdram_bankmachine0_cmd_ready $1\main_sdram_bankmachine0_cmd_ready[0:0]
+ end
+ attribute \src "ls180.v:4169.1-4176.4"
+ process $proc$ls180.v:4169$584
assign { } { }
assign $0\main_uart_tx_fifo_wrport_adr[3:0] 4'0000
- attribute \src "ls180.v:4175.2-4179.5"
+ attribute \src "ls180.v:4171.2-4175.5"
switch \main_uart_tx_fifo_replace
- attribute \src "ls180.v:4175.6-4175.31"
+ attribute \src "ls180.v:4171.6-4171.31"
case 1'1
- assign $0\main_uart_tx_fifo_wrport_adr[3:0] $sub$ls180.v:4176$585_Y
- attribute \src "ls180.v:4177.6-4177.10"
+ assign $0\main_uart_tx_fifo_wrport_adr[3:0] $sub$ls180.v:4172$585_Y
+ attribute \src "ls180.v:4173.6-4173.10"
case
assign $0\main_uart_tx_fifo_wrport_adr[3:0] \main_uart_tx_fifo_produce
end
sync always
update \main_uart_tx_fifo_wrport_adr $0\main_uart_tx_fifo_wrport_adr[3:0]
end
- attribute \src "ls180.v:418.5-418.47"
- process $proc$ls180.v:418$2895
+ attribute \src "ls180.v:417.12-417.57"
+ process $proc$ls180.v:417$2898
assign { } { }
- assign $1\main_sdram_bankmachine0_refresh_gnt[0:0] 1'0
- sync always
- sync init
- update \main_sdram_bankmachine0_refresh_gnt $1\main_sdram_bankmachine0_refresh_gnt[0:0]
- end
- attribute \src "ls180.v:419.5-419.45"
- process $proc$ls180.v:419$2896
- assign { } { }
- assign $1\main_sdram_bankmachine0_cmd_valid[0:0] 1'0
+ assign $1\main_sdram_bankmachine0_cmd_payload_a[12:0] 13'0000000000000
sync always
sync init
- update \main_sdram_bankmachine0_cmd_valid $1\main_sdram_bankmachine0_cmd_valid[0:0]
+ update \main_sdram_bankmachine0_cmd_payload_a $1\main_sdram_bankmachine0_cmd_payload_a[12:0]
end
- attribute \src "ls180.v:420.5-420.45"
- process $proc$ls180.v:420$2897
+ attribute \src "ls180.v:419.5-419.51"
+ process $proc$ls180.v:419$2899
assign { } { }
- assign $1\main_sdram_bankmachine0_cmd_ready[0:0] 1'0
+ assign $1\main_sdram_bankmachine0_cmd_payload_cas[0:0] 1'0
sync always
sync init
- update \main_sdram_bankmachine0_cmd_ready $1\main_sdram_bankmachine0_cmd_ready[0:0]
+ update \main_sdram_bankmachine0_cmd_payload_cas $1\main_sdram_bankmachine0_cmd_payload_cas[0:0]
end
- attribute \src "ls180.v:4203.1-4210.4"
- process $proc$ls180.v:4203$595
+ attribute \src "ls180.v:4199.1-4206.4"
+ process $proc$ls180.v:4199$595
assign { } { }
assign $0\main_uart_rx_fifo_wrport_adr[3:0] 4'0000
- attribute \src "ls180.v:4205.2-4209.5"
+ attribute \src "ls180.v:4201.2-4205.5"
switch \main_uart_rx_fifo_replace
- attribute \src "ls180.v:4205.6-4205.31"
+ attribute \src "ls180.v:4201.6-4201.31"
case 1'1
- assign $0\main_uart_rx_fifo_wrport_adr[3:0] $sub$ls180.v:4206$596_Y
- attribute \src "ls180.v:4207.6-4207.10"
+ assign $0\main_uart_rx_fifo_wrport_adr[3:0] $sub$ls180.v:4202$596_Y
+ attribute \src "ls180.v:4203.6-4203.10"
case
assign $0\main_uart_rx_fifo_wrport_adr[3:0] \main_uart_rx_fifo_produce
end
sync always
update \main_uart_rx_fifo_wrport_adr $0\main_uart_rx_fifo_wrport_adr[3:0]
end
- attribute \src "ls180.v:421.12-421.57"
- process $proc$ls180.v:421$2898
+ attribute \src "ls180.v:420.5-420.51"
+ process $proc$ls180.v:420$2900
assign { } { }
- assign $1\main_sdram_bankmachine0_cmd_payload_a[12:0] 13'0000000000000
+ assign $1\main_sdram_bankmachine0_cmd_payload_ras[0:0] 1'0
sync always
sync init
- update \main_sdram_bankmachine0_cmd_payload_a $1\main_sdram_bankmachine0_cmd_payload_a[12:0]
+ update \main_sdram_bankmachine0_cmd_payload_ras $1\main_sdram_bankmachine0_cmd_payload_ras[0:0]
end
- attribute \src "ls180.v:423.5-423.51"
- process $proc$ls180.v:423$2899
+ attribute \src "ls180.v:421.5-421.50"
+ process $proc$ls180.v:421$2901
assign { } { }
- assign $1\main_sdram_bankmachine0_cmd_payload_cas[0:0] 1'0
+ assign $1\main_sdram_bankmachine0_cmd_payload_we[0:0] 1'0
sync always
sync init
- update \main_sdram_bankmachine0_cmd_payload_cas $1\main_sdram_bankmachine0_cmd_payload_cas[0:0]
+ update \main_sdram_bankmachine0_cmd_payload_we $1\main_sdram_bankmachine0_cmd_payload_we[0:0]
end
- attribute \src "ls180.v:4233.1-4281.4"
- process $proc$ls180.v:4233$606
+ attribute \src "ls180.v:422.5-422.54"
+ process $proc$ls180.v:422$2902
assign { } { }
+ assign $1\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'0
+ sync always
+ sync init
+ update \main_sdram_bankmachine0_cmd_payload_is_cmd $1\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0]
+ end
+ attribute \src "ls180.v:4229.1-4277.4"
+ process $proc$ls180.v:4229$606
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign $0\main_spimaster25_clk_enable[0:0] 1'0
- assign $0\main_spimaster27_count_spimaster0_next_value[2:0] 3'000
assign $0\main_spimaster26_cs_enable[0:0] 1'0
- assign $0\main_spimaster27_count_spimaster0_next_value_ce[0:0] 1'0
+ assign { } { }
assign $0\main_spimaster28_mosi_latch[0:0] 1'0
+ assign $0\main_spimaster27_count_spimaster0_next_value[2:0] 3'000
assign $0\main_spimaster2_done[0:0] 1'0
+ assign $0\main_spimaster27_count_spimaster0_next_value_ce[0:0] 1'0
assign $0\main_spimaster29_miso_latch[0:0] 1'0
assign $0\main_spimaster3_irq[0:0] 1'0
assign $0\builder_spimaster0_next_state[1:0] \builder_spimaster0_state
- attribute \src "ls180.v:4244.2-4280.9"
+ attribute \src "ls180.v:4240.2-4276.9"
switch \builder_spimaster0_state
attribute \src "ls180.v:0.0-0.0"
case 2'01
assign $0\main_spimaster27_count_spimaster0_next_value[2:0] 3'000
assign $0\main_spimaster27_count_spimaster0_next_value_ce[0:0] 1'1
- attribute \src "ls180.v:4248.4-4251.7"
+ attribute \src "ls180.v:4244.4-4247.7"
switch \main_spimaster32_clk_fall
- attribute \src "ls180.v:4248.8-4248.33"
+ attribute \src "ls180.v:4244.8-4244.33"
case 1'1
assign $0\main_spimaster26_cs_enable[0:0] 1'1
assign $0\builder_spimaster0_next_state[1:0] 2'10
case 2'10
assign $0\main_spimaster25_clk_enable[0:0] 1'1
assign $0\main_spimaster26_cs_enable[0:0] 1'1
- attribute \src "ls180.v:4256.4-4262.7"
+ attribute \src "ls180.v:4252.4-4258.7"
switch \main_spimaster32_clk_fall
- attribute \src "ls180.v:4256.8-4256.33"
+ attribute \src "ls180.v:4252.8-4252.33"
case 1'1
- assign $0\main_spimaster27_count_spimaster0_next_value[2:0] $add$ls180.v:4257$607_Y
+ assign $0\main_spimaster27_count_spimaster0_next_value[2:0] $add$ls180.v:4253$607_Y
assign $0\main_spimaster27_count_spimaster0_next_value_ce[0:0] 1'1
- attribute \src "ls180.v:4259.5-4261.8"
- switch $eq$ls180.v:4259$609_Y
- attribute \src "ls180.v:4259.9-4259.68"
+ attribute \src "ls180.v:4255.5-4257.8"
+ switch $eq$ls180.v:4255$609_Y
+ attribute \src "ls180.v:4255.9-4255.68"
case 1'1
assign $0\builder_spimaster0_next_state[1:0] 2'11
case
attribute \src "ls180.v:0.0-0.0"
case 2'11
assign $0\main_spimaster26_cs_enable[0:0] 1'1
- attribute \src "ls180.v:4266.4-4270.7"
+ attribute \src "ls180.v:4262.4-4266.7"
switch \main_spimaster31_clk_rise
- attribute \src "ls180.v:4266.8-4266.33"
+ attribute \src "ls180.v:4262.8-4262.33"
case 1'1
assign $0\main_spimaster29_miso_latch[0:0] 1'1
assign $0\main_spimaster3_irq[0:0] 1'1
attribute \src "ls180.v:0.0-0.0"
case
assign $0\main_spimaster2_done[0:0] 1'1
- attribute \src "ls180.v:4274.4-4278.7"
+ attribute \src "ls180.v:4270.4-4274.7"
switch \main_spimaster0_start
- attribute \src "ls180.v:4274.8-4274.29"
+ attribute \src "ls180.v:4270.8-4270.29"
case 1'1
assign $0\main_spimaster2_done[0:0] 1'0
assign $0\main_spimaster28_mosi_latch[0:0] 1'1
update \main_spimaster27_count_spimaster0_next_value $0\main_spimaster27_count_spimaster0_next_value[2:0]
update \main_spimaster27_count_spimaster0_next_value_ce $0\main_spimaster27_count_spimaster0_next_value_ce[0:0]
end
- attribute \src "ls180.v:424.5-424.51"
- process $proc$ls180.v:424$2900
- assign { } { }
- assign $1\main_sdram_bankmachine0_cmd_payload_ras[0:0] 1'0
- sync always
- sync init
- update \main_sdram_bankmachine0_cmd_payload_ras $1\main_sdram_bankmachine0_cmd_payload_ras[0:0]
- end
- attribute \src "ls180.v:425.5-425.50"
- process $proc$ls180.v:425$2901
- assign { } { }
- assign $1\main_sdram_bankmachine0_cmd_payload_we[0:0] 1'0
- sync always
- sync init
- update \main_sdram_bankmachine0_cmd_payload_we $1\main_sdram_bankmachine0_cmd_payload_we[0:0]
- end
- attribute \src "ls180.v:426.5-426.54"
- process $proc$ls180.v:426$2902
- assign { } { }
- assign $1\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'0
- sync always
- sync init
- update \main_sdram_bankmachine0_cmd_payload_is_cmd $1\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0]
- end
- attribute \src "ls180.v:427.5-427.55"
- process $proc$ls180.v:427$2903
+ attribute \src "ls180.v:423.5-423.55"
+ process $proc$ls180.v:423$2903
assign { } { }
assign $1\main_sdram_bankmachine0_cmd_payload_is_read[0:0] 1'0
sync always
sync init
update \main_sdram_bankmachine0_cmd_payload_is_read $1\main_sdram_bankmachine0_cmd_payload_is_read[0:0]
end
- attribute \src "ls180.v:428.5-428.56"
- process $proc$ls180.v:428$2904
+ attribute \src "ls180.v:424.5-424.56"
+ process $proc$ls180.v:424$2904
assign { } { }
assign $1\main_sdram_bankmachine0_cmd_payload_is_write[0:0] 1'0
sync always
sync init
update \main_sdram_bankmachine0_cmd_payload_is_write $1\main_sdram_bankmachine0_cmd_payload_is_write[0:0]
end
- attribute \src "ls180.v:429.5-429.50"
- process $proc$ls180.v:429$2905
+ attribute \src "ls180.v:425.5-425.50"
+ process $proc$ls180.v:425$2905
assign { } { }
assign $1\main_sdram_bankmachine0_auto_precharge[0:0] 1'0
sync always
sync init
update \main_sdram_bankmachine0_auto_precharge $1\main_sdram_bankmachine0_auto_precharge[0:0]
end
- attribute \src "ls180.v:4292.1-4340.4"
- process $proc$ls180.v:4292$614
+ attribute \src "ls180.v:428.5-428.67"
+ process $proc$ls180.v:428$2906
+ assign { } { }
+ assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first[0:0] 1'0
+ sync always
+ update \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first[0:0]
+ sync init
+ end
+ attribute \src "ls180.v:4288.1-4336.4"
+ process $proc$ls180.v:4288$614
assign { } { }
assign { } { }
assign { } { }
assign $0\main_spisdcard_miso_latch[0:0] 1'0
assign $0\main_spisdcard_irq[0:0] 1'0
assign $0\builder_spimaster1_next_state[1:0] \builder_spimaster1_state
- attribute \src "ls180.v:4303.2-4339.9"
+ attribute \src "ls180.v:4299.2-4335.9"
switch \builder_spimaster1_state
attribute \src "ls180.v:0.0-0.0"
case 2'01
assign $0\main_spisdcard_count_spimaster1_next_value[2:0] 3'000
assign $0\main_spisdcard_count_spimaster1_next_value_ce[0:0] 1'1
- attribute \src "ls180.v:4307.4-4310.7"
+ attribute \src "ls180.v:4303.4-4306.7"
switch \main_spisdcard_clk_fall
- attribute \src "ls180.v:4307.8-4307.31"
+ attribute \src "ls180.v:4303.8-4303.31"
case 1'1
assign $0\main_spisdcard_cs_enable[0:0] 1'1
assign $0\builder_spimaster1_next_state[1:0] 2'10
case 2'10
assign $0\main_spisdcard_clk_enable[0:0] 1'1
assign $0\main_spisdcard_cs_enable[0:0] 1'1
- attribute \src "ls180.v:4315.4-4321.7"
+ attribute \src "ls180.v:4311.4-4317.7"
switch \main_spisdcard_clk_fall
- attribute \src "ls180.v:4315.8-4315.31"
+ attribute \src "ls180.v:4311.8-4311.31"
case 1'1
- assign $0\main_spisdcard_count_spimaster1_next_value[2:0] $add$ls180.v:4316$615_Y
+ assign $0\main_spisdcard_count_spimaster1_next_value[2:0] $add$ls180.v:4312$615_Y
assign $0\main_spisdcard_count_spimaster1_next_value_ce[0:0] 1'1
- attribute \src "ls180.v:4318.5-4320.8"
- switch $eq$ls180.v:4318$617_Y
- attribute \src "ls180.v:4318.9-4318.66"
+ attribute \src "ls180.v:4314.5-4316.8"
+ switch $eq$ls180.v:4314$617_Y
+ attribute \src "ls180.v:4314.9-4314.66"
case 1'1
assign $0\builder_spimaster1_next_state[1:0] 2'11
case
attribute \src "ls180.v:0.0-0.0"
case 2'11
assign $0\main_spisdcard_cs_enable[0:0] 1'1
- attribute \src "ls180.v:4325.4-4329.7"
+ attribute \src "ls180.v:4321.4-4325.7"
switch \main_spisdcard_clk_rise
- attribute \src "ls180.v:4325.8-4325.31"
+ attribute \src "ls180.v:4321.8-4321.31"
case 1'1
assign $0\main_spisdcard_miso_latch[0:0] 1'1
assign $0\main_spisdcard_irq[0:0] 1'1
attribute \src "ls180.v:0.0-0.0"
case
assign $0\main_spisdcard_done0[0:0] 1'1
- attribute \src "ls180.v:4333.4-4337.7"
+ attribute \src "ls180.v:4329.4-4333.7"
switch \main_spisdcard_start0
- attribute \src "ls180.v:4333.8-4333.29"
+ attribute \src "ls180.v:4329.8-4329.29"
case 1'1
assign $0\main_spisdcard_done0[0:0] 1'0
assign $0\main_spisdcard_mosi_latch[0:0] 1'1
update \main_spisdcard_count_spimaster1_next_value $0\main_spisdcard_count_spimaster1_next_value[2:0]
update \main_spisdcard_count_spimaster1_next_value_ce $0\main_spisdcard_count_spimaster1_next_value_ce[0:0]
end
- attribute \src "ls180.v:432.5-432.67"
- process $proc$ls180.v:432$2906
- assign { } { }
- assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first[0:0] 1'0
- sync always
- update \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first[0:0]
- sync init
- end
- attribute \src "ls180.v:433.5-433.66"
- process $proc$ls180.v:433$2907
+ attribute \src "ls180.v:429.5-429.66"
+ process $proc$ls180.v:429$2907
assign { } { }
assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last[0:0] 1'0
sync always
update \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last[0:0]
sync init
end
- attribute \src "ls180.v:4372.1-4400.4"
- process $proc$ls180.v:4372$639
+ attribute \src "ls180.v:4368.1-4396.4"
+ process $proc$ls180.v:4368$639
assign { } { }
assign $0\main_sdphy_clocker_clk1[0:0] 1'0
- attribute \src "ls180.v:4374.2-4399.9"
+ attribute \src "ls180.v:4370.2-4395.9"
switch \main_sdphy_clocker_storage
attribute \src "ls180.v:0.0-0.0"
case 9'000000100
sync always
update \main_sdphy_clocker_clk1 $0\main_sdphy_clocker_clk1[0:0]
end
- attribute \src "ls180.v:4402.1-4435.4"
- process $proc$ls180.v:4402$642
+ attribute \src "ls180.v:4398.1-4431.4"
+ process $proc$ls180.v:4398$642
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign $0\main_sdphy_init_pads_out_payload_cmd_oe[0:0] 1'0
+ assign $0\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] 1'0
+ assign $0\main_sdphy_init_pads_out_payload_cmd_o[0:0] 1'0
assign $0\main_sdphy_init_pads_out_payload_data_o[3:0] 4'0000
assign $0\main_sdphy_init_pads_out_payload_data_oe[0:0] 1'0
- assign { } { }
assign $0\main_sdphy_init_pads_out_payload_clk[0:0] 1'0
+ assign { } { }
assign $0\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] 8'00000000
- assign $0\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] 1'0
- assign $0\main_sdphy_init_pads_out_payload_cmd_o[0:0] 1'0
assign $0\builder_sdphy_sdphyinit_next_state[0:0] \builder_sdphy_sdphyinit_state
- attribute \src "ls180.v:4412.2-4434.9"
+ attribute \src "ls180.v:4408.2-4430.9"
switch \builder_sdphy_sdphyinit_state
attribute \src "ls180.v:0.0-0.0"
case 1'1
assign $0\main_sdphy_init_pads_out_payload_cmd_o[0:0] 1'1
assign $0\main_sdphy_init_pads_out_payload_data_oe[0:0] 1'1
assign $0\main_sdphy_init_pads_out_payload_data_o[3:0] 4'1111
- attribute \src "ls180.v:4419.4-4425.7"
+ attribute \src "ls180.v:4415.4-4421.7"
switch \main_sdphy_init_pads_out_ready
- attribute \src "ls180.v:4419.8-4419.38"
+ attribute \src "ls180.v:4415.8-4415.38"
case 1'1
- assign $0\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] $add$ls180.v:4420$643_Y
+ assign $0\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] $add$ls180.v:4416$643_Y
assign $0\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] 1'1
- attribute \src "ls180.v:4422.5-4424.8"
- switch $eq$ls180.v:4422$644_Y
- attribute \src "ls180.v:4422.9-4422.41"
+ attribute \src "ls180.v:4418.5-4420.8"
+ switch $eq$ls180.v:4418$644_Y
+ attribute \src "ls180.v:4418.9-4418.41"
case 1'1
assign $0\builder_sdphy_sdphyinit_next_state[0:0] 1'0
case
case
assign $0\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] 8'00000000
assign $0\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] 1'1
- attribute \src "ls180.v:4430.4-4432.7"
+ attribute \src "ls180.v:4426.4-4428.7"
switch \main_sdphy_init_initialize_re
- attribute \src "ls180.v:4430.8-4430.37"
+ attribute \src "ls180.v:4426.8-4426.37"
case 1'1
assign $0\builder_sdphy_sdphyinit_next_state[0:0] 1'1
case
update \main_sdphy_init_count_sdphy_sdphyinit_next_value $0\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0]
update \main_sdphy_init_count_sdphy_sdphyinit_next_value_ce $0\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0]
end
- attribute \src "ls180.v:4436.1-4512.4"
- process $proc$ls180.v:4436$645
+ attribute \src "ls180.v:4432.1-4508.4"
+ process $proc$ls180.v:4432$645
assign { } { }
assign { } { }
assign { } { }
assign $0\main_sdphy_cmdw_done[0:0] 1'0
assign { } { }
assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] 8'00000000
- assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] 1'0
assign $0\main_sdphy_cmdw_pads_out_payload_clk[0:0] 1'0
+ assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] 1'0
assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] 1'0
assign $0\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] 1'0
assign $0\builder_sdphy_sdphycmdw_next_state[1:0] \builder_sdphy_sdphycmdw_state
- attribute \src "ls180.v:4446.2-4511.9"
+ attribute \src "ls180.v:4442.2-4507.9"
switch \builder_sdphy_sdphycmdw_state
attribute \src "ls180.v:0.0-0.0"
case 2'01
assign $0\main_sdphy_cmdw_pads_out_payload_clk[0:0] 1'1
assign $0\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] 1'1
- attribute \src "ls180.v:4450.4-4475.11"
+ attribute \src "ls180.v:4446.4-4471.11"
switch \main_sdphy_cmdw_count
attribute \src "ls180.v:0.0-0.0"
case 8'00000000
assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] \main_sdphy_cmdw_sink_payload_data [0]
case
end
- attribute \src "ls180.v:4476.4-4487.7"
+ attribute \src "ls180.v:4472.4-4483.7"
switch \main_sdphy_cmdw_pads_out_ready
- attribute \src "ls180.v:4476.8-4476.38"
+ attribute \src "ls180.v:4472.8-4472.38"
case 1'1
- assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] $add$ls180.v:4477$646_Y
+ assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] $add$ls180.v:4473$646_Y
assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] 1'1
- attribute \src "ls180.v:4479.5-4486.8"
- switch $eq$ls180.v:4479$647_Y
- attribute \src "ls180.v:4479.9-4479.40"
+ attribute \src "ls180.v:4475.5-4482.8"
+ switch $eq$ls180.v:4475$647_Y
+ attribute \src "ls180.v:4475.9-4475.40"
case 1'1
- attribute \src "ls180.v:4480.6-4485.9"
+ attribute \src "ls180.v:4476.6-4481.9"
switch \main_sdphy_cmdw_sink_last
- attribute \src "ls180.v:4480.10-4480.35"
+ attribute \src "ls180.v:4476.10-4476.35"
case 1'1
assign $0\builder_sdphy_sdphycmdw_next_state[1:0] 2'10
- attribute \src "ls180.v:4482.10-4482.14"
+ attribute \src "ls180.v:4478.10-4478.14"
case
assign $0\main_sdphy_cmdw_sink_ready[0:0] 1'1
assign $0\builder_sdphy_sdphycmdw_next_state[1:0] 2'00
assign $0\main_sdphy_cmdw_pads_out_payload_clk[0:0] 1'1
assign $0\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] 1'1
assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] 1'1
- attribute \src "ls180.v:4493.4-4500.7"
+ attribute \src "ls180.v:4489.4-4496.7"
switch \main_sdphy_cmdw_pads_out_ready
- attribute \src "ls180.v:4493.8-4493.38"
+ attribute \src "ls180.v:4489.8-4489.38"
case 1'1
- assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] $add$ls180.v:4494$648_Y
+ assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] $add$ls180.v:4490$648_Y
assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] 1'1
- attribute \src "ls180.v:4496.5-4499.8"
- switch $eq$ls180.v:4496$649_Y
- attribute \src "ls180.v:4496.9-4496.40"
+ attribute \src "ls180.v:4492.5-4495.8"
+ switch $eq$ls180.v:4492$649_Y
+ attribute \src "ls180.v:4492.9-4492.40"
case 1'1
assign $0\main_sdphy_cmdw_sink_ready[0:0] 1'1
assign $0\builder_sdphy_sdphycmdw_next_state[1:0] 2'00
case
assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] 8'00000000
assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] 1'1
- attribute \src "ls180.v:4505.4-4509.7"
- switch $and$ls180.v:4505$650_Y
- attribute \src "ls180.v:4505.8-4505.69"
+ attribute \src "ls180.v:4501.4-4505.7"
+ switch $and$ls180.v:4501$650_Y
+ attribute \src "ls180.v:4501.8-4501.69"
case 1'1
assign $0\builder_sdphy_sdphycmdw_next_state[1:0] 2'01
- attribute \src "ls180.v:4507.8-4507.12"
+ attribute \src "ls180.v:4503.8-4503.12"
case
assign $0\main_sdphy_cmdw_done[0:0] 1'1
end
update \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0]
update \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0]
end
- attribute \src "ls180.v:448.11-448.68"
- process $proc$ls180.v:448$2908
+ attribute \src "ls180.v:444.11-444.68"
+ process $proc$ls180.v:444$2908
assign { } { }
assign $1\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] 4'0000
sync always
sync init
update \main_sdram_bankmachine0_cmd_buffer_lookahead_level $1\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0]
end
- attribute \src "ls180.v:449.5-449.64"
- process $proc$ls180.v:449$2909
+ attribute \src "ls180.v:445.5-445.64"
+ process $proc$ls180.v:445$2909
assign { } { }
assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_replace[0:0] 1'0
sync always
update \main_sdram_bankmachine0_cmd_buffer_lookahead_replace $0\main_sdram_bankmachine0_cmd_buffer_lookahead_replace[0:0]
sync init
end
- attribute \src "ls180.v:450.11-450.70"
- process $proc$ls180.v:450$2910
+ attribute \src "ls180.v:446.11-446.70"
+ process $proc$ls180.v:446$2910
assign { } { }
assign $1\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] 3'000
sync always
sync init
update \main_sdram_bankmachine0_cmd_buffer_lookahead_produce $1\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0]
end
- attribute \src "ls180.v:451.11-451.70"
- process $proc$ls180.v:451$2911
+ attribute \src "ls180.v:447.11-447.70"
+ process $proc$ls180.v:447$2911
assign { } { }
assign $1\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] 3'000
sync always
sync init
update \main_sdram_bankmachine0_cmd_buffer_lookahead_consume $1\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0]
end
- attribute \src "ls180.v:452.11-452.73"
- process $proc$ls180.v:452$2912
+ attribute \src "ls180.v:448.11-448.73"
+ process $proc$ls180.v:448$2912
assign { } { }
assign $1\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] 3'000
sync always
sync init
update \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr $1\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0]
end
- attribute \src "ls180.v:4546.1-4639.4"
- process $proc$ls180.v:4546$659
+ attribute \src "ls180.v:4542.1-4635.4"
+ process $proc$ls180.v:4542$659
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign $0\main_sdphy_cmdr_source_valid[0:0] 1'0
assign $0\main_sdphy_cmdr_source_last[0:0] 1'0
- assign { } { }
assign $0\main_sdphy_cmdr_source_payload_data[7:0] 8'00000000
- assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] 8'00000000
assign $0\main_sdphy_cmdr_source_payload_status[2:0] 3'000
+ assign { } { }
+ assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] 8'00000000
assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] 1'0
assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] 0
assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] 1'0
assign $0\main_sdphy_cmdr_pads_out_payload_cmd_oe[0:0] 1'0
assign $0\main_sdphy_cmdr_sink_ready[0:0] 1'0
assign $0\builder_sdphy_sdphycmdr_next_state[2:0] \builder_sdphy_sdphycmdr_state
- attribute \src "ls180.v:4564.2-4638.9"
+ attribute \src "ls180.v:4560.2-4634.9"
switch \builder_sdphy_sdphycmdr_state
attribute \src "ls180.v:0.0-0.0"
case 3'001
assign $0\main_sdphy_cmdr_pads_out_payload_clk[0:0] 1'1
assign $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] 1'0
assign $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] 1'1
- assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] $sub$ls180.v:4572$660_Y
+ assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] $sub$ls180.v:4568$660_Y
assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] 1'1
- attribute \src "ls180.v:4569.4-4571.7"
+ attribute \src "ls180.v:4565.4-4567.7"
switch \main_sdphy_cmdr_cmdr_source_source_valid0
- attribute \src "ls180.v:4569.8-4569.49"
+ attribute \src "ls180.v:4565.8-4565.49"
case 1'1
assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'010
case
end
- attribute \src "ls180.v:4574.4-4577.7"
- switch $eq$ls180.v:4574$661_Y
- attribute \src "ls180.v:4574.8-4574.41"
+ attribute \src "ls180.v:4570.4-4573.7"
+ switch $eq$ls180.v:4570$661_Y
+ attribute \src "ls180.v:4570.8-4570.41"
case 1'1
assign $0\main_sdphy_cmdr_sink_ready[0:0] 1'1
assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'100
assign $0\main_sdphy_cmdr_pads_out_payload_clk[0:0] 1'1
assign $0\main_sdphy_cmdr_source_valid[0:0] \main_sdphy_cmdr_cmdr_source_source_valid0
assign $0\main_sdphy_cmdr_source_payload_status[2:0] 3'000
- assign $0\main_sdphy_cmdr_source_last[0:0] $eq$ls180.v:4583$663_Y
+ assign $0\main_sdphy_cmdr_source_last[0:0] $eq$ls180.v:4579$663_Y
assign $0\main_sdphy_cmdr_source_payload_data[7:0] \main_sdphy_cmdr_cmdr_source_source_payload_data0
- assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] $sub$ls180.v:4600$666_Y
+ assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] $sub$ls180.v:4596$666_Y
assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] 1'1
- attribute \src "ls180.v:4585.4-4599.7"
- switch $and$ls180.v:4585$664_Y
- attribute \src "ls180.v:4585.8-4585.69"
+ attribute \src "ls180.v:4581.4-4595.7"
+ switch $and$ls180.v:4581$664_Y
+ attribute \src "ls180.v:4581.8-4581.69"
case 1'1
assign $0\main_sdphy_cmdr_cmdr_source_source_ready0[0:0] 1'1
- assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] $add$ls180.v:4587$665_Y
+ assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] $add$ls180.v:4583$665_Y
assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] 1'1
- attribute \src "ls180.v:4589.5-4598.8"
+ attribute \src "ls180.v:4585.5-4594.8"
switch \main_sdphy_cmdr_source_last
- attribute \src "ls180.v:4589.9-4589.36"
+ attribute \src "ls180.v:4585.9-4585.36"
case 1'1
assign $0\main_sdphy_cmdr_sink_ready[0:0] 1'1
- attribute \src "ls180.v:4591.6-4597.9"
+ attribute \src "ls180.v:4587.6-4593.9"
switch \main_sdphy_cmdr_sink_last
- attribute \src "ls180.v:4591.10-4591.35"
+ attribute \src "ls180.v:4587.10-4587.35"
case 1'1
assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] 8'00000000
assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] 1'1
assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'011
- attribute \src "ls180.v:4595.10-4595.14"
+ attribute \src "ls180.v:4591.10-4591.14"
case
assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'000
end
end
case
end
- attribute \src "ls180.v:4602.4-4605.7"
- switch $eq$ls180.v:4602$667_Y
- attribute \src "ls180.v:4602.8-4602.41"
+ attribute \src "ls180.v:4598.4-4601.7"
+ switch $eq$ls180.v:4598$667_Y
+ attribute \src "ls180.v:4598.8-4598.41"
case 1'1
assign $0\main_sdphy_cmdr_sink_ready[0:0] 1'1
assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'100
assign $0\main_sdphy_cmdr_pads_out_payload_clk[0:0] 1'1
assign $0\main_sdphy_cmdr_pads_out_payload_cmd_oe[0:0] 1'1
assign $0\main_sdphy_cmdr_pads_out_payload_cmd_o[0:0] 1'1
- attribute \src "ls180.v:4611.4-4617.7"
+ attribute \src "ls180.v:4607.4-4613.7"
switch \main_sdphy_cmdr_pads_out_ready
- attribute \src "ls180.v:4611.8-4611.38"
+ attribute \src "ls180.v:4607.8-4607.38"
case 1'1
- assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] $add$ls180.v:4612$668_Y
+ assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] $add$ls180.v:4608$668_Y
assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] 1'1
- attribute \src "ls180.v:4614.5-4616.8"
- switch $eq$ls180.v:4614$669_Y
- attribute \src "ls180.v:4614.9-4614.40"
+ attribute \src "ls180.v:4610.5-4612.8"
+ switch $eq$ls180.v:4610$669_Y
+ attribute \src "ls180.v:4610.9-4610.40"
case 1'1
assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'000
case
assign $0\main_sdphy_cmdr_source_valid[0:0] 1'1
assign $0\main_sdphy_cmdr_source_payload_status[2:0] 3'001
assign $0\main_sdphy_cmdr_source_last[0:0] 1'1
- attribute \src "ls180.v:4623.4-4625.7"
- switch $and$ls180.v:4623$670_Y
- attribute \src "ls180.v:4623.8-4623.69"
+ attribute \src "ls180.v:4619.4-4621.7"
+ switch $and$ls180.v:4619$670_Y
+ attribute \src "ls180.v:4619.8-4619.69"
case 1'1
assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'000
case
assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] 1'1
assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] 500000
assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] 1'1
- attribute \src "ls180.v:4632.4-4636.7"
- switch $and$ls180.v:4632$672_Y
- attribute \src "ls180.v:4632.8-4632.94"
+ attribute \src "ls180.v:4628.4-4632.7"
+ switch $and$ls180.v:4628$672_Y
+ attribute \src "ls180.v:4628.8-4628.94"
case 1'1
assign $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] 1'1
assign $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] 1'1
update \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2 $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0]
update \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2 $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0]
end
- attribute \src "ls180.v:4673.1-4700.4"
- process $proc$ls180.v:4673$680
- assign { } { }
+ attribute \src "ls180.v:4669.1-4696.4"
+ process $proc$ls180.v:4669$680
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign $0\main_sdphy_dataw_crcr_source_source_ready0[0:0] 1'0
- assign $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] 1'0
- assign $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] 1'0
assign $0\main_sdphy_dataw_error[0:0] 1'0
+ assign { } { }
+ assign $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] 1'0
assign $0\main_sdphy_dataw_valid[0:0] 1'0
+ assign $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] 1'0
assign $0\builder_sdphy_sdphycrcr_next_state[0:0] \builder_sdphy_sdphycrcr_state
- attribute \src "ls180.v:4681.2-4699.9"
+ attribute \src "ls180.v:4677.2-4695.9"
switch \builder_sdphy_sdphycrcr_state
attribute \src "ls180.v:0.0-0.0"
case 1'1
assign $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] 1'0
assign $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] 1'1
assign $0\main_sdphy_dataw_crcr_source_source_ready0[0:0] 1'1
- attribute \src "ls180.v:4686.4-4690.7"
+ attribute \src "ls180.v:4682.4-4686.7"
switch \main_sdphy_dataw_crcr_source_source_valid0
- attribute \src "ls180.v:4686.8-4686.50"
+ attribute \src "ls180.v:4682.8-4682.50"
case 1'1
- assign $0\main_sdphy_dataw_valid[0:0] $ne$ls180.v:4687$681_Y
- assign $0\main_sdphy_dataw_error[0:0] $eq$ls180.v:4688$682_Y
+ assign $0\main_sdphy_dataw_valid[0:0] $ne$ls180.v:4683$681_Y
+ assign $0\main_sdphy_dataw_error[0:0] $eq$ls180.v:4684$682_Y
assign $0\builder_sdphy_sdphycrcr_next_state[0:0] 1'0
case
end
attribute \src "ls180.v:0.0-0.0"
case
- attribute \src "ls180.v:4693.4-4697.7"
+ attribute \src "ls180.v:4689.4-4693.7"
switch \main_sdphy_dataw_start
- attribute \src "ls180.v:4693.8-4693.30"
+ attribute \src "ls180.v:4689.8-4689.30"
case 1'1
assign $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] 1'1
assign $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] 1'1
update \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0]
update \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0]
end
- attribute \src "ls180.v:4701.1-4773.4"
- process $proc$ls180.v:4701$683
+ attribute \src "ls180.v:469.5-469.59"
+ process $proc$ls180.v:469$2913
assign { } { }
+ assign $1\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] 1'0
+ sync always
+ sync init
+ update \main_sdram_bankmachine0_cmd_buffer_source_valid $1\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0]
+ end
+ attribute \src "ls180.v:4697.1-4769.4"
+ process $proc$ls180.v:4697$683
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
+ assign { } { }
+ assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] 1'0
assign $0\main_sdphy_dataw_pads_out_payload_clk[0:0] 1'0
assign $0\main_sdphy_dataw_pads_out_payload_data_o[3:0] 4'0000
assign $0\main_sdphy_dataw_pads_out_payload_data_oe[0:0] 1'0
assign $0\main_sdphy_dataw_sink_ready[0:0] 1'0
assign $0\main_sdphy_dataw_start[0:0] 1'0
+ assign $0\main_sdphy_dataw_stop[0:0] 1'0
assign { } { }
assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] 8'00000000
- assign $0\main_sdphy_dataw_stop[0:0] 1'0
- assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] 1'0
assign $0\builder_sdphy_fsm_next_state[2:0] \builder_sdphy_fsm_state
- attribute \src "ls180.v:4712.2-4772.9"
+ attribute \src "ls180.v:4708.2-4768.9"
switch \builder_sdphy_fsm_state
attribute \src "ls180.v:0.0-0.0"
case 3'001
assign $0\main_sdphy_dataw_pads_out_payload_clk[0:0] 1'1
assign $0\main_sdphy_dataw_pads_out_payload_data_oe[0:0] 1'1
assign $0\main_sdphy_dataw_pads_out_payload_data_o[3:0] 4'0000
- attribute \src "ls180.v:4717.4-4719.7"
+ attribute \src "ls180.v:4713.4-4715.7"
switch \main_sdphy_dataw_pads_out_ready
- attribute \src "ls180.v:4717.8-4717.39"
+ attribute \src "ls180.v:4713.8-4713.39"
case 1'1
assign $0\builder_sdphy_fsm_next_state[2:0] 3'010
case
end
attribute \src "ls180.v:0.0-0.0"
case 3'010
- assign $0\main_sdphy_dataw_stop[0:0] $not$ls180.v:4722$684_Y
+ assign $0\main_sdphy_dataw_stop[0:0] $not$ls180.v:4718$684_Y
assign $0\main_sdphy_dataw_pads_out_payload_clk[0:0] 1'1
assign $0\main_sdphy_dataw_pads_out_payload_data_oe[0:0] 1'1
- attribute \src "ls180.v:4725.4-4732.11"
+ attribute \src "ls180.v:4721.4-4728.11"
switch \main_sdphy_dataw_count
attribute \src "ls180.v:0.0-0.0"
case 8'00000000
assign $0\main_sdphy_dataw_pads_out_payload_data_o[3:0] \main_sdphy_dataw_sink_payload_data [3:0]
case
end
- attribute \src "ls180.v:4733.4-4745.7"
+ attribute \src "ls180.v:4729.4-4741.7"
switch \main_sdphy_dataw_pads_out_ready
- attribute \src "ls180.v:4733.8-4733.39"
+ attribute \src "ls180.v:4729.8-4729.39"
case 1'1
- assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] $add$ls180.v:4734$685_Y
+ assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] $add$ls180.v:4730$685_Y
assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] 1'1
- attribute \src "ls180.v:4736.5-4744.8"
- switch $eq$ls180.v:4736$686_Y
- attribute \src "ls180.v:4736.9-4736.41"
+ attribute \src "ls180.v:4732.5-4740.8"
+ switch $eq$ls180.v:4732$686_Y
+ attribute \src "ls180.v:4732.9-4732.41"
case 1'1
assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] 8'00000000
assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] 1'1
- attribute \src "ls180.v:4739.6-4743.9"
+ attribute \src "ls180.v:4735.6-4739.9"
switch \main_sdphy_dataw_sink_last
- attribute \src "ls180.v:4739.10-4739.36"
+ attribute \src "ls180.v:4735.10-4735.36"
case 1'1
assign $0\builder_sdphy_fsm_next_state[2:0] 3'011
- attribute \src "ls180.v:4741.10-4741.14"
+ attribute \src "ls180.v:4737.10-4737.14"
case
assign $0\main_sdphy_dataw_sink_ready[0:0] 1'1
end
assign $0\main_sdphy_dataw_pads_out_payload_clk[0:0] 1'1
assign $0\main_sdphy_dataw_pads_out_payload_data_oe[0:0] 1'1
assign $0\main_sdphy_dataw_pads_out_payload_data_o[3:0] 4'1111
- attribute \src "ls180.v:4751.4-4754.7"
+ attribute \src "ls180.v:4747.4-4750.7"
switch \main_sdphy_dataw_pads_out_ready
- attribute \src "ls180.v:4751.8-4751.39"
+ attribute \src "ls180.v:4747.8-4747.39"
case 1'1
assign $0\main_sdphy_dataw_start[0:0] 1'1
assign $0\builder_sdphy_fsm_next_state[2:0] 3'100
attribute \src "ls180.v:0.0-0.0"
case 3'100
assign $0\main_sdphy_dataw_pads_out_payload_clk[0:0] 1'1
- attribute \src "ls180.v:4758.4-4763.7"
+ attribute \src "ls180.v:4754.4-4759.7"
switch \main_sdphy_dataw_pads_out_ready
- attribute \src "ls180.v:4758.8-4758.39"
+ attribute \src "ls180.v:4754.8-4754.39"
case 1'1
- attribute \src "ls180.v:4759.5-4762.8"
+ attribute \src "ls180.v:4755.5-4758.8"
switch \main_sdphy_dataw_pads_in_payload_data_i [0]
- attribute \src "ls180.v:4759.9-4759.51"
+ attribute \src "ls180.v:4755.9-4755.51"
case 1'1
assign $0\main_sdphy_dataw_sink_ready[0:0] 1'1
assign $0\builder_sdphy_fsm_next_state[2:0] 3'000
case
assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] 8'00000000
assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] 1'1
- attribute \src "ls180.v:4768.4-4770.7"
- switch $and$ls180.v:4768$687_Y
- attribute \src "ls180.v:4768.8-4768.71"
+ attribute \src "ls180.v:4764.4-4766.7"
+ switch $and$ls180.v:4764$687_Y
+ attribute \src "ls180.v:4764.8-4764.71"
case 1'1
assign $0\builder_sdphy_fsm_next_state[2:0] 3'001
case
update \main_sdphy_dataw_count_sdphy_fsm_next_value $0\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0]
update \main_sdphy_dataw_count_sdphy_fsm_next_value_ce $0\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0]
end
- attribute \src "ls180.v:473.5-473.59"
- process $proc$ls180.v:473$2913
- assign { } { }
- assign $1\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] 1'0
- sync always
- sync init
- update \main_sdram_bankmachine0_cmd_buffer_source_valid $1\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0]
- end
- attribute \src "ls180.v:475.5-475.59"
- process $proc$ls180.v:475$2914
+ attribute \src "ls180.v:471.5-471.59"
+ process $proc$ls180.v:471$2914
assign { } { }
assign $1\main_sdram_bankmachine0_cmd_buffer_source_first[0:0] 1'0
sync always
sync init
update \main_sdram_bankmachine0_cmd_buffer_source_first $1\main_sdram_bankmachine0_cmd_buffer_source_first[0:0]
end
- attribute \src "ls180.v:476.5-476.58"
- process $proc$ls180.v:476$2915
+ attribute \src "ls180.v:472.5-472.58"
+ process $proc$ls180.v:472$2915
assign { } { }
assign $1\main_sdram_bankmachine0_cmd_buffer_source_last[0:0] 1'0
sync always
sync init
update \main_sdram_bankmachine0_cmd_buffer_source_last $1\main_sdram_bankmachine0_cmd_buffer_source_last[0:0]
end
- attribute \src "ls180.v:477.5-477.64"
- process $proc$ls180.v:477$2916
+ attribute \src "ls180.v:473.5-473.64"
+ process $proc$ls180.v:473$2916
assign { } { }
assign $1\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] 1'0
sync always
sync init
update \main_sdram_bankmachine0_cmd_buffer_source_payload_we $1\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0]
end
- attribute \src "ls180.v:478.12-478.74"
- process $proc$ls180.v:478$2917
+ attribute \src "ls180.v:474.12-474.74"
+ process $proc$ls180.v:474$2917
assign { } { }
assign $1\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000
sync always
sync init
update \main_sdram_bankmachine0_cmd_buffer_source_payload_addr $1\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0]
end
- attribute \src "ls180.v:479.12-479.47"
- process $proc$ls180.v:479$2918
+ attribute \src "ls180.v:475.12-475.47"
+ process $proc$ls180.v:475$2918
assign { } { }
assign $1\main_sdram_bankmachine0_row[12:0] 13'0000000000000
sync always
sync init
update \main_sdram_bankmachine0_row $1\main_sdram_bankmachine0_row[12:0]
end
- attribute \src "ls180.v:480.5-480.46"
- process $proc$ls180.v:480$2919
+ attribute \src "ls180.v:476.5-476.46"
+ process $proc$ls180.v:476$2919
assign { } { }
assign $1\main_sdram_bankmachine0_row_opened[0:0] 1'0
sync always
sync init
update \main_sdram_bankmachine0_row_opened $1\main_sdram_bankmachine0_row_opened[0:0]
end
- attribute \src "ls180.v:4807.1-4908.4"
- process $proc$ls180.v:4807$695
+ attribute \src "ls180.v:478.5-478.44"
+ process $proc$ls180.v:478$2920
assign { } { }
+ assign $1\main_sdram_bankmachine0_row_open[0:0] 1'0
+ sync always
+ sync init
+ update \main_sdram_bankmachine0_row_open $1\main_sdram_bankmachine0_row_open[0:0]
+ end
+ attribute \src "ls180.v:479.5-479.45"
+ process $proc$ls180.v:479$2921
assign { } { }
+ assign $1\main_sdram_bankmachine0_row_close[0:0] 1'0
+ sync always
+ sync init
+ update \main_sdram_bankmachine0_row_close $1\main_sdram_bankmachine0_row_close[0:0]
+ end
+ attribute \src "ls180.v:480.5-480.54"
+ process $proc$ls180.v:480$2922
+ assign { } { }
+ assign $1\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] 1'0
+ sync always
+ sync init
+ update \main_sdram_bankmachine0_row_col_n_addr_sel $1\main_sdram_bankmachine0_row_col_n_addr_sel[0:0]
+ end
+ attribute \src "ls180.v:4803.1-4904.4"
+ process $proc$ls180.v:4803$695
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\main_sdphy_datar_source_valid[0:0] 1'0
- assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] 0
- assign $0\main_sdphy_datar_pads_out_payload_clk[0:0] 1'0
- assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] 1'0
- assign $0\main_sdphy_datar_source_payload_status[2:0] 3'000
+ assign { } { }
+ assign { } { }
+ assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'0
assign $0\main_sdphy_datar_source_last[0:0] 1'0
+ assign $0\main_sdphy_datar_pads_out_payload_clk[0:0] 1'0
assign $0\main_sdphy_datar_source_payload_data[7:0] 8'00000000
+ assign $0\main_sdphy_datar_source_payload_status[2:0] 3'000
+ assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] 0
assign $0\main_sdphy_datar_datar_source_source_ready0[0:0] 1'0
- assign $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] 1'0
+ assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] 1'0
assign $0\main_sdphy_datar_stop[0:0] 1'0
+ assign $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] 1'0
assign $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] 1'0
assign $0\main_sdphy_datar_sink_ready[0:0] 1'0
+ assign $0\main_sdphy_datar_source_valid[0:0] 1'0
assign { } { }
assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] 10'0000000000
- assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'0
assign $0\builder_sdphy_sdphydatar_next_state[2:0] \builder_sdphy_sdphydatar_state
- attribute \src "ls180.v:4824.2-4907.9"
+ attribute \src "ls180.v:4820.2-4903.9"
switch \builder_sdphy_sdphydatar_state
attribute \src "ls180.v:0.0-0.0"
case 3'001
assign $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] 1'1
assign { } { }
assign { } { }
- assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] $sub$ls180.v:4834$697_Y
+ assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] $sub$ls180.v:4830$697_Y
assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] 1'1
- attribute \src "ls180.v:4831.4-4833.7"
+ attribute \src "ls180.v:4827.4-4829.7"
switch \main_sdphy_datar_datar_source_source_valid0
- attribute \src "ls180.v:4831.8-4831.51"
+ attribute \src "ls180.v:4827.8-4827.51"
case 1'1
assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'010
case
end
- attribute \src "ls180.v:4836.4-4839.7"
- switch $eq$ls180.v:4836$698_Y
- attribute \src "ls180.v:4836.8-4836.42"
+ attribute \src "ls180.v:4832.4-4835.7"
+ switch $eq$ls180.v:4832$698_Y
+ attribute \src "ls180.v:4832.8-4832.42"
case 1'1
assign $0\main_sdphy_datar_sink_ready[0:0] 1'1
assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'100
assign $0\main_sdphy_datar_pads_out_payload_clk[0:0] 1'1
assign $0\main_sdphy_datar_source_valid[0:0] \main_sdphy_datar_datar_source_source_valid0
assign $0\main_sdphy_datar_source_payload_status[2:0] 3'000
- assign $0\main_sdphy_datar_source_last[0:0] $eq$ls180.v:4845$701_Y
+ assign $0\main_sdphy_datar_source_last[0:0] $eq$ls180.v:4841$701_Y
assign $0\main_sdphy_datar_source_payload_data[7:0] \main_sdphy_datar_datar_source_source_payload_data0
- assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] $sub$ls180.v:4866$703_Y
+ assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] $sub$ls180.v:4862$703_Y
assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] 1'1
- attribute \src "ls180.v:4847.4-4865.7"
+ attribute \src "ls180.v:4843.4-4861.7"
switch \main_sdphy_datar_source_valid
- attribute \src "ls180.v:4847.8-4847.37"
+ attribute \src "ls180.v:4843.8-4843.37"
case 1'1
- attribute \src "ls180.v:4848.5-4864.8"
+ attribute \src "ls180.v:4844.5-4860.8"
switch \main_sdphy_datar_source_ready
- attribute \src "ls180.v:4848.9-4848.38"
+ attribute \src "ls180.v:4844.9-4844.38"
case 1'1
assign $0\main_sdphy_datar_datar_source_source_ready0[0:0] 1'1
- assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] $add$ls180.v:4850$702_Y
+ assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] $add$ls180.v:4846$702_Y
assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'1
- attribute \src "ls180.v:4852.6-4861.9"
+ attribute \src "ls180.v:4848.6-4857.9"
switch \main_sdphy_datar_source_last
- attribute \src "ls180.v:4852.10-4852.38"
+ attribute \src "ls180.v:4848.10-4848.38"
case 1'1
assign $0\main_sdphy_datar_sink_ready[0:0] 1'1
- attribute \src "ls180.v:4854.7-4860.10"
+ attribute \src "ls180.v:4850.7-4856.10"
switch \main_sdphy_datar_sink_last
- attribute \src "ls180.v:4854.11-4854.37"
+ attribute \src "ls180.v:4850.11-4850.37"
case 1'1
assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] 10'0000000000
assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'1
assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'011
- attribute \src "ls180.v:4858.11-4858.15"
+ attribute \src "ls180.v:4854.11-4854.15"
case
assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'000
end
case
end
- attribute \src "ls180.v:4862.9-4862.13"
+ attribute \src "ls180.v:4858.9-4858.13"
case
assign $0\main_sdphy_datar_stop[0:0] 1'1
end
case
end
- attribute \src "ls180.v:4868.4-4871.7"
- switch $eq$ls180.v:4868$704_Y
- attribute \src "ls180.v:4868.8-4868.42"
+ attribute \src "ls180.v:4864.4-4867.7"
+ switch $eq$ls180.v:4864$704_Y
+ attribute \src "ls180.v:4864.8-4864.42"
case 1'1
assign $0\main_sdphy_datar_sink_ready[0:0] 1'1
assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'100
attribute \src "ls180.v:0.0-0.0"
case 3'011
assign $0\main_sdphy_datar_pads_out_payload_clk[0:0] 1'1
- attribute \src "ls180.v:4875.4-4881.7"
+ attribute \src "ls180.v:4871.4-4877.7"
switch \main_sdphy_datar_pads_out_ready
- attribute \src "ls180.v:4875.8-4875.39"
+ attribute \src "ls180.v:4871.8-4871.39"
case 1'1
- assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] $add$ls180.v:4876$705_Y
+ assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] $add$ls180.v:4872$705_Y
assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'1
- attribute \src "ls180.v:4878.5-4880.8"
- switch $eq$ls180.v:4878$706_Y
- attribute \src "ls180.v:4878.9-4878.42"
+ attribute \src "ls180.v:4874.5-4876.8"
+ switch $eq$ls180.v:4874$706_Y
+ attribute \src "ls180.v:4874.9-4874.42"
case 1'1
assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'000
case
assign $0\main_sdphy_datar_source_valid[0:0] 1'1
assign $0\main_sdphy_datar_source_payload_status[2:0] 3'001
assign $0\main_sdphy_datar_source_last[0:0] 1'1
- attribute \src "ls180.v:4887.4-4889.7"
- switch $and$ls180.v:4887$707_Y
- attribute \src "ls180.v:4887.8-4887.71"
+ attribute \src "ls180.v:4883.4-4885.7"
+ switch $and$ls180.v:4883$707_Y
+ attribute \src "ls180.v:4883.8-4883.71"
case 1'1
assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'000
case
case
assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] 10'0000000000
assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'1
- attribute \src "ls180.v:4894.4-4905.7"
- switch $and$ls180.v:4894$708_Y
- attribute \src "ls180.v:4894.8-4894.71"
+ attribute \src "ls180.v:4890.4-4901.7"
+ switch $and$ls180.v:4890$708_Y
+ attribute \src "ls180.v:4890.8-4890.71"
case 1'1
assign $0\main_sdphy_datar_pads_out_payload_clk[0:0] 1'1
- attribute \src "ls180.v:4896.5-4904.8"
+ attribute \src "ls180.v:4892.5-4900.8"
switch \main_sdphy_datar_pads_out_ready
- attribute \src "ls180.v:4896.9-4896.40"
+ attribute \src "ls180.v:4892.9-4892.40"
case 1'1
assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] 500000
assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] 1'1
update \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2 $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0]
update \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2 $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0]
end
- attribute \src "ls180.v:482.5-482.44"
- process $proc$ls180.v:482$2920
+ attribute \src "ls180.v:482.32-482.76"
+ process $proc$ls180.v:482$2923
assign { } { }
- assign $1\main_sdram_bankmachine0_row_open[0:0] 1'0
+ assign $1\main_sdram_bankmachine0_twtpcon_ready[0:0] 1'0
sync always
sync init
- update \main_sdram_bankmachine0_row_open $1\main_sdram_bankmachine0_row_open[0:0]
+ update \main_sdram_bankmachine0_twtpcon_ready $1\main_sdram_bankmachine0_twtpcon_ready[0:0]
end
- attribute \src "ls180.v:483.5-483.45"
- process $proc$ls180.v:483$2921
+ attribute \src "ls180.v:483.11-483.55"
+ process $proc$ls180.v:483$2924
assign { } { }
- assign $1\main_sdram_bankmachine0_row_close[0:0] 1'0
+ assign $1\main_sdram_bankmachine0_twtpcon_count[2:0] 3'000
sync always
sync init
- update \main_sdram_bankmachine0_row_close $1\main_sdram_bankmachine0_row_close[0:0]
+ update \main_sdram_bankmachine0_twtpcon_count $1\main_sdram_bankmachine0_twtpcon_count[2:0]
end
- attribute \src "ls180.v:484.5-484.54"
- process $proc$ls180.v:484$2922
+ attribute \src "ls180.v:485.32-485.75"
+ process $proc$ls180.v:485$2925
assign { } { }
- assign $1\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] 1'0
+ assign $0\main_sdram_bankmachine0_trccon_ready[0:0] 1'1
sync always
+ update \main_sdram_bankmachine0_trccon_ready $0\main_sdram_bankmachine0_trccon_ready[0:0]
sync init
- update \main_sdram_bankmachine0_row_col_n_addr_sel $1\main_sdram_bankmachine0_row_col_n_addr_sel[0:0]
end
- attribute \src "ls180.v:486.32-486.76"
- process $proc$ls180.v:486$2923
+ attribute \src "ls180.v:487.32-487.76"
+ process $proc$ls180.v:487$2926
assign { } { }
- assign $1\main_sdram_bankmachine0_twtpcon_ready[0:0] 1'0
+ assign $0\main_sdram_bankmachine0_trascon_ready[0:0] 1'1
sync always
+ update \main_sdram_bankmachine0_trascon_ready $0\main_sdram_bankmachine0_trascon_ready[0:0]
sync init
- update \main_sdram_bankmachine0_twtpcon_ready $1\main_sdram_bankmachine0_twtpcon_ready[0:0]
end
- attribute \src "ls180.v:487.11-487.55"
- process $proc$ls180.v:487$2924
+ attribute \src "ls180.v:493.5-493.51"
+ process $proc$ls180.v:493$2927
assign { } { }
- assign $1\main_sdram_bankmachine0_twtpcon_count[2:0] 3'000
+ assign $1\main_sdram_bankmachine1_req_wdata_ready[0:0] 1'0
sync always
sync init
- update \main_sdram_bankmachine0_twtpcon_count $1\main_sdram_bankmachine0_twtpcon_count[2:0]
+ update \main_sdram_bankmachine1_req_wdata_ready $1\main_sdram_bankmachine1_req_wdata_ready[0:0]
end
- attribute \src "ls180.v:489.32-489.75"
- process $proc$ls180.v:489$2925
+ attribute \src "ls180.v:494.5-494.51"
+ process $proc$ls180.v:494$2928
assign { } { }
- assign $0\main_sdram_bankmachine0_trccon_ready[0:0] 1'1
+ assign $1\main_sdram_bankmachine1_req_rdata_valid[0:0] 1'0
sync always
- update \main_sdram_bankmachine0_trccon_ready $0\main_sdram_bankmachine0_trccon_ready[0:0]
sync init
+ update \main_sdram_bankmachine1_req_rdata_valid $1\main_sdram_bankmachine1_req_rdata_valid[0:0]
end
- attribute \src "ls180.v:491.32-491.76"
- process $proc$ls180.v:491$2926
+ attribute \src "ls180.v:496.5-496.47"
+ process $proc$ls180.v:496$2929
assign { } { }
- assign $0\main_sdram_bankmachine0_trascon_ready[0:0] 1'1
+ assign $1\main_sdram_bankmachine1_refresh_gnt[0:0] 1'0
sync always
- update \main_sdram_bankmachine0_trascon_ready $0\main_sdram_bankmachine0_trascon_ready[0:0]
sync init
+ update \main_sdram_bankmachine1_refresh_gnt $1\main_sdram_bankmachine1_refresh_gnt[0:0]
end
- attribute \src "ls180.v:4966.1-4973.4"
- process $proc$ls180.v:4966$830
+ attribute \src "ls180.v:4962.1-4969.4"
+ process $proc$ls180.v:4962$830
assign { } { }
assign $0\main_sdcore_crc7_inserter_crc[6:0] 7'0000000
- attribute \src "ls180.v:4968.2-4972.5"
+ attribute \src "ls180.v:4964.2-4968.5"
switch \main_sdcore_crc7_inserter_enable
- attribute \src "ls180.v:4968.6-4968.38"
+ attribute \src "ls180.v:4964.6-4964.38"
case 1'1
assign $0\main_sdcore_crc7_inserter_crc[6:0] \main_sdcore_crc7_inserter_crcreg40
- attribute \src "ls180.v:4970.6-4970.10"
+ attribute \src "ls180.v:4966.6-4966.10"
case
assign $0\main_sdcore_crc7_inserter_crc[6:0] \main_sdcore_crc7_inserter_crcreg0
end
sync always
update \main_sdcore_crc7_inserter_crc $0\main_sdcore_crc7_inserter_crc[6:0]
end
- attribute \src "ls180.v:497.5-497.51"
- process $proc$ls180.v:497$2927
+ attribute \src "ls180.v:497.5-497.45"
+ process $proc$ls180.v:497$2930
assign { } { }
- assign $1\main_sdram_bankmachine1_req_wdata_ready[0:0] 1'0
+ assign $1\main_sdram_bankmachine1_cmd_valid[0:0] 1'0
sync always
sync init
- update \main_sdram_bankmachine1_req_wdata_ready $1\main_sdram_bankmachine1_req_wdata_ready[0:0]
+ update \main_sdram_bankmachine1_cmd_valid $1\main_sdram_bankmachine1_cmd_valid[0:0]
end
- attribute \src "ls180.v:498.5-498.51"
- process $proc$ls180.v:498$2928
+ attribute \src "ls180.v:498.5-498.45"
+ process $proc$ls180.v:498$2931
assign { } { }
- assign $1\main_sdram_bankmachine1_req_rdata_valid[0:0] 1'0
+ assign $1\main_sdram_bankmachine1_cmd_ready[0:0] 1'0
sync always
sync init
- update \main_sdram_bankmachine1_req_rdata_valid $1\main_sdram_bankmachine1_req_rdata_valid[0:0]
+ update \main_sdram_bankmachine1_cmd_ready $1\main_sdram_bankmachine1_cmd_ready[0:0]
end
- attribute \src "ls180.v:4988.1-4995.4"
- process $proc$ls180.v:4988$853
+ attribute \src "ls180.v:4984.1-4991.4"
+ process $proc$ls180.v:4984$853
assign { } { }
assign $0\main_sdcore_crc16_inserter_crc0_crc[15:0] 16'0000000000000000
- attribute \src "ls180.v:4990.2-4994.5"
+ attribute \src "ls180.v:4986.2-4990.5"
switch \main_sdcore_crc16_inserter_crc0_enable
- attribute \src "ls180.v:4990.6-4990.44"
+ attribute \src "ls180.v:4986.6-4986.44"
case 1'1
assign $0\main_sdcore_crc16_inserter_crc0_crc[15:0] \main_sdcore_crc16_inserter_crc0_crcreg2
- attribute \src "ls180.v:4992.6-4992.10"
+ attribute \src "ls180.v:4988.6-4988.10"
case
assign $0\main_sdcore_crc16_inserter_crc0_crc[15:0] \main_sdcore_crc16_inserter_crc0_crcreg0
end
sync always
update \main_sdcore_crc16_inserter_crc0_crc $0\main_sdcore_crc16_inserter_crc0_crc[15:0]
end
- attribute \src "ls180.v:4998.1-5005.4"
- process $proc$ls180.v:4998$864
+ attribute \src "ls180.v:499.12-499.57"
+ process $proc$ls180.v:499$2932
+ assign { } { }
+ assign $1\main_sdram_bankmachine1_cmd_payload_a[12:0] 13'0000000000000
+ sync always
+ sync init
+ update \main_sdram_bankmachine1_cmd_payload_a $1\main_sdram_bankmachine1_cmd_payload_a[12:0]
+ end
+ attribute \src "ls180.v:4994.1-5001.4"
+ process $proc$ls180.v:4994$864
assign { } { }
assign $0\main_sdcore_crc16_inserter_crc1_crc[15:0] 16'0000000000000000
- attribute \src "ls180.v:5000.2-5004.5"
+ attribute \src "ls180.v:4996.2-5000.5"
switch \main_sdcore_crc16_inserter_crc1_enable
- attribute \src "ls180.v:5000.6-5000.44"
+ attribute \src "ls180.v:4996.6-4996.44"
case 1'1
assign $0\main_sdcore_crc16_inserter_crc1_crc[15:0] \main_sdcore_crc16_inserter_crc1_crcreg2
- attribute \src "ls180.v:5002.6-5002.10"
+ attribute \src "ls180.v:4998.6-4998.10"
case
assign $0\main_sdcore_crc16_inserter_crc1_crc[15:0] \main_sdcore_crc16_inserter_crc1_crcreg0
end
sync always
update \main_sdcore_crc16_inserter_crc1_crc $0\main_sdcore_crc16_inserter_crc1_crc[15:0]
end
- attribute \src "ls180.v:500.5-500.47"
- process $proc$ls180.v:500$2929
- assign { } { }
- assign $1\main_sdram_bankmachine1_refresh_gnt[0:0] 1'0
- sync always
- sync init
- update \main_sdram_bankmachine1_refresh_gnt $1\main_sdram_bankmachine1_refresh_gnt[0:0]
- end
- attribute \src "ls180.v:5008.1-5015.4"
- process $proc$ls180.v:5008$875
+ attribute \src "ls180.v:5004.1-5011.4"
+ process $proc$ls180.v:5004$875
assign { } { }
assign $0\main_sdcore_crc16_inserter_crc2_crc[15:0] 16'0000000000000000
- attribute \src "ls180.v:5010.2-5014.5"
+ attribute \src "ls180.v:5006.2-5010.5"
switch \main_sdcore_crc16_inserter_crc2_enable
- attribute \src "ls180.v:5010.6-5010.44"
+ attribute \src "ls180.v:5006.6-5006.44"
case 1'1
assign $0\main_sdcore_crc16_inserter_crc2_crc[15:0] \main_sdcore_crc16_inserter_crc2_crcreg2
- attribute \src "ls180.v:5012.6-5012.10"
+ attribute \src "ls180.v:5008.6-5008.10"
case
assign $0\main_sdcore_crc16_inserter_crc2_crc[15:0] \main_sdcore_crc16_inserter_crc2_crcreg0
end
sync always
update \main_sdcore_crc16_inserter_crc2_crc $0\main_sdcore_crc16_inserter_crc2_crc[15:0]
end
- attribute \src "ls180.v:501.5-501.45"
- process $proc$ls180.v:501$2930
+ attribute \src "ls180.v:501.5-501.51"
+ process $proc$ls180.v:501$2933
assign { } { }
- assign $1\main_sdram_bankmachine1_cmd_valid[0:0] 1'0
+ assign $1\main_sdram_bankmachine1_cmd_payload_cas[0:0] 1'0
sync always
sync init
- update \main_sdram_bankmachine1_cmd_valid $1\main_sdram_bankmachine1_cmd_valid[0:0]
+ update \main_sdram_bankmachine1_cmd_payload_cas $1\main_sdram_bankmachine1_cmd_payload_cas[0:0]
end
- attribute \src "ls180.v:5018.1-5025.4"
- process $proc$ls180.v:5018$886
+ attribute \src "ls180.v:5014.1-5021.4"
+ process $proc$ls180.v:5014$886
assign { } { }
assign $0\main_sdcore_crc16_inserter_crc3_crc[15:0] 16'0000000000000000
- attribute \src "ls180.v:5020.2-5024.5"
+ attribute \src "ls180.v:5016.2-5020.5"
switch \main_sdcore_crc16_inserter_crc3_enable
- attribute \src "ls180.v:5020.6-5020.44"
+ attribute \src "ls180.v:5016.6-5016.44"
case 1'1
assign $0\main_sdcore_crc16_inserter_crc3_crc[15:0] \main_sdcore_crc16_inserter_crc3_crcreg2
- attribute \src "ls180.v:5022.6-5022.10"
+ attribute \src "ls180.v:5018.6-5018.10"
case
assign $0\main_sdcore_crc16_inserter_crc3_crc[15:0] \main_sdcore_crc16_inserter_crc3_crcreg0
end
sync always
update \main_sdcore_crc16_inserter_crc3_crc $0\main_sdcore_crc16_inserter_crc3_crc[15:0]
end
- attribute \src "ls180.v:502.5-502.45"
- process $proc$ls180.v:502$2931
+ attribute \src "ls180.v:502.5-502.51"
+ process $proc$ls180.v:502$2934
assign { } { }
- assign $1\main_sdram_bankmachine1_cmd_ready[0:0] 1'0
+ assign $1\main_sdram_bankmachine1_cmd_payload_ras[0:0] 1'0
sync always
sync init
- update \main_sdram_bankmachine1_cmd_ready $1\main_sdram_bankmachine1_cmd_ready[0:0]
+ update \main_sdram_bankmachine1_cmd_payload_ras $1\main_sdram_bankmachine1_cmd_payload_ras[0:0]
end
- attribute \src "ls180.v:5026.1-5105.4"
- process $proc$ls180.v:5026$887
+ attribute \src "ls180.v:5022.1-5101.4"
+ process $proc$ls180.v:5022$887
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
+ assign $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0] 16'0000000000000000
+ assign $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0] 1'0
assign $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] 16'0000000000000000
assign $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] 1'0
+ assign $0\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0] 1'0
assign $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] 3'000
- assign $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] 1'0
assign $0\main_sdcore_crc16_inserter_sink_ready[0:0] 1'0
- assign $0\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0] 16'0000000000000000
+ assign $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] 1'0
assign { } { }
assign $0\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0] 16'0000000000000000
- assign $0\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0] 1'0
assign $0\main_sdcore_crc16_inserter_source_valid[0:0] 1'0
- assign $0\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0] 1'0
- assign $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0] 16'0000000000000000
+ assign $0\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0] 1'0
+ assign $0\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0] 16'0000000000000000
assign $0\main_sdcore_crc16_inserter_source_last[0:0] 1'0
- assign $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0] 1'0
assign $0\main_sdcore_crc16_inserter_source_payload_data[7:0] 8'00000000
assign $0\builder_sdcore_crcupstreaminserter_next_state[0:0] \builder_sdcore_crcupstreaminserter_state
- attribute \src "ls180.v:5043.2-5104.9"
+ attribute \src "ls180.v:5039.2-5100.9"
switch \builder_sdcore_crcupstreaminserter_state
attribute \src "ls180.v:0.0-0.0"
case 1'1
assign $0\main_sdcore_crc16_inserter_sink_ready[0:0] 1'0
assign $0\main_sdcore_crc16_inserter_source_valid[0:0] 1'1
- attribute \src "ls180.v:5047.4-5049.7"
- switch $eq$ls180.v:5047$888_Y
- attribute \src "ls180.v:5047.8-5047.48"
+ attribute \src "ls180.v:5043.4-5045.7"
+ switch $eq$ls180.v:5043$888_Y
+ attribute \src "ls180.v:5043.8-5043.48"
case 1'1
assign $0\main_sdcore_crc16_inserter_source_last[0:0] 1'1
case
end
- attribute \src "ls180.v:5050.4-5075.11"
+ attribute \src "ls180.v:5046.4-5071.11"
switch \main_sdcore_crc16_inserter_cnt
attribute \src "ls180.v:0.0-0.0"
case 3'000
assign $0\main_sdcore_crc16_inserter_source_payload_data[7:0] { \main_sdcore_crc16_inserter_crctmp3 [1] \main_sdcore_crc16_inserter_crctmp2 [1] \main_sdcore_crc16_inserter_crctmp1 [1] \main_sdcore_crc16_inserter_crctmp0 [1] \main_sdcore_crc16_inserter_crctmp3 [0] \main_sdcore_crc16_inserter_crctmp2 [0] \main_sdcore_crc16_inserter_crctmp1 [0] \main_sdcore_crc16_inserter_crctmp0 [0] }
case
end
- attribute \src "ls180.v:5076.4-5083.7"
+ attribute \src "ls180.v:5072.4-5079.7"
switch \main_sdcore_crc16_inserter_source_ready
- attribute \src "ls180.v:5076.8-5076.47"
+ attribute \src "ls180.v:5072.8-5072.47"
case 1'1
- attribute \src "ls180.v:5077.5-5082.8"
- switch $eq$ls180.v:5077$889_Y
- attribute \src "ls180.v:5077.9-5077.49"
+ attribute \src "ls180.v:5073.5-5078.8"
+ switch $eq$ls180.v:5073$889_Y
+ attribute \src "ls180.v:5073.9-5073.49"
case 1'1
assign $0\builder_sdcore_crcupstreaminserter_next_state[0:0] 1'0
- attribute \src "ls180.v:5079.9-5079.13"
+ attribute \src "ls180.v:5075.9-5075.13"
case
- assign $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] $add$ls180.v:5080$890_Y
+ assign $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] $add$ls180.v:5076$890_Y
assign $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] 1'1
end
case
assign $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0] 1'1
assign $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] \main_sdcore_crc16_inserter_crc3_crc
assign $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] 1'1
- attribute \src "ls180.v:5098.4-5102.7"
- switch $and$ls180.v:5098$892_Y
- attribute \src "ls180.v:5098.8-5098.128"
+ attribute \src "ls180.v:5094.4-5098.7"
+ switch $and$ls180.v:5094$892_Y
+ attribute \src "ls180.v:5094.8-5094.128"
case 1'1
assign $0\builder_sdcore_crcupstreaminserter_next_state[0:0] 1'1
assign $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] 3'000
update \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4 $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0]
update \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4 $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0]
end
- attribute \src "ls180.v:503.12-503.57"
- process $proc$ls180.v:503$2932
- assign { } { }
- assign $1\main_sdram_bankmachine1_cmd_payload_a[12:0] 13'0000000000000
- sync always
- sync init
- update \main_sdram_bankmachine1_cmd_payload_a $1\main_sdram_bankmachine1_cmd_payload_a[12:0]
- end
- attribute \src "ls180.v:505.5-505.51"
- process $proc$ls180.v:505$2933
- assign { } { }
- assign $1\main_sdram_bankmachine1_cmd_payload_cas[0:0] 1'0
- sync always
- sync init
- update \main_sdram_bankmachine1_cmd_payload_cas $1\main_sdram_bankmachine1_cmd_payload_cas[0:0]
- end
- attribute \src "ls180.v:506.5-506.51"
- process $proc$ls180.v:506$2934
- assign { } { }
- assign $1\main_sdram_bankmachine1_cmd_payload_ras[0:0] 1'0
- sync always
- sync init
- update \main_sdram_bankmachine1_cmd_payload_ras $1\main_sdram_bankmachine1_cmd_payload_ras[0:0]
- end
- attribute \src "ls180.v:507.5-507.50"
- process $proc$ls180.v:507$2935
+ attribute \src "ls180.v:503.5-503.50"
+ process $proc$ls180.v:503$2935
assign { } { }
assign $1\main_sdram_bankmachine1_cmd_payload_we[0:0] 1'0
sync always
sync init
update \main_sdram_bankmachine1_cmd_payload_we $1\main_sdram_bankmachine1_cmd_payload_we[0:0]
end
- attribute \src "ls180.v:508.5-508.54"
- process $proc$ls180.v:508$2936
+ attribute \src "ls180.v:504.5-504.54"
+ process $proc$ls180.v:504$2936
assign { } { }
assign $1\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] 1'0
sync always
sync init
update \main_sdram_bankmachine1_cmd_payload_is_cmd $1\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0]
end
- attribute \src "ls180.v:509.5-509.55"
- process $proc$ls180.v:509$2937
+ attribute \src "ls180.v:505.5-505.55"
+ process $proc$ls180.v:505$2937
assign { } { }
assign $1\main_sdram_bankmachine1_cmd_payload_is_read[0:0] 1'0
sync always
sync init
update \main_sdram_bankmachine1_cmd_payload_is_read $1\main_sdram_bankmachine1_cmd_payload_is_read[0:0]
end
- attribute \src "ls180.v:510.5-510.56"
- process $proc$ls180.v:510$2938
+ attribute \src "ls180.v:506.5-506.56"
+ process $proc$ls180.v:506$2938
assign { } { }
assign $1\main_sdram_bankmachine1_cmd_payload_is_write[0:0] 1'0
sync always
sync init
update \main_sdram_bankmachine1_cmd_payload_is_write $1\main_sdram_bankmachine1_cmd_payload_is_write[0:0]
end
- attribute \src "ls180.v:5106.1-5111.4"
- process $proc$ls180.v:5106$893
+ attribute \src "ls180.v:507.5-507.50"
+ process $proc$ls180.v:507$2939
+ assign { } { }
+ assign $1\main_sdram_bankmachine1_auto_precharge[0:0] 1'0
+ sync always
+ sync init
+ update \main_sdram_bankmachine1_auto_precharge $1\main_sdram_bankmachine1_auto_precharge[0:0]
+ end
+ attribute \src "ls180.v:510.5-510.67"
+ process $proc$ls180.v:510$2940
+ assign { } { }
+ assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first[0:0] 1'0
+ sync always
+ update \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first[0:0]
+ sync init
+ end
+ attribute \src "ls180.v:5102.1-5107.4"
+ process $proc$ls180.v:5102$893
assign { } { }
assign $0\main_sdcore_crc16_checker_valid[0:0] 1'0
- attribute \src "ls180.v:5108.2-5110.5"
- switch $and$ls180.v:5108$900_Y
- attribute \src "ls180.v:5108.6-5108.301"
+ attribute \src "ls180.v:5104.2-5106.5"
+ switch $and$ls180.v:5104$900_Y
+ attribute \src "ls180.v:5104.6-5104.301"
case 1'1
assign $0\main_sdcore_crc16_checker_valid[0:0] 1'1
case
sync always
update \main_sdcore_crc16_checker_valid $0\main_sdcore_crc16_checker_valid[0:0]
end
- attribute \src "ls180.v:511.5-511.50"
- process $proc$ls180.v:511$2939
+ attribute \src "ls180.v:511.5-511.66"
+ process $proc$ls180.v:511$2941
assign { } { }
- assign $1\main_sdram_bankmachine1_auto_precharge[0:0] 1'0
+ assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last[0:0] 1'0
sync always
+ update \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last[0:0]
sync init
- update \main_sdram_bankmachine1_auto_precharge $1\main_sdram_bankmachine1_auto_precharge[0:0]
end
- attribute \src "ls180.v:5114.1-5121.4"
- process $proc$ls180.v:5114$902
+ attribute \src "ls180.v:5110.1-5117.4"
+ process $proc$ls180.v:5110$902
assign { } { }
assign $0\main_sdcore_crc16_checker_crc0_clr[0:0] 1'0
- attribute \src "ls180.v:5116.2-5120.5"
- switch $eq$ls180.v:5116$903_Y
- attribute \src "ls180.v:5116.6-5116.45"
+ attribute \src "ls180.v:5112.2-5116.5"
+ switch $eq$ls180.v:5112$903_Y
+ attribute \src "ls180.v:5112.6-5112.45"
case 1'1
assign $0\main_sdcore_crc16_checker_crc0_clr[0:0] 1'1
- attribute \src "ls180.v:5118.6-5118.10"
+ attribute \src "ls180.v:5114.6-5114.10"
case
assign $0\main_sdcore_crc16_checker_crc0_clr[0:0] 1'0
end
sync always
update \main_sdcore_crc16_checker_crc0_clr $0\main_sdcore_crc16_checker_crc0_clr[0:0]
end
- attribute \src "ls180.v:5124.1-5131.4"
- process $proc$ls180.v:5124$905
+ attribute \src "ls180.v:5120.1-5127.4"
+ process $proc$ls180.v:5120$905
assign { } { }
assign $0\main_sdcore_crc16_checker_crc1_clr[0:0] 1'0
- attribute \src "ls180.v:5126.2-5130.5"
- switch $eq$ls180.v:5126$906_Y
- attribute \src "ls180.v:5126.6-5126.45"
+ attribute \src "ls180.v:5122.2-5126.5"
+ switch $eq$ls180.v:5122$906_Y
+ attribute \src "ls180.v:5122.6-5122.45"
case 1'1
assign $0\main_sdcore_crc16_checker_crc1_clr[0:0] 1'1
- attribute \src "ls180.v:5128.6-5128.10"
+ attribute \src "ls180.v:5124.6-5124.10"
case
assign $0\main_sdcore_crc16_checker_crc1_clr[0:0] 1'0
end
sync always
update \main_sdcore_crc16_checker_crc1_clr $0\main_sdcore_crc16_checker_crc1_clr[0:0]
end
- attribute \src "ls180.v:5134.1-5141.4"
- process $proc$ls180.v:5134$908
+ attribute \src "ls180.v:5130.1-5137.4"
+ process $proc$ls180.v:5130$908
assign { } { }
assign $0\main_sdcore_crc16_checker_crc2_clr[0:0] 1'0
- attribute \src "ls180.v:5136.2-5140.5"
- switch $eq$ls180.v:5136$909_Y
- attribute \src "ls180.v:5136.6-5136.45"
+ attribute \src "ls180.v:5132.2-5136.5"
+ switch $eq$ls180.v:5132$909_Y
+ attribute \src "ls180.v:5132.6-5132.45"
case 1'1
assign $0\main_sdcore_crc16_checker_crc2_clr[0:0] 1'1
- attribute \src "ls180.v:5138.6-5138.10"
+ attribute \src "ls180.v:5134.6-5134.10"
case
assign $0\main_sdcore_crc16_checker_crc2_clr[0:0] 1'0
end
sync always
update \main_sdcore_crc16_checker_crc2_clr $0\main_sdcore_crc16_checker_crc2_clr[0:0]
end
- attribute \src "ls180.v:514.5-514.67"
- process $proc$ls180.v:514$2940
- assign { } { }
- assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first[0:0] 1'0
- sync always
- update \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first[0:0]
- sync init
- end
- attribute \src "ls180.v:5144.1-5151.4"
- process $proc$ls180.v:5144$911
+ attribute \src "ls180.v:5140.1-5147.4"
+ process $proc$ls180.v:5140$911
assign { } { }
assign $0\main_sdcore_crc16_checker_crc3_clr[0:0] 1'0
- attribute \src "ls180.v:5146.2-5150.5"
- switch $eq$ls180.v:5146$912_Y
- attribute \src "ls180.v:5146.6-5146.45"
+ attribute \src "ls180.v:5142.2-5146.5"
+ switch $eq$ls180.v:5142$912_Y
+ attribute \src "ls180.v:5142.6-5142.45"
case 1'1
assign $0\main_sdcore_crc16_checker_crc3_clr[0:0] 1'1
- attribute \src "ls180.v:5148.6-5148.10"
+ attribute \src "ls180.v:5144.6-5144.10"
case
assign $0\main_sdcore_crc16_checker_crc3_clr[0:0] 1'0
end
sync always
update \main_sdcore_crc16_checker_crc3_clr $0\main_sdcore_crc16_checker_crc3_clr[0:0]
end
- attribute \src "ls180.v:515.5-515.66"
- process $proc$ls180.v:515$2941
- assign { } { }
- assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last[0:0] 1'0
- sync always
- update \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last[0:0]
- sync init
- end
- attribute \src "ls180.v:5153.1-5158.4"
- process $proc$ls180.v:5153$913
+ attribute \src "ls180.v:5149.1-5154.4"
+ process $proc$ls180.v:5149$913
assign { } { }
assign $0\main_sdcore_crc16_checker_source_valid[0:0] 1'0
- attribute \src "ls180.v:5155.2-5157.5"
- switch $and$ls180.v:5155$915_Y
- attribute \src "ls180.v:5155.6-5155.85"
+ attribute \src "ls180.v:5151.2-5153.5"
+ switch $and$ls180.v:5151$915_Y
+ attribute \src "ls180.v:5151.6-5151.85"
case 1'1
assign $0\main_sdcore_crc16_checker_source_valid[0:0] 1'1
case
sync always
update \main_sdcore_crc16_checker_source_valid $0\main_sdcore_crc16_checker_source_valid[0:0]
end
- attribute \src "ls180.v:5159.1-5166.4"
- process $proc$ls180.v:5159$916
+ attribute \src "ls180.v:5155.1-5162.4"
+ process $proc$ls180.v:5155$916
assign { } { }
assign $0\main_sdcore_crc16_checker_sink_ready[0:0] 1'0
- attribute \src "ls180.v:5161.2-5165.5"
- switch $lt$ls180.v:5161$917_Y
- attribute \src "ls180.v:5161.6-5161.44"
+ attribute \src "ls180.v:5157.2-5161.5"
+ switch $lt$ls180.v:5157$917_Y
+ attribute \src "ls180.v:5157.6-5157.44"
case 1'1
assign $0\main_sdcore_crc16_checker_sink_ready[0:0] 1'1
- attribute \src "ls180.v:5163.6-5163.10"
+ attribute \src "ls180.v:5159.6-5159.10"
case
assign $0\main_sdcore_crc16_checker_sink_ready[0:0] \main_sdcore_crc16_checker_source_ready
end
sync always
update \main_sdcore_crc16_checker_sink_ready $0\main_sdcore_crc16_checker_sink_ready[0:0]
end
- attribute \src "ls180.v:5170.1-5177.4"
- process $proc$ls180.v:5170$928
+ attribute \src "ls180.v:5166.1-5173.4"
+ process $proc$ls180.v:5166$928
assign { } { }
assign $0\main_sdcore_crc16_checker_crc0_crc[15:0] 16'0000000000000000
- attribute \src "ls180.v:5172.2-5176.5"
+ attribute \src "ls180.v:5168.2-5172.5"
switch \main_sdcore_crc16_checker_crc0_enable
- attribute \src "ls180.v:5172.6-5172.43"
+ attribute \src "ls180.v:5168.6-5168.43"
case 1'1
assign $0\main_sdcore_crc16_checker_crc0_crc[15:0] \main_sdcore_crc16_checker_crc0_crcreg2
- attribute \src "ls180.v:5174.6-5174.10"
+ attribute \src "ls180.v:5170.6-5170.10"
case
assign $0\main_sdcore_crc16_checker_crc0_crc[15:0] \main_sdcore_crc16_checker_crc0_crcreg0
end
sync always
update \main_sdcore_crc16_checker_crc0_crc $0\main_sdcore_crc16_checker_crc0_crc[15:0]
end
- attribute \src "ls180.v:5180.1-5187.4"
- process $proc$ls180.v:5180$939
+ attribute \src "ls180.v:5176.1-5183.4"
+ process $proc$ls180.v:5176$939
assign { } { }
assign $0\main_sdcore_crc16_checker_crc1_crc[15:0] 16'0000000000000000
- attribute \src "ls180.v:5182.2-5186.5"
+ attribute \src "ls180.v:5178.2-5182.5"
switch \main_sdcore_crc16_checker_crc1_enable
- attribute \src "ls180.v:5182.6-5182.43"
+ attribute \src "ls180.v:5178.6-5178.43"
case 1'1
assign $0\main_sdcore_crc16_checker_crc1_crc[15:0] \main_sdcore_crc16_checker_crc1_crcreg2
- attribute \src "ls180.v:5184.6-5184.10"
+ attribute \src "ls180.v:5180.6-5180.10"
case
assign $0\main_sdcore_crc16_checker_crc1_crc[15:0] \main_sdcore_crc16_checker_crc1_crcreg0
end
sync always
update \main_sdcore_crc16_checker_crc1_crc $0\main_sdcore_crc16_checker_crc1_crc[15:0]
end
- attribute \src "ls180.v:5190.1-5197.4"
- process $proc$ls180.v:5190$950
+ attribute \src "ls180.v:5186.1-5193.4"
+ process $proc$ls180.v:5186$950
assign { } { }
assign $0\main_sdcore_crc16_checker_crc2_crc[15:0] 16'0000000000000000
- attribute \src "ls180.v:5192.2-5196.5"
+ attribute \src "ls180.v:5188.2-5192.5"
switch \main_sdcore_crc16_checker_crc2_enable
- attribute \src "ls180.v:5192.6-5192.43"
+ attribute \src "ls180.v:5188.6-5188.43"
case 1'1
assign $0\main_sdcore_crc16_checker_crc2_crc[15:0] \main_sdcore_crc16_checker_crc2_crcreg2
- attribute \src "ls180.v:5194.6-5194.10"
+ attribute \src "ls180.v:5190.6-5190.10"
case
assign $0\main_sdcore_crc16_checker_crc2_crc[15:0] \main_sdcore_crc16_checker_crc2_crcreg0
end
sync always
update \main_sdcore_crc16_checker_crc2_crc $0\main_sdcore_crc16_checker_crc2_crc[15:0]
end
- attribute \src "ls180.v:5200.1-5207.4"
- process $proc$ls180.v:5200$961
+ attribute \src "ls180.v:5196.1-5203.4"
+ process $proc$ls180.v:5196$961
assign { } { }
assign $0\main_sdcore_crc16_checker_crc3_crc[15:0] 16'0000000000000000
- attribute \src "ls180.v:5202.2-5206.5"
+ attribute \src "ls180.v:5198.2-5202.5"
switch \main_sdcore_crc16_checker_crc3_enable
- attribute \src "ls180.v:5202.6-5202.43"
+ attribute \src "ls180.v:5198.6-5198.43"
case 1'1
assign $0\main_sdcore_crc16_checker_crc3_crc[15:0] \main_sdcore_crc16_checker_crc3_crcreg2
- attribute \src "ls180.v:5204.6-5204.10"
+ attribute \src "ls180.v:5200.6-5200.10"
case
assign $0\main_sdcore_crc16_checker_crc3_crc[15:0] \main_sdcore_crc16_checker_crc3_crcreg0
end
sync always
update \main_sdcore_crc16_checker_crc3_crc $0\main_sdcore_crc16_checker_crc3_crc[15:0]
end
- attribute \src "ls180.v:5208.1-5398.4"
- process $proc$ls180.v:5208$962
+ attribute \src "ls180.v:5204.1-5394.4"
+ process $proc$ls180.v:5204$962
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
+ assign $0\main_sdcore_cmd_error_sdcore_fsm_next_value4[0:0] 1'0
assign $0\main_sdcore_cmd_error_sdcore_fsm_next_value_ce4[0:0] 1'0
- assign $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] 1'0
assign $0\main_sdcore_crc16_checker_sink_valid[0:0] 1'0
- assign $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] 1'0
+ assign $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] 1'0
assign $0\main_sdcore_crc16_checker_sink_first[0:0] 1'0
+ assign $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] 1'0
assign $0\main_sdcore_crc16_checker_sink_last[0:0] 1'0
- assign $0\main_sdcore_data_error_sdcore_fsm_next_value6[0:0] 1'0
assign $0\main_sdcore_crc16_checker_sink_payload_data[7:0] 8'00000000
+ assign $0\main_sdcore_data_error_sdcore_fsm_next_value6[0:0] 1'0
assign $0\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] 1'0
assign $0\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] 1'0
assign $0\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] 1'0
assign $0\main_sdcore_crc16_inserter_source_ready[0:0] 1'0
assign $0\main_sdphy_datar_sink_valid[0:0] 1'0
assign $0\main_sdphy_dataw_sink_valid[0:0] 1'0
- assign $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
assign $0\main_sdphy_dataw_sink_first[0:0] 1'0
- assign $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] 1'0
+ assign $0\main_sdphy_datar_sink_last[0:0] 1'0
assign $0\main_sdphy_dataw_sink_last[0:0] 1'0
- assign $0\main_sdphy_datar_sink_payload_block_length[9:0] 10'0000000000
+ assign $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
assign $0\main_sdphy_dataw_sink_payload_data[7:0] 8'00000000
- assign $0\main_sdphy_datar_sink_last[0:0] 1'0
+ assign $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] 1'0
assign $0\main_sdphy_cmdr_sink_valid[0:0] 1'0
assign $0\main_sdphy_datar_source_ready[0:0] 1'0
+ assign $0\main_sdphy_datar_sink_payload_block_length[9:0] 10'0000000000
assign $0\main_sdphy_cmdr_sink_last[0:0] 1'0
assign $0\main_sdphy_cmdr_sink_payload_length[7:0] 8'00000000
assign $0\main_sdphy_cmdr_source_ready[0:0] 1'0
assign $0\main_sdphy_cmdw_sink_valid[0:0] 1'0
assign { } { }
- assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] 1'0
- assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] 1'0
assign $0\main_sdphy_cmdw_sink_last[0:0] 1'0
+ assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] 1'0
assign $0\main_sdphy_cmdw_sink_payload_data[7:0] 8'00000000
+ assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] 1'0
assign $0\main_sdcore_data_done_sdcore_fsm_next_value1[0:0] 1'0
assign $0\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] 1'0
assign $0\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] 3'000
assign $0\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] 1'0
assign $0\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] 0
assign $0\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] 1'0
- assign $0\main_sdcore_cmd_error_sdcore_fsm_next_value4[0:0] 1'0
assign $0\builder_sdcore_fsm_next_state[2:0] \builder_sdcore_fsm_state
- attribute \src "ls180.v:5249.2-5397.9"
+ attribute \src "ls180.v:5245.2-5393.9"
switch \builder_sdcore_fsm_state
attribute \src "ls180.v:0.0-0.0"
case 3'001
assign $0\main_sdphy_cmdw_sink_valid[0:0] 1'1
- attribute \src "ls180.v:5252.4-5272.11"
+ attribute \src "ls180.v:5248.4-5268.11"
switch \main_sdcore_cmd_count
attribute \src "ls180.v:0.0-0.0"
case 3'000
attribute \src "ls180.v:0.0-0.0"
case 3'101
assign $0\main_sdphy_cmdw_sink_payload_data[7:0] { \main_sdcore_crc7_inserter_crc 1'1 }
- assign $0\main_sdphy_cmdw_sink_last[0:0] $eq$ls180.v:5270$963_Y
+ assign $0\main_sdphy_cmdw_sink_last[0:0] $eq$ls180.v:5266$963_Y
case
end
- attribute \src "ls180.v:5273.4-5285.7"
- switch $and$ls180.v:5273$964_Y
- attribute \src "ls180.v:5273.8-5273.65"
+ attribute \src "ls180.v:5269.4-5281.7"
+ switch $and$ls180.v:5269$964_Y
+ attribute \src "ls180.v:5269.8-5269.65"
case 1'1
- assign $0\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] $add$ls180.v:5274$965_Y
+ assign $0\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] $add$ls180.v:5270$965_Y
assign $0\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] 1'1
- attribute \src "ls180.v:5276.5-5284.8"
- switch $eq$ls180.v:5276$966_Y
- attribute \src "ls180.v:5276.9-5276.40"
+ attribute \src "ls180.v:5272.5-5280.8"
+ switch $eq$ls180.v:5272$966_Y
+ attribute \src "ls180.v:5272.9-5272.40"
case 1'1
- attribute \src "ls180.v:5277.6-5283.9"
- switch $eq$ls180.v:5277$967_Y
- attribute \src "ls180.v:5277.10-5277.40"
+ attribute \src "ls180.v:5273.6-5279.9"
+ switch $eq$ls180.v:5273$967_Y
+ attribute \src "ls180.v:5273.10-5273.40"
case 1'1
assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] 1'1
assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] 1'1
assign $0\builder_sdcore_fsm_next_state[2:0] 3'000
- attribute \src "ls180.v:5281.10-5281.14"
+ attribute \src "ls180.v:5277.10-5277.14"
case
assign $0\builder_sdcore_fsm_next_state[2:0] 3'010
end
attribute \src "ls180.v:0.0-0.0"
case 3'010
assign $0\main_sdphy_cmdr_sink_valid[0:0] 1'1
- assign $0\main_sdphy_cmdr_sink_last[0:0] $eq$ls180.v:5289$968_Y
+ assign $0\main_sdphy_cmdr_sink_last[0:0] $eq$ls180.v:5285$968_Y
assign $0\main_sdphy_cmdr_source_ready[0:0] 1'1
- attribute \src "ls180.v:5290.4-5294.7"
- switch $eq$ls180.v:5290$969_Y
- attribute \src "ls180.v:5290.8-5290.38"
+ attribute \src "ls180.v:5286.4-5290.7"
+ switch $eq$ls180.v:5286$969_Y
+ attribute \src "ls180.v:5286.8-5286.38"
case 1'1
assign $0\main_sdphy_cmdr_sink_payload_length[7:0] 8'00010001
- attribute \src "ls180.v:5292.8-5292.12"
+ attribute \src "ls180.v:5288.8-5288.12"
case
assign $0\main_sdphy_cmdr_sink_payload_length[7:0] 8'00000110
end
- attribute \src "ls180.v:5296.4-5317.7"
+ attribute \src "ls180.v:5292.4-5313.7"
switch \main_sdphy_cmdr_source_valid
- attribute \src "ls180.v:5296.8-5296.36"
+ attribute \src "ls180.v:5292.8-5292.36"
case 1'1
- attribute \src "ls180.v:5297.5-5316.8"
- switch $eq$ls180.v:5297$970_Y
- attribute \src "ls180.v:5297.9-5297.56"
+ attribute \src "ls180.v:5293.5-5312.8"
+ switch $eq$ls180.v:5293$970_Y
+ attribute \src "ls180.v:5293.9-5293.56"
case 1'1
assign $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] 1'1
assign $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] 1'1
assign $0\builder_sdcore_fsm_next_state[2:0] 3'000
- attribute \src "ls180.v:5301.9-5301.13"
+ attribute \src "ls180.v:5297.9-5297.13"
case
- attribute \src "ls180.v:5302.6-5315.9"
+ attribute \src "ls180.v:5298.6-5311.9"
switch \main_sdphy_cmdr_source_last
- attribute \src "ls180.v:5302.10-5302.37"
+ attribute \src "ls180.v:5298.10-5298.37"
case 1'1
- attribute \src "ls180.v:5303.7-5311.10"
- switch $eq$ls180.v:5303$971_Y
- attribute \src "ls180.v:5303.11-5303.42"
+ attribute \src "ls180.v:5299.7-5307.10"
+ switch $eq$ls180.v:5299$971_Y
+ attribute \src "ls180.v:5299.11-5299.42"
case 1'1
assign $0\builder_sdcore_fsm_next_state[2:0] 3'011
- attribute \src "ls180.v:5305.11-5305.15"
+ attribute \src "ls180.v:5301.11-5301.15"
case
- attribute \src "ls180.v:5306.8-5310.11"
- switch $eq$ls180.v:5306$972_Y
- attribute \src "ls180.v:5306.12-5306.43"
+ attribute \src "ls180.v:5302.8-5306.11"
+ switch $eq$ls180.v:5302$972_Y
+ attribute \src "ls180.v:5302.12-5302.43"
case 1'1
assign $0\builder_sdcore_fsm_next_state[2:0] 3'100
- attribute \src "ls180.v:5308.12-5308.16"
+ attribute \src "ls180.v:5304.12-5304.16"
case
assign $0\builder_sdcore_fsm_next_state[2:0] 3'000
end
end
- attribute \src "ls180.v:5312.10-5312.14"
+ attribute \src "ls180.v:5308.10-5308.14"
case
assign $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] { \main_sdcore_cmd_response_status [119:0] \main_sdphy_cmdr_source_payload_data }
assign $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] 1'1
assign $0\main_sdphy_dataw_sink_last[0:0] \main_sdcore_crc16_inserter_source_last
assign $0\main_sdphy_dataw_sink_payload_data[7:0] \main_sdcore_crc16_inserter_source_payload_data
assign $0\main_sdphy_datar_source_ready[0:0] 1'1
- attribute \src "ls180.v:5325.4-5331.7"
- switch $and$ls180.v:5325$974_Y
- attribute \src "ls180.v:5325.8-5325.98"
+ attribute \src "ls180.v:5321.4-5327.7"
+ switch $and$ls180.v:5321$974_Y
+ attribute \src "ls180.v:5321.8-5321.98"
case 1'1
- assign $0\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] $add$ls180.v:5326$975_Y
+ assign $0\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] $add$ls180.v:5322$975_Y
assign $0\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] 1'1
- attribute \src "ls180.v:5328.5-5330.8"
- switch $eq$ls180.v:5328$977_Y
- attribute \src "ls180.v:5328.9-5328.77"
+ attribute \src "ls180.v:5324.5-5326.8"
+ switch $eq$ls180.v:5324$977_Y
+ attribute \src "ls180.v:5324.9-5324.77"
case 1'1
assign $0\builder_sdcore_fsm_next_state[2:0] 3'000
case
end
case
end
- attribute \src "ls180.v:5333.4-5338.7"
+ attribute \src "ls180.v:5329.4-5334.7"
switch \main_sdphy_datar_source_valid
- attribute \src "ls180.v:5333.8-5333.37"
+ attribute \src "ls180.v:5329.8-5329.37"
case 1'1
- attribute \src "ls180.v:5334.5-5337.8"
- switch $ne$ls180.v:5334$978_Y
- attribute \src "ls180.v:5334.9-5334.57"
+ attribute \src "ls180.v:5330.5-5333.8"
+ switch $ne$ls180.v:5330$978_Y
+ attribute \src "ls180.v:5330.9-5330.57"
case 1'1
assign $0\main_sdcore_data_error_sdcore_fsm_next_value6[0:0] 1'1
assign $0\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] 1'1
case 3'100
assign $0\main_sdphy_datar_sink_valid[0:0] 1'1
assign $0\main_sdphy_datar_sink_payload_block_length[9:0] \main_sdcore_block_length_storage
- assign $0\main_sdphy_datar_sink_last[0:0] $eq$ls180.v:5343$980_Y
- attribute \src "ls180.v:5344.4-5370.7"
+ assign $0\main_sdphy_datar_sink_last[0:0] $eq$ls180.v:5339$980_Y
+ attribute \src "ls180.v:5340.4-5366.7"
switch \main_sdphy_datar_source_valid
- attribute \src "ls180.v:5344.8-5344.37"
+ attribute \src "ls180.v:5340.8-5340.37"
case 1'1
- attribute \src "ls180.v:5345.5-5369.8"
- switch $eq$ls180.v:5345$981_Y
- attribute \src "ls180.v:5345.9-5345.57"
+ attribute \src "ls180.v:5341.5-5365.8"
+ switch $eq$ls180.v:5341$981_Y
+ attribute \src "ls180.v:5341.9-5341.57"
case 1'1
assign $0\main_sdcore_crc16_checker_sink_valid[0:0] \main_sdphy_datar_source_valid
assign $0\main_sdphy_datar_source_ready[0:0] \main_sdcore_crc16_checker_sink_ready
assign $0\main_sdcore_crc16_checker_sink_first[0:0] \main_sdphy_datar_source_first
assign $0\main_sdcore_crc16_checker_sink_last[0:0] \main_sdphy_datar_source_last
assign $0\main_sdcore_crc16_checker_sink_payload_data[7:0] \main_sdphy_datar_source_payload_data
- attribute \src "ls180.v:5351.6-5359.9"
- switch $and$ls180.v:5351$982_Y
- attribute \src "ls180.v:5351.10-5351.72"
+ attribute \src "ls180.v:5347.6-5355.9"
+ switch $and$ls180.v:5347$982_Y
+ attribute \src "ls180.v:5347.10-5347.72"
case 1'1
- assign $0\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] $add$ls180.v:5352$983_Y
+ assign $0\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] $add$ls180.v:5348$983_Y
assign $0\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] 1'1
- attribute \src "ls180.v:5354.7-5358.10"
- switch $eq$ls180.v:5354$985_Y
- attribute \src "ls180.v:5354.11-5354.79"
+ attribute \src "ls180.v:5350.7-5354.10"
+ switch $eq$ls180.v:5350$985_Y
+ attribute \src "ls180.v:5350.11-5350.79"
case 1'1
assign $0\builder_sdcore_fsm_next_state[2:0] 3'000
- attribute \src "ls180.v:5356.11-5356.15"
+ attribute \src "ls180.v:5352.11-5352.15"
case
assign $0\builder_sdcore_fsm_next_state[2:0] 3'100
end
case
end
- attribute \src "ls180.v:5360.9-5360.13"
+ attribute \src "ls180.v:5356.9-5356.13"
case
- attribute \src "ls180.v:5361.6-5368.9"
- switch $eq$ls180.v:5361$986_Y
- attribute \src "ls180.v:5361.10-5361.58"
+ attribute \src "ls180.v:5357.6-5364.9"
+ switch $eq$ls180.v:5357$986_Y
+ attribute \src "ls180.v:5357.10-5357.58"
case 1'1
assign $0\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] 1'1
assign $0\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] 1'1
assign $0\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] 1'1
assign $0\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] 0
assign $0\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] 1'1
- attribute \src "ls180.v:5381.4-5395.7"
+ attribute \src "ls180.v:5377.4-5391.7"
switch \main_sdcore_cmd_send_re
- attribute \src "ls180.v:5381.8-5381.31"
+ attribute \src "ls180.v:5377.8-5377.31"
case 1'1
assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] 1'0
assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] 1'1
update \main_sdcore_cmd_response_status_sdcore_fsm_next_value8 $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0]
update \main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8 $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0]
end
- attribute \src "ls180.v:530.11-530.68"
- process $proc$ls180.v:530$2942
+ attribute \src "ls180.v:526.11-526.68"
+ process $proc$ls180.v:526$2942
assign { } { }
assign $1\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] 4'0000
sync always
sync init
update \main_sdram_bankmachine1_cmd_buffer_lookahead_level $1\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0]
end
- attribute \src "ls180.v:531.5-531.64"
- process $proc$ls180.v:531$2943
+ attribute \src "ls180.v:527.5-527.64"
+ process $proc$ls180.v:527$2943
assign { } { }
assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_replace[0:0] 1'0
sync always
update \main_sdram_bankmachine1_cmd_buffer_lookahead_replace $0\main_sdram_bankmachine1_cmd_buffer_lookahead_replace[0:0]
sync init
end
- attribute \src "ls180.v:532.11-532.70"
- process $proc$ls180.v:532$2944
+ attribute \src "ls180.v:528.11-528.70"
+ process $proc$ls180.v:528$2944
assign { } { }
assign $1\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] 3'000
sync always
sync init
update \main_sdram_bankmachine1_cmd_buffer_lookahead_produce $1\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0]
end
- attribute \src "ls180.v:533.11-533.70"
- process $proc$ls180.v:533$2945
+ attribute \src "ls180.v:529.11-529.70"
+ process $proc$ls180.v:529$2945
assign { } { }
assign $1\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] 3'000
sync always
sync init
update \main_sdram_bankmachine1_cmd_buffer_lookahead_consume $1\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0]
end
- attribute \src "ls180.v:534.11-534.73"
- process $proc$ls180.v:534$2946
+ attribute \src "ls180.v:530.11-530.73"
+ process $proc$ls180.v:530$2946
assign { } { }
assign $1\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] 3'000
sync always
sync init
update \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr $1\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0]
end
- attribute \src "ls180.v:5426.1-5433.4"
- process $proc$ls180.v:5426$987
+ attribute \src "ls180.v:5422.1-5429.4"
+ process $proc$ls180.v:5422$987
assign { } { }
assign $0\main_sdblock2mem_fifo_wrport_adr[4:0] 5'00000
- attribute \src "ls180.v:5428.2-5432.5"
+ attribute \src "ls180.v:5424.2-5428.5"
switch \main_sdblock2mem_fifo_replace
- attribute \src "ls180.v:5428.6-5428.35"
+ attribute \src "ls180.v:5424.6-5424.35"
case 1'1
- assign $0\main_sdblock2mem_fifo_wrport_adr[4:0] $sub$ls180.v:5429$988_Y
- attribute \src "ls180.v:5430.6-5430.10"
+ assign $0\main_sdblock2mem_fifo_wrport_adr[4:0] $sub$ls180.v:5425$988_Y
+ attribute \src "ls180.v:5426.6-5426.10"
case
assign $0\main_sdblock2mem_fifo_wrport_adr[4:0] \main_sdblock2mem_fifo_produce
end
sync always
update \main_sdblock2mem_fifo_wrport_adr $0\main_sdblock2mem_fifo_wrport_adr[4:0]
end
- attribute \src "ls180.v:5459.1-5498.4"
- process $proc$ls180.v:5459$998
+ attribute \src "ls180.v:5455.1-5494.4"
+ process $proc$ls180.v:5455$998
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
+ assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] 0
assign $0\main_sdblock2mem_sink_sink_payload_data1[31:0] 0
+ assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] 1'0
assign $0\main_sdblock2mem_wishbonedmawriter_status[0:0] 1'0
assign $0\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0] 1'0
assign $0\main_sdblock2mem_sink_sink_payload_address[31:0] 0
assign $0\main_sdblock2mem_sink_sink_valid1[0:0] 1'0
assign { } { }
- assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] 0
- assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] 1'0
assign $0\builder_sdblock2memdma_next_state[1:0] \builder_sdblock2memdma_state
- attribute \src "ls180.v:5469.2-5497.9"
+ attribute \src "ls180.v:5465.2-5493.9"
switch \builder_sdblock2memdma_state
attribute \src "ls180.v:0.0-0.0"
case 2'01
assign $0\main_sdblock2mem_sink_sink_valid1[0:0] \main_sdblock2mem_wishbonedmawriter_sink_valid
assign $0\main_sdblock2mem_sink_sink_payload_data1[31:0] \main_sdblock2mem_wishbonedmawriter_sink_payload_data
- assign $0\main_sdblock2mem_sink_sink_payload_address[31:0] $add$ls180.v:5473$999_Y
+ assign $0\main_sdblock2mem_sink_sink_payload_address[31:0] $add$ls180.v:5469$999_Y
assign $0\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0] \main_sdblock2mem_sink_sink_ready1
- attribute \src "ls180.v:5475.4-5486.7"
- switch $and$ls180.v:5475$1000_Y
- attribute \src "ls180.v:5475.8-5475.103"
+ attribute \src "ls180.v:5471.4-5482.7"
+ switch $and$ls180.v:5471$1000_Y
+ attribute \src "ls180.v:5471.8-5471.103"
case 1'1
- assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] $add$ls180.v:5476$1001_Y
+ assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] $add$ls180.v:5472$1001_Y
assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] 1'1
- attribute \src "ls180.v:5478.5-5485.8"
- switch $eq$ls180.v:5478$1003_Y
- attribute \src "ls180.v:5478.9-5478.106"
+ attribute \src "ls180.v:5474.5-5481.8"
+ switch $eq$ls180.v:5474$1003_Y
+ attribute \src "ls180.v:5474.9-5474.106"
case 1'1
- attribute \src "ls180.v:5479.6-5484.9"
+ attribute \src "ls180.v:5475.6-5480.9"
switch \main_sdblock2mem_wishbonedmawriter_loop_storage
- attribute \src "ls180.v:5479.10-5479.57"
+ attribute \src "ls180.v:5475.10-5475.57"
case 1'1
assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] 0
assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] 1'1
- attribute \src "ls180.v:5482.10-5482.14"
+ attribute \src "ls180.v:5478.10-5478.14"
case
assign $0\builder_sdblock2memdma_next_state[1:0] 2'10
end
sync init
update \main_libresocsim_reset_storage $1\main_libresocsim_reset_storage[0:0]
end
- attribute \src "ls180.v:5518.1-5555.4"
- process $proc$ls180.v:5518$1005
+ attribute \src "ls180.v:551.5-551.59"
+ process $proc$ls180.v:551$2947
+ assign { } { }
+ assign $1\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] 1'0
+ sync always
+ sync init
+ update \main_sdram_bankmachine1_cmd_buffer_source_valid $1\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0]
+ end
+ attribute \src "ls180.v:5514.1-5551.4"
+ process $proc$ls180.v:5514$1005
assign { } { }
assign { } { }
assign { } { }
assign $0\main_sdmem2block_dma_source_valid[0:0] 1'0
assign $0\main_interface1_bus_we[0:0] 1'0
assign $0\main_sdmem2block_dma_source_last[0:0] 1'0
- assign { } { }
assign $0\main_sdmem2block_dma_source_payload_data[31:0] 0
+ assign { } { }
assign $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[31:0] 0
assign $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] 1'0
assign $0\builder_sdmem2blockdma_fsm_next_state[0:0] \builder_sdmem2blockdma_fsm_state
- attribute \src "ls180.v:5532.2-5554.9"
+ attribute \src "ls180.v:5528.2-5550.9"
switch \builder_sdmem2blockdma_fsm_state
attribute \src "ls180.v:0.0-0.0"
case 1'1
assign $0\main_sdmem2block_dma_source_valid[0:0] 1'1
assign $0\main_sdmem2block_dma_source_last[0:0] \main_sdmem2block_dma_sink_last
assign $0\main_sdmem2block_dma_source_payload_data[31:0] \main_sdmem2block_dma_data
- attribute \src "ls180.v:5537.4-5540.7"
+ attribute \src "ls180.v:5533.4-5536.7"
switch \main_sdmem2block_dma_source_ready
- attribute \src "ls180.v:5537.8-5537.41"
+ attribute \src "ls180.v:5533.8-5533.41"
case 1'1
assign $0\main_sdmem2block_dma_sink_ready[0:0] 1'1
assign $0\builder_sdmem2blockdma_fsm_next_state[0:0] 1'0
assign $0\main_interface1_bus_we[0:0] 1'0
assign $0\main_interface1_bus_sel[3:0] 4'1111
assign $0\main_interface1_bus_adr[31:0] \main_sdmem2block_dma_sink_payload_address
- attribute \src "ls180.v:5548.4-5552.7"
- switch $and$ls180.v:5548$1006_Y
- attribute \src "ls180.v:5548.8-5548.59"
+ attribute \src "ls180.v:5544.4-5548.7"
+ switch $and$ls180.v:5544$1006_Y
+ attribute \src "ls180.v:5544.8-5544.59"
case 1'1
assign $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[31:0] { \main_interface1_bus_dat_r [7:0] \main_interface1_bus_dat_r [15:8] \main_interface1_bus_dat_r [23:16] \main_interface1_bus_dat_r [31:24] }
assign $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] 1'1
update \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[31:0]
update \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0]
end
- attribute \src "ls180.v:555.5-555.59"
- process $proc$ls180.v:555$2947
+ attribute \src "ls180.v:553.5-553.59"
+ process $proc$ls180.v:553$2948
assign { } { }
- assign $1\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] 1'0
+ assign $1\main_sdram_bankmachine1_cmd_buffer_source_first[0:0] 1'0
sync always
sync init
- update \main_sdram_bankmachine1_cmd_buffer_source_valid $1\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0]
+ update \main_sdram_bankmachine1_cmd_buffer_source_first $1\main_sdram_bankmachine1_cmd_buffer_source_first[0:0]
+ end
+ attribute \src "ls180.v:554.5-554.58"
+ process $proc$ls180.v:554$2949
+ assign { } { }
+ assign $1\main_sdram_bankmachine1_cmd_buffer_source_last[0:0] 1'0
+ sync always
+ sync init
+ update \main_sdram_bankmachine1_cmd_buffer_source_last $1\main_sdram_bankmachine1_cmd_buffer_source_last[0:0]
end
- attribute \src "ls180.v:5556.1-5592.4"
- process $proc$ls180.v:5556$1007
+ attribute \src "ls180.v:555.5-555.64"
+ process $proc$ls180.v:555$2950
+ assign { } { }
+ assign $1\main_sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] 1'0
+ sync always
+ sync init
+ update \main_sdram_bankmachine1_cmd_buffer_source_payload_we $1\main_sdram_bankmachine1_cmd_buffer_source_payload_we[0:0]
+ end
+ attribute \src "ls180.v:5552.1-5588.4"
+ process $proc$ls180.v:5552$1007
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign $0\main_sdmem2block_dma_sink_valid[0:0] 1'0
+ assign $0\main_sdmem2block_dma_sink_payload_address[31:0] 0
assign $0\main_sdmem2block_dma_done_status[0:0] 1'0
assign { } { }
+ assign $0\main_sdmem2block_dma_sink_last[0:0] 1'0
assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] 0
assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] 1'0
- assign $0\main_sdmem2block_dma_sink_last[0:0] 1'0
- assign $0\main_sdmem2block_dma_sink_payload_address[31:0] 0
assign $0\builder_sdmem2blockdma_resetinserter_next_state[1:0] \builder_sdmem2blockdma_resetinserter_state
- attribute \src "ls180.v:5565.2-5591.9"
+ attribute \src "ls180.v:5561.2-5587.9"
switch \builder_sdmem2blockdma_resetinserter_state
attribute \src "ls180.v:0.0-0.0"
case 2'01
assign $0\main_sdmem2block_dma_sink_valid[0:0] 1'1
- assign $0\main_sdmem2block_dma_sink_last[0:0] $eq$ls180.v:5568$1009_Y
- assign $0\main_sdmem2block_dma_sink_payload_address[31:0] $add$ls180.v:5569$1010_Y
- attribute \src "ls180.v:5570.4-5581.7"
+ assign $0\main_sdmem2block_dma_sink_last[0:0] $eq$ls180.v:5564$1009_Y
+ assign $0\main_sdmem2block_dma_sink_payload_address[31:0] $add$ls180.v:5565$1010_Y
+ attribute \src "ls180.v:5566.4-5577.7"
switch \main_sdmem2block_dma_sink_ready
- attribute \src "ls180.v:5570.8-5570.39"
+ attribute \src "ls180.v:5566.8-5566.39"
case 1'1
- assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] $add$ls180.v:5571$1011_Y
+ assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] $add$ls180.v:5567$1011_Y
assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] 1'1
- attribute \src "ls180.v:5573.5-5580.8"
+ attribute \src "ls180.v:5569.5-5576.8"
switch \main_sdmem2block_dma_sink_last
- attribute \src "ls180.v:5573.9-5573.39"
+ attribute \src "ls180.v:5569.9-5569.39"
case 1'1
- attribute \src "ls180.v:5574.6-5579.9"
+ attribute \src "ls180.v:5570.6-5575.9"
switch \main_sdmem2block_dma_loop_storage
- attribute \src "ls180.v:5574.10-5574.43"
+ attribute \src "ls180.v:5570.10-5570.43"
case 1'1
assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] 0
assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] 1'1
- attribute \src "ls180.v:5577.10-5577.14"
+ attribute \src "ls180.v:5573.10-5573.14"
case
assign $0\builder_sdmem2blockdma_resetinserter_next_state[1:0] 2'10
end
update \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0]
update \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0]
end
- attribute \src "ls180.v:557.5-557.59"
- process $proc$ls180.v:557$2948
+ attribute \src "ls180.v:556.12-556.74"
+ process $proc$ls180.v:556$2951
assign { } { }
- assign $1\main_sdram_bankmachine1_cmd_buffer_source_first[0:0] 1'0
+ assign $1\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000
sync always
sync init
- update \main_sdram_bankmachine1_cmd_buffer_source_first $1\main_sdram_bankmachine1_cmd_buffer_source_first[0:0]
+ update \main_sdram_bankmachine1_cmd_buffer_source_payload_addr $1\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0]
end
- attribute \src "ls180.v:558.5-558.58"
- process $proc$ls180.v:558$2949
+ attribute \src "ls180.v:557.12-557.47"
+ process $proc$ls180.v:557$2952
assign { } { }
- assign $1\main_sdram_bankmachine1_cmd_buffer_source_last[0:0] 1'0
+ assign $1\main_sdram_bankmachine1_row[12:0] 13'0000000000000
sync always
sync init
- update \main_sdram_bankmachine1_cmd_buffer_source_last $1\main_sdram_bankmachine1_cmd_buffer_source_last[0:0]
+ update \main_sdram_bankmachine1_row $1\main_sdram_bankmachine1_row[12:0]
end
- attribute \src "ls180.v:559.5-559.64"
- process $proc$ls180.v:559$2950
+ attribute \src "ls180.v:558.5-558.46"
+ process $proc$ls180.v:558$2953
assign { } { }
- assign $1\main_sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] 1'0
+ assign $1\main_sdram_bankmachine1_row_opened[0:0] 1'0
sync always
sync init
- update \main_sdram_bankmachine1_cmd_buffer_source_payload_we $1\main_sdram_bankmachine1_cmd_buffer_source_payload_we[0:0]
+ update \main_sdram_bankmachine1_row_opened $1\main_sdram_bankmachine1_row_opened[0:0]
end
attribute \src "ls180.v:56.5-56.37"
process $proc$ls180.v:56$2764
sync init
update \main_libresocsim_reset_re $1\main_libresocsim_reset_re[0:0]
end
- attribute \src "ls180.v:560.12-560.74"
- process $proc$ls180.v:560$2951
+ attribute \src "ls180.v:560.5-560.44"
+ process $proc$ls180.v:560$2954
assign { } { }
- assign $1\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000
+ assign $1\main_sdram_bankmachine1_row_open[0:0] 1'0
sync always
sync init
- update \main_sdram_bankmachine1_cmd_buffer_source_payload_addr $1\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0]
+ update \main_sdram_bankmachine1_row_open $1\main_sdram_bankmachine1_row_open[0:0]
end
- attribute \src "ls180.v:5604.1-5620.4"
- process $proc$ls180.v:5604$1017
+ attribute \src "ls180.v:5600.1-5616.4"
+ process $proc$ls180.v:5600$1017
assign { } { }
assign $0\main_sdmem2block_converter_source_payload_data[7:0] 8'00000000
- attribute \src "ls180.v:5606.2-5619.9"
+ attribute \src "ls180.v:5602.2-5615.9"
switch \main_sdmem2block_converter_mux
attribute \src "ls180.v:0.0-0.0"
case 2'00
sync always
update \main_sdmem2block_converter_source_payload_data $0\main_sdmem2block_converter_source_payload_data[7:0]
end
- attribute \src "ls180.v:561.12-561.47"
- process $proc$ls180.v:561$2952
+ attribute \src "ls180.v:561.5-561.45"
+ process $proc$ls180.v:561$2955
assign { } { }
- assign $1\main_sdram_bankmachine1_row[12:0] 13'0000000000000
+ assign $1\main_sdram_bankmachine1_row_close[0:0] 1'0
sync always
sync init
- update \main_sdram_bankmachine1_row $1\main_sdram_bankmachine1_row[12:0]
+ update \main_sdram_bankmachine1_row_close $1\main_sdram_bankmachine1_row_close[0:0]
end
- attribute \src "ls180.v:562.5-562.46"
- process $proc$ls180.v:562$2953
+ attribute \src "ls180.v:562.5-562.54"
+ process $proc$ls180.v:562$2956
assign { } { }
- assign $1\main_sdram_bankmachine1_row_opened[0:0] 1'0
+ assign $1\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] 1'0
sync always
sync init
- update \main_sdram_bankmachine1_row_opened $1\main_sdram_bankmachine1_row_opened[0:0]
+ update \main_sdram_bankmachine1_row_col_n_addr_sel $1\main_sdram_bankmachine1_row_col_n_addr_sel[0:0]
end
- attribute \src "ls180.v:5634.1-5641.4"
- process $proc$ls180.v:5634$1018
+ attribute \src "ls180.v:5630.1-5637.4"
+ process $proc$ls180.v:5630$1018
assign { } { }
assign $0\main_sdmem2block_fifo_wrport_adr[4:0] 5'00000
- attribute \src "ls180.v:5636.2-5640.5"
+ attribute \src "ls180.v:5632.2-5636.5"
switch \main_sdmem2block_fifo_replace
- attribute \src "ls180.v:5636.6-5636.35"
+ attribute \src "ls180.v:5632.6-5632.35"
case 1'1
- assign $0\main_sdmem2block_fifo_wrport_adr[4:0] $sub$ls180.v:5637$1019_Y
- attribute \src "ls180.v:5638.6-5638.10"
+ assign $0\main_sdmem2block_fifo_wrport_adr[4:0] $sub$ls180.v:5633$1019_Y
+ attribute \src "ls180.v:5634.6-5634.10"
case
assign $0\main_sdmem2block_fifo_wrport_adr[4:0] \main_sdmem2block_fifo_produce
end
sync always
update \main_sdmem2block_fifo_wrport_adr $0\main_sdmem2block_fifo_wrport_adr[4:0]
end
- attribute \src "ls180.v:564.5-564.44"
- process $proc$ls180.v:564$2954
+ attribute \src "ls180.v:564.32-564.76"
+ process $proc$ls180.v:564$2957
assign { } { }
- assign $1\main_sdram_bankmachine1_row_open[0:0] 1'0
+ assign $1\main_sdram_bankmachine1_twtpcon_ready[0:0] 1'0
sync always
sync init
- update \main_sdram_bankmachine1_row_open $1\main_sdram_bankmachine1_row_open[0:0]
+ update \main_sdram_bankmachine1_twtpcon_ready $1\main_sdram_bankmachine1_twtpcon_ready[0:0]
end
- attribute \src "ls180.v:5649.1-5685.4"
- process $proc$ls180.v:5649$1025
+ attribute \src "ls180.v:5645.1-5681.4"
+ process $proc$ls180.v:5645$1025
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
+ assign $0\builder_libresocsim_adr_next_value_ce1[0:0] 1'0
assign $0\builder_libresocsim_we_next_value2[0:0] 1'0
assign $0\builder_libresocsim_we_next_value_ce2[0:0] 1'0
assign $0\builder_libresocsim_wishbone_dat_r[31:0] 0
assign $0\builder_libresocsim_dat_w_next_value0[7:0] 8'00000000
assign $0\builder_libresocsim_dat_w_next_value_ce0[0:0] 1'0
assign $0\builder_libresocsim_adr_next_value1[13:0] 14'00000000000000
- assign $0\builder_libresocsim_adr_next_value_ce1[0:0] 1'0
assign $0\builder_next_state[1:0] \builder_state
- attribute \src "ls180.v:5660.2-5684.9"
+ attribute \src "ls180.v:5656.2-5680.9"
switch \builder_state
attribute \src "ls180.v:0.0-0.0"
case 2'01
case
assign $0\builder_libresocsim_dat_w_next_value0[7:0] \builder_libresocsim_wishbone_dat_w [7:0]
assign $0\builder_libresocsim_dat_w_next_value_ce0[0:0] 1'1
- attribute \src "ls180.v:5676.4-5682.7"
- switch $and$ls180.v:5676$1026_Y
- attribute \src "ls180.v:5676.8-5676.77"
+ attribute \src "ls180.v:5672.4-5678.7"
+ switch $and$ls180.v:5672$1026_Y
+ attribute \src "ls180.v:5672.8-5672.77"
case 1'1
assign $0\builder_libresocsim_adr_next_value1[13:0] \builder_libresocsim_wishbone_adr [13:0]
assign $0\builder_libresocsim_adr_next_value_ce1[0:0] 1'1
- assign $0\builder_libresocsim_we_next_value2[0:0] $and$ls180.v:5679$1028_Y
+ assign $0\builder_libresocsim_we_next_value2[0:0] $and$ls180.v:5675$1028_Y
assign $0\builder_libresocsim_we_next_value_ce2[0:0] 1'1
assign $0\builder_next_state[1:0] 2'01
case
update \builder_libresocsim_we_next_value2 $0\builder_libresocsim_we_next_value2[0:0]
update \builder_libresocsim_we_next_value_ce2 $0\builder_libresocsim_we_next_value_ce2[0:0]
end
- attribute \src "ls180.v:565.5-565.45"
- process $proc$ls180.v:565$2955
+ attribute \src "ls180.v:565.11-565.55"
+ process $proc$ls180.v:565$2958
assign { } { }
- assign $1\main_sdram_bankmachine1_row_close[0:0] 1'0
+ assign $1\main_sdram_bankmachine1_twtpcon_count[2:0] 3'000
sync always
sync init
- update \main_sdram_bankmachine1_row_close $1\main_sdram_bankmachine1_row_close[0:0]
+ update \main_sdram_bankmachine1_twtpcon_count $1\main_sdram_bankmachine1_twtpcon_count[2:0]
end
- attribute \src "ls180.v:566.5-566.54"
- process $proc$ls180.v:566$2956
+ attribute \src "ls180.v:567.32-567.75"
+ process $proc$ls180.v:567$2959
assign { } { }
- assign $1\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] 1'0
+ assign $0\main_sdram_bankmachine1_trccon_ready[0:0] 1'1
sync always
+ update \main_sdram_bankmachine1_trccon_ready $0\main_sdram_bankmachine1_trccon_ready[0:0]
sync init
- update \main_sdram_bankmachine1_row_col_n_addr_sel $1\main_sdram_bankmachine1_row_col_n_addr_sel[0:0]
end
- attribute \src "ls180.v:568.32-568.76"
- process $proc$ls180.v:568$2957
+ attribute \src "ls180.v:569.32-569.76"
+ process $proc$ls180.v:569$2960
assign { } { }
- assign $1\main_sdram_bankmachine1_twtpcon_ready[0:0] 1'0
+ assign $0\main_sdram_bankmachine1_trascon_ready[0:0] 1'1
sync always
+ update \main_sdram_bankmachine1_trascon_ready $0\main_sdram_bankmachine1_trascon_ready[0:0]
sync init
- update \main_sdram_bankmachine1_twtpcon_ready $1\main_sdram_bankmachine1_twtpcon_ready[0:0]
- end
- attribute \src "ls180.v:569.11-569.55"
- process $proc$ls180.v:569$2958
- assign { } { }
- assign $1\main_sdram_bankmachine1_twtpcon_count[2:0] 3'000
- sync always
- sync init
- update \main_sdram_bankmachine1_twtpcon_count $1\main_sdram_bankmachine1_twtpcon_count[2:0]
end
attribute \src "ls180.v:57.12-57.60"
process $proc$ls180.v:57$2765
sync init
update \main_libresocsim_scratch_storage $1\main_libresocsim_scratch_storage[31:0]
end
- attribute \src "ls180.v:571.32-571.75"
- process $proc$ls180.v:571$2959
- assign { } { }
- assign $0\main_sdram_bankmachine1_trccon_ready[0:0] 1'1
- sync always
- update \main_sdram_bankmachine1_trccon_ready $0\main_sdram_bankmachine1_trccon_ready[0:0]
- sync init
- end
- attribute \src "ls180.v:5710.1-5717.4"
- process $proc$ls180.v:5710$1049
+ attribute \src "ls180.v:5706.1-5713.4"
+ process $proc$ls180.v:5706$1049
assign { } { }
assign { } { }
- assign $0\builder_slave_sel[4:0] [0] $eq$ls180.v:5712$1050_Y
- assign $0\builder_slave_sel[4:0] [1] $eq$ls180.v:5713$1051_Y
- assign $0\builder_slave_sel[4:0] [2] $eq$ls180.v:5714$1052_Y
- assign $0\builder_slave_sel[4:0] [3] $eq$ls180.v:5715$1053_Y
- assign $0\builder_slave_sel[4:0] [4] $eq$ls180.v:5716$1054_Y
+ assign $0\builder_slave_sel[4:0] [0] $eq$ls180.v:5708$1050_Y
+ assign $0\builder_slave_sel[4:0] [1] $eq$ls180.v:5709$1051_Y
+ assign $0\builder_slave_sel[4:0] [2] $eq$ls180.v:5710$1052_Y
+ assign $0\builder_slave_sel[4:0] [3] $eq$ls180.v:5711$1053_Y
+ assign $0\builder_slave_sel[4:0] [4] $eq$ls180.v:5712$1054_Y
sync always
update \builder_slave_sel $0\builder_slave_sel[4:0]
end
- attribute \src "ls180.v:573.32-573.76"
- process $proc$ls180.v:573$2960
+ attribute \src "ls180.v:575.5-575.51"
+ process $proc$ls180.v:575$2961
assign { } { }
- assign $0\main_sdram_bankmachine1_trascon_ready[0:0] 1'1
+ assign $1\main_sdram_bankmachine2_req_wdata_ready[0:0] 1'0
sync always
- update \main_sdram_bankmachine1_trascon_ready $0\main_sdram_bankmachine1_trascon_ready[0:0]
sync init
+ update \main_sdram_bankmachine2_req_wdata_ready $1\main_sdram_bankmachine2_req_wdata_ready[0:0]
end
- attribute \src "ls180.v:5760.1-5771.4"
- process $proc$ls180.v:5760$1067
+ attribute \src "ls180.v:5756.1-5767.4"
+ process $proc$ls180.v:5756$1067
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign $0\builder_error[0:0] 1'0
- assign $0\builder_shared_ack[0:0] $or$ls180.v:5764$1071_Y
- assign $0\builder_shared_dat_r[31:0] $or$ls180.v:5765$1080_Y
- attribute \src "ls180.v:5766.2-5770.5"
+ assign $0\builder_shared_ack[0:0] $or$ls180.v:5760$1071_Y
+ assign $0\builder_shared_dat_r[31:0] $or$ls180.v:5761$1080_Y
+ attribute \src "ls180.v:5762.2-5766.5"
switch \builder_done
- attribute \src "ls180.v:5766.6-5766.18"
+ attribute \src "ls180.v:5762.6-5762.18"
case 1'1
assign $0\builder_shared_dat_r[31:0] 32'11111111111111111111111111111111
assign $0\builder_shared_ack[0:0] 1'1
update \builder_shared_ack $0\builder_shared_ack[0:0]
update \builder_error $0\builder_error[0:0]
end
- attribute \src "ls180.v:579.5-579.51"
- process $proc$ls180.v:579$2961
- assign { } { }
- assign $1\main_sdram_bankmachine2_req_wdata_ready[0:0] 1'0
- sync always
- sync init
- update \main_sdram_bankmachine2_req_wdata_ready $1\main_sdram_bankmachine2_req_wdata_ready[0:0]
- end
- attribute \src "ls180.v:58.5-58.39"
- process $proc$ls180.v:58$2766
- assign { } { }
- assign $1\main_libresocsim_scratch_re[0:0] 1'0
- sync always
- sync init
- update \main_libresocsim_scratch_re $1\main_libresocsim_scratch_re[0:0]
- end
- attribute \src "ls180.v:580.5-580.51"
- process $proc$ls180.v:580$2962
+ attribute \src "ls180.v:576.5-576.51"
+ process $proc$ls180.v:576$2962
assign { } { }
assign $1\main_sdram_bankmachine2_req_rdata_valid[0:0] 1'0
sync always
sync init
update \main_sdram_bankmachine2_req_rdata_valid $1\main_sdram_bankmachine2_req_rdata_valid[0:0]
end
- attribute \src "ls180.v:582.5-582.47"
- process $proc$ls180.v:582$2963
+ attribute \src "ls180.v:578.5-578.47"
+ process $proc$ls180.v:578$2963
assign { } { }
assign $1\main_sdram_bankmachine2_refresh_gnt[0:0] 1'0
sync always
sync init
update \main_sdram_bankmachine2_refresh_gnt $1\main_sdram_bankmachine2_refresh_gnt[0:0]
end
- attribute \src "ls180.v:583.5-583.45"
- process $proc$ls180.v:583$2964
+ attribute \src "ls180.v:579.5-579.45"
+ process $proc$ls180.v:579$2964
assign { } { }
assign $1\main_sdram_bankmachine2_cmd_valid[0:0] 1'0
sync always
sync init
update \main_sdram_bankmachine2_cmd_valid $1\main_sdram_bankmachine2_cmd_valid[0:0]
end
- attribute \src "ls180.v:584.5-584.45"
- process $proc$ls180.v:584$2965
+ attribute \src "ls180.v:58.5-58.39"
+ process $proc$ls180.v:58$2766
+ assign { } { }
+ assign $1\main_libresocsim_scratch_re[0:0] 1'0
+ sync always
+ sync init
+ update \main_libresocsim_scratch_re $1\main_libresocsim_scratch_re[0:0]
+ end
+ attribute \src "ls180.v:580.5-580.45"
+ process $proc$ls180.v:580$2965
assign { } { }
assign $1\main_sdram_bankmachine2_cmd_ready[0:0] 1'0
sync always
sync init
update \main_sdram_bankmachine2_cmd_ready $1\main_sdram_bankmachine2_cmd_ready[0:0]
end
- attribute \src "ls180.v:585.12-585.57"
- process $proc$ls180.v:585$2966
+ attribute \src "ls180.v:581.12-581.57"
+ process $proc$ls180.v:581$2966
assign { } { }
assign $1\main_sdram_bankmachine2_cmd_payload_a[12:0] 13'0000000000000
sync always
sync init
update \main_sdram_bankmachine2_cmd_payload_a $1\main_sdram_bankmachine2_cmd_payload_a[12:0]
end
- attribute \src "ls180.v:587.5-587.51"
- process $proc$ls180.v:587$2967
+ attribute \src "ls180.v:583.5-583.51"
+ process $proc$ls180.v:583$2967
assign { } { }
assign $1\main_sdram_bankmachine2_cmd_payload_cas[0:0] 1'0
sync always
sync init
update \main_sdram_bankmachine2_cmd_payload_cas $1\main_sdram_bankmachine2_cmd_payload_cas[0:0]
end
- attribute \src "ls180.v:588.5-588.51"
- process $proc$ls180.v:588$2968
+ attribute \src "ls180.v:584.5-584.51"
+ process $proc$ls180.v:584$2968
assign { } { }
assign $1\main_sdram_bankmachine2_cmd_payload_ras[0:0] 1'0
sync always
sync init
update \main_sdram_bankmachine2_cmd_payload_ras $1\main_sdram_bankmachine2_cmd_payload_ras[0:0]
end
- attribute \src "ls180.v:589.5-589.50"
- process $proc$ls180.v:589$2969
+ attribute \src "ls180.v:585.5-585.50"
+ process $proc$ls180.v:585$2969
assign { } { }
assign $1\main_sdram_bankmachine2_cmd_payload_we[0:0] 1'0
sync always
sync init
update \main_sdram_bankmachine2_cmd_payload_we $1\main_sdram_bankmachine2_cmd_payload_we[0:0]
end
- attribute \src "ls180.v:590.5-590.54"
- process $proc$ls180.v:590$2970
+ attribute \src "ls180.v:586.5-586.54"
+ process $proc$ls180.v:586$2970
assign { } { }
assign $1\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'0
sync always
sync init
update \main_sdram_bankmachine2_cmd_payload_is_cmd $1\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0]
end
- attribute \src "ls180.v:591.5-591.55"
- process $proc$ls180.v:591$2971
+ attribute \src "ls180.v:587.5-587.55"
+ process $proc$ls180.v:587$2971
assign { } { }
assign $1\main_sdram_bankmachine2_cmd_payload_is_read[0:0] 1'0
sync always
sync init
update \main_sdram_bankmachine2_cmd_payload_is_read $1\main_sdram_bankmachine2_cmd_payload_is_read[0:0]
end
- attribute \src "ls180.v:592.5-592.56"
- process $proc$ls180.v:592$2972
+ attribute \src "ls180.v:588.5-588.56"
+ process $proc$ls180.v:588$2972
assign { } { }
assign $1\main_sdram_bankmachine2_cmd_payload_is_write[0:0] 1'0
sync always
sync init
update \main_sdram_bankmachine2_cmd_payload_is_write $1\main_sdram_bankmachine2_cmd_payload_is_write[0:0]
end
- attribute \src "ls180.v:593.5-593.50"
- process $proc$ls180.v:593$2973
+ attribute \src "ls180.v:589.5-589.50"
+ process $proc$ls180.v:589$2973
assign { } { }
assign $1\main_sdram_bankmachine2_auto_precharge[0:0] 1'0
sync always
sync init
update \main_sdram_bankmachine2_auto_precharge $1\main_sdram_bankmachine2_auto_precharge[0:0]
end
- attribute \src "ls180.v:596.5-596.67"
- process $proc$ls180.v:596$2974
+ attribute \src "ls180.v:592.5-592.67"
+ process $proc$ls180.v:592$2974
assign { } { }
assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first[0:0] 1'0
sync always
update \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first[0:0]
sync init
end
- attribute \src "ls180.v:597.5-597.66"
- process $proc$ls180.v:597$2975
+ attribute \src "ls180.v:593.5-593.66"
+ process $proc$ls180.v:593$2975
assign { } { }
assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last[0:0] 1'0
sync always
update \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last[0:0]
sync init
end
- attribute \src "ls180.v:612.11-612.68"
- process $proc$ls180.v:612$2976
+ attribute \src "ls180.v:608.11-608.68"
+ process $proc$ls180.v:608$2976
assign { } { }
assign $1\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] 4'0000
sync always
sync init
update \main_sdram_bankmachine2_cmd_buffer_lookahead_level $1\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0]
end
- attribute \src "ls180.v:613.5-613.64"
- process $proc$ls180.v:613$2977
+ attribute \src "ls180.v:609.5-609.64"
+ process $proc$ls180.v:609$2977
assign { } { }
assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_replace[0:0] 1'0
sync always
update \main_sdram_bankmachine2_cmd_buffer_lookahead_replace $0\main_sdram_bankmachine2_cmd_buffer_lookahead_replace[0:0]
sync init
end
- attribute \src "ls180.v:614.11-614.70"
- process $proc$ls180.v:614$2978
+ attribute \src "ls180.v:610.11-610.70"
+ process $proc$ls180.v:610$2978
assign { } { }
assign $1\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] 3'000
sync always
sync init
update \main_sdram_bankmachine2_cmd_buffer_lookahead_produce $1\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0]
end
- attribute \src "ls180.v:615.11-615.70"
- process $proc$ls180.v:615$2979
+ attribute \src "ls180.v:611.11-611.70"
+ process $proc$ls180.v:611$2979
assign { } { }
assign $1\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] 3'000
sync always
sync init
update \main_sdram_bankmachine2_cmd_buffer_lookahead_consume $1\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0]
end
- attribute \src "ls180.v:616.11-616.73"
- process $proc$ls180.v:616$2980
+ attribute \src "ls180.v:612.11-612.73"
+ process $proc$ls180.v:612$2980
assign { } { }
assign $1\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] 3'000
sync always
sync init
update \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr $1\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0]
end
- attribute \src "ls180.v:6285.1-6290.4"
- process $proc$ls180.v:6285$1954
+ attribute \src "ls180.v:6281.1-6286.4"
+ process $proc$ls180.v:6281$1954
assign { } { }
assign $0\main_spimaster9_start[0:0] 1'0
- attribute \src "ls180.v:6287.2-6289.5"
+ attribute \src "ls180.v:6283.2-6285.5"
switch \main_spimaster12_re
- attribute \src "ls180.v:6287.6-6287.25"
+ attribute \src "ls180.v:6283.6-6283.25"
case 1'1
assign $0\main_spimaster9_start[0:0] \main_spimaster11_storage [0]
case
sync init
update \main_libresocsim_bus_errors $1\main_libresocsim_bus_errors[31:0]
end
- attribute \src "ls180.v:6331.1-6336.4"
- process $proc$ls180.v:6331$2019
+ attribute \src "ls180.v:6327.1-6332.4"
+ process $proc$ls180.v:6327$2019
assign { } { }
assign $0\main_spisdcard_start1[0:0] 1'0
- attribute \src "ls180.v:6333.2-6335.5"
+ attribute \src "ls180.v:6329.2-6331.5"
switch \main_spisdcard_control_re
- attribute \src "ls180.v:6333.6-6333.31"
+ attribute \src "ls180.v:6329.6-6329.31"
case 1'1
assign $0\main_spisdcard_start1[0:0] \main_spisdcard_control_storage [0]
case
sync always
update \main_spisdcard_start1 $0\main_spisdcard_start1[0:0]
end
- attribute \src "ls180.v:637.5-637.59"
- process $proc$ls180.v:637$2981
+ attribute \src "ls180.v:633.5-633.59"
+ process $proc$ls180.v:633$2981
assign { } { }
assign $1\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] 1'0
sync always
sync init
update \main_sdram_bankmachine2_cmd_buffer_source_valid $1\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0]
end
- attribute \src "ls180.v:639.5-639.59"
- process $proc$ls180.v:639$2982
+ attribute \src "ls180.v:635.5-635.59"
+ process $proc$ls180.v:635$2982
assign { } { }
assign $1\main_sdram_bankmachine2_cmd_buffer_source_first[0:0] 1'0
sync always
sync init
update \main_sdram_bankmachine2_cmd_buffer_source_first $1\main_sdram_bankmachine2_cmd_buffer_source_first[0:0]
end
- attribute \src "ls180.v:640.5-640.58"
- process $proc$ls180.v:640$2983
+ attribute \src "ls180.v:636.5-636.58"
+ process $proc$ls180.v:636$2983
assign { } { }
assign $1\main_sdram_bankmachine2_cmd_buffer_source_last[0:0] 1'0
sync always
sync init
update \main_sdram_bankmachine2_cmd_buffer_source_last $1\main_sdram_bankmachine2_cmd_buffer_source_last[0:0]
end
- attribute \src "ls180.v:641.5-641.64"
- process $proc$ls180.v:641$2984
+ attribute \src "ls180.v:637.5-637.64"
+ process $proc$ls180.v:637$2984
assign { } { }
assign $1\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] 1'0
sync always
sync init
update \main_sdram_bankmachine2_cmd_buffer_source_payload_we $1\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0]
end
- attribute \src "ls180.v:642.12-642.74"
- process $proc$ls180.v:642$2985
+ attribute \src "ls180.v:638.12-638.74"
+ process $proc$ls180.v:638$2985
assign { } { }
assign $1\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000
sync always
sync init
update \main_sdram_bankmachine2_cmd_buffer_source_payload_addr $1\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0]
end
- attribute \src "ls180.v:643.12-643.47"
- process $proc$ls180.v:643$2986
+ attribute \src "ls180.v:639.12-639.47"
+ process $proc$ls180.v:639$2986
assign { } { }
assign $1\main_sdram_bankmachine2_row[12:0] 13'0000000000000
sync always
sync init
update \main_sdram_bankmachine2_row $1\main_sdram_bankmachine2_row[12:0]
end
- attribute \src "ls180.v:644.5-644.46"
- process $proc$ls180.v:644$2987
+ attribute \src "ls180.v:640.5-640.46"
+ process $proc$ls180.v:640$2987
assign { } { }
assign $1\main_sdram_bankmachine2_row_opened[0:0] 1'0
sync always
sync init
update \main_sdram_bankmachine2_row_opened $1\main_sdram_bankmachine2_row_opened[0:0]
end
- attribute \src "ls180.v:646.5-646.44"
- process $proc$ls180.v:646$2988
+ attribute \src "ls180.v:642.5-642.44"
+ process $proc$ls180.v:642$2988
assign { } { }
assign $1\main_sdram_bankmachine2_row_open[0:0] 1'0
sync always
sync init
update \main_sdram_bankmachine2_row_open $1\main_sdram_bankmachine2_row_open[0:0]
end
- attribute \src "ls180.v:647.5-647.45"
- process $proc$ls180.v:647$2989
+ attribute \src "ls180.v:643.5-643.45"
+ process $proc$ls180.v:643$2989
assign { } { }
assign $1\main_sdram_bankmachine2_row_close[0:0] 1'0
sync always
sync init
update \main_sdram_bankmachine2_row_close $1\main_sdram_bankmachine2_row_close[0:0]
end
- attribute \src "ls180.v:648.5-648.54"
- process $proc$ls180.v:648$2990
+ attribute \src "ls180.v:644.5-644.54"
+ process $proc$ls180.v:644$2990
assign { } { }
assign $1\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] 1'0
sync always
sync init
update \main_sdram_bankmachine2_row_col_n_addr_sel $1\main_sdram_bankmachine2_row_col_n_addr_sel[0:0]
end
- attribute \src "ls180.v:65.12-65.55"
- process $proc$ls180.v:65$2768
- assign { } { }
- assign $1\main_libresocsim_libresoc_interrupt[15:0] 16'0000000000000000
- sync always
- sync init
- update \main_libresocsim_libresoc_interrupt $1\main_libresocsim_libresoc_interrupt[15:0]
- end
- attribute \src "ls180.v:650.32-650.76"
- process $proc$ls180.v:650$2991
+ attribute \src "ls180.v:646.32-646.76"
+ process $proc$ls180.v:646$2991
assign { } { }
assign $1\main_sdram_bankmachine2_twtpcon_ready[0:0] 1'0
sync always
sync init
update \main_sdram_bankmachine2_twtpcon_ready $1\main_sdram_bankmachine2_twtpcon_ready[0:0]
end
- attribute \src "ls180.v:651.11-651.55"
- process $proc$ls180.v:651$2992
+ attribute \src "ls180.v:647.11-647.55"
+ process $proc$ls180.v:647$2992
assign { } { }
assign $1\main_sdram_bankmachine2_twtpcon_count[2:0] 3'000
sync always
sync init
update \main_sdram_bankmachine2_twtpcon_count $1\main_sdram_bankmachine2_twtpcon_count[2:0]
end
- attribute \src "ls180.v:6520.1-6536.4"
- process $proc$ls180.v:6520$2240
+ attribute \src "ls180.v:649.32-649.75"
+ process $proc$ls180.v:649$2993
+ assign { } { }
+ assign $0\main_sdram_bankmachine2_trccon_ready[0:0] 1'1
+ sync always
+ update \main_sdram_bankmachine2_trccon_ready $0\main_sdram_bankmachine2_trccon_ready[0:0]
+ sync init
+ end
+ attribute \src "ls180.v:65.12-65.55"
+ process $proc$ls180.v:65$2768
+ assign { } { }
+ assign $1\main_libresocsim_libresoc_interrupt[15:0] 16'0000000000000000
+ sync always
+ sync init
+ update \main_libresocsim_libresoc_interrupt $1\main_libresocsim_libresoc_interrupt[15:0]
+ end
+ attribute \src "ls180.v:651.32-651.76"
+ process $proc$ls180.v:651$2994
+ assign { } { }
+ assign $0\main_sdram_bankmachine2_trascon_ready[0:0] 1'1
+ sync always
+ update \main_sdram_bankmachine2_trascon_ready $0\main_sdram_bankmachine2_trascon_ready[0:0]
+ sync init
+ end
+ attribute \src "ls180.v:6516.1-6532.4"
+ process $proc$ls180.v:6516$2240
assign { } { }
assign $0\builder_comb_rhs_array_muxed0[0:0] 1'0
- attribute \src "ls180.v:6522.2-6535.9"
+ attribute \src "ls180.v:6518.2-6531.9"
switch \main_sdram_choose_cmd_grant
attribute \src "ls180.v:0.0-0.0"
case 2'00
sync always
update \builder_comb_rhs_array_muxed0 $0\builder_comb_rhs_array_muxed0[0:0]
end
- attribute \src "ls180.v:653.32-653.75"
- process $proc$ls180.v:653$2993
- assign { } { }
- assign $0\main_sdram_bankmachine2_trccon_ready[0:0] 1'1
- sync always
- update \main_sdram_bankmachine2_trccon_ready $0\main_sdram_bankmachine2_trccon_ready[0:0]
- sync init
- end
- attribute \src "ls180.v:6537.1-6553.4"
- process $proc$ls180.v:6537$2241
+ attribute \src "ls180.v:6533.1-6549.4"
+ process $proc$ls180.v:6533$2241
assign { } { }
assign $0\builder_comb_rhs_array_muxed1[12:0] 13'0000000000000
- attribute \src "ls180.v:6539.2-6552.9"
+ attribute \src "ls180.v:6535.2-6548.9"
switch \main_sdram_choose_cmd_grant
attribute \src "ls180.v:0.0-0.0"
case 2'00
sync always
update \builder_comb_rhs_array_muxed1 $0\builder_comb_rhs_array_muxed1[12:0]
end
- attribute \src "ls180.v:655.32-655.76"
- process $proc$ls180.v:655$2994
- assign { } { }
- assign $0\main_sdram_bankmachine2_trascon_ready[0:0] 1'1
- sync always
- update \main_sdram_bankmachine2_trascon_ready $0\main_sdram_bankmachine2_trascon_ready[0:0]
- sync init
- end
- attribute \src "ls180.v:6554.1-6570.4"
- process $proc$ls180.v:6554$2242
+ attribute \src "ls180.v:6550.1-6566.4"
+ process $proc$ls180.v:6550$2242
assign { } { }
assign $0\builder_comb_rhs_array_muxed2[1:0] 2'00
- attribute \src "ls180.v:6556.2-6569.9"
+ attribute \src "ls180.v:6552.2-6565.9"
switch \main_sdram_choose_cmd_grant
attribute \src "ls180.v:0.0-0.0"
case 2'00
sync always
update \builder_comb_rhs_array_muxed2 $0\builder_comb_rhs_array_muxed2[1:0]
end
- attribute \src "ls180.v:6571.1-6587.4"
- process $proc$ls180.v:6571$2243
+ attribute \src "ls180.v:6567.1-6583.4"
+ process $proc$ls180.v:6567$2243
assign { } { }
assign $0\builder_comb_rhs_array_muxed3[0:0] 1'0
- attribute \src "ls180.v:6573.2-6586.9"
+ attribute \src "ls180.v:6569.2-6582.9"
switch \main_sdram_choose_cmd_grant
attribute \src "ls180.v:0.0-0.0"
case 2'00
sync always
update \builder_comb_rhs_array_muxed3 $0\builder_comb_rhs_array_muxed3[0:0]
end
- attribute \src "ls180.v:6588.1-6604.4"
- process $proc$ls180.v:6588$2244
+ attribute \src "ls180.v:657.5-657.51"
+ process $proc$ls180.v:657$2995
+ assign { } { }
+ assign $1\main_sdram_bankmachine3_req_wdata_ready[0:0] 1'0
+ sync always
+ sync init
+ update \main_sdram_bankmachine3_req_wdata_ready $1\main_sdram_bankmachine3_req_wdata_ready[0:0]
+ end
+ attribute \src "ls180.v:658.5-658.51"
+ process $proc$ls180.v:658$2996
+ assign { } { }
+ assign $1\main_sdram_bankmachine3_req_rdata_valid[0:0] 1'0
+ sync always
+ sync init
+ update \main_sdram_bankmachine3_req_rdata_valid $1\main_sdram_bankmachine3_req_rdata_valid[0:0]
+ end
+ attribute \src "ls180.v:6584.1-6600.4"
+ process $proc$ls180.v:6584$2244
assign { } { }
assign $0\builder_comb_rhs_array_muxed4[0:0] 1'0
- attribute \src "ls180.v:6590.2-6603.9"
+ attribute \src "ls180.v:6586.2-6599.9"
switch \main_sdram_choose_cmd_grant
attribute \src "ls180.v:0.0-0.0"
case 2'00
sync always
update \builder_comb_rhs_array_muxed4 $0\builder_comb_rhs_array_muxed4[0:0]
end
- attribute \src "ls180.v:6605.1-6621.4"
- process $proc$ls180.v:6605$2245
+ attribute \src "ls180.v:660.5-660.47"
+ process $proc$ls180.v:660$2997
+ assign { } { }
+ assign $1\main_sdram_bankmachine3_refresh_gnt[0:0] 1'0
+ sync always
+ sync init
+ update \main_sdram_bankmachine3_refresh_gnt $1\main_sdram_bankmachine3_refresh_gnt[0:0]
+ end
+ attribute \src "ls180.v:6601.1-6617.4"
+ process $proc$ls180.v:6601$2245
assign { } { }
assign $0\builder_comb_rhs_array_muxed5[0:0] 1'0
- attribute \src "ls180.v:6607.2-6620.9"
+ attribute \src "ls180.v:6603.2-6616.9"
switch \main_sdram_choose_cmd_grant
attribute \src "ls180.v:0.0-0.0"
case 2'00
sync always
update \builder_comb_rhs_array_muxed5 $0\builder_comb_rhs_array_muxed5[0:0]
end
- attribute \src "ls180.v:661.5-661.51"
- process $proc$ls180.v:661$2995
- assign { } { }
- assign $1\main_sdram_bankmachine3_req_wdata_ready[0:0] 1'0
- sync always
- sync init
- update \main_sdram_bankmachine3_req_wdata_ready $1\main_sdram_bankmachine3_req_wdata_ready[0:0]
- end
- attribute \src "ls180.v:662.5-662.51"
- process $proc$ls180.v:662$2996
+ attribute \src "ls180.v:661.5-661.45"
+ process $proc$ls180.v:661$2998
assign { } { }
- assign $1\main_sdram_bankmachine3_req_rdata_valid[0:0] 1'0
+ assign $1\main_sdram_bankmachine3_cmd_valid[0:0] 1'0
sync always
sync init
- update \main_sdram_bankmachine3_req_rdata_valid $1\main_sdram_bankmachine3_req_rdata_valid[0:0]
+ update \main_sdram_bankmachine3_cmd_valid $1\main_sdram_bankmachine3_cmd_valid[0:0]
end
- attribute \src "ls180.v:6622.1-6638.4"
- process $proc$ls180.v:6622$2246
+ attribute \src "ls180.v:6618.1-6634.4"
+ process $proc$ls180.v:6618$2246
assign { } { }
assign $0\builder_comb_t_array_muxed0[0:0] 1'0
- attribute \src "ls180.v:6624.2-6637.9"
+ attribute \src "ls180.v:6620.2-6633.9"
switch \main_sdram_choose_cmd_grant
attribute \src "ls180.v:0.0-0.0"
case 2'00
sync always
update \builder_comb_t_array_muxed0 $0\builder_comb_t_array_muxed0[0:0]
end
- attribute \src "ls180.v:6639.1-6655.4"
- process $proc$ls180.v:6639$2247
+ attribute \src "ls180.v:662.5-662.45"
+ process $proc$ls180.v:662$2999
+ assign { } { }
+ assign $1\main_sdram_bankmachine3_cmd_ready[0:0] 1'0
+ sync always
+ sync init
+ update \main_sdram_bankmachine3_cmd_ready $1\main_sdram_bankmachine3_cmd_ready[0:0]
+ end
+ attribute \src "ls180.v:663.12-663.57"
+ process $proc$ls180.v:663$3000
+ assign { } { }
+ assign $1\main_sdram_bankmachine3_cmd_payload_a[12:0] 13'0000000000000
+ sync always
+ sync init
+ update \main_sdram_bankmachine3_cmd_payload_a $1\main_sdram_bankmachine3_cmd_payload_a[12:0]
+ end
+ attribute \src "ls180.v:6635.1-6651.4"
+ process $proc$ls180.v:6635$2247
assign { } { }
assign $0\builder_comb_t_array_muxed1[0:0] 1'0
- attribute \src "ls180.v:6641.2-6654.9"
+ attribute \src "ls180.v:6637.2-6650.9"
switch \main_sdram_choose_cmd_grant
attribute \src "ls180.v:0.0-0.0"
case 2'00
sync always
update \builder_comb_t_array_muxed1 $0\builder_comb_t_array_muxed1[0:0]
end
- attribute \src "ls180.v:664.5-664.47"
- process $proc$ls180.v:664$2997
+ attribute \src "ls180.v:665.5-665.51"
+ process $proc$ls180.v:665$3001
assign { } { }
- assign $1\main_sdram_bankmachine3_refresh_gnt[0:0] 1'0
- sync always
- sync init
- update \main_sdram_bankmachine3_refresh_gnt $1\main_sdram_bankmachine3_refresh_gnt[0:0]
- end
- attribute \src "ls180.v:665.5-665.45"
- process $proc$ls180.v:665$2998
- assign { } { }
- assign $1\main_sdram_bankmachine3_cmd_valid[0:0] 1'0
+ assign $1\main_sdram_bankmachine3_cmd_payload_cas[0:0] 1'0
sync always
sync init
- update \main_sdram_bankmachine3_cmd_valid $1\main_sdram_bankmachine3_cmd_valid[0:0]
+ update \main_sdram_bankmachine3_cmd_payload_cas $1\main_sdram_bankmachine3_cmd_payload_cas[0:0]
end
- attribute \src "ls180.v:6656.1-6672.4"
- process $proc$ls180.v:6656$2248
+ attribute \src "ls180.v:6652.1-6668.4"
+ process $proc$ls180.v:6652$2248
assign { } { }
assign $0\builder_comb_t_array_muxed2[0:0] 1'0
- attribute \src "ls180.v:6658.2-6671.9"
+ attribute \src "ls180.v:6654.2-6667.9"
switch \main_sdram_choose_cmd_grant
attribute \src "ls180.v:0.0-0.0"
case 2'00
sync always
update \builder_comb_t_array_muxed2 $0\builder_comb_t_array_muxed2[0:0]
end
- attribute \src "ls180.v:666.5-666.45"
- process $proc$ls180.v:666$2999
+ attribute \src "ls180.v:666.5-666.51"
+ process $proc$ls180.v:666$3002
assign { } { }
- assign $1\main_sdram_bankmachine3_cmd_ready[0:0] 1'0
- sync always
- sync init
- update \main_sdram_bankmachine3_cmd_ready $1\main_sdram_bankmachine3_cmd_ready[0:0]
- end
- attribute \src "ls180.v:667.12-667.57"
- process $proc$ls180.v:667$3000
- assign { } { }
- assign $1\main_sdram_bankmachine3_cmd_payload_a[12:0] 13'0000000000000
+ assign $1\main_sdram_bankmachine3_cmd_payload_ras[0:0] 1'0
sync always
sync init
- update \main_sdram_bankmachine3_cmd_payload_a $1\main_sdram_bankmachine3_cmd_payload_a[12:0]
+ update \main_sdram_bankmachine3_cmd_payload_ras $1\main_sdram_bankmachine3_cmd_payload_ras[0:0]
end
- attribute \src "ls180.v:6673.1-6689.4"
- process $proc$ls180.v:6673$2249
+ attribute \src "ls180.v:6669.1-6685.4"
+ process $proc$ls180.v:6669$2249
assign { } { }
assign $0\builder_comb_rhs_array_muxed6[0:0] 1'0
- attribute \src "ls180.v:6675.2-6688.9"
+ attribute \src "ls180.v:6671.2-6684.9"
switch \main_sdram_choose_req_grant
attribute \src "ls180.v:0.0-0.0"
case 2'00
sync always
update \builder_comb_rhs_array_muxed6 $0\builder_comb_rhs_array_muxed6[0:0]
end
- attribute \src "ls180.v:669.5-669.51"
- process $proc$ls180.v:669$3001
+ attribute \src "ls180.v:667.5-667.50"
+ process $proc$ls180.v:667$3003
assign { } { }
- assign $1\main_sdram_bankmachine3_cmd_payload_cas[0:0] 1'0
+ assign $1\main_sdram_bankmachine3_cmd_payload_we[0:0] 1'0
sync always
sync init
- update \main_sdram_bankmachine3_cmd_payload_cas $1\main_sdram_bankmachine3_cmd_payload_cas[0:0]
+ update \main_sdram_bankmachine3_cmd_payload_we $1\main_sdram_bankmachine3_cmd_payload_we[0:0]
+ end
+ attribute \src "ls180.v:668.5-668.54"
+ process $proc$ls180.v:668$3004
+ assign { } { }
+ assign $1\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] 1'0
+ sync always
+ sync init
+ update \main_sdram_bankmachine3_cmd_payload_is_cmd $1\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0]
end
- attribute \src "ls180.v:6690.1-6706.4"
- process $proc$ls180.v:6690$2250
+ attribute \src "ls180.v:6686.1-6702.4"
+ process $proc$ls180.v:6686$2250
assign { } { }
assign $0\builder_comb_rhs_array_muxed7[12:0] 13'0000000000000
- attribute \src "ls180.v:6692.2-6705.9"
+ attribute \src "ls180.v:6688.2-6701.9"
switch \main_sdram_choose_req_grant
attribute \src "ls180.v:0.0-0.0"
case 2'00
sync always
update \builder_comb_rhs_array_muxed7 $0\builder_comb_rhs_array_muxed7[12:0]
end
- attribute \src "ls180.v:670.5-670.51"
- process $proc$ls180.v:670$3002
+ attribute \src "ls180.v:669.5-669.55"
+ process $proc$ls180.v:669$3005
assign { } { }
- assign $1\main_sdram_bankmachine3_cmd_payload_ras[0:0] 1'0
+ assign $1\main_sdram_bankmachine3_cmd_payload_is_read[0:0] 1'0
sync always
sync init
- update \main_sdram_bankmachine3_cmd_payload_ras $1\main_sdram_bankmachine3_cmd_payload_ras[0:0]
+ update \main_sdram_bankmachine3_cmd_payload_is_read $1\main_sdram_bankmachine3_cmd_payload_is_read[0:0]
+ end
+ attribute \src "ls180.v:670.5-670.56"
+ process $proc$ls180.v:670$3006
+ assign { } { }
+ assign $1\main_sdram_bankmachine3_cmd_payload_is_write[0:0] 1'0
+ sync always
+ sync init
+ update \main_sdram_bankmachine3_cmd_payload_is_write $1\main_sdram_bankmachine3_cmd_payload_is_write[0:0]
end
- attribute \src "ls180.v:6707.1-6723.4"
- process $proc$ls180.v:6707$2251
+ attribute \src "ls180.v:6703.1-6719.4"
+ process $proc$ls180.v:6703$2251
assign { } { }
assign $0\builder_comb_rhs_array_muxed8[1:0] 2'00
- attribute \src "ls180.v:6709.2-6722.9"
+ attribute \src "ls180.v:6705.2-6718.9"
switch \main_sdram_choose_req_grant
attribute \src "ls180.v:0.0-0.0"
case 2'00
update \builder_comb_rhs_array_muxed8 $0\builder_comb_rhs_array_muxed8[1:0]
end
attribute \src "ls180.v:671.5-671.50"
- process $proc$ls180.v:671$3003
- assign { } { }
- assign $1\main_sdram_bankmachine3_cmd_payload_we[0:0] 1'0
- sync always
- sync init
- update \main_sdram_bankmachine3_cmd_payload_we $1\main_sdram_bankmachine3_cmd_payload_we[0:0]
- end
- attribute \src "ls180.v:672.5-672.54"
- process $proc$ls180.v:672$3004
+ process $proc$ls180.v:671$3007
assign { } { }
- assign $1\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] 1'0
+ assign $1\main_sdram_bankmachine3_auto_precharge[0:0] 1'0
sync always
sync init
- update \main_sdram_bankmachine3_cmd_payload_is_cmd $1\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0]
+ update \main_sdram_bankmachine3_auto_precharge $1\main_sdram_bankmachine3_auto_precharge[0:0]
end
- attribute \src "ls180.v:6724.1-6740.4"
- process $proc$ls180.v:6724$2252
+ attribute \src "ls180.v:6720.1-6736.4"
+ process $proc$ls180.v:6720$2252
assign { } { }
assign $0\builder_comb_rhs_array_muxed9[0:0] 1'0
- attribute \src "ls180.v:6726.2-6739.9"
+ attribute \src "ls180.v:6722.2-6735.9"
switch \main_sdram_choose_req_grant
attribute \src "ls180.v:0.0-0.0"
case 2'00
sync always
update \builder_comb_rhs_array_muxed9 $0\builder_comb_rhs_array_muxed9[0:0]
end
- attribute \src "ls180.v:673.5-673.55"
- process $proc$ls180.v:673$3005
- assign { } { }
- assign $1\main_sdram_bankmachine3_cmd_payload_is_read[0:0] 1'0
- sync always
- sync init
- update \main_sdram_bankmachine3_cmd_payload_is_read $1\main_sdram_bankmachine3_cmd_payload_is_read[0:0]
- end
- attribute \src "ls180.v:674.5-674.56"
- process $proc$ls180.v:674$3006
- assign { } { }
- assign $1\main_sdram_bankmachine3_cmd_payload_is_write[0:0] 1'0
- sync always
- sync init
- update \main_sdram_bankmachine3_cmd_payload_is_write $1\main_sdram_bankmachine3_cmd_payload_is_write[0:0]
- end
- attribute \src "ls180.v:6741.1-6757.4"
- process $proc$ls180.v:6741$2253
+ attribute \src "ls180.v:6737.1-6753.4"
+ process $proc$ls180.v:6737$2253
assign { } { }
assign $0\builder_comb_rhs_array_muxed10[0:0] 1'0
- attribute \src "ls180.v:6743.2-6756.9"
+ attribute \src "ls180.v:6739.2-6752.9"
switch \main_sdram_choose_req_grant
attribute \src "ls180.v:0.0-0.0"
case 2'00
sync always
update \builder_comb_rhs_array_muxed10 $0\builder_comb_rhs_array_muxed10[0:0]
end
- attribute \src "ls180.v:675.5-675.50"
- process $proc$ls180.v:675$3007
+ attribute \src "ls180.v:674.5-674.67"
+ process $proc$ls180.v:674$3008
assign { } { }
- assign $1\main_sdram_bankmachine3_auto_precharge[0:0] 1'0
+ assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first[0:0] 1'0
sync always
+ update \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first[0:0]
+ sync init
+ end
+ attribute \src "ls180.v:675.5-675.66"
+ process $proc$ls180.v:675$3009
+ assign { } { }
+ assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last[0:0] 1'0
+ sync always
+ update \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last[0:0]
sync init
- update \main_sdram_bankmachine3_auto_precharge $1\main_sdram_bankmachine3_auto_precharge[0:0]
end
- attribute \src "ls180.v:6758.1-6774.4"
- process $proc$ls180.v:6758$2254
+ attribute \src "ls180.v:6754.1-6770.4"
+ process $proc$ls180.v:6754$2254
assign { } { }
assign $0\builder_comb_rhs_array_muxed11[0:0] 1'0
- attribute \src "ls180.v:6760.2-6773.9"
+ attribute \src "ls180.v:6756.2-6769.9"
switch \main_sdram_choose_req_grant
attribute \src "ls180.v:0.0-0.0"
case 2'00
sync always
update \builder_comb_rhs_array_muxed11 $0\builder_comb_rhs_array_muxed11[0:0]
end
- attribute \src "ls180.v:6775.1-6791.4"
- process $proc$ls180.v:6775$2255
+ attribute \src "ls180.v:6771.1-6787.4"
+ process $proc$ls180.v:6771$2255
assign { } { }
assign $0\builder_comb_t_array_muxed3[0:0] 1'0
- attribute \src "ls180.v:6777.2-6790.9"
+ attribute \src "ls180.v:6773.2-6786.9"
switch \main_sdram_choose_req_grant
attribute \src "ls180.v:0.0-0.0"
case 2'00
sync always
update \builder_comb_t_array_muxed3 $0\builder_comb_t_array_muxed3[0:0]
end
- attribute \src "ls180.v:678.5-678.67"
- process $proc$ls180.v:678$3008
- assign { } { }
- assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first[0:0] 1'0
- sync always
- update \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first[0:0]
- sync init
- end
- attribute \src "ls180.v:679.5-679.66"
- process $proc$ls180.v:679$3009
- assign { } { }
- assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last[0:0] 1'0
- sync always
- update \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last[0:0]
- sync init
- end
- attribute \src "ls180.v:6792.1-6808.4"
- process $proc$ls180.v:6792$2256
+ attribute \src "ls180.v:6788.1-6804.4"
+ process $proc$ls180.v:6788$2256
assign { } { }
assign $0\builder_comb_t_array_muxed4[0:0] 1'0
- attribute \src "ls180.v:6794.2-6807.9"
+ attribute \src "ls180.v:6790.2-6803.9"
switch \main_sdram_choose_req_grant
attribute \src "ls180.v:0.0-0.0"
case 2'00
sync always
update \builder_comb_t_array_muxed4 $0\builder_comb_t_array_muxed4[0:0]
end
- attribute \src "ls180.v:6809.1-6825.4"
- process $proc$ls180.v:6809$2257
+ attribute \src "ls180.v:6805.1-6821.4"
+ process $proc$ls180.v:6805$2257
assign { } { }
assign $0\builder_comb_t_array_muxed5[0:0] 1'0
- attribute \src "ls180.v:6811.2-6824.9"
+ attribute \src "ls180.v:6807.2-6820.9"
switch \main_sdram_choose_req_grant
attribute \src "ls180.v:0.0-0.0"
case 2'00
sync always
update \builder_comb_t_array_muxed5 $0\builder_comb_t_array_muxed5[0:0]
end
- attribute \src "ls180.v:6826.1-6833.4"
- process $proc$ls180.v:6826$2258
+ attribute \src "ls180.v:6822.1-6829.4"
+ process $proc$ls180.v:6822$2258
assign { } { }
assign $0\builder_comb_rhs_array_muxed12[21:0] 22'0000000000000000000000
- attribute \src "ls180.v:6828.2-6832.9"
+ attribute \src "ls180.v:6824.2-6828.9"
switch \builder_roundrobin0_grant
attribute \src "ls180.v:0.0-0.0"
case
sync always
update \builder_comb_rhs_array_muxed12 $0\builder_comb_rhs_array_muxed12[21:0]
end
- attribute \src "ls180.v:6834.1-6841.4"
- process $proc$ls180.v:6834$2259
+ attribute \src "ls180.v:6830.1-6837.4"
+ process $proc$ls180.v:6830$2259
assign { } { }
assign $0\builder_comb_rhs_array_muxed13[0:0] 1'0
- attribute \src "ls180.v:6836.2-6840.9"
+ attribute \src "ls180.v:6832.2-6836.9"
switch \builder_roundrobin0_grant
attribute \src "ls180.v:0.0-0.0"
case
sync always
update \builder_comb_rhs_array_muxed13 $0\builder_comb_rhs_array_muxed13[0:0]
end
- attribute \src "ls180.v:6842.1-6849.4"
- process $proc$ls180.v:6842$2260
+ attribute \src "ls180.v:6838.1-6845.4"
+ process $proc$ls180.v:6838$2260
assign { } { }
assign $0\builder_comb_rhs_array_muxed14[0:0] 1'0
- attribute \src "ls180.v:6844.2-6848.9"
+ attribute \src "ls180.v:6840.2-6844.9"
switch \builder_roundrobin0_grant
attribute \src "ls180.v:0.0-0.0"
case
- assign $0\builder_comb_rhs_array_muxed14[0:0] $and$ls180.v:6846$2273_Y
+ assign $0\builder_comb_rhs_array_muxed14[0:0] $and$ls180.v:6842$2273_Y
end
sync always
update \builder_comb_rhs_array_muxed14 $0\builder_comb_rhs_array_muxed14[0:0]
end
- attribute \src "ls180.v:6850.1-6857.4"
- process $proc$ls180.v:6850$2274
+ attribute \src "ls180.v:6846.1-6853.4"
+ process $proc$ls180.v:6846$2274
assign { } { }
assign $0\builder_comb_rhs_array_muxed15[21:0] 22'0000000000000000000000
- attribute \src "ls180.v:6852.2-6856.9"
+ attribute \src "ls180.v:6848.2-6852.9"
switch \builder_roundrobin1_grant
attribute \src "ls180.v:0.0-0.0"
case
sync always
update \builder_comb_rhs_array_muxed15 $0\builder_comb_rhs_array_muxed15[21:0]
end
- attribute \src "ls180.v:6858.1-6865.4"
- process $proc$ls180.v:6858$2275
+ attribute \src "ls180.v:6854.1-6861.4"
+ process $proc$ls180.v:6854$2275
assign { } { }
assign $0\builder_comb_rhs_array_muxed16[0:0] 1'0
- attribute \src "ls180.v:6860.2-6864.9"
+ attribute \src "ls180.v:6856.2-6860.9"
switch \builder_roundrobin1_grant
attribute \src "ls180.v:0.0-0.0"
case
sync always
update \builder_comb_rhs_array_muxed16 $0\builder_comb_rhs_array_muxed16[0:0]
end
- attribute \src "ls180.v:6866.1-6873.4"
- process $proc$ls180.v:6866$2276
+ attribute \src "ls180.v:6862.1-6869.4"
+ process $proc$ls180.v:6862$2276
assign { } { }
assign $0\builder_comb_rhs_array_muxed17[0:0] 1'0
- attribute \src "ls180.v:6868.2-6872.9"
+ attribute \src "ls180.v:6864.2-6868.9"
switch \builder_roundrobin1_grant
attribute \src "ls180.v:0.0-0.0"
case
- assign $0\builder_comb_rhs_array_muxed17[0:0] $and$ls180.v:6870$2289_Y
+ assign $0\builder_comb_rhs_array_muxed17[0:0] $and$ls180.v:6866$2289_Y
end
sync always
update \builder_comb_rhs_array_muxed17 $0\builder_comb_rhs_array_muxed17[0:0]
end
- attribute \src "ls180.v:6874.1-6881.4"
- process $proc$ls180.v:6874$2290
+ attribute \src "ls180.v:6870.1-6877.4"
+ process $proc$ls180.v:6870$2290
assign { } { }
assign $0\builder_comb_rhs_array_muxed18[21:0] 22'0000000000000000000000
- attribute \src "ls180.v:6876.2-6880.9"
+ attribute \src "ls180.v:6872.2-6876.9"
switch \builder_roundrobin2_grant
attribute \src "ls180.v:0.0-0.0"
case
sync always
update \builder_comb_rhs_array_muxed18 $0\builder_comb_rhs_array_muxed18[21:0]
end
- attribute \src "ls180.v:6882.1-6889.4"
- process $proc$ls180.v:6882$2291
+ attribute \src "ls180.v:6878.1-6885.4"
+ process $proc$ls180.v:6878$2291
assign { } { }
assign $0\builder_comb_rhs_array_muxed19[0:0] 1'0
- attribute \src "ls180.v:6884.2-6888.9"
+ attribute \src "ls180.v:6880.2-6884.9"
switch \builder_roundrobin2_grant
attribute \src "ls180.v:0.0-0.0"
case
sync always
update \builder_comb_rhs_array_muxed19 $0\builder_comb_rhs_array_muxed19[0:0]
end
- attribute \src "ls180.v:6890.1-6897.4"
- process $proc$ls180.v:6890$2292
+ attribute \src "ls180.v:6886.1-6893.4"
+ process $proc$ls180.v:6886$2292
assign { } { }
assign $0\builder_comb_rhs_array_muxed20[0:0] 1'0
- attribute \src "ls180.v:6892.2-6896.9"
+ attribute \src "ls180.v:6888.2-6892.9"
switch \builder_roundrobin2_grant
attribute \src "ls180.v:0.0-0.0"
case
- assign $0\builder_comb_rhs_array_muxed20[0:0] $and$ls180.v:6894$2305_Y
+ assign $0\builder_comb_rhs_array_muxed20[0:0] $and$ls180.v:6890$2305_Y
end
sync always
update \builder_comb_rhs_array_muxed20 $0\builder_comb_rhs_array_muxed20[0:0]
end
- attribute \src "ls180.v:6898.1-6905.4"
- process $proc$ls180.v:6898$2306
+ attribute \src "ls180.v:6894.1-6901.4"
+ process $proc$ls180.v:6894$2306
assign { } { }
assign $0\builder_comb_rhs_array_muxed21[21:0] 22'0000000000000000000000
- attribute \src "ls180.v:6900.2-6904.9"
+ attribute \src "ls180.v:6896.2-6900.9"
switch \builder_roundrobin3_grant
attribute \src "ls180.v:0.0-0.0"
case
sync always
update \builder_comb_rhs_array_muxed21 $0\builder_comb_rhs_array_muxed21[21:0]
end
- attribute \src "ls180.v:6906.1-6913.4"
- process $proc$ls180.v:6906$2307
+ attribute \src "ls180.v:690.11-690.68"
+ process $proc$ls180.v:690$3010
+ assign { } { }
+ assign $1\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] 4'0000
+ sync always
+ sync init
+ update \main_sdram_bankmachine3_cmd_buffer_lookahead_level $1\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0]
+ end
+ attribute \src "ls180.v:6902.1-6909.4"
+ process $proc$ls180.v:6902$2307
assign { } { }
assign $0\builder_comb_rhs_array_muxed22[0:0] 1'0
- attribute \src "ls180.v:6908.2-6912.9"
+ attribute \src "ls180.v:6904.2-6908.9"
switch \builder_roundrobin3_grant
attribute \src "ls180.v:0.0-0.0"
case
sync always
update \builder_comb_rhs_array_muxed22 $0\builder_comb_rhs_array_muxed22[0:0]
end
- attribute \src "ls180.v:6914.1-6921.4"
- process $proc$ls180.v:6914$2308
+ attribute \src "ls180.v:691.5-691.64"
+ process $proc$ls180.v:691$3011
+ assign { } { }
+ assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_replace[0:0] 1'0
+ sync always
+ update \main_sdram_bankmachine3_cmd_buffer_lookahead_replace $0\main_sdram_bankmachine3_cmd_buffer_lookahead_replace[0:0]
+ sync init
+ end
+ attribute \src "ls180.v:6910.1-6917.4"
+ process $proc$ls180.v:6910$2308
assign { } { }
assign $0\builder_comb_rhs_array_muxed23[0:0] 1'0
- attribute \src "ls180.v:6916.2-6920.9"
+ attribute \src "ls180.v:6912.2-6916.9"
switch \builder_roundrobin3_grant
attribute \src "ls180.v:0.0-0.0"
case
- assign $0\builder_comb_rhs_array_muxed23[0:0] $and$ls180.v:6918$2321_Y
+ assign $0\builder_comb_rhs_array_muxed23[0:0] $and$ls180.v:6914$2321_Y
end
sync always
update \builder_comb_rhs_array_muxed23 $0\builder_comb_rhs_array_muxed23[0:0]
end
- attribute \src "ls180.v:6922.1-6941.4"
- process $proc$ls180.v:6922$2322
+ attribute \src "ls180.v:6918.1-6937.4"
+ process $proc$ls180.v:6918$2322
assign { } { }
assign $0\builder_comb_rhs_array_muxed24[31:0] 0
- attribute \src "ls180.v:6924.2-6940.9"
+ attribute \src "ls180.v:6920.2-6936.9"
switch \builder_grant
attribute \src "ls180.v:0.0-0.0"
case 3'000
sync always
update \builder_comb_rhs_array_muxed24 $0\builder_comb_rhs_array_muxed24[31:0]
end
- attribute \src "ls180.v:694.11-694.68"
- process $proc$ls180.v:694$3010
+ attribute \src "ls180.v:692.11-692.70"
+ process $proc$ls180.v:692$3012
assign { } { }
- assign $1\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] 4'0000
+ assign $1\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] 3'000
sync always
sync init
- update \main_sdram_bankmachine3_cmd_buffer_lookahead_level $1\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0]
+ update \main_sdram_bankmachine3_cmd_buffer_lookahead_produce $1\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0]
+ end
+ attribute \src "ls180.v:693.11-693.70"
+ process $proc$ls180.v:693$3013
+ assign { } { }
+ assign $1\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] 3'000
+ sync always
+ sync init
+ update \main_sdram_bankmachine3_cmd_buffer_lookahead_consume $1\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0]
end
- attribute \src "ls180.v:6942.1-6961.4"
- process $proc$ls180.v:6942$2323
+ attribute \src "ls180.v:6938.1-6957.4"
+ process $proc$ls180.v:6938$2323
assign { } { }
assign $0\builder_comb_rhs_array_muxed25[31:0] 0
- attribute \src "ls180.v:6944.2-6960.9"
+ attribute \src "ls180.v:6940.2-6956.9"
switch \builder_grant
attribute \src "ls180.v:0.0-0.0"
case 3'000
sync always
update \builder_comb_rhs_array_muxed25 $0\builder_comb_rhs_array_muxed25[31:0]
end
- attribute \src "ls180.v:695.5-695.64"
- process $proc$ls180.v:695$3011
- assign { } { }
- assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_replace[0:0] 1'0
- sync always
- update \main_sdram_bankmachine3_cmd_buffer_lookahead_replace $0\main_sdram_bankmachine3_cmd_buffer_lookahead_replace[0:0]
- sync init
- end
- attribute \src "ls180.v:696.11-696.70"
- process $proc$ls180.v:696$3012
+ attribute \src "ls180.v:694.11-694.73"
+ process $proc$ls180.v:694$3014
assign { } { }
- assign $1\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] 3'000
+ assign $1\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] 3'000
sync always
sync init
- update \main_sdram_bankmachine3_cmd_buffer_lookahead_produce $1\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0]
+ update \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr $1\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0]
end
- attribute \src "ls180.v:6962.1-6981.4"
- process $proc$ls180.v:6962$2324
+ attribute \src "ls180.v:6958.1-6977.4"
+ process $proc$ls180.v:6958$2324
assign { } { }
assign $0\builder_comb_rhs_array_muxed26[3:0] 4'0000
- attribute \src "ls180.v:6964.2-6980.9"
+ attribute \src "ls180.v:6960.2-6976.9"
switch \builder_grant
attribute \src "ls180.v:0.0-0.0"
case 3'000
sync always
update \builder_comb_rhs_array_muxed26 $0\builder_comb_rhs_array_muxed26[3:0]
end
- attribute \src "ls180.v:697.11-697.70"
- process $proc$ls180.v:697$3013
- assign { } { }
- assign $1\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] 3'000
- sync always
- sync init
- update \main_sdram_bankmachine3_cmd_buffer_lookahead_consume $1\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0]
- end
- attribute \src "ls180.v:698.11-698.73"
- process $proc$ls180.v:698$3014
- assign { } { }
- assign $1\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] 3'000
- sync always
- sync init
- update \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr $1\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0]
- end
- attribute \src "ls180.v:6982.1-7001.4"
- process $proc$ls180.v:6982$2325
+ attribute \src "ls180.v:6978.1-6997.4"
+ process $proc$ls180.v:6978$2325
assign { } { }
assign $0\builder_comb_rhs_array_muxed27[0:0] 1'0
- attribute \src "ls180.v:6984.2-7000.9"
+ attribute \src "ls180.v:6980.2-6996.9"
switch \builder_grant
attribute \src "ls180.v:0.0-0.0"
case 3'000
sync always
update \builder_comb_rhs_array_muxed27 $0\builder_comb_rhs_array_muxed27[0:0]
end
- attribute \src "ls180.v:7002.1-7021.4"
- process $proc$ls180.v:7002$2326
+ attribute \src "ls180.v:6998.1-7017.4"
+ process $proc$ls180.v:6998$2326
assign { } { }
assign $0\builder_comb_rhs_array_muxed28[0:0] 1'0
- attribute \src "ls180.v:7004.2-7020.9"
+ attribute \src "ls180.v:7000.2-7016.9"
switch \builder_grant
attribute \src "ls180.v:0.0-0.0"
case 3'000
sync always
update \builder_comb_rhs_array_muxed28 $0\builder_comb_rhs_array_muxed28[0:0]
end
- attribute \src "ls180.v:7022.1-7041.4"
- process $proc$ls180.v:7022$2327
+ attribute \src "ls180.v:7018.1-7037.4"
+ process $proc$ls180.v:7018$2327
assign { } { }
assign $0\builder_comb_rhs_array_muxed29[0:0] 1'0
- attribute \src "ls180.v:7024.2-7040.9"
+ attribute \src "ls180.v:7020.2-7036.9"
switch \builder_grant
attribute \src "ls180.v:0.0-0.0"
case 3'000
sync always
update \builder_comb_rhs_array_muxed29 $0\builder_comb_rhs_array_muxed29[0:0]
end
- attribute \src "ls180.v:7042.1-7061.4"
- process $proc$ls180.v:7042$2328
+ attribute \src "ls180.v:7038.1-7057.4"
+ process $proc$ls180.v:7038$2328
assign { } { }
assign $0\builder_comb_rhs_array_muxed30[2:0] 3'000
- attribute \src "ls180.v:7044.2-7060.9"
+ attribute \src "ls180.v:7040.2-7056.9"
switch \builder_grant
attribute \src "ls180.v:0.0-0.0"
case 3'000
sync always
update \builder_comb_rhs_array_muxed30 $0\builder_comb_rhs_array_muxed30[2:0]
end
- attribute \src "ls180.v:7062.1-7081.4"
- process $proc$ls180.v:7062$2329
+ attribute \src "ls180.v:7058.1-7077.4"
+ process $proc$ls180.v:7058$2329
assign { } { }
assign $0\builder_comb_rhs_array_muxed31[1:0] 2'00
- attribute \src "ls180.v:7064.2-7080.9"
+ attribute \src "ls180.v:7060.2-7076.9"
switch \builder_grant
attribute \src "ls180.v:0.0-0.0"
case 3'000
sync always
update \builder_comb_rhs_array_muxed31 $0\builder_comb_rhs_array_muxed31[1:0]
end
- attribute \src "ls180.v:7082.1-7098.4"
- process $proc$ls180.v:7082$2330
+ attribute \src "ls180.v:7078.1-7094.4"
+ process $proc$ls180.v:7078$2330
assign { } { }
assign $0\builder_sync_rhs_array_muxed0[1:0] 2'00
- attribute \src "ls180.v:7084.2-7097.9"
+ attribute \src "ls180.v:7080.2-7093.9"
switch \main_sdram_steerer_sel
attribute \src "ls180.v:0.0-0.0"
case 2'00
sync always
update \builder_sync_rhs_array_muxed0 $0\builder_sync_rhs_array_muxed0[1:0]
end
- attribute \src "ls180.v:7099.1-7115.4"
- process $proc$ls180.v:7099$2331
+ attribute \src "ls180.v:7095.1-7111.4"
+ process $proc$ls180.v:7095$2331
assign { } { }
assign $0\builder_sync_rhs_array_muxed1[12:0] 13'0000000000000
- attribute \src "ls180.v:7101.2-7114.9"
+ attribute \src "ls180.v:7097.2-7110.9"
switch \main_sdram_steerer_sel
attribute \src "ls180.v:0.0-0.0"
case 2'00
sync always
update \builder_sync_rhs_array_muxed1 $0\builder_sync_rhs_array_muxed1[12:0]
end
- attribute \src "ls180.v:7116.1-7132.4"
- process $proc$ls180.v:7116$2332
+ attribute \src "ls180.v:7112.1-7128.4"
+ process $proc$ls180.v:7112$2332
assign { } { }
assign $0\builder_sync_rhs_array_muxed2[0:0] 1'0
- attribute \src "ls180.v:7118.2-7131.9"
+ attribute \src "ls180.v:7114.2-7127.9"
switch \main_sdram_steerer_sel
attribute \src "ls180.v:0.0-0.0"
case 2'00
assign $0\builder_sync_rhs_array_muxed2[0:0] 1'0
attribute \src "ls180.v:0.0-0.0"
case 2'01
- assign $0\builder_sync_rhs_array_muxed2[0:0] $and$ls180.v:7123$2334_Y
+ assign $0\builder_sync_rhs_array_muxed2[0:0] $and$ls180.v:7119$2334_Y
attribute \src "ls180.v:0.0-0.0"
case 2'10
- assign $0\builder_sync_rhs_array_muxed2[0:0] $and$ls180.v:7126$2336_Y
+ assign $0\builder_sync_rhs_array_muxed2[0:0] $and$ls180.v:7122$2336_Y
attribute \src "ls180.v:0.0-0.0"
case
- assign $0\builder_sync_rhs_array_muxed2[0:0] $and$ls180.v:7129$2338_Y
+ assign $0\builder_sync_rhs_array_muxed2[0:0] $and$ls180.v:7125$2338_Y
end
sync always
update \builder_sync_rhs_array_muxed2 $0\builder_sync_rhs_array_muxed2[0:0]
end
- attribute \src "ls180.v:7133.1-7149.4"
- process $proc$ls180.v:7133$2339
+ attribute \src "ls180.v:7129.1-7145.4"
+ process $proc$ls180.v:7129$2339
assign { } { }
assign $0\builder_sync_rhs_array_muxed3[0:0] 1'0
- attribute \src "ls180.v:7135.2-7148.9"
+ attribute \src "ls180.v:7131.2-7144.9"
switch \main_sdram_steerer_sel
attribute \src "ls180.v:0.0-0.0"
case 2'00
assign $0\builder_sync_rhs_array_muxed3[0:0] 1'0
attribute \src "ls180.v:0.0-0.0"
case 2'01
- assign $0\builder_sync_rhs_array_muxed3[0:0] $and$ls180.v:7140$2341_Y
+ assign $0\builder_sync_rhs_array_muxed3[0:0] $and$ls180.v:7136$2341_Y
attribute \src "ls180.v:0.0-0.0"
case 2'10
- assign $0\builder_sync_rhs_array_muxed3[0:0] $and$ls180.v:7143$2343_Y
+ assign $0\builder_sync_rhs_array_muxed3[0:0] $and$ls180.v:7139$2343_Y
attribute \src "ls180.v:0.0-0.0"
case
- assign $0\builder_sync_rhs_array_muxed3[0:0] $and$ls180.v:7146$2345_Y
+ assign $0\builder_sync_rhs_array_muxed3[0:0] $and$ls180.v:7142$2345_Y
end
sync always
update \builder_sync_rhs_array_muxed3 $0\builder_sync_rhs_array_muxed3[0:0]
end
- attribute \src "ls180.v:7150.1-7166.4"
- process $proc$ls180.v:7150$2346
+ attribute \src "ls180.v:7146.1-7162.4"
+ process $proc$ls180.v:7146$2346
assign { } { }
assign $0\builder_sync_rhs_array_muxed4[0:0] 1'0
- attribute \src "ls180.v:7152.2-7165.9"
+ attribute \src "ls180.v:7148.2-7161.9"
switch \main_sdram_steerer_sel
attribute \src "ls180.v:0.0-0.0"
case 2'00
assign $0\builder_sync_rhs_array_muxed4[0:0] 1'0
attribute \src "ls180.v:0.0-0.0"
case 2'01
- assign $0\builder_sync_rhs_array_muxed4[0:0] $and$ls180.v:7157$2348_Y
+ assign $0\builder_sync_rhs_array_muxed4[0:0] $and$ls180.v:7153$2348_Y
attribute \src "ls180.v:0.0-0.0"
case 2'10
- assign $0\builder_sync_rhs_array_muxed4[0:0] $and$ls180.v:7160$2350_Y
+ assign $0\builder_sync_rhs_array_muxed4[0:0] $and$ls180.v:7156$2350_Y
attribute \src "ls180.v:0.0-0.0"
case
- assign $0\builder_sync_rhs_array_muxed4[0:0] $and$ls180.v:7163$2352_Y
+ assign $0\builder_sync_rhs_array_muxed4[0:0] $and$ls180.v:7159$2352_Y
end
sync always
update \builder_sync_rhs_array_muxed4 $0\builder_sync_rhs_array_muxed4[0:0]
end
- attribute \src "ls180.v:7167.1-7183.4"
- process $proc$ls180.v:7167$2353
+ attribute \src "ls180.v:715.5-715.59"
+ process $proc$ls180.v:715$3015
+ assign { } { }
+ assign $1\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] 1'0
+ sync always
+ sync init
+ update \main_sdram_bankmachine3_cmd_buffer_source_valid $1\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0]
+ end
+ attribute \src "ls180.v:7163.1-7179.4"
+ process $proc$ls180.v:7163$2353
assign { } { }
assign $0\builder_sync_rhs_array_muxed5[0:0] 1'0
- attribute \src "ls180.v:7169.2-7182.9"
+ attribute \src "ls180.v:7165.2-7178.9"
switch \main_sdram_steerer_sel
attribute \src "ls180.v:0.0-0.0"
case 2'00
assign $0\builder_sync_rhs_array_muxed5[0:0] 1'0
attribute \src "ls180.v:0.0-0.0"
case 2'01
- assign $0\builder_sync_rhs_array_muxed5[0:0] $and$ls180.v:7174$2355_Y
+ assign $0\builder_sync_rhs_array_muxed5[0:0] $and$ls180.v:7170$2355_Y
attribute \src "ls180.v:0.0-0.0"
case 2'10
- assign $0\builder_sync_rhs_array_muxed5[0:0] $and$ls180.v:7177$2357_Y
+ assign $0\builder_sync_rhs_array_muxed5[0:0] $and$ls180.v:7173$2357_Y
attribute \src "ls180.v:0.0-0.0"
case
- assign $0\builder_sync_rhs_array_muxed5[0:0] $and$ls180.v:7180$2359_Y
+ assign $0\builder_sync_rhs_array_muxed5[0:0] $and$ls180.v:7176$2359_Y
end
sync always
update \builder_sync_rhs_array_muxed5 $0\builder_sync_rhs_array_muxed5[0:0]
end
- attribute \src "ls180.v:7184.1-7200.4"
- process $proc$ls180.v:7184$2360
+ attribute \src "ls180.v:717.5-717.59"
+ process $proc$ls180.v:717$3016
+ assign { } { }
+ assign $1\main_sdram_bankmachine3_cmd_buffer_source_first[0:0] 1'0
+ sync always
+ sync init
+ update \main_sdram_bankmachine3_cmd_buffer_source_first $1\main_sdram_bankmachine3_cmd_buffer_source_first[0:0]
+ end
+ attribute \src "ls180.v:718.5-718.58"
+ process $proc$ls180.v:718$3017
+ assign { } { }
+ assign $1\main_sdram_bankmachine3_cmd_buffer_source_last[0:0] 1'0
+ sync always
+ sync init
+ update \main_sdram_bankmachine3_cmd_buffer_source_last $1\main_sdram_bankmachine3_cmd_buffer_source_last[0:0]
+ end
+ attribute \src "ls180.v:7180.1-7196.4"
+ process $proc$ls180.v:7180$2360
assign { } { }
assign $0\builder_sync_rhs_array_muxed6[0:0] 1'0
- attribute \src "ls180.v:7186.2-7199.9"
+ attribute \src "ls180.v:7182.2-7195.9"
switch \main_sdram_steerer_sel
attribute \src "ls180.v:0.0-0.0"
case 2'00
assign $0\builder_sync_rhs_array_muxed6[0:0] 1'0
attribute \src "ls180.v:0.0-0.0"
case 2'01
- assign $0\builder_sync_rhs_array_muxed6[0:0] $and$ls180.v:7191$2362_Y
+ assign $0\builder_sync_rhs_array_muxed6[0:0] $and$ls180.v:7187$2362_Y
attribute \src "ls180.v:0.0-0.0"
case 2'10
- assign $0\builder_sync_rhs_array_muxed6[0:0] $and$ls180.v:7194$2364_Y
+ assign $0\builder_sync_rhs_array_muxed6[0:0] $and$ls180.v:7190$2364_Y
attribute \src "ls180.v:0.0-0.0"
case
- assign $0\builder_sync_rhs_array_muxed6[0:0] $and$ls180.v:7197$2366_Y
+ assign $0\builder_sync_rhs_array_muxed6[0:0] $and$ls180.v:7193$2366_Y
end
sync always
update \builder_sync_rhs_array_muxed6 $0\builder_sync_rhs_array_muxed6[0:0]
end
- attribute \src "ls180.v:719.5-719.59"
- process $proc$ls180.v:719$3015
- assign { } { }
- assign $1\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] 1'0
- sync always
- sync init
- update \main_sdram_bankmachine3_cmd_buffer_source_valid $1\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0]
- end
- attribute \src "ls180.v:72.5-72.46"
- process $proc$ls180.v:72$2769
+ attribute \src "ls180.v:719.5-719.64"
+ process $proc$ls180.v:719$3018
assign { } { }
- assign $1\main_libresocsim_libresoc_dbus_ack[0:0] 1'0
+ assign $1\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] 1'0
sync always
sync init
- update \main_libresocsim_libresoc_dbus_ack $1\main_libresocsim_libresoc_dbus_ack[0:0]
+ update \main_sdram_bankmachine3_cmd_buffer_source_payload_we $1\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0]
end
- attribute \src "ls180.v:7201.1-7229.4"
- process $proc$ls180.v:7201$2367
+ attribute \src "ls180.v:7197.1-7225.4"
+ process $proc$ls180.v:7197$2367
assign { } { }
assign $0\builder_sync_f_array_muxed0[0:0] 1'0
- attribute \src "ls180.v:7203.2-7228.9"
+ attribute \src "ls180.v:7199.2-7224.9"
switch \main_spimaster34_mosi_sel
attribute \src "ls180.v:0.0-0.0"
case 3'000
sync always
update \builder_sync_f_array_muxed0 $0\builder_sync_f_array_muxed0[0:0]
end
- attribute \src "ls180.v:721.5-721.59"
- process $proc$ls180.v:721$3016
+ attribute \src "ls180.v:72.5-72.46"
+ process $proc$ls180.v:72$2769
assign { } { }
- assign $1\main_sdram_bankmachine3_cmd_buffer_source_first[0:0] 1'0
+ assign $1\main_libresocsim_libresoc_dbus_ack[0:0] 1'0
sync always
sync init
- update \main_sdram_bankmachine3_cmd_buffer_source_first $1\main_sdram_bankmachine3_cmd_buffer_source_first[0:0]
+ update \main_libresocsim_libresoc_dbus_ack $1\main_libresocsim_libresoc_dbus_ack[0:0]
end
- attribute \src "ls180.v:722.5-722.58"
- process $proc$ls180.v:722$3017
+ attribute \src "ls180.v:720.12-720.74"
+ process $proc$ls180.v:720$3019
assign { } { }
- assign $1\main_sdram_bankmachine3_cmd_buffer_source_last[0:0] 1'0
+ assign $1\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000
sync always
sync init
- update \main_sdram_bankmachine3_cmd_buffer_source_last $1\main_sdram_bankmachine3_cmd_buffer_source_last[0:0]
+ update \main_sdram_bankmachine3_cmd_buffer_source_payload_addr $1\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0]
end
- attribute \src "ls180.v:723.5-723.64"
- process $proc$ls180.v:723$3018
+ attribute \src "ls180.v:721.12-721.47"
+ process $proc$ls180.v:721$3020
assign { } { }
- assign $1\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] 1'0
+ assign $1\main_sdram_bankmachine3_row[12:0] 13'0000000000000
sync always
sync init
- update \main_sdram_bankmachine3_cmd_buffer_source_payload_we $1\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0]
+ update \main_sdram_bankmachine3_row $1\main_sdram_bankmachine3_row[12:0]
+ end
+ attribute \src "ls180.v:722.5-722.46"
+ process $proc$ls180.v:722$3021
+ assign { } { }
+ assign $1\main_sdram_bankmachine3_row_opened[0:0] 1'0
+ sync always
+ sync init
+ update \main_sdram_bankmachine3_row_opened $1\main_sdram_bankmachine3_row_opened[0:0]
end
- attribute \src "ls180.v:7230.1-7258.4"
- process $proc$ls180.v:7230$2368
+ attribute \src "ls180.v:7226.1-7254.4"
+ process $proc$ls180.v:7226$2368
assign { } { }
assign $0\builder_sync_f_array_muxed1[0:0] 1'0
- attribute \src "ls180.v:7232.2-7257.9"
+ attribute \src "ls180.v:7228.2-7253.9"
switch \main_spisdcard_mosi_sel
attribute \src "ls180.v:0.0-0.0"
case 3'000
sync always
update \builder_sync_f_array_muxed1 $0\builder_sync_f_array_muxed1[0:0]
end
- attribute \src "ls180.v:724.12-724.74"
- process $proc$ls180.v:724$3019
+ attribute \src "ls180.v:724.5-724.44"
+ process $proc$ls180.v:724$3022
assign { } { }
- assign $1\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000
+ assign $1\main_sdram_bankmachine3_row_open[0:0] 1'0
sync always
sync init
- update \main_sdram_bankmachine3_cmd_buffer_source_payload_addr $1\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0]
+ update \main_sdram_bankmachine3_row_open $1\main_sdram_bankmachine3_row_open[0:0]
end
- attribute \src "ls180.v:725.12-725.47"
- process $proc$ls180.v:725$3020
+ attribute \src "ls180.v:725.5-725.45"
+ process $proc$ls180.v:725$3023
assign { } { }
- assign $1\main_sdram_bankmachine3_row[12:0] 13'0000000000000
+ assign $1\main_sdram_bankmachine3_row_close[0:0] 1'0
sync always
sync init
- update \main_sdram_bankmachine3_row $1\main_sdram_bankmachine3_row[12:0]
+ update \main_sdram_bankmachine3_row_close $1\main_sdram_bankmachine3_row_close[0:0]
end
- attribute \src "ls180.v:726.5-726.46"
- process $proc$ls180.v:726$3021
+ attribute \src "ls180.v:726.5-726.54"
+ process $proc$ls180.v:726$3024
assign { } { }
- assign $1\main_sdram_bankmachine3_row_opened[0:0] 1'0
+ assign $1\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] 1'0
sync always
sync init
- update \main_sdram_bankmachine3_row_opened $1\main_sdram_bankmachine3_row_opened[0:0]
+ update \main_sdram_bankmachine3_row_col_n_addr_sel $1\main_sdram_bankmachine3_row_col_n_addr_sel[0:0]
end
- attribute \src "ls180.v:728.5-728.44"
- process $proc$ls180.v:728$3022
+ attribute \src "ls180.v:728.32-728.76"
+ process $proc$ls180.v:728$3025
assign { } { }
- assign $1\main_sdram_bankmachine3_row_open[0:0] 1'0
+ assign $1\main_sdram_bankmachine3_twtpcon_ready[0:0] 1'0
sync always
sync init
- update \main_sdram_bankmachine3_row_open $1\main_sdram_bankmachine3_row_open[0:0]
+ update \main_sdram_bankmachine3_twtpcon_ready $1\main_sdram_bankmachine3_twtpcon_ready[0:0]
end
- attribute \src "ls180.v:729.5-729.45"
- process $proc$ls180.v:729$3023
+ attribute \src "ls180.v:729.11-729.55"
+ process $proc$ls180.v:729$3026
assign { } { }
- assign $1\main_sdram_bankmachine3_row_close[0:0] 1'0
+ assign $1\main_sdram_bankmachine3_twtpcon_count[2:0] 3'000
sync always
sync init
- update \main_sdram_bankmachine3_row_close $1\main_sdram_bankmachine3_row_close[0:0]
+ update \main_sdram_bankmachine3_twtpcon_count $1\main_sdram_bankmachine3_twtpcon_count[2:0]
end
- attribute \src "ls180.v:730.5-730.54"
- process $proc$ls180.v:730$3024
+ attribute \src "ls180.v:731.32-731.75"
+ process $proc$ls180.v:731$3027
assign { } { }
- assign $1\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] 1'0
+ assign $0\main_sdram_bankmachine3_trccon_ready[0:0] 1'1
sync always
+ update \main_sdram_bankmachine3_trccon_ready $0\main_sdram_bankmachine3_trccon_ready[0:0]
sync init
- update \main_sdram_bankmachine3_row_col_n_addr_sel $1\main_sdram_bankmachine3_row_col_n_addr_sel[0:0]
end
- attribute \src "ls180.v:7316.1-7334.4"
- process $proc$ls180.v:7316$2369
+ attribute \src "ls180.v:7312.1-7330.4"
+ process $proc$ls180.v:7312$2369
assign { } { }
assign { } { }
assign $0\main_gpio_status[15:0] [0] \builder_multiregimpl1_regs1
sync always
update \main_gpio_status $0\main_gpio_status[15:0]
end
- attribute \src "ls180.v:732.32-732.76"
- process $proc$ls180.v:732$3025
+ attribute \src "ls180.v:733.32-733.76"
+ process $proc$ls180.v:733$3028
assign { } { }
- assign $1\main_sdram_bankmachine3_twtpcon_ready[0:0] 1'0
- sync always
- sync init
- update \main_sdram_bankmachine3_twtpcon_ready $1\main_sdram_bankmachine3_twtpcon_ready[0:0]
- end
- attribute \src "ls180.v:733.11-733.55"
- process $proc$ls180.v:733$3026
- assign { } { }
- assign $1\main_sdram_bankmachine3_twtpcon_count[2:0] 3'000
- sync always
- sync init
- update \main_sdram_bankmachine3_twtpcon_count $1\main_sdram_bankmachine3_twtpcon_count[2:0]
- end
- attribute \src "ls180.v:735.32-735.75"
- process $proc$ls180.v:735$3027
- assign { } { }
- assign $0\main_sdram_bankmachine3_trccon_ready[0:0] 1'1
+ assign $0\main_sdram_bankmachine3_trascon_ready[0:0] 1'1
sync always
- update \main_sdram_bankmachine3_trccon_ready $0\main_sdram_bankmachine3_trccon_ready[0:0]
+ update \main_sdram_bankmachine3_trascon_ready $0\main_sdram_bankmachine3_trascon_ready[0:0]
sync init
end
- attribute \src "ls180.v:7355.1-7357.4"
- process $proc$ls180.v:7355$2370
+ attribute \src "ls180.v:7351.1-7353.4"
+ process $proc$ls180.v:7351$2370
assign { } { }
assign $0\main_int_rst[0:0] \sys_rst
sync posedge \por_clk
update \main_int_rst $0\main_int_rst[0:0]
end
- attribute \src "ls180.v:7359.1-7429.4"
- process $proc$ls180.v:7359$2371
+ attribute \src "ls180.v:7355.1-7425.4"
+ process $proc$ls180.v:7355$2371
assign { } { }
assign { } { }
assign { } { }
assign $0\sdram_dm[1:0] [0] \main_dfi_p0_wrdata_mask [0]
assign $0\sdram_dm[1:0] [1] \main_dfi_p0_wrdata_mask [1]
assign $0\sdram_clock[0:0] \sys_clk_1
- assign $0\sdcard_clk[0:0] $and$ls180.v:7416$2373_Y
+ assign $0\sdcard_clk[0:0] $and$ls180.v:7412$2373_Y
assign $0\sdcard_cmd_oe[0:0] \main_sdphy_sdpads_cmd_oe
assign $0\sdcard_cmd_o[0:0] \main_sdphy_sdpads_cmd_o
assign $0\main_sdphy_sdpads_cmd_i[0:0] \sdcard_cmd_i
update \main_sdphy_sdpads_cmd_i $0\main_sdphy_sdpads_cmd_i[0:0]
update \main_sdphy_sdpads_data_i $0\main_sdphy_sdpads_data_i[3:0]
end
- attribute \src "ls180.v:737.32-737.76"
- process $proc$ls180.v:737$3028
- assign { } { }
- assign $0\main_sdram_bankmachine3_trascon_ready[0:0] 1'1
- sync always
- update \main_sdram_bankmachine3_trascon_ready $0\main_sdram_bankmachine3_trascon_ready[0:0]
- sync init
- end
- attribute \src "ls180.v:740.5-740.44"
- process $proc$ls180.v:740$3029
+ attribute \src "ls180.v:736.5-736.44"
+ process $proc$ls180.v:736$3029
assign { } { }
assign $0\main_sdram_choose_cmd_want_reads[0:0] 1'0
sync always
update \main_sdram_choose_cmd_want_reads $0\main_sdram_choose_cmd_want_reads[0:0]
sync init
end
- attribute \src "ls180.v:741.5-741.45"
- process $proc$ls180.v:741$3030
+ attribute \src "ls180.v:737.5-737.45"
+ process $proc$ls180.v:737$3030
assign { } { }
assign $0\main_sdram_choose_cmd_want_writes[0:0] 1'0
sync always
update \main_sdram_choose_cmd_want_writes $0\main_sdram_choose_cmd_want_writes[0:0]
sync init
end
- attribute \src "ls180.v:742.5-742.43"
- process $proc$ls180.v:742$3031
+ attribute \src "ls180.v:738.5-738.43"
+ process $proc$ls180.v:738$3031
assign { } { }
assign $0\main_sdram_choose_cmd_want_cmds[0:0] 1'0
sync always
update \main_sdram_choose_cmd_want_cmds $0\main_sdram_choose_cmd_want_cmds[0:0]
sync init
end
- attribute \src "ls180.v:743.5-743.48"
- process $proc$ls180.v:743$3032
+ attribute \src "ls180.v:739.5-739.48"
+ process $proc$ls180.v:739$3032
assign { } { }
assign $0\main_sdram_choose_cmd_want_activates[0:0] 1'0
sync always
update \main_sdram_choose_cmd_want_activates $0\main_sdram_choose_cmd_want_activates[0:0]
sync init
end
- attribute \src "ls180.v:7431.1-10043.4"
- process $proc$ls180.v:7431$2374
- assign $0\pwm[1:0] \pwm
- assign $0\uart_tx[0:0] \uart_tx
- assign $0\spimaster_clk[0:0] \spimaster_clk
- assign $0\spimaster_mosi[0:0] \spimaster_mosi
+ attribute \src "ls180.v:74.5-74.46"
+ process $proc$ls180.v:74$2770
assign { } { }
+ assign $0\main_libresocsim_libresoc_dbus_err[0:0] 1'0
+ sync always
+ update \main_libresocsim_libresoc_dbus_err $0\main_libresocsim_libresoc_dbus_err[0:0]
+ sync init
+ end
+ attribute \src "ls180.v:741.5-741.43"
+ process $proc$ls180.v:741$3033
+ assign { } { }
+ assign $0\main_sdram_choose_cmd_cmd_ready[0:0] 1'0
+ sync always
+ update \main_sdram_choose_cmd_cmd_ready $0\main_sdram_choose_cmd_cmd_ready[0:0]
+ sync init
+ end
+ attribute \src "ls180.v:7427.1-10039.4"
+ process $proc$ls180.v:7427$2374
+ assign $0\pwm[1:0] \pwm
assign $0\spisdcard_clk[0:0] \spisdcard_clk
assign $0\spisdcard_mosi[0:0] \spisdcard_mosi
assign { } { }
+ assign $0\spimaster_clk[0:0] \spimaster_clk
+ assign $0\spimaster_mosi[0:0] \spimaster_mosi
+ assign { } { }
+ assign $0\uart_tx[0:0] \uart_tx
assign $0\main_libresocsim_reset_storage[0:0] \main_libresocsim_reset_storage
assign { } { }
assign $0\main_libresocsim_scratch_storage[31:0] \main_libresocsim_scratch_storage
assign { } { }
assign { } { }
assign { } { }
- assign $0\main_dummy[23:0] [0] $or$ls180.v:7432$2375_Y
- assign $0\main_dummy[23:0] [1] $or$ls180.v:7433$2376_Y
- assign $0\main_dummy[23:0] [2] $or$ls180.v:7434$2377_Y
- assign $0\main_dummy[23:0] [3] $or$ls180.v:7435$2378_Y
- assign $0\main_dummy[23:0] [4] $or$ls180.v:7436$2379_Y
- assign $0\main_dummy[23:0] [5] $or$ls180.v:7437$2380_Y
- assign $0\main_dummy[23:0] [6] $or$ls180.v:7438$2381_Y
- assign $0\main_dummy[23:0] [7] $or$ls180.v:7439$2382_Y
- assign $0\main_dummy[23:0] [8] $or$ls180.v:7440$2383_Y
- assign $0\main_dummy[23:0] [9] $or$ls180.v:7441$2384_Y
- assign $0\main_dummy[23:0] [10] $or$ls180.v:7442$2385_Y
- assign $0\main_dummy[23:0] [11] $or$ls180.v:7443$2386_Y
- assign $0\main_dummy[23:0] [12] $or$ls180.v:7444$2387_Y
- assign $0\main_dummy[23:0] [13] $or$ls180.v:7445$2388_Y
- assign $0\main_dummy[23:0] [14] $or$ls180.v:7446$2389_Y
- assign $0\main_dummy[23:0] [15] $or$ls180.v:7447$2390_Y
- assign $0\main_dummy[23:0] [16] $or$ls180.v:7448$2391_Y
- assign $0\main_dummy[23:0] [17] $or$ls180.v:7449$2392_Y
- assign $0\main_dummy[23:0] [18] $or$ls180.v:7450$2393_Y
- assign $0\main_dummy[23:0] [19] $or$ls180.v:7451$2394_Y
- assign $0\main_dummy[23:0] [20] $or$ls180.v:7452$2395_Y
- assign $0\main_dummy[23:0] [21] $or$ls180.v:7453$2396_Y
- assign $0\main_dummy[23:0] [22] $or$ls180.v:7454$2397_Y
- assign $0\main_dummy[23:0] [23] $or$ls180.v:7455$2398_Y
+ assign $0\main_dummy[23:0] [0] $or$ls180.v:7428$2375_Y
+ assign $0\main_dummy[23:0] [1] $or$ls180.v:7429$2376_Y
+ assign $0\main_dummy[23:0] [2] $or$ls180.v:7430$2377_Y
+ assign $0\main_dummy[23:0] [3] $or$ls180.v:7431$2378_Y
+ assign $0\main_dummy[23:0] [4] $or$ls180.v:7432$2379_Y
+ assign $0\main_dummy[23:0] [5] $or$ls180.v:7433$2380_Y
+ assign $0\main_dummy[23:0] [6] $or$ls180.v:7434$2381_Y
+ assign $0\main_dummy[23:0] [7] $or$ls180.v:7435$2382_Y
+ assign $0\main_dummy[23:0] [8] $or$ls180.v:7436$2383_Y
+ assign $0\main_dummy[23:0] [9] $or$ls180.v:7437$2384_Y
+ assign $0\main_dummy[23:0] [10] $or$ls180.v:7438$2385_Y
+ assign $0\main_dummy[23:0] [11] $or$ls180.v:7439$2386_Y
+ assign $0\main_dummy[23:0] [12] $or$ls180.v:7440$2387_Y
+ assign $0\main_dummy[23:0] [13] $or$ls180.v:7441$2388_Y
+ assign $0\main_dummy[23:0] [14] $or$ls180.v:7442$2389_Y
+ assign $0\main_dummy[23:0] [15] $or$ls180.v:7443$2390_Y
+ assign $0\main_dummy[23:0] [16] $or$ls180.v:7444$2391_Y
+ assign $0\main_dummy[23:0] [17] $or$ls180.v:7445$2392_Y
+ assign $0\main_dummy[23:0] [18] $or$ls180.v:7446$2393_Y
+ assign $0\main_dummy[23:0] [19] $or$ls180.v:7447$2394_Y
+ assign $0\main_dummy[23:0] [20] $or$ls180.v:7448$2395_Y
+ assign $0\main_dummy[23:0] [21] $or$ls180.v:7449$2396_Y
+ assign $0\main_dummy[23:0] [22] $or$ls180.v:7450$2397_Y
+ assign $0\main_dummy[23:0] [23] $or$ls180.v:7451$2398_Y
assign $0\builder_converter0_state[0:0] \builder_converter0_next_state
assign $0\builder_converter1_state[0:0] \builder_converter1_next_state
assign $0\builder_converter2_state[0:0] \builder_converter2_next_state
assign $0\main_sdram_dfi_p0_cs_n[0:0] 1'0
assign $0\main_sdram_dfi_p0_bank[1:0] \builder_sync_rhs_array_muxed0
assign $0\main_sdram_dfi_p0_address[12:0] \builder_sync_rhs_array_muxed1
- assign $0\main_sdram_dfi_p0_cas_n[0:0] $not$ls180.v:7897$2495_Y
- assign $0\main_sdram_dfi_p0_ras_n[0:0] $not$ls180.v:7898$2496_Y
- assign $0\main_sdram_dfi_p0_we_n[0:0] $not$ls180.v:7899$2497_Y
+ assign $0\main_sdram_dfi_p0_cas_n[0:0] $not$ls180.v:7893$2495_Y
+ assign $0\main_sdram_dfi_p0_ras_n[0:0] $not$ls180.v:7894$2496_Y
+ assign $0\main_sdram_dfi_p0_we_n[0:0] $not$ls180.v:7895$2497_Y
assign $0\main_sdram_dfi_p0_rddata_en[0:0] \builder_sync_rhs_array_muxed5
assign $0\main_sdram_dfi_p0_wrdata_en[0:0] \builder_sync_rhs_array_muxed6
assign $0\builder_multiplexer_state[2:0] \builder_multiplexer_next_state
- assign $0\builder_new_master_wdata_ready[0:0] $or$ls180.v:7933$2515_Y
- assign $0\builder_new_master_rdata_valid0[0:0] $or$ls180.v:7934$2527_Y
+ assign $0\builder_new_master_wdata_ready[0:0] $or$ls180.v:7929$2515_Y
+ assign $0\builder_new_master_rdata_valid0[0:0] $or$ls180.v:7930$2527_Y
assign $0\builder_new_master_rdata_valid1[0:0] \builder_new_master_rdata_valid0
assign $0\builder_new_master_rdata_valid2[0:0] \builder_new_master_rdata_valid1
assign $0\builder_new_master_rdata_valid3[0:0] \builder_new_master_rdata_valid2
assign $0\main_uart_phy_rx_r[0:0] \main_uart_phy_rx
assign $0\main_uart_tx_old_trigger[0:0] \main_uart_tx_trigger
assign $0\main_uart_rx_old_trigger[0:0] \main_uart_rx_trigger
- assign $0\main_spimaster30_clk_divider[15:0] $add$ls180.v:8092$2573_Y
- assign $0\spisdcard_cs_n[0:0] $or$ls180.v:8101$2576_Y
+ assign $0\main_spimaster30_clk_divider[15:0] $add$ls180.v:8088$2573_Y
+ assign $0\spisdcard_cs_n[0:0] $or$ls180.v:8097$2576_Y
assign $0\builder_spimaster0_state[1:0] \builder_spimaster0_next_state
- assign $0\main_spisdcard_clk_divider1[15:0] $add$ls180.v:8127$2578_Y
- assign $0\spimaster_cs_n[0:0] $or$ls180.v:8136$2581_Y
+ assign $0\main_spisdcard_clk_divider1[15:0] $add$ls180.v:8123$2578_Y
+ assign $0\spimaster_cs_n[0:0] $or$ls180.v:8132$2581_Y
assign $0\builder_spimaster1_state[1:0] \builder_spimaster1_next_state
assign $0\main_sdphy_clocker_clk_d[0:0] \main_sdphy_clocker_clk1
assign $0\main_sdphy_clocker_clk0[0:0] \main_sdphy_clocker_clk1
assign $0\builder_multiregimpl15_regs1[0:0] \builder_multiregimpl15_regs0
assign $0\builder_multiregimpl16_regs0[0:0] \main_gpio_pads_i [15]
assign $0\builder_multiregimpl16_regs1[0:0] \builder_multiregimpl16_regs0
- attribute \src "ls180.v:7456.2-7458.5"
- switch $or$ls180.v:7456$2399_Y
- attribute \src "ls180.v:7456.6-7456.94"
+ attribute \src "ls180.v:7452.2-7454.5"
+ switch $or$ls180.v:7452$2399_Y
+ attribute \src "ls180.v:7452.6-7452.94"
case 1'1
assign $0\main_libresocsim_converter0_dat_r[63:0] \main_libresocsim_libresoc_ibus_dat_r
case
end
- attribute \src "ls180.v:7460.2-7462.5"
+ attribute \src "ls180.v:7456.2-7458.5"
switch \main_libresocsim_converter0_counter_converter0_next_value_ce
- attribute \src "ls180.v:7460.6-7460.66"
+ attribute \src "ls180.v:7456.6-7456.66"
case 1'1
assign $0\main_libresocsim_converter0_counter[0:0] \main_libresocsim_converter0_counter_converter0_next_value
case
end
- attribute \src "ls180.v:7463.2-7466.5"
+ attribute \src "ls180.v:7459.2-7462.5"
switch \main_libresocsim_converter0_reset
- attribute \src "ls180.v:7463.6-7463.39"
+ attribute \src "ls180.v:7459.6-7459.39"
case 1'1
assign $0\main_libresocsim_converter0_counter[0:0] 1'0
assign $0\builder_converter0_state[0:0] 1'0
case
end
- attribute \src "ls180.v:7467.2-7469.5"
- switch $or$ls180.v:7467$2400_Y
- attribute \src "ls180.v:7467.6-7467.94"
+ attribute \src "ls180.v:7463.2-7465.5"
+ switch $or$ls180.v:7463$2400_Y
+ attribute \src "ls180.v:7463.6-7463.94"
case 1'1
assign $0\main_libresocsim_converter1_dat_r[63:0] \main_libresocsim_libresoc_dbus_dat_r
case
end
- attribute \src "ls180.v:7471.2-7473.5"
+ attribute \src "ls180.v:7467.2-7469.5"
switch \main_libresocsim_converter1_counter_converter1_next_value_ce
- attribute \src "ls180.v:7471.6-7471.66"
+ attribute \src "ls180.v:7467.6-7467.66"
case 1'1
assign $0\main_libresocsim_converter1_counter[0:0] \main_libresocsim_converter1_counter_converter1_next_value
case
end
- attribute \src "ls180.v:7474.2-7477.5"
+ attribute \src "ls180.v:7470.2-7473.5"
switch \main_libresocsim_converter1_reset
- attribute \src "ls180.v:7474.6-7474.39"
+ attribute \src "ls180.v:7470.6-7470.39"
case 1'1
assign $0\main_libresocsim_converter1_counter[0:0] 1'0
assign $0\builder_converter1_state[0:0] 1'0
case
end
- attribute \src "ls180.v:7478.2-7480.5"
- switch $or$ls180.v:7478$2401_Y
- attribute \src "ls180.v:7478.6-7478.94"
+ attribute \src "ls180.v:7474.2-7476.5"
+ switch $or$ls180.v:7474$2401_Y
+ attribute \src "ls180.v:7474.6-7474.94"
case 1'1
assign $0\main_libresocsim_converter2_dat_r[63:0] \main_libresocsim_libresoc_jtag_wb_dat_r
case
end
- attribute \src "ls180.v:7482.2-7484.5"
+ attribute \src "ls180.v:7478.2-7480.5"
switch \main_libresocsim_converter2_counter_converter2_next_value_ce
- attribute \src "ls180.v:7482.6-7482.66"
+ attribute \src "ls180.v:7478.6-7478.66"
case 1'1
assign $0\main_libresocsim_converter2_counter[0:0] \main_libresocsim_converter2_counter_converter2_next_value
case
end
- attribute \src "ls180.v:7485.2-7488.5"
+ attribute \src "ls180.v:7481.2-7484.5"
switch \main_libresocsim_converter2_reset
- attribute \src "ls180.v:7485.6-7485.39"
+ attribute \src "ls180.v:7481.6-7481.39"
case 1'1
assign $0\main_libresocsim_converter2_counter[0:0] 1'0
assign $0\builder_converter2_state[0:0] 1'0
case
end
- attribute \src "ls180.v:7489.2-7493.5"
- switch $ne$ls180.v:7489$2402_Y
- attribute \src "ls180.v:7489.6-7489.53"
+ attribute \src "ls180.v:7485.2-7489.5"
+ switch $ne$ls180.v:7485$2402_Y
+ attribute \src "ls180.v:7485.6-7485.53"
case 1'1
- attribute \src "ls180.v:7490.3-7492.6"
+ attribute \src "ls180.v:7486.3-7488.6"
switch \main_libresocsim_bus_error
- attribute \src "ls180.v:7490.7-7490.33"
+ attribute \src "ls180.v:7486.7-7486.33"
case 1'1
- assign $0\main_libresocsim_bus_errors[31:0] $add$ls180.v:7491$2403_Y
+ assign $0\main_libresocsim_bus_errors[31:0] $add$ls180.v:7487$2403_Y
case
end
case
end
- attribute \src "ls180.v:7495.2-7497.5"
- switch $and$ls180.v:7495$2406_Y
- attribute \src "ls180.v:7495.6-7495.103"
+ attribute \src "ls180.v:7491.2-7493.5"
+ switch $and$ls180.v:7491$2406_Y
+ attribute \src "ls180.v:7491.6-7491.103"
case 1'1
assign $0\main_libresocsim_ram_bus_ack[0:0] 1'1
case
end
- attribute \src "ls180.v:7498.2-7506.5"
+ attribute \src "ls180.v:7494.2-7502.5"
switch \main_libresocsim_en_storage
- attribute \src "ls180.v:7498.6-7498.33"
+ attribute \src "ls180.v:7494.6-7494.33"
case 1'1
- attribute \src "ls180.v:7499.3-7503.6"
- switch $eq$ls180.v:7499$2407_Y
- attribute \src "ls180.v:7499.7-7499.39"
+ attribute \src "ls180.v:7495.3-7499.6"
+ switch $eq$ls180.v:7495$2407_Y
+ attribute \src "ls180.v:7495.7-7495.39"
case 1'1
assign $0\main_libresocsim_value[31:0] \main_libresocsim_reload_storage
- attribute \src "ls180.v:7501.7-7501.11"
+ attribute \src "ls180.v:7497.7-7497.11"
case
- assign $0\main_libresocsim_value[31:0] $sub$ls180.v:7502$2408_Y
+ assign $0\main_libresocsim_value[31:0] $sub$ls180.v:7498$2408_Y
end
- attribute \src "ls180.v:7504.6-7504.10"
+ attribute \src "ls180.v:7500.6-7500.10"
case
assign $0\main_libresocsim_value[31:0] \main_libresocsim_load_storage
end
- attribute \src "ls180.v:7507.2-7509.5"
+ attribute \src "ls180.v:7503.2-7505.5"
switch \main_libresocsim_update_value_re
- attribute \src "ls180.v:7507.6-7507.38"
+ attribute \src "ls180.v:7503.6-7503.38"
case 1'1
assign $0\main_libresocsim_value_status[31:0] \main_libresocsim_value
case
end
- attribute \src "ls180.v:7510.2-7512.5"
+ attribute \src "ls180.v:7506.2-7508.5"
switch \main_libresocsim_zero_clear
- attribute \src "ls180.v:7510.6-7510.33"
+ attribute \src "ls180.v:7506.6-7506.33"
case 1'1
assign $0\main_libresocsim_zero_pending[0:0] 1'0
case
end
- attribute \src "ls180.v:7514.2-7516.5"
- switch $and$ls180.v:7514$2410_Y
- attribute \src "ls180.v:7514.6-7514.76"
+ attribute \src "ls180.v:7510.2-7512.5"
+ switch $and$ls180.v:7510$2410_Y
+ attribute \src "ls180.v:7510.6-7510.76"
case 1'1
assign $0\main_libresocsim_zero_pending[0:0] 1'1
case
end
- attribute \src "ls180.v:7519.2-7521.5"
+ attribute \src "ls180.v:7515.2-7517.5"
switch \main_sdram_inti_p0_rddata_valid
- attribute \src "ls180.v:7519.6-7519.37"
+ attribute \src "ls180.v:7515.6-7515.37"
case 1'1
assign $0\main_sdram_status[15:0] \main_sdram_inti_p0_rddata
case
end
- attribute \src "ls180.v:7522.2-7526.5"
- switch $and$ls180.v:7522$2412_Y
- attribute \src "ls180.v:7522.6-7522.57"
+ attribute \src "ls180.v:7518.2-7522.5"
+ switch $and$ls180.v:7518$2412_Y
+ attribute \src "ls180.v:7518.6-7518.57"
case 1'1
- assign $0\main_sdram_timer_count1[9:0] $sub$ls180.v:7523$2413_Y
- attribute \src "ls180.v:7524.6-7524.10"
+ assign $0\main_sdram_timer_count1[9:0] $sub$ls180.v:7519$2413_Y
+ attribute \src "ls180.v:7520.6-7520.10"
case
assign $0\main_sdram_timer_count1[9:0] 10'1100001101
end
- attribute \src "ls180.v:7528.2-7534.5"
+ attribute \src "ls180.v:7524.2-7530.5"
switch \main_sdram_postponer_req_i
- attribute \src "ls180.v:7528.6-7528.32"
+ attribute \src "ls180.v:7524.6-7524.32"
case 1'1
- assign $0\main_sdram_postponer_count[0:0] $sub$ls180.v:7529$2414_Y
- attribute \src "ls180.v:7530.3-7533.6"
- switch $eq$ls180.v:7530$2415_Y
- attribute \src "ls180.v:7530.7-7530.43"
+ assign $0\main_sdram_postponer_count[0:0] $sub$ls180.v:7525$2414_Y
+ attribute \src "ls180.v:7526.3-7529.6"
+ switch $eq$ls180.v:7526$2415_Y
+ attribute \src "ls180.v:7526.7-7526.43"
case 1'1
assign $0\main_sdram_postponer_count[0:0] 1'0
assign $0\main_sdram_postponer_req_o[0:0] 1'1
end
case
end
- attribute \src "ls180.v:7535.2-7543.5"
+ attribute \src "ls180.v:7531.2-7539.5"
switch \main_sdram_sequencer_start0
- attribute \src "ls180.v:7535.6-7535.33"
+ attribute \src "ls180.v:7531.6-7531.33"
case 1'1
assign $0\main_sdram_sequencer_count[0:0] 1'0
- attribute \src "ls180.v:7537.6-7537.10"
+ attribute \src "ls180.v:7533.6-7533.10"
case
- attribute \src "ls180.v:7538.3-7542.6"
+ attribute \src "ls180.v:7534.3-7538.6"
switch \main_sdram_sequencer_done1
- attribute \src "ls180.v:7538.7-7538.33"
+ attribute \src "ls180.v:7534.7-7534.33"
case 1'1
- attribute \src "ls180.v:7539.4-7541.7"
- switch $ne$ls180.v:7539$2416_Y
- attribute \src "ls180.v:7539.8-7539.44"
+ attribute \src "ls180.v:7535.4-7537.7"
+ switch $ne$ls180.v:7535$2416_Y
+ attribute \src "ls180.v:7535.8-7535.44"
case 1'1
- assign $0\main_sdram_sequencer_count[0:0] $sub$ls180.v:7540$2417_Y
+ assign $0\main_sdram_sequencer_count[0:0] $sub$ls180.v:7536$2417_Y
case
end
case
end
end
- attribute \src "ls180.v:7550.2-7556.5"
- switch $and$ls180.v:7550$2419_Y
- attribute \src "ls180.v:7550.6-7550.76"
+ attribute \src "ls180.v:7546.2-7552.5"
+ switch $and$ls180.v:7546$2419_Y
+ attribute \src "ls180.v:7546.6-7546.76"
case 1'1
assign $0\main_sdram_cmd_payload_a[12:0] 13'0010000000000
assign $0\main_sdram_cmd_payload_ba[1:0] 2'00
assign $0\main_sdram_cmd_payload_we[0:0] 1'1
case
end
- attribute \src "ls180.v:7557.2-7563.5"
- switch $eq$ls180.v:7557$2420_Y
- attribute \src "ls180.v:7557.6-7557.44"
+ attribute \src "ls180.v:7553.2-7559.5"
+ switch $eq$ls180.v:7553$2420_Y
+ attribute \src "ls180.v:7553.6-7553.44"
case 1'1
assign $0\main_sdram_cmd_payload_a[12:0] 13'0000000000000
assign $0\main_sdram_cmd_payload_ba[1:0] 2'00
assign $0\main_sdram_cmd_payload_we[0:0] 1'0
case
end
- attribute \src "ls180.v:7564.2-7571.5"
- switch $eq$ls180.v:7564$2421_Y
- attribute \src "ls180.v:7564.6-7564.44"
+ attribute \src "ls180.v:7560.2-7567.5"
+ switch $eq$ls180.v:7560$2421_Y
+ attribute \src "ls180.v:7560.6-7560.44"
case 1'1
assign $0\main_sdram_cmd_payload_a[12:0] 13'0000000000000
assign $0\main_sdram_cmd_payload_ba[1:0] 2'00
assign $0\main_sdram_sequencer_done1[0:0] 1'1
case
end
- attribute \src "ls180.v:7572.2-7582.5"
- switch $eq$ls180.v:7572$2422_Y
- attribute \src "ls180.v:7572.6-7572.44"
+ attribute \src "ls180.v:7568.2-7578.5"
+ switch $eq$ls180.v:7568$2422_Y
+ attribute \src "ls180.v:7568.6-7568.44"
case 1'1
assign $0\main_sdram_sequencer_counter[3:0] 4'0000
- attribute \src "ls180.v:7574.6-7574.10"
+ attribute \src "ls180.v:7570.6-7570.10"
case
- attribute \src "ls180.v:7575.3-7581.6"
- switch $ne$ls180.v:7575$2423_Y
- attribute \src "ls180.v:7575.7-7575.45"
+ attribute \src "ls180.v:7571.3-7577.6"
+ switch $ne$ls180.v:7571$2423_Y
+ attribute \src "ls180.v:7571.7-7571.45"
case 1'1
- assign $0\main_sdram_sequencer_counter[3:0] $add$ls180.v:7576$2424_Y
- attribute \src "ls180.v:7577.7-7577.11"
+ assign $0\main_sdram_sequencer_counter[3:0] $add$ls180.v:7572$2424_Y
+ attribute \src "ls180.v:7573.7-7573.11"
case
- attribute \src "ls180.v:7578.4-7580.7"
+ attribute \src "ls180.v:7574.4-7576.7"
switch \main_sdram_sequencer_start1
- attribute \src "ls180.v:7578.8-7578.35"
+ attribute \src "ls180.v:7574.8-7574.35"
case 1'1
assign $0\main_sdram_sequencer_counter[3:0] 4'0001
case
end
end
end
- attribute \src "ls180.v:7584.2-7591.5"
+ attribute \src "ls180.v:7580.2-7587.5"
switch \main_sdram_bankmachine0_row_close
- attribute \src "ls180.v:7584.6-7584.39"
+ attribute \src "ls180.v:7580.6-7580.39"
case 1'1
assign $0\main_sdram_bankmachine0_row_opened[0:0] 1'0
- attribute \src "ls180.v:7586.6-7586.10"
+ attribute \src "ls180.v:7582.6-7582.10"
case
- attribute \src "ls180.v:7587.3-7590.6"
+ attribute \src "ls180.v:7583.3-7586.6"
switch \main_sdram_bankmachine0_row_open
- attribute \src "ls180.v:7587.7-7587.39"
+ attribute \src "ls180.v:7583.7-7583.39"
case 1'1
assign $0\main_sdram_bankmachine0_row_opened[0:0] 1'1
assign $0\main_sdram_bankmachine0_row[12:0] \main_sdram_bankmachine0_cmd_buffer_source_payload_addr [21:9]
case
end
end
- attribute \src "ls180.v:7592.2-7594.5"
- switch $and$ls180.v:7592$2427_Y
- attribute \src "ls180.v:7592.6-7592.191"
+ attribute \src "ls180.v:7588.2-7590.5"
+ switch $and$ls180.v:7588$2427_Y
+ attribute \src "ls180.v:7588.6-7588.191"
case 1'1
- assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:7593$2428_Y
+ assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:7589$2428_Y
case
end
- attribute \src "ls180.v:7595.2-7597.5"
+ attribute \src "ls180.v:7591.2-7593.5"
switch \main_sdram_bankmachine0_cmd_buffer_lookahead_do_read
- attribute \src "ls180.v:7595.6-7595.58"
+ attribute \src "ls180.v:7591.6-7591.58"
case 1'1
- assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:7596$2429_Y
+ assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:7592$2429_Y
case
end
- attribute \src "ls180.v:7598.2-7606.5"
- switch $and$ls180.v:7598$2432_Y
- attribute \src "ls180.v:7598.6-7598.191"
+ attribute \src "ls180.v:7594.2-7602.5"
+ switch $and$ls180.v:7594$2432_Y
+ attribute \src "ls180.v:7594.6-7594.191"
case 1'1
- attribute \src "ls180.v:7599.3-7601.6"
- switch $not$ls180.v:7599$2433_Y
- attribute \src "ls180.v:7599.7-7599.62"
+ attribute \src "ls180.v:7595.3-7597.6"
+ switch $not$ls180.v:7595$2433_Y
+ attribute \src "ls180.v:7595.7-7595.62"
case 1'1
- assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] $add$ls180.v:7600$2434_Y
+ assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] $add$ls180.v:7596$2434_Y
case
end
- attribute \src "ls180.v:7602.6-7602.10"
+ attribute \src "ls180.v:7598.6-7598.10"
case
- attribute \src "ls180.v:7603.3-7605.6"
+ attribute \src "ls180.v:7599.3-7601.6"
switch \main_sdram_bankmachine0_cmd_buffer_lookahead_do_read
- attribute \src "ls180.v:7603.7-7603.59"
+ attribute \src "ls180.v:7599.7-7599.59"
case 1'1
- assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:7604$2435_Y
+ assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:7600$2435_Y
case
end
end
- attribute \src "ls180.v:7607.2-7613.5"
- switch $or$ls180.v:7607$2437_Y
- attribute \src "ls180.v:7607.6-7607.108"
+ attribute \src "ls180.v:7603.2-7609.5"
+ switch $or$ls180.v:7603$2437_Y
+ attribute \src "ls180.v:7603.6-7603.108"
case 1'1
assign $0\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine0_cmd_buffer_sink_valid
assign $0\main_sdram_bankmachine0_cmd_buffer_source_first[0:0] \main_sdram_bankmachine0_cmd_buffer_sink_first
assign $0\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] \main_sdram_bankmachine0_cmd_buffer_sink_payload_addr
case
end
- attribute \src "ls180.v:7614.2-7628.5"
+ attribute \src "ls180.v:7610.2-7624.5"
switch \main_sdram_bankmachine0_twtpcon_valid
- attribute \src "ls180.v:7614.6-7614.43"
+ attribute \src "ls180.v:7610.6-7610.43"
case 1'1
assign $0\main_sdram_bankmachine0_twtpcon_count[2:0] 3'100
- attribute \src "ls180.v:7616.3-7620.6"
+ attribute \src "ls180.v:7612.3-7616.6"
switch 1'0
- attribute \src "ls180.v:7618.7-7618.11"
+ attribute \src "ls180.v:7614.7-7614.11"
case
assign $0\main_sdram_bankmachine0_twtpcon_ready[0:0] 1'0
end
- attribute \src "ls180.v:7621.6-7621.10"
+ attribute \src "ls180.v:7617.6-7617.10"
case
- attribute \src "ls180.v:7622.3-7627.6"
- switch $not$ls180.v:7622$2438_Y
- attribute \src "ls180.v:7622.7-7622.47"
+ attribute \src "ls180.v:7618.3-7623.6"
+ switch $not$ls180.v:7618$2438_Y
+ attribute \src "ls180.v:7618.7-7618.47"
case 1'1
- assign $0\main_sdram_bankmachine0_twtpcon_count[2:0] $sub$ls180.v:7623$2439_Y
- attribute \src "ls180.v:7624.4-7626.7"
- switch $eq$ls180.v:7624$2440_Y
- attribute \src "ls180.v:7624.8-7624.55"
+ assign $0\main_sdram_bankmachine0_twtpcon_count[2:0] $sub$ls180.v:7619$2439_Y
+ attribute \src "ls180.v:7620.4-7622.7"
+ switch $eq$ls180.v:7620$2440_Y
+ attribute \src "ls180.v:7620.8-7620.55"
case 1'1
assign $0\main_sdram_bankmachine0_twtpcon_ready[0:0] 1'1
case
case
end
end
- attribute \src "ls180.v:7630.2-7637.5"
+ attribute \src "ls180.v:7626.2-7633.5"
switch \main_sdram_bankmachine1_row_close
- attribute \src "ls180.v:7630.6-7630.39"
+ attribute \src "ls180.v:7626.6-7626.39"
case 1'1
assign $0\main_sdram_bankmachine1_row_opened[0:0] 1'0
- attribute \src "ls180.v:7632.6-7632.10"
+ attribute \src "ls180.v:7628.6-7628.10"
case
- attribute \src "ls180.v:7633.3-7636.6"
+ attribute \src "ls180.v:7629.3-7632.6"
switch \main_sdram_bankmachine1_row_open
- attribute \src "ls180.v:7633.7-7633.39"
+ attribute \src "ls180.v:7629.7-7629.39"
case 1'1
assign $0\main_sdram_bankmachine1_row_opened[0:0] 1'1
assign $0\main_sdram_bankmachine1_row[12:0] \main_sdram_bankmachine1_cmd_buffer_source_payload_addr [21:9]
case
end
end
- attribute \src "ls180.v:7638.2-7640.5"
- switch $and$ls180.v:7638$2443_Y
- attribute \src "ls180.v:7638.6-7638.191"
+ attribute \src "ls180.v:7634.2-7636.5"
+ switch $and$ls180.v:7634$2443_Y
+ attribute \src "ls180.v:7634.6-7634.191"
case 1'1
- assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:7639$2444_Y
+ assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:7635$2444_Y
case
end
- attribute \src "ls180.v:7641.2-7643.5"
+ attribute \src "ls180.v:7637.2-7639.5"
switch \main_sdram_bankmachine1_cmd_buffer_lookahead_do_read
- attribute \src "ls180.v:7641.6-7641.58"
+ attribute \src "ls180.v:7637.6-7637.58"
case 1'1
- assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:7642$2445_Y
+ assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:7638$2445_Y
case
end
- attribute \src "ls180.v:7644.2-7652.5"
- switch $and$ls180.v:7644$2448_Y
- attribute \src "ls180.v:7644.6-7644.191"
+ attribute \src "ls180.v:7640.2-7648.5"
+ switch $and$ls180.v:7640$2448_Y
+ attribute \src "ls180.v:7640.6-7640.191"
case 1'1
- attribute \src "ls180.v:7645.3-7647.6"
- switch $not$ls180.v:7645$2449_Y
- attribute \src "ls180.v:7645.7-7645.62"
+ attribute \src "ls180.v:7641.3-7643.6"
+ switch $not$ls180.v:7641$2449_Y
+ attribute \src "ls180.v:7641.7-7641.62"
case 1'1
- assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] $add$ls180.v:7646$2450_Y
+ assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] $add$ls180.v:7642$2450_Y
case
end
- attribute \src "ls180.v:7648.6-7648.10"
+ attribute \src "ls180.v:7644.6-7644.10"
case
- attribute \src "ls180.v:7649.3-7651.6"
+ attribute \src "ls180.v:7645.3-7647.6"
switch \main_sdram_bankmachine1_cmd_buffer_lookahead_do_read
- attribute \src "ls180.v:7649.7-7649.59"
+ attribute \src "ls180.v:7645.7-7645.59"
case 1'1
- assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:7650$2451_Y
+ assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:7646$2451_Y
case
end
end
- attribute \src "ls180.v:7653.2-7659.5"
- switch $or$ls180.v:7653$2453_Y
- attribute \src "ls180.v:7653.6-7653.108"
+ attribute \src "ls180.v:7649.2-7655.5"
+ switch $or$ls180.v:7649$2453_Y
+ attribute \src "ls180.v:7649.6-7649.108"
case 1'1
assign $0\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine1_cmd_buffer_sink_valid
assign $0\main_sdram_bankmachine1_cmd_buffer_source_first[0:0] \main_sdram_bankmachine1_cmd_buffer_sink_first
assign $0\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] \main_sdram_bankmachine1_cmd_buffer_sink_payload_addr
case
end
- attribute \src "ls180.v:7660.2-7674.5"
+ attribute \src "ls180.v:7656.2-7670.5"
switch \main_sdram_bankmachine1_twtpcon_valid
- attribute \src "ls180.v:7660.6-7660.43"
+ attribute \src "ls180.v:7656.6-7656.43"
case 1'1
assign $0\main_sdram_bankmachine1_twtpcon_count[2:0] 3'100
- attribute \src "ls180.v:7662.3-7666.6"
+ attribute \src "ls180.v:7658.3-7662.6"
switch 1'0
- attribute \src "ls180.v:7664.7-7664.11"
+ attribute \src "ls180.v:7660.7-7660.11"
case
assign $0\main_sdram_bankmachine1_twtpcon_ready[0:0] 1'0
end
- attribute \src "ls180.v:7667.6-7667.10"
+ attribute \src "ls180.v:7663.6-7663.10"
case
- attribute \src "ls180.v:7668.3-7673.6"
- switch $not$ls180.v:7668$2454_Y
- attribute \src "ls180.v:7668.7-7668.47"
+ attribute \src "ls180.v:7664.3-7669.6"
+ switch $not$ls180.v:7664$2454_Y
+ attribute \src "ls180.v:7664.7-7664.47"
case 1'1
- assign $0\main_sdram_bankmachine1_twtpcon_count[2:0] $sub$ls180.v:7669$2455_Y
- attribute \src "ls180.v:7670.4-7672.7"
- switch $eq$ls180.v:7670$2456_Y
- attribute \src "ls180.v:7670.8-7670.55"
+ assign $0\main_sdram_bankmachine1_twtpcon_count[2:0] $sub$ls180.v:7665$2455_Y
+ attribute \src "ls180.v:7666.4-7668.7"
+ switch $eq$ls180.v:7666$2456_Y
+ attribute \src "ls180.v:7666.8-7666.55"
case 1'1
assign $0\main_sdram_bankmachine1_twtpcon_ready[0:0] 1'1
case
case
end
end
- attribute \src "ls180.v:7676.2-7683.5"
+ attribute \src "ls180.v:7672.2-7679.5"
switch \main_sdram_bankmachine2_row_close
- attribute \src "ls180.v:7676.6-7676.39"
+ attribute \src "ls180.v:7672.6-7672.39"
case 1'1
assign $0\main_sdram_bankmachine2_row_opened[0:0] 1'0
- attribute \src "ls180.v:7678.6-7678.10"
+ attribute \src "ls180.v:7674.6-7674.10"
case
- attribute \src "ls180.v:7679.3-7682.6"
+ attribute \src "ls180.v:7675.3-7678.6"
switch \main_sdram_bankmachine2_row_open
- attribute \src "ls180.v:7679.7-7679.39"
+ attribute \src "ls180.v:7675.7-7675.39"
case 1'1
assign $0\main_sdram_bankmachine2_row_opened[0:0] 1'1
assign $0\main_sdram_bankmachine2_row[12:0] \main_sdram_bankmachine2_cmd_buffer_source_payload_addr [21:9]
case
end
end
- attribute \src "ls180.v:7684.2-7686.5"
- switch $and$ls180.v:7684$2459_Y
- attribute \src "ls180.v:7684.6-7684.191"
+ attribute \src "ls180.v:7680.2-7682.5"
+ switch $and$ls180.v:7680$2459_Y
+ attribute \src "ls180.v:7680.6-7680.191"
case 1'1
- assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:7685$2460_Y
+ assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:7681$2460_Y
case
end
- attribute \src "ls180.v:7687.2-7689.5"
+ attribute \src "ls180.v:7683.2-7685.5"
switch \main_sdram_bankmachine2_cmd_buffer_lookahead_do_read
- attribute \src "ls180.v:7687.6-7687.58"
+ attribute \src "ls180.v:7683.6-7683.58"
case 1'1
- assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:7688$2461_Y
+ assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:7684$2461_Y
case
end
- attribute \src "ls180.v:7690.2-7698.5"
- switch $and$ls180.v:7690$2464_Y
- attribute \src "ls180.v:7690.6-7690.191"
+ attribute \src "ls180.v:7686.2-7694.5"
+ switch $and$ls180.v:7686$2464_Y
+ attribute \src "ls180.v:7686.6-7686.191"
case 1'1
- attribute \src "ls180.v:7691.3-7693.6"
- switch $not$ls180.v:7691$2465_Y
- attribute \src "ls180.v:7691.7-7691.62"
+ attribute \src "ls180.v:7687.3-7689.6"
+ switch $not$ls180.v:7687$2465_Y
+ attribute \src "ls180.v:7687.7-7687.62"
case 1'1
- assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] $add$ls180.v:7692$2466_Y
+ assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] $add$ls180.v:7688$2466_Y
case
end
- attribute \src "ls180.v:7694.6-7694.10"
+ attribute \src "ls180.v:7690.6-7690.10"
case
- attribute \src "ls180.v:7695.3-7697.6"
+ attribute \src "ls180.v:7691.3-7693.6"
switch \main_sdram_bankmachine2_cmd_buffer_lookahead_do_read
- attribute \src "ls180.v:7695.7-7695.59"
+ attribute \src "ls180.v:7691.7-7691.59"
case 1'1
- assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:7696$2467_Y
+ assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:7692$2467_Y
case
end
end
- attribute \src "ls180.v:7699.2-7705.5"
- switch $or$ls180.v:7699$2469_Y
- attribute \src "ls180.v:7699.6-7699.108"
+ attribute \src "ls180.v:7695.2-7701.5"
+ switch $or$ls180.v:7695$2469_Y
+ attribute \src "ls180.v:7695.6-7695.108"
case 1'1
assign $0\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine2_cmd_buffer_sink_valid
assign $0\main_sdram_bankmachine2_cmd_buffer_source_first[0:0] \main_sdram_bankmachine2_cmd_buffer_sink_first
assign $0\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] \main_sdram_bankmachine2_cmd_buffer_sink_payload_addr
case
end
- attribute \src "ls180.v:7706.2-7720.5"
+ attribute \src "ls180.v:7702.2-7716.5"
switch \main_sdram_bankmachine2_twtpcon_valid
- attribute \src "ls180.v:7706.6-7706.43"
+ attribute \src "ls180.v:7702.6-7702.43"
case 1'1
assign $0\main_sdram_bankmachine2_twtpcon_count[2:0] 3'100
- attribute \src "ls180.v:7708.3-7712.6"
+ attribute \src "ls180.v:7704.3-7708.6"
switch 1'0
- attribute \src "ls180.v:7710.7-7710.11"
+ attribute \src "ls180.v:7706.7-7706.11"
case
assign $0\main_sdram_bankmachine2_twtpcon_ready[0:0] 1'0
end
- attribute \src "ls180.v:7713.6-7713.10"
+ attribute \src "ls180.v:7709.6-7709.10"
case
- attribute \src "ls180.v:7714.3-7719.6"
- switch $not$ls180.v:7714$2470_Y
- attribute \src "ls180.v:7714.7-7714.47"
+ attribute \src "ls180.v:7710.3-7715.6"
+ switch $not$ls180.v:7710$2470_Y
+ attribute \src "ls180.v:7710.7-7710.47"
case 1'1
- assign $0\main_sdram_bankmachine2_twtpcon_count[2:0] $sub$ls180.v:7715$2471_Y
- attribute \src "ls180.v:7716.4-7718.7"
- switch $eq$ls180.v:7716$2472_Y
- attribute \src "ls180.v:7716.8-7716.55"
+ assign $0\main_sdram_bankmachine2_twtpcon_count[2:0] $sub$ls180.v:7711$2471_Y
+ attribute \src "ls180.v:7712.4-7714.7"
+ switch $eq$ls180.v:7712$2472_Y
+ attribute \src "ls180.v:7712.8-7712.55"
case 1'1
assign $0\main_sdram_bankmachine2_twtpcon_ready[0:0] 1'1
case
case
end
end
- attribute \src "ls180.v:7722.2-7729.5"
+ attribute \src "ls180.v:7718.2-7725.5"
switch \main_sdram_bankmachine3_row_close
- attribute \src "ls180.v:7722.6-7722.39"
+ attribute \src "ls180.v:7718.6-7718.39"
case 1'1
assign $0\main_sdram_bankmachine3_row_opened[0:0] 1'0
- attribute \src "ls180.v:7724.6-7724.10"
+ attribute \src "ls180.v:7720.6-7720.10"
case
- attribute \src "ls180.v:7725.3-7728.6"
+ attribute \src "ls180.v:7721.3-7724.6"
switch \main_sdram_bankmachine3_row_open
- attribute \src "ls180.v:7725.7-7725.39"
+ attribute \src "ls180.v:7721.7-7721.39"
case 1'1
assign $0\main_sdram_bankmachine3_row_opened[0:0] 1'1
assign $0\main_sdram_bankmachine3_row[12:0] \main_sdram_bankmachine3_cmd_buffer_source_payload_addr [21:9]
case
end
end
- attribute \src "ls180.v:7730.2-7732.5"
- switch $and$ls180.v:7730$2475_Y
- attribute \src "ls180.v:7730.6-7730.191"
+ attribute \src "ls180.v:7726.2-7728.5"
+ switch $and$ls180.v:7726$2475_Y
+ attribute \src "ls180.v:7726.6-7726.191"
case 1'1
- assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:7731$2476_Y
+ assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:7727$2476_Y
case
end
- attribute \src "ls180.v:7733.2-7735.5"
+ attribute \src "ls180.v:7729.2-7731.5"
switch \main_sdram_bankmachine3_cmd_buffer_lookahead_do_read
- attribute \src "ls180.v:7733.6-7733.58"
+ attribute \src "ls180.v:7729.6-7729.58"
case 1'1
- assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:7734$2477_Y
+ assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:7730$2477_Y
case
end
- attribute \src "ls180.v:7736.2-7744.5"
- switch $and$ls180.v:7736$2480_Y
- attribute \src "ls180.v:7736.6-7736.191"
+ attribute \src "ls180.v:7732.2-7740.5"
+ switch $and$ls180.v:7732$2480_Y
+ attribute \src "ls180.v:7732.6-7732.191"
case 1'1
- attribute \src "ls180.v:7737.3-7739.6"
- switch $not$ls180.v:7737$2481_Y
- attribute \src "ls180.v:7737.7-7737.62"
+ attribute \src "ls180.v:7733.3-7735.6"
+ switch $not$ls180.v:7733$2481_Y
+ attribute \src "ls180.v:7733.7-7733.62"
case 1'1
- assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] $add$ls180.v:7738$2482_Y
+ assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] $add$ls180.v:7734$2482_Y
case
end
- attribute \src "ls180.v:7740.6-7740.10"
+ attribute \src "ls180.v:7736.6-7736.10"
case
- attribute \src "ls180.v:7741.3-7743.6"
+ attribute \src "ls180.v:7737.3-7739.6"
switch \main_sdram_bankmachine3_cmd_buffer_lookahead_do_read
- attribute \src "ls180.v:7741.7-7741.59"
+ attribute \src "ls180.v:7737.7-7737.59"
case 1'1
- assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:7742$2483_Y
+ assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:7738$2483_Y
case
end
end
- attribute \src "ls180.v:7745.2-7751.5"
- switch $or$ls180.v:7745$2485_Y
- attribute \src "ls180.v:7745.6-7745.108"
+ attribute \src "ls180.v:7741.2-7747.5"
+ switch $or$ls180.v:7741$2485_Y
+ attribute \src "ls180.v:7741.6-7741.108"
case 1'1
assign $0\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine3_cmd_buffer_sink_valid
assign $0\main_sdram_bankmachine3_cmd_buffer_source_first[0:0] \main_sdram_bankmachine3_cmd_buffer_sink_first
assign $0\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] \main_sdram_bankmachine3_cmd_buffer_sink_payload_addr
case
end
- attribute \src "ls180.v:7752.2-7766.5"
+ attribute \src "ls180.v:7748.2-7762.5"
switch \main_sdram_bankmachine3_twtpcon_valid
- attribute \src "ls180.v:7752.6-7752.43"
+ attribute \src "ls180.v:7748.6-7748.43"
case 1'1
assign $0\main_sdram_bankmachine3_twtpcon_count[2:0] 3'100
- attribute \src "ls180.v:7754.3-7758.6"
+ attribute \src "ls180.v:7750.3-7754.6"
switch 1'0
- attribute \src "ls180.v:7756.7-7756.11"
+ attribute \src "ls180.v:7752.7-7752.11"
case
assign $0\main_sdram_bankmachine3_twtpcon_ready[0:0] 1'0
end
- attribute \src "ls180.v:7759.6-7759.10"
+ attribute \src "ls180.v:7755.6-7755.10"
case
- attribute \src "ls180.v:7760.3-7765.6"
- switch $not$ls180.v:7760$2486_Y
- attribute \src "ls180.v:7760.7-7760.47"
+ attribute \src "ls180.v:7756.3-7761.6"
+ switch $not$ls180.v:7756$2486_Y
+ attribute \src "ls180.v:7756.7-7756.47"
case 1'1
- assign $0\main_sdram_bankmachine3_twtpcon_count[2:0] $sub$ls180.v:7761$2487_Y
- attribute \src "ls180.v:7762.4-7764.7"
- switch $eq$ls180.v:7762$2488_Y
- attribute \src "ls180.v:7762.8-7762.55"
+ assign $0\main_sdram_bankmachine3_twtpcon_count[2:0] $sub$ls180.v:7757$2487_Y
+ attribute \src "ls180.v:7758.4-7760.7"
+ switch $eq$ls180.v:7758$2488_Y
+ attribute \src "ls180.v:7758.8-7758.55"
case 1'1
assign $0\main_sdram_bankmachine3_twtpcon_ready[0:0] 1'1
case
case
end
end
- attribute \src "ls180.v:7768.2-7774.5"
- switch $not$ls180.v:7768$2489_Y
- attribute \src "ls180.v:7768.6-7768.23"
+ attribute \src "ls180.v:7764.2-7770.5"
+ switch $not$ls180.v:7764$2489_Y
+ attribute \src "ls180.v:7764.6-7764.23"
case 1'1
assign $0\main_sdram_time0[4:0] 5'11111
- attribute \src "ls180.v:7770.6-7770.10"
+ attribute \src "ls180.v:7766.6-7766.10"
case
- attribute \src "ls180.v:7771.3-7773.6"
- switch $not$ls180.v:7771$2490_Y
- attribute \src "ls180.v:7771.7-7771.30"
+ attribute \src "ls180.v:7767.3-7769.6"
+ switch $not$ls180.v:7767$2490_Y
+ attribute \src "ls180.v:7767.7-7767.30"
case 1'1
- assign $0\main_sdram_time0[4:0] $sub$ls180.v:7772$2491_Y
+ assign $0\main_sdram_time0[4:0] $sub$ls180.v:7768$2491_Y
case
end
end
- attribute \src "ls180.v:7775.2-7781.5"
- switch $not$ls180.v:7775$2492_Y
- attribute \src "ls180.v:7775.6-7775.23"
+ attribute \src "ls180.v:7771.2-7777.5"
+ switch $not$ls180.v:7771$2492_Y
+ attribute \src "ls180.v:7771.6-7771.23"
case 1'1
assign $0\main_sdram_time1[3:0] 4'1111
- attribute \src "ls180.v:7777.6-7777.10"
+ attribute \src "ls180.v:7773.6-7773.10"
case
- attribute \src "ls180.v:7778.3-7780.6"
- switch $not$ls180.v:7778$2493_Y
- attribute \src "ls180.v:7778.7-7778.30"
+ attribute \src "ls180.v:7774.3-7776.6"
+ switch $not$ls180.v:7774$2493_Y
+ attribute \src "ls180.v:7774.7-7774.30"
case 1'1
- assign $0\main_sdram_time1[3:0] $sub$ls180.v:7779$2494_Y
+ assign $0\main_sdram_time1[3:0] $sub$ls180.v:7775$2494_Y
case
end
end
- attribute \src "ls180.v:7782.2-7837.5"
+ attribute \src "ls180.v:7778.2-7833.5"
switch \main_sdram_choose_cmd_ce
- attribute \src "ls180.v:7782.6-7782.30"
+ attribute \src "ls180.v:7778.6-7778.30"
case 1'1
- attribute \src "ls180.v:7783.3-7836.10"
+ attribute \src "ls180.v:7779.3-7832.10"
switch \main_sdram_choose_cmd_grant
attribute \src "ls180.v:0.0-0.0"
case 2'00
- attribute \src "ls180.v:7785.5-7795.8"
+ attribute \src "ls180.v:7781.5-7791.8"
switch \main_sdram_choose_cmd_request [1]
- attribute \src "ls180.v:7785.9-7785.41"
+ attribute \src "ls180.v:7781.9-7781.41"
case 1'1
assign $0\main_sdram_choose_cmd_grant[1:0] 2'01
- attribute \src "ls180.v:7787.9-7787.13"
+ attribute \src "ls180.v:7783.9-7783.13"
case
- attribute \src "ls180.v:7788.6-7794.9"
+ attribute \src "ls180.v:7784.6-7790.9"
switch \main_sdram_choose_cmd_request [2]
- attribute \src "ls180.v:7788.10-7788.42"
+ attribute \src "ls180.v:7784.10-7784.42"
case 1'1
assign $0\main_sdram_choose_cmd_grant[1:0] 2'10
- attribute \src "ls180.v:7790.10-7790.14"
+ attribute \src "ls180.v:7786.10-7786.14"
case
- attribute \src "ls180.v:7791.7-7793.10"
+ attribute \src "ls180.v:7787.7-7789.10"
switch \main_sdram_choose_cmd_request [3]
- attribute \src "ls180.v:7791.11-7791.43"
+ attribute \src "ls180.v:7787.11-7787.43"
case 1'1
assign $0\main_sdram_choose_cmd_grant[1:0] 2'11
case
end
attribute \src "ls180.v:0.0-0.0"
case 2'01
- attribute \src "ls180.v:7798.5-7808.8"
+ attribute \src "ls180.v:7794.5-7804.8"
switch \main_sdram_choose_cmd_request [2]
- attribute \src "ls180.v:7798.9-7798.41"
+ attribute \src "ls180.v:7794.9-7794.41"
case 1'1
assign $0\main_sdram_choose_cmd_grant[1:0] 2'10
- attribute \src "ls180.v:7800.9-7800.13"
+ attribute \src "ls180.v:7796.9-7796.13"
case
- attribute \src "ls180.v:7801.6-7807.9"
+ attribute \src "ls180.v:7797.6-7803.9"
switch \main_sdram_choose_cmd_request [3]
- attribute \src "ls180.v:7801.10-7801.42"
+ attribute \src "ls180.v:7797.10-7797.42"
case 1'1
assign $0\main_sdram_choose_cmd_grant[1:0] 2'11
- attribute \src "ls180.v:7803.10-7803.14"
+ attribute \src "ls180.v:7799.10-7799.14"
case
- attribute \src "ls180.v:7804.7-7806.10"
+ attribute \src "ls180.v:7800.7-7802.10"
switch \main_sdram_choose_cmd_request [0]
- attribute \src "ls180.v:7804.11-7804.43"
+ attribute \src "ls180.v:7800.11-7800.43"
case 1'1
assign $0\main_sdram_choose_cmd_grant[1:0] 2'00
case
end
attribute \src "ls180.v:0.0-0.0"
case 2'10
- attribute \src "ls180.v:7811.5-7821.8"
+ attribute \src "ls180.v:7807.5-7817.8"
switch \main_sdram_choose_cmd_request [3]
- attribute \src "ls180.v:7811.9-7811.41"
+ attribute \src "ls180.v:7807.9-7807.41"
case 1'1
assign $0\main_sdram_choose_cmd_grant[1:0] 2'11
- attribute \src "ls180.v:7813.9-7813.13"
+ attribute \src "ls180.v:7809.9-7809.13"
case
- attribute \src "ls180.v:7814.6-7820.9"
+ attribute \src "ls180.v:7810.6-7816.9"
switch \main_sdram_choose_cmd_request [0]
- attribute \src "ls180.v:7814.10-7814.42"
+ attribute \src "ls180.v:7810.10-7810.42"
case 1'1
assign $0\main_sdram_choose_cmd_grant[1:0] 2'00
- attribute \src "ls180.v:7816.10-7816.14"
+ attribute \src "ls180.v:7812.10-7812.14"
case
- attribute \src "ls180.v:7817.7-7819.10"
+ attribute \src "ls180.v:7813.7-7815.10"
switch \main_sdram_choose_cmd_request [1]
- attribute \src "ls180.v:7817.11-7817.43"
+ attribute \src "ls180.v:7813.11-7813.43"
case 1'1
assign $0\main_sdram_choose_cmd_grant[1:0] 2'01
case
end
attribute \src "ls180.v:0.0-0.0"
case 2'11
- attribute \src "ls180.v:7824.5-7834.8"
+ attribute \src "ls180.v:7820.5-7830.8"
switch \main_sdram_choose_cmd_request [0]
- attribute \src "ls180.v:7824.9-7824.41"
+ attribute \src "ls180.v:7820.9-7820.41"
case 1'1
assign $0\main_sdram_choose_cmd_grant[1:0] 2'00
- attribute \src "ls180.v:7826.9-7826.13"
+ attribute \src "ls180.v:7822.9-7822.13"
case
- attribute \src "ls180.v:7827.6-7833.9"
+ attribute \src "ls180.v:7823.6-7829.9"
switch \main_sdram_choose_cmd_request [1]
- attribute \src "ls180.v:7827.10-7827.42"
+ attribute \src "ls180.v:7823.10-7823.42"
case 1'1
assign $0\main_sdram_choose_cmd_grant[1:0] 2'01
- attribute \src "ls180.v:7829.10-7829.14"
+ attribute \src "ls180.v:7825.10-7825.14"
case
- attribute \src "ls180.v:7830.7-7832.10"
+ attribute \src "ls180.v:7826.7-7828.10"
switch \main_sdram_choose_cmd_request [2]
- attribute \src "ls180.v:7830.11-7830.43"
+ attribute \src "ls180.v:7826.11-7826.43"
case 1'1
assign $0\main_sdram_choose_cmd_grant[1:0] 2'10
case
end
case
end
- attribute \src "ls180.v:7838.2-7893.5"
+ attribute \src "ls180.v:7834.2-7889.5"
switch \main_sdram_choose_req_ce
- attribute \src "ls180.v:7838.6-7838.30"
+ attribute \src "ls180.v:7834.6-7834.30"
case 1'1
- attribute \src "ls180.v:7839.3-7892.10"
+ attribute \src "ls180.v:7835.3-7888.10"
switch \main_sdram_choose_req_grant
attribute \src "ls180.v:0.0-0.0"
case 2'00
- attribute \src "ls180.v:7841.5-7851.8"
+ attribute \src "ls180.v:7837.5-7847.8"
switch \main_sdram_choose_req_request [1]
- attribute \src "ls180.v:7841.9-7841.41"
+ attribute \src "ls180.v:7837.9-7837.41"
case 1'1
assign $0\main_sdram_choose_req_grant[1:0] 2'01
- attribute \src "ls180.v:7843.9-7843.13"
+ attribute \src "ls180.v:7839.9-7839.13"
case
- attribute \src "ls180.v:7844.6-7850.9"
+ attribute \src "ls180.v:7840.6-7846.9"
switch \main_sdram_choose_req_request [2]
- attribute \src "ls180.v:7844.10-7844.42"
+ attribute \src "ls180.v:7840.10-7840.42"
case 1'1
assign $0\main_sdram_choose_req_grant[1:0] 2'10
- attribute \src "ls180.v:7846.10-7846.14"
+ attribute \src "ls180.v:7842.10-7842.14"
case
- attribute \src "ls180.v:7847.7-7849.10"
+ attribute \src "ls180.v:7843.7-7845.10"
switch \main_sdram_choose_req_request [3]
- attribute \src "ls180.v:7847.11-7847.43"
+ attribute \src "ls180.v:7843.11-7843.43"
case 1'1
assign $0\main_sdram_choose_req_grant[1:0] 2'11
case
end
attribute \src "ls180.v:0.0-0.0"
case 2'01
- attribute \src "ls180.v:7854.5-7864.8"
+ attribute \src "ls180.v:7850.5-7860.8"
switch \main_sdram_choose_req_request [2]
- attribute \src "ls180.v:7854.9-7854.41"
+ attribute \src "ls180.v:7850.9-7850.41"
case 1'1
assign $0\main_sdram_choose_req_grant[1:0] 2'10
- attribute \src "ls180.v:7856.9-7856.13"
+ attribute \src "ls180.v:7852.9-7852.13"
case
- attribute \src "ls180.v:7857.6-7863.9"
+ attribute \src "ls180.v:7853.6-7859.9"
switch \main_sdram_choose_req_request [3]
- attribute \src "ls180.v:7857.10-7857.42"
+ attribute \src "ls180.v:7853.10-7853.42"
case 1'1
assign $0\main_sdram_choose_req_grant[1:0] 2'11
- attribute \src "ls180.v:7859.10-7859.14"
+ attribute \src "ls180.v:7855.10-7855.14"
case
- attribute \src "ls180.v:7860.7-7862.10"
+ attribute \src "ls180.v:7856.7-7858.10"
switch \main_sdram_choose_req_request [0]
- attribute \src "ls180.v:7860.11-7860.43"
+ attribute \src "ls180.v:7856.11-7856.43"
case 1'1
assign $0\main_sdram_choose_req_grant[1:0] 2'00
case
end
attribute \src "ls180.v:0.0-0.0"
case 2'10
- attribute \src "ls180.v:7867.5-7877.8"
+ attribute \src "ls180.v:7863.5-7873.8"
switch \main_sdram_choose_req_request [3]
- attribute \src "ls180.v:7867.9-7867.41"
+ attribute \src "ls180.v:7863.9-7863.41"
case 1'1
assign $0\main_sdram_choose_req_grant[1:0] 2'11
- attribute \src "ls180.v:7869.9-7869.13"
+ attribute \src "ls180.v:7865.9-7865.13"
case
- attribute \src "ls180.v:7870.6-7876.9"
+ attribute \src "ls180.v:7866.6-7872.9"
switch \main_sdram_choose_req_request [0]
- attribute \src "ls180.v:7870.10-7870.42"
+ attribute \src "ls180.v:7866.10-7866.42"
case 1'1
assign $0\main_sdram_choose_req_grant[1:0] 2'00
- attribute \src "ls180.v:7872.10-7872.14"
+ attribute \src "ls180.v:7868.10-7868.14"
case
- attribute \src "ls180.v:7873.7-7875.10"
+ attribute \src "ls180.v:7869.7-7871.10"
switch \main_sdram_choose_req_request [1]
- attribute \src "ls180.v:7873.11-7873.43"
+ attribute \src "ls180.v:7869.11-7869.43"
case 1'1
assign $0\main_sdram_choose_req_grant[1:0] 2'01
case
end
attribute \src "ls180.v:0.0-0.0"
case 2'11
- attribute \src "ls180.v:7880.5-7890.8"
+ attribute \src "ls180.v:7876.5-7886.8"
switch \main_sdram_choose_req_request [0]
- attribute \src "ls180.v:7880.9-7880.41"
+ attribute \src "ls180.v:7876.9-7876.41"
case 1'1
assign $0\main_sdram_choose_req_grant[1:0] 2'00
- attribute \src "ls180.v:7882.9-7882.13"
+ attribute \src "ls180.v:7878.9-7878.13"
case
- attribute \src "ls180.v:7883.6-7889.9"
+ attribute \src "ls180.v:7879.6-7885.9"
switch \main_sdram_choose_req_request [1]
- attribute \src "ls180.v:7883.10-7883.42"
+ attribute \src "ls180.v:7879.10-7879.42"
case 1'1
assign $0\main_sdram_choose_req_grant[1:0] 2'01
- attribute \src "ls180.v:7885.10-7885.14"
+ attribute \src "ls180.v:7881.10-7881.14"
case
- attribute \src "ls180.v:7886.7-7888.10"
+ attribute \src "ls180.v:7882.7-7884.10"
switch \main_sdram_choose_req_request [2]
- attribute \src "ls180.v:7886.11-7886.43"
+ attribute \src "ls180.v:7882.11-7882.43"
case 1'1
assign $0\main_sdram_choose_req_grant[1:0] 2'10
case
end
case
end
- attribute \src "ls180.v:7902.2-7916.5"
+ attribute \src "ls180.v:7898.2-7912.5"
switch \main_sdram_tccdcon_valid
- attribute \src "ls180.v:7902.6-7902.30"
+ attribute \src "ls180.v:7898.6-7898.30"
case 1'1
assign $0\main_sdram_tccdcon_count[0:0] 1'0
- attribute \src "ls180.v:7904.3-7908.6"
+ attribute \src "ls180.v:7900.3-7904.6"
switch 1'1
- attribute \src "ls180.v:7904.7-7904.11"
+ attribute \src "ls180.v:7900.7-7900.11"
case 1'1
assign $0\main_sdram_tccdcon_ready[0:0] 1'1
case
end
- attribute \src "ls180.v:7909.6-7909.10"
+ attribute \src "ls180.v:7905.6-7905.10"
case
- attribute \src "ls180.v:7910.3-7915.6"
- switch $not$ls180.v:7910$2498_Y
- attribute \src "ls180.v:7910.7-7910.34"
+ attribute \src "ls180.v:7906.3-7911.6"
+ switch $not$ls180.v:7906$2498_Y
+ attribute \src "ls180.v:7906.7-7906.34"
case 1'1
- assign $0\main_sdram_tccdcon_count[0:0] $sub$ls180.v:7911$2499_Y
- attribute \src "ls180.v:7912.4-7914.7"
- switch $eq$ls180.v:7912$2500_Y
- attribute \src "ls180.v:7912.8-7912.42"
+ assign $0\main_sdram_tccdcon_count[0:0] $sub$ls180.v:7907$2499_Y
+ attribute \src "ls180.v:7908.4-7910.7"
+ switch $eq$ls180.v:7908$2500_Y
+ attribute \src "ls180.v:7908.8-7908.42"
case 1'1
assign $0\main_sdram_tccdcon_ready[0:0] 1'1
case
case
end
end
- attribute \src "ls180.v:7917.2-7931.5"
+ attribute \src "ls180.v:7913.2-7927.5"
switch \main_sdram_twtrcon_valid
- attribute \src "ls180.v:7917.6-7917.30"
+ attribute \src "ls180.v:7913.6-7913.30"
case 1'1
assign $0\main_sdram_twtrcon_count[2:0] 3'100
- attribute \src "ls180.v:7919.3-7923.6"
+ attribute \src "ls180.v:7915.3-7919.6"
switch 1'0
- attribute \src "ls180.v:7921.7-7921.11"
+ attribute \src "ls180.v:7917.7-7917.11"
case
assign $0\main_sdram_twtrcon_ready[0:0] 1'0
end
- attribute \src "ls180.v:7924.6-7924.10"
+ attribute \src "ls180.v:7920.6-7920.10"
case
- attribute \src "ls180.v:7925.3-7930.6"
- switch $not$ls180.v:7925$2501_Y
- attribute \src "ls180.v:7925.7-7925.34"
+ attribute \src "ls180.v:7921.3-7926.6"
+ switch $not$ls180.v:7921$2501_Y
+ attribute \src "ls180.v:7921.7-7921.34"
case 1'1
- assign $0\main_sdram_twtrcon_count[2:0] $sub$ls180.v:7926$2502_Y
- attribute \src "ls180.v:7927.4-7929.7"
- switch $eq$ls180.v:7927$2503_Y
- attribute \src "ls180.v:7927.8-7927.42"
+ assign $0\main_sdram_twtrcon_count[2:0] $sub$ls180.v:7922$2502_Y
+ attribute \src "ls180.v:7923.4-7925.7"
+ switch $eq$ls180.v:7923$2503_Y
+ attribute \src "ls180.v:7923.8-7923.42"
case 1'1
assign $0\main_sdram_twtrcon_ready[0:0] 1'1
case
case
end
end
- attribute \src "ls180.v:7938.2-7940.5"
- switch $or$ls180.v:7938$2528_Y
- attribute \src "ls180.v:7938.6-7938.50"
+ attribute \src "ls180.v:7934.2-7936.5"
+ switch $or$ls180.v:7934$2528_Y
+ attribute \src "ls180.v:7934.6-7934.50"
case 1'1
assign $0\main_converter_dat_r[31:0] \main_wb_sdram_dat_r
case
end
- attribute \src "ls180.v:7942.2-7944.5"
+ attribute \src "ls180.v:7938.2-7940.5"
switch \main_converter_counter_converter_next_value_ce
- attribute \src "ls180.v:7942.6-7942.52"
+ attribute \src "ls180.v:7938.6-7938.52"
case 1'1
assign $0\main_converter_counter[0:0] \main_converter_counter_converter_next_value
case
end
- attribute \src "ls180.v:7945.2-7948.5"
+ attribute \src "ls180.v:7941.2-7944.5"
switch \main_converter_reset
- attribute \src "ls180.v:7945.6-7945.26"
+ attribute \src "ls180.v:7941.6-7941.26"
case 1'1
assign $0\main_converter_counter[0:0] 1'0
assign $0\builder_converter_state[0:0] 1'0
case
end
- attribute \src "ls180.v:7949.2-7959.5"
+ attribute \src "ls180.v:7945.2-7955.5"
switch \main_litedram_wb_ack
- attribute \src "ls180.v:7949.6-7949.26"
+ attribute \src "ls180.v:7945.6-7945.26"
case 1'1
assign $0\main_cmd_consumed[0:0] 1'0
assign $0\main_wdata_consumed[0:0] 1'0
- attribute \src "ls180.v:7952.6-7952.10"
+ attribute \src "ls180.v:7948.6-7948.10"
case
- attribute \src "ls180.v:7953.3-7955.6"
- switch $and$ls180.v:7953$2529_Y
- attribute \src "ls180.v:7953.7-7953.50"
+ attribute \src "ls180.v:7949.3-7951.6"
+ switch $and$ls180.v:7949$2529_Y
+ attribute \src "ls180.v:7949.7-7949.50"
case 1'1
assign $0\main_cmd_consumed[0:0] 1'1
case
end
- attribute \src "ls180.v:7956.3-7958.6"
- switch $and$ls180.v:7956$2530_Y
- attribute \src "ls180.v:7956.7-7956.54"
+ attribute \src "ls180.v:7952.3-7954.6"
+ switch $and$ls180.v:7952$2530_Y
+ attribute \src "ls180.v:7952.7-7952.54"
case 1'1
assign $0\main_wdata_consumed[0:0] 1'1
case
end
end
- attribute \src "ls180.v:7961.2-7982.5"
- switch $and$ls180.v:7961$2534_Y
- attribute \src "ls180.v:7961.6-7961.91"
+ attribute \src "ls180.v:7957.2-7978.5"
+ switch $and$ls180.v:7957$2534_Y
+ attribute \src "ls180.v:7957.6-7957.91"
case 1'1
assign $0\main_uart_phy_tx_reg[7:0] \main_uart_phy_sink_payload_data
assign $0\main_uart_phy_tx_bitcount[3:0] 4'0000
assign $0\main_uart_phy_tx_busy[0:0] 1'1
assign $0\uart_tx[0:0] 1'0
- attribute \src "ls180.v:7966.6-7966.10"
+ attribute \src "ls180.v:7962.6-7962.10"
case
- attribute \src "ls180.v:7967.3-7981.6"
- switch $and$ls180.v:7967$2535_Y
- attribute \src "ls180.v:7967.7-7967.60"
+ attribute \src "ls180.v:7963.3-7977.6"
+ switch $and$ls180.v:7963$2535_Y
+ attribute \src "ls180.v:7963.7-7963.60"
case 1'1
- assign $0\main_uart_phy_tx_bitcount[3:0] $add$ls180.v:7968$2536_Y
- attribute \src "ls180.v:7969.4-7980.7"
- switch $eq$ls180.v:7969$2537_Y
- attribute \src "ls180.v:7969.8-7969.43"
+ assign $0\main_uart_phy_tx_bitcount[3:0] $add$ls180.v:7964$2536_Y
+ attribute \src "ls180.v:7965.4-7976.7"
+ switch $eq$ls180.v:7965$2537_Y
+ attribute \src "ls180.v:7965.8-7965.43"
case 1'1
assign $0\uart_tx[0:0] 1'1
- attribute \src "ls180.v:7971.8-7971.12"
+ attribute \src "ls180.v:7967.8-7967.12"
case
- attribute \src "ls180.v:7972.5-7979.8"
- switch $eq$ls180.v:7972$2538_Y
- attribute \src "ls180.v:7972.9-7972.44"
+ attribute \src "ls180.v:7968.5-7975.8"
+ switch $eq$ls180.v:7968$2538_Y
+ attribute \src "ls180.v:7968.9-7968.44"
case 1'1
assign $0\uart_tx[0:0] 1'1
assign $0\main_uart_phy_tx_busy[0:0] 1'0
assign $0\main_uart_phy_sink_ready[0:0] 1'1
- attribute \src "ls180.v:7976.9-7976.13"
+ attribute \src "ls180.v:7972.9-7972.13"
case
assign $0\uart_tx[0:0] \main_uart_phy_tx_reg [0]
assign $0\main_uart_phy_tx_reg[7:0] { 1'0 \main_uart_phy_tx_reg [7:1] }
case
end
end
- attribute \src "ls180.v:7983.2-7987.5"
+ attribute \src "ls180.v:7979.2-7983.5"
switch \main_uart_phy_tx_busy
- attribute \src "ls180.v:7983.6-7983.27"
+ attribute \src "ls180.v:7979.6-7979.27"
case 1'1
- assign { $0\main_uart_phy_uart_clk_txen[0:0] $0\main_uart_phy_phase_accumulator_tx[31:0] } $add$ls180.v:7984$2539_Y
- attribute \src "ls180.v:7985.6-7985.10"
+ assign { $0\main_uart_phy_uart_clk_txen[0:0] $0\main_uart_phy_phase_accumulator_tx[31:0] } $add$ls180.v:7980$2539_Y
+ attribute \src "ls180.v:7981.6-7981.10"
case
assign { $0\main_uart_phy_uart_clk_txen[0:0] $0\main_uart_phy_phase_accumulator_tx[31:0] } { 1'0 \main_uart_phy_storage }
end
- attribute \src "ls180.v:7990.2-8014.5"
- switch $not$ls180.v:7990$2540_Y
- attribute \src "ls180.v:7990.6-7990.30"
+ attribute \src "ls180.v:7986.2-8010.5"
+ switch $not$ls180.v:7986$2540_Y
+ attribute \src "ls180.v:7986.6-7986.30"
case 1'1
- attribute \src "ls180.v:7991.3-7994.6"
- switch $and$ls180.v:7991$2542_Y
- attribute \src "ls180.v:7991.7-7991.49"
+ attribute \src "ls180.v:7987.3-7990.6"
+ switch $and$ls180.v:7987$2542_Y
+ attribute \src "ls180.v:7987.7-7987.49"
case 1'1
assign $0\main_uart_phy_rx_busy[0:0] 1'1
assign $0\main_uart_phy_rx_bitcount[3:0] 4'0000
case
end
- attribute \src "ls180.v:7995.6-7995.10"
+ attribute \src "ls180.v:7991.6-7991.10"
case
- attribute \src "ls180.v:7996.3-8013.6"
+ attribute \src "ls180.v:7992.3-8009.6"
switch \main_uart_phy_uart_clk_rxen
- attribute \src "ls180.v:7996.7-7996.34"
+ attribute \src "ls180.v:7992.7-7992.34"
case 1'1
- assign $0\main_uart_phy_rx_bitcount[3:0] $add$ls180.v:7997$2543_Y
- attribute \src "ls180.v:7998.4-8012.7"
- switch $eq$ls180.v:7998$2544_Y
- attribute \src "ls180.v:7998.8-7998.43"
+ assign $0\main_uart_phy_rx_bitcount[3:0] $add$ls180.v:7993$2543_Y
+ attribute \src "ls180.v:7994.4-8008.7"
+ switch $eq$ls180.v:7994$2544_Y
+ attribute \src "ls180.v:7994.8-7994.43"
case 1'1
- attribute \src "ls180.v:7999.5-8001.8"
+ attribute \src "ls180.v:7995.5-7997.8"
switch \main_uart_phy_rx
- attribute \src "ls180.v:7999.9-7999.25"
+ attribute \src "ls180.v:7995.9-7995.25"
case 1'1
assign $0\main_uart_phy_rx_busy[0:0] 1'0
case
end
- attribute \src "ls180.v:8002.8-8002.12"
+ attribute \src "ls180.v:7998.8-7998.12"
case
- attribute \src "ls180.v:8003.5-8011.8"
- switch $eq$ls180.v:8003$2545_Y
- attribute \src "ls180.v:8003.9-8003.44"
+ attribute \src "ls180.v:7999.5-8007.8"
+ switch $eq$ls180.v:7999$2545_Y
+ attribute \src "ls180.v:7999.9-7999.44"
case 1'1
assign $0\main_uart_phy_rx_busy[0:0] 1'0
- attribute \src "ls180.v:8005.6-8008.9"
+ attribute \src "ls180.v:8001.6-8004.9"
switch \main_uart_phy_rx
- attribute \src "ls180.v:8005.10-8005.26"
+ attribute \src "ls180.v:8001.10-8001.26"
case 1'1
assign $0\main_uart_phy_source_payload_data[7:0] \main_uart_phy_rx_reg
assign $0\main_uart_phy_source_valid[0:0] 1'1
case
end
- attribute \src "ls180.v:8009.9-8009.13"
+ attribute \src "ls180.v:8005.9-8005.13"
case
assign $0\main_uart_phy_rx_reg[7:0] { \main_uart_phy_rx \main_uart_phy_rx_reg [7:1] }
end
case
end
end
- attribute \src "ls180.v:8015.2-8019.5"
+ attribute \src "ls180.v:8011.2-8015.5"
switch \main_uart_phy_rx_busy
- attribute \src "ls180.v:8015.6-8015.27"
+ attribute \src "ls180.v:8011.6-8011.27"
case 1'1
- assign { $0\main_uart_phy_uart_clk_rxen[0:0] $0\main_uart_phy_phase_accumulator_rx[31:0] } $add$ls180.v:8016$2546_Y
- attribute \src "ls180.v:8017.6-8017.10"
+ assign { $0\main_uart_phy_uart_clk_rxen[0:0] $0\main_uart_phy_phase_accumulator_rx[31:0] } $add$ls180.v:8012$2546_Y
+ attribute \src "ls180.v:8013.6-8013.10"
case
assign { $0\main_uart_phy_uart_clk_rxen[0:0] $0\main_uart_phy_phase_accumulator_rx[31:0] } 33'010000000000000000000000000000000
end
- attribute \src "ls180.v:8020.2-8022.5"
+ attribute \src "ls180.v:8016.2-8018.5"
switch \main_uart_tx_clear
- attribute \src "ls180.v:8020.6-8020.24"
+ attribute \src "ls180.v:8016.6-8016.24"
case 1'1
assign $0\main_uart_tx_pending[0:0] 1'0
case
end
- attribute \src "ls180.v:8024.2-8026.5"
- switch $and$ls180.v:8024$2548_Y
- attribute \src "ls180.v:8024.6-8024.58"
+ attribute \src "ls180.v:8020.2-8022.5"
+ switch $and$ls180.v:8020$2548_Y
+ attribute \src "ls180.v:8020.6-8020.58"
case 1'1
assign $0\main_uart_tx_pending[0:0] 1'1
case
end
- attribute \src "ls180.v:8027.2-8029.5"
+ attribute \src "ls180.v:8023.2-8025.5"
switch \main_uart_rx_clear
- attribute \src "ls180.v:8027.6-8027.24"
+ attribute \src "ls180.v:8023.6-8023.24"
case 1'1
assign $0\main_uart_rx_pending[0:0] 1'0
case
end
- attribute \src "ls180.v:8031.2-8033.5"
- switch $and$ls180.v:8031$2550_Y
- attribute \src "ls180.v:8031.6-8031.58"
+ attribute \src "ls180.v:8027.2-8029.5"
+ switch $and$ls180.v:8027$2550_Y
+ attribute \src "ls180.v:8027.6-8027.58"
case 1'1
assign $0\main_uart_rx_pending[0:0] 1'1
case
end
- attribute \src "ls180.v:8034.2-8040.5"
+ attribute \src "ls180.v:8030.2-8036.5"
switch \main_uart_tx_fifo_syncfifo_re
- attribute \src "ls180.v:8034.6-8034.35"
+ attribute \src "ls180.v:8030.6-8030.35"
case 1'1
assign $0\main_uart_tx_fifo_readable[0:0] 1'1
- attribute \src "ls180.v:8036.6-8036.10"
+ attribute \src "ls180.v:8032.6-8032.10"
case
- attribute \src "ls180.v:8037.3-8039.6"
+ attribute \src "ls180.v:8033.3-8035.6"
switch \main_uart_tx_fifo_re
- attribute \src "ls180.v:8037.7-8037.27"
+ attribute \src "ls180.v:8033.7-8033.27"
case 1'1
assign $0\main_uart_tx_fifo_readable[0:0] 1'0
case
end
end
- attribute \src "ls180.v:8041.2-8043.5"
- switch $and$ls180.v:8041$2553_Y
- attribute \src "ls180.v:8041.6-8041.108"
+ attribute \src "ls180.v:8037.2-8039.5"
+ switch $and$ls180.v:8037$2553_Y
+ attribute \src "ls180.v:8037.6-8037.108"
case 1'1
- assign $0\main_uart_tx_fifo_produce[3:0] $add$ls180.v:8042$2554_Y
+ assign $0\main_uart_tx_fifo_produce[3:0] $add$ls180.v:8038$2554_Y
case
end
- attribute \src "ls180.v:8044.2-8046.5"
+ attribute \src "ls180.v:8040.2-8042.5"
switch \main_uart_tx_fifo_do_read
- attribute \src "ls180.v:8044.6-8044.31"
+ attribute \src "ls180.v:8040.6-8040.31"
case 1'1
- assign $0\main_uart_tx_fifo_consume[3:0] $add$ls180.v:8045$2555_Y
+ assign $0\main_uart_tx_fifo_consume[3:0] $add$ls180.v:8041$2555_Y
case
end
- attribute \src "ls180.v:8047.2-8055.5"
- switch $and$ls180.v:8047$2558_Y
- attribute \src "ls180.v:8047.6-8047.108"
+ attribute \src "ls180.v:8043.2-8051.5"
+ switch $and$ls180.v:8043$2558_Y
+ attribute \src "ls180.v:8043.6-8043.108"
case 1'1
- attribute \src "ls180.v:8048.3-8050.6"
- switch $not$ls180.v:8048$2559_Y
- attribute \src "ls180.v:8048.7-8048.35"
+ attribute \src "ls180.v:8044.3-8046.6"
+ switch $not$ls180.v:8044$2559_Y
+ attribute \src "ls180.v:8044.7-8044.35"
case 1'1
- assign $0\main_uart_tx_fifo_level0[4:0] $add$ls180.v:8049$2560_Y
+ assign $0\main_uart_tx_fifo_level0[4:0] $add$ls180.v:8045$2560_Y
case
end
- attribute \src "ls180.v:8051.6-8051.10"
+ attribute \src "ls180.v:8047.6-8047.10"
case
- attribute \src "ls180.v:8052.3-8054.6"
+ attribute \src "ls180.v:8048.3-8050.6"
switch \main_uart_tx_fifo_do_read
- attribute \src "ls180.v:8052.7-8052.32"
+ attribute \src "ls180.v:8048.7-8048.32"
case 1'1
- assign $0\main_uart_tx_fifo_level0[4:0] $sub$ls180.v:8053$2561_Y
+ assign $0\main_uart_tx_fifo_level0[4:0] $sub$ls180.v:8049$2561_Y
case
end
end
- attribute \src "ls180.v:8056.2-8062.5"
+ attribute \src "ls180.v:8052.2-8058.5"
switch \main_uart_rx_fifo_syncfifo_re
- attribute \src "ls180.v:8056.6-8056.35"
+ attribute \src "ls180.v:8052.6-8052.35"
case 1'1
assign $0\main_uart_rx_fifo_readable[0:0] 1'1
- attribute \src "ls180.v:8058.6-8058.10"
+ attribute \src "ls180.v:8054.6-8054.10"
case
- attribute \src "ls180.v:8059.3-8061.6"
+ attribute \src "ls180.v:8055.3-8057.6"
switch \main_uart_rx_fifo_re
- attribute \src "ls180.v:8059.7-8059.27"
+ attribute \src "ls180.v:8055.7-8055.27"
case 1'1
assign $0\main_uart_rx_fifo_readable[0:0] 1'0
case
end
end
- attribute \src "ls180.v:8063.2-8065.5"
- switch $and$ls180.v:8063$2564_Y
- attribute \src "ls180.v:8063.6-8063.108"
+ attribute \src "ls180.v:8059.2-8061.5"
+ switch $and$ls180.v:8059$2564_Y
+ attribute \src "ls180.v:8059.6-8059.108"
case 1'1
- assign $0\main_uart_rx_fifo_produce[3:0] $add$ls180.v:8064$2565_Y
+ assign $0\main_uart_rx_fifo_produce[3:0] $add$ls180.v:8060$2565_Y
case
end
- attribute \src "ls180.v:8066.2-8068.5"
+ attribute \src "ls180.v:8062.2-8064.5"
switch \main_uart_rx_fifo_do_read
- attribute \src "ls180.v:8066.6-8066.31"
+ attribute \src "ls180.v:8062.6-8062.31"
case 1'1
- assign $0\main_uart_rx_fifo_consume[3:0] $add$ls180.v:8067$2566_Y
+ assign $0\main_uart_rx_fifo_consume[3:0] $add$ls180.v:8063$2566_Y
case
end
- attribute \src "ls180.v:8069.2-8077.5"
- switch $and$ls180.v:8069$2569_Y
- attribute \src "ls180.v:8069.6-8069.108"
+ attribute \src "ls180.v:8065.2-8073.5"
+ switch $and$ls180.v:8065$2569_Y
+ attribute \src "ls180.v:8065.6-8065.108"
case 1'1
- attribute \src "ls180.v:8070.3-8072.6"
- switch $not$ls180.v:8070$2570_Y
- attribute \src "ls180.v:8070.7-8070.35"
+ attribute \src "ls180.v:8066.3-8068.6"
+ switch $not$ls180.v:8066$2570_Y
+ attribute \src "ls180.v:8066.7-8066.35"
case 1'1
- assign $0\main_uart_rx_fifo_level0[4:0] $add$ls180.v:8071$2571_Y
+ assign $0\main_uart_rx_fifo_level0[4:0] $add$ls180.v:8067$2571_Y
case
end
- attribute \src "ls180.v:8073.6-8073.10"
+ attribute \src "ls180.v:8069.6-8069.10"
case
- attribute \src "ls180.v:8074.3-8076.6"
+ attribute \src "ls180.v:8070.3-8072.6"
switch \main_uart_rx_fifo_do_read
- attribute \src "ls180.v:8074.7-8074.32"
+ attribute \src "ls180.v:8070.7-8070.32"
case 1'1
- assign $0\main_uart_rx_fifo_level0[4:0] $sub$ls180.v:8075$2572_Y
+ assign $0\main_uart_rx_fifo_level0[4:0] $sub$ls180.v:8071$2572_Y
case
end
end
- attribute \src "ls180.v:8078.2-8091.5"
+ attribute \src "ls180.v:8074.2-8087.5"
switch \main_uart_reset
- attribute \src "ls180.v:8078.6-8078.21"
+ attribute \src "ls180.v:8074.6-8074.21"
case 1'1
assign $0\main_uart_tx_pending[0:0] 1'0
assign $0\main_uart_tx_old_trigger[0:0] 1'0
assign $0\main_uart_rx_fifo_consume[3:0] 4'0000
case
end
- attribute \src "ls180.v:8093.2-8100.5"
+ attribute \src "ls180.v:8089.2-8096.5"
switch \main_spimaster31_clk_rise
- attribute \src "ls180.v:8093.6-8093.31"
+ attribute \src "ls180.v:8089.6-8089.31"
case 1'1
assign $0\spisdcard_clk[0:0] \main_spimaster25_clk_enable
- attribute \src "ls180.v:8095.6-8095.10"
+ attribute \src "ls180.v:8091.6-8091.10"
case
- attribute \src "ls180.v:8096.3-8099.6"
+ attribute \src "ls180.v:8092.3-8095.6"
switch \main_spimaster32_clk_fall
- attribute \src "ls180.v:8096.7-8096.32"
+ attribute \src "ls180.v:8092.7-8092.32"
case 1'1
assign $0\main_spimaster30_clk_divider[15:0] 16'0000000000000000
assign $0\spisdcard_clk[0:0] 1'0
case
end
end
- attribute \src "ls180.v:8102.2-8112.5"
+ attribute \src "ls180.v:8098.2-8108.5"
switch \main_spimaster28_mosi_latch
- attribute \src "ls180.v:8102.6-8102.33"
+ attribute \src "ls180.v:8098.6-8098.33"
case 1'1
assign $0\main_spimaster33_mosi_data[7:0] \main_spimaster4_mosi
assign $0\main_spimaster34_mosi_sel[2:0] 3'111
- attribute \src "ls180.v:8105.6-8105.10"
+ attribute \src "ls180.v:8101.6-8101.10"
case
- attribute \src "ls180.v:8106.3-8111.6"
+ attribute \src "ls180.v:8102.3-8107.6"
switch \main_spimaster32_clk_fall
- attribute \src "ls180.v:8106.7-8106.32"
+ attribute \src "ls180.v:8102.7-8102.32"
case 1'1
- assign $0\main_spimaster34_mosi_sel[2:0] $sub$ls180.v:8110$2577_Y
- attribute \src "ls180.v:8107.4-8109.7"
+ assign $0\main_spimaster34_mosi_sel[2:0] $sub$ls180.v:8106$2577_Y
+ attribute \src "ls180.v:8103.4-8105.7"
switch \main_spimaster26_cs_enable
- attribute \src "ls180.v:8107.8-8107.34"
+ attribute \src "ls180.v:8103.8-8103.34"
case 1'1
assign $0\spisdcard_mosi[0:0] \builder_sync_f_array_muxed0
case
case
end
end
- attribute \src "ls180.v:8113.2-8119.5"
+ attribute \src "ls180.v:8109.2-8115.5"
switch \main_spimaster31_clk_rise
- attribute \src "ls180.v:8113.6-8113.31"
+ attribute \src "ls180.v:8109.6-8109.31"
case 1'1
- attribute \src "ls180.v:8114.3-8118.6"
+ attribute \src "ls180.v:8110.3-8114.6"
switch \main_spimaster7_loopback
- attribute \src "ls180.v:8114.7-8114.31"
+ attribute \src "ls180.v:8110.7-8110.31"
case 1'1
assign $0\main_spimaster35_miso_data[7:0] { \main_spimaster35_miso_data [6:0] \spisdcard_mosi }
- attribute \src "ls180.v:8116.7-8116.11"
+ attribute \src "ls180.v:8112.7-8112.11"
case
assign $0\main_spimaster35_miso_data[7:0] { \main_spimaster35_miso_data [6:0] \spisdcard_miso }
end
case
end
- attribute \src "ls180.v:8120.2-8122.5"
+ attribute \src "ls180.v:8116.2-8118.5"
switch \main_spimaster29_miso_latch
- attribute \src "ls180.v:8120.6-8120.33"
+ attribute \src "ls180.v:8116.6-8116.33"
case 1'1
assign $0\main_spimaster5_miso[7:0] \main_spimaster35_miso_data
case
end
- attribute \src "ls180.v:8124.2-8126.5"
+ attribute \src "ls180.v:8120.2-8122.5"
switch \main_spimaster27_count_spimaster0_next_value_ce
- attribute \src "ls180.v:8124.6-8124.53"
+ attribute \src "ls180.v:8120.6-8120.53"
case 1'1
assign $0\main_spimaster27_count[2:0] \main_spimaster27_count_spimaster0_next_value
case
end
- attribute \src "ls180.v:8128.2-8135.5"
+ attribute \src "ls180.v:8124.2-8131.5"
switch \main_spisdcard_clk_rise
- attribute \src "ls180.v:8128.6-8128.29"
+ attribute \src "ls180.v:8124.6-8124.29"
case 1'1
assign $0\spimaster_clk[0:0] \main_spisdcard_clk_enable
- attribute \src "ls180.v:8130.6-8130.10"
+ attribute \src "ls180.v:8126.6-8126.10"
case
- attribute \src "ls180.v:8131.3-8134.6"
+ attribute \src "ls180.v:8127.3-8130.6"
switch \main_spisdcard_clk_fall
- attribute \src "ls180.v:8131.7-8131.30"
+ attribute \src "ls180.v:8127.7-8127.30"
case 1'1
assign $0\main_spisdcard_clk_divider1[15:0] 16'0000000000000000
assign $0\spimaster_clk[0:0] 1'0
case
end
end
- attribute \src "ls180.v:8137.2-8147.5"
+ attribute \src "ls180.v:8133.2-8143.5"
switch \main_spisdcard_mosi_latch
- attribute \src "ls180.v:8137.6-8137.31"
+ attribute \src "ls180.v:8133.6-8133.31"
case 1'1
assign $0\main_spisdcard_mosi_data[7:0] \main_spisdcard_mosi
assign $0\main_spisdcard_mosi_sel[2:0] 3'111
- attribute \src "ls180.v:8140.6-8140.10"
+ attribute \src "ls180.v:8136.6-8136.10"
case
- attribute \src "ls180.v:8141.3-8146.6"
+ attribute \src "ls180.v:8137.3-8142.6"
switch \main_spisdcard_clk_fall
- attribute \src "ls180.v:8141.7-8141.30"
+ attribute \src "ls180.v:8137.7-8137.30"
case 1'1
- assign $0\main_spisdcard_mosi_sel[2:0] $sub$ls180.v:8145$2582_Y
- attribute \src "ls180.v:8142.4-8144.7"
+ assign $0\main_spisdcard_mosi_sel[2:0] $sub$ls180.v:8141$2582_Y
+ attribute \src "ls180.v:8138.4-8140.7"
switch \main_spisdcard_cs_enable
- attribute \src "ls180.v:8142.8-8142.32"
+ attribute \src "ls180.v:8138.8-8138.32"
case 1'1
assign $0\spimaster_mosi[0:0] \builder_sync_f_array_muxed1
case
case
end
end
- attribute \src "ls180.v:8148.2-8154.5"
+ attribute \src "ls180.v:8144.2-8150.5"
switch \main_spisdcard_clk_rise
- attribute \src "ls180.v:8148.6-8148.29"
+ attribute \src "ls180.v:8144.6-8144.29"
case 1'1
- attribute \src "ls180.v:8149.3-8153.6"
+ attribute \src "ls180.v:8145.3-8149.6"
switch \main_spisdcard_loopback
- attribute \src "ls180.v:8149.7-8149.30"
+ attribute \src "ls180.v:8145.7-8145.30"
case 1'1
assign $0\main_spisdcard_miso_data[7:0] { \main_spisdcard_miso_data [6:0] \spimaster_mosi }
- attribute \src "ls180.v:8151.7-8151.11"
+ attribute \src "ls180.v:8147.7-8147.11"
case
assign $0\main_spisdcard_miso_data[7:0] { \main_spisdcard_miso_data [6:0] \spimaster_miso }
end
case
end
- attribute \src "ls180.v:8155.2-8157.5"
+ attribute \src "ls180.v:8151.2-8153.5"
switch \main_spisdcard_miso_latch
- attribute \src "ls180.v:8155.6-8155.31"
+ attribute \src "ls180.v:8151.6-8151.31"
case 1'1
assign $0\main_spisdcard_miso[7:0] \main_spisdcard_miso_data
case
end
- attribute \src "ls180.v:8159.2-8161.5"
+ attribute \src "ls180.v:8155.2-8157.5"
switch \main_spisdcard_count_spimaster1_next_value_ce
- attribute \src "ls180.v:8159.6-8159.51"
+ attribute \src "ls180.v:8155.6-8155.51"
case 1'1
assign $0\main_spisdcard_count[2:0] \main_spisdcard_count_spimaster1_next_value
case
end
- attribute \src "ls180.v:8162.2-8175.5"
+ attribute \src "ls180.v:8158.2-8171.5"
switch \main_pwm0_enable
- attribute \src "ls180.v:8162.6-8162.22"
+ attribute \src "ls180.v:8158.6-8158.22"
case 1'1
- assign $0\main_pwm0_counter[31:0] $add$ls180.v:8163$2583_Y
- attribute \src "ls180.v:8164.3-8168.6"
- switch $lt$ls180.v:8164$2584_Y
- attribute \src "ls180.v:8164.7-8164.44"
+ assign $0\main_pwm0_counter[31:0] $add$ls180.v:8159$2583_Y
+ attribute \src "ls180.v:8160.3-8164.6"
+ switch $lt$ls180.v:8160$2584_Y
+ attribute \src "ls180.v:8160.7-8160.44"
case 1'1
assign $0\pwm[1:0] [0] 1'1
- attribute \src "ls180.v:8166.7-8166.11"
+ attribute \src "ls180.v:8162.7-8162.11"
case
assign $0\pwm[1:0] [0] 1'0
end
- attribute \src "ls180.v:8169.3-8171.6"
- switch $ge$ls180.v:8169$2586_Y
- attribute \src "ls180.v:8169.7-8169.55"
+ attribute \src "ls180.v:8165.3-8167.6"
+ switch $ge$ls180.v:8165$2586_Y
+ attribute \src "ls180.v:8165.7-8165.55"
case 1'1
assign $0\main_pwm0_counter[31:0] 0
case
end
- attribute \src "ls180.v:8172.6-8172.10"
+ attribute \src "ls180.v:8168.6-8168.10"
case
assign $0\main_pwm0_counter[31:0] 0
assign $0\pwm[1:0] [0] 1'0
end
- attribute \src "ls180.v:8176.2-8189.5"
+ attribute \src "ls180.v:8172.2-8185.5"
switch \main_pwm1_enable
- attribute \src "ls180.v:8176.6-8176.22"
+ attribute \src "ls180.v:8172.6-8172.22"
case 1'1
- assign $0\main_pwm1_counter[31:0] $add$ls180.v:8177$2587_Y
- attribute \src "ls180.v:8178.3-8182.6"
- switch $lt$ls180.v:8178$2588_Y
- attribute \src "ls180.v:8178.7-8178.44"
+ assign $0\main_pwm1_counter[31:0] $add$ls180.v:8173$2587_Y
+ attribute \src "ls180.v:8174.3-8178.6"
+ switch $lt$ls180.v:8174$2588_Y
+ attribute \src "ls180.v:8174.7-8174.44"
case 1'1
assign $0\pwm[1:0] [1] 1'1
- attribute \src "ls180.v:8180.7-8180.11"
+ attribute \src "ls180.v:8176.7-8176.11"
case
assign $0\pwm[1:0] [1] 1'0
end
- attribute \src "ls180.v:8183.3-8185.6"
- switch $ge$ls180.v:8183$2590_Y
- attribute \src "ls180.v:8183.7-8183.55"
+ attribute \src "ls180.v:8179.3-8181.6"
+ switch $ge$ls180.v:8179$2590_Y
+ attribute \src "ls180.v:8179.7-8179.55"
case 1'1
assign $0\main_pwm1_counter[31:0] 0
case
end
- attribute \src "ls180.v:8186.6-8186.10"
+ attribute \src "ls180.v:8182.6-8182.10"
case
assign $0\main_pwm1_counter[31:0] 0
assign $0\pwm[1:0] [1] 1'0
end
- attribute \src "ls180.v:8190.2-8192.5"
- switch $not$ls180.v:8190$2591_Y
- attribute \src "ls180.v:8190.6-8190.32"
+ attribute \src "ls180.v:8186.2-8188.5"
+ switch $not$ls180.v:8186$2591_Y
+ attribute \src "ls180.v:8186.6-8186.32"
case 1'1
- assign $0\main_sdphy_clocker_clks[8:0] $add$ls180.v:8191$2592_Y
+ assign $0\main_sdphy_clocker_clks[8:0] $add$ls180.v:8187$2592_Y
case
end
- attribute \src "ls180.v:8196.2-8198.5"
+ attribute \src "ls180.v:8192.2-8194.5"
switch \main_sdphy_init_count_sdphy_sdphyinit_next_value_ce
- attribute \src "ls180.v:8196.6-8196.57"
+ attribute \src "ls180.v:8192.6-8192.57"
case 1'1
assign $0\main_sdphy_init_count[7:0] \main_sdphy_init_count_sdphy_sdphyinit_next_value
case
end
- attribute \src "ls180.v:8200.2-8202.5"
+ attribute \src "ls180.v:8196.2-8198.5"
switch \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce
- attribute \src "ls180.v:8200.6-8200.57"
+ attribute \src "ls180.v:8196.6-8196.57"
case 1'1
assign $0\main_sdphy_cmdw_count[7:0] \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value
case
end
- attribute \src "ls180.v:8203.2-8205.5"
+ attribute \src "ls180.v:8199.2-8201.5"
switch \main_sdphy_cmdr_cmdr_pads_in_valid
- attribute \src "ls180.v:8203.6-8203.40"
+ attribute \src "ls180.v:8199.6-8199.40"
case 1'1
- assign $0\main_sdphy_cmdr_cmdr_run[0:0] $or$ls180.v:8204$2593_Y
+ assign $0\main_sdphy_cmdr_cmdr_run[0:0] $or$ls180.v:8200$2593_Y
case
end
- attribute \src "ls180.v:8206.2-8208.5"
+ attribute \src "ls180.v:8202.2-8204.5"
switch \main_sdphy_cmdr_cmdr_converter_source_ready
- attribute \src "ls180.v:8206.6-8206.49"
+ attribute \src "ls180.v:8202.6-8202.49"
case 1'1
assign $0\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] 1'0
case
end
- attribute \src "ls180.v:8209.2-8216.5"
+ attribute \src "ls180.v:8205.2-8212.5"
switch \main_sdphy_cmdr_cmdr_converter_load_part
- attribute \src "ls180.v:8209.6-8209.46"
+ attribute \src "ls180.v:8205.6-8205.46"
case 1'1
- attribute \src "ls180.v:8210.3-8215.6"
- switch $or$ls180.v:8210$2595_Y
- attribute \src "ls180.v:8210.7-8210.98"
+ attribute \src "ls180.v:8206.3-8211.6"
+ switch $or$ls180.v:8206$2595_Y
+ attribute \src "ls180.v:8206.7-8206.98"
case 1'1
assign $0\main_sdphy_cmdr_cmdr_converter_demux[2:0] 3'000
assign $0\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] 1'1
- attribute \src "ls180.v:8213.7-8213.11"
+ attribute \src "ls180.v:8209.7-8209.11"
case
- assign $0\main_sdphy_cmdr_cmdr_converter_demux[2:0] $add$ls180.v:8214$2596_Y
+ assign $0\main_sdphy_cmdr_cmdr_converter_demux[2:0] $add$ls180.v:8210$2596_Y
end
case
end
- attribute \src "ls180.v:8217.2-8230.5"
- switch $and$ls180.v:8217$2597_Y
- attribute \src "ls180.v:8217.6-8217.97"
+ attribute \src "ls180.v:8213.2-8226.5"
+ switch $and$ls180.v:8213$2597_Y
+ attribute \src "ls180.v:8213.6-8213.97"
case 1'1
- attribute \src "ls180.v:8218.3-8224.6"
- switch $and$ls180.v:8218$2598_Y
- attribute \src "ls180.v:8218.7-8218.94"
+ attribute \src "ls180.v:8214.3-8220.6"
+ switch $and$ls180.v:8214$2598_Y
+ attribute \src "ls180.v:8214.7-8214.94"
case 1'1
assign $0\main_sdphy_cmdr_cmdr_converter_source_first[0:0] \main_sdphy_cmdr_cmdr_converter_sink_first
assign $0\main_sdphy_cmdr_cmdr_converter_source_last[0:0] \main_sdphy_cmdr_cmdr_converter_sink_last
- attribute \src "ls180.v:8221.7-8221.11"
+ attribute \src "ls180.v:8217.7-8217.11"
case
assign $0\main_sdphy_cmdr_cmdr_converter_source_first[0:0] 1'0
assign $0\main_sdphy_cmdr_cmdr_converter_source_last[0:0] 1'0
end
- attribute \src "ls180.v:8225.6-8225.10"
+ attribute \src "ls180.v:8221.6-8221.10"
case
- attribute \src "ls180.v:8226.3-8229.6"
- switch $and$ls180.v:8226$2599_Y
- attribute \src "ls180.v:8226.7-8226.94"
+ attribute \src "ls180.v:8222.3-8225.6"
+ switch $and$ls180.v:8222$2599_Y
+ attribute \src "ls180.v:8222.7-8222.94"
case 1'1
- assign $0\main_sdphy_cmdr_cmdr_converter_source_first[0:0] $or$ls180.v:8227$2600_Y
- assign $0\main_sdphy_cmdr_cmdr_converter_source_last[0:0] $or$ls180.v:8228$2601_Y
+ assign $0\main_sdphy_cmdr_cmdr_converter_source_first[0:0] $or$ls180.v:8223$2600_Y
+ assign $0\main_sdphy_cmdr_cmdr_converter_source_last[0:0] $or$ls180.v:8224$2601_Y
case
end
end
- attribute \src "ls180.v:8231.2-8258.5"
+ attribute \src "ls180.v:8227.2-8254.5"
switch \main_sdphy_cmdr_cmdr_converter_load_part
- attribute \src "ls180.v:8231.6-8231.46"
+ attribute \src "ls180.v:8227.6-8227.46"
case 1'1
- attribute \src "ls180.v:8232.3-8257.10"
+ attribute \src "ls180.v:8228.3-8253.10"
switch \main_sdphy_cmdr_cmdr_converter_demux
attribute \src "ls180.v:0.0-0.0"
case 3'000
end
case
end
- attribute \src "ls180.v:8259.2-8261.5"
+ attribute \src "ls180.v:8255.2-8257.5"
switch \main_sdphy_cmdr_cmdr_converter_load_part
- attribute \src "ls180.v:8259.6-8259.46"
+ attribute \src "ls180.v:8255.6-8255.46"
case 1'1
- assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count[3:0] $add$ls180.v:8260$2602_Y
+ assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count[3:0] $add$ls180.v:8256$2602_Y
case
end
- attribute \src "ls180.v:8262.2-8267.5"
- switch $or$ls180.v:8262$2604_Y
- attribute \src "ls180.v:8262.6-8262.88"
+ attribute \src "ls180.v:8258.2-8263.5"
+ switch $or$ls180.v:8258$2604_Y
+ attribute \src "ls180.v:8258.6-8258.88"
case 1'1
assign $0\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] \main_sdphy_cmdr_cmdr_buf_sink_valid
assign $0\main_sdphy_cmdr_cmdr_buf_source_first[0:0] \main_sdphy_cmdr_cmdr_buf_sink_first
assign $0\main_sdphy_cmdr_cmdr_buf_source_payload_data[7:0] \main_sdphy_cmdr_cmdr_buf_sink_payload_data
case
end
- attribute \src "ls180.v:8268.2-8273.5"
+ attribute \src "ls180.v:8264.2-8269.5"
switch \main_sdphy_cmdr_cmdr_reset
- attribute \src "ls180.v:8268.6-8268.32"
+ attribute \src "ls180.v:8264.6-8264.32"
case 1'1
assign $0\main_sdphy_cmdr_cmdr_run[0:0] 1'0
assign $0\main_sdphy_cmdr_cmdr_converter_demux[2:0] 3'000
assign $0\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] 1'0
case
end
- attribute \src "ls180.v:8275.2-8277.5"
+ attribute \src "ls180.v:8271.2-8273.5"
switch \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0
- attribute \src "ls180.v:8275.6-8275.58"
+ attribute \src "ls180.v:8271.6-8271.58"
case 1'1
assign $0\main_sdphy_cmdr_count[7:0] \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0
case
end
- attribute \src "ls180.v:8278.2-8280.5"
+ attribute \src "ls180.v:8274.2-8276.5"
switch \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1
- attribute \src "ls180.v:8278.6-8278.60"
+ attribute \src "ls180.v:8274.6-8274.60"
case 1'1
assign $0\main_sdphy_cmdr_timeout[31:0] \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1
case
end
- attribute \src "ls180.v:8281.2-8283.5"
+ attribute \src "ls180.v:8277.2-8279.5"
switch \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2
- attribute \src "ls180.v:8281.6-8281.63"
+ attribute \src "ls180.v:8277.6-8277.63"
case 1'1
assign $0\main_sdphy_cmdr_cmdr_reset[0:0] \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2
case
end
- attribute \src "ls180.v:8284.2-8286.5"
+ attribute \src "ls180.v:8280.2-8282.5"
switch \main_sdphy_dataw_crcr_pads_in_valid
- attribute \src "ls180.v:8284.6-8284.41"
+ attribute \src "ls180.v:8280.6-8280.41"
case 1'1
- assign $0\main_sdphy_dataw_crcr_run[0:0] $or$ls180.v:8285$2605_Y
+ assign $0\main_sdphy_dataw_crcr_run[0:0] $or$ls180.v:8281$2605_Y
case
end
- attribute \src "ls180.v:8287.2-8289.5"
+ attribute \src "ls180.v:8283.2-8285.5"
switch \main_sdphy_dataw_crcr_converter_source_ready
- attribute \src "ls180.v:8287.6-8287.50"
+ attribute \src "ls180.v:8283.6-8283.50"
case 1'1
assign $0\main_sdphy_dataw_crcr_converter_strobe_all[0:0] 1'0
case
end
- attribute \src "ls180.v:8290.2-8297.5"
+ attribute \src "ls180.v:8286.2-8293.5"
switch \main_sdphy_dataw_crcr_converter_load_part
- attribute \src "ls180.v:8290.6-8290.47"
+ attribute \src "ls180.v:8286.6-8286.47"
case 1'1
- attribute \src "ls180.v:8291.3-8296.6"
- switch $or$ls180.v:8291$2607_Y
- attribute \src "ls180.v:8291.7-8291.100"
+ attribute \src "ls180.v:8287.3-8292.6"
+ switch $or$ls180.v:8287$2607_Y
+ attribute \src "ls180.v:8287.7-8287.100"
case 1'1
assign $0\main_sdphy_dataw_crcr_converter_demux[2:0] 3'000
assign $0\main_sdphy_dataw_crcr_converter_strobe_all[0:0] 1'1
- attribute \src "ls180.v:8294.7-8294.11"
+ attribute \src "ls180.v:8290.7-8290.11"
case
- assign $0\main_sdphy_dataw_crcr_converter_demux[2:0] $add$ls180.v:8295$2608_Y
+ assign $0\main_sdphy_dataw_crcr_converter_demux[2:0] $add$ls180.v:8291$2608_Y
end
case
end
- attribute \src "ls180.v:8298.2-8311.5"
- switch $and$ls180.v:8298$2609_Y
- attribute \src "ls180.v:8298.6-8298.99"
+ attribute \src "ls180.v:8294.2-8307.5"
+ switch $and$ls180.v:8294$2609_Y
+ attribute \src "ls180.v:8294.6-8294.99"
case 1'1
- attribute \src "ls180.v:8299.3-8305.6"
- switch $and$ls180.v:8299$2610_Y
- attribute \src "ls180.v:8299.7-8299.96"
+ attribute \src "ls180.v:8295.3-8301.6"
+ switch $and$ls180.v:8295$2610_Y
+ attribute \src "ls180.v:8295.7-8295.96"
case 1'1
assign $0\main_sdphy_dataw_crcr_converter_source_first[0:0] \main_sdphy_dataw_crcr_converter_sink_first
assign $0\main_sdphy_dataw_crcr_converter_source_last[0:0] \main_sdphy_dataw_crcr_converter_sink_last
- attribute \src "ls180.v:8302.7-8302.11"
+ attribute \src "ls180.v:8298.7-8298.11"
case
assign $0\main_sdphy_dataw_crcr_converter_source_first[0:0] 1'0
assign $0\main_sdphy_dataw_crcr_converter_source_last[0:0] 1'0
end
- attribute \src "ls180.v:8306.6-8306.10"
+ attribute \src "ls180.v:8302.6-8302.10"
case
- attribute \src "ls180.v:8307.3-8310.6"
- switch $and$ls180.v:8307$2611_Y
- attribute \src "ls180.v:8307.7-8307.96"
+ attribute \src "ls180.v:8303.3-8306.6"
+ switch $and$ls180.v:8303$2611_Y
+ attribute \src "ls180.v:8303.7-8303.96"
case 1'1
- assign $0\main_sdphy_dataw_crcr_converter_source_first[0:0] $or$ls180.v:8308$2612_Y
- assign $0\main_sdphy_dataw_crcr_converter_source_last[0:0] $or$ls180.v:8309$2613_Y
+ assign $0\main_sdphy_dataw_crcr_converter_source_first[0:0] $or$ls180.v:8304$2612_Y
+ assign $0\main_sdphy_dataw_crcr_converter_source_last[0:0] $or$ls180.v:8305$2613_Y
case
end
end
- attribute \src "ls180.v:8312.2-8339.5"
+ attribute \src "ls180.v:8308.2-8335.5"
switch \main_sdphy_dataw_crcr_converter_load_part
- attribute \src "ls180.v:8312.6-8312.47"
+ attribute \src "ls180.v:8308.6-8308.47"
case 1'1
- attribute \src "ls180.v:8313.3-8338.10"
+ attribute \src "ls180.v:8309.3-8334.10"
switch \main_sdphy_dataw_crcr_converter_demux
attribute \src "ls180.v:0.0-0.0"
case 3'000
end
case
end
- attribute \src "ls180.v:8340.2-8342.5"
+ attribute \src "ls180.v:8336.2-8338.5"
switch \main_sdphy_dataw_crcr_converter_load_part
- attribute \src "ls180.v:8340.6-8340.47"
+ attribute \src "ls180.v:8336.6-8336.47"
case 1'1
- assign $0\main_sdphy_dataw_crcr_converter_source_payload_valid_token_count[3:0] $add$ls180.v:8341$2614_Y
+ assign $0\main_sdphy_dataw_crcr_converter_source_payload_valid_token_count[3:0] $add$ls180.v:8337$2614_Y
case
end
- attribute \src "ls180.v:8343.2-8348.5"
- switch $or$ls180.v:8343$2616_Y
- attribute \src "ls180.v:8343.6-8343.90"
+ attribute \src "ls180.v:8339.2-8344.5"
+ switch $or$ls180.v:8339$2616_Y
+ attribute \src "ls180.v:8339.6-8339.90"
case 1'1
assign $0\main_sdphy_dataw_crcr_buf_source_valid[0:0] \main_sdphy_dataw_crcr_buf_sink_valid
assign $0\main_sdphy_dataw_crcr_buf_source_first[0:0] \main_sdphy_dataw_crcr_buf_sink_first
assign $0\main_sdphy_dataw_crcr_buf_source_payload_data[7:0] \main_sdphy_dataw_crcr_buf_sink_payload_data
case
end
- attribute \src "ls180.v:8349.2-8354.5"
+ attribute \src "ls180.v:8345.2-8350.5"
switch \main_sdphy_dataw_crcr_reset
- attribute \src "ls180.v:8349.6-8349.33"
+ attribute \src "ls180.v:8345.6-8345.33"
case 1'1
assign $0\main_sdphy_dataw_crcr_run[0:0] 1'0
assign $0\main_sdphy_dataw_crcr_converter_demux[2:0] 3'000
assign $0\main_sdphy_dataw_crcr_buf_source_valid[0:0] 1'0
case
end
- attribute \src "ls180.v:8356.2-8358.5"
+ attribute \src "ls180.v:8352.2-8354.5"
switch \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce
- attribute \src "ls180.v:8356.6-8356.63"
+ attribute \src "ls180.v:8352.6-8352.63"
case 1'1
assign $0\main_sdphy_dataw_crcr_reset[0:0] \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value
case
end
- attribute \src "ls180.v:8360.2-8362.5"
+ attribute \src "ls180.v:8356.2-8358.5"
switch \main_sdphy_dataw_count_sdphy_fsm_next_value_ce
- attribute \src "ls180.v:8360.6-8360.52"
+ attribute \src "ls180.v:8356.6-8356.52"
case 1'1
assign $0\main_sdphy_dataw_count[7:0] \main_sdphy_dataw_count_sdphy_fsm_next_value
case
end
- attribute \src "ls180.v:8363.2-8365.5"
+ attribute \src "ls180.v:8359.2-8361.5"
switch \main_sdphy_datar_datar_pads_in_valid
- attribute \src "ls180.v:8363.6-8363.42"
+ attribute \src "ls180.v:8359.6-8359.42"
case 1'1
- assign $0\main_sdphy_datar_datar_run[0:0] $or$ls180.v:8364$2617_Y
+ assign $0\main_sdphy_datar_datar_run[0:0] $or$ls180.v:8360$2617_Y
case
end
- attribute \src "ls180.v:8366.2-8368.5"
+ attribute \src "ls180.v:8362.2-8364.5"
switch \main_sdphy_datar_datar_converter_source_ready
- attribute \src "ls180.v:8366.6-8366.51"
+ attribute \src "ls180.v:8362.6-8362.51"
case 1'1
assign $0\main_sdphy_datar_datar_converter_strobe_all[0:0] 1'0
case
end
- attribute \src "ls180.v:8369.2-8376.5"
+ attribute \src "ls180.v:8365.2-8372.5"
switch \main_sdphy_datar_datar_converter_load_part
- attribute \src "ls180.v:8369.6-8369.48"
+ attribute \src "ls180.v:8365.6-8365.48"
case 1'1
- attribute \src "ls180.v:8370.3-8375.6"
- switch $or$ls180.v:8370$2619_Y
- attribute \src "ls180.v:8370.7-8370.102"
+ attribute \src "ls180.v:8366.3-8371.6"
+ switch $or$ls180.v:8366$2619_Y
+ attribute \src "ls180.v:8366.7-8366.102"
case 1'1
assign $0\main_sdphy_datar_datar_converter_demux[0:0] 1'0
assign $0\main_sdphy_datar_datar_converter_strobe_all[0:0] 1'1
- attribute \src "ls180.v:8373.7-8373.11"
+ attribute \src "ls180.v:8369.7-8369.11"
case
- assign $0\main_sdphy_datar_datar_converter_demux[0:0] $add$ls180.v:8374$2620_Y
+ assign $0\main_sdphy_datar_datar_converter_demux[0:0] $add$ls180.v:8370$2620_Y
end
case
end
- attribute \src "ls180.v:8377.2-8390.5"
- switch $and$ls180.v:8377$2621_Y
- attribute \src "ls180.v:8377.6-8377.101"
+ attribute \src "ls180.v:8373.2-8386.5"
+ switch $and$ls180.v:8373$2621_Y
+ attribute \src "ls180.v:8373.6-8373.101"
case 1'1
- attribute \src "ls180.v:8378.3-8384.6"
- switch $and$ls180.v:8378$2622_Y
- attribute \src "ls180.v:8378.7-8378.98"
+ attribute \src "ls180.v:8374.3-8380.6"
+ switch $and$ls180.v:8374$2622_Y
+ attribute \src "ls180.v:8374.7-8374.98"
case 1'1
assign $0\main_sdphy_datar_datar_converter_source_first[0:0] \main_sdphy_datar_datar_converter_sink_first
assign $0\main_sdphy_datar_datar_converter_source_last[0:0] \main_sdphy_datar_datar_converter_sink_last
- attribute \src "ls180.v:8381.7-8381.11"
+ attribute \src "ls180.v:8377.7-8377.11"
case
assign $0\main_sdphy_datar_datar_converter_source_first[0:0] 1'0
assign $0\main_sdphy_datar_datar_converter_source_last[0:0] 1'0
end
- attribute \src "ls180.v:8385.6-8385.10"
+ attribute \src "ls180.v:8381.6-8381.10"
case
- attribute \src "ls180.v:8386.3-8389.6"
- switch $and$ls180.v:8386$2623_Y
- attribute \src "ls180.v:8386.7-8386.98"
+ attribute \src "ls180.v:8382.3-8385.6"
+ switch $and$ls180.v:8382$2623_Y
+ attribute \src "ls180.v:8382.7-8382.98"
case 1'1
- assign $0\main_sdphy_datar_datar_converter_source_first[0:0] $or$ls180.v:8387$2624_Y
- assign $0\main_sdphy_datar_datar_converter_source_last[0:0] $or$ls180.v:8388$2625_Y
+ assign $0\main_sdphy_datar_datar_converter_source_first[0:0] $or$ls180.v:8383$2624_Y
+ assign $0\main_sdphy_datar_datar_converter_source_last[0:0] $or$ls180.v:8384$2625_Y
case
end
end
- attribute \src "ls180.v:8391.2-8400.5"
+ attribute \src "ls180.v:8387.2-8396.5"
switch \main_sdphy_datar_datar_converter_load_part
- attribute \src "ls180.v:8391.6-8391.48"
+ attribute \src "ls180.v:8387.6-8387.48"
case 1'1
- attribute \src "ls180.v:8392.3-8399.10"
+ attribute \src "ls180.v:8388.3-8395.10"
switch \main_sdphy_datar_datar_converter_demux
attribute \src "ls180.v:0.0-0.0"
case 1'0
end
case
end
- attribute \src "ls180.v:8401.2-8403.5"
+ attribute \src "ls180.v:8397.2-8399.5"
switch \main_sdphy_datar_datar_converter_load_part
- attribute \src "ls180.v:8401.6-8401.48"
+ attribute \src "ls180.v:8397.6-8397.48"
case 1'1
- assign $0\main_sdphy_datar_datar_converter_source_payload_valid_token_count[1:0] $add$ls180.v:8402$2626_Y
+ assign $0\main_sdphy_datar_datar_converter_source_payload_valid_token_count[1:0] $add$ls180.v:8398$2626_Y
case
end
- attribute \src "ls180.v:8404.2-8409.5"
- switch $or$ls180.v:8404$2628_Y
- attribute \src "ls180.v:8404.6-8404.92"
+ attribute \src "ls180.v:8400.2-8405.5"
+ switch $or$ls180.v:8400$2628_Y
+ attribute \src "ls180.v:8400.6-8400.92"
case 1'1
assign $0\main_sdphy_datar_datar_buf_source_valid[0:0] \main_sdphy_datar_datar_buf_sink_valid
assign $0\main_sdphy_datar_datar_buf_source_first[0:0] \main_sdphy_datar_datar_buf_sink_first
assign $0\main_sdphy_datar_datar_buf_source_payload_data[7:0] \main_sdphy_datar_datar_buf_sink_payload_data
case
end
- attribute \src "ls180.v:8410.2-8415.5"
+ attribute \src "ls180.v:8406.2-8411.5"
switch \main_sdphy_datar_datar_reset
- attribute \src "ls180.v:8410.6-8410.34"
+ attribute \src "ls180.v:8406.6-8406.34"
case 1'1
assign $0\main_sdphy_datar_datar_run[0:0] 1'0
assign $0\main_sdphy_datar_datar_converter_demux[0:0] 1'0
assign $0\main_sdphy_datar_datar_buf_source_valid[0:0] 1'0
case
end
- attribute \src "ls180.v:8417.2-8419.5"
+ attribute \src "ls180.v:8413.2-8415.5"
switch \main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0
- attribute \src "ls180.v:8417.6-8417.60"
+ attribute \src "ls180.v:8413.6-8413.60"
case 1'1
assign $0\main_sdphy_datar_count[9:0] \main_sdphy_datar_count_sdphy_sdphydatar_next_value0
case
end
- attribute \src "ls180.v:8420.2-8422.5"
+ attribute \src "ls180.v:8416.2-8418.5"
switch \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1
- attribute \src "ls180.v:8420.6-8420.62"
+ attribute \src "ls180.v:8416.6-8416.62"
case 1'1
assign $0\main_sdphy_datar_timeout[31:0] \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1
case
end
- attribute \src "ls180.v:8423.2-8425.5"
+ attribute \src "ls180.v:8419.2-8421.5"
switch \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2
- attribute \src "ls180.v:8423.6-8423.66"
+ attribute \src "ls180.v:8419.6-8419.66"
case 1'1
assign $0\main_sdphy_datar_datar_reset[0:0] \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2
case
end
- attribute \src "ls180.v:8426.2-8432.5"
+ attribute \src "ls180.v:8422.2-8428.5"
switch \main_sdcore_crc7_inserter_clr
- attribute \src "ls180.v:8426.6-8426.35"
+ attribute \src "ls180.v:8422.6-8422.35"
case 1'1
assign $0\main_sdcore_crc7_inserter_crcreg0[6:0] 7'0000000
- attribute \src "ls180.v:8428.6-8428.10"
+ attribute \src "ls180.v:8424.6-8424.10"
case
- attribute \src "ls180.v:8429.3-8431.6"
+ attribute \src "ls180.v:8425.3-8427.6"
switch \main_sdcore_crc7_inserter_enable
- attribute \src "ls180.v:8429.7-8429.39"
+ attribute \src "ls180.v:8425.7-8425.39"
case 1'1
assign $0\main_sdcore_crc7_inserter_crcreg0[6:0] \main_sdcore_crc7_inserter_crcreg40
case
end
end
- attribute \src "ls180.v:8433.2-8439.5"
+ attribute \src "ls180.v:8429.2-8435.5"
switch \main_sdcore_crc16_inserter_crc0_clr
- attribute \src "ls180.v:8433.6-8433.41"
+ attribute \src "ls180.v:8429.6-8429.41"
case 1'1
assign $0\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] 16'0000000000000000
- attribute \src "ls180.v:8435.6-8435.10"
+ attribute \src "ls180.v:8431.6-8431.10"
case
- attribute \src "ls180.v:8436.3-8438.6"
+ attribute \src "ls180.v:8432.3-8434.6"
switch \main_sdcore_crc16_inserter_crc0_enable
- attribute \src "ls180.v:8436.7-8436.45"
+ attribute \src "ls180.v:8432.7-8432.45"
case 1'1
assign $0\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] \main_sdcore_crc16_inserter_crc0_crcreg2
case
end
end
- attribute \src "ls180.v:8440.2-8446.5"
+ attribute \src "ls180.v:8436.2-8442.5"
switch \main_sdcore_crc16_inserter_crc1_clr
- attribute \src "ls180.v:8440.6-8440.41"
+ attribute \src "ls180.v:8436.6-8436.41"
case 1'1
assign $0\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] 16'0000000000000000
- attribute \src "ls180.v:8442.6-8442.10"
+ attribute \src "ls180.v:8438.6-8438.10"
case
- attribute \src "ls180.v:8443.3-8445.6"
+ attribute \src "ls180.v:8439.3-8441.6"
switch \main_sdcore_crc16_inserter_crc1_enable
- attribute \src "ls180.v:8443.7-8443.45"
+ attribute \src "ls180.v:8439.7-8439.45"
case 1'1
assign $0\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] \main_sdcore_crc16_inserter_crc1_crcreg2
case
end
end
- attribute \src "ls180.v:8447.2-8453.5"
+ attribute \src "ls180.v:8443.2-8449.5"
switch \main_sdcore_crc16_inserter_crc2_clr
- attribute \src "ls180.v:8447.6-8447.41"
+ attribute \src "ls180.v:8443.6-8443.41"
case 1'1
assign $0\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] 16'0000000000000000
- attribute \src "ls180.v:8449.6-8449.10"
+ attribute \src "ls180.v:8445.6-8445.10"
case
- attribute \src "ls180.v:8450.3-8452.6"
+ attribute \src "ls180.v:8446.3-8448.6"
switch \main_sdcore_crc16_inserter_crc2_enable
- attribute \src "ls180.v:8450.7-8450.45"
+ attribute \src "ls180.v:8446.7-8446.45"
case 1'1
assign $0\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] \main_sdcore_crc16_inserter_crc2_crcreg2
case
end
end
- attribute \src "ls180.v:8454.2-8460.5"
+ attribute \src "ls180.v:8450.2-8456.5"
switch \main_sdcore_crc16_inserter_crc3_clr
- attribute \src "ls180.v:8454.6-8454.41"
+ attribute \src "ls180.v:8450.6-8450.41"
case 1'1
assign $0\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] 16'0000000000000000
- attribute \src "ls180.v:8456.6-8456.10"
+ attribute \src "ls180.v:8452.6-8452.10"
case
- attribute \src "ls180.v:8457.3-8459.6"
+ attribute \src "ls180.v:8453.3-8455.6"
switch \main_sdcore_crc16_inserter_crc3_enable
- attribute \src "ls180.v:8457.7-8457.45"
+ attribute \src "ls180.v:8453.7-8453.45"
case 1'1
assign $0\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] \main_sdcore_crc16_inserter_crc3_crcreg2
case
end
end
- attribute \src "ls180.v:8462.2-8464.5"
+ attribute \src "ls180.v:8458.2-8460.5"
switch \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0
- attribute \src "ls180.v:8462.6-8462.82"
+ attribute \src "ls180.v:8458.6-8458.82"
case 1'1
assign $0\main_sdcore_crc16_inserter_crctmp0[15:0] \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0
case
end
- attribute \src "ls180.v:8465.2-8467.5"
+ attribute \src "ls180.v:8461.2-8463.5"
switch \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1
- attribute \src "ls180.v:8465.6-8465.82"
+ attribute \src "ls180.v:8461.6-8461.82"
case 1'1
assign $0\main_sdcore_crc16_inserter_crctmp1[15:0] \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1
case
end
- attribute \src "ls180.v:8468.2-8470.5"
+ attribute \src "ls180.v:8464.2-8466.5"
switch \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2
- attribute \src "ls180.v:8468.6-8468.82"
+ attribute \src "ls180.v:8464.6-8464.82"
case 1'1
assign $0\main_sdcore_crc16_inserter_crctmp2[15:0] \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2
case
end
- attribute \src "ls180.v:8471.2-8473.5"
+ attribute \src "ls180.v:8467.2-8469.5"
switch \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3
- attribute \src "ls180.v:8471.6-8471.82"
+ attribute \src "ls180.v:8467.6-8467.82"
case 1'1
assign $0\main_sdcore_crc16_inserter_crctmp3[15:0] \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3
case
end
- attribute \src "ls180.v:8474.2-8476.5"
+ attribute \src "ls180.v:8470.2-8472.5"
switch \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4
- attribute \src "ls180.v:8474.6-8474.78"
+ attribute \src "ls180.v:8470.6-8470.78"
case 1'1
assign $0\main_sdcore_crc16_inserter_cnt[2:0] \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4
case
end
- attribute \src "ls180.v:8477.2-8479.5"
- switch $and$ls180.v:8477$2629_Y
- attribute \src "ls180.v:8477.6-8477.83"
+ attribute \src "ls180.v:8473.2-8475.5"
+ switch $and$ls180.v:8473$2629_Y
+ attribute \src "ls180.v:8473.6-8473.83"
case 1'1
assign $0\main_sdcore_crc16_checker_crctmp0[15:0] \main_sdcore_crc16_checker_crc0_crc
case
end
- attribute \src "ls180.v:8480.2-8482.5"
- switch $and$ls180.v:8480$2630_Y
- attribute \src "ls180.v:8480.6-8480.83"
+ attribute \src "ls180.v:8476.2-8478.5"
+ switch $and$ls180.v:8476$2630_Y
+ attribute \src "ls180.v:8476.6-8476.83"
case 1'1
assign $0\main_sdcore_crc16_checker_crctmp1[15:0] \main_sdcore_crc16_checker_crc1_crc
case
end
- attribute \src "ls180.v:8483.2-8485.5"
- switch $and$ls180.v:8483$2631_Y
- attribute \src "ls180.v:8483.6-8483.83"
+ attribute \src "ls180.v:8479.2-8481.5"
+ switch $and$ls180.v:8479$2631_Y
+ attribute \src "ls180.v:8479.6-8479.83"
case 1'1
assign $0\main_sdcore_crc16_checker_crctmp2[15:0] \main_sdcore_crc16_checker_crc2_crc
case
end
- attribute \src "ls180.v:8486.2-8488.5"
- switch $and$ls180.v:8486$2632_Y
- attribute \src "ls180.v:8486.6-8486.83"
+ attribute \src "ls180.v:8482.2-8484.5"
+ switch $and$ls180.v:8482$2632_Y
+ attribute \src "ls180.v:8482.6-8482.83"
case 1'1
assign $0\main_sdcore_crc16_checker_crctmp3[15:0] \main_sdcore_crc16_checker_crc3_crc
case
end
- attribute \src "ls180.v:8489.2-8493.5"
- switch $and$ls180.v:8489$2633_Y
- attribute \src "ls180.v:8489.6-8489.83"
+ attribute \src "ls180.v:8485.2-8489.5"
+ switch $and$ls180.v:8485$2633_Y
+ attribute \src "ls180.v:8485.6-8485.83"
case 1'1
assign $0\main_sdcore_crc16_checker_fifo0[15:0] { \main_sdcore_crc16_checker_fifo0 [13:0] \main_sdcore_crc16_checker_sink_payload_data [7] \main_sdcore_crc16_checker_sink_payload_data [3] }
assign $0\main_sdcore_crc16_checker_val[7:0] [7] \main_sdcore_crc16_checker_fifo0 [13]
assign $0\main_sdcore_crc16_checker_val[7:0] [3] \main_sdcore_crc16_checker_fifo0 [12]
case
end
- attribute \src "ls180.v:8494.2-8498.5"
- switch $and$ls180.v:8494$2634_Y
- attribute \src "ls180.v:8494.6-8494.83"
+ attribute \src "ls180.v:8490.2-8494.5"
+ switch $and$ls180.v:8490$2634_Y
+ attribute \src "ls180.v:8490.6-8490.83"
case 1'1
assign $0\main_sdcore_crc16_checker_fifo1[15:0] { \main_sdcore_crc16_checker_fifo1 [13:0] \main_sdcore_crc16_checker_sink_payload_data [6] \main_sdcore_crc16_checker_sink_payload_data [2] }
assign $0\main_sdcore_crc16_checker_val[7:0] [6] \main_sdcore_crc16_checker_fifo1 [13]
assign $0\main_sdcore_crc16_checker_val[7:0] [2] \main_sdcore_crc16_checker_fifo1 [12]
case
end
- attribute \src "ls180.v:8499.2-8503.5"
- switch $and$ls180.v:8499$2635_Y
- attribute \src "ls180.v:8499.6-8499.83"
+ attribute \src "ls180.v:8495.2-8499.5"
+ switch $and$ls180.v:8495$2635_Y
+ attribute \src "ls180.v:8495.6-8495.83"
case 1'1
assign $0\main_sdcore_crc16_checker_fifo2[15:0] { \main_sdcore_crc16_checker_fifo2 [13:0] \main_sdcore_crc16_checker_sink_payload_data [5] \main_sdcore_crc16_checker_sink_payload_data [1] }
assign $0\main_sdcore_crc16_checker_val[7:0] [5] \main_sdcore_crc16_checker_fifo2 [13]
assign $0\main_sdcore_crc16_checker_val[7:0] [1] \main_sdcore_crc16_checker_fifo2 [12]
case
end
- attribute \src "ls180.v:8504.2-8508.5"
- switch $and$ls180.v:8504$2636_Y
- attribute \src "ls180.v:8504.6-8504.83"
+ attribute \src "ls180.v:8500.2-8504.5"
+ switch $and$ls180.v:8500$2636_Y
+ attribute \src "ls180.v:8500.6-8500.83"
case 1'1
assign $0\main_sdcore_crc16_checker_fifo3[15:0] { \main_sdcore_crc16_checker_fifo3 [13:0] \main_sdcore_crc16_checker_sink_payload_data [4] \main_sdcore_crc16_checker_sink_payload_data [0] }
assign $0\main_sdcore_crc16_checker_val[7:0] [4] \main_sdcore_crc16_checker_fifo3 [13]
assign $0\main_sdcore_crc16_checker_val[7:0] [0] \main_sdcore_crc16_checker_fifo3 [12]
case
end
- attribute \src "ls180.v:8509.2-8517.5"
- switch $and$ls180.v:8509$2637_Y
- attribute \src "ls180.v:8509.6-8509.83"
+ attribute \src "ls180.v:8505.2-8513.5"
+ switch $and$ls180.v:8505$2637_Y
+ attribute \src "ls180.v:8505.6-8505.83"
case 1'1
- attribute \src "ls180.v:8510.3-8516.6"
+ attribute \src "ls180.v:8506.3-8512.6"
switch \main_sdcore_crc16_checker_sink_last
- attribute \src "ls180.v:8510.7-8510.42"
+ attribute \src "ls180.v:8506.7-8506.42"
case 1'1
assign $0\main_sdcore_crc16_checker_cnt[3:0] 4'0000
- attribute \src "ls180.v:8512.7-8512.11"
+ attribute \src "ls180.v:8508.7-8508.11"
case
- attribute \src "ls180.v:8513.4-8515.7"
- switch $ne$ls180.v:8513$2638_Y
- attribute \src "ls180.v:8513.8-8513.48"
+ attribute \src "ls180.v:8509.4-8511.7"
+ switch $ne$ls180.v:8509$2638_Y
+ attribute \src "ls180.v:8509.8-8509.48"
case 1'1
- assign $0\main_sdcore_crc16_checker_cnt[3:0] $add$ls180.v:8514$2639_Y
+ assign $0\main_sdcore_crc16_checker_cnt[3:0] $add$ls180.v:8510$2639_Y
case
end
end
case
end
- attribute \src "ls180.v:8518.2-8524.5"
+ attribute \src "ls180.v:8514.2-8520.5"
switch \main_sdcore_crc16_checker_crc0_clr
- attribute \src "ls180.v:8518.6-8518.40"
+ attribute \src "ls180.v:8514.6-8514.40"
case 1'1
assign $0\main_sdcore_crc16_checker_crc0_crcreg0[15:0] 16'0000000000000000
- attribute \src "ls180.v:8520.6-8520.10"
+ attribute \src "ls180.v:8516.6-8516.10"
case
- attribute \src "ls180.v:8521.3-8523.6"
+ attribute \src "ls180.v:8517.3-8519.6"
switch \main_sdcore_crc16_checker_crc0_enable
- attribute \src "ls180.v:8521.7-8521.44"
+ attribute \src "ls180.v:8517.7-8517.44"
case 1'1
assign $0\main_sdcore_crc16_checker_crc0_crcreg0[15:0] \main_sdcore_crc16_checker_crc0_crcreg2
case
end
end
- attribute \src "ls180.v:8525.2-8531.5"
+ attribute \src "ls180.v:8521.2-8527.5"
switch \main_sdcore_crc16_checker_crc1_clr
- attribute \src "ls180.v:8525.6-8525.40"
+ attribute \src "ls180.v:8521.6-8521.40"
case 1'1
assign $0\main_sdcore_crc16_checker_crc1_crcreg0[15:0] 16'0000000000000000
- attribute \src "ls180.v:8527.6-8527.10"
+ attribute \src "ls180.v:8523.6-8523.10"
case
- attribute \src "ls180.v:8528.3-8530.6"
+ attribute \src "ls180.v:8524.3-8526.6"
switch \main_sdcore_crc16_checker_crc1_enable
- attribute \src "ls180.v:8528.7-8528.44"
+ attribute \src "ls180.v:8524.7-8524.44"
case 1'1
assign $0\main_sdcore_crc16_checker_crc1_crcreg0[15:0] \main_sdcore_crc16_checker_crc1_crcreg2
case
end
end
- attribute \src "ls180.v:8532.2-8538.5"
+ attribute \src "ls180.v:8528.2-8534.5"
switch \main_sdcore_crc16_checker_crc2_clr
- attribute \src "ls180.v:8532.6-8532.40"
+ attribute \src "ls180.v:8528.6-8528.40"
case 1'1
assign $0\main_sdcore_crc16_checker_crc2_crcreg0[15:0] 16'0000000000000000
- attribute \src "ls180.v:8534.6-8534.10"
+ attribute \src "ls180.v:8530.6-8530.10"
case
- attribute \src "ls180.v:8535.3-8537.6"
+ attribute \src "ls180.v:8531.3-8533.6"
switch \main_sdcore_crc16_checker_crc2_enable
- attribute \src "ls180.v:8535.7-8535.44"
+ attribute \src "ls180.v:8531.7-8531.44"
case 1'1
assign $0\main_sdcore_crc16_checker_crc2_crcreg0[15:0] \main_sdcore_crc16_checker_crc2_crcreg2
case
end
end
- attribute \src "ls180.v:8539.2-8545.5"
+ attribute \src "ls180.v:8535.2-8541.5"
switch \main_sdcore_crc16_checker_crc3_clr
- attribute \src "ls180.v:8539.6-8539.40"
+ attribute \src "ls180.v:8535.6-8535.40"
case 1'1
assign $0\main_sdcore_crc16_checker_crc3_crcreg0[15:0] 16'0000000000000000
- attribute \src "ls180.v:8541.6-8541.10"
+ attribute \src "ls180.v:8537.6-8537.10"
case
- attribute \src "ls180.v:8542.3-8544.6"
+ attribute \src "ls180.v:8538.3-8540.6"
switch \main_sdcore_crc16_checker_crc3_enable
- attribute \src "ls180.v:8542.7-8542.44"
+ attribute \src "ls180.v:8538.7-8538.44"
case 1'1
assign $0\main_sdcore_crc16_checker_crc3_crcreg0[15:0] \main_sdcore_crc16_checker_crc3_crcreg2
case
end
end
- attribute \src "ls180.v:8547.2-8549.5"
+ attribute \src "ls180.v:8543.2-8545.5"
switch \main_sdcore_cmd_done_sdcore_fsm_next_value_ce0
- attribute \src "ls180.v:8547.6-8547.52"
+ attribute \src "ls180.v:8543.6-8543.52"
case 1'1
assign $0\main_sdcore_cmd_done[0:0] \main_sdcore_cmd_done_sdcore_fsm_next_value0
case
end
- attribute \src "ls180.v:8550.2-8552.5"
+ attribute \src "ls180.v:8546.2-8548.5"
switch \main_sdcore_data_done_sdcore_fsm_next_value_ce1
- attribute \src "ls180.v:8550.6-8550.53"
+ attribute \src "ls180.v:8546.6-8546.53"
case 1'1
assign $0\main_sdcore_data_done[0:0] \main_sdcore_data_done_sdcore_fsm_next_value1
case
end
- attribute \src "ls180.v:8553.2-8555.5"
+ attribute \src "ls180.v:8549.2-8551.5"
switch \main_sdcore_cmd_count_sdcore_fsm_next_value_ce2
- attribute \src "ls180.v:8553.6-8553.53"
+ attribute \src "ls180.v:8549.6-8549.53"
case 1'1
assign $0\main_sdcore_cmd_count[2:0] \main_sdcore_cmd_count_sdcore_fsm_next_value2
case
end
- attribute \src "ls180.v:8556.2-8558.5"
+ attribute \src "ls180.v:8552.2-8554.5"
switch \main_sdcore_data_count_sdcore_fsm_next_value_ce3
- attribute \src "ls180.v:8556.6-8556.54"
+ attribute \src "ls180.v:8552.6-8552.54"
case 1'1
assign $0\main_sdcore_data_count[31:0] \main_sdcore_data_count_sdcore_fsm_next_value3
case
end
- attribute \src "ls180.v:8559.2-8561.5"
+ attribute \src "ls180.v:8555.2-8557.5"
switch \main_sdcore_cmd_error_sdcore_fsm_next_value_ce4
- attribute \src "ls180.v:8559.6-8559.53"
+ attribute \src "ls180.v:8555.6-8555.53"
case 1'1
assign $0\main_sdcore_cmd_error[0:0] \main_sdcore_cmd_error_sdcore_fsm_next_value4
case
end
- attribute \src "ls180.v:8562.2-8564.5"
+ attribute \src "ls180.v:8558.2-8560.5"
switch \main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5
- attribute \src "ls180.v:8562.6-8562.55"
+ attribute \src "ls180.v:8558.6-8558.55"
case 1'1
assign $0\main_sdcore_cmd_timeout[0:0] \main_sdcore_cmd_timeout_sdcore_fsm_next_value5
case
end
- attribute \src "ls180.v:8565.2-8567.5"
+ attribute \src "ls180.v:8561.2-8563.5"
switch \main_sdcore_data_error_sdcore_fsm_next_value_ce6
- attribute \src "ls180.v:8565.6-8565.54"
+ attribute \src "ls180.v:8561.6-8561.54"
case 1'1
assign $0\main_sdcore_data_error[0:0] \main_sdcore_data_error_sdcore_fsm_next_value6
case
end
- attribute \src "ls180.v:8568.2-8570.5"
+ attribute \src "ls180.v:8564.2-8566.5"
switch \main_sdcore_data_timeout_sdcore_fsm_next_value_ce7
- attribute \src "ls180.v:8568.6-8568.56"
+ attribute \src "ls180.v:8564.6-8564.56"
case 1'1
assign $0\main_sdcore_data_timeout[0:0] \main_sdcore_data_timeout_sdcore_fsm_next_value7
case
end
- attribute \src "ls180.v:8571.2-8573.5"
+ attribute \src "ls180.v:8567.2-8569.5"
switch \main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8
- attribute \src "ls180.v:8571.6-8571.63"
+ attribute \src "ls180.v:8567.6-8567.63"
case 1'1
assign $0\main_sdcore_cmd_response_status[127:0] \main_sdcore_cmd_response_status_sdcore_fsm_next_value8
case
end
- attribute \src "ls180.v:8574.2-8576.5"
- switch $and$ls180.v:8574$2642_Y
- attribute \src "ls180.v:8574.6-8574.120"
+ attribute \src "ls180.v:8570.2-8572.5"
+ switch $and$ls180.v:8570$2642_Y
+ attribute \src "ls180.v:8570.6-8570.120"
case 1'1
- assign $0\main_sdblock2mem_fifo_produce[4:0] $add$ls180.v:8575$2643_Y
+ assign $0\main_sdblock2mem_fifo_produce[4:0] $add$ls180.v:8571$2643_Y
case
end
- attribute \src "ls180.v:8577.2-8579.5"
+ attribute \src "ls180.v:8573.2-8575.5"
switch \main_sdblock2mem_fifo_do_read
- attribute \src "ls180.v:8577.6-8577.35"
+ attribute \src "ls180.v:8573.6-8573.35"
case 1'1
- assign $0\main_sdblock2mem_fifo_consume[4:0] $add$ls180.v:8578$2644_Y
+ assign $0\main_sdblock2mem_fifo_consume[4:0] $add$ls180.v:8574$2644_Y
case
end
- attribute \src "ls180.v:8580.2-8588.5"
- switch $and$ls180.v:8580$2647_Y
- attribute \src "ls180.v:8580.6-8580.120"
+ attribute \src "ls180.v:8576.2-8584.5"
+ switch $and$ls180.v:8576$2647_Y
+ attribute \src "ls180.v:8576.6-8576.120"
case 1'1
- attribute \src "ls180.v:8581.3-8583.6"
- switch $not$ls180.v:8581$2648_Y
- attribute \src "ls180.v:8581.7-8581.39"
+ attribute \src "ls180.v:8577.3-8579.6"
+ switch $not$ls180.v:8577$2648_Y
+ attribute \src "ls180.v:8577.7-8577.39"
case 1'1
- assign $0\main_sdblock2mem_fifo_level[5:0] $add$ls180.v:8582$2649_Y
+ assign $0\main_sdblock2mem_fifo_level[5:0] $add$ls180.v:8578$2649_Y
case
end
- attribute \src "ls180.v:8584.6-8584.10"
+ attribute \src "ls180.v:8580.6-8580.10"
case
- attribute \src "ls180.v:8585.3-8587.6"
+ attribute \src "ls180.v:8581.3-8583.6"
switch \main_sdblock2mem_fifo_do_read
- attribute \src "ls180.v:8585.7-8585.36"
+ attribute \src "ls180.v:8581.7-8581.36"
case 1'1
- assign $0\main_sdblock2mem_fifo_level[5:0] $sub$ls180.v:8586$2650_Y
+ assign $0\main_sdblock2mem_fifo_level[5:0] $sub$ls180.v:8582$2650_Y
case
end
end
- attribute \src "ls180.v:8589.2-8591.5"
+ attribute \src "ls180.v:8585.2-8587.5"
switch \main_sdblock2mem_converter_source_ready
- attribute \src "ls180.v:8589.6-8589.45"
+ attribute \src "ls180.v:8585.6-8585.45"
case 1'1
assign $0\main_sdblock2mem_converter_strobe_all[0:0] 1'0
case
end
- attribute \src "ls180.v:8592.2-8599.5"
+ attribute \src "ls180.v:8588.2-8595.5"
switch \main_sdblock2mem_converter_load_part
- attribute \src "ls180.v:8592.6-8592.42"
+ attribute \src "ls180.v:8588.6-8588.42"
case 1'1
- attribute \src "ls180.v:8593.3-8598.6"
- switch $or$ls180.v:8593$2652_Y
- attribute \src "ls180.v:8593.7-8593.90"
+ attribute \src "ls180.v:8589.3-8594.6"
+ switch $or$ls180.v:8589$2652_Y
+ attribute \src "ls180.v:8589.7-8589.90"
case 1'1
assign $0\main_sdblock2mem_converter_demux[1:0] 2'00
assign $0\main_sdblock2mem_converter_strobe_all[0:0] 1'1
- attribute \src "ls180.v:8596.7-8596.11"
+ attribute \src "ls180.v:8592.7-8592.11"
case
- assign $0\main_sdblock2mem_converter_demux[1:0] $add$ls180.v:8597$2653_Y
+ assign $0\main_sdblock2mem_converter_demux[1:0] $add$ls180.v:8593$2653_Y
end
case
end
- attribute \src "ls180.v:8600.2-8613.5"
- switch $and$ls180.v:8600$2654_Y
- attribute \src "ls180.v:8600.6-8600.89"
+ attribute \src "ls180.v:8596.2-8609.5"
+ switch $and$ls180.v:8596$2654_Y
+ attribute \src "ls180.v:8596.6-8596.89"
case 1'1
- attribute \src "ls180.v:8601.3-8607.6"
- switch $and$ls180.v:8601$2655_Y
- attribute \src "ls180.v:8601.7-8601.86"
+ attribute \src "ls180.v:8597.3-8603.6"
+ switch $and$ls180.v:8597$2655_Y
+ attribute \src "ls180.v:8597.7-8597.86"
case 1'1
assign $0\main_sdblock2mem_converter_source_first[0:0] \main_sdblock2mem_converter_sink_first
assign $0\main_sdblock2mem_converter_source_last[0:0] \main_sdblock2mem_converter_sink_last
- attribute \src "ls180.v:8604.7-8604.11"
+ attribute \src "ls180.v:8600.7-8600.11"
case
assign $0\main_sdblock2mem_converter_source_first[0:0] 1'0
assign $0\main_sdblock2mem_converter_source_last[0:0] 1'0
end
- attribute \src "ls180.v:8608.6-8608.10"
+ attribute \src "ls180.v:8604.6-8604.10"
case
- attribute \src "ls180.v:8609.3-8612.6"
- switch $and$ls180.v:8609$2656_Y
- attribute \src "ls180.v:8609.7-8609.86"
+ attribute \src "ls180.v:8605.3-8608.6"
+ switch $and$ls180.v:8605$2656_Y
+ attribute \src "ls180.v:8605.7-8605.86"
case 1'1
- assign $0\main_sdblock2mem_converter_source_first[0:0] $or$ls180.v:8610$2657_Y
- assign $0\main_sdblock2mem_converter_source_last[0:0] $or$ls180.v:8611$2658_Y
+ assign $0\main_sdblock2mem_converter_source_first[0:0] $or$ls180.v:8606$2657_Y
+ assign $0\main_sdblock2mem_converter_source_last[0:0] $or$ls180.v:8607$2658_Y
case
end
end
- attribute \src "ls180.v:8614.2-8629.5"
+ attribute \src "ls180.v:8610.2-8625.5"
switch \main_sdblock2mem_converter_load_part
- attribute \src "ls180.v:8614.6-8614.42"
+ attribute \src "ls180.v:8610.6-8610.42"
case 1'1
- attribute \src "ls180.v:8615.3-8628.10"
+ attribute \src "ls180.v:8611.3-8624.10"
switch \main_sdblock2mem_converter_demux
attribute \src "ls180.v:0.0-0.0"
case 2'00
end
case
end
- attribute \src "ls180.v:8630.2-8632.5"
+ attribute \src "ls180.v:8626.2-8628.5"
switch \main_sdblock2mem_converter_load_part
- attribute \src "ls180.v:8630.6-8630.42"
+ attribute \src "ls180.v:8626.6-8626.42"
case 1'1
- assign $0\main_sdblock2mem_converter_source_payload_valid_token_count[2:0] $add$ls180.v:8631$2659_Y
+ assign $0\main_sdblock2mem_converter_source_payload_valid_token_count[2:0] $add$ls180.v:8627$2659_Y
case
end
- attribute \src "ls180.v:8634.2-8636.5"
+ attribute \src "ls180.v:8630.2-8632.5"
switch \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce
- attribute \src "ls180.v:8634.6-8634.76"
+ attribute \src "ls180.v:8630.6-8630.76"
case 1'1
assign $0\main_sdblock2mem_wishbonedmawriter_offset[31:0] \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value
case
end
- attribute \src "ls180.v:8637.2-8640.5"
+ attribute \src "ls180.v:8633.2-8636.5"
switch \main_sdblock2mem_wishbonedmawriter_reset
- attribute \src "ls180.v:8637.6-8637.46"
+ attribute \src "ls180.v:8633.6-8633.46"
case 1'1
assign $0\main_sdblock2mem_wishbonedmawriter_offset[31:0] 0
assign $0\builder_sdblock2memdma_state[1:0] 2'00
case
end
- attribute \src "ls180.v:8642.2-8644.5"
+ attribute \src "ls180.v:8638.2-8640.5"
switch \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce
- attribute \src "ls180.v:8642.6-8642.64"
+ attribute \src "ls180.v:8638.6-8638.64"
case 1'1
assign $0\main_sdmem2block_dma_data[31:0] \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value
case
end
- attribute \src "ls180.v:8646.2-8648.5"
+ attribute \src "ls180.v:8642.2-8644.5"
switch \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce
- attribute \src "ls180.v:8646.6-8646.76"
+ attribute \src "ls180.v:8642.6-8642.76"
case 1'1
assign $0\main_sdmem2block_dma_offset[31:0] \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value
case
end
- attribute \src "ls180.v:8649.2-8652.5"
+ attribute \src "ls180.v:8645.2-8648.5"
switch \main_sdmem2block_dma_reset
- attribute \src "ls180.v:8649.6-8649.32"
+ attribute \src "ls180.v:8645.6-8645.32"
case 1'1
assign $0\main_sdmem2block_dma_offset[31:0] 0
assign $0\builder_sdmem2blockdma_resetinserter_state[1:0] 2'00
case
end
- attribute \src "ls180.v:8653.2-8659.5"
- switch $and$ls180.v:8653$2660_Y
- attribute \src "ls180.v:8653.6-8653.89"
+ attribute \src "ls180.v:8649.2-8655.5"
+ switch $and$ls180.v:8649$2660_Y
+ attribute \src "ls180.v:8649.6-8649.89"
case 1'1
- attribute \src "ls180.v:8654.3-8658.6"
+ attribute \src "ls180.v:8650.3-8654.6"
switch \main_sdmem2block_converter_last
- attribute \src "ls180.v:8654.7-8654.38"
+ attribute \src "ls180.v:8650.7-8650.38"
case 1'1
assign $0\main_sdmem2block_converter_mux[1:0] 2'00
- attribute \src "ls180.v:8656.7-8656.11"
+ attribute \src "ls180.v:8652.7-8652.11"
case
- assign $0\main_sdmem2block_converter_mux[1:0] $add$ls180.v:8657$2661_Y
+ assign $0\main_sdmem2block_converter_mux[1:0] $add$ls180.v:8653$2661_Y
end
case
end
- attribute \src "ls180.v:8660.2-8662.5"
- switch $and$ls180.v:8660$2664_Y
- attribute \src "ls180.v:8660.6-8660.120"
+ attribute \src "ls180.v:8656.2-8658.5"
+ switch $and$ls180.v:8656$2664_Y
+ attribute \src "ls180.v:8656.6-8656.120"
case 1'1
- assign $0\main_sdmem2block_fifo_produce[4:0] $add$ls180.v:8661$2665_Y
+ assign $0\main_sdmem2block_fifo_produce[4:0] $add$ls180.v:8657$2665_Y
case
end
- attribute \src "ls180.v:8663.2-8665.5"
+ attribute \src "ls180.v:8659.2-8661.5"
switch \main_sdmem2block_fifo_do_read
- attribute \src "ls180.v:8663.6-8663.35"
+ attribute \src "ls180.v:8659.6-8659.35"
case 1'1
- assign $0\main_sdmem2block_fifo_consume[4:0] $add$ls180.v:8664$2666_Y
+ assign $0\main_sdmem2block_fifo_consume[4:0] $add$ls180.v:8660$2666_Y
case
end
- attribute \src "ls180.v:8666.2-8674.5"
- switch $and$ls180.v:8666$2669_Y
- attribute \src "ls180.v:8666.6-8666.120"
+ attribute \src "ls180.v:8662.2-8670.5"
+ switch $and$ls180.v:8662$2669_Y
+ attribute \src "ls180.v:8662.6-8662.120"
case 1'1
- attribute \src "ls180.v:8667.3-8669.6"
- switch $not$ls180.v:8667$2670_Y
- attribute \src "ls180.v:8667.7-8667.39"
+ attribute \src "ls180.v:8663.3-8665.6"
+ switch $not$ls180.v:8663$2670_Y
+ attribute \src "ls180.v:8663.7-8663.39"
case 1'1
- assign $0\main_sdmem2block_fifo_level[5:0] $add$ls180.v:8668$2671_Y
+ assign $0\main_sdmem2block_fifo_level[5:0] $add$ls180.v:8664$2671_Y
case
end
- attribute \src "ls180.v:8670.6-8670.10"
+ attribute \src "ls180.v:8666.6-8666.10"
case
- attribute \src "ls180.v:8671.3-8673.6"
+ attribute \src "ls180.v:8667.3-8669.6"
switch \main_sdmem2block_fifo_do_read
- attribute \src "ls180.v:8671.7-8671.36"
+ attribute \src "ls180.v:8667.7-8667.36"
case 1'1
- assign $0\main_sdmem2block_fifo_level[5:0] $sub$ls180.v:8672$2672_Y
+ assign $0\main_sdmem2block_fifo_level[5:0] $sub$ls180.v:8668$2672_Y
case
end
end
- attribute \src "ls180.v:8676.2-8678.5"
+ attribute \src "ls180.v:8672.2-8674.5"
switch \builder_libresocsim_dat_w_next_value_ce0
- attribute \src "ls180.v:8676.6-8676.46"
+ attribute \src "ls180.v:8672.6-8672.46"
case 1'1
assign $0\builder_libresocsim_dat_w[7:0] \builder_libresocsim_dat_w_next_value0
case
end
- attribute \src "ls180.v:8679.2-8681.5"
+ attribute \src "ls180.v:8675.2-8677.5"
switch \builder_libresocsim_adr_next_value_ce1
- attribute \src "ls180.v:8679.6-8679.44"
+ attribute \src "ls180.v:8675.6-8675.44"
case 1'1
assign $0\builder_libresocsim_adr[13:0] \builder_libresocsim_adr_next_value1
case
end
- attribute \src "ls180.v:8682.2-8684.5"
+ attribute \src "ls180.v:8678.2-8680.5"
switch \builder_libresocsim_we_next_value_ce2
- attribute \src "ls180.v:8682.6-8682.43"
+ attribute \src "ls180.v:8678.6-8678.43"
case 1'1
assign $0\builder_libresocsim_we[0:0] \builder_libresocsim_we_next_value2
case
end
- attribute \src "ls180.v:8685.2-8781.9"
+ attribute \src "ls180.v:8681.2-8777.9"
switch \builder_grant
attribute \src "ls180.v:0.0-0.0"
case 3'000
- attribute \src "ls180.v:8687.4-8703.7"
- switch $not$ls180.v:8687$2673_Y
- attribute \src "ls180.v:8687.8-8687.29"
+ attribute \src "ls180.v:8683.4-8699.7"
+ switch $not$ls180.v:8683$2673_Y
+ attribute \src "ls180.v:8683.8-8683.29"
case 1'1
- attribute \src "ls180.v:8688.5-8702.8"
+ attribute \src "ls180.v:8684.5-8698.8"
switch \builder_request [1]
- attribute \src "ls180.v:8688.9-8688.27"
+ attribute \src "ls180.v:8684.9-8684.27"
case 1'1
assign $0\builder_grant[2:0] 3'001
- attribute \src "ls180.v:8690.9-8690.13"
+ attribute \src "ls180.v:8686.9-8686.13"
case
- attribute \src "ls180.v:8691.6-8701.9"
+ attribute \src "ls180.v:8687.6-8697.9"
switch \builder_request [2]
- attribute \src "ls180.v:8691.10-8691.28"
+ attribute \src "ls180.v:8687.10-8687.28"
case 1'1
assign $0\builder_grant[2:0] 3'010
- attribute \src "ls180.v:8693.10-8693.14"
+ attribute \src "ls180.v:8689.10-8689.14"
case
- attribute \src "ls180.v:8694.7-8700.10"
+ attribute \src "ls180.v:8690.7-8696.10"
switch \builder_request [3]
- attribute \src "ls180.v:8694.11-8694.29"
+ attribute \src "ls180.v:8690.11-8690.29"
case 1'1
assign $0\builder_grant[2:0] 3'011
- attribute \src "ls180.v:8696.11-8696.15"
+ attribute \src "ls180.v:8692.11-8692.15"
case
- attribute \src "ls180.v:8697.8-8699.11"
+ attribute \src "ls180.v:8693.8-8695.11"
switch \builder_request [4]
- attribute \src "ls180.v:8697.12-8697.30"
+ attribute \src "ls180.v:8693.12-8693.30"
case 1'1
assign $0\builder_grant[2:0] 3'100
case
end
attribute \src "ls180.v:0.0-0.0"
case 3'001
- attribute \src "ls180.v:8706.4-8722.7"
- switch $not$ls180.v:8706$2674_Y
- attribute \src "ls180.v:8706.8-8706.29"
+ attribute \src "ls180.v:8702.4-8718.7"
+ switch $not$ls180.v:8702$2674_Y
+ attribute \src "ls180.v:8702.8-8702.29"
case 1'1
- attribute \src "ls180.v:8707.5-8721.8"
+ attribute \src "ls180.v:8703.5-8717.8"
switch \builder_request [2]
- attribute \src "ls180.v:8707.9-8707.27"
+ attribute \src "ls180.v:8703.9-8703.27"
case 1'1
assign $0\builder_grant[2:0] 3'010
- attribute \src "ls180.v:8709.9-8709.13"
+ attribute \src "ls180.v:8705.9-8705.13"
case
- attribute \src "ls180.v:8710.6-8720.9"
+ attribute \src "ls180.v:8706.6-8716.9"
switch \builder_request [3]
- attribute \src "ls180.v:8710.10-8710.28"
+ attribute \src "ls180.v:8706.10-8706.28"
case 1'1
assign $0\builder_grant[2:0] 3'011
- attribute \src "ls180.v:8712.10-8712.14"
+ attribute \src "ls180.v:8708.10-8708.14"
case
- attribute \src "ls180.v:8713.7-8719.10"
+ attribute \src "ls180.v:8709.7-8715.10"
switch \builder_request [4]
- attribute \src "ls180.v:8713.11-8713.29"
+ attribute \src "ls180.v:8709.11-8709.29"
case 1'1
assign $0\builder_grant[2:0] 3'100
- attribute \src "ls180.v:8715.11-8715.15"
+ attribute \src "ls180.v:8711.11-8711.15"
case
- attribute \src "ls180.v:8716.8-8718.11"
+ attribute \src "ls180.v:8712.8-8714.11"
switch \builder_request [0]
- attribute \src "ls180.v:8716.12-8716.30"
+ attribute \src "ls180.v:8712.12-8712.30"
case 1'1
assign $0\builder_grant[2:0] 3'000
case
end
attribute \src "ls180.v:0.0-0.0"
case 3'010
- attribute \src "ls180.v:8725.4-8741.7"
- switch $not$ls180.v:8725$2675_Y
- attribute \src "ls180.v:8725.8-8725.29"
+ attribute \src "ls180.v:8721.4-8737.7"
+ switch $not$ls180.v:8721$2675_Y
+ attribute \src "ls180.v:8721.8-8721.29"
case 1'1
- attribute \src "ls180.v:8726.5-8740.8"
+ attribute \src "ls180.v:8722.5-8736.8"
switch \builder_request [3]
- attribute \src "ls180.v:8726.9-8726.27"
+ attribute \src "ls180.v:8722.9-8722.27"
case 1'1
assign $0\builder_grant[2:0] 3'011
- attribute \src "ls180.v:8728.9-8728.13"
+ attribute \src "ls180.v:8724.9-8724.13"
case
- attribute \src "ls180.v:8729.6-8739.9"
+ attribute \src "ls180.v:8725.6-8735.9"
switch \builder_request [4]
- attribute \src "ls180.v:8729.10-8729.28"
+ attribute \src "ls180.v:8725.10-8725.28"
case 1'1
assign $0\builder_grant[2:0] 3'100
- attribute \src "ls180.v:8731.10-8731.14"
+ attribute \src "ls180.v:8727.10-8727.14"
case
- attribute \src "ls180.v:8732.7-8738.10"
+ attribute \src "ls180.v:8728.7-8734.10"
switch \builder_request [0]
- attribute \src "ls180.v:8732.11-8732.29"
+ attribute \src "ls180.v:8728.11-8728.29"
case 1'1
assign $0\builder_grant[2:0] 3'000
- attribute \src "ls180.v:8734.11-8734.15"
+ attribute \src "ls180.v:8730.11-8730.15"
case
- attribute \src "ls180.v:8735.8-8737.11"
+ attribute \src "ls180.v:8731.8-8733.11"
switch \builder_request [1]
- attribute \src "ls180.v:8735.12-8735.30"
+ attribute \src "ls180.v:8731.12-8731.30"
case 1'1
assign $0\builder_grant[2:0] 3'001
case
end
attribute \src "ls180.v:0.0-0.0"
case 3'011
- attribute \src "ls180.v:8744.4-8760.7"
- switch $not$ls180.v:8744$2676_Y
- attribute \src "ls180.v:8744.8-8744.29"
+ attribute \src "ls180.v:8740.4-8756.7"
+ switch $not$ls180.v:8740$2676_Y
+ attribute \src "ls180.v:8740.8-8740.29"
case 1'1
- attribute \src "ls180.v:8745.5-8759.8"
+ attribute \src "ls180.v:8741.5-8755.8"
switch \builder_request [4]
- attribute \src "ls180.v:8745.9-8745.27"
+ attribute \src "ls180.v:8741.9-8741.27"
case 1'1
assign $0\builder_grant[2:0] 3'100
- attribute \src "ls180.v:8747.9-8747.13"
+ attribute \src "ls180.v:8743.9-8743.13"
case
- attribute \src "ls180.v:8748.6-8758.9"
+ attribute \src "ls180.v:8744.6-8754.9"
switch \builder_request [0]
- attribute \src "ls180.v:8748.10-8748.28"
+ attribute \src "ls180.v:8744.10-8744.28"
case 1'1
assign $0\builder_grant[2:0] 3'000
- attribute \src "ls180.v:8750.10-8750.14"
+ attribute \src "ls180.v:8746.10-8746.14"
case
- attribute \src "ls180.v:8751.7-8757.10"
+ attribute \src "ls180.v:8747.7-8753.10"
switch \builder_request [1]
- attribute \src "ls180.v:8751.11-8751.29"
+ attribute \src "ls180.v:8747.11-8747.29"
case 1'1
assign $0\builder_grant[2:0] 3'001
- attribute \src "ls180.v:8753.11-8753.15"
+ attribute \src "ls180.v:8749.11-8749.15"
case
- attribute \src "ls180.v:8754.8-8756.11"
+ attribute \src "ls180.v:8750.8-8752.11"
switch \builder_request [2]
- attribute \src "ls180.v:8754.12-8754.30"
+ attribute \src "ls180.v:8750.12-8750.30"
case 1'1
assign $0\builder_grant[2:0] 3'010
case
end
attribute \src "ls180.v:0.0-0.0"
case 3'100
- attribute \src "ls180.v:8763.4-8779.7"
- switch $not$ls180.v:8763$2677_Y
- attribute \src "ls180.v:8763.8-8763.29"
+ attribute \src "ls180.v:8759.4-8775.7"
+ switch $not$ls180.v:8759$2677_Y
+ attribute \src "ls180.v:8759.8-8759.29"
case 1'1
- attribute \src "ls180.v:8764.5-8778.8"
+ attribute \src "ls180.v:8760.5-8774.8"
switch \builder_request [0]
- attribute \src "ls180.v:8764.9-8764.27"
+ attribute \src "ls180.v:8760.9-8760.27"
case 1'1
assign $0\builder_grant[2:0] 3'000
- attribute \src "ls180.v:8766.9-8766.13"
+ attribute \src "ls180.v:8762.9-8762.13"
case
- attribute \src "ls180.v:8767.6-8777.9"
+ attribute \src "ls180.v:8763.6-8773.9"
switch \builder_request [1]
- attribute \src "ls180.v:8767.10-8767.28"
+ attribute \src "ls180.v:8763.10-8763.28"
case 1'1
assign $0\builder_grant[2:0] 3'001
- attribute \src "ls180.v:8769.10-8769.14"
+ attribute \src "ls180.v:8765.10-8765.14"
case
- attribute \src "ls180.v:8770.7-8776.10"
+ attribute \src "ls180.v:8766.7-8772.10"
switch \builder_request [2]
- attribute \src "ls180.v:8770.11-8770.29"
+ attribute \src "ls180.v:8766.11-8766.29"
case 1'1
assign $0\builder_grant[2:0] 3'010
- attribute \src "ls180.v:8772.11-8772.15"
+ attribute \src "ls180.v:8768.11-8768.15"
case
- attribute \src "ls180.v:8773.8-8775.11"
+ attribute \src "ls180.v:8769.8-8771.11"
switch \builder_request [3]
- attribute \src "ls180.v:8773.12-8773.30"
+ attribute \src "ls180.v:8769.12-8769.30"
case 1'1
assign $0\builder_grant[2:0] 3'011
case
end
case
end
- attribute \src "ls180.v:8783.2-8789.5"
+ attribute \src "ls180.v:8779.2-8785.5"
switch \builder_wait
- attribute \src "ls180.v:8783.6-8783.18"
+ attribute \src "ls180.v:8779.6-8779.18"
case 1'1
- attribute \src "ls180.v:8784.3-8786.6"
- switch $not$ls180.v:8784$2678_Y
- attribute \src "ls180.v:8784.7-8784.22"
+ attribute \src "ls180.v:8780.3-8782.6"
+ switch $not$ls180.v:8780$2678_Y
+ attribute \src "ls180.v:8780.7-8780.22"
case 1'1
- assign $0\builder_count[19:0] $sub$ls180.v:8785$2679_Y
+ assign $0\builder_count[19:0] $sub$ls180.v:8781$2679_Y
case
end
- attribute \src "ls180.v:8787.6-8787.10"
+ attribute \src "ls180.v:8783.6-8783.10"
case
assign $0\builder_count[19:0] 20'11110100001001000000
end
- attribute \src "ls180.v:8791.2-8821.5"
+ attribute \src "ls180.v:8787.2-8817.5"
switch \builder_csrbank0_sel
- attribute \src "ls180.v:8791.6-8791.26"
+ attribute \src "ls180.v:8787.6-8787.26"
case 1'1
- attribute \src "ls180.v:8792.3-8820.10"
+ attribute \src "ls180.v:8788.3-8816.10"
switch \builder_interface0_bank_bus_adr [3:0]
attribute \src "ls180.v:0.0-0.0"
case 4'0000
end
case
end
- attribute \src "ls180.v:8822.2-8824.5"
+ attribute \src "ls180.v:8818.2-8820.5"
switch \builder_csrbank0_reset0_re
- attribute \src "ls180.v:8822.6-8822.32"
+ attribute \src "ls180.v:8818.6-8818.32"
case 1'1
assign $0\main_libresocsim_reset_storage[0:0] \builder_csrbank0_reset0_r
case
end
- attribute \src "ls180.v:8826.2-8828.5"
+ attribute \src "ls180.v:8822.2-8824.5"
switch \builder_csrbank0_scratch3_re
- attribute \src "ls180.v:8826.6-8826.34"
+ attribute \src "ls180.v:8822.6-8822.34"
case 1'1
assign $0\main_libresocsim_scratch_storage[31:0] [31:24] \builder_csrbank0_scratch3_r
case
end
- attribute \src "ls180.v:8829.2-8831.5"
+ attribute \src "ls180.v:8825.2-8827.5"
switch \builder_csrbank0_scratch2_re
- attribute \src "ls180.v:8829.6-8829.34"
+ attribute \src "ls180.v:8825.6-8825.34"
case 1'1
assign $0\main_libresocsim_scratch_storage[31:0] [23:16] \builder_csrbank0_scratch2_r
case
end
- attribute \src "ls180.v:8832.2-8834.5"
+ attribute \src "ls180.v:8828.2-8830.5"
switch \builder_csrbank0_scratch1_re
- attribute \src "ls180.v:8832.6-8832.34"
+ attribute \src "ls180.v:8828.6-8828.34"
case 1'1
assign $0\main_libresocsim_scratch_storage[31:0] [15:8] \builder_csrbank0_scratch1_r
case
end
- attribute \src "ls180.v:8835.2-8837.5"
+ attribute \src "ls180.v:8831.2-8833.5"
switch \builder_csrbank0_scratch0_re
- attribute \src "ls180.v:8835.6-8835.34"
+ attribute \src "ls180.v:8831.6-8831.34"
case 1'1
assign $0\main_libresocsim_scratch_storage[31:0] [7:0] \builder_csrbank0_scratch0_r
case
end
- attribute \src "ls180.v:8840.2-8861.5"
+ attribute \src "ls180.v:8836.2-8857.5"
switch \builder_csrbank1_sel
- attribute \src "ls180.v:8840.6-8840.26"
+ attribute \src "ls180.v:8836.6-8836.26"
case 1'1
- attribute \src "ls180.v:8841.3-8860.10"
+ attribute \src "ls180.v:8837.3-8856.10"
switch \builder_interface1_bank_bus_adr [2:0]
attribute \src "ls180.v:0.0-0.0"
case 3'000
end
case
end
- attribute \src "ls180.v:8862.2-8864.5"
+ attribute \src "ls180.v:8858.2-8860.5"
switch \builder_csrbank1_oe1_re
- attribute \src "ls180.v:8862.6-8862.29"
+ attribute \src "ls180.v:8858.6-8858.29"
case 1'1
assign $0\main_gpio_oe_storage[15:0] [15:8] \builder_csrbank1_oe1_r
case
end
- attribute \src "ls180.v:8865.2-8867.5"
+ attribute \src "ls180.v:8861.2-8863.5"
switch \builder_csrbank1_oe0_re
- attribute \src "ls180.v:8865.6-8865.29"
+ attribute \src "ls180.v:8861.6-8861.29"
case 1'1
assign $0\main_gpio_oe_storage[15:0] [7:0] \builder_csrbank1_oe0_r
case
end
- attribute \src "ls180.v:8869.2-8871.5"
+ attribute \src "ls180.v:8865.2-8867.5"
switch \builder_csrbank1_out1_re
- attribute \src "ls180.v:8869.6-8869.30"
+ attribute \src "ls180.v:8865.6-8865.30"
case 1'1
assign $0\main_gpio_out_storage[15:0] [15:8] \builder_csrbank1_out1_r
case
end
- attribute \src "ls180.v:8872.2-8874.5"
+ attribute \src "ls180.v:8868.2-8870.5"
switch \builder_csrbank1_out0_re
- attribute \src "ls180.v:8872.6-8872.30"
+ attribute \src "ls180.v:8868.6-8868.30"
case 1'1
assign $0\main_gpio_out_storage[15:0] [7:0] \builder_csrbank1_out0_r
case
end
- attribute \src "ls180.v:8877.2-8886.5"
+ attribute \src "ls180.v:8873.2-8882.5"
switch \builder_csrbank2_sel
- attribute \src "ls180.v:8877.6-8877.26"
+ attribute \src "ls180.v:8873.6-8873.26"
case 1'1
- attribute \src "ls180.v:8878.3-8885.10"
+ attribute \src "ls180.v:8874.3-8881.10"
switch \builder_interface2_bank_bus_adr [0]
attribute \src "ls180.v:0.0-0.0"
case 1'0
end
case
end
- attribute \src "ls180.v:8887.2-8889.5"
+ attribute \src "ls180.v:8883.2-8885.5"
switch \builder_csrbank2_w0_re
- attribute \src "ls180.v:8887.6-8887.28"
+ attribute \src "ls180.v:8883.6-8883.28"
case 1'1
assign $0\main_i2c_storage[2:0] \builder_csrbank2_w0_r
case
end
- attribute \src "ls180.v:8892.2-8922.5"
+ attribute \src "ls180.v:8888.2-8918.5"
switch \builder_csrbank3_sel
- attribute \src "ls180.v:8892.6-8892.26"
+ attribute \src "ls180.v:8888.6-8888.26"
case 1'1
- attribute \src "ls180.v:8893.3-8921.10"
+ attribute \src "ls180.v:8889.3-8917.10"
switch \builder_interface3_bank_bus_adr [3:0]
attribute \src "ls180.v:0.0-0.0"
case 4'0000
end
case
end
- attribute \src "ls180.v:8923.2-8925.5"
+ attribute \src "ls180.v:8919.2-8921.5"
switch \builder_csrbank3_enable0_re
- attribute \src "ls180.v:8923.6-8923.33"
+ attribute \src "ls180.v:8919.6-8919.33"
case 1'1
assign $0\main_pwm0_enable_storage[0:0] \builder_csrbank3_enable0_r
case
end
- attribute \src "ls180.v:8927.2-8929.5"
+ attribute \src "ls180.v:8923.2-8925.5"
switch \builder_csrbank3_width3_re
- attribute \src "ls180.v:8927.6-8927.32"
+ attribute \src "ls180.v:8923.6-8923.32"
case 1'1
assign $0\main_pwm0_width_storage[31:0] [31:24] \builder_csrbank3_width3_r
case
end
- attribute \src "ls180.v:8930.2-8932.5"
+ attribute \src "ls180.v:8926.2-8928.5"
switch \builder_csrbank3_width2_re
- attribute \src "ls180.v:8930.6-8930.32"
+ attribute \src "ls180.v:8926.6-8926.32"
case 1'1
assign $0\main_pwm0_width_storage[31:0] [23:16] \builder_csrbank3_width2_r
case
end
- attribute \src "ls180.v:8933.2-8935.5"
+ attribute \src "ls180.v:8929.2-8931.5"
switch \builder_csrbank3_width1_re
- attribute \src "ls180.v:8933.6-8933.32"
+ attribute \src "ls180.v:8929.6-8929.32"
case 1'1
assign $0\main_pwm0_width_storage[31:0] [15:8] \builder_csrbank3_width1_r
case
end
- attribute \src "ls180.v:8936.2-8938.5"
+ attribute \src "ls180.v:8932.2-8934.5"
switch \builder_csrbank3_width0_re
- attribute \src "ls180.v:8936.6-8936.32"
+ attribute \src "ls180.v:8932.6-8932.32"
case 1'1
assign $0\main_pwm0_width_storage[31:0] [7:0] \builder_csrbank3_width0_r
case
end
- attribute \src "ls180.v:8940.2-8942.5"
+ attribute \src "ls180.v:8936.2-8938.5"
switch \builder_csrbank3_period3_re
- attribute \src "ls180.v:8940.6-8940.33"
+ attribute \src "ls180.v:8936.6-8936.33"
case 1'1
assign $0\main_pwm0_period_storage[31:0] [31:24] \builder_csrbank3_period3_r
case
end
- attribute \src "ls180.v:8943.2-8945.5"
+ attribute \src "ls180.v:8939.2-8941.5"
switch \builder_csrbank3_period2_re
- attribute \src "ls180.v:8943.6-8943.33"
+ attribute \src "ls180.v:8939.6-8939.33"
case 1'1
assign $0\main_pwm0_period_storage[31:0] [23:16] \builder_csrbank3_period2_r
case
end
- attribute \src "ls180.v:8946.2-8948.5"
+ attribute \src "ls180.v:8942.2-8944.5"
switch \builder_csrbank3_period1_re
- attribute \src "ls180.v:8946.6-8946.33"
+ attribute \src "ls180.v:8942.6-8942.33"
case 1'1
assign $0\main_pwm0_period_storage[31:0] [15:8] \builder_csrbank3_period1_r
case
end
- attribute \src "ls180.v:8949.2-8951.5"
+ attribute \src "ls180.v:8945.2-8947.5"
switch \builder_csrbank3_period0_re
- attribute \src "ls180.v:8949.6-8949.33"
+ attribute \src "ls180.v:8945.6-8945.33"
case 1'1
assign $0\main_pwm0_period_storage[31:0] [7:0] \builder_csrbank3_period0_r
case
end
- attribute \src "ls180.v:8954.2-8984.5"
+ attribute \src "ls180.v:8950.2-8980.5"
switch \builder_csrbank4_sel
- attribute \src "ls180.v:8954.6-8954.26"
+ attribute \src "ls180.v:8950.6-8950.26"
case 1'1
- attribute \src "ls180.v:8955.3-8983.10"
+ attribute \src "ls180.v:8951.3-8979.10"
switch \builder_interface4_bank_bus_adr [3:0]
attribute \src "ls180.v:0.0-0.0"
case 4'0000
end
case
end
- attribute \src "ls180.v:8985.2-8987.5"
+ attribute \src "ls180.v:8981.2-8983.5"
switch \builder_csrbank4_enable0_re
- attribute \src "ls180.v:8985.6-8985.33"
+ attribute \src "ls180.v:8981.6-8981.33"
case 1'1
assign $0\main_pwm1_enable_storage[0:0] \builder_csrbank4_enable0_r
case
end
- attribute \src "ls180.v:8989.2-8991.5"
+ attribute \src "ls180.v:8985.2-8987.5"
switch \builder_csrbank4_width3_re
- attribute \src "ls180.v:8989.6-8989.32"
+ attribute \src "ls180.v:8985.6-8985.32"
case 1'1
assign $0\main_pwm1_width_storage[31:0] [31:24] \builder_csrbank4_width3_r
case
end
- attribute \src "ls180.v:8992.2-8994.5"
+ attribute \src "ls180.v:8988.2-8990.5"
switch \builder_csrbank4_width2_re
- attribute \src "ls180.v:8992.6-8992.32"
+ attribute \src "ls180.v:8988.6-8988.32"
case 1'1
assign $0\main_pwm1_width_storage[31:0] [23:16] \builder_csrbank4_width2_r
case
end
- attribute \src "ls180.v:8995.2-8997.5"
+ attribute \src "ls180.v:8991.2-8993.5"
switch \builder_csrbank4_width1_re
- attribute \src "ls180.v:8995.6-8995.32"
+ attribute \src "ls180.v:8991.6-8991.32"
case 1'1
assign $0\main_pwm1_width_storage[31:0] [15:8] \builder_csrbank4_width1_r
case
end
- attribute \src "ls180.v:8998.2-9000.5"
+ attribute \src "ls180.v:8994.2-8996.5"
switch \builder_csrbank4_width0_re
- attribute \src "ls180.v:8998.6-8998.32"
+ attribute \src "ls180.v:8994.6-8994.32"
case 1'1
assign $0\main_pwm1_width_storage[31:0] [7:0] \builder_csrbank4_width0_r
case
end
- attribute \src "ls180.v:9002.2-9004.5"
+ attribute \src "ls180.v:8998.2-9000.5"
switch \builder_csrbank4_period3_re
- attribute \src "ls180.v:9002.6-9002.33"
+ attribute \src "ls180.v:8998.6-8998.33"
case 1'1
assign $0\main_pwm1_period_storage[31:0] [31:24] \builder_csrbank4_period3_r
case
end
- attribute \src "ls180.v:9005.2-9007.5"
+ attribute \src "ls180.v:9001.2-9003.5"
switch \builder_csrbank4_period2_re
- attribute \src "ls180.v:9005.6-9005.33"
+ attribute \src "ls180.v:9001.6-9001.33"
case 1'1
assign $0\main_pwm1_period_storage[31:0] [23:16] \builder_csrbank4_period2_r
case
end
- attribute \src "ls180.v:9008.2-9010.5"
+ attribute \src "ls180.v:9004.2-9006.5"
switch \builder_csrbank4_period1_re
- attribute \src "ls180.v:9008.6-9008.33"
+ attribute \src "ls180.v:9004.6-9004.33"
case 1'1
assign $0\main_pwm1_period_storage[31:0] [15:8] \builder_csrbank4_period1_r
case
end
- attribute \src "ls180.v:9011.2-9013.5"
+ attribute \src "ls180.v:9007.2-9009.5"
switch \builder_csrbank4_period0_re
- attribute \src "ls180.v:9011.6-9011.33"
+ attribute \src "ls180.v:9007.6-9007.33"
case 1'1
assign $0\main_pwm1_period_storage[31:0] [7:0] \builder_csrbank4_period0_r
case
end
- attribute \src "ls180.v:9016.2-9064.5"
+ attribute \src "ls180.v:9012.2-9060.5"
switch \builder_csrbank5_sel
- attribute \src "ls180.v:9016.6-9016.26"
+ attribute \src "ls180.v:9012.6-9012.26"
case 1'1
- attribute \src "ls180.v:9017.3-9063.10"
+ attribute \src "ls180.v:9013.3-9059.10"
switch \builder_interface5_bank_bus_adr [3:0]
attribute \src "ls180.v:0.0-0.0"
case 4'0000
end
case
end
- attribute \src "ls180.v:9065.2-9067.5"
+ attribute \src "ls180.v:9061.2-9063.5"
switch \builder_csrbank5_dma_base7_re
- attribute \src "ls180.v:9065.6-9065.35"
+ attribute \src "ls180.v:9061.6-9061.35"
case 1'1
assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [63:56] \builder_csrbank5_dma_base7_r
case
end
- attribute \src "ls180.v:9068.2-9070.5"
+ attribute \src "ls180.v:9064.2-9066.5"
switch \builder_csrbank5_dma_base6_re
- attribute \src "ls180.v:9068.6-9068.35"
+ attribute \src "ls180.v:9064.6-9064.35"
case 1'1
assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [55:48] \builder_csrbank5_dma_base6_r
case
end
- attribute \src "ls180.v:9071.2-9073.5"
+ attribute \src "ls180.v:9067.2-9069.5"
switch \builder_csrbank5_dma_base5_re
- attribute \src "ls180.v:9071.6-9071.35"
+ attribute \src "ls180.v:9067.6-9067.35"
case 1'1
assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [47:40] \builder_csrbank5_dma_base5_r
case
end
- attribute \src "ls180.v:9074.2-9076.5"
+ attribute \src "ls180.v:9070.2-9072.5"
switch \builder_csrbank5_dma_base4_re
- attribute \src "ls180.v:9074.6-9074.35"
+ attribute \src "ls180.v:9070.6-9070.35"
case 1'1
assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [39:32] \builder_csrbank5_dma_base4_r
case
end
- attribute \src "ls180.v:9077.2-9079.5"
+ attribute \src "ls180.v:9073.2-9075.5"
switch \builder_csrbank5_dma_base3_re
- attribute \src "ls180.v:9077.6-9077.35"
+ attribute \src "ls180.v:9073.6-9073.35"
case 1'1
assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [31:24] \builder_csrbank5_dma_base3_r
case
end
- attribute \src "ls180.v:9080.2-9082.5"
+ attribute \src "ls180.v:9076.2-9078.5"
switch \builder_csrbank5_dma_base2_re
- attribute \src "ls180.v:9080.6-9080.35"
+ attribute \src "ls180.v:9076.6-9076.35"
case 1'1
assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [23:16] \builder_csrbank5_dma_base2_r
case
end
- attribute \src "ls180.v:9083.2-9085.5"
+ attribute \src "ls180.v:9079.2-9081.5"
switch \builder_csrbank5_dma_base1_re
- attribute \src "ls180.v:9083.6-9083.35"
+ attribute \src "ls180.v:9079.6-9079.35"
case 1'1
assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [15:8] \builder_csrbank5_dma_base1_r
case
end
- attribute \src "ls180.v:9086.2-9088.5"
+ attribute \src "ls180.v:9082.2-9084.5"
switch \builder_csrbank5_dma_base0_re
- attribute \src "ls180.v:9086.6-9086.35"
+ attribute \src "ls180.v:9082.6-9082.35"
case 1'1
assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [7:0] \builder_csrbank5_dma_base0_r
case
end
- attribute \src "ls180.v:9090.2-9092.5"
+ attribute \src "ls180.v:9086.2-9088.5"
switch \builder_csrbank5_dma_length3_re
- attribute \src "ls180.v:9090.6-9090.37"
+ attribute \src "ls180.v:9086.6-9086.37"
case 1'1
assign $0\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] [31:24] \builder_csrbank5_dma_length3_r
case
end
- attribute \src "ls180.v:9093.2-9095.5"
+ attribute \src "ls180.v:9089.2-9091.5"
switch \builder_csrbank5_dma_length2_re
- attribute \src "ls180.v:9093.6-9093.37"
+ attribute \src "ls180.v:9089.6-9089.37"
case 1'1
assign $0\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] [23:16] \builder_csrbank5_dma_length2_r
case
end
- attribute \src "ls180.v:9096.2-9098.5"
+ attribute \src "ls180.v:9092.2-9094.5"
switch \builder_csrbank5_dma_length1_re
- attribute \src "ls180.v:9096.6-9096.37"
+ attribute \src "ls180.v:9092.6-9092.37"
case 1'1
assign $0\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] [15:8] \builder_csrbank5_dma_length1_r
case
end
- attribute \src "ls180.v:9099.2-9101.5"
+ attribute \src "ls180.v:9095.2-9097.5"
switch \builder_csrbank5_dma_length0_re
- attribute \src "ls180.v:9099.6-9099.37"
+ attribute \src "ls180.v:9095.6-9095.37"
case 1'1
assign $0\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] [7:0] \builder_csrbank5_dma_length0_r
case
end
- attribute \src "ls180.v:9103.2-9105.5"
+ attribute \src "ls180.v:9099.2-9101.5"
switch \builder_csrbank5_dma_enable0_re
- attribute \src "ls180.v:9103.6-9103.37"
+ attribute \src "ls180.v:9099.6-9099.37"
case 1'1
assign $0\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0] \builder_csrbank5_dma_enable0_r
case
end
- attribute \src "ls180.v:9107.2-9109.5"
+ attribute \src "ls180.v:9103.2-9105.5"
switch \builder_csrbank5_dma_loop0_re
- attribute \src "ls180.v:9107.6-9107.35"
+ attribute \src "ls180.v:9103.6-9103.35"
case 1'1
assign $0\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0] \builder_csrbank5_dma_loop0_r
case
end
- attribute \src "ls180.v:9112.2-9214.5"
+ attribute \src "ls180.v:9108.2-9210.5"
switch \builder_csrbank6_sel
- attribute \src "ls180.v:9112.6-9112.26"
+ attribute \src "ls180.v:9108.6-9108.26"
case 1'1
- attribute \src "ls180.v:9113.3-9213.10"
+ attribute \src "ls180.v:9109.3-9209.10"
switch \builder_interface6_bank_bus_adr [5:0]
attribute \src "ls180.v:0.0-0.0"
case 6'000000
end
case
end
- attribute \src "ls180.v:9215.2-9217.5"
+ attribute \src "ls180.v:9211.2-9213.5"
switch \builder_csrbank6_cmd_argument3_re
- attribute \src "ls180.v:9215.6-9215.39"
+ attribute \src "ls180.v:9211.6-9211.39"
case 1'1
assign $0\main_sdcore_cmd_argument_storage[31:0] [31:24] \builder_csrbank6_cmd_argument3_r
case
end
- attribute \src "ls180.v:9218.2-9220.5"
+ attribute \src "ls180.v:9214.2-9216.5"
switch \builder_csrbank6_cmd_argument2_re
- attribute \src "ls180.v:9218.6-9218.39"
+ attribute \src "ls180.v:9214.6-9214.39"
case 1'1
assign $0\main_sdcore_cmd_argument_storage[31:0] [23:16] \builder_csrbank6_cmd_argument2_r
case
end
- attribute \src "ls180.v:9221.2-9223.5"
+ attribute \src "ls180.v:9217.2-9219.5"
switch \builder_csrbank6_cmd_argument1_re
- attribute \src "ls180.v:9221.6-9221.39"
+ attribute \src "ls180.v:9217.6-9217.39"
case 1'1
assign $0\main_sdcore_cmd_argument_storage[31:0] [15:8] \builder_csrbank6_cmd_argument1_r
case
end
- attribute \src "ls180.v:9224.2-9226.5"
+ attribute \src "ls180.v:9220.2-9222.5"
switch \builder_csrbank6_cmd_argument0_re
- attribute \src "ls180.v:9224.6-9224.39"
+ attribute \src "ls180.v:9220.6-9220.39"
case 1'1
assign $0\main_sdcore_cmd_argument_storage[31:0] [7:0] \builder_csrbank6_cmd_argument0_r
case
end
- attribute \src "ls180.v:9228.2-9230.5"
+ attribute \src "ls180.v:9224.2-9226.5"
switch \builder_csrbank6_cmd_command3_re
- attribute \src "ls180.v:9228.6-9228.38"
+ attribute \src "ls180.v:9224.6-9224.38"
case 1'1
assign $0\main_sdcore_cmd_command_storage[31:0] [31:24] \builder_csrbank6_cmd_command3_r
case
end
- attribute \src "ls180.v:9231.2-9233.5"
+ attribute \src "ls180.v:9227.2-9229.5"
switch \builder_csrbank6_cmd_command2_re
- attribute \src "ls180.v:9231.6-9231.38"
+ attribute \src "ls180.v:9227.6-9227.38"
case 1'1
assign $0\main_sdcore_cmd_command_storage[31:0] [23:16] \builder_csrbank6_cmd_command2_r
case
end
- attribute \src "ls180.v:9234.2-9236.5"
+ attribute \src "ls180.v:9230.2-9232.5"
switch \builder_csrbank6_cmd_command1_re
- attribute \src "ls180.v:9234.6-9234.38"
+ attribute \src "ls180.v:9230.6-9230.38"
case 1'1
assign $0\main_sdcore_cmd_command_storage[31:0] [15:8] \builder_csrbank6_cmd_command1_r
case
end
- attribute \src "ls180.v:9237.2-9239.5"
+ attribute \src "ls180.v:9233.2-9235.5"
switch \builder_csrbank6_cmd_command0_re
- attribute \src "ls180.v:9237.6-9237.38"
+ attribute \src "ls180.v:9233.6-9233.38"
case 1'1
assign $0\main_sdcore_cmd_command_storage[31:0] [7:0] \builder_csrbank6_cmd_command0_r
case
end
- attribute \src "ls180.v:9241.2-9243.5"
+ attribute \src "ls180.v:9237.2-9239.5"
switch \builder_csrbank6_block_length1_re
- attribute \src "ls180.v:9241.6-9241.39"
+ attribute \src "ls180.v:9237.6-9237.39"
case 1'1
assign $0\main_sdcore_block_length_storage[9:0] [9:8] \builder_csrbank6_block_length1_r
case
end
- attribute \src "ls180.v:9244.2-9246.5"
+ attribute \src "ls180.v:9240.2-9242.5"
switch \builder_csrbank6_block_length0_re
- attribute \src "ls180.v:9244.6-9244.39"
+ attribute \src "ls180.v:9240.6-9240.39"
case 1'1
assign $0\main_sdcore_block_length_storage[9:0] [7:0] \builder_csrbank6_block_length0_r
case
end
- attribute \src "ls180.v:9248.2-9250.5"
+ attribute \src "ls180.v:9244.2-9246.5"
switch \builder_csrbank6_block_count3_re
- attribute \src "ls180.v:9248.6-9248.38"
+ attribute \src "ls180.v:9244.6-9244.38"
case 1'1
assign $0\main_sdcore_block_count_storage[31:0] [31:24] \builder_csrbank6_block_count3_r
case
end
- attribute \src "ls180.v:9251.2-9253.5"
+ attribute \src "ls180.v:9247.2-9249.5"
switch \builder_csrbank6_block_count2_re
- attribute \src "ls180.v:9251.6-9251.38"
+ attribute \src "ls180.v:9247.6-9247.38"
case 1'1
assign $0\main_sdcore_block_count_storage[31:0] [23:16] \builder_csrbank6_block_count2_r
case
end
- attribute \src "ls180.v:9254.2-9256.5"
+ attribute \src "ls180.v:9250.2-9252.5"
switch \builder_csrbank6_block_count1_re
- attribute \src "ls180.v:9254.6-9254.38"
+ attribute \src "ls180.v:9250.6-9250.38"
case 1'1
assign $0\main_sdcore_block_count_storage[31:0] [15:8] \builder_csrbank6_block_count1_r
case
end
- attribute \src "ls180.v:9257.2-9259.5"
+ attribute \src "ls180.v:9253.2-9255.5"
switch \builder_csrbank6_block_count0_re
- attribute \src "ls180.v:9257.6-9257.38"
+ attribute \src "ls180.v:9253.6-9253.38"
case 1'1
assign $0\main_sdcore_block_count_storage[31:0] [7:0] \builder_csrbank6_block_count0_r
case
end
- attribute \src "ls180.v:9262.2-9322.5"
+ attribute \src "ls180.v:9258.2-9318.5"
switch \builder_csrbank7_sel
- attribute \src "ls180.v:9262.6-9262.26"
+ attribute \src "ls180.v:9258.6-9258.26"
case 1'1
- attribute \src "ls180.v:9263.3-9321.10"
+ attribute \src "ls180.v:9259.3-9317.10"
switch \builder_interface7_bank_bus_adr [4:0]
attribute \src "ls180.v:0.0-0.0"
case 5'00000
end
case
end
- attribute \src "ls180.v:9323.2-9325.5"
+ attribute \src "ls180.v:9319.2-9321.5"
switch \builder_csrbank7_dma_base7_re
- attribute \src "ls180.v:9323.6-9323.35"
+ attribute \src "ls180.v:9319.6-9319.35"
case 1'1
assign $0\main_sdmem2block_dma_base_storage[63:0] [63:56] \builder_csrbank7_dma_base7_r
case
end
- attribute \src "ls180.v:9326.2-9328.5"
+ attribute \src "ls180.v:9322.2-9324.5"
switch \builder_csrbank7_dma_base6_re
- attribute \src "ls180.v:9326.6-9326.35"
+ attribute \src "ls180.v:9322.6-9322.35"
case 1'1
assign $0\main_sdmem2block_dma_base_storage[63:0] [55:48] \builder_csrbank7_dma_base6_r
case
end
- attribute \src "ls180.v:9329.2-9331.5"
+ attribute \src "ls180.v:9325.2-9327.5"
switch \builder_csrbank7_dma_base5_re
- attribute \src "ls180.v:9329.6-9329.35"
+ attribute \src "ls180.v:9325.6-9325.35"
case 1'1
assign $0\main_sdmem2block_dma_base_storage[63:0] [47:40] \builder_csrbank7_dma_base5_r
case
end
- attribute \src "ls180.v:9332.2-9334.5"
+ attribute \src "ls180.v:9328.2-9330.5"
switch \builder_csrbank7_dma_base4_re
- attribute \src "ls180.v:9332.6-9332.35"
+ attribute \src "ls180.v:9328.6-9328.35"
case 1'1
assign $0\main_sdmem2block_dma_base_storage[63:0] [39:32] \builder_csrbank7_dma_base4_r
case
end
- attribute \src "ls180.v:9335.2-9337.5"
+ attribute \src "ls180.v:9331.2-9333.5"
switch \builder_csrbank7_dma_base3_re
- attribute \src "ls180.v:9335.6-9335.35"
+ attribute \src "ls180.v:9331.6-9331.35"
case 1'1
assign $0\main_sdmem2block_dma_base_storage[63:0] [31:24] \builder_csrbank7_dma_base3_r
case
end
- attribute \src "ls180.v:9338.2-9340.5"
+ attribute \src "ls180.v:9334.2-9336.5"
switch \builder_csrbank7_dma_base2_re
- attribute \src "ls180.v:9338.6-9338.35"
+ attribute \src "ls180.v:9334.6-9334.35"
case 1'1
assign $0\main_sdmem2block_dma_base_storage[63:0] [23:16] \builder_csrbank7_dma_base2_r
case
end
- attribute \src "ls180.v:9341.2-9343.5"
+ attribute \src "ls180.v:9337.2-9339.5"
switch \builder_csrbank7_dma_base1_re
- attribute \src "ls180.v:9341.6-9341.35"
+ attribute \src "ls180.v:9337.6-9337.35"
case 1'1
assign $0\main_sdmem2block_dma_base_storage[63:0] [15:8] \builder_csrbank7_dma_base1_r
case
end
- attribute \src "ls180.v:9344.2-9346.5"
+ attribute \src "ls180.v:9340.2-9342.5"
switch \builder_csrbank7_dma_base0_re
- attribute \src "ls180.v:9344.6-9344.35"
+ attribute \src "ls180.v:9340.6-9340.35"
case 1'1
assign $0\main_sdmem2block_dma_base_storage[63:0] [7:0] \builder_csrbank7_dma_base0_r
case
end
- attribute \src "ls180.v:9348.2-9350.5"
+ attribute \src "ls180.v:9344.2-9346.5"
switch \builder_csrbank7_dma_length3_re
- attribute \src "ls180.v:9348.6-9348.37"
+ attribute \src "ls180.v:9344.6-9344.37"
case 1'1
assign $0\main_sdmem2block_dma_length_storage[31:0] [31:24] \builder_csrbank7_dma_length3_r
case
end
- attribute \src "ls180.v:9351.2-9353.5"
+ attribute \src "ls180.v:9347.2-9349.5"
switch \builder_csrbank7_dma_length2_re
- attribute \src "ls180.v:9351.6-9351.37"
+ attribute \src "ls180.v:9347.6-9347.37"
case 1'1
assign $0\main_sdmem2block_dma_length_storage[31:0] [23:16] \builder_csrbank7_dma_length2_r
case
end
- attribute \src "ls180.v:9354.2-9356.5"
+ attribute \src "ls180.v:9350.2-9352.5"
switch \builder_csrbank7_dma_length1_re
- attribute \src "ls180.v:9354.6-9354.37"
+ attribute \src "ls180.v:9350.6-9350.37"
case 1'1
assign $0\main_sdmem2block_dma_length_storage[31:0] [15:8] \builder_csrbank7_dma_length1_r
case
end
- attribute \src "ls180.v:9357.2-9359.5"
+ attribute \src "ls180.v:9353.2-9355.5"
switch \builder_csrbank7_dma_length0_re
- attribute \src "ls180.v:9357.6-9357.37"
+ attribute \src "ls180.v:9353.6-9353.37"
case 1'1
assign $0\main_sdmem2block_dma_length_storage[31:0] [7:0] \builder_csrbank7_dma_length0_r
case
end
- attribute \src "ls180.v:9361.2-9363.5"
+ attribute \src "ls180.v:9357.2-9359.5"
switch \builder_csrbank7_dma_enable0_re
- attribute \src "ls180.v:9361.6-9361.37"
+ attribute \src "ls180.v:9357.6-9357.37"
case 1'1
assign $0\main_sdmem2block_dma_enable_storage[0:0] \builder_csrbank7_dma_enable0_r
case
end
- attribute \src "ls180.v:9365.2-9367.5"
+ attribute \src "ls180.v:9361.2-9363.5"
switch \builder_csrbank7_dma_loop0_re
- attribute \src "ls180.v:9365.6-9365.35"
+ attribute \src "ls180.v:9361.6-9361.35"
case 1'1
assign $0\main_sdmem2block_dma_loop_storage[0:0] \builder_csrbank7_dma_loop0_r
case
end
- attribute \src "ls180.v:9370.2-9385.5"
+ attribute \src "ls180.v:9366.2-9381.5"
switch \builder_csrbank8_sel
- attribute \src "ls180.v:9370.6-9370.26"
+ attribute \src "ls180.v:9366.6-9366.26"
case 1'1
- attribute \src "ls180.v:9371.3-9384.10"
+ attribute \src "ls180.v:9367.3-9380.10"
switch \builder_interface8_bank_bus_adr [1:0]
attribute \src "ls180.v:0.0-0.0"
case 2'00
end
case
end
- attribute \src "ls180.v:9386.2-9388.5"
+ attribute \src "ls180.v:9382.2-9384.5"
switch \builder_csrbank8_clocker_divider1_re
- attribute \src "ls180.v:9386.6-9386.42"
+ attribute \src "ls180.v:9382.6-9382.42"
case 1'1
assign $0\main_sdphy_clocker_storage[8:0] [8] \builder_csrbank8_clocker_divider1_r
case
end
- attribute \src "ls180.v:9389.2-9391.5"
+ attribute \src "ls180.v:9385.2-9387.5"
switch \builder_csrbank8_clocker_divider0_re
- attribute \src "ls180.v:9389.6-9389.42"
+ attribute \src "ls180.v:9385.6-9385.42"
case 1'1
assign $0\main_sdphy_clocker_storage[8:0] [7:0] \builder_csrbank8_clocker_divider0_r
case
end
- attribute \src "ls180.v:9394.2-9427.5"
+ attribute \src "ls180.v:9390.2-9423.5"
switch \builder_csrbank9_sel
- attribute \src "ls180.v:9394.6-9394.26"
+ attribute \src "ls180.v:9390.6-9390.26"
case 1'1
- attribute \src "ls180.v:9395.3-9426.10"
+ attribute \src "ls180.v:9391.3-9422.10"
switch \builder_interface9_bank_bus_adr [3:0]
attribute \src "ls180.v:0.0-0.0"
case 4'0000
end
case
end
- attribute \src "ls180.v:9428.2-9430.5"
+ attribute \src "ls180.v:9424.2-9426.5"
switch \builder_csrbank9_dfii_control0_re
- attribute \src "ls180.v:9428.6-9428.39"
+ attribute \src "ls180.v:9424.6-9424.39"
case 1'1
assign $0\main_sdram_storage[3:0] \builder_csrbank9_dfii_control0_r
case
end
- attribute \src "ls180.v:9432.2-9434.5"
+ attribute \src "ls180.v:9428.2-9430.5"
switch \builder_csrbank9_dfii_pi0_command0_re
- attribute \src "ls180.v:9432.6-9432.43"
+ attribute \src "ls180.v:9428.6-9428.43"
case 1'1
assign $0\main_sdram_command_storage[5:0] \builder_csrbank9_dfii_pi0_command0_r
case
end
- attribute \src "ls180.v:9436.2-9438.5"
+ attribute \src "ls180.v:9432.2-9434.5"
switch \builder_csrbank9_dfii_pi0_address1_re
- attribute \src "ls180.v:9436.6-9436.43"
+ attribute \src "ls180.v:9432.6-9432.43"
case 1'1
assign $0\main_sdram_address_storage[12:0] [12:8] \builder_csrbank9_dfii_pi0_address1_r
case
end
- attribute \src "ls180.v:9439.2-9441.5"
+ attribute \src "ls180.v:9435.2-9437.5"
switch \builder_csrbank9_dfii_pi0_address0_re
- attribute \src "ls180.v:9439.6-9439.43"
+ attribute \src "ls180.v:9435.6-9435.43"
case 1'1
assign $0\main_sdram_address_storage[12:0] [7:0] \builder_csrbank9_dfii_pi0_address0_r
case
end
- attribute \src "ls180.v:9443.2-9445.5"
+ attribute \src "ls180.v:9439.2-9441.5"
switch \builder_csrbank9_dfii_pi0_baddress0_re
- attribute \src "ls180.v:9443.6-9443.44"
+ attribute \src "ls180.v:9439.6-9439.44"
case 1'1
assign $0\main_sdram_baddress_storage[1:0] \builder_csrbank9_dfii_pi0_baddress0_r
case
end
- attribute \src "ls180.v:9447.2-9449.5"
+ attribute \src "ls180.v:9443.2-9445.5"
switch \builder_csrbank9_dfii_pi0_wrdata1_re
- attribute \src "ls180.v:9447.6-9447.42"
+ attribute \src "ls180.v:9443.6-9443.42"
case 1'1
assign $0\main_sdram_wrdata_storage[15:0] [15:8] \builder_csrbank9_dfii_pi0_wrdata1_r
case
end
- attribute \src "ls180.v:9450.2-9452.5"
+ attribute \src "ls180.v:9446.2-9448.5"
switch \builder_csrbank9_dfii_pi0_wrdata0_re
- attribute \src "ls180.v:9450.6-9450.42"
+ attribute \src "ls180.v:9446.6-9446.42"
case 1'1
assign $0\main_sdram_wrdata_storage[15:0] [7:0] \builder_csrbank9_dfii_pi0_wrdata0_r
case
end
- attribute \src "ls180.v:9455.2-9479.5"
+ attribute \src "ls180.v:9451.2-9475.5"
switch \builder_csrbank10_sel
- attribute \src "ls180.v:9455.6-9455.27"
+ attribute \src "ls180.v:9451.6-9451.27"
case 1'1
- attribute \src "ls180.v:9456.3-9478.10"
+ attribute \src "ls180.v:9452.3-9474.10"
switch \builder_interface10_bank_bus_adr [2:0]
attribute \src "ls180.v:0.0-0.0"
case 3'000
end
case
end
- attribute \src "ls180.v:9480.2-9482.5"
+ attribute \src "ls180.v:9476.2-9478.5"
switch \builder_csrbank10_control1_re
- attribute \src "ls180.v:9480.6-9480.35"
+ attribute \src "ls180.v:9476.6-9476.35"
case 1'1
assign $0\main_spimaster11_storage[15:0] [15:8] \builder_csrbank10_control1_r
case
end
- attribute \src "ls180.v:9483.2-9485.5"
+ attribute \src "ls180.v:9479.2-9481.5"
switch \builder_csrbank10_control0_re
- attribute \src "ls180.v:9483.6-9483.35"
+ attribute \src "ls180.v:9479.6-9479.35"
case 1'1
assign $0\main_spimaster11_storage[15:0] [7:0] \builder_csrbank10_control0_r
case
end
- attribute \src "ls180.v:9487.2-9489.5"
+ attribute \src "ls180.v:9483.2-9485.5"
switch \builder_csrbank10_mosi0_re
- attribute \src "ls180.v:9487.6-9487.32"
+ attribute \src "ls180.v:9483.6-9483.32"
case 1'1
assign $0\main_spimaster16_storage[7:0] \builder_csrbank10_mosi0_r
case
end
- attribute \src "ls180.v:9491.2-9493.5"
+ attribute \src "ls180.v:9487.2-9489.5"
switch \builder_csrbank10_cs0_re
- attribute \src "ls180.v:9491.6-9491.30"
+ attribute \src "ls180.v:9487.6-9487.30"
case 1'1
assign $0\main_spimaster21_storage[0:0] \builder_csrbank10_cs0_r
case
end
- attribute \src "ls180.v:9495.2-9497.5"
+ attribute \src "ls180.v:9491.2-9493.5"
switch \builder_csrbank10_loopback0_re
- attribute \src "ls180.v:9495.6-9495.36"
+ attribute \src "ls180.v:9491.6-9491.36"
case 1'1
assign $0\main_spimaster23_storage[0:0] \builder_csrbank10_loopback0_r
case
end
- attribute \src "ls180.v:9500.2-9530.5"
+ attribute \src "ls180.v:9496.2-9526.5"
switch \builder_csrbank11_sel
- attribute \src "ls180.v:9500.6-9500.27"
+ attribute \src "ls180.v:9496.6-9496.27"
case 1'1
- attribute \src "ls180.v:9501.3-9529.10"
+ attribute \src "ls180.v:9497.3-9525.10"
switch \builder_interface11_bank_bus_adr [3:0]
attribute \src "ls180.v:0.0-0.0"
case 4'0000
end
case
end
- attribute \src "ls180.v:9531.2-9533.5"
+ attribute \src "ls180.v:9527.2-9529.5"
switch \builder_csrbank11_control1_re
- attribute \src "ls180.v:9531.6-9531.35"
+ attribute \src "ls180.v:9527.6-9527.35"
case 1'1
assign $0\main_spisdcard_control_storage[15:0] [15:8] \builder_csrbank11_control1_r
case
end
- attribute \src "ls180.v:9534.2-9536.5"
+ attribute \src "ls180.v:9530.2-9532.5"
switch \builder_csrbank11_control0_re
- attribute \src "ls180.v:9534.6-9534.35"
+ attribute \src "ls180.v:9530.6-9530.35"
case 1'1
assign $0\main_spisdcard_control_storage[15:0] [7:0] \builder_csrbank11_control0_r
case
end
- attribute \src "ls180.v:9538.2-9540.5"
+ attribute \src "ls180.v:9534.2-9536.5"
switch \builder_csrbank11_mosi0_re
- attribute \src "ls180.v:9538.6-9538.32"
+ attribute \src "ls180.v:9534.6-9534.32"
case 1'1
assign $0\main_spisdcard_mosi_storage[7:0] \builder_csrbank11_mosi0_r
case
end
- attribute \src "ls180.v:9542.2-9544.5"
+ attribute \src "ls180.v:9538.2-9540.5"
switch \builder_csrbank11_cs0_re
- attribute \src "ls180.v:9542.6-9542.30"
+ attribute \src "ls180.v:9538.6-9538.30"
case 1'1
assign $0\main_spisdcard_cs_storage[0:0] \builder_csrbank11_cs0_r
case
end
- attribute \src "ls180.v:9546.2-9548.5"
+ attribute \src "ls180.v:9542.2-9544.5"
switch \builder_csrbank11_loopback0_re
- attribute \src "ls180.v:9546.6-9546.36"
+ attribute \src "ls180.v:9542.6-9542.36"
case 1'1
assign $0\main_spisdcard_loopback_storage[0:0] \builder_csrbank11_loopback0_r
case
end
- attribute \src "ls180.v:9550.2-9552.5"
+ attribute \src "ls180.v:9546.2-9548.5"
switch \builder_csrbank11_clk_divider1_re
- attribute \src "ls180.v:9550.6-9550.39"
+ attribute \src "ls180.v:9546.6-9546.39"
case 1'1
assign $0\main_spimaster1_storage[15:0] [15:8] \builder_csrbank11_clk_divider1_r
case
end
- attribute \src "ls180.v:9553.2-9555.5"
+ attribute \src "ls180.v:9549.2-9551.5"
switch \builder_csrbank11_clk_divider0_re
- attribute \src "ls180.v:9553.6-9553.39"
+ attribute \src "ls180.v:9549.6-9549.39"
case 1'1
assign $0\main_spimaster1_storage[15:0] [7:0] \builder_csrbank11_clk_divider0_r
case
end
- attribute \src "ls180.v:9558.2-9612.5"
+ attribute \src "ls180.v:9554.2-9608.5"
switch \builder_csrbank12_sel
- attribute \src "ls180.v:9558.6-9558.27"
+ attribute \src "ls180.v:9554.6-9554.27"
case 1'1
- attribute \src "ls180.v:9559.3-9611.10"
+ attribute \src "ls180.v:9555.3-9607.10"
switch \builder_interface12_bank_bus_adr [4:0]
attribute \src "ls180.v:0.0-0.0"
case 5'00000
end
case
end
- attribute \src "ls180.v:9613.2-9615.5"
+ attribute \src "ls180.v:9609.2-9611.5"
switch \builder_csrbank12_load3_re
- attribute \src "ls180.v:9613.6-9613.32"
+ attribute \src "ls180.v:9609.6-9609.32"
case 1'1
assign $0\main_libresocsim_load_storage[31:0] [31:24] \builder_csrbank12_load3_r
case
end
- attribute \src "ls180.v:9616.2-9618.5"
+ attribute \src "ls180.v:9612.2-9614.5"
switch \builder_csrbank12_load2_re
- attribute \src "ls180.v:9616.6-9616.32"
+ attribute \src "ls180.v:9612.6-9612.32"
case 1'1
assign $0\main_libresocsim_load_storage[31:0] [23:16] \builder_csrbank12_load2_r
case
end
- attribute \src "ls180.v:9619.2-9621.5"
+ attribute \src "ls180.v:9615.2-9617.5"
switch \builder_csrbank12_load1_re
- attribute \src "ls180.v:9619.6-9619.32"
+ attribute \src "ls180.v:9615.6-9615.32"
case 1'1
assign $0\main_libresocsim_load_storage[31:0] [15:8] \builder_csrbank12_load1_r
case
end
- attribute \src "ls180.v:9622.2-9624.5"
+ attribute \src "ls180.v:9618.2-9620.5"
switch \builder_csrbank12_load0_re
- attribute \src "ls180.v:9622.6-9622.32"
+ attribute \src "ls180.v:9618.6-9618.32"
case 1'1
assign $0\main_libresocsim_load_storage[31:0] [7:0] \builder_csrbank12_load0_r
case
end
- attribute \src "ls180.v:9626.2-9628.5"
+ attribute \src "ls180.v:9622.2-9624.5"
switch \builder_csrbank12_reload3_re
- attribute \src "ls180.v:9626.6-9626.34"
+ attribute \src "ls180.v:9622.6-9622.34"
case 1'1
assign $0\main_libresocsim_reload_storage[31:0] [31:24] \builder_csrbank12_reload3_r
case
end
- attribute \src "ls180.v:9629.2-9631.5"
+ attribute \src "ls180.v:9625.2-9627.5"
switch \builder_csrbank12_reload2_re
- attribute \src "ls180.v:9629.6-9629.34"
+ attribute \src "ls180.v:9625.6-9625.34"
case 1'1
assign $0\main_libresocsim_reload_storage[31:0] [23:16] \builder_csrbank12_reload2_r
case
end
- attribute \src "ls180.v:9632.2-9634.5"
+ attribute \src "ls180.v:9628.2-9630.5"
switch \builder_csrbank12_reload1_re
- attribute \src "ls180.v:9632.6-9632.34"
+ attribute \src "ls180.v:9628.6-9628.34"
case 1'1
assign $0\main_libresocsim_reload_storage[31:0] [15:8] \builder_csrbank12_reload1_r
case
end
- attribute \src "ls180.v:9635.2-9637.5"
+ attribute \src "ls180.v:9631.2-9633.5"
switch \builder_csrbank12_reload0_re
- attribute \src "ls180.v:9635.6-9635.34"
+ attribute \src "ls180.v:9631.6-9631.34"
case 1'1
assign $0\main_libresocsim_reload_storage[31:0] [7:0] \builder_csrbank12_reload0_r
case
end
- attribute \src "ls180.v:9639.2-9641.5"
+ attribute \src "ls180.v:9635.2-9637.5"
switch \builder_csrbank12_en0_re
- attribute \src "ls180.v:9639.6-9639.30"
+ attribute \src "ls180.v:9635.6-9635.30"
case 1'1
assign $0\main_libresocsim_en_storage[0:0] \builder_csrbank12_en0_r
case
end
- attribute \src "ls180.v:9643.2-9645.5"
+ attribute \src "ls180.v:9639.2-9641.5"
switch \builder_csrbank12_update_value0_re
- attribute \src "ls180.v:9643.6-9643.40"
+ attribute \src "ls180.v:9639.6-9639.40"
case 1'1
assign $0\main_libresocsim_update_value_storage[0:0] \builder_csrbank12_update_value0_r
case
end
- attribute \src "ls180.v:9647.2-9649.5"
+ attribute \src "ls180.v:9643.2-9645.5"
switch \builder_csrbank12_ev_enable0_re
- attribute \src "ls180.v:9647.6-9647.37"
+ attribute \src "ls180.v:9643.6-9643.37"
case 1'1
assign $0\main_libresocsim_eventmanager_storage[0:0] \builder_csrbank12_ev_enable0_r
case
end
- attribute \src "ls180.v:9652.2-9679.5"
+ attribute \src "ls180.v:9648.2-9675.5"
switch \builder_csrbank13_sel
- attribute \src "ls180.v:9652.6-9652.27"
+ attribute \src "ls180.v:9648.6-9648.27"
case 1'1
- attribute \src "ls180.v:9653.3-9678.10"
+ attribute \src "ls180.v:9649.3-9674.10"
switch \builder_interface13_bank_bus_adr [2:0]
attribute \src "ls180.v:0.0-0.0"
case 3'000
end
case
end
- attribute \src "ls180.v:9680.2-9682.5"
+ attribute \src "ls180.v:9676.2-9678.5"
switch \builder_csrbank13_ev_enable0_re
- attribute \src "ls180.v:9680.6-9680.37"
+ attribute \src "ls180.v:9676.6-9676.37"
case 1'1
assign $0\main_uart_eventmanager_storage[1:0] \builder_csrbank13_ev_enable0_r
case
end
- attribute \src "ls180.v:9685.2-9700.5"
+ attribute \src "ls180.v:9681.2-9696.5"
switch \builder_csrbank14_sel
- attribute \src "ls180.v:9685.6-9685.27"
+ attribute \src "ls180.v:9681.6-9681.27"
case 1'1
- attribute \src "ls180.v:9686.3-9699.10"
+ attribute \src "ls180.v:9682.3-9695.10"
switch \builder_interface14_bank_bus_adr [1:0]
attribute \src "ls180.v:0.0-0.0"
case 2'00
end
case
end
- attribute \src "ls180.v:9701.2-9703.5"
+ attribute \src "ls180.v:9697.2-9699.5"
switch \builder_csrbank14_tuning_word3_re
- attribute \src "ls180.v:9701.6-9701.39"
+ attribute \src "ls180.v:9697.6-9697.39"
case 1'1
assign $0\main_uart_phy_storage[31:0] [31:24] \builder_csrbank14_tuning_word3_r
case
end
- attribute \src "ls180.v:9704.2-9706.5"
+ attribute \src "ls180.v:9700.2-9702.5"
switch \builder_csrbank14_tuning_word2_re
- attribute \src "ls180.v:9704.6-9704.39"
+ attribute \src "ls180.v:9700.6-9700.39"
case 1'1
assign $0\main_uart_phy_storage[31:0] [23:16] \builder_csrbank14_tuning_word2_r
case
end
- attribute \src "ls180.v:9707.2-9709.5"
+ attribute \src "ls180.v:9703.2-9705.5"
switch \builder_csrbank14_tuning_word1_re
- attribute \src "ls180.v:9707.6-9707.39"
+ attribute \src "ls180.v:9703.6-9703.39"
case 1'1
assign $0\main_uart_phy_storage[31:0] [15:8] \builder_csrbank14_tuning_word1_r
case
end
- attribute \src "ls180.v:9710.2-9712.5"
+ attribute \src "ls180.v:9706.2-9708.5"
switch \builder_csrbank14_tuning_word0_re
- attribute \src "ls180.v:9710.6-9710.39"
+ attribute \src "ls180.v:9706.6-9706.39"
case 1'1
assign $0\main_uart_phy_storage[31:0] [7:0] \builder_csrbank14_tuning_word0_r
case
end
- attribute \src "ls180.v:9714.2-10008.5"
+ attribute \src "ls180.v:9710.2-10004.5"
switch \sys_rst_1
- attribute \src "ls180.v:9714.6-9714.15"
+ attribute \src "ls180.v:9710.6-9710.15"
case 1'1
assign $0\main_libresocsim_reset_storage[0:0] 1'0
assign $0\main_libresocsim_reset_re[0:0] 1'0
assign $0\main_libresocsim_scratch_re[0:0] 1'0
assign $0\main_libresocsim_bus_errors[31:0] 0
assign $0\pwm[1:0] 2'00
- assign $0\uart_tx[0:0] 1'1
- assign $0\spimaster_clk[0:0] 1'0
- assign $0\spimaster_mosi[0:0] 1'0
- assign $0\spimaster_cs_n[0:0] 1'0
assign $0\spisdcard_clk[0:0] 1'0
assign $0\spisdcard_mosi[0:0] 1'0
assign $0\spisdcard_cs_n[0:0] 1'0
+ assign $0\spimaster_clk[0:0] 1'0
+ assign $0\spimaster_mosi[0:0] 1'0
+ assign $0\spimaster_cs_n[0:0] 1'0
+ assign $0\uart_tx[0:0] 1'1
assign $0\main_libresocsim_converter0_counter[0:0] 1'0
assign $0\main_libresocsim_converter1_counter[0:0] 1'0
assign $0\main_libresocsim_converter2_counter[0:0] 1'0
end
sync posedge \sys_clk_1
update \pwm $0\pwm[1:0]
- update \uart_tx $0\uart_tx[0:0]
- update \spimaster_clk $0\spimaster_clk[0:0]
- update \spimaster_mosi $0\spimaster_mosi[0:0]
- update \spimaster_cs_n $0\spimaster_cs_n[0:0]
update \spisdcard_clk $0\spisdcard_clk[0:0]
update \spisdcard_mosi $0\spisdcard_mosi[0:0]
update \spisdcard_cs_n $0\spisdcard_cs_n[0:0]
+ update \spimaster_clk $0\spimaster_clk[0:0]
+ update \spimaster_mosi $0\spimaster_mosi[0:0]
+ update \spimaster_cs_n $0\spimaster_cs_n[0:0]
+ update \uart_tx $0\uart_tx[0:0]
update \main_libresocsim_reset_storage $0\main_libresocsim_reset_storage[0:0]
update \main_libresocsim_reset_re $0\main_libresocsim_reset_re[0:0]
update \main_libresocsim_scratch_storage $0\main_libresocsim_scratch_storage[31:0]
update \builder_multiregimpl16_regs0 $0\builder_multiregimpl16_regs0[0:0]
update \builder_multiregimpl16_regs1 $0\builder_multiregimpl16_regs1[0:0]
end
- attribute \src "ls180.v:745.5-745.43"
- process $proc$ls180.v:745$3033
- assign { } { }
- assign $0\main_sdram_choose_cmd_cmd_ready[0:0] 1'0
- sync always
- update \main_sdram_choose_cmd_cmd_ready $0\main_sdram_choose_cmd_cmd_ready[0:0]
- sync init
- end
- attribute \src "ls180.v:748.5-748.49"
- process $proc$ls180.v:748$3034
+ attribute \src "ls180.v:744.5-744.49"
+ process $proc$ls180.v:744$3034
assign { } { }
assign $1\main_sdram_choose_cmd_cmd_payload_cas[0:0] 1'0
sync always
sync init
update \main_sdram_choose_cmd_cmd_payload_cas $1\main_sdram_choose_cmd_cmd_payload_cas[0:0]
end
- attribute \src "ls180.v:749.5-749.49"
- process $proc$ls180.v:749$3035
+ attribute \src "ls180.v:745.5-745.49"
+ process $proc$ls180.v:745$3035
assign { } { }
assign $1\main_sdram_choose_cmd_cmd_payload_ras[0:0] 1'0
sync always
sync init
update \main_sdram_choose_cmd_cmd_payload_ras $1\main_sdram_choose_cmd_cmd_payload_ras[0:0]
end
- attribute \src "ls180.v:750.5-750.48"
- process $proc$ls180.v:750$3036
+ attribute \src "ls180.v:746.5-746.48"
+ process $proc$ls180.v:746$3036
assign { } { }
assign $1\main_sdram_choose_cmd_cmd_payload_we[0:0] 1'0
sync always
sync init
update \main_sdram_choose_cmd_cmd_payload_we $1\main_sdram_choose_cmd_cmd_payload_we[0:0]
end
- attribute \src "ls180.v:754.11-754.46"
- process $proc$ls180.v:754$3037
+ attribute \src "ls180.v:750.11-750.46"
+ process $proc$ls180.v:750$3037
assign { } { }
assign $1\main_sdram_choose_cmd_valids[3:0] 4'0000
sync always
sync init
update \main_sdram_choose_cmd_valids $1\main_sdram_choose_cmd_valids[3:0]
end
- attribute \src "ls180.v:756.11-756.45"
- process $proc$ls180.v:756$3038
+ attribute \src "ls180.v:752.11-752.45"
+ process $proc$ls180.v:752$3038
assign { } { }
assign $1\main_sdram_choose_cmd_grant[1:0] 2'00
sync always
sync init
update \main_sdram_choose_cmd_grant $1\main_sdram_choose_cmd_grant[1:0]
end
- attribute \src "ls180.v:758.5-758.44"
- process $proc$ls180.v:758$3039
+ attribute \src "ls180.v:754.5-754.44"
+ process $proc$ls180.v:754$3039
assign { } { }
assign $1\main_sdram_choose_req_want_reads[0:0] 1'0
sync always
sync init
update \main_sdram_choose_req_want_reads $1\main_sdram_choose_req_want_reads[0:0]
end
- attribute \src "ls180.v:759.5-759.45"
- process $proc$ls180.v:759$3040
+ attribute \src "ls180.v:755.5-755.45"
+ process $proc$ls180.v:755$3040
assign { } { }
assign $1\main_sdram_choose_req_want_writes[0:0] 1'0
sync always
sync init
update \main_sdram_choose_req_want_writes $1\main_sdram_choose_req_want_writes[0:0]
end
- attribute \src "ls180.v:76.5-76.46"
- process $proc$ls180.v:76$2770
- assign { } { }
- assign $0\main_libresocsim_libresoc_dbus_err[0:0] 1'0
- sync always
- update \main_libresocsim_libresoc_dbus_err $0\main_libresocsim_libresoc_dbus_err[0:0]
- sync init
- end
- attribute \src "ls180.v:761.5-761.48"
- process $proc$ls180.v:761$3041
+ attribute \src "ls180.v:757.5-757.48"
+ process $proc$ls180.v:757$3041
assign { } { }
assign $1\main_sdram_choose_req_want_activates[0:0] 1'0
sync always
sync init
update \main_sdram_choose_req_want_activates $1\main_sdram_choose_req_want_activates[0:0]
end
- attribute \src "ls180.v:763.5-763.43"
- process $proc$ls180.v:763$3042
+ attribute \src "ls180.v:759.5-759.43"
+ process $proc$ls180.v:759$3042
assign { } { }
assign $1\main_sdram_choose_req_cmd_ready[0:0] 1'0
sync always
sync init
update \main_sdram_choose_req_cmd_ready $1\main_sdram_choose_req_cmd_ready[0:0]
end
- attribute \src "ls180.v:766.5-766.49"
- process $proc$ls180.v:766$3043
+ attribute \src "ls180.v:762.5-762.49"
+ process $proc$ls180.v:762$3043
assign { } { }
assign $1\main_sdram_choose_req_cmd_payload_cas[0:0] 1'0
sync always
sync init
update \main_sdram_choose_req_cmd_payload_cas $1\main_sdram_choose_req_cmd_payload_cas[0:0]
end
- attribute \src "ls180.v:767.5-767.49"
- process $proc$ls180.v:767$3044
+ attribute \src "ls180.v:763.5-763.49"
+ process $proc$ls180.v:763$3044
assign { } { }
assign $1\main_sdram_choose_req_cmd_payload_ras[0:0] 1'0
sync always
sync init
update \main_sdram_choose_req_cmd_payload_ras $1\main_sdram_choose_req_cmd_payload_ras[0:0]
end
- attribute \src "ls180.v:768.5-768.48"
- process $proc$ls180.v:768$3045
+ attribute \src "ls180.v:764.5-764.48"
+ process $proc$ls180.v:764$3045
assign { } { }
assign $1\main_sdram_choose_req_cmd_payload_we[0:0] 1'0
sync always
sync init
update \main_sdram_choose_req_cmd_payload_we $1\main_sdram_choose_req_cmd_payload_we[0:0]
end
- attribute \src "ls180.v:772.11-772.46"
- process $proc$ls180.v:772$3046
+ attribute \src "ls180.v:768.11-768.46"
+ process $proc$ls180.v:768$3046
assign { } { }
assign $1\main_sdram_choose_req_valids[3:0] 4'0000
sync always
sync init
update \main_sdram_choose_req_valids $1\main_sdram_choose_req_valids[3:0]
end
- attribute \src "ls180.v:774.11-774.45"
- process $proc$ls180.v:774$3047
+ attribute \src "ls180.v:770.11-770.45"
+ process $proc$ls180.v:770$3047
assign { } { }
assign $1\main_sdram_choose_req_grant[1:0] 2'00
sync always
sync init
update \main_sdram_choose_req_grant $1\main_sdram_choose_req_grant[1:0]
end
- attribute \src "ls180.v:776.12-776.36"
- process $proc$ls180.v:776$3048
+ attribute \src "ls180.v:772.12-772.36"
+ process $proc$ls180.v:772$3048
assign { } { }
assign $0\main_sdram_nop_a[12:0] 13'0000000000000
sync always
update \main_sdram_nop_a $0\main_sdram_nop_a[12:0]
sync init
end
- attribute \src "ls180.v:777.11-777.35"
- process $proc$ls180.v:777$3049
+ attribute \src "ls180.v:773.11-773.35"
+ process $proc$ls180.v:773$3049
assign { } { }
assign $0\main_sdram_nop_ba[1:0] 2'00
sync always
update \main_sdram_nop_ba $0\main_sdram_nop_ba[1:0]
sync init
end
- attribute \src "ls180.v:778.11-778.40"
- process $proc$ls180.v:778$3050
+ attribute \src "ls180.v:774.11-774.40"
+ process $proc$ls180.v:774$3050
assign { } { }
assign $1\main_sdram_steerer_sel[1:0] 2'00
sync always
sync init
update \main_sdram_steerer_sel $1\main_sdram_steerer_sel[1:0]
end
- attribute \src "ls180.v:779.5-779.31"
- process $proc$ls180.v:779$3051
+ attribute \src "ls180.v:775.5-775.31"
+ process $proc$ls180.v:775$3051
assign { } { }
assign $0\main_sdram_steerer0[0:0] 1'1
sync always
update \main_sdram_steerer0 $0\main_sdram_steerer0[0:0]
sync init
end
- attribute \src "ls180.v:780.5-780.31"
- process $proc$ls180.v:780$3052
+ attribute \src "ls180.v:776.5-776.31"
+ process $proc$ls180.v:776$3052
assign { } { }
assign $0\main_sdram_steerer1[0:0] 1'1
sync always
update \main_sdram_steerer1 $0\main_sdram_steerer1[0:0]
sync init
end
- attribute \src "ls180.v:782.32-782.63"
- process $proc$ls180.v:782$3053
+ attribute \src "ls180.v:778.32-778.63"
+ process $proc$ls180.v:778$3053
assign { } { }
assign $0\main_sdram_trrdcon_ready[0:0] 1'1
sync always
update \main_sdram_trrdcon_ready $0\main_sdram_trrdcon_ready[0:0]
sync init
end
- attribute \src "ls180.v:784.32-784.63"
- process $proc$ls180.v:784$3054
+ attribute \src "ls180.v:780.32-780.63"
+ process $proc$ls180.v:780$3054
assign { } { }
assign $0\main_sdram_tfawcon_ready[0:0] 1'1
sync always
update \main_sdram_tfawcon_ready $0\main_sdram_tfawcon_ready[0:0]
sync init
end
- attribute \src "ls180.v:786.32-786.63"
- process $proc$ls180.v:786$3055
+ attribute \src "ls180.v:782.32-782.63"
+ process $proc$ls180.v:782$3055
assign { } { }
assign $1\main_sdram_tccdcon_ready[0:0] 1'0
sync always
sync init
update \main_sdram_tccdcon_ready $1\main_sdram_tccdcon_ready[0:0]
end
- attribute \src "ls180.v:787.5-787.36"
- process $proc$ls180.v:787$3056
+ attribute \src "ls180.v:783.5-783.36"
+ process $proc$ls180.v:783$3056
assign { } { }
assign $1\main_sdram_tccdcon_count[0:0] 1'0
sync always
sync init
update \main_sdram_tccdcon_count $1\main_sdram_tccdcon_count[0:0]
end
- attribute \src "ls180.v:789.32-789.63"
- process $proc$ls180.v:789$3057
+ attribute \src "ls180.v:785.32-785.63"
+ process $proc$ls180.v:785$3057
assign { } { }
assign $1\main_sdram_twtrcon_ready[0:0] 1'0
sync always
sync init
update \main_sdram_twtrcon_ready $1\main_sdram_twtrcon_ready[0:0]
end
- attribute \src "ls180.v:790.11-790.42"
- process $proc$ls180.v:790$3058
+ attribute \src "ls180.v:786.11-786.42"
+ process $proc$ls180.v:786$3058
assign { } { }
assign $1\main_sdram_twtrcon_count[2:0] 3'000
sync always
sync init
update \main_sdram_twtrcon_count $1\main_sdram_twtrcon_count[2:0]
end
- attribute \src "ls180.v:793.5-793.26"
- process $proc$ls180.v:793$3059
+ attribute \src "ls180.v:789.5-789.26"
+ process $proc$ls180.v:789$3059
assign { } { }
assign $1\main_sdram_en0[0:0] 1'0
sync always
sync init
update \main_sdram_en0 $1\main_sdram_en0[0:0]
end
- attribute \src "ls180.v:795.11-795.34"
- process $proc$ls180.v:795$3060
+ attribute \src "ls180.v:791.11-791.34"
+ process $proc$ls180.v:791$3060
assign { } { }
assign $1\main_sdram_time0[4:0] 5'00000
sync always
sync init
update \main_sdram_time0 $1\main_sdram_time0[4:0]
end
- attribute \src "ls180.v:796.5-796.26"
- process $proc$ls180.v:796$3061
+ attribute \src "ls180.v:792.5-792.26"
+ process $proc$ls180.v:792$3061
assign { } { }
assign $1\main_sdram_en1[0:0] 1'0
sync always
sync init
update \main_sdram_en1 $1\main_sdram_en1[0:0]
end
- attribute \src "ls180.v:798.11-798.34"
- process $proc$ls180.v:798$3062
+ attribute \src "ls180.v:794.11-794.34"
+ process $proc$ls180.v:794$3062
assign { } { }
assign $1\main_sdram_time1[3:0] 4'0000
sync always
sync init
update \main_sdram_time1 $1\main_sdram_time1[3:0]
end
- attribute \src "ls180.v:819.5-819.29"
- process $proc$ls180.v:819$3063
+ attribute \src "ls180.v:81.5-81.46"
+ process $proc$ls180.v:81$2771
+ assign { } { }
+ assign $1\main_libresocsim_libresoc_ibus_ack[0:0] 1'0
+ sync always
+ sync init
+ update \main_libresocsim_libresoc_ibus_ack $1\main_libresocsim_libresoc_ibus_ack[0:0]
+ end
+ attribute \src "ls180.v:815.5-815.29"
+ process $proc$ls180.v:815$3063
assign { } { }
assign $1\main_wb_sdram_ack[0:0] 1'0
sync always
sync init
update \main_wb_sdram_ack $1\main_wb_sdram_ack[0:0]
end
- attribute \src "ls180.v:823.5-823.29"
- process $proc$ls180.v:823$3064
+ attribute \src "ls180.v:819.5-819.29"
+ process $proc$ls180.v:819$3064
assign { } { }
assign $0\main_wb_sdram_err[0:0] 1'0
sync always
update \main_wb_sdram_err $0\main_wb_sdram_err[0:0]
sync init
end
- attribute \src "ls180.v:824.12-824.40"
- process $proc$ls180.v:824$3065
+ attribute \src "ls180.v:820.12-820.40"
+ process $proc$ls180.v:820$3065
assign { } { }
assign $1\main_litedram_wb_adr[29:0] 30'000000000000000000000000000000
sync always
sync init
update \main_litedram_wb_adr $1\main_litedram_wb_adr[29:0]
end
- attribute \src "ls180.v:825.12-825.42"
- process $proc$ls180.v:825$3066
+ attribute \src "ls180.v:821.12-821.42"
+ process $proc$ls180.v:821$3066
assign { } { }
assign $1\main_litedram_wb_dat_w[15:0] 16'0000000000000000
sync always
sync init
update \main_litedram_wb_dat_w $1\main_litedram_wb_dat_w[15:0]
end
- attribute \src "ls180.v:827.11-827.38"
- process $proc$ls180.v:827$3067
+ attribute \src "ls180.v:823.11-823.38"
+ process $proc$ls180.v:823$3067
assign { } { }
assign $1\main_litedram_wb_sel[1:0] 2'00
sync always
sync init
update \main_litedram_wb_sel $1\main_litedram_wb_sel[1:0]
end
- attribute \src "ls180.v:828.5-828.32"
- process $proc$ls180.v:828$3068
+ attribute \src "ls180.v:824.5-824.32"
+ process $proc$ls180.v:824$3068
assign { } { }
assign $1\main_litedram_wb_cyc[0:0] 1'0
sync always
sync init
update \main_litedram_wb_cyc $1\main_litedram_wb_cyc[0:0]
end
- attribute \src "ls180.v:829.5-829.32"
- process $proc$ls180.v:829$3069
+ attribute \src "ls180.v:825.5-825.32"
+ process $proc$ls180.v:825$3069
assign { } { }
assign $1\main_litedram_wb_stb[0:0] 1'0
sync always
sync init
update \main_litedram_wb_stb $1\main_litedram_wb_stb[0:0]
end
- attribute \src "ls180.v:83.5-83.46"
- process $proc$ls180.v:83$2771
- assign { } { }
- assign $1\main_libresocsim_libresoc_ibus_ack[0:0] 1'0
- sync always
- sync init
- update \main_libresocsim_libresoc_ibus_ack $1\main_libresocsim_libresoc_ibus_ack[0:0]
- end
- attribute \src "ls180.v:831.5-831.31"
- process $proc$ls180.v:831$3070
+ attribute \src "ls180.v:827.5-827.31"
+ process $proc$ls180.v:827$3070
assign { } { }
assign $1\main_litedram_wb_we[0:0] 1'0
sync always
sync init
update \main_litedram_wb_we $1\main_litedram_wb_we[0:0]
end
- attribute \src "ls180.v:832.5-832.31"
- process $proc$ls180.v:832$3071
+ attribute \src "ls180.v:828.5-828.31"
+ process $proc$ls180.v:828$3071
assign { } { }
assign $1\main_converter_skip[0:0] 1'0
sync always
sync init
update \main_converter_skip $1\main_converter_skip[0:0]
end
- attribute \src "ls180.v:833.5-833.34"
- process $proc$ls180.v:833$3072
+ attribute \src "ls180.v:829.5-829.34"
+ process $proc$ls180.v:829$3072
assign { } { }
assign $1\main_converter_counter[0:0] 1'0
sync always
sync init
update \main_converter_counter $1\main_converter_counter[0:0]
end
- attribute \src "ls180.v:835.12-835.40"
- process $proc$ls180.v:835$3073
+ attribute \src "ls180.v:83.5-83.46"
+ process $proc$ls180.v:83$2772
+ assign { } { }
+ assign $0\main_libresocsim_libresoc_ibus_err[0:0] 1'0
+ sync always
+ update \main_libresocsim_libresoc_ibus_err $0\main_libresocsim_libresoc_ibus_err[0:0]
+ sync init
+ end
+ attribute \src "ls180.v:831.12-831.40"
+ process $proc$ls180.v:831$3073
assign { } { }
assign $1\main_converter_dat_r[31:0] 0
sync always
sync init
update \main_converter_dat_r $1\main_converter_dat_r[31:0]
end
- attribute \src "ls180.v:836.5-836.29"
- process $proc$ls180.v:836$3074
+ attribute \src "ls180.v:832.5-832.29"
+ process $proc$ls180.v:832$3074
assign { } { }
assign $1\main_cmd_consumed[0:0] 1'0
sync always
sync init
update \main_cmd_consumed $1\main_cmd_consumed[0:0]
end
- attribute \src "ls180.v:837.5-837.31"
- process $proc$ls180.v:837$3075
+ attribute \src "ls180.v:833.5-833.31"
+ process $proc$ls180.v:833$3075
assign { } { }
assign $1\main_wdata_consumed[0:0] 1'0
sync always
sync init
update \main_wdata_consumed $1\main_wdata_consumed[0:0]
end
- attribute \src "ls180.v:841.12-841.47"
- process $proc$ls180.v:841$3076
+ attribute \src "ls180.v:837.12-837.47"
+ process $proc$ls180.v:837$3076
assign { } { }
assign $1\main_uart_phy_storage[31:0] 9895604
sync always
sync init
update \main_uart_phy_storage $1\main_uart_phy_storage[31:0]
end
- attribute \src "ls180.v:842.5-842.28"
- process $proc$ls180.v:842$3077
+ attribute \src "ls180.v:838.5-838.28"
+ process $proc$ls180.v:838$3077
assign { } { }
assign $1\main_uart_phy_re[0:0] 1'0
sync always
sync init
update \main_uart_phy_re $1\main_uart_phy_re[0:0]
end
- attribute \src "ls180.v:844.5-844.36"
- process $proc$ls180.v:844$3078
+ attribute \src "ls180.v:840.5-840.36"
+ process $proc$ls180.v:840$3078
assign { } { }
assign $1\main_uart_phy_sink_ready[0:0] 1'0
sync always
sync init
update \main_uart_phy_sink_ready $1\main_uart_phy_sink_ready[0:0]
end
- attribute \src "ls180.v:848.5-848.39"
- process $proc$ls180.v:848$3079
+ attribute \src "ls180.v:844.5-844.39"
+ process $proc$ls180.v:844$3079
assign { } { }
assign $1\main_uart_phy_uart_clk_txen[0:0] 1'0
sync always
sync init
update \main_uart_phy_uart_clk_txen $1\main_uart_phy_uart_clk_txen[0:0]
end
- attribute \src "ls180.v:849.12-849.54"
- process $proc$ls180.v:849$3080
+ attribute \src "ls180.v:845.12-845.54"
+ process $proc$ls180.v:845$3080
assign { } { }
assign $1\main_uart_phy_phase_accumulator_tx[31:0] 0
sync always
sync init
update \main_uart_phy_phase_accumulator_tx $1\main_uart_phy_phase_accumulator_tx[31:0]
end
- attribute \src "ls180.v:850.11-850.38"
- process $proc$ls180.v:850$3081
+ attribute \src "ls180.v:846.11-846.38"
+ process $proc$ls180.v:846$3081
assign { } { }
assign $1\main_uart_phy_tx_reg[7:0] 8'00000000
sync always
sync init
update \main_uart_phy_tx_reg $1\main_uart_phy_tx_reg[7:0]
end
- attribute \src "ls180.v:851.11-851.43"
- process $proc$ls180.v:851$3082
+ attribute \src "ls180.v:847.11-847.43"
+ process $proc$ls180.v:847$3082
assign { } { }
assign $1\main_uart_phy_tx_bitcount[3:0] 4'0000
sync always
sync init
update \main_uart_phy_tx_bitcount $1\main_uart_phy_tx_bitcount[3:0]
end
- attribute \src "ls180.v:852.5-852.33"
- process $proc$ls180.v:852$3083
+ attribute \src "ls180.v:848.5-848.33"
+ process $proc$ls180.v:848$3083
assign { } { }
assign $1\main_uart_phy_tx_busy[0:0] 1'0
sync always
sync init
update \main_uart_phy_tx_busy $1\main_uart_phy_tx_busy[0:0]
end
- attribute \src "ls180.v:853.5-853.38"
- process $proc$ls180.v:853$3084
+ attribute \src "ls180.v:849.5-849.38"
+ process $proc$ls180.v:849$3084
assign { } { }
assign $1\main_uart_phy_source_valid[0:0] 1'0
sync always
sync init
update \main_uart_phy_source_valid $1\main_uart_phy_source_valid[0:0]
end
- attribute \src "ls180.v:855.5-855.38"
- process $proc$ls180.v:855$3085
+ attribute \src "ls180.v:851.5-851.38"
+ process $proc$ls180.v:851$3085
assign { } { }
assign $0\main_uart_phy_source_first[0:0] 1'0
sync always
update \main_uart_phy_source_first $0\main_uart_phy_source_first[0:0]
sync init
end
- attribute \src "ls180.v:856.5-856.37"
- process $proc$ls180.v:856$3086
+ attribute \src "ls180.v:852.5-852.37"
+ process $proc$ls180.v:852$3086
assign { } { }
assign $0\main_uart_phy_source_last[0:0] 1'0
sync always
update \main_uart_phy_source_last $0\main_uart_phy_source_last[0:0]
sync init
end
- attribute \src "ls180.v:857.11-857.51"
- process $proc$ls180.v:857$3087
+ attribute \src "ls180.v:853.11-853.51"
+ process $proc$ls180.v:853$3087
assign { } { }
assign $1\main_uart_phy_source_payload_data[7:0] 8'00000000
sync always
sync init
update \main_uart_phy_source_payload_data $1\main_uart_phy_source_payload_data[7:0]
end
- attribute \src "ls180.v:858.5-858.39"
- process $proc$ls180.v:858$3088
+ attribute \src "ls180.v:854.5-854.39"
+ process $proc$ls180.v:854$3088
assign { } { }
assign $1\main_uart_phy_uart_clk_rxen[0:0] 1'0
sync always
sync init
update \main_uart_phy_uart_clk_rxen $1\main_uart_phy_uart_clk_rxen[0:0]
end
- attribute \src "ls180.v:859.12-859.54"
- process $proc$ls180.v:859$3089
+ attribute \src "ls180.v:855.12-855.54"
+ process $proc$ls180.v:855$3089
assign { } { }
assign $1\main_uart_phy_phase_accumulator_rx[31:0] 0
sync always
sync init
update \main_uart_phy_phase_accumulator_rx $1\main_uart_phy_phase_accumulator_rx[31:0]
end
- attribute \src "ls180.v:861.5-861.30"
- process $proc$ls180.v:861$3090
+ attribute \src "ls180.v:857.5-857.30"
+ process $proc$ls180.v:857$3090
assign { } { }
assign $1\main_uart_phy_rx_r[0:0] 1'0
sync always
sync init
update \main_uart_phy_rx_r $1\main_uart_phy_rx_r[0:0]
end
- attribute \src "ls180.v:862.11-862.38"
- process $proc$ls180.v:862$3091
+ attribute \src "ls180.v:858.11-858.38"
+ process $proc$ls180.v:858$3091
assign { } { }
assign $1\main_uart_phy_rx_reg[7:0] 8'00000000
sync always
sync init
update \main_uart_phy_rx_reg $1\main_uart_phy_rx_reg[7:0]
end
- attribute \src "ls180.v:863.11-863.43"
- process $proc$ls180.v:863$3092
+ attribute \src "ls180.v:859.11-859.43"
+ process $proc$ls180.v:859$3092
assign { } { }
assign $1\main_uart_phy_rx_bitcount[3:0] 4'0000
sync always
sync init
update \main_uart_phy_rx_bitcount $1\main_uart_phy_rx_bitcount[3:0]
end
- attribute \src "ls180.v:864.5-864.33"
- process $proc$ls180.v:864$3093
+ attribute \src "ls180.v:860.5-860.33"
+ process $proc$ls180.v:860$3093
assign { } { }
assign $1\main_uart_phy_rx_busy[0:0] 1'0
sync always
sync init
update \main_uart_phy_rx_busy $1\main_uart_phy_rx_busy[0:0]
end
- attribute \src "ls180.v:87.5-87.46"
- process $proc$ls180.v:87$2772
- assign { } { }
- assign $0\main_libresocsim_libresoc_ibus_err[0:0] 1'0
- sync always
- update \main_libresocsim_libresoc_ibus_err $0\main_libresocsim_libresoc_ibus_err[0:0]
- sync init
- end
- attribute \src "ls180.v:875.5-875.32"
- process $proc$ls180.v:875$3094
+ attribute \src "ls180.v:871.5-871.32"
+ process $proc$ls180.v:871$3094
assign { } { }
assign $1\main_uart_tx_pending[0:0] 1'0
sync always
sync init
update \main_uart_tx_pending $1\main_uart_tx_pending[0:0]
end
- attribute \src "ls180.v:877.5-877.30"
- process $proc$ls180.v:877$3095
+ attribute \src "ls180.v:873.5-873.30"
+ process $proc$ls180.v:873$3095
assign { } { }
assign $1\main_uart_tx_clear[0:0] 1'0
sync always
sync init
update \main_uart_tx_clear $1\main_uart_tx_clear[0:0]
end
- attribute \src "ls180.v:878.5-878.36"
- process $proc$ls180.v:878$3096
+ attribute \src "ls180.v:874.5-874.36"
+ process $proc$ls180.v:874$3096
assign { } { }
assign $1\main_uart_tx_old_trigger[0:0] 1'0
sync always
sync init
update \main_uart_tx_old_trigger $1\main_uart_tx_old_trigger[0:0]
end
- attribute \src "ls180.v:880.5-880.32"
- process $proc$ls180.v:880$3097
+ attribute \src "ls180.v:876.5-876.32"
+ process $proc$ls180.v:876$3097
assign { } { }
assign $1\main_uart_rx_pending[0:0] 1'0
sync always
sync init
update \main_uart_rx_pending $1\main_uart_rx_pending[0:0]
end
- attribute \src "ls180.v:882.5-882.30"
- process $proc$ls180.v:882$3098
+ attribute \src "ls180.v:878.5-878.30"
+ process $proc$ls180.v:878$3098
assign { } { }
assign $1\main_uart_rx_clear[0:0] 1'0
sync always
sync init
update \main_uart_rx_clear $1\main_uart_rx_clear[0:0]
end
- attribute \src "ls180.v:883.5-883.36"
- process $proc$ls180.v:883$3099
+ attribute \src "ls180.v:879.5-879.36"
+ process $proc$ls180.v:879$3099
assign { } { }
assign $1\main_uart_rx_old_trigger[0:0] 1'0
sync always
sync init
update \main_uart_rx_old_trigger $1\main_uart_rx_old_trigger[0:0]
end
- attribute \src "ls180.v:887.11-887.49"
- process $proc$ls180.v:887$3100
+ attribute \src "ls180.v:883.11-883.49"
+ process $proc$ls180.v:883$3100
assign { } { }
assign $1\main_uart_eventmanager_status_w[1:0] 2'00
sync always
sync init
update \main_uart_eventmanager_status_w $1\main_uart_eventmanager_status_w[1:0]
end
- attribute \src "ls180.v:891.11-891.50"
- process $proc$ls180.v:891$3101
+ attribute \src "ls180.v:887.11-887.50"
+ process $proc$ls180.v:887$3101
assign { } { }
assign $1\main_uart_eventmanager_pending_w[1:0] 2'00
sync always
sync init
update \main_uart_eventmanager_pending_w $1\main_uart_eventmanager_pending_w[1:0]
end
- attribute \src "ls180.v:892.11-892.48"
- process $proc$ls180.v:892$3102
+ attribute \src "ls180.v:888.11-888.48"
+ process $proc$ls180.v:888$3102
assign { } { }
assign $1\main_uart_eventmanager_storage[1:0] 2'00
sync always
sync init
update \main_uart_eventmanager_storage $1\main_uart_eventmanager_storage[1:0]
end
- attribute \src "ls180.v:893.5-893.37"
- process $proc$ls180.v:893$3103
+ attribute \src "ls180.v:889.5-889.37"
+ process $proc$ls180.v:889$3103
assign { } { }
assign $1\main_uart_eventmanager_re[0:0] 1'0
sync always
sync init
update \main_uart_eventmanager_re $1\main_uart_eventmanager_re[0:0]
end
- attribute \src "ls180.v:910.5-910.40"
- process $proc$ls180.v:910$3104
+ attribute \src "ls180.v:906.5-906.40"
+ process $proc$ls180.v:906$3104
assign { } { }
assign $0\main_uart_tx_fifo_sink_first[0:0] 1'0
sync always
update \main_uart_tx_fifo_sink_first $0\main_uart_tx_fifo_sink_first[0:0]
sync init
end
- attribute \src "ls180.v:911.5-911.39"
- process $proc$ls180.v:911$3105
+ attribute \src "ls180.v:907.5-907.39"
+ process $proc$ls180.v:907$3105
assign { } { }
assign $0\main_uart_tx_fifo_sink_last[0:0] 1'0
sync always
update \main_uart_tx_fifo_sink_last $0\main_uart_tx_fifo_sink_last[0:0]
sync init
end
- attribute \src "ls180.v:919.5-919.38"
- process $proc$ls180.v:919$3106
+ attribute \src "ls180.v:915.5-915.38"
+ process $proc$ls180.v:915$3106
assign { } { }
assign $1\main_uart_tx_fifo_readable[0:0] 1'0
sync always
sync init
update \main_uart_tx_fifo_readable $1\main_uart_tx_fifo_readable[0:0]
end
- attribute \src "ls180.v:926.11-926.42"
- process $proc$ls180.v:926$3107
+ attribute \src "ls180.v:922.11-922.42"
+ process $proc$ls180.v:922$3107
assign { } { }
assign $1\main_uart_tx_fifo_level0[4:0] 5'00000
sync always
sync init
update \main_uart_tx_fifo_level0 $1\main_uart_tx_fifo_level0[4:0]
end
- attribute \src "ls180.v:927.5-927.37"
- process $proc$ls180.v:927$3108
+ attribute \src "ls180.v:923.5-923.37"
+ process $proc$ls180.v:923$3108
assign { } { }
assign $0\main_uart_tx_fifo_replace[0:0] 1'0
sync always
update \main_uart_tx_fifo_replace $0\main_uart_tx_fifo_replace[0:0]
sync init
end
- attribute \src "ls180.v:928.11-928.43"
- process $proc$ls180.v:928$3109
+ attribute \src "ls180.v:924.11-924.43"
+ process $proc$ls180.v:924$3109
assign { } { }
assign $1\main_uart_tx_fifo_produce[3:0] 4'0000
sync always
sync init
update \main_uart_tx_fifo_produce $1\main_uart_tx_fifo_produce[3:0]
end
- attribute \src "ls180.v:929.11-929.43"
- process $proc$ls180.v:929$3110
+ attribute \src "ls180.v:925.11-925.43"
+ process $proc$ls180.v:925$3110
assign { } { }
assign $1\main_uart_tx_fifo_consume[3:0] 4'0000
sync always
sync init
update \main_uart_tx_fifo_consume $1\main_uart_tx_fifo_consume[3:0]
end
- attribute \src "ls180.v:930.11-930.46"
- process $proc$ls180.v:930$3111
+ attribute \src "ls180.v:926.11-926.46"
+ process $proc$ls180.v:926$3111
assign { } { }
assign $1\main_uart_tx_fifo_wrport_adr[3:0] 4'0000
sync always
sync init
update \main_uart_tx_fifo_wrport_adr $1\main_uart_tx_fifo_wrport_adr[3:0]
end
- attribute \src "ls180.v:956.5-956.38"
- process $proc$ls180.v:956$3112
+ attribute \src "ls180.v:952.5-952.38"
+ process $proc$ls180.v:952$3112
assign { } { }
assign $1\main_uart_rx_fifo_readable[0:0] 1'0
sync always
sync init
update \main_uart_rx_fifo_readable $1\main_uart_rx_fifo_readable[0:0]
end
- attribute \src "ls180.v:963.11-963.42"
- process $proc$ls180.v:963$3113
+ attribute \src "ls180.v:959.11-959.42"
+ process $proc$ls180.v:959$3113
assign { } { }
assign $1\main_uart_rx_fifo_level0[4:0] 5'00000
sync always
sync init
update \main_uart_rx_fifo_level0 $1\main_uart_rx_fifo_level0[4:0]
end
- attribute \src "ls180.v:964.5-964.37"
- process $proc$ls180.v:964$3114
+ attribute \src "ls180.v:960.5-960.37"
+ process $proc$ls180.v:960$3114
assign { } { }
assign $0\main_uart_rx_fifo_replace[0:0] 1'0
sync always
update \main_uart_rx_fifo_replace $0\main_uart_rx_fifo_replace[0:0]
sync init
end
- attribute \src "ls180.v:965.11-965.43"
- process $proc$ls180.v:965$3115
+ attribute \src "ls180.v:961.11-961.43"
+ process $proc$ls180.v:961$3115
assign { } { }
assign $1\main_uart_rx_fifo_produce[3:0] 4'0000
sync always
sync init
update \main_uart_rx_fifo_produce $1\main_uart_rx_fifo_produce[3:0]
end
- attribute \src "ls180.v:966.11-966.43"
- process $proc$ls180.v:966$3116
+ attribute \src "ls180.v:962.11-962.43"
+ process $proc$ls180.v:962$3116
assign { } { }
assign $1\main_uart_rx_fifo_consume[3:0] 4'0000
sync always
sync init
update \main_uart_rx_fifo_consume $1\main_uart_rx_fifo_consume[3:0]
end
- attribute \src "ls180.v:967.11-967.46"
- process $proc$ls180.v:967$3117
+ attribute \src "ls180.v:963.11-963.46"
+ process $proc$ls180.v:963$3117
assign { } { }
assign $1\main_uart_rx_fifo_wrport_adr[3:0] 4'0000
sync always
sync init
update \main_uart_rx_fifo_wrport_adr $1\main_uart_rx_fifo_wrport_adr[3:0]
end
- attribute \src "ls180.v:982.5-982.27"
- process $proc$ls180.v:982$3118
+ attribute \src "ls180.v:978.5-978.27"
+ process $proc$ls180.v:978$3118
assign { } { }
assign $0\main_uart_reset[0:0] 1'0
sync always
update \main_uart_reset $0\main_uart_reset[0:0]
sync init
end
- attribute \src "ls180.v:983.12-983.40"
- process $proc$ls180.v:983$3119
+ attribute \src "ls180.v:979.12-979.40"
+ process $proc$ls180.v:979$3119
assign { } { }
assign $1\main_gpio_oe_storage[15:0] 16'0000000000000000
sync always
sync init
update \main_gpio_oe_storage $1\main_gpio_oe_storage[15:0]
end
- attribute \src "ls180.v:984.5-984.27"
- process $proc$ls180.v:984$3120
+ attribute \src "ls180.v:980.5-980.27"
+ process $proc$ls180.v:980$3120
assign { } { }
assign $1\main_gpio_oe_re[0:0] 1'0
sync always
sync init
update \main_gpio_oe_re $1\main_gpio_oe_re[0:0]
end
- attribute \src "ls180.v:985.12-985.36"
- process $proc$ls180.v:985$3121
+ attribute \src "ls180.v:981.12-981.36"
+ process $proc$ls180.v:981$3121
assign { } { }
assign $1\main_gpio_status[15:0] 16'0000000000000000
sync always
sync init
update \main_gpio_status $1\main_gpio_status[15:0]
end
- attribute \src "ls180.v:987.12-987.41"
- process $proc$ls180.v:987$3122
+ attribute \src "ls180.v:983.12-983.41"
+ process $proc$ls180.v:983$3122
assign { } { }
assign $1\main_gpio_out_storage[15:0] 16'0000000000000000
sync always
sync init
update \main_gpio_out_storage $1\main_gpio_out_storage[15:0]
end
- attribute \src "ls180.v:988.5-988.28"
- process $proc$ls180.v:988$3123
+ attribute \src "ls180.v:984.5-984.28"
+ process $proc$ls180.v:984$3123
assign { } { }
assign $1\main_gpio_out_re[0:0] 1'0
sync always
sync init
update \main_gpio_out_re $1\main_gpio_out_re[0:0]
end
- attribute \src "ls180.v:994.5-994.32"
- process $proc$ls180.v:994$3124
+ attribute \src "ls180.v:990.5-990.32"
+ process $proc$ls180.v:990$3124
assign { } { }
assign $1\main_spimaster2_done[0:0] 1'0
sync always
sync init
update \main_spimaster2_done $1\main_spimaster2_done[0:0]
end
- attribute \src "ls180.v:995.5-995.31"
- process $proc$ls180.v:995$3125
+ attribute \src "ls180.v:991.5-991.31"
+ process $proc$ls180.v:991$3125
assign { } { }
assign $1\main_spimaster3_irq[0:0] 1'0
sync always
sync init
update \main_spimaster3_irq $1\main_spimaster3_irq[0:0]
end
- attribute \src "ls180.v:997.11-997.38"
- process $proc$ls180.v:997$3126
+ attribute \src "ls180.v:993.11-993.38"
+ process $proc$ls180.v:993$3126
assign { } { }
assign $1\main_spimaster5_miso[7:0] 8'00000000
sync always
sync init
update \main_spimaster5_miso $1\main_spimaster5_miso[7:0]
end
+ attribute \src "ls180.v:996.12-996.47"
+ process $proc$ls180.v:996$3127
+ assign { } { }
+ assign $0\main_spimaster8_clk_divider[15:0] 16'0000000000000111
+ sync always
+ update \main_spimaster8_clk_divider $0\main_spimaster8_clk_divider[15:0]
+ sync init
+ end
+ attribute \src "ls180.v:997.5-997.33"
+ process $proc$ls180.v:997$3128
+ assign { } { }
+ assign $1\main_spimaster9_start[0:0] 1'0
+ sync always
+ sync init
+ update \main_spimaster9_start $1\main_spimaster9_start[0:0]
+ end
+ attribute \src "ls180.v:999.12-999.44"
+ process $proc$ls180.v:999$3129
+ assign { } { }
+ assign $1\main_spimaster11_storage[15:0] 16'0000000000000000
+ sync always
+ sync init
+ update \main_spimaster11_storage $1\main_spimaster11_storage[15:0]
+ end
connect \main_libresocsim_libresoc_reset \main_libresocsim_reset
connect \main_libresocsim_libresoc_clk_sel \sys_clksel_i
connect \sys_pll_18_o \main_libresocsim_libresoc_pll_18_o
connect \main_sdcore_sink_sink_last \main_sdmem2block_source_source_last0
connect \main_sdcore_sink_sink_payload_data \main_sdmem2block_source_source_payload_data0
connect \main_libresocsim_bus_error \builder_error
- connect \main_libresocsim_converter0_reset $not$ls180.v:2777$14_Y
+ connect \main_libresocsim_converter0_reset $not$ls180.v:2773$14_Y
connect \main_libresocsim_libresoc_ibus_dat_r { \main_libresocsim_interface0_converted_interface_dat_r \main_libresocsim_converter0_dat_r [63:32] }
- connect \main_libresocsim_converter1_reset $not$ls180.v:2837$25_Y
+ connect \main_libresocsim_converter1_reset $not$ls180.v:2833$25_Y
connect \main_libresocsim_libresoc_dbus_dat_r { \main_libresocsim_interface1_converted_interface_dat_r \main_libresocsim_converter1_dat_r [63:32] }
- connect \main_libresocsim_converter2_reset $not$ls180.v:2897$36_Y
+ connect \main_libresocsim_converter2_reset $not$ls180.v:2893$36_Y
connect \main_libresocsim_libresoc_jtag_wb_dat_r { \main_libresocsim_interface2_converted_interface_dat_r \main_libresocsim_converter2_dat_r [63:32] }
connect \main_libresocsim_reset \main_libresocsim_reset_re
connect \main_libresocsim_bus_errors_status \main_libresocsim_bus_errors
connect \main_libresocsim_adr \main_libresocsim_ram_bus_adr [6:0]
connect \main_libresocsim_ram_bus_dat_r \main_libresocsim_dat_r
connect \main_libresocsim_dat_w \main_libresocsim_ram_bus_dat_w
- connect \main_libresocsim_zero_trigger $ne$ls180.v:2969$60_Y
+ connect \main_libresocsim_zero_trigger $ne$ls180.v:2965$60_Y
connect \main_libresocsim_eventmanager_status_w \main_libresocsim_zero_status
connect \main_libresocsim_eventmanager_pending_w \main_libresocsim_zero_pending
- connect \main_libresocsim_irq $and$ls180.v:2978$63_Y
+ connect \main_libresocsim_irq $and$ls180.v:2974$63_Y
connect \main_libresocsim_zero_status \main_libresocsim_zero_trigger
connect \sys_clk_1 \sys_clk
connect \por_clk \sys_clk
connect \main_sdram_inti_p0_reset_n \main_sdram_reset_n
connect \main_sdram_inti_p0_address \main_sdram_address_storage
connect \main_sdram_inti_p0_bank \main_sdram_baddress_storage
- connect \main_sdram_inti_p0_wrdata_en $and$ls180.v:3092$70_Y
- connect \main_sdram_inti_p0_rddata_en $and$ls180.v:3093$71_Y
+ connect \main_sdram_inti_p0_wrdata_en $and$ls180.v:3088$70_Y
+ connect \main_sdram_inti_p0_rddata_en $and$ls180.v:3089$71_Y
connect \main_sdram_inti_p0_wrdata \main_sdram_wrdata_storage
connect \main_sdram_inti_p0_wrdata_mask 2'00
connect \main_sdram_bankmachine0_req_valid \main_sdram_interface_bank0_valid
connect \main_sdram_interface_bank3_lock \main_sdram_bankmachine3_req_lock
connect \main_sdram_interface_bank3_wdata_ready \main_sdram_bankmachine3_req_wdata_ready
connect \main_sdram_interface_bank3_rdata_valid \main_sdram_bankmachine3_req_rdata_valid
- connect \main_sdram_timer_wait $not$ls180.v:3124$72_Y
+ connect \main_sdram_timer_wait $not$ls180.v:3120$72_Y
connect \main_sdram_postponer_req_i \main_sdram_timer_done0
connect \main_sdram_wants_refresh \main_sdram_postponer_req_o
- connect \main_sdram_timer_done1 $eq$ls180.v:3127$73_Y
+ connect \main_sdram_timer_done1 $eq$ls180.v:3123$73_Y
connect \main_sdram_timer_done0 \main_sdram_timer_done1
connect \main_sdram_timer_count0 \main_sdram_timer_count1
- connect \main_sdram_sequencer_start1 $or$ls180.v:3130$75_Y
- connect \main_sdram_sequencer_done0 $and$ls180.v:3131$77_Y
+ connect \main_sdram_sequencer_start1 $or$ls180.v:3126$75_Y
+ connect \main_sdram_sequencer_done0 $and$ls180.v:3127$77_Y
connect \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_valid \main_sdram_bankmachine0_req_valid
connect \main_sdram_bankmachine0_req_ready \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_ready
connect \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_we \main_sdram_bankmachine0_req_we
connect \main_sdram_bankmachine0_cmd_buffer_sink_last \main_sdram_bankmachine0_cmd_buffer_lookahead_source_last
connect \main_sdram_bankmachine0_cmd_buffer_sink_payload_we \main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_we
connect \main_sdram_bankmachine0_cmd_buffer_sink_payload_addr \main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr
- connect \main_sdram_bankmachine0_cmd_buffer_source_ready $or$ls180.v:3173$79_Y
- connect \main_sdram_bankmachine0_req_lock $or$ls180.v:3174$80_Y
- connect \main_sdram_bankmachine0_row_hit $eq$ls180.v:3175$81_Y
+ connect \main_sdram_bankmachine0_cmd_buffer_source_ready $or$ls180.v:3169$79_Y
+ connect \main_sdram_bankmachine0_req_lock $or$ls180.v:3170$80_Y
+ connect \main_sdram_bankmachine0_row_hit $eq$ls180.v:3171$81_Y
connect \main_sdram_bankmachine0_cmd_payload_ba 2'00
- connect \main_sdram_bankmachine0_twtpcon_valid $and$ls180.v:3185$86_Y
- connect \main_sdram_bankmachine0_trccon_valid $and$ls180.v:3186$88_Y
- connect \main_sdram_bankmachine0_trascon_valid $and$ls180.v:3187$90_Y
+ connect \main_sdram_bankmachine0_twtpcon_valid $and$ls180.v:3181$86_Y
+ connect \main_sdram_bankmachine0_trccon_valid $and$ls180.v:3182$88_Y
+ connect \main_sdram_bankmachine0_trascon_valid $and$ls180.v:3183$90_Y
connect \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_din { \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_last \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_first \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we }
connect { \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we } \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout
connect \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_ready \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable
connect \main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr
connect \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_re \main_sdram_bankmachine0_cmd_buffer_lookahead_source_ready
connect \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_din
- connect \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_we $and$ls180.v:3219$98_Y
- connect \main_sdram_bankmachine0_cmd_buffer_lookahead_do_read $and$ls180.v:3220$99_Y
+ connect \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_we $and$ls180.v:3215$98_Y
+ connect \main_sdram_bankmachine0_cmd_buffer_lookahead_do_read $and$ls180.v:3216$99_Y
connect \main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_adr \main_sdram_bankmachine0_cmd_buffer_lookahead_consume
connect \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout \main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r
- connect \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable $ne$ls180.v:3223$100_Y
- connect \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable $ne$ls180.v:3224$101_Y
- connect \main_sdram_bankmachine0_cmd_buffer_sink_ready $or$ls180.v:3225$103_Y
+ connect \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable $ne$ls180.v:3219$100_Y
+ connect \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable $ne$ls180.v:3220$101_Y
+ connect \main_sdram_bankmachine0_cmd_buffer_sink_ready $or$ls180.v:3221$103_Y
connect \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_valid \main_sdram_bankmachine1_req_valid
connect \main_sdram_bankmachine1_req_ready \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_ready
connect \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_we \main_sdram_bankmachine1_req_we
connect \main_sdram_bankmachine1_cmd_buffer_sink_last \main_sdram_bankmachine1_cmd_buffer_lookahead_source_last
connect \main_sdram_bankmachine1_cmd_buffer_sink_payload_we \main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_we
connect \main_sdram_bankmachine1_cmd_buffer_sink_payload_addr \main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr
- connect \main_sdram_bankmachine1_cmd_buffer_source_ready $or$ls180.v:3330$109_Y
- connect \main_sdram_bankmachine1_req_lock $or$ls180.v:3331$110_Y
- connect \main_sdram_bankmachine1_row_hit $eq$ls180.v:3332$111_Y
+ connect \main_sdram_bankmachine1_cmd_buffer_source_ready $or$ls180.v:3326$109_Y
+ connect \main_sdram_bankmachine1_req_lock $or$ls180.v:3327$110_Y
+ connect \main_sdram_bankmachine1_row_hit $eq$ls180.v:3328$111_Y
connect \main_sdram_bankmachine1_cmd_payload_ba 2'01
- connect \main_sdram_bankmachine1_twtpcon_valid $and$ls180.v:3342$116_Y
- connect \main_sdram_bankmachine1_trccon_valid $and$ls180.v:3343$118_Y
- connect \main_sdram_bankmachine1_trascon_valid $and$ls180.v:3344$120_Y
+ connect \main_sdram_bankmachine1_twtpcon_valid $and$ls180.v:3338$116_Y
+ connect \main_sdram_bankmachine1_trccon_valid $and$ls180.v:3339$118_Y
+ connect \main_sdram_bankmachine1_trascon_valid $and$ls180.v:3340$120_Y
connect \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_din { \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_last \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_first \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we }
connect { \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we } \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout
connect \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_ready \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable
connect \main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr
connect \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_re \main_sdram_bankmachine1_cmd_buffer_lookahead_source_ready
connect \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_din
- connect \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_we $and$ls180.v:3376$128_Y
- connect \main_sdram_bankmachine1_cmd_buffer_lookahead_do_read $and$ls180.v:3377$129_Y
+ connect \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_we $and$ls180.v:3372$128_Y
+ connect \main_sdram_bankmachine1_cmd_buffer_lookahead_do_read $and$ls180.v:3373$129_Y
connect \main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_adr \main_sdram_bankmachine1_cmd_buffer_lookahead_consume
connect \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout \main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r
- connect \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable $ne$ls180.v:3380$130_Y
- connect \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable $ne$ls180.v:3381$131_Y
- connect \main_sdram_bankmachine1_cmd_buffer_sink_ready $or$ls180.v:3382$133_Y
+ connect \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable $ne$ls180.v:3376$130_Y
+ connect \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable $ne$ls180.v:3377$131_Y
+ connect \main_sdram_bankmachine1_cmd_buffer_sink_ready $or$ls180.v:3378$133_Y
connect \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_valid \main_sdram_bankmachine2_req_valid
connect \main_sdram_bankmachine2_req_ready \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_ready
connect \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_we \main_sdram_bankmachine2_req_we
connect \main_sdram_bankmachine2_cmd_buffer_sink_last \main_sdram_bankmachine2_cmd_buffer_lookahead_source_last
connect \main_sdram_bankmachine2_cmd_buffer_sink_payload_we \main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_we
connect \main_sdram_bankmachine2_cmd_buffer_sink_payload_addr \main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr
- connect \main_sdram_bankmachine2_cmd_buffer_source_ready $or$ls180.v:3487$139_Y
- connect \main_sdram_bankmachine2_req_lock $or$ls180.v:3488$140_Y
- connect \main_sdram_bankmachine2_row_hit $eq$ls180.v:3489$141_Y
+ connect \main_sdram_bankmachine2_cmd_buffer_source_ready $or$ls180.v:3483$139_Y
+ connect \main_sdram_bankmachine2_req_lock $or$ls180.v:3484$140_Y
+ connect \main_sdram_bankmachine2_row_hit $eq$ls180.v:3485$141_Y
connect \main_sdram_bankmachine2_cmd_payload_ba 2'10
- connect \main_sdram_bankmachine2_twtpcon_valid $and$ls180.v:3499$146_Y
- connect \main_sdram_bankmachine2_trccon_valid $and$ls180.v:3500$148_Y
- connect \main_sdram_bankmachine2_trascon_valid $and$ls180.v:3501$150_Y
+ connect \main_sdram_bankmachine2_twtpcon_valid $and$ls180.v:3495$146_Y
+ connect \main_sdram_bankmachine2_trccon_valid $and$ls180.v:3496$148_Y
+ connect \main_sdram_bankmachine2_trascon_valid $and$ls180.v:3497$150_Y
connect \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_din { \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_last \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_first \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we }
connect { \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we } \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout
connect \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_ready \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable
connect \main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr
connect \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_re \main_sdram_bankmachine2_cmd_buffer_lookahead_source_ready
connect \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_din
- connect \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_we $and$ls180.v:3533$158_Y
- connect \main_sdram_bankmachine2_cmd_buffer_lookahead_do_read $and$ls180.v:3534$159_Y
+ connect \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_we $and$ls180.v:3529$158_Y
+ connect \main_sdram_bankmachine2_cmd_buffer_lookahead_do_read $and$ls180.v:3530$159_Y
connect \main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_adr \main_sdram_bankmachine2_cmd_buffer_lookahead_consume
connect \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout \main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r
- connect \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable $ne$ls180.v:3537$160_Y
- connect \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable $ne$ls180.v:3538$161_Y
- connect \main_sdram_bankmachine2_cmd_buffer_sink_ready $or$ls180.v:3539$163_Y
+ connect \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable $ne$ls180.v:3533$160_Y
+ connect \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable $ne$ls180.v:3534$161_Y
+ connect \main_sdram_bankmachine2_cmd_buffer_sink_ready $or$ls180.v:3535$163_Y
connect \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_valid \main_sdram_bankmachine3_req_valid
connect \main_sdram_bankmachine3_req_ready \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_ready
connect \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_we \main_sdram_bankmachine3_req_we
connect \main_sdram_bankmachine3_cmd_buffer_sink_last \main_sdram_bankmachine3_cmd_buffer_lookahead_source_last
connect \main_sdram_bankmachine3_cmd_buffer_sink_payload_we \main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_we
connect \main_sdram_bankmachine3_cmd_buffer_sink_payload_addr \main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr
- connect \main_sdram_bankmachine3_cmd_buffer_source_ready $or$ls180.v:3644$169_Y
- connect \main_sdram_bankmachine3_req_lock $or$ls180.v:3645$170_Y
- connect \main_sdram_bankmachine3_row_hit $eq$ls180.v:3646$171_Y
+ connect \main_sdram_bankmachine3_cmd_buffer_source_ready $or$ls180.v:3640$169_Y
+ connect \main_sdram_bankmachine3_req_lock $or$ls180.v:3641$170_Y
+ connect \main_sdram_bankmachine3_row_hit $eq$ls180.v:3642$171_Y
connect \main_sdram_bankmachine3_cmd_payload_ba 2'11
- connect \main_sdram_bankmachine3_twtpcon_valid $and$ls180.v:3656$176_Y
- connect \main_sdram_bankmachine3_trccon_valid $and$ls180.v:3657$178_Y
- connect \main_sdram_bankmachine3_trascon_valid $and$ls180.v:3658$180_Y
+ connect \main_sdram_bankmachine3_twtpcon_valid $and$ls180.v:3652$176_Y
+ connect \main_sdram_bankmachine3_trccon_valid $and$ls180.v:3653$178_Y
+ connect \main_sdram_bankmachine3_trascon_valid $and$ls180.v:3654$180_Y
connect \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_din { \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_last \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_first \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we }
connect { \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we } \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout
connect \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_ready \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable
connect \main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr
connect \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_re \main_sdram_bankmachine3_cmd_buffer_lookahead_source_ready
connect \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_din
- connect \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_we $and$ls180.v:3690$188_Y
- connect \main_sdram_bankmachine3_cmd_buffer_lookahead_do_read $and$ls180.v:3691$189_Y
+ connect \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_we $and$ls180.v:3686$188_Y
+ connect \main_sdram_bankmachine3_cmd_buffer_lookahead_do_read $and$ls180.v:3687$189_Y
connect \main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_adr \main_sdram_bankmachine3_cmd_buffer_lookahead_consume
connect \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout \main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r
- connect \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable $ne$ls180.v:3694$190_Y
- connect \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable $ne$ls180.v:3695$191_Y
- connect \main_sdram_bankmachine3_cmd_buffer_sink_ready $or$ls180.v:3696$193_Y
+ connect \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable $ne$ls180.v:3690$190_Y
+ connect \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable $ne$ls180.v:3691$191_Y
+ connect \main_sdram_bankmachine3_cmd_buffer_sink_ready $or$ls180.v:3692$193_Y
connect \main_sdram_choose_req_want_cmds 1'1
- connect \main_sdram_trrdcon_valid $and$ls180.v:3792$204_Y
- connect \main_sdram_tfawcon_valid $and$ls180.v:3793$210_Y
- connect \main_sdram_ras_allowed $and$ls180.v:3794$211_Y
- connect \main_sdram_tccdcon_valid $and$ls180.v:3795$214_Y
+ connect \main_sdram_trrdcon_valid $and$ls180.v:3788$204_Y
+ connect \main_sdram_tfawcon_valid $and$ls180.v:3789$210_Y
+ connect \main_sdram_ras_allowed $and$ls180.v:3790$211_Y
+ connect \main_sdram_tccdcon_valid $and$ls180.v:3791$214_Y
connect \main_sdram_cas_allowed \main_sdram_tccdcon_ready
- connect \main_sdram_twtrcon_valid $and$ls180.v:3797$216_Y
- connect \main_sdram_read_available $or$ls180.v:3798$223_Y
- connect \main_sdram_write_available $or$ls180.v:3799$230_Y
- connect \main_sdram_max_time0 $eq$ls180.v:3800$231_Y
- connect \main_sdram_max_time1 $eq$ls180.v:3801$232_Y
+ connect \main_sdram_twtrcon_valid $and$ls180.v:3793$216_Y
+ connect \main_sdram_read_available $or$ls180.v:3794$223_Y
+ connect \main_sdram_write_available $or$ls180.v:3795$230_Y
+ connect \main_sdram_max_time0 $eq$ls180.v:3796$231_Y
+ connect \main_sdram_max_time1 $eq$ls180.v:3797$232_Y
connect \main_sdram_bankmachine0_refresh_req \main_sdram_cmd_valid
connect \main_sdram_bankmachine1_refresh_req \main_sdram_cmd_valid
connect \main_sdram_bankmachine2_refresh_req \main_sdram_cmd_valid
connect \main_sdram_bankmachine3_refresh_req \main_sdram_cmd_valid
- connect \main_sdram_go_to_refresh $and$ls180.v:3806$235_Y
+ connect \main_sdram_go_to_refresh $and$ls180.v:3802$235_Y
connect \main_sdram_interface_rdata \main_sdram_dfi_p0_rddata
connect \main_sdram_dfi_p0_wrdata \main_sdram_interface_wdata
- connect \main_sdram_dfi_p0_wrdata_mask $not$ls180.v:3809$236_Y
+ connect \main_sdram_dfi_p0_wrdata_mask $not$ls180.v:3805$236_Y
connect \main_sdram_choose_cmd_request \main_sdram_choose_cmd_valids
connect \main_sdram_choose_cmd_cmd_valid \builder_comb_rhs_array_muxed0
connect \main_sdram_choose_cmd_cmd_payload_a \builder_comb_rhs_array_muxed1
connect \main_sdram_choose_cmd_cmd_payload_is_read \builder_comb_rhs_array_muxed3
connect \main_sdram_choose_cmd_cmd_payload_is_write \builder_comb_rhs_array_muxed4
connect \main_sdram_choose_cmd_cmd_payload_is_cmd \builder_comb_rhs_array_muxed5
- connect \main_sdram_choose_cmd_ce $or$ls180.v:3842$294_Y
+ connect \main_sdram_choose_cmd_ce $or$ls180.v:3838$294_Y
connect \main_sdram_choose_req_request \main_sdram_choose_req_valids
connect \main_sdram_choose_req_cmd_valid \builder_comb_rhs_array_muxed6
connect \main_sdram_choose_req_cmd_payload_a \builder_comb_rhs_array_muxed7
connect \main_sdram_choose_req_cmd_payload_is_read \builder_comb_rhs_array_muxed9
connect \main_sdram_choose_req_cmd_payload_is_write \builder_comb_rhs_array_muxed10
connect \main_sdram_choose_req_cmd_payload_is_cmd \builder_comb_rhs_array_muxed11
- connect \main_sdram_choose_req_ce $or$ls180.v:3911$380_Y
+ connect \main_sdram_choose_req_ce $or$ls180.v:3907$380_Y
connect \main_sdram_dfi_p0_reset_n 1'1
connect \main_sdram_dfi_p0_cke \main_sdram_steerer0
connect \main_sdram_dfi_p0_odt \main_sdram_steerer1
- connect \builder_roundrobin0_request $and$ls180.v:3988$412_Y
- connect \builder_roundrobin0_ce $and$ls180.v:3989$415_Y
+ connect \builder_roundrobin0_request $and$ls180.v:3984$412_Y
+ connect \builder_roundrobin0_ce $and$ls180.v:3985$415_Y
connect \main_sdram_interface_bank0_addr \builder_comb_rhs_array_muxed12
connect \main_sdram_interface_bank0_we \builder_comb_rhs_array_muxed13
connect \main_sdram_interface_bank0_valid \builder_comb_rhs_array_muxed14
- connect \builder_roundrobin1_request $and$ls180.v:3993$428_Y
- connect \builder_roundrobin1_ce $and$ls180.v:3994$431_Y
+ connect \builder_roundrobin1_request $and$ls180.v:3989$428_Y
+ connect \builder_roundrobin1_ce $and$ls180.v:3990$431_Y
connect \main_sdram_interface_bank1_addr \builder_comb_rhs_array_muxed15
connect \main_sdram_interface_bank1_we \builder_comb_rhs_array_muxed16
connect \main_sdram_interface_bank1_valid \builder_comb_rhs_array_muxed17
- connect \builder_roundrobin2_request $and$ls180.v:3998$444_Y
- connect \builder_roundrobin2_ce $and$ls180.v:3999$447_Y
+ connect \builder_roundrobin2_request $and$ls180.v:3994$444_Y
+ connect \builder_roundrobin2_ce $and$ls180.v:3995$447_Y
connect \main_sdram_interface_bank2_addr \builder_comb_rhs_array_muxed18
connect \main_sdram_interface_bank2_we \builder_comb_rhs_array_muxed19
connect \main_sdram_interface_bank2_valid \builder_comb_rhs_array_muxed20
- connect \builder_roundrobin3_request $and$ls180.v:4003$460_Y
- connect \builder_roundrobin3_ce $and$ls180.v:4004$463_Y
+ connect \builder_roundrobin3_request $and$ls180.v:3999$460_Y
+ connect \builder_roundrobin3_ce $and$ls180.v:4000$463_Y
connect \main_sdram_interface_bank3_addr \builder_comb_rhs_array_muxed21
connect \main_sdram_interface_bank3_we \builder_comb_rhs_array_muxed22
connect \main_sdram_interface_bank3_valid \builder_comb_rhs_array_muxed23
- connect \main_port_cmd_ready $or$ls180.v:4008$527_Y
+ connect \main_port_cmd_ready $or$ls180.v:4004$527_Y
connect \main_port_wdata_ready \builder_new_master_wdata_ready
connect \main_port_rdata_valid \builder_new_master_rdata_valid3
connect \main_port_rdata_payload_data \main_sdram_interface_rdata
connect \builder_roundrobin1_grant 1'0
connect \builder_roundrobin2_grant 1'0
connect \builder_roundrobin3_grant 1'0
- connect \main_converter_reset $not$ls180.v:4030$529_Y
+ connect \main_converter_reset $not$ls180.v:4026$529_Y
connect \main_wb_sdram_dat_r { \main_litedram_wb_dat_r \main_converter_dat_r [31:16] }
- connect \main_port_cmd_payload_addr $sub$ls180.v:4090$540_Y [23:0]
+ connect \main_port_cmd_payload_addr $sub$ls180.v:4086$540_Y [23:0]
connect \main_port_cmd_payload_we \main_litedram_wb_we
connect \main_port_wdata_payload_data \main_litedram_wb_dat_w
connect \main_port_wdata_payload_we \main_litedram_wb_sel
connect \main_litedram_wb_dat_r \main_port_rdata_payload_data
- connect \main_port_flush $not$ls180.v:4095$541_Y
- connect \main_port_cmd_last $not$ls180.v:4096$542_Y
- connect \main_port_cmd_valid $and$ls180.v:4097$545_Y
- connect \main_port_wdata_valid $and$ls180.v:4098$549_Y
- connect \main_port_rdata_ready $and$ls180.v:4099$552_Y
- connect \main_litedram_wb_ack $and$ls180.v:4100$557_Y
- connect \main_ack_cmd $or$ls180.v:4101$559_Y
- connect \main_ack_wdata $or$ls180.v:4102$561_Y
- connect \main_ack_rdata $and$ls180.v:4103$562_Y
+ connect \main_port_flush $not$ls180.v:4091$541_Y
+ connect \main_port_cmd_last $not$ls180.v:4092$542_Y
+ connect \main_port_cmd_valid $and$ls180.v:4093$545_Y
+ connect \main_port_wdata_valid $and$ls180.v:4094$549_Y
+ connect \main_port_rdata_ready $and$ls180.v:4095$552_Y
+ connect \main_litedram_wb_ack $and$ls180.v:4096$557_Y
+ connect \main_ack_cmd $or$ls180.v:4097$559_Y
+ connect \main_ack_wdata $or$ls180.v:4098$561_Y
+ connect \main_ack_rdata $and$ls180.v:4099$562_Y
connect \main_uart_uart_sink_valid \main_uart_phy_source_valid
connect \main_uart_phy_source_ready \main_uart_uart_sink_ready
connect \main_uart_uart_sink_first \main_uart_phy_source_first
connect \main_uart_phy_sink_payload_data \main_uart_uart_source_payload_data
connect \main_uart_tx_fifo_sink_valid \main_uart_rxtx_re
connect \main_uart_tx_fifo_sink_payload_data \main_uart_rxtx_r
- connect \main_uart_txfull_status $not$ls180.v:4116$563_Y
- connect \main_uart_txempty_status $not$ls180.v:4117$564_Y
+ connect \main_uart_txfull_status $not$ls180.v:4112$563_Y
+ connect \main_uart_txempty_status $not$ls180.v:4113$564_Y
connect \main_uart_uart_source_valid \main_uart_tx_fifo_source_valid
connect \main_uart_tx_fifo_source_ready \main_uart_uart_source_ready
connect \main_uart_uart_source_first \main_uart_tx_fifo_source_first
connect \main_uart_uart_source_last \main_uart_tx_fifo_source_last
connect \main_uart_uart_source_payload_data \main_uart_tx_fifo_source_payload_data
- connect \main_uart_tx_trigger $not$ls180.v:4123$565_Y
+ connect \main_uart_tx_trigger $not$ls180.v:4119$565_Y
connect \main_uart_rx_fifo_sink_valid \main_uart_uart_sink_valid
connect \main_uart_uart_sink_ready \main_uart_rx_fifo_sink_ready
connect \main_uart_rx_fifo_sink_first \main_uart_uart_sink_first
connect \main_uart_rx_fifo_sink_last \main_uart_uart_sink_last
connect \main_uart_rx_fifo_sink_payload_data \main_uart_uart_sink_payload_data
- connect \main_uart_rxempty_status $not$ls180.v:4129$566_Y
- connect \main_uart_rxfull_status $not$ls180.v:4130$567_Y
+ connect \main_uart_rxempty_status $not$ls180.v:4125$566_Y
+ connect \main_uart_rxfull_status $not$ls180.v:4126$567_Y
connect \main_uart_rxtx_w \main_uart_rx_fifo_source_payload_data
- connect \main_uart_rx_fifo_source_ready $or$ls180.v:4132$569_Y
- connect \main_uart_rx_trigger $not$ls180.v:4133$570_Y
- connect \main_uart_irq $or$ls180.v:4156$579_Y
+ connect \main_uart_rx_fifo_source_ready $or$ls180.v:4128$569_Y
+ connect \main_uart_rx_trigger $not$ls180.v:4129$570_Y
+ connect \main_uart_irq $or$ls180.v:4152$579_Y
connect \main_uart_tx_status \main_uart_tx_trigger
connect \main_uart_rx_status \main_uart_rx_trigger
connect \main_uart_tx_fifo_syncfifo_din { \main_uart_tx_fifo_fifo_in_last \main_uart_tx_fifo_fifo_in_first \main_uart_tx_fifo_fifo_in_payload_data }
connect \main_uart_tx_fifo_source_last \main_uart_tx_fifo_fifo_out_last
connect \main_uart_tx_fifo_source_payload_data \main_uart_tx_fifo_fifo_out_payload_data
connect \main_uart_tx_fifo_re \main_uart_tx_fifo_source_ready
- connect \main_uart_tx_fifo_syncfifo_re $and$ls180.v:4171$582_Y
- connect \main_uart_tx_fifo_level1 $add$ls180.v:4172$583_Y
+ connect \main_uart_tx_fifo_syncfifo_re $and$ls180.v:4167$582_Y
+ connect \main_uart_tx_fifo_level1 $add$ls180.v:4168$583_Y
connect \main_uart_tx_fifo_wrport_dat_w \main_uart_tx_fifo_syncfifo_din
- connect \main_uart_tx_fifo_wrport_we $and$ls180.v:4182$587_Y
- connect \main_uart_tx_fifo_do_read $and$ls180.v:4183$588_Y
+ connect \main_uart_tx_fifo_wrport_we $and$ls180.v:4178$587_Y
+ connect \main_uart_tx_fifo_do_read $and$ls180.v:4179$588_Y
connect \main_uart_tx_fifo_rdport_adr \main_uart_tx_fifo_consume
connect \main_uart_tx_fifo_syncfifo_dout \main_uart_tx_fifo_rdport_dat_r
connect \main_uart_tx_fifo_rdport_re \main_uart_tx_fifo_do_read
- connect \main_uart_tx_fifo_syncfifo_writable $ne$ls180.v:4187$589_Y
- connect \main_uart_tx_fifo_syncfifo_readable $ne$ls180.v:4188$590_Y
+ connect \main_uart_tx_fifo_syncfifo_writable $ne$ls180.v:4183$589_Y
+ connect \main_uart_tx_fifo_syncfifo_readable $ne$ls180.v:4184$590_Y
connect \main_uart_rx_fifo_syncfifo_din { \main_uart_rx_fifo_fifo_in_last \main_uart_rx_fifo_fifo_in_first \main_uart_rx_fifo_fifo_in_payload_data }
connect { \main_uart_rx_fifo_fifo_out_last \main_uart_rx_fifo_fifo_out_first \main_uart_rx_fifo_fifo_out_payload_data } \main_uart_rx_fifo_syncfifo_dout
connect \main_uart_rx_fifo_sink_ready \main_uart_rx_fifo_syncfifo_writable
connect \main_uart_rx_fifo_source_last \main_uart_rx_fifo_fifo_out_last
connect \main_uart_rx_fifo_source_payload_data \main_uart_rx_fifo_fifo_out_payload_data
connect \main_uart_rx_fifo_re \main_uart_rx_fifo_source_ready
- connect \main_uart_rx_fifo_syncfifo_re $and$ls180.v:4201$593_Y
- connect \main_uart_rx_fifo_level1 $add$ls180.v:4202$594_Y
+ connect \main_uart_rx_fifo_syncfifo_re $and$ls180.v:4197$593_Y
+ connect \main_uart_rx_fifo_level1 $add$ls180.v:4198$594_Y
connect \main_uart_rx_fifo_wrport_dat_w \main_uart_rx_fifo_syncfifo_din
- connect \main_uart_rx_fifo_wrport_we $and$ls180.v:4212$598_Y
- connect \main_uart_rx_fifo_do_read $and$ls180.v:4213$599_Y
+ connect \main_uart_rx_fifo_wrport_we $and$ls180.v:4208$598_Y
+ connect \main_uart_rx_fifo_do_read $and$ls180.v:4209$599_Y
connect \main_uart_rx_fifo_rdport_adr \main_uart_rx_fifo_consume
connect \main_uart_rx_fifo_syncfifo_dout \main_uart_rx_fifo_rdport_dat_r
connect \main_uart_rx_fifo_rdport_re \main_uart_rx_fifo_do_read
- connect \main_uart_rx_fifo_syncfifo_writable $ne$ls180.v:4217$600_Y
- connect \main_uart_rx_fifo_syncfifo_readable $ne$ls180.v:4218$601_Y
+ connect \main_uart_rx_fifo_syncfifo_writable $ne$ls180.v:4213$600_Y
+ connect \main_uart_rx_fifo_syncfifo_readable $ne$ls180.v:4214$601_Y
connect \main_gpio_pads_i \gpio_i
connect \gpio_o \main_gpio_pads_o
connect \gpio_oe \main_gpio_pads_oe
connect \main_spimaster18_status \main_spimaster5_miso
connect \main_spimaster6_cs \main_spimaster21_storage
connect \main_spimaster7_loopback \main_spimaster23_storage
- connect \main_spimaster31_clk_rise $eq$ls180.v:4231$603_Y
- connect \main_spimaster32_clk_fall $eq$ls180.v:4232$605_Y
+ connect \main_spimaster31_clk_rise $eq$ls180.v:4227$603_Y
+ connect \main_spimaster32_clk_fall $eq$ls180.v:4228$605_Y
connect \main_spisdcard_start0 \main_spisdcard_start1
connect \main_spisdcard_length0 \main_spisdcard_length1
connect \main_spisdcard_mosi \main_spisdcard_mosi_storage
connect \main_spisdcard_miso_status \main_spisdcard_miso
connect \main_spisdcard_cs \main_spisdcard_cs_storage
connect \main_spisdcard_loopback \main_spisdcard_loopback_storage
- connect \main_spisdcard_clk_rise $eq$ls180.v:4289$611_Y
- connect \main_spisdcard_clk_fall $eq$ls180.v:4290$613_Y
+ connect \main_spisdcard_clk_rise $eq$ls180.v:4285$611_Y
+ connect \main_spisdcard_clk_fall $eq$ls180.v:4286$613_Y
connect \main_spisdcard_clk_divider0 \main_spimaster1_storage
connect \i2c_scl \main_i2c_scl
connect \i2c_sda_oe \main_i2c_oe
connect \i2c_sda_o \main_i2c_sda0
connect \main_i2c_sda1 \i2c_sda_i
connect \main_sdphy_status 1'0
- connect \main_sdphy_sdpads_clk $or$ls180.v:4346$621_Y
- connect \main_sdphy_sdpads_cmd_oe $or$ls180.v:4347$625_Y
- connect \main_sdphy_sdpads_cmd_o $or$ls180.v:4348$629_Y
- connect \main_sdphy_sdpads_data_oe $or$ls180.v:4349$633_Y
- connect \main_sdphy_sdpads_data_o $or$ls180.v:4350$637_Y
+ connect \main_sdphy_sdpads_clk $or$ls180.v:4342$621_Y
+ connect \main_sdphy_sdpads_cmd_oe $or$ls180.v:4343$625_Y
+ connect \main_sdphy_sdpads_cmd_o $or$ls180.v:4344$629_Y
+ connect \main_sdphy_sdpads_data_oe $or$ls180.v:4345$633_Y
+ connect \main_sdphy_sdpads_data_o $or$ls180.v:4346$637_Y
connect \main_sdphy_init_pads_out_ready \main_sdphy_clocker_ce
connect \main_sdphy_cmdw_pads_out_ready \main_sdphy_clocker_ce
connect \main_sdphy_cmdr_pads_out_ready \main_sdphy_clocker_ce
connect \main_sdphy_datar_pads_in_pads_in_valid \main_sdphy_clocker_ce
connect \main_sdphy_datar_pads_in_pads_in_payload_cmd_i \main_sdphy_sdpads_cmd_i
connect \main_sdphy_datar_pads_in_pads_in_payload_data_i \main_sdphy_sdpads_data_i
- connect \main_sdphy_clocker_stop $or$ls180.v:4371$638_Y
- connect \main_sdphy_clocker_ce $and$ls180.v:4401$641_Y
+ connect \main_sdphy_clocker_stop $or$ls180.v:4367$638_Y
+ connect \main_sdphy_clocker_ce $and$ls180.v:4397$641_Y
connect \main_sdphy_cmdr_cmdr_pads_in_valid \main_sdphy_cmdr_pads_in_pads_in_valid
connect \main_sdphy_cmdr_pads_in_pads_in_ready \main_sdphy_cmdr_cmdr_pads_in_ready
connect \main_sdphy_cmdr_cmdr_pads_in_first \main_sdphy_cmdr_pads_in_pads_in_first
connect \main_sdphy_cmdr_cmdr_pads_in_payload_data_i \main_sdphy_cmdr_pads_in_pads_in_payload_data_i
connect \main_sdphy_cmdr_cmdr_pads_in_payload_data_o \main_sdphy_cmdr_pads_in_pads_in_payload_data_o
connect \main_sdphy_cmdr_cmdr_pads_in_payload_data_oe \main_sdphy_cmdr_pads_in_pads_in_payload_data_oe
- connect \main_sdphy_cmdr_cmdr_start $eq$ls180.v:4524$651_Y
- connect \main_sdphy_cmdr_cmdr_converter_sink_valid $and$ls180.v:4525$653_Y
+ connect \main_sdphy_cmdr_cmdr_start $eq$ls180.v:4520$651_Y
+ connect \main_sdphy_cmdr_cmdr_converter_sink_valid $and$ls180.v:4521$653_Y
connect \main_sdphy_cmdr_cmdr_converter_sink_payload_data \main_sdphy_cmdr_cmdr_pads_in_payload_cmd_i
connect \main_sdphy_cmdr_cmdr_buf_sink_valid \main_sdphy_cmdr_cmdr_source_source_valid1
connect \main_sdphy_cmdr_cmdr_source_source_ready1 \main_sdphy_cmdr_cmdr_buf_sink_ready
connect \main_sdphy_cmdr_cmdr_source_source_first1 \main_sdphy_cmdr_cmdr_converter_source_first
connect \main_sdphy_cmdr_cmdr_source_source_last1 \main_sdphy_cmdr_cmdr_converter_source_last
connect \main_sdphy_cmdr_cmdr_source_source_payload_data1 \main_sdphy_cmdr_cmdr_converter_source_payload_data
- connect \main_sdphy_cmdr_cmdr_converter_sink_ready $or$ls180.v:4542$655_Y
+ connect \main_sdphy_cmdr_cmdr_converter_sink_ready $or$ls180.v:4538$655_Y
connect \main_sdphy_cmdr_cmdr_converter_source_valid \main_sdphy_cmdr_cmdr_converter_strobe_all
- connect \main_sdphy_cmdr_cmdr_converter_load_part $and$ls180.v:4544$656_Y
- connect \main_sdphy_cmdr_cmdr_buf_sink_ready $or$ls180.v:4545$658_Y
+ connect \main_sdphy_cmdr_cmdr_converter_load_part $and$ls180.v:4540$656_Y
+ connect \main_sdphy_cmdr_cmdr_buf_sink_ready $or$ls180.v:4541$658_Y
connect \main_sdphy_dataw_crcr_pads_in_valid \main_sdphy_dataw_pads_in_pads_in_valid
connect \main_sdphy_dataw_pads_in_pads_in_ready \main_sdphy_dataw_crcr_pads_in_ready
connect \main_sdphy_dataw_crcr_pads_in_first \main_sdphy_dataw_pads_in_pads_in_first
connect \main_sdphy_dataw_crcr_pads_in_payload_data_i \main_sdphy_dataw_pads_in_pads_in_payload_data_i
connect \main_sdphy_dataw_crcr_pads_in_payload_data_o \main_sdphy_dataw_pads_in_pads_in_payload_data_o
connect \main_sdphy_dataw_crcr_pads_in_payload_data_oe \main_sdphy_dataw_pads_in_pads_in_payload_data_oe
- connect \main_sdphy_dataw_crcr_start $eq$ls180.v:4651$673_Y
- connect \main_sdphy_dataw_crcr_converter_sink_valid $and$ls180.v:4652$674_Y
+ connect \main_sdphy_dataw_crcr_start $eq$ls180.v:4647$673_Y
+ connect \main_sdphy_dataw_crcr_converter_sink_valid $and$ls180.v:4648$674_Y
connect \main_sdphy_dataw_crcr_converter_sink_payload_data \main_sdphy_dataw_crcr_pads_in_payload_data_i [0]
connect \main_sdphy_dataw_crcr_buf_sink_valid \main_sdphy_dataw_crcr_source_source_valid1
connect \main_sdphy_dataw_crcr_source_source_ready1 \main_sdphy_dataw_crcr_buf_sink_ready
connect \main_sdphy_dataw_crcr_source_source_first1 \main_sdphy_dataw_crcr_converter_source_first
connect \main_sdphy_dataw_crcr_source_source_last1 \main_sdphy_dataw_crcr_converter_source_last
connect \main_sdphy_dataw_crcr_source_source_payload_data1 \main_sdphy_dataw_crcr_converter_source_payload_data
- connect \main_sdphy_dataw_crcr_converter_sink_ready $or$ls180.v:4669$676_Y
+ connect \main_sdphy_dataw_crcr_converter_sink_ready $or$ls180.v:4665$676_Y
connect \main_sdphy_dataw_crcr_converter_source_valid \main_sdphy_dataw_crcr_converter_strobe_all
- connect \main_sdphy_dataw_crcr_converter_load_part $and$ls180.v:4671$677_Y
- connect \main_sdphy_dataw_crcr_buf_sink_ready $or$ls180.v:4672$679_Y
+ connect \main_sdphy_dataw_crcr_converter_load_part $and$ls180.v:4667$677_Y
+ connect \main_sdphy_dataw_crcr_buf_sink_ready $or$ls180.v:4668$679_Y
connect \main_sdphy_datar_datar_pads_in_valid \main_sdphy_datar_pads_in_pads_in_valid
connect \main_sdphy_datar_pads_in_pads_in_ready \main_sdphy_datar_datar_pads_in_ready
connect \main_sdphy_datar_datar_pads_in_first \main_sdphy_datar_pads_in_pads_in_first
connect \main_sdphy_datar_datar_pads_in_payload_data_i \main_sdphy_datar_pads_in_pads_in_payload_data_i
connect \main_sdphy_datar_datar_pads_in_payload_data_o \main_sdphy_datar_pads_in_pads_in_payload_data_o
connect \main_sdphy_datar_datar_pads_in_payload_data_oe \main_sdphy_datar_pads_in_pads_in_payload_data_oe
- connect \main_sdphy_datar_datar_start $eq$ls180.v:4785$688_Y
- connect \main_sdphy_datar_datar_converter_sink_valid $and$ls180.v:4786$689_Y
+ connect \main_sdphy_datar_datar_start $eq$ls180.v:4781$688_Y
+ connect \main_sdphy_datar_datar_converter_sink_valid $and$ls180.v:4782$689_Y
connect \main_sdphy_datar_datar_converter_sink_payload_data \main_sdphy_datar_datar_pads_in_payload_data_i
connect \main_sdphy_datar_datar_buf_sink_valid \main_sdphy_datar_datar_source_source_valid1
connect \main_sdphy_datar_datar_source_source_ready1 \main_sdphy_datar_datar_buf_sink_ready
connect \main_sdphy_datar_datar_source_source_first1 \main_sdphy_datar_datar_converter_source_first
connect \main_sdphy_datar_datar_source_source_last1 \main_sdphy_datar_datar_converter_source_last
connect \main_sdphy_datar_datar_source_source_payload_data1 \main_sdphy_datar_datar_converter_source_payload_data
- connect \main_sdphy_datar_datar_converter_sink_ready $or$ls180.v:4803$691_Y
+ connect \main_sdphy_datar_datar_converter_sink_ready $or$ls180.v:4799$691_Y
connect \main_sdphy_datar_datar_converter_source_valid \main_sdphy_datar_datar_converter_strobe_all
- connect \main_sdphy_datar_datar_converter_load_part $and$ls180.v:4805$692_Y
- connect \main_sdphy_datar_datar_buf_sink_ready $or$ls180.v:4806$694_Y
+ connect \main_sdphy_datar_datar_converter_load_part $and$ls180.v:4801$692_Y
+ connect \main_sdphy_datar_datar_buf_sink_ready $or$ls180.v:4802$694_Y
connect \main_sdcore_crc16_inserter_sink_valid \main_sdcore_sink_sink_valid
connect \main_sdcore_sink_sink_ready \main_sdcore_crc16_inserter_sink_ready
connect \main_sdcore_crc16_inserter_sink_first \main_sdcore_sink_sink_first
connect \main_sdcore_cmd_type \main_sdcore_cmd_command_storage [1:0]
connect \main_sdcore_data_type \main_sdcore_cmd_command_storage [6:5]
connect \main_sdcore_cmd_event_status { 1'0 \main_sdcore_cmd_timeout \main_sdcore_cmd_error \main_sdcore_cmd_done }
- connect \main_sdcore_data_event_status { $not$ls180.v:4922$709_Y \main_sdcore_data_timeout \main_sdcore_data_error \main_sdcore_data_done }
+ connect \main_sdcore_data_event_status { $not$ls180.v:4918$709_Y \main_sdcore_data_timeout \main_sdcore_data_error \main_sdcore_data_done }
connect \main_sdcore_crc7_inserter_val { 2'01 \main_sdcore_cmd_command_storage [13:8] \main_sdcore_cmd_argument_storage }
connect \main_sdcore_crc7_inserter_clr 1'1
connect \main_sdcore_crc7_inserter_enable 1'1
- connect \main_sdcore_crc7_inserter_crcreg1 { \main_sdcore_crc7_inserter_crcreg0 [5:3] $xor$ls180.v:4926$712_Y \main_sdcore_crc7_inserter_crcreg0 [1:0] $xor$ls180.v:4926$710_Y }
- connect \main_sdcore_crc7_inserter_crcreg2 { \main_sdcore_crc7_inserter_crcreg1 [5:3] $xor$ls180.v:4927$715_Y \main_sdcore_crc7_inserter_crcreg1 [1:0] $xor$ls180.v:4927$713_Y }
- connect \main_sdcore_crc7_inserter_crcreg3 { \main_sdcore_crc7_inserter_crcreg2 [5:3] $xor$ls180.v:4928$718_Y \main_sdcore_crc7_inserter_crcreg2 [1:0] $xor$ls180.v:4928$716_Y }
- connect \main_sdcore_crc7_inserter_crcreg4 { \main_sdcore_crc7_inserter_crcreg3 [5:3] $xor$ls180.v:4929$721_Y \main_sdcore_crc7_inserter_crcreg3 [1:0] $xor$ls180.v:4929$719_Y }
- connect \main_sdcore_crc7_inserter_crcreg5 { \main_sdcore_crc7_inserter_crcreg4 [5:3] $xor$ls180.v:4930$724_Y \main_sdcore_crc7_inserter_crcreg4 [1:0] $xor$ls180.v:4930$722_Y }
- connect \main_sdcore_crc7_inserter_crcreg6 { \main_sdcore_crc7_inserter_crcreg5 [5:3] $xor$ls180.v:4931$727_Y \main_sdcore_crc7_inserter_crcreg5 [1:0] $xor$ls180.v:4931$725_Y }
- connect \main_sdcore_crc7_inserter_crcreg7 { \main_sdcore_crc7_inserter_crcreg6 [5:3] $xor$ls180.v:4932$730_Y \main_sdcore_crc7_inserter_crcreg6 [1:0] $xor$ls180.v:4932$728_Y }
- connect \main_sdcore_crc7_inserter_crcreg8 { \main_sdcore_crc7_inserter_crcreg7 [5:3] $xor$ls180.v:4933$733_Y \main_sdcore_crc7_inserter_crcreg7 [1:0] $xor$ls180.v:4933$731_Y }
- connect \main_sdcore_crc7_inserter_crcreg9 { \main_sdcore_crc7_inserter_crcreg8 [5:3] $xor$ls180.v:4934$736_Y \main_sdcore_crc7_inserter_crcreg8 [1:0] $xor$ls180.v:4934$734_Y }
- connect \main_sdcore_crc7_inserter_crcreg10 { \main_sdcore_crc7_inserter_crcreg9 [5:3] $xor$ls180.v:4935$739_Y \main_sdcore_crc7_inserter_crcreg9 [1:0] $xor$ls180.v:4935$737_Y }
- connect \main_sdcore_crc7_inserter_crcreg11 { \main_sdcore_crc7_inserter_crcreg10 [5:3] $xor$ls180.v:4936$742_Y \main_sdcore_crc7_inserter_crcreg10 [1:0] $xor$ls180.v:4936$740_Y }
- connect \main_sdcore_crc7_inserter_crcreg12 { \main_sdcore_crc7_inserter_crcreg11 [5:3] $xor$ls180.v:4937$745_Y \main_sdcore_crc7_inserter_crcreg11 [1:0] $xor$ls180.v:4937$743_Y }
- connect \main_sdcore_crc7_inserter_crcreg13 { \main_sdcore_crc7_inserter_crcreg12 [5:3] $xor$ls180.v:4938$748_Y \main_sdcore_crc7_inserter_crcreg12 [1:0] $xor$ls180.v:4938$746_Y }
- connect \main_sdcore_crc7_inserter_crcreg14 { \main_sdcore_crc7_inserter_crcreg13 [5:3] $xor$ls180.v:4939$751_Y \main_sdcore_crc7_inserter_crcreg13 [1:0] $xor$ls180.v:4939$749_Y }
- connect \main_sdcore_crc7_inserter_crcreg15 { \main_sdcore_crc7_inserter_crcreg14 [5:3] $xor$ls180.v:4940$754_Y \main_sdcore_crc7_inserter_crcreg14 [1:0] $xor$ls180.v:4940$752_Y }
- connect \main_sdcore_crc7_inserter_crcreg16 { \main_sdcore_crc7_inserter_crcreg15 [5:3] $xor$ls180.v:4941$757_Y \main_sdcore_crc7_inserter_crcreg15 [1:0] $xor$ls180.v:4941$755_Y }
- connect \main_sdcore_crc7_inserter_crcreg17 { \main_sdcore_crc7_inserter_crcreg16 [5:3] $xor$ls180.v:4942$760_Y \main_sdcore_crc7_inserter_crcreg16 [1:0] $xor$ls180.v:4942$758_Y }
- connect \main_sdcore_crc7_inserter_crcreg18 { \main_sdcore_crc7_inserter_crcreg17 [5:3] $xor$ls180.v:4943$763_Y \main_sdcore_crc7_inserter_crcreg17 [1:0] $xor$ls180.v:4943$761_Y }
- connect \main_sdcore_crc7_inserter_crcreg19 { \main_sdcore_crc7_inserter_crcreg18 [5:3] $xor$ls180.v:4944$766_Y \main_sdcore_crc7_inserter_crcreg18 [1:0] $xor$ls180.v:4944$764_Y }
- connect \main_sdcore_crc7_inserter_crcreg20 { \main_sdcore_crc7_inserter_crcreg19 [5:3] $xor$ls180.v:4945$769_Y \main_sdcore_crc7_inserter_crcreg19 [1:0] $xor$ls180.v:4945$767_Y }
- connect \main_sdcore_crc7_inserter_crcreg21 { \main_sdcore_crc7_inserter_crcreg20 [5:3] $xor$ls180.v:4946$772_Y \main_sdcore_crc7_inserter_crcreg20 [1:0] $xor$ls180.v:4946$770_Y }
- connect \main_sdcore_crc7_inserter_crcreg22 { \main_sdcore_crc7_inserter_crcreg21 [5:3] $xor$ls180.v:4947$775_Y \main_sdcore_crc7_inserter_crcreg21 [1:0] $xor$ls180.v:4947$773_Y }
- connect \main_sdcore_crc7_inserter_crcreg23 { \main_sdcore_crc7_inserter_crcreg22 [5:3] $xor$ls180.v:4948$778_Y \main_sdcore_crc7_inserter_crcreg22 [1:0] $xor$ls180.v:4948$776_Y }
- connect \main_sdcore_crc7_inserter_crcreg24 { \main_sdcore_crc7_inserter_crcreg23 [5:3] $xor$ls180.v:4949$781_Y \main_sdcore_crc7_inserter_crcreg23 [1:0] $xor$ls180.v:4949$779_Y }
- connect \main_sdcore_crc7_inserter_crcreg25 { \main_sdcore_crc7_inserter_crcreg24 [5:3] $xor$ls180.v:4950$784_Y \main_sdcore_crc7_inserter_crcreg24 [1:0] $xor$ls180.v:4950$782_Y }
- connect \main_sdcore_crc7_inserter_crcreg26 { \main_sdcore_crc7_inserter_crcreg25 [5:3] $xor$ls180.v:4951$787_Y \main_sdcore_crc7_inserter_crcreg25 [1:0] $xor$ls180.v:4951$785_Y }
- connect \main_sdcore_crc7_inserter_crcreg27 { \main_sdcore_crc7_inserter_crcreg26 [5:3] $xor$ls180.v:4952$790_Y \main_sdcore_crc7_inserter_crcreg26 [1:0] $xor$ls180.v:4952$788_Y }
- connect \main_sdcore_crc7_inserter_crcreg28 { \main_sdcore_crc7_inserter_crcreg27 [5:3] $xor$ls180.v:4953$793_Y \main_sdcore_crc7_inserter_crcreg27 [1:0] $xor$ls180.v:4953$791_Y }
- connect \main_sdcore_crc7_inserter_crcreg29 { \main_sdcore_crc7_inserter_crcreg28 [5:3] $xor$ls180.v:4954$796_Y \main_sdcore_crc7_inserter_crcreg28 [1:0] $xor$ls180.v:4954$794_Y }
- connect \main_sdcore_crc7_inserter_crcreg30 { \main_sdcore_crc7_inserter_crcreg29 [5:3] $xor$ls180.v:4955$799_Y \main_sdcore_crc7_inserter_crcreg29 [1:0] $xor$ls180.v:4955$797_Y }
- connect \main_sdcore_crc7_inserter_crcreg31 { \main_sdcore_crc7_inserter_crcreg30 [5:3] $xor$ls180.v:4956$802_Y \main_sdcore_crc7_inserter_crcreg30 [1:0] $xor$ls180.v:4956$800_Y }
- connect \main_sdcore_crc7_inserter_crcreg32 { \main_sdcore_crc7_inserter_crcreg31 [5:3] $xor$ls180.v:4957$805_Y \main_sdcore_crc7_inserter_crcreg31 [1:0] $xor$ls180.v:4957$803_Y }
- connect \main_sdcore_crc7_inserter_crcreg33 { \main_sdcore_crc7_inserter_crcreg32 [5:3] $xor$ls180.v:4958$808_Y \main_sdcore_crc7_inserter_crcreg32 [1:0] $xor$ls180.v:4958$806_Y }
- connect \main_sdcore_crc7_inserter_crcreg34 { \main_sdcore_crc7_inserter_crcreg33 [5:3] $xor$ls180.v:4959$811_Y \main_sdcore_crc7_inserter_crcreg33 [1:0] $xor$ls180.v:4959$809_Y }
- connect \main_sdcore_crc7_inserter_crcreg35 { \main_sdcore_crc7_inserter_crcreg34 [5:3] $xor$ls180.v:4960$814_Y \main_sdcore_crc7_inserter_crcreg34 [1:0] $xor$ls180.v:4960$812_Y }
- connect \main_sdcore_crc7_inserter_crcreg36 { \main_sdcore_crc7_inserter_crcreg35 [5:3] $xor$ls180.v:4961$817_Y \main_sdcore_crc7_inserter_crcreg35 [1:0] $xor$ls180.v:4961$815_Y }
- connect \main_sdcore_crc7_inserter_crcreg37 { \main_sdcore_crc7_inserter_crcreg36 [5:3] $xor$ls180.v:4962$820_Y \main_sdcore_crc7_inserter_crcreg36 [1:0] $xor$ls180.v:4962$818_Y }
- connect \main_sdcore_crc7_inserter_crcreg38 { \main_sdcore_crc7_inserter_crcreg37 [5:3] $xor$ls180.v:4963$823_Y \main_sdcore_crc7_inserter_crcreg37 [1:0] $xor$ls180.v:4963$821_Y }
- connect \main_sdcore_crc7_inserter_crcreg39 { \main_sdcore_crc7_inserter_crcreg38 [5:3] $xor$ls180.v:4964$826_Y \main_sdcore_crc7_inserter_crcreg38 [1:0] $xor$ls180.v:4964$824_Y }
- connect \main_sdcore_crc7_inserter_crcreg40 { \main_sdcore_crc7_inserter_crcreg39 [5:3] $xor$ls180.v:4965$829_Y \main_sdcore_crc7_inserter_crcreg39 [1:0] $xor$ls180.v:4965$827_Y }
+ connect \main_sdcore_crc7_inserter_crcreg1 { \main_sdcore_crc7_inserter_crcreg0 [5:3] $xor$ls180.v:4922$712_Y \main_sdcore_crc7_inserter_crcreg0 [1:0] $xor$ls180.v:4922$710_Y }
+ connect \main_sdcore_crc7_inserter_crcreg2 { \main_sdcore_crc7_inserter_crcreg1 [5:3] $xor$ls180.v:4923$715_Y \main_sdcore_crc7_inserter_crcreg1 [1:0] $xor$ls180.v:4923$713_Y }
+ connect \main_sdcore_crc7_inserter_crcreg3 { \main_sdcore_crc7_inserter_crcreg2 [5:3] $xor$ls180.v:4924$718_Y \main_sdcore_crc7_inserter_crcreg2 [1:0] $xor$ls180.v:4924$716_Y }
+ connect \main_sdcore_crc7_inserter_crcreg4 { \main_sdcore_crc7_inserter_crcreg3 [5:3] $xor$ls180.v:4925$721_Y \main_sdcore_crc7_inserter_crcreg3 [1:0] $xor$ls180.v:4925$719_Y }
+ connect \main_sdcore_crc7_inserter_crcreg5 { \main_sdcore_crc7_inserter_crcreg4 [5:3] $xor$ls180.v:4926$724_Y \main_sdcore_crc7_inserter_crcreg4 [1:0] $xor$ls180.v:4926$722_Y }
+ connect \main_sdcore_crc7_inserter_crcreg6 { \main_sdcore_crc7_inserter_crcreg5 [5:3] $xor$ls180.v:4927$727_Y \main_sdcore_crc7_inserter_crcreg5 [1:0] $xor$ls180.v:4927$725_Y }
+ connect \main_sdcore_crc7_inserter_crcreg7 { \main_sdcore_crc7_inserter_crcreg6 [5:3] $xor$ls180.v:4928$730_Y \main_sdcore_crc7_inserter_crcreg6 [1:0] $xor$ls180.v:4928$728_Y }
+ connect \main_sdcore_crc7_inserter_crcreg8 { \main_sdcore_crc7_inserter_crcreg7 [5:3] $xor$ls180.v:4929$733_Y \main_sdcore_crc7_inserter_crcreg7 [1:0] $xor$ls180.v:4929$731_Y }
+ connect \main_sdcore_crc7_inserter_crcreg9 { \main_sdcore_crc7_inserter_crcreg8 [5:3] $xor$ls180.v:4930$736_Y \main_sdcore_crc7_inserter_crcreg8 [1:0] $xor$ls180.v:4930$734_Y }
+ connect \main_sdcore_crc7_inserter_crcreg10 { \main_sdcore_crc7_inserter_crcreg9 [5:3] $xor$ls180.v:4931$739_Y \main_sdcore_crc7_inserter_crcreg9 [1:0] $xor$ls180.v:4931$737_Y }
+ connect \main_sdcore_crc7_inserter_crcreg11 { \main_sdcore_crc7_inserter_crcreg10 [5:3] $xor$ls180.v:4932$742_Y \main_sdcore_crc7_inserter_crcreg10 [1:0] $xor$ls180.v:4932$740_Y }
+ connect \main_sdcore_crc7_inserter_crcreg12 { \main_sdcore_crc7_inserter_crcreg11 [5:3] $xor$ls180.v:4933$745_Y \main_sdcore_crc7_inserter_crcreg11 [1:0] $xor$ls180.v:4933$743_Y }
+ connect \main_sdcore_crc7_inserter_crcreg13 { \main_sdcore_crc7_inserter_crcreg12 [5:3] $xor$ls180.v:4934$748_Y \main_sdcore_crc7_inserter_crcreg12 [1:0] $xor$ls180.v:4934$746_Y }
+ connect \main_sdcore_crc7_inserter_crcreg14 { \main_sdcore_crc7_inserter_crcreg13 [5:3] $xor$ls180.v:4935$751_Y \main_sdcore_crc7_inserter_crcreg13 [1:0] $xor$ls180.v:4935$749_Y }
+ connect \main_sdcore_crc7_inserter_crcreg15 { \main_sdcore_crc7_inserter_crcreg14 [5:3] $xor$ls180.v:4936$754_Y \main_sdcore_crc7_inserter_crcreg14 [1:0] $xor$ls180.v:4936$752_Y }
+ connect \main_sdcore_crc7_inserter_crcreg16 { \main_sdcore_crc7_inserter_crcreg15 [5:3] $xor$ls180.v:4937$757_Y \main_sdcore_crc7_inserter_crcreg15 [1:0] $xor$ls180.v:4937$755_Y }
+ connect \main_sdcore_crc7_inserter_crcreg17 { \main_sdcore_crc7_inserter_crcreg16 [5:3] $xor$ls180.v:4938$760_Y \main_sdcore_crc7_inserter_crcreg16 [1:0] $xor$ls180.v:4938$758_Y }
+ connect \main_sdcore_crc7_inserter_crcreg18 { \main_sdcore_crc7_inserter_crcreg17 [5:3] $xor$ls180.v:4939$763_Y \main_sdcore_crc7_inserter_crcreg17 [1:0] $xor$ls180.v:4939$761_Y }
+ connect \main_sdcore_crc7_inserter_crcreg19 { \main_sdcore_crc7_inserter_crcreg18 [5:3] $xor$ls180.v:4940$766_Y \main_sdcore_crc7_inserter_crcreg18 [1:0] $xor$ls180.v:4940$764_Y }
+ connect \main_sdcore_crc7_inserter_crcreg20 { \main_sdcore_crc7_inserter_crcreg19 [5:3] $xor$ls180.v:4941$769_Y \main_sdcore_crc7_inserter_crcreg19 [1:0] $xor$ls180.v:4941$767_Y }
+ connect \main_sdcore_crc7_inserter_crcreg21 { \main_sdcore_crc7_inserter_crcreg20 [5:3] $xor$ls180.v:4942$772_Y \main_sdcore_crc7_inserter_crcreg20 [1:0] $xor$ls180.v:4942$770_Y }
+ connect \main_sdcore_crc7_inserter_crcreg22 { \main_sdcore_crc7_inserter_crcreg21 [5:3] $xor$ls180.v:4943$775_Y \main_sdcore_crc7_inserter_crcreg21 [1:0] $xor$ls180.v:4943$773_Y }
+ connect \main_sdcore_crc7_inserter_crcreg23 { \main_sdcore_crc7_inserter_crcreg22 [5:3] $xor$ls180.v:4944$778_Y \main_sdcore_crc7_inserter_crcreg22 [1:0] $xor$ls180.v:4944$776_Y }
+ connect \main_sdcore_crc7_inserter_crcreg24 { \main_sdcore_crc7_inserter_crcreg23 [5:3] $xor$ls180.v:4945$781_Y \main_sdcore_crc7_inserter_crcreg23 [1:0] $xor$ls180.v:4945$779_Y }
+ connect \main_sdcore_crc7_inserter_crcreg25 { \main_sdcore_crc7_inserter_crcreg24 [5:3] $xor$ls180.v:4946$784_Y \main_sdcore_crc7_inserter_crcreg24 [1:0] $xor$ls180.v:4946$782_Y }
+ connect \main_sdcore_crc7_inserter_crcreg26 { \main_sdcore_crc7_inserter_crcreg25 [5:3] $xor$ls180.v:4947$787_Y \main_sdcore_crc7_inserter_crcreg25 [1:0] $xor$ls180.v:4947$785_Y }
+ connect \main_sdcore_crc7_inserter_crcreg27 { \main_sdcore_crc7_inserter_crcreg26 [5:3] $xor$ls180.v:4948$790_Y \main_sdcore_crc7_inserter_crcreg26 [1:0] $xor$ls180.v:4948$788_Y }
+ connect \main_sdcore_crc7_inserter_crcreg28 { \main_sdcore_crc7_inserter_crcreg27 [5:3] $xor$ls180.v:4949$793_Y \main_sdcore_crc7_inserter_crcreg27 [1:0] $xor$ls180.v:4949$791_Y }
+ connect \main_sdcore_crc7_inserter_crcreg29 { \main_sdcore_crc7_inserter_crcreg28 [5:3] $xor$ls180.v:4950$796_Y \main_sdcore_crc7_inserter_crcreg28 [1:0] $xor$ls180.v:4950$794_Y }
+ connect \main_sdcore_crc7_inserter_crcreg30 { \main_sdcore_crc7_inserter_crcreg29 [5:3] $xor$ls180.v:4951$799_Y \main_sdcore_crc7_inserter_crcreg29 [1:0] $xor$ls180.v:4951$797_Y }
+ connect \main_sdcore_crc7_inserter_crcreg31 { \main_sdcore_crc7_inserter_crcreg30 [5:3] $xor$ls180.v:4952$802_Y \main_sdcore_crc7_inserter_crcreg30 [1:0] $xor$ls180.v:4952$800_Y }
+ connect \main_sdcore_crc7_inserter_crcreg32 { \main_sdcore_crc7_inserter_crcreg31 [5:3] $xor$ls180.v:4953$805_Y \main_sdcore_crc7_inserter_crcreg31 [1:0] $xor$ls180.v:4953$803_Y }
+ connect \main_sdcore_crc7_inserter_crcreg33 { \main_sdcore_crc7_inserter_crcreg32 [5:3] $xor$ls180.v:4954$808_Y \main_sdcore_crc7_inserter_crcreg32 [1:0] $xor$ls180.v:4954$806_Y }
+ connect \main_sdcore_crc7_inserter_crcreg34 { \main_sdcore_crc7_inserter_crcreg33 [5:3] $xor$ls180.v:4955$811_Y \main_sdcore_crc7_inserter_crcreg33 [1:0] $xor$ls180.v:4955$809_Y }
+ connect \main_sdcore_crc7_inserter_crcreg35 { \main_sdcore_crc7_inserter_crcreg34 [5:3] $xor$ls180.v:4956$814_Y \main_sdcore_crc7_inserter_crcreg34 [1:0] $xor$ls180.v:4956$812_Y }
+ connect \main_sdcore_crc7_inserter_crcreg36 { \main_sdcore_crc7_inserter_crcreg35 [5:3] $xor$ls180.v:4957$817_Y \main_sdcore_crc7_inserter_crcreg35 [1:0] $xor$ls180.v:4957$815_Y }
+ connect \main_sdcore_crc7_inserter_crcreg37 { \main_sdcore_crc7_inserter_crcreg36 [5:3] $xor$ls180.v:4958$820_Y \main_sdcore_crc7_inserter_crcreg36 [1:0] $xor$ls180.v:4958$818_Y }
+ connect \main_sdcore_crc7_inserter_crcreg38 { \main_sdcore_crc7_inserter_crcreg37 [5:3] $xor$ls180.v:4959$823_Y \main_sdcore_crc7_inserter_crcreg37 [1:0] $xor$ls180.v:4959$821_Y }
+ connect \main_sdcore_crc7_inserter_crcreg39 { \main_sdcore_crc7_inserter_crcreg38 [5:3] $xor$ls180.v:4960$826_Y \main_sdcore_crc7_inserter_crcreg38 [1:0] $xor$ls180.v:4960$824_Y }
+ connect \main_sdcore_crc7_inserter_crcreg40 { \main_sdcore_crc7_inserter_crcreg39 [5:3] $xor$ls180.v:4961$829_Y \main_sdcore_crc7_inserter_crcreg39 [1:0] $xor$ls180.v:4961$827_Y }
connect \main_sdcore_crc16_inserter_crc0_val { \main_sdcore_crc16_inserter_sink_payload_data [4] \main_sdcore_crc16_inserter_sink_payload_data [0] }
- connect \main_sdcore_crc16_inserter_crc0_clr $and$ls180.v:4975$832_Y
- connect \main_sdcore_crc16_inserter_crc0_enable $and$ls180.v:4976$833_Y
+ connect \main_sdcore_crc16_inserter_crc0_clr $and$ls180.v:4971$832_Y
+ connect \main_sdcore_crc16_inserter_crc0_enable $and$ls180.v:4972$833_Y
connect \main_sdcore_crc16_inserter_crc1_val { \main_sdcore_crc16_inserter_sink_payload_data [5] \main_sdcore_crc16_inserter_sink_payload_data [1] }
- connect \main_sdcore_crc16_inserter_crc1_clr $and$ls180.v:4978$835_Y
- connect \main_sdcore_crc16_inserter_crc1_enable $and$ls180.v:4979$836_Y
+ connect \main_sdcore_crc16_inserter_crc1_clr $and$ls180.v:4974$835_Y
+ connect \main_sdcore_crc16_inserter_crc1_enable $and$ls180.v:4975$836_Y
connect \main_sdcore_crc16_inserter_crc2_val { \main_sdcore_crc16_inserter_sink_payload_data [6] \main_sdcore_crc16_inserter_sink_payload_data [2] }
- connect \main_sdcore_crc16_inserter_crc2_clr $and$ls180.v:4981$838_Y
- connect \main_sdcore_crc16_inserter_crc2_enable $and$ls180.v:4982$839_Y
+ connect \main_sdcore_crc16_inserter_crc2_clr $and$ls180.v:4977$838_Y
+ connect \main_sdcore_crc16_inserter_crc2_enable $and$ls180.v:4978$839_Y
connect \main_sdcore_crc16_inserter_crc3_val { \main_sdcore_crc16_inserter_sink_payload_data [7] \main_sdcore_crc16_inserter_sink_payload_data [3] }
- connect \main_sdcore_crc16_inserter_crc3_clr $and$ls180.v:4984$841_Y
- connect \main_sdcore_crc16_inserter_crc3_enable $and$ls180.v:4985$842_Y
- connect \main_sdcore_crc16_inserter_crc0_crcreg1 { \main_sdcore_crc16_inserter_crc0_crcreg0 [14:12] $xor$ls180.v:4986$847_Y \main_sdcore_crc16_inserter_crc0_crcreg0 [10:5] $xor$ls180.v:4986$845_Y \main_sdcore_crc16_inserter_crc0_crcreg0 [3:0] $xor$ls180.v:4986$843_Y }
- connect \main_sdcore_crc16_inserter_crc0_crcreg2 { \main_sdcore_crc16_inserter_crc0_crcreg1 [14:12] $xor$ls180.v:4987$852_Y \main_sdcore_crc16_inserter_crc0_crcreg1 [10:5] $xor$ls180.v:4987$850_Y \main_sdcore_crc16_inserter_crc0_crcreg1 [3:0] $xor$ls180.v:4987$848_Y }
- connect \main_sdcore_crc16_inserter_crc1_crcreg1 { \main_sdcore_crc16_inserter_crc1_crcreg0 [14:12] $xor$ls180.v:4996$858_Y \main_sdcore_crc16_inserter_crc1_crcreg0 [10:5] $xor$ls180.v:4996$856_Y \main_sdcore_crc16_inserter_crc1_crcreg0 [3:0] $xor$ls180.v:4996$854_Y }
- connect \main_sdcore_crc16_inserter_crc1_crcreg2 { \main_sdcore_crc16_inserter_crc1_crcreg1 [14:12] $xor$ls180.v:4997$863_Y \main_sdcore_crc16_inserter_crc1_crcreg1 [10:5] $xor$ls180.v:4997$861_Y \main_sdcore_crc16_inserter_crc1_crcreg1 [3:0] $xor$ls180.v:4997$859_Y }
- connect \main_sdcore_crc16_inserter_crc2_crcreg1 { \main_sdcore_crc16_inserter_crc2_crcreg0 [14:12] $xor$ls180.v:5006$869_Y \main_sdcore_crc16_inserter_crc2_crcreg0 [10:5] $xor$ls180.v:5006$867_Y \main_sdcore_crc16_inserter_crc2_crcreg0 [3:0] $xor$ls180.v:5006$865_Y }
- connect \main_sdcore_crc16_inserter_crc2_crcreg2 { \main_sdcore_crc16_inserter_crc2_crcreg1 [14:12] $xor$ls180.v:5007$874_Y \main_sdcore_crc16_inserter_crc2_crcreg1 [10:5] $xor$ls180.v:5007$872_Y \main_sdcore_crc16_inserter_crc2_crcreg1 [3:0] $xor$ls180.v:5007$870_Y }
- connect \main_sdcore_crc16_inserter_crc3_crcreg1 { \main_sdcore_crc16_inserter_crc3_crcreg0 [14:12] $xor$ls180.v:5016$880_Y \main_sdcore_crc16_inserter_crc3_crcreg0 [10:5] $xor$ls180.v:5016$878_Y \main_sdcore_crc16_inserter_crc3_crcreg0 [3:0] $xor$ls180.v:5016$876_Y }
- connect \main_sdcore_crc16_inserter_crc3_crcreg2 { \main_sdcore_crc16_inserter_crc3_crcreg1 [14:12] $xor$ls180.v:5017$885_Y \main_sdcore_crc16_inserter_crc3_crcreg1 [10:5] $xor$ls180.v:5017$883_Y \main_sdcore_crc16_inserter_crc3_crcreg1 [3:0] $xor$ls180.v:5017$881_Y }
+ connect \main_sdcore_crc16_inserter_crc3_clr $and$ls180.v:4980$841_Y
+ connect \main_sdcore_crc16_inserter_crc3_enable $and$ls180.v:4981$842_Y
+ connect \main_sdcore_crc16_inserter_crc0_crcreg1 { \main_sdcore_crc16_inserter_crc0_crcreg0 [14:12] $xor$ls180.v:4982$847_Y \main_sdcore_crc16_inserter_crc0_crcreg0 [10:5] $xor$ls180.v:4982$845_Y \main_sdcore_crc16_inserter_crc0_crcreg0 [3:0] $xor$ls180.v:4982$843_Y }
+ connect \main_sdcore_crc16_inserter_crc0_crcreg2 { \main_sdcore_crc16_inserter_crc0_crcreg1 [14:12] $xor$ls180.v:4983$852_Y \main_sdcore_crc16_inserter_crc0_crcreg1 [10:5] $xor$ls180.v:4983$850_Y \main_sdcore_crc16_inserter_crc0_crcreg1 [3:0] $xor$ls180.v:4983$848_Y }
+ connect \main_sdcore_crc16_inserter_crc1_crcreg1 { \main_sdcore_crc16_inserter_crc1_crcreg0 [14:12] $xor$ls180.v:4992$858_Y \main_sdcore_crc16_inserter_crc1_crcreg0 [10:5] $xor$ls180.v:4992$856_Y \main_sdcore_crc16_inserter_crc1_crcreg0 [3:0] $xor$ls180.v:4992$854_Y }
+ connect \main_sdcore_crc16_inserter_crc1_crcreg2 { \main_sdcore_crc16_inserter_crc1_crcreg1 [14:12] $xor$ls180.v:4993$863_Y \main_sdcore_crc16_inserter_crc1_crcreg1 [10:5] $xor$ls180.v:4993$861_Y \main_sdcore_crc16_inserter_crc1_crcreg1 [3:0] $xor$ls180.v:4993$859_Y }
+ connect \main_sdcore_crc16_inserter_crc2_crcreg1 { \main_sdcore_crc16_inserter_crc2_crcreg0 [14:12] $xor$ls180.v:5002$869_Y \main_sdcore_crc16_inserter_crc2_crcreg0 [10:5] $xor$ls180.v:5002$867_Y \main_sdcore_crc16_inserter_crc2_crcreg0 [3:0] $xor$ls180.v:5002$865_Y }
+ connect \main_sdcore_crc16_inserter_crc2_crcreg2 { \main_sdcore_crc16_inserter_crc2_crcreg1 [14:12] $xor$ls180.v:5003$874_Y \main_sdcore_crc16_inserter_crc2_crcreg1 [10:5] $xor$ls180.v:5003$872_Y \main_sdcore_crc16_inserter_crc2_crcreg1 [3:0] $xor$ls180.v:5003$870_Y }
+ connect \main_sdcore_crc16_inserter_crc3_crcreg1 { \main_sdcore_crc16_inserter_crc3_crcreg0 [14:12] $xor$ls180.v:5012$880_Y \main_sdcore_crc16_inserter_crc3_crcreg0 [10:5] $xor$ls180.v:5012$878_Y \main_sdcore_crc16_inserter_crc3_crcreg0 [3:0] $xor$ls180.v:5012$876_Y }
+ connect \main_sdcore_crc16_inserter_crc3_crcreg2 { \main_sdcore_crc16_inserter_crc3_crcreg1 [14:12] $xor$ls180.v:5013$885_Y \main_sdcore_crc16_inserter_crc3_crcreg1 [10:5] $xor$ls180.v:5013$883_Y \main_sdcore_crc16_inserter_crc3_crcreg1 [3:0] $xor$ls180.v:5013$881_Y }
connect \main_sdcore_crc16_checker_crc0_val { \main_sdcore_crc16_checker_val [7] \main_sdcore_crc16_checker_val [3] }
- connect \main_sdcore_crc16_checker_crc0_enable $and$ls180.v:5113$901_Y
+ connect \main_sdcore_crc16_checker_crc0_enable $and$ls180.v:5109$901_Y
connect \main_sdcore_crc16_checker_crc1_val { \main_sdcore_crc16_checker_val [6] \main_sdcore_crc16_checker_val [2] }
- connect \main_sdcore_crc16_checker_crc1_enable $and$ls180.v:5123$904_Y
+ connect \main_sdcore_crc16_checker_crc1_enable $and$ls180.v:5119$904_Y
connect \main_sdcore_crc16_checker_crc2_val { \main_sdcore_crc16_checker_val [5] \main_sdcore_crc16_checker_val [1] }
- connect \main_sdcore_crc16_checker_crc2_enable $and$ls180.v:5133$907_Y
+ connect \main_sdcore_crc16_checker_crc2_enable $and$ls180.v:5129$907_Y
connect \main_sdcore_crc16_checker_crc3_val { \main_sdcore_crc16_checker_val [4] \main_sdcore_crc16_checker_val [0] }
- connect \main_sdcore_crc16_checker_crc3_enable $and$ls180.v:5143$910_Y
+ connect \main_sdcore_crc16_checker_crc3_enable $and$ls180.v:5139$910_Y
connect \main_sdcore_crc16_checker_source_payload_data \main_sdcore_crc16_checker_val
connect \main_sdcore_crc16_checker_source_last \main_sdcore_crc16_checker_sink_last
- connect \main_sdcore_crc16_checker_crc0_crcreg1 { \main_sdcore_crc16_checker_crc0_crcreg0 [14:12] $xor$ls180.v:5168$922_Y \main_sdcore_crc16_checker_crc0_crcreg0 [10:5] $xor$ls180.v:5168$920_Y \main_sdcore_crc16_checker_crc0_crcreg0 [3:0] $xor$ls180.v:5168$918_Y }
- connect \main_sdcore_crc16_checker_crc0_crcreg2 { \main_sdcore_crc16_checker_crc0_crcreg1 [14:12] $xor$ls180.v:5169$927_Y \main_sdcore_crc16_checker_crc0_crcreg1 [10:5] $xor$ls180.v:5169$925_Y \main_sdcore_crc16_checker_crc0_crcreg1 [3:0] $xor$ls180.v:5169$923_Y }
- connect \main_sdcore_crc16_checker_crc1_crcreg1 { \main_sdcore_crc16_checker_crc1_crcreg0 [14:12] $xor$ls180.v:5178$933_Y \main_sdcore_crc16_checker_crc1_crcreg0 [10:5] $xor$ls180.v:5178$931_Y \main_sdcore_crc16_checker_crc1_crcreg0 [3:0] $xor$ls180.v:5178$929_Y }
- connect \main_sdcore_crc16_checker_crc1_crcreg2 { \main_sdcore_crc16_checker_crc1_crcreg1 [14:12] $xor$ls180.v:5179$938_Y \main_sdcore_crc16_checker_crc1_crcreg1 [10:5] $xor$ls180.v:5179$936_Y \main_sdcore_crc16_checker_crc1_crcreg1 [3:0] $xor$ls180.v:5179$934_Y }
- connect \main_sdcore_crc16_checker_crc2_crcreg1 { \main_sdcore_crc16_checker_crc2_crcreg0 [14:12] $xor$ls180.v:5188$944_Y \main_sdcore_crc16_checker_crc2_crcreg0 [10:5] $xor$ls180.v:5188$942_Y \main_sdcore_crc16_checker_crc2_crcreg0 [3:0] $xor$ls180.v:5188$940_Y }
- connect \main_sdcore_crc16_checker_crc2_crcreg2 { \main_sdcore_crc16_checker_crc2_crcreg1 [14:12] $xor$ls180.v:5189$949_Y \main_sdcore_crc16_checker_crc2_crcreg1 [10:5] $xor$ls180.v:5189$947_Y \main_sdcore_crc16_checker_crc2_crcreg1 [3:0] $xor$ls180.v:5189$945_Y }
- connect \main_sdcore_crc16_checker_crc3_crcreg1 { \main_sdcore_crc16_checker_crc3_crcreg0 [14:12] $xor$ls180.v:5198$955_Y \main_sdcore_crc16_checker_crc3_crcreg0 [10:5] $xor$ls180.v:5198$953_Y \main_sdcore_crc16_checker_crc3_crcreg0 [3:0] $xor$ls180.v:5198$951_Y }
- connect \main_sdcore_crc16_checker_crc3_crcreg2 { \main_sdcore_crc16_checker_crc3_crcreg1 [14:12] $xor$ls180.v:5199$960_Y \main_sdcore_crc16_checker_crc3_crcreg1 [10:5] $xor$ls180.v:5199$958_Y \main_sdcore_crc16_checker_crc3_crcreg1 [3:0] $xor$ls180.v:5199$956_Y }
+ connect \main_sdcore_crc16_checker_crc0_crcreg1 { \main_sdcore_crc16_checker_crc0_crcreg0 [14:12] $xor$ls180.v:5164$922_Y \main_sdcore_crc16_checker_crc0_crcreg0 [10:5] $xor$ls180.v:5164$920_Y \main_sdcore_crc16_checker_crc0_crcreg0 [3:0] $xor$ls180.v:5164$918_Y }
+ connect \main_sdcore_crc16_checker_crc0_crcreg2 { \main_sdcore_crc16_checker_crc0_crcreg1 [14:12] $xor$ls180.v:5165$927_Y \main_sdcore_crc16_checker_crc0_crcreg1 [10:5] $xor$ls180.v:5165$925_Y \main_sdcore_crc16_checker_crc0_crcreg1 [3:0] $xor$ls180.v:5165$923_Y }
+ connect \main_sdcore_crc16_checker_crc1_crcreg1 { \main_sdcore_crc16_checker_crc1_crcreg0 [14:12] $xor$ls180.v:5174$933_Y \main_sdcore_crc16_checker_crc1_crcreg0 [10:5] $xor$ls180.v:5174$931_Y \main_sdcore_crc16_checker_crc1_crcreg0 [3:0] $xor$ls180.v:5174$929_Y }
+ connect \main_sdcore_crc16_checker_crc1_crcreg2 { \main_sdcore_crc16_checker_crc1_crcreg1 [14:12] $xor$ls180.v:5175$938_Y \main_sdcore_crc16_checker_crc1_crcreg1 [10:5] $xor$ls180.v:5175$936_Y \main_sdcore_crc16_checker_crc1_crcreg1 [3:0] $xor$ls180.v:5175$934_Y }
+ connect \main_sdcore_crc16_checker_crc2_crcreg1 { \main_sdcore_crc16_checker_crc2_crcreg0 [14:12] $xor$ls180.v:5184$944_Y \main_sdcore_crc16_checker_crc2_crcreg0 [10:5] $xor$ls180.v:5184$942_Y \main_sdcore_crc16_checker_crc2_crcreg0 [3:0] $xor$ls180.v:5184$940_Y }
+ connect \main_sdcore_crc16_checker_crc2_crcreg2 { \main_sdcore_crc16_checker_crc2_crcreg1 [14:12] $xor$ls180.v:5185$949_Y \main_sdcore_crc16_checker_crc2_crcreg1 [10:5] $xor$ls180.v:5185$947_Y \main_sdcore_crc16_checker_crc2_crcreg1 [3:0] $xor$ls180.v:5185$945_Y }
+ connect \main_sdcore_crc16_checker_crc3_crcreg1 { \main_sdcore_crc16_checker_crc3_crcreg0 [14:12] $xor$ls180.v:5194$955_Y \main_sdcore_crc16_checker_crc3_crcreg0 [10:5] $xor$ls180.v:5194$953_Y \main_sdcore_crc16_checker_crc3_crcreg0 [3:0] $xor$ls180.v:5194$951_Y }
+ connect \main_sdcore_crc16_checker_crc3_crcreg2 { \main_sdcore_crc16_checker_crc3_crcreg1 [14:12] $xor$ls180.v:5195$960_Y \main_sdcore_crc16_checker_crc3_crcreg1 [10:5] $xor$ls180.v:5195$958_Y \main_sdcore_crc16_checker_crc3_crcreg1 [3:0] $xor$ls180.v:5195$956_Y }
connect \main_sdblock2mem_fifo_sink_valid \main_sdblock2mem_sink_sink_valid0
connect \main_sdblock2mem_sink_sink_ready0 \main_sdblock2mem_fifo_sink_ready
connect \main_sdblock2mem_fifo_sink_first \main_sdblock2mem_sink_sink_first
connect \main_sdblock2mem_fifo_source_payload_data \main_sdblock2mem_fifo_fifo_out_payload_data
connect \main_sdblock2mem_fifo_syncfifo_re \main_sdblock2mem_fifo_source_ready
connect \main_sdblock2mem_fifo_wrport_dat_w \main_sdblock2mem_fifo_syncfifo_din
- connect \main_sdblock2mem_fifo_wrport_we $and$ls180.v:5435$990_Y
- connect \main_sdblock2mem_fifo_do_read $and$ls180.v:5436$991_Y
+ connect \main_sdblock2mem_fifo_wrport_we $and$ls180.v:5431$990_Y
+ connect \main_sdblock2mem_fifo_do_read $and$ls180.v:5432$991_Y
connect \main_sdblock2mem_fifo_rdport_adr \main_sdblock2mem_fifo_consume
connect \main_sdblock2mem_fifo_syncfifo_dout \main_sdblock2mem_fifo_rdport_dat_r
- connect \main_sdblock2mem_fifo_syncfifo_writable $ne$ls180.v:5439$992_Y
- connect \main_sdblock2mem_fifo_syncfifo_readable $ne$ls180.v:5440$993_Y
+ connect \main_sdblock2mem_fifo_syncfifo_writable $ne$ls180.v:5435$992_Y
+ connect \main_sdblock2mem_fifo_syncfifo_readable $ne$ls180.v:5436$993_Y
connect \main_sdblock2mem_source_source_valid \main_sdblock2mem_converter_source_valid
connect \main_sdblock2mem_converter_source_ready \main_sdblock2mem_source_source_ready
connect \main_sdblock2mem_source_source_first \main_sdblock2mem_converter_source_first
connect \main_sdblock2mem_source_source_last \main_sdblock2mem_converter_source_last
connect \main_sdblock2mem_source_source_payload_data \main_sdblock2mem_converter_source_payload_data
- connect \main_sdblock2mem_converter_sink_ready $or$ls180.v:5446$995_Y
+ connect \main_sdblock2mem_converter_sink_ready $or$ls180.v:5442$995_Y
connect \main_sdblock2mem_converter_source_valid \main_sdblock2mem_converter_strobe_all
- connect \main_sdblock2mem_converter_load_part $and$ls180.v:5448$996_Y
+ connect \main_sdblock2mem_converter_load_part $and$ls180.v:5444$996_Y
connect \main_interface0_bus_stb \main_sdblock2mem_sink_sink_valid1
connect \main_interface0_bus_cyc \main_sdblock2mem_sink_sink_valid1
connect \main_interface0_bus_we 1'1
connect \main_sdblock2mem_sink_sink_ready1 \main_interface0_bus_ack
connect \main_sdblock2mem_wishbonedmawriter_base \main_sdblock2mem_wishbonedmawriter_base_storage [33:2]
connect \main_sdblock2mem_wishbonedmawriter_length { 2'00 \main_sdblock2mem_wishbonedmawriter_length_storage [31:2] }
- connect \main_sdblock2mem_wishbonedmawriter_reset $not$ls180.v:5458$997_Y
+ connect \main_sdblock2mem_wishbonedmawriter_reset $not$ls180.v:5454$997_Y
connect \main_sdmem2block_converter_sink_valid \main_sdmem2block_dma_source_valid
connect \main_sdmem2block_dma_source_ready \main_sdmem2block_converter_sink_ready
connect \main_sdmem2block_converter_sink_first \main_sdmem2block_dma_source_first
connect \main_sdmem2block_dma_base \main_sdmem2block_dma_base_storage [33:2]
connect \main_sdmem2block_dma_length { 2'00 \main_sdmem2block_dma_length_storage [31:2] }
connect \main_sdmem2block_dma_offset_status \main_sdmem2block_dma_offset
- connect \main_sdmem2block_dma_reset $not$ls180.v:5517$1004_Y
+ connect \main_sdmem2block_dma_reset $not$ls180.v:5513$1004_Y
connect \main_sdmem2block_source_source_valid1 \main_sdmem2block_converter_source_valid
connect \main_sdmem2block_converter_source_ready \main_sdmem2block_source_source_ready1
connect \main_sdmem2block_source_source_first1 \main_sdmem2block_converter_source_first
connect \main_sdmem2block_source_source_last1 \main_sdmem2block_converter_source_last
connect \main_sdmem2block_source_source_payload_data1 \main_sdmem2block_converter_source_payload_data
- connect \main_sdmem2block_converter_first $eq$ls180.v:5598$1012_Y
- connect \main_sdmem2block_converter_last $eq$ls180.v:5599$1013_Y
+ connect \main_sdmem2block_converter_first $eq$ls180.v:5594$1012_Y
+ connect \main_sdmem2block_converter_last $eq$ls180.v:5595$1013_Y
connect \main_sdmem2block_converter_source_valid \main_sdmem2block_converter_sink_valid
- connect \main_sdmem2block_converter_source_first $and$ls180.v:5601$1014_Y
- connect \main_sdmem2block_converter_source_last $and$ls180.v:5602$1015_Y
- connect \main_sdmem2block_converter_sink_ready $and$ls180.v:5603$1016_Y
+ connect \main_sdmem2block_converter_source_first $and$ls180.v:5597$1014_Y
+ connect \main_sdmem2block_converter_source_last $and$ls180.v:5598$1015_Y
+ connect \main_sdmem2block_converter_sink_ready $and$ls180.v:5599$1016_Y
connect \main_sdmem2block_converter_source_payload_valid_token_count \main_sdmem2block_converter_last
connect \main_sdmem2block_fifo_syncfifo_din { \main_sdmem2block_fifo_fifo_in_last \main_sdmem2block_fifo_fifo_in_first \main_sdmem2block_fifo_fifo_in_payload_data }
connect { \main_sdmem2block_fifo_fifo_out_last \main_sdmem2block_fifo_fifo_out_first \main_sdmem2block_fifo_fifo_out_payload_data } \main_sdmem2block_fifo_syncfifo_dout
connect \main_sdmem2block_fifo_source_payload_data \main_sdmem2block_fifo_fifo_out_payload_data
connect \main_sdmem2block_fifo_syncfifo_re \main_sdmem2block_fifo_source_ready
connect \main_sdmem2block_fifo_wrport_dat_w \main_sdmem2block_fifo_syncfifo_din
- connect \main_sdmem2block_fifo_wrport_we $and$ls180.v:5643$1021_Y
- connect \main_sdmem2block_fifo_do_read $and$ls180.v:5644$1022_Y
+ connect \main_sdmem2block_fifo_wrport_we $and$ls180.v:5639$1021_Y
+ connect \main_sdmem2block_fifo_do_read $and$ls180.v:5640$1022_Y
connect \main_sdmem2block_fifo_rdport_adr \main_sdmem2block_fifo_consume
connect \main_sdmem2block_fifo_syncfifo_dout \main_sdmem2block_fifo_rdport_dat_r
- connect \main_sdmem2block_fifo_syncfifo_writable $ne$ls180.v:5647$1023_Y
- connect \main_sdmem2block_fifo_syncfifo_readable $ne$ls180.v:5648$1024_Y
+ connect \main_sdmem2block_fifo_syncfifo_writable $ne$ls180.v:5643$1023_Y
+ connect \main_sdmem2block_fifo_syncfifo_readable $ne$ls180.v:5644$1024_Y
connect \builder_shared_adr \builder_comb_rhs_array_muxed24 [29:0]
connect \builder_shared_dat_w \builder_comb_rhs_array_muxed25
connect \builder_shared_sel \builder_comb_rhs_array_muxed26
connect \main_libresocsim_interface2_converted_interface_dat_r \builder_shared_dat_r
connect \main_interface0_bus_dat_r \builder_shared_dat_r
connect \main_interface1_bus_dat_r \builder_shared_dat_r
- connect \main_libresocsim_interface0_converted_interface_ack $and$ls180.v:5699$1030_Y
- connect \main_libresocsim_interface1_converted_interface_ack $and$ls180.v:5700$1032_Y
- connect \main_libresocsim_interface2_converted_interface_ack $and$ls180.v:5701$1034_Y
- connect \main_interface0_bus_ack $and$ls180.v:5702$1036_Y
- connect \main_interface1_bus_ack $and$ls180.v:5703$1038_Y
- connect \main_libresocsim_interface0_converted_interface_err $and$ls180.v:5704$1040_Y
- connect \main_libresocsim_interface1_converted_interface_err $and$ls180.v:5705$1042_Y
- connect \main_libresocsim_interface2_converted_interface_err $and$ls180.v:5706$1044_Y
- connect \main_interface0_bus_err $and$ls180.v:5707$1046_Y
- connect \main_interface1_bus_err $and$ls180.v:5708$1048_Y
+ connect \main_libresocsim_interface0_converted_interface_ack $and$ls180.v:5695$1030_Y
+ connect \main_libresocsim_interface1_converted_interface_ack $and$ls180.v:5696$1032_Y
+ connect \main_libresocsim_interface2_converted_interface_ack $and$ls180.v:5697$1034_Y
+ connect \main_interface0_bus_ack $and$ls180.v:5698$1036_Y
+ connect \main_interface1_bus_ack $and$ls180.v:5699$1038_Y
+ connect \main_libresocsim_interface0_converted_interface_err $and$ls180.v:5700$1040_Y
+ connect \main_libresocsim_interface1_converted_interface_err $and$ls180.v:5701$1042_Y
+ connect \main_libresocsim_interface2_converted_interface_err $and$ls180.v:5702$1044_Y
+ connect \main_interface0_bus_err $and$ls180.v:5703$1046_Y
+ connect \main_interface1_bus_err $and$ls180.v:5704$1048_Y
connect \builder_request { \main_interface1_bus_cyc \main_interface0_bus_cyc \main_libresocsim_interface2_converted_interface_cyc \main_libresocsim_interface1_converted_interface_cyc \main_libresocsim_interface0_converted_interface_cyc }
connect \main_libresocsim_ram_bus_adr \builder_shared_adr
connect \main_libresocsim_ram_bus_dat_w \builder_shared_dat_w
connect \builder_libresocsim_wishbone_we \builder_shared_we
connect \builder_libresocsim_wishbone_cti \builder_shared_cti
connect \builder_libresocsim_wishbone_bte \builder_shared_bte
- connect \main_libresocsim_ram_bus_cyc $and$ls180.v:5753$1055_Y
- connect \main_libresocsim_libresoc_xics_icp_cyc $and$ls180.v:5754$1056_Y
- connect \main_libresocsim_libresoc_xics_ics_cyc $and$ls180.v:5755$1057_Y
- connect \main_wb_sdram_cyc $and$ls180.v:5756$1058_Y
- connect \builder_libresocsim_wishbone_cyc $and$ls180.v:5757$1059_Y
- connect \builder_shared_err $or$ls180.v:5758$1063_Y
- connect \builder_wait $and$ls180.v:5759$1066_Y
- connect \builder_done $eq$ls180.v:5772$1081_Y
- connect \builder_csrbank0_sel $eq$ls180.v:5773$1082_Y
+ connect \main_libresocsim_ram_bus_cyc $and$ls180.v:5749$1055_Y
+ connect \main_libresocsim_libresoc_xics_icp_cyc $and$ls180.v:5750$1056_Y
+ connect \main_libresocsim_libresoc_xics_ics_cyc $and$ls180.v:5751$1057_Y
+ connect \main_wb_sdram_cyc $and$ls180.v:5752$1058_Y
+ connect \builder_libresocsim_wishbone_cyc $and$ls180.v:5753$1059_Y
+ connect \builder_shared_err $or$ls180.v:5754$1063_Y
+ connect \builder_wait $and$ls180.v:5755$1066_Y
+ connect \builder_done $eq$ls180.v:5768$1081_Y
+ connect \builder_csrbank0_sel $eq$ls180.v:5769$1082_Y
connect \builder_csrbank0_reset0_r \builder_interface0_bank_bus_dat_w [0]
- connect \builder_csrbank0_reset0_re $and$ls180.v:5775$1085_Y
- connect \builder_csrbank0_reset0_we $and$ls180.v:5776$1089_Y
+ connect \builder_csrbank0_reset0_re $and$ls180.v:5771$1085_Y
+ connect \builder_csrbank0_reset0_we $and$ls180.v:5772$1089_Y
connect \builder_csrbank0_scratch3_r \builder_interface0_bank_bus_dat_w
- connect \builder_csrbank0_scratch3_re $and$ls180.v:5778$1092_Y
- connect \builder_csrbank0_scratch3_we $and$ls180.v:5779$1096_Y
+ connect \builder_csrbank0_scratch3_re $and$ls180.v:5774$1092_Y
+ connect \builder_csrbank0_scratch3_we $and$ls180.v:5775$1096_Y
connect \builder_csrbank0_scratch2_r \builder_interface0_bank_bus_dat_w
- connect \builder_csrbank0_scratch2_re $and$ls180.v:5781$1099_Y
- connect \builder_csrbank0_scratch2_we $and$ls180.v:5782$1103_Y
+ connect \builder_csrbank0_scratch2_re $and$ls180.v:5777$1099_Y
+ connect \builder_csrbank0_scratch2_we $and$ls180.v:5778$1103_Y
connect \builder_csrbank0_scratch1_r \builder_interface0_bank_bus_dat_w
- connect \builder_csrbank0_scratch1_re $and$ls180.v:5784$1106_Y
- connect \builder_csrbank0_scratch1_we $and$ls180.v:5785$1110_Y
+ connect \builder_csrbank0_scratch1_re $and$ls180.v:5780$1106_Y
+ connect \builder_csrbank0_scratch1_we $and$ls180.v:5781$1110_Y
connect \builder_csrbank0_scratch0_r \builder_interface0_bank_bus_dat_w
- connect \builder_csrbank0_scratch0_re $and$ls180.v:5787$1113_Y
- connect \builder_csrbank0_scratch0_we $and$ls180.v:5788$1117_Y
+ connect \builder_csrbank0_scratch0_re $and$ls180.v:5783$1113_Y
+ connect \builder_csrbank0_scratch0_we $and$ls180.v:5784$1117_Y
connect \builder_csrbank0_bus_errors3_r \builder_interface0_bank_bus_dat_w
- connect \builder_csrbank0_bus_errors3_re $and$ls180.v:5790$1120_Y
- connect \builder_csrbank0_bus_errors3_we $and$ls180.v:5791$1124_Y
+ connect \builder_csrbank0_bus_errors3_re $and$ls180.v:5786$1120_Y
+ connect \builder_csrbank0_bus_errors3_we $and$ls180.v:5787$1124_Y
connect \builder_csrbank0_bus_errors2_r \builder_interface0_bank_bus_dat_w
- connect \builder_csrbank0_bus_errors2_re $and$ls180.v:5793$1127_Y
- connect \builder_csrbank0_bus_errors2_we $and$ls180.v:5794$1131_Y
+ connect \builder_csrbank0_bus_errors2_re $and$ls180.v:5789$1127_Y
+ connect \builder_csrbank0_bus_errors2_we $and$ls180.v:5790$1131_Y
connect \builder_csrbank0_bus_errors1_r \builder_interface0_bank_bus_dat_w
- connect \builder_csrbank0_bus_errors1_re $and$ls180.v:5796$1134_Y
- connect \builder_csrbank0_bus_errors1_we $and$ls180.v:5797$1138_Y
+ connect \builder_csrbank0_bus_errors1_re $and$ls180.v:5792$1134_Y
+ connect \builder_csrbank0_bus_errors1_we $and$ls180.v:5793$1138_Y
connect \builder_csrbank0_bus_errors0_r \builder_interface0_bank_bus_dat_w
- connect \builder_csrbank0_bus_errors0_re $and$ls180.v:5799$1141_Y
- connect \builder_csrbank0_bus_errors0_we $and$ls180.v:5800$1145_Y
+ connect \builder_csrbank0_bus_errors0_re $and$ls180.v:5795$1141_Y
+ connect \builder_csrbank0_bus_errors0_we $and$ls180.v:5796$1145_Y
connect \builder_csrbank0_reset0_w \main_libresocsim_reset_storage
connect \builder_csrbank0_scratch3_w \main_libresocsim_scratch_storage [31:24]
connect \builder_csrbank0_scratch2_w \main_libresocsim_scratch_storage [23:16]
connect \builder_csrbank0_bus_errors1_w \main_libresocsim_bus_errors_status [15:8]
connect \builder_csrbank0_bus_errors0_w \main_libresocsim_bus_errors_status [7:0]
connect \main_libresocsim_bus_errors_we \builder_csrbank0_bus_errors0_we
- connect \builder_csrbank1_sel $eq$ls180.v:5811$1146_Y
+ connect \builder_csrbank1_sel $eq$ls180.v:5807$1146_Y
connect \builder_csrbank1_oe1_r \builder_interface1_bank_bus_dat_w
- connect \builder_csrbank1_oe1_re $and$ls180.v:5813$1149_Y
- connect \builder_csrbank1_oe1_we $and$ls180.v:5814$1153_Y
+ connect \builder_csrbank1_oe1_re $and$ls180.v:5809$1149_Y
+ connect \builder_csrbank1_oe1_we $and$ls180.v:5810$1153_Y
connect \builder_csrbank1_oe0_r \builder_interface1_bank_bus_dat_w
- connect \builder_csrbank1_oe0_re $and$ls180.v:5816$1156_Y
- connect \builder_csrbank1_oe0_we $and$ls180.v:5817$1160_Y
+ connect \builder_csrbank1_oe0_re $and$ls180.v:5812$1156_Y
+ connect \builder_csrbank1_oe0_we $and$ls180.v:5813$1160_Y
connect \builder_csrbank1_in1_r \builder_interface1_bank_bus_dat_w
- connect \builder_csrbank1_in1_re $and$ls180.v:5819$1163_Y
- connect \builder_csrbank1_in1_we $and$ls180.v:5820$1167_Y
+ connect \builder_csrbank1_in1_re $and$ls180.v:5815$1163_Y
+ connect \builder_csrbank1_in1_we $and$ls180.v:5816$1167_Y
connect \builder_csrbank1_in0_r \builder_interface1_bank_bus_dat_w
- connect \builder_csrbank1_in0_re $and$ls180.v:5822$1170_Y
- connect \builder_csrbank1_in0_we $and$ls180.v:5823$1174_Y
+ connect \builder_csrbank1_in0_re $and$ls180.v:5818$1170_Y
+ connect \builder_csrbank1_in0_we $and$ls180.v:5819$1174_Y
connect \builder_csrbank1_out1_r \builder_interface1_bank_bus_dat_w
- connect \builder_csrbank1_out1_re $and$ls180.v:5825$1177_Y
- connect \builder_csrbank1_out1_we $and$ls180.v:5826$1181_Y
+ connect \builder_csrbank1_out1_re $and$ls180.v:5821$1177_Y
+ connect \builder_csrbank1_out1_we $and$ls180.v:5822$1181_Y
connect \builder_csrbank1_out0_r \builder_interface1_bank_bus_dat_w
- connect \builder_csrbank1_out0_re $and$ls180.v:5828$1184_Y
- connect \builder_csrbank1_out0_we $and$ls180.v:5829$1188_Y
+ connect \builder_csrbank1_out0_re $and$ls180.v:5824$1184_Y
+ connect \builder_csrbank1_out0_we $and$ls180.v:5825$1188_Y
connect \builder_csrbank1_oe1_w \main_gpio_oe_storage [15:8]
connect \builder_csrbank1_oe0_w \main_gpio_oe_storage [7:0]
connect \builder_csrbank1_in1_w \main_gpio_status [15:8]
connect \main_gpio_we \builder_csrbank1_in0_we
connect \builder_csrbank1_out1_w \main_gpio_out_storage [15:8]
connect \builder_csrbank1_out0_w \main_gpio_out_storage [7:0]
- connect \builder_csrbank2_sel $eq$ls180.v:5837$1189_Y
+ connect \builder_csrbank2_sel $eq$ls180.v:5833$1189_Y
connect \builder_csrbank2_w0_r \builder_interface2_bank_bus_dat_w [2:0]
- connect \builder_csrbank2_w0_re $and$ls180.v:5839$1192_Y
- connect \builder_csrbank2_w0_we $and$ls180.v:5840$1196_Y
+ connect \builder_csrbank2_w0_re $and$ls180.v:5835$1192_Y
+ connect \builder_csrbank2_w0_we $and$ls180.v:5836$1196_Y
connect \builder_csrbank2_r_r \builder_interface2_bank_bus_dat_w [0]
- connect \builder_csrbank2_r_re $and$ls180.v:5842$1199_Y
- connect \builder_csrbank2_r_we $and$ls180.v:5843$1203_Y
+ connect \builder_csrbank2_r_re $and$ls180.v:5838$1199_Y
+ connect \builder_csrbank2_r_we $and$ls180.v:5839$1203_Y
connect \main_i2c_scl \main_i2c_storage [0]
connect \main_i2c_oe \main_i2c_storage [1]
connect \main_i2c_sda0 \main_i2c_storage [2]
connect \main_i2c_status \main_i2c_sda1
connect \builder_csrbank2_r_w \main_i2c_status
connect \main_i2c_we \builder_csrbank2_r_we
- connect \builder_csrbank3_sel $eq$ls180.v:5851$1204_Y
+ connect \builder_csrbank3_sel $eq$ls180.v:5847$1204_Y
connect \builder_csrbank3_enable0_r \builder_interface3_bank_bus_dat_w [0]
- connect \builder_csrbank3_enable0_re $and$ls180.v:5853$1207_Y
- connect \builder_csrbank3_enable0_we $and$ls180.v:5854$1211_Y
+ connect \builder_csrbank3_enable0_re $and$ls180.v:5849$1207_Y
+ connect \builder_csrbank3_enable0_we $and$ls180.v:5850$1211_Y
connect \builder_csrbank3_width3_r \builder_interface3_bank_bus_dat_w
- connect \builder_csrbank3_width3_re $and$ls180.v:5856$1214_Y
- connect \builder_csrbank3_width3_we $and$ls180.v:5857$1218_Y
+ connect \builder_csrbank3_width3_re $and$ls180.v:5852$1214_Y
+ connect \builder_csrbank3_width3_we $and$ls180.v:5853$1218_Y
connect \builder_csrbank3_width2_r \builder_interface3_bank_bus_dat_w
- connect \builder_csrbank3_width2_re $and$ls180.v:5859$1221_Y
- connect \builder_csrbank3_width2_we $and$ls180.v:5860$1225_Y
+ connect \builder_csrbank3_width2_re $and$ls180.v:5855$1221_Y
+ connect \builder_csrbank3_width2_we $and$ls180.v:5856$1225_Y
connect \builder_csrbank3_width1_r \builder_interface3_bank_bus_dat_w
- connect \builder_csrbank3_width1_re $and$ls180.v:5862$1228_Y
- connect \builder_csrbank3_width1_we $and$ls180.v:5863$1232_Y
+ connect \builder_csrbank3_width1_re $and$ls180.v:5858$1228_Y
+ connect \builder_csrbank3_width1_we $and$ls180.v:5859$1232_Y
connect \builder_csrbank3_width0_r \builder_interface3_bank_bus_dat_w
- connect \builder_csrbank3_width0_re $and$ls180.v:5865$1235_Y
- connect \builder_csrbank3_width0_we $and$ls180.v:5866$1239_Y
+ connect \builder_csrbank3_width0_re $and$ls180.v:5861$1235_Y
+ connect \builder_csrbank3_width0_we $and$ls180.v:5862$1239_Y
connect \builder_csrbank3_period3_r \builder_interface3_bank_bus_dat_w
- connect \builder_csrbank3_period3_re $and$ls180.v:5868$1242_Y
- connect \builder_csrbank3_period3_we $and$ls180.v:5869$1246_Y
+ connect \builder_csrbank3_period3_re $and$ls180.v:5864$1242_Y
+ connect \builder_csrbank3_period3_we $and$ls180.v:5865$1246_Y
connect \builder_csrbank3_period2_r \builder_interface3_bank_bus_dat_w
- connect \builder_csrbank3_period2_re $and$ls180.v:5871$1249_Y
- connect \builder_csrbank3_period2_we $and$ls180.v:5872$1253_Y
+ connect \builder_csrbank3_period2_re $and$ls180.v:5867$1249_Y
+ connect \builder_csrbank3_period2_we $and$ls180.v:5868$1253_Y
connect \builder_csrbank3_period1_r \builder_interface3_bank_bus_dat_w
- connect \builder_csrbank3_period1_re $and$ls180.v:5874$1256_Y
- connect \builder_csrbank3_period1_we $and$ls180.v:5875$1260_Y
+ connect \builder_csrbank3_period1_re $and$ls180.v:5870$1256_Y
+ connect \builder_csrbank3_period1_we $and$ls180.v:5871$1260_Y
connect \builder_csrbank3_period0_r \builder_interface3_bank_bus_dat_w
- connect \builder_csrbank3_period0_re $and$ls180.v:5877$1263_Y
- connect \builder_csrbank3_period0_we $and$ls180.v:5878$1267_Y
+ connect \builder_csrbank3_period0_re $and$ls180.v:5873$1263_Y
+ connect \builder_csrbank3_period0_we $and$ls180.v:5874$1267_Y
connect \builder_csrbank3_enable0_w \main_pwm0_enable_storage
connect \builder_csrbank3_width3_w \main_pwm0_width_storage [31:24]
connect \builder_csrbank3_width2_w \main_pwm0_width_storage [23:16]
connect \builder_csrbank3_period2_w \main_pwm0_period_storage [23:16]
connect \builder_csrbank3_period1_w \main_pwm0_period_storage [15:8]
connect \builder_csrbank3_period0_w \main_pwm0_period_storage [7:0]
- connect \builder_csrbank4_sel $eq$ls180.v:5888$1268_Y
+ connect \builder_csrbank4_sel $eq$ls180.v:5884$1268_Y
connect \builder_csrbank4_enable0_r \builder_interface4_bank_bus_dat_w [0]
- connect \builder_csrbank4_enable0_re $and$ls180.v:5890$1271_Y
- connect \builder_csrbank4_enable0_we $and$ls180.v:5891$1275_Y
+ connect \builder_csrbank4_enable0_re $and$ls180.v:5886$1271_Y
+ connect \builder_csrbank4_enable0_we $and$ls180.v:5887$1275_Y
connect \builder_csrbank4_width3_r \builder_interface4_bank_bus_dat_w
- connect \builder_csrbank4_width3_re $and$ls180.v:5893$1278_Y
- connect \builder_csrbank4_width3_we $and$ls180.v:5894$1282_Y
+ connect \builder_csrbank4_width3_re $and$ls180.v:5889$1278_Y
+ connect \builder_csrbank4_width3_we $and$ls180.v:5890$1282_Y
connect \builder_csrbank4_width2_r \builder_interface4_bank_bus_dat_w
- connect \builder_csrbank4_width2_re $and$ls180.v:5896$1285_Y
- connect \builder_csrbank4_width2_we $and$ls180.v:5897$1289_Y
+ connect \builder_csrbank4_width2_re $and$ls180.v:5892$1285_Y
+ connect \builder_csrbank4_width2_we $and$ls180.v:5893$1289_Y
connect \builder_csrbank4_width1_r \builder_interface4_bank_bus_dat_w
- connect \builder_csrbank4_width1_re $and$ls180.v:5899$1292_Y
- connect \builder_csrbank4_width1_we $and$ls180.v:5900$1296_Y
+ connect \builder_csrbank4_width1_re $and$ls180.v:5895$1292_Y
+ connect \builder_csrbank4_width1_we $and$ls180.v:5896$1296_Y
connect \builder_csrbank4_width0_r \builder_interface4_bank_bus_dat_w
- connect \builder_csrbank4_width0_re $and$ls180.v:5902$1299_Y
- connect \builder_csrbank4_width0_we $and$ls180.v:5903$1303_Y
+ connect \builder_csrbank4_width0_re $and$ls180.v:5898$1299_Y
+ connect \builder_csrbank4_width0_we $and$ls180.v:5899$1303_Y
connect \builder_csrbank4_period3_r \builder_interface4_bank_bus_dat_w
- connect \builder_csrbank4_period3_re $and$ls180.v:5905$1306_Y
- connect \builder_csrbank4_period3_we $and$ls180.v:5906$1310_Y
+ connect \builder_csrbank4_period3_re $and$ls180.v:5901$1306_Y
+ connect \builder_csrbank4_period3_we $and$ls180.v:5902$1310_Y
connect \builder_csrbank4_period2_r \builder_interface4_bank_bus_dat_w
- connect \builder_csrbank4_period2_re $and$ls180.v:5908$1313_Y
- connect \builder_csrbank4_period2_we $and$ls180.v:5909$1317_Y
+ connect \builder_csrbank4_period2_re $and$ls180.v:5904$1313_Y
+ connect \builder_csrbank4_period2_we $and$ls180.v:5905$1317_Y
connect \builder_csrbank4_period1_r \builder_interface4_bank_bus_dat_w
- connect \builder_csrbank4_period1_re $and$ls180.v:5911$1320_Y
- connect \builder_csrbank4_period1_we $and$ls180.v:5912$1324_Y
+ connect \builder_csrbank4_period1_re $and$ls180.v:5907$1320_Y
+ connect \builder_csrbank4_period1_we $and$ls180.v:5908$1324_Y
connect \builder_csrbank4_period0_r \builder_interface4_bank_bus_dat_w
- connect \builder_csrbank4_period0_re $and$ls180.v:5914$1327_Y
- connect \builder_csrbank4_period0_we $and$ls180.v:5915$1331_Y
+ connect \builder_csrbank4_period0_re $and$ls180.v:5910$1327_Y
+ connect \builder_csrbank4_period0_we $and$ls180.v:5911$1331_Y
connect \builder_csrbank4_enable0_w \main_pwm1_enable_storage
connect \builder_csrbank4_width3_w \main_pwm1_width_storage [31:24]
connect \builder_csrbank4_width2_w \main_pwm1_width_storage [23:16]
connect \builder_csrbank4_period2_w \main_pwm1_period_storage [23:16]
connect \builder_csrbank4_period1_w \main_pwm1_period_storage [15:8]
connect \builder_csrbank4_period0_w \main_pwm1_period_storage [7:0]
- connect \builder_csrbank5_sel $eq$ls180.v:5925$1332_Y
+ connect \builder_csrbank5_sel $eq$ls180.v:5921$1332_Y
connect \builder_csrbank5_dma_base7_r \builder_interface5_bank_bus_dat_w
- connect \builder_csrbank5_dma_base7_re $and$ls180.v:5927$1335_Y
- connect \builder_csrbank5_dma_base7_we $and$ls180.v:5928$1339_Y
+ connect \builder_csrbank5_dma_base7_re $and$ls180.v:5923$1335_Y
+ connect \builder_csrbank5_dma_base7_we $and$ls180.v:5924$1339_Y
connect \builder_csrbank5_dma_base6_r \builder_interface5_bank_bus_dat_w
- connect \builder_csrbank5_dma_base6_re $and$ls180.v:5930$1342_Y
- connect \builder_csrbank5_dma_base6_we $and$ls180.v:5931$1346_Y
+ connect \builder_csrbank5_dma_base6_re $and$ls180.v:5926$1342_Y
+ connect \builder_csrbank5_dma_base6_we $and$ls180.v:5927$1346_Y
connect \builder_csrbank5_dma_base5_r \builder_interface5_bank_bus_dat_w
- connect \builder_csrbank5_dma_base5_re $and$ls180.v:5933$1349_Y
- connect \builder_csrbank5_dma_base5_we $and$ls180.v:5934$1353_Y
+ connect \builder_csrbank5_dma_base5_re $and$ls180.v:5929$1349_Y
+ connect \builder_csrbank5_dma_base5_we $and$ls180.v:5930$1353_Y
connect \builder_csrbank5_dma_base4_r \builder_interface5_bank_bus_dat_w
- connect \builder_csrbank5_dma_base4_re $and$ls180.v:5936$1356_Y
- connect \builder_csrbank5_dma_base4_we $and$ls180.v:5937$1360_Y
+ connect \builder_csrbank5_dma_base4_re $and$ls180.v:5932$1356_Y
+ connect \builder_csrbank5_dma_base4_we $and$ls180.v:5933$1360_Y
connect \builder_csrbank5_dma_base3_r \builder_interface5_bank_bus_dat_w
- connect \builder_csrbank5_dma_base3_re $and$ls180.v:5939$1363_Y
- connect \builder_csrbank5_dma_base3_we $and$ls180.v:5940$1367_Y
+ connect \builder_csrbank5_dma_base3_re $and$ls180.v:5935$1363_Y
+ connect \builder_csrbank5_dma_base3_we $and$ls180.v:5936$1367_Y
connect \builder_csrbank5_dma_base2_r \builder_interface5_bank_bus_dat_w
- connect \builder_csrbank5_dma_base2_re $and$ls180.v:5942$1370_Y
- connect \builder_csrbank5_dma_base2_we $and$ls180.v:5943$1374_Y
+ connect \builder_csrbank5_dma_base2_re $and$ls180.v:5938$1370_Y
+ connect \builder_csrbank5_dma_base2_we $and$ls180.v:5939$1374_Y
connect \builder_csrbank5_dma_base1_r \builder_interface5_bank_bus_dat_w
- connect \builder_csrbank5_dma_base1_re $and$ls180.v:5945$1377_Y
- connect \builder_csrbank5_dma_base1_we $and$ls180.v:5946$1381_Y
+ connect \builder_csrbank5_dma_base1_re $and$ls180.v:5941$1377_Y
+ connect \builder_csrbank5_dma_base1_we $and$ls180.v:5942$1381_Y
connect \builder_csrbank5_dma_base0_r \builder_interface5_bank_bus_dat_w
- connect \builder_csrbank5_dma_base0_re $and$ls180.v:5948$1384_Y
- connect \builder_csrbank5_dma_base0_we $and$ls180.v:5949$1388_Y
+ connect \builder_csrbank5_dma_base0_re $and$ls180.v:5944$1384_Y
+ connect \builder_csrbank5_dma_base0_we $and$ls180.v:5945$1388_Y
connect \builder_csrbank5_dma_length3_r \builder_interface5_bank_bus_dat_w
- connect \builder_csrbank5_dma_length3_re $and$ls180.v:5951$1391_Y
- connect \builder_csrbank5_dma_length3_we $and$ls180.v:5952$1395_Y
+ connect \builder_csrbank5_dma_length3_re $and$ls180.v:5947$1391_Y
+ connect \builder_csrbank5_dma_length3_we $and$ls180.v:5948$1395_Y
connect \builder_csrbank5_dma_length2_r \builder_interface5_bank_bus_dat_w
- connect \builder_csrbank5_dma_length2_re $and$ls180.v:5954$1398_Y
- connect \builder_csrbank5_dma_length2_we $and$ls180.v:5955$1402_Y
+ connect \builder_csrbank5_dma_length2_re $and$ls180.v:5950$1398_Y
+ connect \builder_csrbank5_dma_length2_we $and$ls180.v:5951$1402_Y
connect \builder_csrbank5_dma_length1_r \builder_interface5_bank_bus_dat_w
- connect \builder_csrbank5_dma_length1_re $and$ls180.v:5957$1405_Y
- connect \builder_csrbank5_dma_length1_we $and$ls180.v:5958$1409_Y
+ connect \builder_csrbank5_dma_length1_re $and$ls180.v:5953$1405_Y
+ connect \builder_csrbank5_dma_length1_we $and$ls180.v:5954$1409_Y
connect \builder_csrbank5_dma_length0_r \builder_interface5_bank_bus_dat_w
- connect \builder_csrbank5_dma_length0_re $and$ls180.v:5960$1412_Y
- connect \builder_csrbank5_dma_length0_we $and$ls180.v:5961$1416_Y
+ connect \builder_csrbank5_dma_length0_re $and$ls180.v:5956$1412_Y
+ connect \builder_csrbank5_dma_length0_we $and$ls180.v:5957$1416_Y
connect \builder_csrbank5_dma_enable0_r \builder_interface5_bank_bus_dat_w [0]
- connect \builder_csrbank5_dma_enable0_re $and$ls180.v:5963$1419_Y
- connect \builder_csrbank5_dma_enable0_we $and$ls180.v:5964$1423_Y
+ connect \builder_csrbank5_dma_enable0_re $and$ls180.v:5959$1419_Y
+ connect \builder_csrbank5_dma_enable0_we $and$ls180.v:5960$1423_Y
connect \builder_csrbank5_dma_done_r \builder_interface5_bank_bus_dat_w [0]
- connect \builder_csrbank5_dma_done_re $and$ls180.v:5966$1426_Y
- connect \builder_csrbank5_dma_done_we $and$ls180.v:5967$1430_Y
+ connect \builder_csrbank5_dma_done_re $and$ls180.v:5962$1426_Y
+ connect \builder_csrbank5_dma_done_we $and$ls180.v:5963$1430_Y
connect \builder_csrbank5_dma_loop0_r \builder_interface5_bank_bus_dat_w [0]
- connect \builder_csrbank5_dma_loop0_re $and$ls180.v:5969$1433_Y
- connect \builder_csrbank5_dma_loop0_we $and$ls180.v:5970$1437_Y
+ connect \builder_csrbank5_dma_loop0_re $and$ls180.v:5965$1433_Y
+ connect \builder_csrbank5_dma_loop0_we $and$ls180.v:5966$1437_Y
connect \builder_csrbank5_dma_base7_w \main_sdblock2mem_wishbonedmawriter_base_storage [63:56]
connect \builder_csrbank5_dma_base6_w \main_sdblock2mem_wishbonedmawriter_base_storage [55:48]
connect \builder_csrbank5_dma_base5_w \main_sdblock2mem_wishbonedmawriter_base_storage [47:40]
connect \builder_csrbank5_dma_done_w \main_sdblock2mem_wishbonedmawriter_status
connect \main_sdblock2mem_wishbonedmawriter_we \builder_csrbank5_dma_done_we
connect \builder_csrbank5_dma_loop0_w \main_sdblock2mem_wishbonedmawriter_loop_storage
- connect \builder_csrbank6_sel $eq$ls180.v:5987$1438_Y
+ connect \builder_csrbank6_sel $eq$ls180.v:5983$1438_Y
connect \builder_csrbank6_cmd_argument3_r \builder_interface6_bank_bus_dat_w
- connect \builder_csrbank6_cmd_argument3_re $and$ls180.v:5989$1441_Y
- connect \builder_csrbank6_cmd_argument3_we $and$ls180.v:5990$1445_Y
+ connect \builder_csrbank6_cmd_argument3_re $and$ls180.v:5985$1441_Y
+ connect \builder_csrbank6_cmd_argument3_we $and$ls180.v:5986$1445_Y
connect \builder_csrbank6_cmd_argument2_r \builder_interface6_bank_bus_dat_w
- connect \builder_csrbank6_cmd_argument2_re $and$ls180.v:5992$1448_Y
- connect \builder_csrbank6_cmd_argument2_we $and$ls180.v:5993$1452_Y
+ connect \builder_csrbank6_cmd_argument2_re $and$ls180.v:5988$1448_Y
+ connect \builder_csrbank6_cmd_argument2_we $and$ls180.v:5989$1452_Y
connect \builder_csrbank6_cmd_argument1_r \builder_interface6_bank_bus_dat_w
- connect \builder_csrbank6_cmd_argument1_re $and$ls180.v:5995$1455_Y
- connect \builder_csrbank6_cmd_argument1_we $and$ls180.v:5996$1459_Y
+ connect \builder_csrbank6_cmd_argument1_re $and$ls180.v:5991$1455_Y
+ connect \builder_csrbank6_cmd_argument1_we $and$ls180.v:5992$1459_Y
connect \builder_csrbank6_cmd_argument0_r \builder_interface6_bank_bus_dat_w
- connect \builder_csrbank6_cmd_argument0_re $and$ls180.v:5998$1462_Y
- connect \builder_csrbank6_cmd_argument0_we $and$ls180.v:5999$1466_Y
+ connect \builder_csrbank6_cmd_argument0_re $and$ls180.v:5994$1462_Y
+ connect \builder_csrbank6_cmd_argument0_we $and$ls180.v:5995$1466_Y
connect \builder_csrbank6_cmd_command3_r \builder_interface6_bank_bus_dat_w
- connect \builder_csrbank6_cmd_command3_re $and$ls180.v:6001$1469_Y
- connect \builder_csrbank6_cmd_command3_we $and$ls180.v:6002$1473_Y
+ connect \builder_csrbank6_cmd_command3_re $and$ls180.v:5997$1469_Y
+ connect \builder_csrbank6_cmd_command3_we $and$ls180.v:5998$1473_Y
connect \builder_csrbank6_cmd_command2_r \builder_interface6_bank_bus_dat_w
- connect \builder_csrbank6_cmd_command2_re $and$ls180.v:6004$1476_Y
- connect \builder_csrbank6_cmd_command2_we $and$ls180.v:6005$1480_Y
+ connect \builder_csrbank6_cmd_command2_re $and$ls180.v:6000$1476_Y
+ connect \builder_csrbank6_cmd_command2_we $and$ls180.v:6001$1480_Y
connect \builder_csrbank6_cmd_command1_r \builder_interface6_bank_bus_dat_w
- connect \builder_csrbank6_cmd_command1_re $and$ls180.v:6007$1483_Y
- connect \builder_csrbank6_cmd_command1_we $and$ls180.v:6008$1487_Y
+ connect \builder_csrbank6_cmd_command1_re $and$ls180.v:6003$1483_Y
+ connect \builder_csrbank6_cmd_command1_we $and$ls180.v:6004$1487_Y
connect \builder_csrbank6_cmd_command0_r \builder_interface6_bank_bus_dat_w
- connect \builder_csrbank6_cmd_command0_re $and$ls180.v:6010$1490_Y
- connect \builder_csrbank6_cmd_command0_we $and$ls180.v:6011$1494_Y
+ connect \builder_csrbank6_cmd_command0_re $and$ls180.v:6006$1490_Y
+ connect \builder_csrbank6_cmd_command0_we $and$ls180.v:6007$1494_Y
connect \main_sdcore_cmd_send_r \builder_interface6_bank_bus_dat_w [0]
- connect \main_sdcore_cmd_send_re $and$ls180.v:6013$1497_Y
- connect \main_sdcore_cmd_send_we $and$ls180.v:6014$1501_Y
+ connect \main_sdcore_cmd_send_re $and$ls180.v:6009$1497_Y
+ connect \main_sdcore_cmd_send_we $and$ls180.v:6010$1501_Y
connect \builder_csrbank6_cmd_response15_r \builder_interface6_bank_bus_dat_w
- connect \builder_csrbank6_cmd_response15_re $and$ls180.v:6016$1504_Y
- connect \builder_csrbank6_cmd_response15_we $and$ls180.v:6017$1508_Y
+ connect \builder_csrbank6_cmd_response15_re $and$ls180.v:6012$1504_Y
+ connect \builder_csrbank6_cmd_response15_we $and$ls180.v:6013$1508_Y
connect \builder_csrbank6_cmd_response14_r \builder_interface6_bank_bus_dat_w
- connect \builder_csrbank6_cmd_response14_re $and$ls180.v:6019$1511_Y
- connect \builder_csrbank6_cmd_response14_we $and$ls180.v:6020$1515_Y
+ connect \builder_csrbank6_cmd_response14_re $and$ls180.v:6015$1511_Y
+ connect \builder_csrbank6_cmd_response14_we $and$ls180.v:6016$1515_Y
connect \builder_csrbank6_cmd_response13_r \builder_interface6_bank_bus_dat_w
- connect \builder_csrbank6_cmd_response13_re $and$ls180.v:6022$1518_Y
- connect \builder_csrbank6_cmd_response13_we $and$ls180.v:6023$1522_Y
+ connect \builder_csrbank6_cmd_response13_re $and$ls180.v:6018$1518_Y
+ connect \builder_csrbank6_cmd_response13_we $and$ls180.v:6019$1522_Y
connect \builder_csrbank6_cmd_response12_r \builder_interface6_bank_bus_dat_w
- connect \builder_csrbank6_cmd_response12_re $and$ls180.v:6025$1525_Y
- connect \builder_csrbank6_cmd_response12_we $and$ls180.v:6026$1529_Y
+ connect \builder_csrbank6_cmd_response12_re $and$ls180.v:6021$1525_Y
+ connect \builder_csrbank6_cmd_response12_we $and$ls180.v:6022$1529_Y
connect \builder_csrbank6_cmd_response11_r \builder_interface6_bank_bus_dat_w
- connect \builder_csrbank6_cmd_response11_re $and$ls180.v:6028$1532_Y
- connect \builder_csrbank6_cmd_response11_we $and$ls180.v:6029$1536_Y
+ connect \builder_csrbank6_cmd_response11_re $and$ls180.v:6024$1532_Y
+ connect \builder_csrbank6_cmd_response11_we $and$ls180.v:6025$1536_Y
connect \builder_csrbank6_cmd_response10_r \builder_interface6_bank_bus_dat_w
- connect \builder_csrbank6_cmd_response10_re $and$ls180.v:6031$1539_Y
- connect \builder_csrbank6_cmd_response10_we $and$ls180.v:6032$1543_Y
+ connect \builder_csrbank6_cmd_response10_re $and$ls180.v:6027$1539_Y
+ connect \builder_csrbank6_cmd_response10_we $and$ls180.v:6028$1543_Y
connect \builder_csrbank6_cmd_response9_r \builder_interface6_bank_bus_dat_w
- connect \builder_csrbank6_cmd_response9_re $and$ls180.v:6034$1546_Y
- connect \builder_csrbank6_cmd_response9_we $and$ls180.v:6035$1550_Y
+ connect \builder_csrbank6_cmd_response9_re $and$ls180.v:6030$1546_Y
+ connect \builder_csrbank6_cmd_response9_we $and$ls180.v:6031$1550_Y
connect \builder_csrbank6_cmd_response8_r \builder_interface6_bank_bus_dat_w
- connect \builder_csrbank6_cmd_response8_re $and$ls180.v:6037$1553_Y
- connect \builder_csrbank6_cmd_response8_we $and$ls180.v:6038$1557_Y
+ connect \builder_csrbank6_cmd_response8_re $and$ls180.v:6033$1553_Y
+ connect \builder_csrbank6_cmd_response8_we $and$ls180.v:6034$1557_Y
connect \builder_csrbank6_cmd_response7_r \builder_interface6_bank_bus_dat_w
- connect \builder_csrbank6_cmd_response7_re $and$ls180.v:6040$1560_Y
- connect \builder_csrbank6_cmd_response7_we $and$ls180.v:6041$1564_Y
+ connect \builder_csrbank6_cmd_response7_re $and$ls180.v:6036$1560_Y
+ connect \builder_csrbank6_cmd_response7_we $and$ls180.v:6037$1564_Y
connect \builder_csrbank6_cmd_response6_r \builder_interface6_bank_bus_dat_w
- connect \builder_csrbank6_cmd_response6_re $and$ls180.v:6043$1567_Y
- connect \builder_csrbank6_cmd_response6_we $and$ls180.v:6044$1571_Y
+ connect \builder_csrbank6_cmd_response6_re $and$ls180.v:6039$1567_Y
+ connect \builder_csrbank6_cmd_response6_we $and$ls180.v:6040$1571_Y
connect \builder_csrbank6_cmd_response5_r \builder_interface6_bank_bus_dat_w
- connect \builder_csrbank6_cmd_response5_re $and$ls180.v:6046$1574_Y
- connect \builder_csrbank6_cmd_response5_we $and$ls180.v:6047$1578_Y
+ connect \builder_csrbank6_cmd_response5_re $and$ls180.v:6042$1574_Y
+ connect \builder_csrbank6_cmd_response5_we $and$ls180.v:6043$1578_Y
connect \builder_csrbank6_cmd_response4_r \builder_interface6_bank_bus_dat_w
- connect \builder_csrbank6_cmd_response4_re $and$ls180.v:6049$1581_Y
- connect \builder_csrbank6_cmd_response4_we $and$ls180.v:6050$1585_Y
+ connect \builder_csrbank6_cmd_response4_re $and$ls180.v:6045$1581_Y
+ connect \builder_csrbank6_cmd_response4_we $and$ls180.v:6046$1585_Y
connect \builder_csrbank6_cmd_response3_r \builder_interface6_bank_bus_dat_w
- connect \builder_csrbank6_cmd_response3_re $and$ls180.v:6052$1588_Y
- connect \builder_csrbank6_cmd_response3_we $and$ls180.v:6053$1592_Y
+ connect \builder_csrbank6_cmd_response3_re $and$ls180.v:6048$1588_Y
+ connect \builder_csrbank6_cmd_response3_we $and$ls180.v:6049$1592_Y
connect \builder_csrbank6_cmd_response2_r \builder_interface6_bank_bus_dat_w
- connect \builder_csrbank6_cmd_response2_re $and$ls180.v:6055$1595_Y
- connect \builder_csrbank6_cmd_response2_we $and$ls180.v:6056$1599_Y
+ connect \builder_csrbank6_cmd_response2_re $and$ls180.v:6051$1595_Y
+ connect \builder_csrbank6_cmd_response2_we $and$ls180.v:6052$1599_Y
connect \builder_csrbank6_cmd_response1_r \builder_interface6_bank_bus_dat_w
- connect \builder_csrbank6_cmd_response1_re $and$ls180.v:6058$1602_Y
- connect \builder_csrbank6_cmd_response1_we $and$ls180.v:6059$1606_Y
+ connect \builder_csrbank6_cmd_response1_re $and$ls180.v:6054$1602_Y
+ connect \builder_csrbank6_cmd_response1_we $and$ls180.v:6055$1606_Y
connect \builder_csrbank6_cmd_response0_r \builder_interface6_bank_bus_dat_w
- connect \builder_csrbank6_cmd_response0_re $and$ls180.v:6061$1609_Y
- connect \builder_csrbank6_cmd_response0_we $and$ls180.v:6062$1613_Y
+ connect \builder_csrbank6_cmd_response0_re $and$ls180.v:6057$1609_Y
+ connect \builder_csrbank6_cmd_response0_we $and$ls180.v:6058$1613_Y
connect \builder_csrbank6_cmd_event_r \builder_interface6_bank_bus_dat_w [3:0]
- connect \builder_csrbank6_cmd_event_re $and$ls180.v:6064$1616_Y
- connect \builder_csrbank6_cmd_event_we $and$ls180.v:6065$1620_Y
+ connect \builder_csrbank6_cmd_event_re $and$ls180.v:6060$1616_Y
+ connect \builder_csrbank6_cmd_event_we $and$ls180.v:6061$1620_Y
connect \builder_csrbank6_data_event_r \builder_interface6_bank_bus_dat_w [3:0]
- connect \builder_csrbank6_data_event_re $and$ls180.v:6067$1623_Y
- connect \builder_csrbank6_data_event_we $and$ls180.v:6068$1627_Y
+ connect \builder_csrbank6_data_event_re $and$ls180.v:6063$1623_Y
+ connect \builder_csrbank6_data_event_we $and$ls180.v:6064$1627_Y
connect \builder_csrbank6_block_length1_r \builder_interface6_bank_bus_dat_w [1:0]
- connect \builder_csrbank6_block_length1_re $and$ls180.v:6070$1630_Y
- connect \builder_csrbank6_block_length1_we $and$ls180.v:6071$1634_Y
+ connect \builder_csrbank6_block_length1_re $and$ls180.v:6066$1630_Y
+ connect \builder_csrbank6_block_length1_we $and$ls180.v:6067$1634_Y
connect \builder_csrbank6_block_length0_r \builder_interface6_bank_bus_dat_w
- connect \builder_csrbank6_block_length0_re $and$ls180.v:6073$1637_Y
- connect \builder_csrbank6_block_length0_we $and$ls180.v:6074$1641_Y
+ connect \builder_csrbank6_block_length0_re $and$ls180.v:6069$1637_Y
+ connect \builder_csrbank6_block_length0_we $and$ls180.v:6070$1641_Y
connect \builder_csrbank6_block_count3_r \builder_interface6_bank_bus_dat_w
- connect \builder_csrbank6_block_count3_re $and$ls180.v:6076$1644_Y
- connect \builder_csrbank6_block_count3_we $and$ls180.v:6077$1648_Y
+ connect \builder_csrbank6_block_count3_re $and$ls180.v:6072$1644_Y
+ connect \builder_csrbank6_block_count3_we $and$ls180.v:6073$1648_Y
connect \builder_csrbank6_block_count2_r \builder_interface6_bank_bus_dat_w
- connect \builder_csrbank6_block_count2_re $and$ls180.v:6079$1651_Y
- connect \builder_csrbank6_block_count2_we $and$ls180.v:6080$1655_Y
+ connect \builder_csrbank6_block_count2_re $and$ls180.v:6075$1651_Y
+ connect \builder_csrbank6_block_count2_we $and$ls180.v:6076$1655_Y
connect \builder_csrbank6_block_count1_r \builder_interface6_bank_bus_dat_w
- connect \builder_csrbank6_block_count1_re $and$ls180.v:6082$1658_Y
- connect \builder_csrbank6_block_count1_we $and$ls180.v:6083$1662_Y
+ connect \builder_csrbank6_block_count1_re $and$ls180.v:6078$1658_Y
+ connect \builder_csrbank6_block_count1_we $and$ls180.v:6079$1662_Y
connect \builder_csrbank6_block_count0_r \builder_interface6_bank_bus_dat_w
- connect \builder_csrbank6_block_count0_re $and$ls180.v:6085$1665_Y
- connect \builder_csrbank6_block_count0_we $and$ls180.v:6086$1669_Y
+ connect \builder_csrbank6_block_count0_re $and$ls180.v:6081$1665_Y
+ connect \builder_csrbank6_block_count0_we $and$ls180.v:6082$1669_Y
connect \builder_csrbank6_cmd_argument3_w \main_sdcore_cmd_argument_storage [31:24]
connect \builder_csrbank6_cmd_argument2_w \main_sdcore_cmd_argument_storage [23:16]
connect \builder_csrbank6_cmd_argument1_w \main_sdcore_cmd_argument_storage [15:8]
connect \builder_csrbank6_block_count2_w \main_sdcore_block_count_storage [23:16]
connect \builder_csrbank6_block_count1_w \main_sdcore_block_count_storage [15:8]
connect \builder_csrbank6_block_count0_w \main_sdcore_block_count_storage [7:0]
- connect \builder_csrbank7_sel $eq$ls180.v:6122$1670_Y
+ connect \builder_csrbank7_sel $eq$ls180.v:6118$1670_Y
connect \builder_csrbank7_dma_base7_r \builder_interface7_bank_bus_dat_w
- connect \builder_csrbank7_dma_base7_re $and$ls180.v:6124$1673_Y
- connect \builder_csrbank7_dma_base7_we $and$ls180.v:6125$1677_Y
+ connect \builder_csrbank7_dma_base7_re $and$ls180.v:6120$1673_Y
+ connect \builder_csrbank7_dma_base7_we $and$ls180.v:6121$1677_Y
connect \builder_csrbank7_dma_base6_r \builder_interface7_bank_bus_dat_w
- connect \builder_csrbank7_dma_base6_re $and$ls180.v:6127$1680_Y
- connect \builder_csrbank7_dma_base6_we $and$ls180.v:6128$1684_Y
+ connect \builder_csrbank7_dma_base6_re $and$ls180.v:6123$1680_Y
+ connect \builder_csrbank7_dma_base6_we $and$ls180.v:6124$1684_Y
connect \builder_csrbank7_dma_base5_r \builder_interface7_bank_bus_dat_w
- connect \builder_csrbank7_dma_base5_re $and$ls180.v:6130$1687_Y
- connect \builder_csrbank7_dma_base5_we $and$ls180.v:6131$1691_Y
+ connect \builder_csrbank7_dma_base5_re $and$ls180.v:6126$1687_Y
+ connect \builder_csrbank7_dma_base5_we $and$ls180.v:6127$1691_Y
connect \builder_csrbank7_dma_base4_r \builder_interface7_bank_bus_dat_w
- connect \builder_csrbank7_dma_base4_re $and$ls180.v:6133$1694_Y
- connect \builder_csrbank7_dma_base4_we $and$ls180.v:6134$1698_Y
+ connect \builder_csrbank7_dma_base4_re $and$ls180.v:6129$1694_Y
+ connect \builder_csrbank7_dma_base4_we $and$ls180.v:6130$1698_Y
connect \builder_csrbank7_dma_base3_r \builder_interface7_bank_bus_dat_w
- connect \builder_csrbank7_dma_base3_re $and$ls180.v:6136$1701_Y
- connect \builder_csrbank7_dma_base3_we $and$ls180.v:6137$1705_Y
+ connect \builder_csrbank7_dma_base3_re $and$ls180.v:6132$1701_Y
+ connect \builder_csrbank7_dma_base3_we $and$ls180.v:6133$1705_Y
connect \builder_csrbank7_dma_base2_r \builder_interface7_bank_bus_dat_w
- connect \builder_csrbank7_dma_base2_re $and$ls180.v:6139$1708_Y
- connect \builder_csrbank7_dma_base2_we $and$ls180.v:6140$1712_Y
+ connect \builder_csrbank7_dma_base2_re $and$ls180.v:6135$1708_Y
+ connect \builder_csrbank7_dma_base2_we $and$ls180.v:6136$1712_Y
connect \builder_csrbank7_dma_base1_r \builder_interface7_bank_bus_dat_w
- connect \builder_csrbank7_dma_base1_re $and$ls180.v:6142$1715_Y
- connect \builder_csrbank7_dma_base1_we $and$ls180.v:6143$1719_Y
+ connect \builder_csrbank7_dma_base1_re $and$ls180.v:6138$1715_Y
+ connect \builder_csrbank7_dma_base1_we $and$ls180.v:6139$1719_Y
connect \builder_csrbank7_dma_base0_r \builder_interface7_bank_bus_dat_w
- connect \builder_csrbank7_dma_base0_re $and$ls180.v:6145$1722_Y
- connect \builder_csrbank7_dma_base0_we $and$ls180.v:6146$1726_Y
+ connect \builder_csrbank7_dma_base0_re $and$ls180.v:6141$1722_Y
+ connect \builder_csrbank7_dma_base0_we $and$ls180.v:6142$1726_Y
connect \builder_csrbank7_dma_length3_r \builder_interface7_bank_bus_dat_w
- connect \builder_csrbank7_dma_length3_re $and$ls180.v:6148$1729_Y
- connect \builder_csrbank7_dma_length3_we $and$ls180.v:6149$1733_Y
+ connect \builder_csrbank7_dma_length3_re $and$ls180.v:6144$1729_Y
+ connect \builder_csrbank7_dma_length3_we $and$ls180.v:6145$1733_Y
connect \builder_csrbank7_dma_length2_r \builder_interface7_bank_bus_dat_w
- connect \builder_csrbank7_dma_length2_re $and$ls180.v:6151$1736_Y
- connect \builder_csrbank7_dma_length2_we $and$ls180.v:6152$1740_Y
+ connect \builder_csrbank7_dma_length2_re $and$ls180.v:6147$1736_Y
+ connect \builder_csrbank7_dma_length2_we $and$ls180.v:6148$1740_Y
connect \builder_csrbank7_dma_length1_r \builder_interface7_bank_bus_dat_w
- connect \builder_csrbank7_dma_length1_re $and$ls180.v:6154$1743_Y
- connect \builder_csrbank7_dma_length1_we $and$ls180.v:6155$1747_Y
+ connect \builder_csrbank7_dma_length1_re $and$ls180.v:6150$1743_Y
+ connect \builder_csrbank7_dma_length1_we $and$ls180.v:6151$1747_Y
connect \builder_csrbank7_dma_length0_r \builder_interface7_bank_bus_dat_w
- connect \builder_csrbank7_dma_length0_re $and$ls180.v:6157$1750_Y
- connect \builder_csrbank7_dma_length0_we $and$ls180.v:6158$1754_Y
+ connect \builder_csrbank7_dma_length0_re $and$ls180.v:6153$1750_Y
+ connect \builder_csrbank7_dma_length0_we $and$ls180.v:6154$1754_Y
connect \builder_csrbank7_dma_enable0_r \builder_interface7_bank_bus_dat_w [0]
- connect \builder_csrbank7_dma_enable0_re $and$ls180.v:6160$1757_Y
- connect \builder_csrbank7_dma_enable0_we $and$ls180.v:6161$1761_Y
+ connect \builder_csrbank7_dma_enable0_re $and$ls180.v:6156$1757_Y
+ connect \builder_csrbank7_dma_enable0_we $and$ls180.v:6157$1761_Y
connect \builder_csrbank7_dma_done_r \builder_interface7_bank_bus_dat_w [0]
- connect \builder_csrbank7_dma_done_re $and$ls180.v:6163$1764_Y
- connect \builder_csrbank7_dma_done_we $and$ls180.v:6164$1768_Y
+ connect \builder_csrbank7_dma_done_re $and$ls180.v:6159$1764_Y
+ connect \builder_csrbank7_dma_done_we $and$ls180.v:6160$1768_Y
connect \builder_csrbank7_dma_loop0_r \builder_interface7_bank_bus_dat_w [0]
- connect \builder_csrbank7_dma_loop0_re $and$ls180.v:6166$1771_Y
- connect \builder_csrbank7_dma_loop0_we $and$ls180.v:6167$1775_Y
+ connect \builder_csrbank7_dma_loop0_re $and$ls180.v:6162$1771_Y
+ connect \builder_csrbank7_dma_loop0_we $and$ls180.v:6163$1775_Y
connect \builder_csrbank7_dma_offset3_r \builder_interface7_bank_bus_dat_w
- connect \builder_csrbank7_dma_offset3_re $and$ls180.v:6169$1778_Y
- connect \builder_csrbank7_dma_offset3_we $and$ls180.v:6170$1782_Y
+ connect \builder_csrbank7_dma_offset3_re $and$ls180.v:6165$1778_Y
+ connect \builder_csrbank7_dma_offset3_we $and$ls180.v:6166$1782_Y
connect \builder_csrbank7_dma_offset2_r \builder_interface7_bank_bus_dat_w
- connect \builder_csrbank7_dma_offset2_re $and$ls180.v:6172$1785_Y
- connect \builder_csrbank7_dma_offset2_we $and$ls180.v:6173$1789_Y
+ connect \builder_csrbank7_dma_offset2_re $and$ls180.v:6168$1785_Y
+ connect \builder_csrbank7_dma_offset2_we $and$ls180.v:6169$1789_Y
connect \builder_csrbank7_dma_offset1_r \builder_interface7_bank_bus_dat_w
- connect \builder_csrbank7_dma_offset1_re $and$ls180.v:6175$1792_Y
- connect \builder_csrbank7_dma_offset1_we $and$ls180.v:6176$1796_Y
+ connect \builder_csrbank7_dma_offset1_re $and$ls180.v:6171$1792_Y
+ connect \builder_csrbank7_dma_offset1_we $and$ls180.v:6172$1796_Y
connect \builder_csrbank7_dma_offset0_r \builder_interface7_bank_bus_dat_w
- connect \builder_csrbank7_dma_offset0_re $and$ls180.v:6178$1799_Y
- connect \builder_csrbank7_dma_offset0_we $and$ls180.v:6179$1803_Y
+ connect \builder_csrbank7_dma_offset0_re $and$ls180.v:6174$1799_Y
+ connect \builder_csrbank7_dma_offset0_we $and$ls180.v:6175$1803_Y
connect \builder_csrbank7_dma_base7_w \main_sdmem2block_dma_base_storage [63:56]
connect \builder_csrbank7_dma_base6_w \main_sdmem2block_dma_base_storage [55:48]
connect \builder_csrbank7_dma_base5_w \main_sdmem2block_dma_base_storage [47:40]
connect \builder_csrbank7_dma_offset1_w \main_sdmem2block_dma_offset_status [15:8]
connect \builder_csrbank7_dma_offset0_w \main_sdmem2block_dma_offset_status [7:0]
connect \main_sdmem2block_dma_offset_we \builder_csrbank7_dma_offset0_we
- connect \builder_csrbank8_sel $eq$ls180.v:6201$1804_Y
+ connect \builder_csrbank8_sel $eq$ls180.v:6197$1804_Y
connect \builder_csrbank8_card_detect_r \builder_interface8_bank_bus_dat_w [0]
- connect \builder_csrbank8_card_detect_re $and$ls180.v:6203$1807_Y
- connect \builder_csrbank8_card_detect_we $and$ls180.v:6204$1811_Y
+ connect \builder_csrbank8_card_detect_re $and$ls180.v:6199$1807_Y
+ connect \builder_csrbank8_card_detect_we $and$ls180.v:6200$1811_Y
connect \builder_csrbank8_clocker_divider1_r \builder_interface8_bank_bus_dat_w [0]
- connect \builder_csrbank8_clocker_divider1_re $and$ls180.v:6206$1814_Y
- connect \builder_csrbank8_clocker_divider1_we $and$ls180.v:6207$1818_Y
+ connect \builder_csrbank8_clocker_divider1_re $and$ls180.v:6202$1814_Y
+ connect \builder_csrbank8_clocker_divider1_we $and$ls180.v:6203$1818_Y
connect \builder_csrbank8_clocker_divider0_r \builder_interface8_bank_bus_dat_w
- connect \builder_csrbank8_clocker_divider0_re $and$ls180.v:6209$1821_Y
- connect \builder_csrbank8_clocker_divider0_we $and$ls180.v:6210$1825_Y
+ connect \builder_csrbank8_clocker_divider0_re $and$ls180.v:6205$1821_Y
+ connect \builder_csrbank8_clocker_divider0_we $and$ls180.v:6206$1825_Y
connect \main_sdphy_init_initialize_r \builder_interface8_bank_bus_dat_w [0]
- connect \main_sdphy_init_initialize_re $and$ls180.v:6212$1828_Y
- connect \main_sdphy_init_initialize_we $and$ls180.v:6213$1832_Y
+ connect \main_sdphy_init_initialize_re $and$ls180.v:6208$1828_Y
+ connect \main_sdphy_init_initialize_we $and$ls180.v:6209$1832_Y
connect \builder_csrbank8_card_detect_w \main_sdphy_status
connect \main_sdphy_we \builder_csrbank8_card_detect_we
connect \builder_csrbank8_clocker_divider1_w \main_sdphy_clocker_storage [8]
connect \builder_csrbank8_clocker_divider0_w \main_sdphy_clocker_storage [7:0]
- connect \builder_csrbank9_sel $eq$ls180.v:6218$1833_Y
+ connect \builder_csrbank9_sel $eq$ls180.v:6214$1833_Y
connect \builder_csrbank9_dfii_control0_r \builder_interface9_bank_bus_dat_w [3:0]
- connect \builder_csrbank9_dfii_control0_re $and$ls180.v:6220$1836_Y
- connect \builder_csrbank9_dfii_control0_we $and$ls180.v:6221$1840_Y
+ connect \builder_csrbank9_dfii_control0_re $and$ls180.v:6216$1836_Y
+ connect \builder_csrbank9_dfii_control0_we $and$ls180.v:6217$1840_Y
connect \builder_csrbank9_dfii_pi0_command0_r \builder_interface9_bank_bus_dat_w [5:0]
- connect \builder_csrbank9_dfii_pi0_command0_re $and$ls180.v:6223$1843_Y
- connect \builder_csrbank9_dfii_pi0_command0_we $and$ls180.v:6224$1847_Y
+ connect \builder_csrbank9_dfii_pi0_command0_re $and$ls180.v:6219$1843_Y
+ connect \builder_csrbank9_dfii_pi0_command0_we $and$ls180.v:6220$1847_Y
connect \main_sdram_command_issue_r \builder_interface9_bank_bus_dat_w [0]
- connect \main_sdram_command_issue_re $and$ls180.v:6226$1850_Y
- connect \main_sdram_command_issue_we $and$ls180.v:6227$1854_Y
+ connect \main_sdram_command_issue_re $and$ls180.v:6222$1850_Y
+ connect \main_sdram_command_issue_we $and$ls180.v:6223$1854_Y
connect \builder_csrbank9_dfii_pi0_address1_r \builder_interface9_bank_bus_dat_w [4:0]
- connect \builder_csrbank9_dfii_pi0_address1_re $and$ls180.v:6229$1857_Y
- connect \builder_csrbank9_dfii_pi0_address1_we $and$ls180.v:6230$1861_Y
+ connect \builder_csrbank9_dfii_pi0_address1_re $and$ls180.v:6225$1857_Y
+ connect \builder_csrbank9_dfii_pi0_address1_we $and$ls180.v:6226$1861_Y
connect \builder_csrbank9_dfii_pi0_address0_r \builder_interface9_bank_bus_dat_w
- connect \builder_csrbank9_dfii_pi0_address0_re $and$ls180.v:6232$1864_Y
- connect \builder_csrbank9_dfii_pi0_address0_we $and$ls180.v:6233$1868_Y
+ connect \builder_csrbank9_dfii_pi0_address0_re $and$ls180.v:6228$1864_Y
+ connect \builder_csrbank9_dfii_pi0_address0_we $and$ls180.v:6229$1868_Y
connect \builder_csrbank9_dfii_pi0_baddress0_r \builder_interface9_bank_bus_dat_w [1:0]
- connect \builder_csrbank9_dfii_pi0_baddress0_re $and$ls180.v:6235$1871_Y
- connect \builder_csrbank9_dfii_pi0_baddress0_we $and$ls180.v:6236$1875_Y
+ connect \builder_csrbank9_dfii_pi0_baddress0_re $and$ls180.v:6231$1871_Y
+ connect \builder_csrbank9_dfii_pi0_baddress0_we $and$ls180.v:6232$1875_Y
connect \builder_csrbank9_dfii_pi0_wrdata1_r \builder_interface9_bank_bus_dat_w
- connect \builder_csrbank9_dfii_pi0_wrdata1_re $and$ls180.v:6238$1878_Y
- connect \builder_csrbank9_dfii_pi0_wrdata1_we $and$ls180.v:6239$1882_Y
+ connect \builder_csrbank9_dfii_pi0_wrdata1_re $and$ls180.v:6234$1878_Y
+ connect \builder_csrbank9_dfii_pi0_wrdata1_we $and$ls180.v:6235$1882_Y
connect \builder_csrbank9_dfii_pi0_wrdata0_r \builder_interface9_bank_bus_dat_w
- connect \builder_csrbank9_dfii_pi0_wrdata0_re $and$ls180.v:6241$1885_Y
- connect \builder_csrbank9_dfii_pi0_wrdata0_we $and$ls180.v:6242$1889_Y
+ connect \builder_csrbank9_dfii_pi0_wrdata0_re $and$ls180.v:6237$1885_Y
+ connect \builder_csrbank9_dfii_pi0_wrdata0_we $and$ls180.v:6238$1889_Y
connect \builder_csrbank9_dfii_pi0_rddata1_r \builder_interface9_bank_bus_dat_w
- connect \builder_csrbank9_dfii_pi0_rddata1_re $and$ls180.v:6244$1892_Y
- connect \builder_csrbank9_dfii_pi0_rddata1_we $and$ls180.v:6245$1896_Y
+ connect \builder_csrbank9_dfii_pi0_rddata1_re $and$ls180.v:6240$1892_Y
+ connect \builder_csrbank9_dfii_pi0_rddata1_we $and$ls180.v:6241$1896_Y
connect \builder_csrbank9_dfii_pi0_rddata0_r \builder_interface9_bank_bus_dat_w
- connect \builder_csrbank9_dfii_pi0_rddata0_re $and$ls180.v:6247$1899_Y
- connect \builder_csrbank9_dfii_pi0_rddata0_we $and$ls180.v:6248$1903_Y
+ connect \builder_csrbank9_dfii_pi0_rddata0_re $and$ls180.v:6243$1899_Y
+ connect \builder_csrbank9_dfii_pi0_rddata0_we $and$ls180.v:6244$1903_Y
connect \main_sdram_sel \main_sdram_storage [0]
connect \main_sdram_cke \main_sdram_storage [1]
connect \main_sdram_odt \main_sdram_storage [2]
connect \builder_csrbank9_dfii_pi0_rddata1_w \main_sdram_status [15:8]
connect \builder_csrbank9_dfii_pi0_rddata0_w \main_sdram_status [7:0]
connect \main_sdram_we \builder_csrbank9_dfii_pi0_rddata0_we
- connect \builder_csrbank10_sel $eq$ls180.v:6263$1904_Y
+ connect \builder_csrbank10_sel $eq$ls180.v:6259$1904_Y
connect \builder_csrbank10_control1_r \builder_interface10_bank_bus_dat_w
- connect \builder_csrbank10_control1_re $and$ls180.v:6265$1907_Y
- connect \builder_csrbank10_control1_we $and$ls180.v:6266$1911_Y
+ connect \builder_csrbank10_control1_re $and$ls180.v:6261$1907_Y
+ connect \builder_csrbank10_control1_we $and$ls180.v:6262$1911_Y
connect \builder_csrbank10_control0_r \builder_interface10_bank_bus_dat_w
- connect \builder_csrbank10_control0_re $and$ls180.v:6268$1914_Y
- connect \builder_csrbank10_control0_we $and$ls180.v:6269$1918_Y
+ connect \builder_csrbank10_control0_re $and$ls180.v:6264$1914_Y
+ connect \builder_csrbank10_control0_we $and$ls180.v:6265$1918_Y
connect \builder_csrbank10_status_r \builder_interface10_bank_bus_dat_w [0]
- connect \builder_csrbank10_status_re $and$ls180.v:6271$1921_Y
- connect \builder_csrbank10_status_we $and$ls180.v:6272$1925_Y
+ connect \builder_csrbank10_status_re $and$ls180.v:6267$1921_Y
+ connect \builder_csrbank10_status_we $and$ls180.v:6268$1925_Y
connect \builder_csrbank10_mosi0_r \builder_interface10_bank_bus_dat_w
- connect \builder_csrbank10_mosi0_re $and$ls180.v:6274$1928_Y
- connect \builder_csrbank10_mosi0_we $and$ls180.v:6275$1932_Y
+ connect \builder_csrbank10_mosi0_re $and$ls180.v:6270$1928_Y
+ connect \builder_csrbank10_mosi0_we $and$ls180.v:6271$1932_Y
connect \builder_csrbank10_miso_r \builder_interface10_bank_bus_dat_w
- connect \builder_csrbank10_miso_re $and$ls180.v:6277$1935_Y
- connect \builder_csrbank10_miso_we $and$ls180.v:6278$1939_Y
+ connect \builder_csrbank10_miso_re $and$ls180.v:6273$1935_Y
+ connect \builder_csrbank10_miso_we $and$ls180.v:6274$1939_Y
connect \builder_csrbank10_cs0_r \builder_interface10_bank_bus_dat_w [0]
- connect \builder_csrbank10_cs0_re $and$ls180.v:6280$1942_Y
- connect \builder_csrbank10_cs0_we $and$ls180.v:6281$1946_Y
+ connect \builder_csrbank10_cs0_re $and$ls180.v:6276$1942_Y
+ connect \builder_csrbank10_cs0_we $and$ls180.v:6277$1946_Y
connect \builder_csrbank10_loopback0_r \builder_interface10_bank_bus_dat_w [0]
- connect \builder_csrbank10_loopback0_re $and$ls180.v:6283$1949_Y
- connect \builder_csrbank10_loopback0_we $and$ls180.v:6284$1953_Y
+ connect \builder_csrbank10_loopback0_re $and$ls180.v:6279$1949_Y
+ connect \builder_csrbank10_loopback0_we $and$ls180.v:6280$1953_Y
connect \main_spimaster10_length \main_spimaster11_storage [15:8]
connect \builder_csrbank10_control1_w \main_spimaster11_storage [15:8]
connect \builder_csrbank10_control0_w \main_spimaster11_storage [7:0]
connect \main_spimaster20_sel \main_spimaster21_storage
connect \builder_csrbank10_cs0_w \main_spimaster21_storage
connect \builder_csrbank10_loopback0_w \main_spimaster23_storage
- connect \builder_csrbank11_sel $eq$ls180.v:6303$1955_Y
+ connect \builder_csrbank11_sel $eq$ls180.v:6299$1955_Y
connect \builder_csrbank11_control1_r \builder_interface11_bank_bus_dat_w
- connect \builder_csrbank11_control1_re $and$ls180.v:6305$1958_Y
- connect \builder_csrbank11_control1_we $and$ls180.v:6306$1962_Y
+ connect \builder_csrbank11_control1_re $and$ls180.v:6301$1958_Y
+ connect \builder_csrbank11_control1_we $and$ls180.v:6302$1962_Y
connect \builder_csrbank11_control0_r \builder_interface11_bank_bus_dat_w
- connect \builder_csrbank11_control0_re $and$ls180.v:6308$1965_Y
- connect \builder_csrbank11_control0_we $and$ls180.v:6309$1969_Y
+ connect \builder_csrbank11_control0_re $and$ls180.v:6304$1965_Y
+ connect \builder_csrbank11_control0_we $and$ls180.v:6305$1969_Y
connect \builder_csrbank11_status_r \builder_interface11_bank_bus_dat_w [0]
- connect \builder_csrbank11_status_re $and$ls180.v:6311$1972_Y
- connect \builder_csrbank11_status_we $and$ls180.v:6312$1976_Y
+ connect \builder_csrbank11_status_re $and$ls180.v:6307$1972_Y
+ connect \builder_csrbank11_status_we $and$ls180.v:6308$1976_Y
connect \builder_csrbank11_mosi0_r \builder_interface11_bank_bus_dat_w
- connect \builder_csrbank11_mosi0_re $and$ls180.v:6314$1979_Y
- connect \builder_csrbank11_mosi0_we $and$ls180.v:6315$1983_Y
+ connect \builder_csrbank11_mosi0_re $and$ls180.v:6310$1979_Y
+ connect \builder_csrbank11_mosi0_we $and$ls180.v:6311$1983_Y
connect \builder_csrbank11_miso_r \builder_interface11_bank_bus_dat_w
- connect \builder_csrbank11_miso_re $and$ls180.v:6317$1986_Y
- connect \builder_csrbank11_miso_we $and$ls180.v:6318$1990_Y
+ connect \builder_csrbank11_miso_re $and$ls180.v:6313$1986_Y
+ connect \builder_csrbank11_miso_we $and$ls180.v:6314$1990_Y
connect \builder_csrbank11_cs0_r \builder_interface11_bank_bus_dat_w [0]
- connect \builder_csrbank11_cs0_re $and$ls180.v:6320$1993_Y
- connect \builder_csrbank11_cs0_we $and$ls180.v:6321$1997_Y
+ connect \builder_csrbank11_cs0_re $and$ls180.v:6316$1993_Y
+ connect \builder_csrbank11_cs0_we $and$ls180.v:6317$1997_Y
connect \builder_csrbank11_loopback0_r \builder_interface11_bank_bus_dat_w [0]
- connect \builder_csrbank11_loopback0_re $and$ls180.v:6323$2000_Y
- connect \builder_csrbank11_loopback0_we $and$ls180.v:6324$2004_Y
+ connect \builder_csrbank11_loopback0_re $and$ls180.v:6319$2000_Y
+ connect \builder_csrbank11_loopback0_we $and$ls180.v:6320$2004_Y
connect \builder_csrbank11_clk_divider1_r \builder_interface11_bank_bus_dat_w
- connect \builder_csrbank11_clk_divider1_re $and$ls180.v:6326$2007_Y
- connect \builder_csrbank11_clk_divider1_we $and$ls180.v:6327$2011_Y
+ connect \builder_csrbank11_clk_divider1_re $and$ls180.v:6322$2007_Y
+ connect \builder_csrbank11_clk_divider1_we $and$ls180.v:6323$2011_Y
connect \builder_csrbank11_clk_divider0_r \builder_interface11_bank_bus_dat_w
- connect \builder_csrbank11_clk_divider0_re $and$ls180.v:6329$2014_Y
- connect \builder_csrbank11_clk_divider0_we $and$ls180.v:6330$2018_Y
+ connect \builder_csrbank11_clk_divider0_re $and$ls180.v:6325$2014_Y
+ connect \builder_csrbank11_clk_divider0_we $and$ls180.v:6326$2018_Y
connect \main_spisdcard_length1 \main_spisdcard_control_storage [15:8]
connect \builder_csrbank11_control1_w \main_spisdcard_control_storage [15:8]
connect \builder_csrbank11_control0_w \main_spisdcard_control_storage [7:0]
connect \builder_csrbank11_loopback0_w \main_spisdcard_loopback_storage
connect \builder_csrbank11_clk_divider1_w \main_spimaster1_storage [15:8]
connect \builder_csrbank11_clk_divider0_w \main_spimaster1_storage [7:0]
- connect \builder_csrbank12_sel $eq$ls180.v:6351$2020_Y
+ connect \builder_csrbank12_sel $eq$ls180.v:6347$2020_Y
connect \builder_csrbank12_load3_r \builder_interface12_bank_bus_dat_w
- connect \builder_csrbank12_load3_re $and$ls180.v:6353$2023_Y
- connect \builder_csrbank12_load3_we $and$ls180.v:6354$2027_Y
+ connect \builder_csrbank12_load3_re $and$ls180.v:6349$2023_Y
+ connect \builder_csrbank12_load3_we $and$ls180.v:6350$2027_Y
connect \builder_csrbank12_load2_r \builder_interface12_bank_bus_dat_w
- connect \builder_csrbank12_load2_re $and$ls180.v:6356$2030_Y
- connect \builder_csrbank12_load2_we $and$ls180.v:6357$2034_Y
+ connect \builder_csrbank12_load2_re $and$ls180.v:6352$2030_Y
+ connect \builder_csrbank12_load2_we $and$ls180.v:6353$2034_Y
connect \builder_csrbank12_load1_r \builder_interface12_bank_bus_dat_w
- connect \builder_csrbank12_load1_re $and$ls180.v:6359$2037_Y
- connect \builder_csrbank12_load1_we $and$ls180.v:6360$2041_Y
+ connect \builder_csrbank12_load1_re $and$ls180.v:6355$2037_Y
+ connect \builder_csrbank12_load1_we $and$ls180.v:6356$2041_Y
connect \builder_csrbank12_load0_r \builder_interface12_bank_bus_dat_w
- connect \builder_csrbank12_load0_re $and$ls180.v:6362$2044_Y
- connect \builder_csrbank12_load0_we $and$ls180.v:6363$2048_Y
+ connect \builder_csrbank12_load0_re $and$ls180.v:6358$2044_Y
+ connect \builder_csrbank12_load0_we $and$ls180.v:6359$2048_Y
connect \builder_csrbank12_reload3_r \builder_interface12_bank_bus_dat_w
- connect \builder_csrbank12_reload3_re $and$ls180.v:6365$2051_Y
- connect \builder_csrbank12_reload3_we $and$ls180.v:6366$2055_Y
+ connect \builder_csrbank12_reload3_re $and$ls180.v:6361$2051_Y
+ connect \builder_csrbank12_reload3_we $and$ls180.v:6362$2055_Y
connect \builder_csrbank12_reload2_r \builder_interface12_bank_bus_dat_w
- connect \builder_csrbank12_reload2_re $and$ls180.v:6368$2058_Y
- connect \builder_csrbank12_reload2_we $and$ls180.v:6369$2062_Y
+ connect \builder_csrbank12_reload2_re $and$ls180.v:6364$2058_Y
+ connect \builder_csrbank12_reload2_we $and$ls180.v:6365$2062_Y
connect \builder_csrbank12_reload1_r \builder_interface12_bank_bus_dat_w
- connect \builder_csrbank12_reload1_re $and$ls180.v:6371$2065_Y
- connect \builder_csrbank12_reload1_we $and$ls180.v:6372$2069_Y
+ connect \builder_csrbank12_reload1_re $and$ls180.v:6367$2065_Y
+ connect \builder_csrbank12_reload1_we $and$ls180.v:6368$2069_Y
connect \builder_csrbank12_reload0_r \builder_interface12_bank_bus_dat_w
- connect \builder_csrbank12_reload0_re $and$ls180.v:6374$2072_Y
- connect \builder_csrbank12_reload0_we $and$ls180.v:6375$2076_Y
+ connect \builder_csrbank12_reload0_re $and$ls180.v:6370$2072_Y
+ connect \builder_csrbank12_reload0_we $and$ls180.v:6371$2076_Y
connect \builder_csrbank12_en0_r \builder_interface12_bank_bus_dat_w [0]
- connect \builder_csrbank12_en0_re $and$ls180.v:6377$2079_Y
- connect \builder_csrbank12_en0_we $and$ls180.v:6378$2083_Y
+ connect \builder_csrbank12_en0_re $and$ls180.v:6373$2079_Y
+ connect \builder_csrbank12_en0_we $and$ls180.v:6374$2083_Y
connect \builder_csrbank12_update_value0_r \builder_interface12_bank_bus_dat_w [0]
- connect \builder_csrbank12_update_value0_re $and$ls180.v:6380$2086_Y
- connect \builder_csrbank12_update_value0_we $and$ls180.v:6381$2090_Y
+ connect \builder_csrbank12_update_value0_re $and$ls180.v:6376$2086_Y
+ connect \builder_csrbank12_update_value0_we $and$ls180.v:6377$2090_Y
connect \builder_csrbank12_value3_r \builder_interface12_bank_bus_dat_w
- connect \builder_csrbank12_value3_re $and$ls180.v:6383$2093_Y
- connect \builder_csrbank12_value3_we $and$ls180.v:6384$2097_Y
+ connect \builder_csrbank12_value3_re $and$ls180.v:6379$2093_Y
+ connect \builder_csrbank12_value3_we $and$ls180.v:6380$2097_Y
connect \builder_csrbank12_value2_r \builder_interface12_bank_bus_dat_w
- connect \builder_csrbank12_value2_re $and$ls180.v:6386$2100_Y
- connect \builder_csrbank12_value2_we $and$ls180.v:6387$2104_Y
+ connect \builder_csrbank12_value2_re $and$ls180.v:6382$2100_Y
+ connect \builder_csrbank12_value2_we $and$ls180.v:6383$2104_Y
connect \builder_csrbank12_value1_r \builder_interface12_bank_bus_dat_w
- connect \builder_csrbank12_value1_re $and$ls180.v:6389$2107_Y
- connect \builder_csrbank12_value1_we $and$ls180.v:6390$2111_Y
+ connect \builder_csrbank12_value1_re $and$ls180.v:6385$2107_Y
+ connect \builder_csrbank12_value1_we $and$ls180.v:6386$2111_Y
connect \builder_csrbank12_value0_r \builder_interface12_bank_bus_dat_w
- connect \builder_csrbank12_value0_re $and$ls180.v:6392$2114_Y
- connect \builder_csrbank12_value0_we $and$ls180.v:6393$2118_Y
+ connect \builder_csrbank12_value0_re $and$ls180.v:6388$2114_Y
+ connect \builder_csrbank12_value0_we $and$ls180.v:6389$2118_Y
connect \main_libresocsim_eventmanager_status_r \builder_interface12_bank_bus_dat_w [0]
- connect \main_libresocsim_eventmanager_status_re $and$ls180.v:6395$2121_Y
- connect \main_libresocsim_eventmanager_status_we $and$ls180.v:6396$2125_Y
+ connect \main_libresocsim_eventmanager_status_re $and$ls180.v:6391$2121_Y
+ connect \main_libresocsim_eventmanager_status_we $and$ls180.v:6392$2125_Y
connect \main_libresocsim_eventmanager_pending_r \builder_interface12_bank_bus_dat_w [0]
- connect \main_libresocsim_eventmanager_pending_re $and$ls180.v:6398$2128_Y
- connect \main_libresocsim_eventmanager_pending_we $and$ls180.v:6399$2132_Y
+ connect \main_libresocsim_eventmanager_pending_re $and$ls180.v:6394$2128_Y
+ connect \main_libresocsim_eventmanager_pending_we $and$ls180.v:6395$2132_Y
connect \builder_csrbank12_ev_enable0_r \builder_interface12_bank_bus_dat_w [0]
- connect \builder_csrbank12_ev_enable0_re $and$ls180.v:6401$2135_Y
- connect \builder_csrbank12_ev_enable0_we $and$ls180.v:6402$2139_Y
+ connect \builder_csrbank12_ev_enable0_re $and$ls180.v:6397$2135_Y
+ connect \builder_csrbank12_ev_enable0_we $and$ls180.v:6398$2139_Y
connect \builder_csrbank12_load3_w \main_libresocsim_load_storage [31:24]
connect \builder_csrbank12_load2_w \main_libresocsim_load_storage [23:16]
connect \builder_csrbank12_load1_w \main_libresocsim_load_storage [15:8]
connect \builder_csrbank12_value0_w \main_libresocsim_value_status [7:0]
connect \main_libresocsim_value_we \builder_csrbank12_value0_we
connect \builder_csrbank12_ev_enable0_w \main_libresocsim_eventmanager_storage
- connect \builder_csrbank13_sel $eq$ls180.v:6419$2140_Y
+ connect \builder_csrbank13_sel $eq$ls180.v:6415$2140_Y
connect \main_uart_rxtx_r \builder_interface13_bank_bus_dat_w
- connect \main_uart_rxtx_re $and$ls180.v:6421$2143_Y
- connect \main_uart_rxtx_we $and$ls180.v:6422$2147_Y
+ connect \main_uart_rxtx_re $and$ls180.v:6417$2143_Y
+ connect \main_uart_rxtx_we $and$ls180.v:6418$2147_Y
connect \builder_csrbank13_txfull_r \builder_interface13_bank_bus_dat_w [0]
- connect \builder_csrbank13_txfull_re $and$ls180.v:6424$2150_Y
- connect \builder_csrbank13_txfull_we $and$ls180.v:6425$2154_Y
+ connect \builder_csrbank13_txfull_re $and$ls180.v:6420$2150_Y
+ connect \builder_csrbank13_txfull_we $and$ls180.v:6421$2154_Y
connect \builder_csrbank13_rxempty_r \builder_interface13_bank_bus_dat_w [0]
- connect \builder_csrbank13_rxempty_re $and$ls180.v:6427$2157_Y
- connect \builder_csrbank13_rxempty_we $and$ls180.v:6428$2161_Y
+ connect \builder_csrbank13_rxempty_re $and$ls180.v:6423$2157_Y
+ connect \builder_csrbank13_rxempty_we $and$ls180.v:6424$2161_Y
connect \main_uart_eventmanager_status_r \builder_interface13_bank_bus_dat_w [1:0]
- connect \main_uart_eventmanager_status_re $and$ls180.v:6430$2164_Y
- connect \main_uart_eventmanager_status_we $and$ls180.v:6431$2168_Y
+ connect \main_uart_eventmanager_status_re $and$ls180.v:6426$2164_Y
+ connect \main_uart_eventmanager_status_we $and$ls180.v:6427$2168_Y
connect \main_uart_eventmanager_pending_r \builder_interface13_bank_bus_dat_w [1:0]
- connect \main_uart_eventmanager_pending_re $and$ls180.v:6433$2171_Y
- connect \main_uart_eventmanager_pending_we $and$ls180.v:6434$2175_Y
+ connect \main_uart_eventmanager_pending_re $and$ls180.v:6429$2171_Y
+ connect \main_uart_eventmanager_pending_we $and$ls180.v:6430$2175_Y
connect \builder_csrbank13_ev_enable0_r \builder_interface13_bank_bus_dat_w [1:0]
- connect \builder_csrbank13_ev_enable0_re $and$ls180.v:6436$2178_Y
- connect \builder_csrbank13_ev_enable0_we $and$ls180.v:6437$2182_Y
+ connect \builder_csrbank13_ev_enable0_re $and$ls180.v:6432$2178_Y
+ connect \builder_csrbank13_ev_enable0_we $and$ls180.v:6433$2182_Y
connect \builder_csrbank13_txempty_r \builder_interface13_bank_bus_dat_w [0]
- connect \builder_csrbank13_txempty_re $and$ls180.v:6439$2185_Y
- connect \builder_csrbank13_txempty_we $and$ls180.v:6440$2189_Y
+ connect \builder_csrbank13_txempty_re $and$ls180.v:6435$2185_Y
+ connect \builder_csrbank13_txempty_we $and$ls180.v:6436$2189_Y
connect \builder_csrbank13_rxfull_r \builder_interface13_bank_bus_dat_w [0]
- connect \builder_csrbank13_rxfull_re $and$ls180.v:6442$2192_Y
- connect \builder_csrbank13_rxfull_we $and$ls180.v:6443$2196_Y
+ connect \builder_csrbank13_rxfull_re $and$ls180.v:6438$2192_Y
+ connect \builder_csrbank13_rxfull_we $and$ls180.v:6439$2196_Y
connect \builder_csrbank13_txfull_w \main_uart_txfull_status
connect \main_uart_txfull_we \builder_csrbank13_txfull_we
connect \builder_csrbank13_rxempty_w \main_uart_rxempty_status
connect \main_uart_txempty_we \builder_csrbank13_txempty_we
connect \builder_csrbank13_rxfull_w \main_uart_rxfull_status
connect \main_uart_rxfull_we \builder_csrbank13_rxfull_we
- connect \builder_csrbank14_sel $eq$ls180.v:6453$2197_Y
+ connect \builder_csrbank14_sel $eq$ls180.v:6449$2197_Y
connect \builder_csrbank14_tuning_word3_r \builder_interface14_bank_bus_dat_w
- connect \builder_csrbank14_tuning_word3_re $and$ls180.v:6455$2200_Y
- connect \builder_csrbank14_tuning_word3_we $and$ls180.v:6456$2204_Y
+ connect \builder_csrbank14_tuning_word3_re $and$ls180.v:6451$2200_Y
+ connect \builder_csrbank14_tuning_word3_we $and$ls180.v:6452$2204_Y
connect \builder_csrbank14_tuning_word2_r \builder_interface14_bank_bus_dat_w
- connect \builder_csrbank14_tuning_word2_re $and$ls180.v:6458$2207_Y
- connect \builder_csrbank14_tuning_word2_we $and$ls180.v:6459$2211_Y
+ connect \builder_csrbank14_tuning_word2_re $and$ls180.v:6454$2207_Y
+ connect \builder_csrbank14_tuning_word2_we $and$ls180.v:6455$2211_Y
connect \builder_csrbank14_tuning_word1_r \builder_interface14_bank_bus_dat_w
- connect \builder_csrbank14_tuning_word1_re $and$ls180.v:6461$2214_Y
- connect \builder_csrbank14_tuning_word1_we $and$ls180.v:6462$2218_Y
+ connect \builder_csrbank14_tuning_word1_re $and$ls180.v:6457$2214_Y
+ connect \builder_csrbank14_tuning_word1_we $and$ls180.v:6458$2218_Y
connect \builder_csrbank14_tuning_word0_r \builder_interface14_bank_bus_dat_w
- connect \builder_csrbank14_tuning_word0_re $and$ls180.v:6464$2221_Y
- connect \builder_csrbank14_tuning_word0_we $and$ls180.v:6465$2225_Y
+ connect \builder_csrbank14_tuning_word0_re $and$ls180.v:6460$2221_Y
+ connect \builder_csrbank14_tuning_word0_we $and$ls180.v:6461$2225_Y
connect \builder_csrbank14_tuning_word3_w \main_uart_phy_storage [31:24]
connect \builder_csrbank14_tuning_word2_w \main_uart_phy_storage [23:16]
connect \builder_csrbank14_tuning_word1_w \main_uart_phy_storage [15:8]
connect \builder_interface12_bank_bus_dat_w \builder_csr_interconnect_dat_w
connect \builder_interface13_bank_bus_dat_w \builder_csr_interconnect_dat_w
connect \builder_interface14_bank_bus_dat_w \builder_csr_interconnect_dat_w
- connect \builder_csr_interconnect_dat_r $or$ls180.v:6519$2239_Y
+ connect \builder_csr_interconnect_dat_r $or$ls180.v:6515$2239_Y
connect \sdrio_clk \sys_clk_1
connect \sdrio_clk_1 \sys_clk_1
connect \sdrio_clk_2 \sys_clk_1
connect \sdrio_clk_66 \sys_clk_1
connect \sdrio_clk_67 \sys_clk_1
connect \sdrio_clk_68 \sys_clk_1
- connect \main_libresocsim_dat_r $memrd$\mem$ls180.v:10059$2693_DATA
+ connect \main_libresocsim_dat_r $memrd$\mem$ls180.v:10055$2693_DATA
connect \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_r \memdat
- connect \main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage$ls180.v:10077$2700_DATA
+ connect \main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage$ls180.v:10073$2700_DATA
connect \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_r \memdat_1
- connect \main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage_1$ls180.v:10091$2707_DATA
+ connect \main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage_1$ls180.v:10087$2707_DATA
connect \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_r \memdat_2
- connect \main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage_2$ls180.v:10105$2714_DATA
+ connect \main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage_2$ls180.v:10101$2714_DATA
connect \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_r \memdat_3
- connect \main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage_3$ls180.v:10119$2721_DATA
+ connect \main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage_3$ls180.v:10115$2721_DATA
connect \main_uart_tx_fifo_wrport_dat_r \memdat_4
connect \main_uart_tx_fifo_rdport_dat_r \memdat_5
connect \main_uart_rx_fifo_wrport_dat_r \memdat_6
connect \main_uart_rx_fifo_rdport_dat_r \memdat_7
connect \main_sdblock2mem_fifo_wrport_dat_r \memdat_8
- connect \main_sdblock2mem_fifo_rdport_dat_r $memrd$\storage_6$ls180.v:10167$2742_DATA
+ connect \main_sdblock2mem_fifo_rdport_dat_r $memrd$\storage_6$ls180.v:10163$2742_DATA
connect \main_sdmem2block_fifo_wrport_dat_r \memdat_9
- connect \main_sdmem2block_fifo_rdport_dat_r $memrd$\storage_7$ls180.v:10181$2749_DATA
+ connect \main_sdmem2block_fifo_rdport_dat_r $memrd$\storage_7$ls180.v:10177$2749_DATA
end
attribute \src "libresoc.v:45741.1-45785.10"
attribute \cells_not_processed 1
update \spr_o_ok $0\spr_o_ok[0:0]
end
end
-attribute \src "libresoc.v:47604.1-48736.10"
+attribute \src "libresoc.v:47604.1-48728.10"
attribute \cells_not_processed 1
attribute \top 1
attribute \nmigen.hierarchy "test_issuer"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:105"
wire output 5 \busy_o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168"
- wire input 372 \clk
+ wire input 368 \clk
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:10"
- wire width 2 input 374 \clk_sel_i
+ wire width 2 input 370 \clk_sel_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:104"
wire input 4 \core_bigendian_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32"
wire width 45 input 338 \dbus__adr
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32"
- wire width 2 input 347 \dbus__bte
+ wire width 2 input 348 \dbus__bte
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32"
- wire width 3 input 346 \dbus__cti
+ wire width 3 input 347 \dbus__cti
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32"
wire input 342 \dbus__cyc
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32"
wire width 64 input 339 \dbus__dat_w
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32"
- wire input 348 \dbus__err
+ wire input 346 \dbus__err
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32"
wire width 8 input 341 \dbus__sel
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20"
wire width 45 output 327 \ibus__adr
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20"
- wire width 2 input 336 \ibus__bte
+ wire width 2 input 337 \ibus__bte
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20"
- wire width 3 input 335 \ibus__cti
+ wire width 3 input 336 \ibus__cti
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20"
wire output 331 \ibus__cyc
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20"
wire width 64 input 328 \ibus__dat_w
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20"
- wire input 337 \ibus__err
+ wire input 335 \ibus__err
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20"
wire width 8 output 330 \ibus__sel
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81"
wire width 28 input 349 \icp_wb__adr
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81"
- wire width 2 input 358 \icp_wb__bte
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81"
- wire width 3 input 357 \icp_wb__cti
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81"
wire input 353 \icp_wb__cyc
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81"
wire width 32 output 351 \icp_wb__dat_r
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81"
wire width 32 input 350 \icp_wb__dat_w
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81"
- wire input 359 \icp_wb__err
+ wire input 357 \icp_wb__err
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81"
wire width 4 input 352 \icp_wb__sel
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81"
wire input 356 \icp_wb__we
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235"
- wire output 366 \ics_wb__ack
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235"
- wire width 28 input 360 \ics_wb__adr
+ wire output 364 \ics_wb__ack
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235"
- wire width 2 input 369 \ics_wb__bte
+ wire width 28 input 358 \ics_wb__adr
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235"
- wire width 3 input 368 \ics_wb__cti
+ wire input 362 \ics_wb__cyc
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235"
- wire input 364 \ics_wb__cyc
+ wire width 32 output 360 \ics_wb__dat_r
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235"
- wire width 32 output 362 \ics_wb__dat_r
+ wire width 32 input 359 \ics_wb__dat_w
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235"
- wire width 32 input 361 \ics_wb__dat_w
+ wire input 366 \ics_wb__err
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235"
- wire input 370 \ics_wb__err
+ wire width 4 input 361 \ics_wb__sel
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235"
- wire width 4 input 363 \ics_wb__sel
+ wire input 363 \ics_wb__stb
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235"
- wire input 365 \ics_wb__stb
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235"
- wire input 367 \ics_wb__we
+ wire input 365 \ics_wb__we
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:237"
- wire width 16 input 371 \int_level_i
+ wire width 16 input 367 \int_level_i
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740"
wire input 17 \jtag_wb__ack
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
wire output 142 \mtwi_sda__pad__oe
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
- wire width 64 input 377 \pc_i
+ wire width 64 input 373 \pc_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire input 1 \pc_i_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:102"
wire width 64 output 2 \pc_o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:467"
- wire output 375 \pll_18_o
+ wire output 371 \pll_18_o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:9"
wire \pll_clk_24_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:11"
wire \pll_clk_pll_o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:13"
- wire output 376 \pll_lck_o
+ wire output 372 \pll_lck_o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:12"
wire \pll_pll_18_o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:482"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
wire output 148 \pwm_1__pad__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168"
- wire input 373 \rst
+ wire input 369 \rst
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
wire input 155 \sd0_clk__core__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169"
wire \ti_coresync_clk
attribute \module_not_derived 1
- attribute \src "libresoc.v:48371.7-48377.4"
+ attribute \src "libresoc.v:48363.7-48369.4"
cell \pll \pll
connect \clk_24_i \pll_clk_24_i
connect \clk_pll_o \pll_clk_pll_o
connect \pll_lck_o \pll_lck_o
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:48378.6-48730.4"
+ attribute \src "libresoc.v:48370.6-48722.4"
cell \ti \ti
connect \TAP_bus__tck \TAP_bus__tck
connect \TAP_bus__tdi \TAP_bus__tdi
connect \pll_clk_24_i \clk
connect \pllclk_clk \pll_clk_pll_o
end
-attribute \src "libresoc.v:48740.1-52518.10"
+attribute \src "libresoc.v:48732.1-52510.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti"
attribute \generator "nMigen"
module \ti
- attribute \src "libresoc.v:52250.3-52286.6"
+ attribute \src "libresoc.v:52242.3-52278.6"
wire $0\bigendian_i$next[0:0]$2136
- attribute \src "libresoc.v:50867.3-50868.39"
+ attribute \src "libresoc.v:50859.3-50860.39"
wire $0\bigendian_i[0:0]
- attribute \src "libresoc.v:51948.3-51960.6"
+ attribute \src "libresoc.v:51940.3-51952.6"
wire width 4 $0\cia__ren[3:0]
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire width 8 $0\core_asmcode$next[7:0]$1854
- attribute \src "libresoc.v:50871.3-50872.41"
+ attribute \src "libresoc.v:50863.3-50864.41"
wire width 8 $0\core_asmcode[7:0]
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire width 64 $0\core_core_cia$next[63:0]$1855
- attribute \src "libresoc.v:50947.3-50948.43"
+ attribute \src "libresoc.v:50939.3-50940.43"
wire width 64 $0\core_core_cia[63:0]
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire width 8 $0\core_core_cr_rd$next[7:0]$1856
- attribute \src "libresoc.v:50991.3-50992.47"
+ attribute \src "libresoc.v:50983.3-50984.47"
wire width 8 $0\core_core_cr_rd[7:0]
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire $0\core_core_cr_rd_ok$next[0:0]$1857
- attribute \src "libresoc.v:50993.3-50994.53"
+ attribute \src "libresoc.v:50985.3-50986.53"
wire $0\core_core_cr_rd_ok[0:0]
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire width 8 $0\core_core_cr_wr$next[7:0]$1858
- attribute \src "libresoc.v:50995.3-50996.47"
+ attribute \src "libresoc.v:50987.3-50988.47"
wire width 8 $0\core_core_cr_wr[7:0]
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire $0\core_core_cr_wr_ok$next[0:0]$1859
- attribute \src "libresoc.v:50997.3-50998.53"
+ attribute \src "libresoc.v:50989.3-50990.53"
wire $0\core_core_cr_wr_ok[0:0]
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire $0\core_core_exc_$signal$50$next[0:0]$1860
- attribute \src "libresoc.v:50973.3-50974.67"
+ attribute \src "libresoc.v:50965.3-50966.67"
wire $0\core_core_exc_$signal$50[0:0]$1729
- attribute \src "libresoc.v:48913.7-48913.40"
+ attribute \src "libresoc.v:48905.7-48905.40"
wire $0\core_core_exc_$signal$50[0:0]$2175
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire $0\core_core_exc_$signal$51$next[0:0]$1861
- attribute \src "libresoc.v:50975.3-50976.67"
+ attribute \src "libresoc.v:50967.3-50968.67"
wire $0\core_core_exc_$signal$51[0:0]$1731
- attribute \src "libresoc.v:48917.7-48917.40"
+ attribute \src "libresoc.v:48909.7-48909.40"
wire $0\core_core_exc_$signal$51[0:0]$2177
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire $0\core_core_exc_$signal$52$next[0:0]$1862
- attribute \src "libresoc.v:50977.3-50978.67"
+ attribute \src "libresoc.v:50969.3-50970.67"
wire $0\core_core_exc_$signal$52[0:0]$1733
- attribute \src "libresoc.v:48921.7-48921.40"
+ attribute \src "libresoc.v:48913.7-48913.40"
wire $0\core_core_exc_$signal$52[0:0]$2179
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire $0\core_core_exc_$signal$53$next[0:0]$1863
- attribute \src "libresoc.v:50979.3-50980.67"
+ attribute \src "libresoc.v:50971.3-50972.67"
wire $0\core_core_exc_$signal$53[0:0]$1735
- attribute \src "libresoc.v:48925.7-48925.40"
+ attribute \src "libresoc.v:48917.7-48917.40"
wire $0\core_core_exc_$signal$53[0:0]$2181
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire $0\core_core_exc_$signal$54$next[0:0]$1864
- attribute \src "libresoc.v:50981.3-50982.67"
+ attribute \src "libresoc.v:50973.3-50974.67"
wire $0\core_core_exc_$signal$54[0:0]$1737
- attribute \src "libresoc.v:48929.7-48929.40"
+ attribute \src "libresoc.v:48921.7-48921.40"
wire $0\core_core_exc_$signal$54[0:0]$2183
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire $0\core_core_exc_$signal$55$next[0:0]$1865
- attribute \src "libresoc.v:50983.3-50984.67"
+ attribute \src "libresoc.v:50975.3-50976.67"
wire $0\core_core_exc_$signal$55[0:0]$1739
- attribute \src "libresoc.v:48933.7-48933.40"
+ attribute \src "libresoc.v:48925.7-48925.40"
wire $0\core_core_exc_$signal$55[0:0]$2185
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire $0\core_core_exc_$signal$56$next[0:0]$1866
- attribute \src "libresoc.v:50985.3-50986.67"
+ attribute \src "libresoc.v:50977.3-50978.67"
wire $0\core_core_exc_$signal$56[0:0]$1741
- attribute \src "libresoc.v:48937.7-48937.40"
+ attribute \src "libresoc.v:48929.7-48929.40"
wire $0\core_core_exc_$signal$56[0:0]$2187
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire $0\core_core_exc_$signal$next[0:0]$1867
- attribute \src "libresoc.v:50971.3-50972.61"
+ attribute \src "libresoc.v:50963.3-50964.61"
wire $0\core_core_exc_$signal[0:0]$1727
- attribute \src "libresoc.v:48911.7-48911.37"
+ attribute \src "libresoc.v:48903.7-48903.37"
wire $0\core_core_exc_$signal[0:0]$2173
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire width 12 $0\core_core_fn_unit$next[11:0]$1868
- attribute \src "libresoc.v:50953.3-50954.51"
+ attribute \src "libresoc.v:50945.3-50946.51"
wire width 12 $0\core_core_fn_unit[11:0]
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire width 2 $0\core_core_input_carry$next[1:0]$1869
- attribute \src "libresoc.v:50967.3-50968.59"
+ attribute \src "libresoc.v:50959.3-50960.59"
wire width 2 $0\core_core_input_carry[1:0]
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire width 32 $0\core_core_insn$next[31:0]$1870
- attribute \src "libresoc.v:50949.3-50950.45"
+ attribute \src "libresoc.v:50941.3-50942.45"
wire width 32 $0\core_core_insn[31:0]
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire width 7 $0\core_core_insn_type$next[6:0]$1871
- attribute \src "libresoc.v:50951.3-50952.55"
+ attribute \src "libresoc.v:50943.3-50944.55"
wire width 7 $0\core_core_insn_type[6:0]
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire $0\core_core_is_32bit$next[0:0]$1872
- attribute \src "libresoc.v:50999.3-51000.53"
+ attribute \src "libresoc.v:50991.3-50992.53"
wire $0\core_core_is_32bit[0:0]
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire $0\core_core_lk$next[0:0]$1873
- attribute \src "libresoc.v:50955.3-50956.41"
+ attribute \src "libresoc.v:50947.3-50948.41"
wire $0\core_core_lk[0:0]
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire width 64 $0\core_core_msr$next[63:0]$1874
- attribute \src "libresoc.v:50945.3-50946.43"
+ attribute \src "libresoc.v:50937.3-50938.43"
wire width 64 $0\core_core_msr[63:0]
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire $0\core_core_oe$next[0:0]$1875
- attribute \src "libresoc.v:50961.3-50962.41"
+ attribute \src "libresoc.v:50953.3-50954.41"
wire $0\core_core_oe[0:0]
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire $0\core_core_oe_ok$next[0:0]$1876
- attribute \src "libresoc.v:50963.3-50964.47"
+ attribute \src "libresoc.v:50955.3-50956.47"
wire $0\core_core_oe_ok[0:0]
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire $0\core_core_rc$next[0:0]$1877
- attribute \src "libresoc.v:50957.3-50958.41"
+ attribute \src "libresoc.v:50949.3-50950.41"
wire $0\core_core_rc[0:0]
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire $0\core_core_rc_ok$next[0:0]$1878
- attribute \src "libresoc.v:50959.3-50960.47"
+ attribute \src "libresoc.v:50951.3-50952.47"
wire $0\core_core_rc_ok[0:0]
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire width 13 $0\core_core_trapaddr$next[12:0]$1879
- attribute \src "libresoc.v:50989.3-50990.53"
+ attribute \src "libresoc.v:50981.3-50982.53"
wire width 13 $0\core_core_trapaddr[12:0]
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire width 8 $0\core_core_traptype$next[7:0]$1880
- attribute \src "libresoc.v:50969.3-50970.53"
+ attribute \src "libresoc.v:50961.3-50962.53"
wire width 8 $0\core_core_traptype[7:0]
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire width 3 $0\core_cr_in1$next[2:0]$1881
- attribute \src "libresoc.v:50927.3-50928.39"
+ attribute \src "libresoc.v:50919.3-50920.39"
wire width 3 $0\core_cr_in1[2:0]
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire $0\core_cr_in1_ok$next[0:0]$1882
- attribute \src "libresoc.v:50929.3-50930.45"
+ attribute \src "libresoc.v:50921.3-50922.45"
wire $0\core_cr_in1_ok[0:0]
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire width 3 $0\core_cr_in2$48$next[2:0]$1883
- attribute \src "libresoc.v:50935.3-50936.47"
+ attribute \src "libresoc.v:50927.3-50928.47"
wire width 3 $0\core_cr_in2$48[2:0]$1707
- attribute \src "libresoc.v:49098.13-49098.36"
+ attribute \src "libresoc.v:49090.13-49090.36"
wire width 3 $0\core_cr_in2$48[2:0]$2205
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire width 3 $0\core_cr_in2$next[2:0]$1884
- attribute \src "libresoc.v:50931.3-50932.39"
+ attribute \src "libresoc.v:50923.3-50924.39"
wire width 3 $0\core_cr_in2[2:0]
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire $0\core_cr_in2_ok$49$next[0:0]$1885
- attribute \src "libresoc.v:50937.3-50938.53"
+ attribute \src "libresoc.v:50929.3-50930.53"
wire $0\core_cr_in2_ok$49[0:0]$1709
- attribute \src "libresoc.v:49106.7-49106.33"
+ attribute \src "libresoc.v:49098.7-49098.33"
wire $0\core_cr_in2_ok$49[0:0]$2208
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire $0\core_cr_in2_ok$next[0:0]$1886
- attribute \src "libresoc.v:50933.3-50934.45"
+ attribute \src "libresoc.v:50925.3-50926.45"
wire $0\core_cr_in2_ok[0:0]
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire width 3 $0\core_cr_out$next[2:0]$1887
- attribute \src "libresoc.v:50939.3-50940.39"
+ attribute \src "libresoc.v:50931.3-50932.39"
wire width 3 $0\core_cr_out[2:0]
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire $0\core_cr_out_ok$next[0:0]$1888
- attribute \src "libresoc.v:50941.3-50942.45"
+ attribute \src "libresoc.v:50933.3-50934.45"
wire $0\core_cr_out_ok[0:0]
- attribute \src "libresoc.v:51559.3-51590.6"
+ attribute \src "libresoc.v:51551.3-51582.6"
wire width 64 $0\core_dec$next[63:0]$1775
- attribute \src "libresoc.v:50857.3-50858.33"
+ attribute \src "libresoc.v:50849.3-50850.33"
wire width 64 $0\core_dec[63:0]
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire width 5 $0\core_ea$next[4:0]$1889
- attribute \src "libresoc.v:50879.3-50880.31"
+ attribute \src "libresoc.v:50871.3-50872.31"
wire width 5 $0\core_ea[4:0]
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire $0\core_ea_ok$next[0:0]$1890
- attribute \src "libresoc.v:50881.3-50882.37"
+ attribute \src "libresoc.v:50873.3-50874.37"
wire $0\core_ea_ok[0:0]
- attribute \src "libresoc.v:51559.3-51590.6"
+ attribute \src "libresoc.v:51551.3-51582.6"
wire $0\core_eint$next[0:0]$1776
- attribute \src "libresoc.v:51025.3-51026.35"
+ attribute \src "libresoc.v:51017.3-51018.35"
wire $0\core_eint[0:0]
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire width 3 $0\core_fast1$next[2:0]$1891
- attribute \src "libresoc.v:50909.3-50910.37"
+ attribute \src "libresoc.v:50901.3-50902.37"
wire width 3 $0\core_fast1[2:0]
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire $0\core_fast1_ok$next[0:0]$1892
- attribute \src "libresoc.v:50911.3-50912.43"
+ attribute \src "libresoc.v:50903.3-50904.43"
wire $0\core_fast1_ok[0:0]
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire width 3 $0\core_fast2$next[2:0]$1893
- attribute \src "libresoc.v:50913.3-50914.37"
+ attribute \src "libresoc.v:50905.3-50906.37"
wire width 3 $0\core_fast2[2:0]
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire $0\core_fast2_ok$next[0:0]$1894
- attribute \src "libresoc.v:50915.3-50916.43"
+ attribute \src "libresoc.v:50907.3-50908.43"
wire $0\core_fast2_ok[0:0]
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire width 3 $0\core_fasto1$next[2:0]$1895
- attribute \src "libresoc.v:50917.3-50918.39"
+ attribute \src "libresoc.v:50909.3-50910.39"
wire width 3 $0\core_fasto1[2:0]
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire $0\core_fasto1_ok$next[0:0]$1896
- attribute \src "libresoc.v:50919.3-50920.45"
+ attribute \src "libresoc.v:50911.3-50912.45"
wire $0\core_fasto1_ok[0:0]
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire width 3 $0\core_fasto2$next[2:0]$1897
- attribute \src "libresoc.v:50923.3-50924.39"
+ attribute \src "libresoc.v:50915.3-50916.39"
wire width 3 $0\core_fasto2[2:0]
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire $0\core_fasto2_ok$next[0:0]$1898
- attribute \src "libresoc.v:50925.3-50926.45"
+ attribute \src "libresoc.v:50917.3-50918.45"
wire $0\core_fasto2_ok[0:0]
- attribute \src "libresoc.v:51559.3-51590.6"
+ attribute \src "libresoc.v:51551.3-51582.6"
wire width 64 $0\core_msr$next[63:0]$1777
- attribute \src "libresoc.v:51009.3-51010.33"
+ attribute \src "libresoc.v:51001.3-51002.33"
wire width 64 $0\core_msr[63:0]
- attribute \src "libresoc.v:51559.3-51590.6"
+ attribute \src "libresoc.v:51551.3-51582.6"
wire width 64 $0\core_pc$next[63:0]$1778
- attribute \src "libresoc.v:50987.3-50988.31"
+ attribute \src "libresoc.v:50979.3-50980.31"
wire width 64 $0\core_pc[63:0]
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire width 5 $0\core_reg1$next[4:0]$1899
- attribute \src "libresoc.v:50883.3-50884.35"
+ attribute \src "libresoc.v:50875.3-50876.35"
wire width 5 $0\core_reg1[4:0]
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire $0\core_reg1_ok$next[0:0]$1900
- attribute \src "libresoc.v:50885.3-50886.41"
+ attribute \src "libresoc.v:50877.3-50878.41"
wire $0\core_reg1_ok[0:0]
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire width 5 $0\core_reg2$next[4:0]$1901
- attribute \src "libresoc.v:50887.3-50888.35"
+ attribute \src "libresoc.v:50879.3-50880.35"
wire width 5 $0\core_reg2[4:0]
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire $0\core_reg2_ok$next[0:0]$1902
- attribute \src "libresoc.v:50889.3-50890.41"
+ attribute \src "libresoc.v:50881.3-50882.41"
wire $0\core_reg2_ok[0:0]
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire width 5 $0\core_reg3$next[4:0]$1903
- attribute \src "libresoc.v:50891.3-50892.35"
+ attribute \src "libresoc.v:50883.3-50884.35"
wire width 5 $0\core_reg3[4:0]
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire $0\core_reg3_ok$next[0:0]$1904
- attribute \src "libresoc.v:50893.3-50894.41"
+ attribute \src "libresoc.v:50885.3-50886.41"
wire $0\core_reg3_ok[0:0]
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire width 5 $0\core_rego$next[4:0]$1905
- attribute \src "libresoc.v:50873.3-50874.35"
+ attribute \src "libresoc.v:50865.3-50866.35"
wire width 5 $0\core_rego[4:0]
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire $0\core_rego_ok$next[0:0]$1906
- attribute \src "libresoc.v:50875.3-50876.41"
+ attribute \src "libresoc.v:50867.3-50868.41"
wire $0\core_rego_ok[0:0]
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire width 10 $0\core_spr1$next[9:0]$1907
- attribute \src "libresoc.v:50901.3-50902.35"
+ attribute \src "libresoc.v:50893.3-50894.35"
wire width 10 $0\core_spr1[9:0]
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire $0\core_spr1_ok$next[0:0]$1908
- attribute \src "libresoc.v:50903.3-50904.41"
+ attribute \src "libresoc.v:50895.3-50896.41"
wire $0\core_spr1_ok[0:0]
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire width 10 $0\core_spro$next[9:0]$1909
- attribute \src "libresoc.v:50895.3-50896.35"
+ attribute \src "libresoc.v:50887.3-50888.35"
wire width 10 $0\core_spro[9:0]
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire $0\core_spro_ok$next[0:0]$1910
- attribute \src "libresoc.v:50897.3-50898.41"
+ attribute \src "libresoc.v:50889.3-50890.41"
wire $0\core_spro_ok[0:0]
- attribute \src "libresoc.v:52450.3-52468.6"
+ attribute \src "libresoc.v:52442.3-52460.6"
wire $0\core_stopped_i[0:0]
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire width 3 $0\core_xer_in$next[2:0]$1911
- attribute \src "libresoc.v:50905.3-50906.39"
+ attribute \src "libresoc.v:50897.3-50898.39"
wire width 3 $0\core_xer_in[2:0]
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire $0\core_xer_out$next[0:0]$1912
- attribute \src "libresoc.v:50907.3-50908.41"
+ attribute \src "libresoc.v:50899.3-50900.41"
wire $0\core_xer_out[0:0]
- attribute \src "libresoc.v:51005.3-51006.30"
+ attribute \src "libresoc.v:50997.3-50998.30"
wire $0\cu_st__rel_o_dly[0:0]
- attribute \src "libresoc.v:51705.3-51713.6"
+ attribute \src "libresoc.v:51697.3-51705.6"
wire $0\d_cr_delay$next[0:0]$1807
- attribute \src "libresoc.v:50921.3-50922.37"
+ attribute \src "libresoc.v:50913.3-50914.37"
wire $0\d_cr_delay[0:0]
- attribute \src "libresoc.v:51666.3-51674.6"
+ attribute \src "libresoc.v:51658.3-51666.6"
wire $0\d_reg_delay$next[0:0]$1801
- attribute \src "libresoc.v:50943.3-50944.39"
+ attribute \src "libresoc.v:50935.3-50936.39"
wire $0\d_reg_delay[0:0]
- attribute \src "libresoc.v:51744.3-51752.6"
+ attribute \src "libresoc.v:51736.3-51744.6"
wire $0\d_xer_delay$next[0:0]$1813
- attribute \src "libresoc.v:50899.3-50900.39"
+ attribute \src "libresoc.v:50891.3-50892.39"
wire $0\d_xer_delay[0:0]
- attribute \src "libresoc.v:51982.3-52002.6"
+ attribute \src "libresoc.v:51974.3-51994.6"
wire width 64 $0\data_i[63:0]
- attribute \src "libresoc.v:52469.3-52487.6"
+ attribute \src "libresoc.v:52461.3-52479.6"
wire $0\dbg_core_stopped_i[0:0]
- attribute \src "libresoc.v:51724.3-51733.6"
+ attribute \src "libresoc.v:51716.3-51725.6"
wire $0\dbg_d_cr_ack[0:0]
- attribute \src "libresoc.v:51714.3-51723.6"
+ attribute \src "libresoc.v:51706.3-51715.6"
wire width 64 $0\dbg_d_cr_data[63:0]
- attribute \src "libresoc.v:51685.3-51694.6"
+ attribute \src "libresoc.v:51677.3-51686.6"
wire $0\dbg_d_gpr_ack[0:0]
- attribute \src "libresoc.v:51675.3-51684.6"
+ attribute \src "libresoc.v:51667.3-51676.6"
wire width 64 $0\dbg_d_gpr_data[63:0]
- attribute \src "libresoc.v:51763.3-51772.6"
+ attribute \src "libresoc.v:51755.3-51764.6"
wire $0\dbg_d_xer_ack[0:0]
- attribute \src "libresoc.v:51753.3-51762.6"
+ attribute \src "libresoc.v:51745.3-51754.6"
wire width 64 $0\dbg_d_xer_data[63:0]
- attribute \src "libresoc.v:51501.3-51509.6"
+ attribute \src "libresoc.v:51493.3-51501.6"
wire width 4 $0\dbg_dmi_addr_i$next[3:0]$1763
- attribute \src "libresoc.v:51023.3-51024.45"
+ attribute \src "libresoc.v:51015.3-51016.45"
wire width 4 $0\dbg_dmi_addr_i[3:0]
- attribute \src "libresoc.v:52019.3-52027.6"
+ attribute \src "libresoc.v:52011.3-52019.6"
wire width 64 $0\dbg_dmi_din$next[63:0]$1846
- attribute \src "libresoc.v:51017.3-51018.39"
+ attribute \src "libresoc.v:51009.3-51010.39"
wire width 64 $0\dbg_dmi_din[63:0]
- attribute \src "libresoc.v:51510.3-51518.6"
+ attribute \src "libresoc.v:51502.3-51510.6"
wire $0\dbg_dmi_req_i$next[0:0]$1766
- attribute \src "libresoc.v:51021.3-51022.43"
+ attribute \src "libresoc.v:51013.3-51014.43"
wire $0\dbg_dmi_req_i[0:0]
- attribute \src "libresoc.v:51914.3-51922.6"
+ attribute \src "libresoc.v:51906.3-51914.6"
wire $0\dbg_dmi_we_i$next[0:0]$1835
- attribute \src "libresoc.v:51019.3-51020.41"
+ attribute \src "libresoc.v:51011.3-51012.41"
wire $0\dbg_dmi_we_i[0:0]
- attribute \src "libresoc.v:51887.3-51902.6"
+ attribute \src "libresoc.v:51879.3-51894.6"
wire width 64 $0\dec2_cur_dec$next[63:0]$1830
- attribute \src "libresoc.v:50855.3-50856.41"
+ attribute \src "libresoc.v:50847.3-50848.41"
wire width 64 $0\dec2_cur_dec[63:0]
- attribute \src "libresoc.v:52194.3-52202.6"
+ attribute \src "libresoc.v:52186.3-52194.6"
wire $0\dec2_cur_eint$next[0:0]$2124
- attribute \src "libresoc.v:51011.3-51012.43"
+ attribute \src "libresoc.v:51003.3-51004.43"
wire $0\dec2_cur_eint[0:0]
- attribute \src "libresoc.v:51519.3-51539.6"
+ attribute \src "libresoc.v:51511.3-51531.6"
wire width 64 $0\dec2_cur_msr$next[63:0]$1769
- attribute \src "libresoc.v:50859.3-50860.41"
+ attribute \src "libresoc.v:50851.3-50852.41"
wire width 64 $0\dec2_cur_msr[63:0]
- attribute \src "libresoc.v:52353.3-52373.6"
+ attribute \src "libresoc.v:52345.3-52365.6"
wire width 64 $0\dec2_cur_pc$next[63:0]$2145
- attribute \src "libresoc.v:50865.3-50866.39"
+ attribute \src "libresoc.v:50857.3-50858.39"
wire width 64 $0\dec2_cur_pc[63:0]
- attribute \src "libresoc.v:51540.3-51558.6"
+ attribute \src "libresoc.v:51532.3-51550.6"
wire width 32 $0\dec2_raw_opcode_in[31:0]
- attribute \src "libresoc.v:52203.3-52212.6"
+ attribute \src "libresoc.v:52195.3-52204.6"
wire width 2 $0\delay$next[1:0]$2127
- attribute \src "libresoc.v:51007.3-51008.27"
+ attribute \src "libresoc.v:50999.3-51000.27"
wire width 2 $0\delay[1:0]
- attribute \src "libresoc.v:51646.3-51655.6"
+ attribute \src "libresoc.v:51638.3-51647.6"
wire width 5 $0\dmi__addr[4:0]
- attribute \src "libresoc.v:51656.3-51665.6"
+ attribute \src "libresoc.v:51648.3-51657.6"
wire $0\dmi__ren[0:0]
- attribute \src "libresoc.v:51803.3-51830.6"
+ attribute \src "libresoc.v:51795.3-51822.6"
wire width 2 $0\fsm_state$131$next[1:0]$1820
- attribute \src "libresoc.v:50877.3-50878.45"
+ attribute \src "libresoc.v:50869.3-50870.45"
wire width 2 $0\fsm_state$131[1:0]$1677
- attribute \src "libresoc.v:50017.13-50017.35"
+ attribute \src "libresoc.v:50009.13-50009.35"
wire width 2 $0\fsm_state$131[1:0]$2254
- attribute \src "libresoc.v:52404.3-52449.6"
+ attribute \src "libresoc.v:52396.3-52441.6"
wire width 2 $0\fsm_state$next[1:0]$2156
- attribute \src "libresoc.v:50861.3-50862.35"
+ attribute \src "libresoc.v:50853.3-50854.35"
wire width 2 $0\fsm_state[1:0]
- attribute \src "libresoc.v:51695.3-51704.6"
+ attribute \src "libresoc.v:51687.3-51696.6"
wire width 8 $0\full_rd2__ren[7:0]
- attribute \src "libresoc.v:51734.3-51743.6"
+ attribute \src "libresoc.v:51726.3-51735.6"
wire width 3 $0\full_rd__ren[2:0]
- attribute \src "libresoc.v:51591.3-51614.6"
+ attribute \src "libresoc.v:51583.3-51606.6"
wire width 32 $0\ilatch$next[31:0]$1792
- attribute \src "libresoc.v:50965.3-50966.29"
+ attribute \src "libresoc.v:50957.3-50958.29"
wire width 32 $0\ilatch[31:0]
- attribute \src "libresoc.v:52287.3-52302.6"
+ attribute \src "libresoc.v:52279.3-52294.6"
wire width 48 $0\imem_a_pc_i[47:0]
- attribute \src "libresoc.v:52303.3-52327.6"
+ attribute \src "libresoc.v:52295.3-52319.6"
wire $0\imem_a_valid_i[0:0]
- attribute \src "libresoc.v:52328.3-52352.6"
+ attribute \src "libresoc.v:52320.3-52344.6"
wire $0\imem_f_valid_i[0:0]
- attribute \src "libresoc.v:48741.7-48741.20"
+ attribute \src "libresoc.v:48733.7-48733.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:51842.3-51856.6"
+ attribute \src "libresoc.v:51834.3-51848.6"
wire width 3 $0\issue__addr$135[2:0]$1825
- attribute \src "libresoc.v:51773.3-51787.6"
+ attribute \src "libresoc.v:51765.3-51779.6"
wire width 3 $0\issue__addr[2:0]
- attribute \src "libresoc.v:51872.3-51886.6"
+ attribute \src "libresoc.v:51864.3-51878.6"
wire width 64 $0\issue__data_i[63:0]
- attribute \src "libresoc.v:51788.3-51802.6"
+ attribute \src "libresoc.v:51780.3-51794.6"
wire $0\issue__ren[0:0]
- attribute \src "libresoc.v:51857.3-51871.6"
+ attribute \src "libresoc.v:51849.3-51863.6"
wire $0\issue__wen[0:0]
- attribute \src "libresoc.v:51635.3-51645.6"
+ attribute \src "libresoc.v:51627.3-51637.6"
wire $0\issue_i[0:0]
- attribute \src "libresoc.v:51615.3-51634.6"
+ attribute \src "libresoc.v:51607.3-51626.6"
wire $0\ivalid_i[0:0]
- attribute \src "libresoc.v:52176.3-52184.6"
+ attribute \src "libresoc.v:52168.3-52176.6"
wire $0\jtag_dmi0__ack_o$next[0:0]$2118
- attribute \src "libresoc.v:51015.3-51016.49"
+ attribute \src "libresoc.v:51007.3-51008.49"
wire $0\jtag_dmi0__ack_o[0:0]
- attribute \src "libresoc.v:52185.3-52193.6"
+ attribute \src "libresoc.v:52177.3-52185.6"
wire width 64 $0\jtag_dmi0__dout$next[63:0]$2121
- attribute \src "libresoc.v:51013.3-51014.47"
+ attribute \src "libresoc.v:51005.3-51006.47"
wire width 64 $0\jtag_dmi0__dout[63:0]
- attribute \src "libresoc.v:52003.3-52018.6"
+ attribute \src "libresoc.v:51995.3-52010.6"
wire width 4 $0\msr__ren[3:0]
- attribute \src "libresoc.v:52374.3-52403.6"
+ attribute \src "libresoc.v:52366.3-52395.6"
wire $0\msr_read$next[0:0]$2150
- attribute \src "libresoc.v:50863.3-50864.33"
+ attribute \src "libresoc.v:50855.3-50856.33"
wire $0\msr_read[0:0]
- attribute \src "libresoc.v:51831.3-51841.6"
+ attribute \src "libresoc.v:51823.3-51833.6"
wire width 64 $0\new_dec[63:0]
- attribute \src "libresoc.v:51903.3-51913.6"
+ attribute \src "libresoc.v:51895.3-51905.6"
wire width 64 $0\new_tb[63:0]
- attribute \src "libresoc.v:51932.3-51947.6"
+ attribute \src "libresoc.v:51924.3-51939.6"
wire width 64 $0\pc[63:0]
- attribute \src "libresoc.v:52028.3-52052.6"
+ attribute \src "libresoc.v:52020.3-52044.6"
wire $0\pc_changed$next[0:0]$1849
- attribute \src "libresoc.v:51001.3-51002.37"
+ attribute \src "libresoc.v:50993.3-50994.37"
wire $0\pc_changed[0:0]
- attribute \src "libresoc.v:51923.3-51931.6"
+ attribute \src "libresoc.v:51915.3-51923.6"
wire $0\pc_ok_delay$next[0:0]$1838
- attribute \src "libresoc.v:51003.3-51004.39"
+ attribute \src "libresoc.v:50995.3-50996.39"
wire $0\pc_ok_delay[0:0]
- attribute \src "libresoc.v:52213.3-52249.6"
+ attribute \src "libresoc.v:52205.3-52241.6"
wire width 32 $0\raw_insn_i$next[31:0]$2130
- attribute \src "libresoc.v:50869.3-50870.37"
+ attribute \src "libresoc.v:50861.3-50862.37"
wire width 32 $0\raw_insn_i[31:0]
- attribute \src "libresoc.v:51961.3-51981.6"
+ attribute \src "libresoc.v:51953.3-51973.6"
wire width 4 $0\wen[3:0]
- attribute \src "libresoc.v:52250.3-52286.6"
+ attribute \src "libresoc.v:52242.3-52278.6"
wire $1\bigendian_i$next[0:0]$2137
- attribute \src "libresoc.v:48873.7-48873.25"
+ attribute \src "libresoc.v:48865.7-48865.25"
wire $1\bigendian_i[0:0]
- attribute \src "libresoc.v:51948.3-51960.6"
+ attribute \src "libresoc.v:51940.3-51952.6"
wire width 4 $1\cia__ren[3:0]
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire width 8 $1\core_asmcode$next[7:0]$1913
- attribute \src "libresoc.v:48885.13-48885.33"
+ attribute \src "libresoc.v:48877.13-48877.33"
wire width 8 $1\core_asmcode[7:0]
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire width 64 $1\core_core_cia$next[63:0]$1914
- attribute \src "libresoc.v:48891.14-48891.50"
+ attribute \src "libresoc.v:48883.14-48883.50"
wire width 64 $1\core_core_cia[63:0]
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire width 8 $1\core_core_cr_rd$next[7:0]$1915
- attribute \src "libresoc.v:48895.13-48895.36"
+ attribute \src "libresoc.v:48887.13-48887.36"
wire width 8 $1\core_core_cr_rd[7:0]
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire $1\core_core_cr_rd_ok$next[0:0]$1916
- attribute \src "libresoc.v:48899.7-48899.32"
+ attribute \src "libresoc.v:48891.7-48891.32"
wire $1\core_core_cr_rd_ok[0:0]
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire width 8 $1\core_core_cr_wr$next[7:0]$1917
- attribute \src "libresoc.v:48903.13-48903.36"
+ attribute \src "libresoc.v:48895.13-48895.36"
wire width 8 $1\core_core_cr_wr[7:0]
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire $1\core_core_cr_wr_ok$next[0:0]$1918
- attribute \src "libresoc.v:48907.7-48907.32"
+ attribute \src "libresoc.v:48899.7-48899.32"
wire $1\core_core_cr_wr_ok[0:0]
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire $1\core_core_exc_$signal$50$next[0:0]$1919
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire $1\core_core_exc_$signal$51$next[0:0]$1920
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire $1\core_core_exc_$signal$52$next[0:0]$1921
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire $1\core_core_exc_$signal$53$next[0:0]$1922
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire $1\core_core_exc_$signal$54$next[0:0]$1923
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire $1\core_core_exc_$signal$55$next[0:0]$1924
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire $1\core_core_exc_$signal$56$next[0:0]$1925
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire $1\core_core_exc_$signal$next[0:0]$1926
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire width 12 $1\core_core_fn_unit$next[11:0]$1927
- attribute \src "libresoc.v:48956.14-48956.41"
+ attribute \src "libresoc.v:48948.14-48948.41"
wire width 12 $1\core_core_fn_unit[11:0]
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire width 2 $1\core_core_input_carry$next[1:0]$1928
- attribute \src "libresoc.v:48964.13-48964.41"
+ attribute \src "libresoc.v:48956.13-48956.41"
wire width 2 $1\core_core_input_carry[1:0]
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire width 32 $1\core_core_insn$next[31:0]$1929
- attribute \src "libresoc.v:48968.14-48968.36"
+ attribute \src "libresoc.v:48960.14-48960.36"
wire width 32 $1\core_core_insn[31:0]
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire width 7 $1\core_core_insn_type$next[6:0]$1930
- attribute \src "libresoc.v:49046.13-49046.40"
+ attribute \src "libresoc.v:49038.13-49038.40"
wire width 7 $1\core_core_insn_type[6:0]
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire $1\core_core_is_32bit$next[0:0]$1931
- attribute \src "libresoc.v:49050.7-49050.32"
+ attribute \src "libresoc.v:49042.7-49042.32"
wire $1\core_core_is_32bit[0:0]
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire $1\core_core_lk$next[0:0]$1932
- attribute \src "libresoc.v:49054.7-49054.26"
+ attribute \src "libresoc.v:49046.7-49046.26"
wire $1\core_core_lk[0:0]
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire width 64 $1\core_core_msr$next[63:0]$1933
- attribute \src "libresoc.v:49058.14-49058.50"
+ attribute \src "libresoc.v:49050.14-49050.50"
wire width 64 $1\core_core_msr[63:0]
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire $1\core_core_oe$next[0:0]$1934
- attribute \src "libresoc.v:49062.7-49062.26"
+ attribute \src "libresoc.v:49054.7-49054.26"
wire $1\core_core_oe[0:0]
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire $1\core_core_oe_ok$next[0:0]$1935
- attribute \src "libresoc.v:49066.7-49066.29"
+ attribute \src "libresoc.v:49058.7-49058.29"
wire $1\core_core_oe_ok[0:0]
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire $1\core_core_rc$next[0:0]$1936
- attribute \src "libresoc.v:49070.7-49070.26"
+ attribute \src "libresoc.v:49062.7-49062.26"
wire $1\core_core_rc[0:0]
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire $1\core_core_rc_ok$next[0:0]$1937
- attribute \src "libresoc.v:49074.7-49074.29"
+ attribute \src "libresoc.v:49066.7-49066.29"
wire $1\core_core_rc_ok[0:0]
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire width 13 $1\core_core_trapaddr$next[12:0]$1938
- attribute \src "libresoc.v:49078.14-49078.43"
+ attribute \src "libresoc.v:49070.14-49070.43"
wire width 13 $1\core_core_trapaddr[12:0]
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire width 8 $1\core_core_traptype$next[7:0]$1939
- attribute \src "libresoc.v:49082.13-49082.39"
+ attribute \src "libresoc.v:49074.13-49074.39"
wire width 8 $1\core_core_traptype[7:0]
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire width 3 $1\core_cr_in1$next[2:0]$1940
- attribute \src "libresoc.v:49088.13-49088.31"
+ attribute \src "libresoc.v:49080.13-49080.31"
wire width 3 $1\core_cr_in1[2:0]
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire $1\core_cr_in1_ok$next[0:0]$1941
- attribute \src "libresoc.v:49092.7-49092.28"
+ attribute \src "libresoc.v:49084.7-49084.28"
wire $1\core_cr_in1_ok[0:0]
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire width 3 $1\core_cr_in2$48$next[2:0]$1942
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire width 3 $1\core_cr_in2$next[2:0]$1943
- attribute \src "libresoc.v:49096.13-49096.31"
+ attribute \src "libresoc.v:49088.13-49088.31"
wire width 3 $1\core_cr_in2[2:0]
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire $1\core_cr_in2_ok$49$next[0:0]$1944
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire $1\core_cr_in2_ok$next[0:0]$1945
- attribute \src "libresoc.v:49104.7-49104.28"
+ attribute \src "libresoc.v:49096.7-49096.28"
wire $1\core_cr_in2_ok[0:0]
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire width 3 $1\core_cr_out$next[2:0]$1946
- attribute \src "libresoc.v:49112.13-49112.31"
+ attribute \src "libresoc.v:49104.13-49104.31"
wire width 3 $1\core_cr_out[2:0]
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire $1\core_cr_out_ok$next[0:0]$1947
- attribute \src "libresoc.v:49116.7-49116.28"
+ attribute \src "libresoc.v:49108.7-49108.28"
wire $1\core_cr_out_ok[0:0]
- attribute \src "libresoc.v:51559.3-51590.6"
+ attribute \src "libresoc.v:51551.3-51582.6"
wire width 64 $1\core_dec$next[63:0]$1779
- attribute \src "libresoc.v:49120.14-49120.45"
+ attribute \src "libresoc.v:49112.14-49112.45"
wire width 64 $1\core_dec[63:0]
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire width 5 $1\core_ea$next[4:0]$1948
- attribute \src "libresoc.v:49124.13-49124.28"
+ attribute \src "libresoc.v:49116.13-49116.28"
wire width 5 $1\core_ea[4:0]
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire $1\core_ea_ok$next[0:0]$1949
- attribute \src "libresoc.v:49128.7-49128.24"
+ attribute \src "libresoc.v:49120.7-49120.24"
wire $1\core_ea_ok[0:0]
- attribute \src "libresoc.v:51559.3-51590.6"
+ attribute \src "libresoc.v:51551.3-51582.6"
wire $1\core_eint$next[0:0]$1780
- attribute \src "libresoc.v:49132.7-49132.23"
+ attribute \src "libresoc.v:49124.7-49124.23"
wire $1\core_eint[0:0]
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire width 3 $1\core_fast1$next[2:0]$1950
- attribute \src "libresoc.v:49136.13-49136.30"
+ attribute \src "libresoc.v:49128.13-49128.30"
wire width 3 $1\core_fast1[2:0]
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire $1\core_fast1_ok$next[0:0]$1951
- attribute \src "libresoc.v:49140.7-49140.27"
+ attribute \src "libresoc.v:49132.7-49132.27"
wire $1\core_fast1_ok[0:0]
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire width 3 $1\core_fast2$next[2:0]$1952
- attribute \src "libresoc.v:49144.13-49144.30"
+ attribute \src "libresoc.v:49136.13-49136.30"
wire width 3 $1\core_fast2[2:0]
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire $1\core_fast2_ok$next[0:0]$1953
- attribute \src "libresoc.v:49148.7-49148.27"
+ attribute \src "libresoc.v:49140.7-49140.27"
wire $1\core_fast2_ok[0:0]
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire width 3 $1\core_fasto1$next[2:0]$1954
- attribute \src "libresoc.v:49152.13-49152.31"
+ attribute \src "libresoc.v:49144.13-49144.31"
wire width 3 $1\core_fasto1[2:0]
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire $1\core_fasto1_ok$next[0:0]$1955
- attribute \src "libresoc.v:49156.7-49156.28"
+ attribute \src "libresoc.v:49148.7-49148.28"
wire $1\core_fasto1_ok[0:0]
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire width 3 $1\core_fasto2$next[2:0]$1956
- attribute \src "libresoc.v:49160.13-49160.31"
+ attribute \src "libresoc.v:49152.13-49152.31"
wire width 3 $1\core_fasto2[2:0]
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire $1\core_fasto2_ok$next[0:0]$1957
- attribute \src "libresoc.v:49164.7-49164.28"
+ attribute \src "libresoc.v:49156.7-49156.28"
wire $1\core_fasto2_ok[0:0]
- attribute \src "libresoc.v:51559.3-51590.6"
+ attribute \src "libresoc.v:51551.3-51582.6"
wire width 64 $1\core_msr$next[63:0]$1781
- attribute \src "libresoc.v:49168.14-49168.45"
+ attribute \src "libresoc.v:49160.14-49160.45"
wire width 64 $1\core_msr[63:0]
- attribute \src "libresoc.v:51559.3-51590.6"
+ attribute \src "libresoc.v:51551.3-51582.6"
wire width 64 $1\core_pc$next[63:0]$1782
- attribute \src "libresoc.v:49172.14-49172.44"
+ attribute \src "libresoc.v:49164.14-49164.44"
wire width 64 $1\core_pc[63:0]
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire width 5 $1\core_reg1$next[4:0]$1958
- attribute \src "libresoc.v:49176.13-49176.30"
+ attribute \src "libresoc.v:49168.13-49168.30"
wire width 5 $1\core_reg1[4:0]
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire $1\core_reg1_ok$next[0:0]$1959
- attribute \src "libresoc.v:49180.7-49180.26"
+ attribute \src "libresoc.v:49172.7-49172.26"
wire $1\core_reg1_ok[0:0]
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire width 5 $1\core_reg2$next[4:0]$1960
- attribute \src "libresoc.v:49184.13-49184.30"
+ attribute \src "libresoc.v:49176.13-49176.30"
wire width 5 $1\core_reg2[4:0]
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire $1\core_reg2_ok$next[0:0]$1961
- attribute \src "libresoc.v:49188.7-49188.26"
+ attribute \src "libresoc.v:49180.7-49180.26"
wire $1\core_reg2_ok[0:0]
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire width 5 $1\core_reg3$next[4:0]$1962
- attribute \src "libresoc.v:49192.13-49192.30"
+ attribute \src "libresoc.v:49184.13-49184.30"
wire width 5 $1\core_reg3[4:0]
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire $1\core_reg3_ok$next[0:0]$1963
- attribute \src "libresoc.v:49196.7-49196.26"
+ attribute \src "libresoc.v:49188.7-49188.26"
wire $1\core_reg3_ok[0:0]
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire width 5 $1\core_rego$next[4:0]$1964
- attribute \src "libresoc.v:49200.13-49200.30"
+ attribute \src "libresoc.v:49192.13-49192.30"
wire width 5 $1\core_rego[4:0]
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire $1\core_rego_ok$next[0:0]$1965
- attribute \src "libresoc.v:49204.7-49204.26"
+ attribute \src "libresoc.v:49196.7-49196.26"
wire $1\core_rego_ok[0:0]
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire width 10 $1\core_spr1$next[9:0]$1966
- attribute \src "libresoc.v:49319.13-49319.32"
+ attribute \src "libresoc.v:49311.13-49311.32"
wire width 10 $1\core_spr1[9:0]
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire $1\core_spr1_ok$next[0:0]$1967
- attribute \src "libresoc.v:49323.7-49323.26"
+ attribute \src "libresoc.v:49315.7-49315.26"
wire $1\core_spr1_ok[0:0]
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire width 10 $1\core_spro$next[9:0]$1968
- attribute \src "libresoc.v:49438.13-49438.32"
+ attribute \src "libresoc.v:49430.13-49430.32"
wire width 10 $1\core_spro[9:0]
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire $1\core_spro_ok$next[0:0]$1969
- attribute \src "libresoc.v:49442.7-49442.26"
+ attribute \src "libresoc.v:49434.7-49434.26"
wire $1\core_spro_ok[0:0]
- attribute \src "libresoc.v:52450.3-52468.6"
+ attribute \src "libresoc.v:52442.3-52460.6"
wire $1\core_stopped_i[0:0]
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire width 3 $1\core_xer_in$next[2:0]$1970
- attribute \src "libresoc.v:49450.13-49450.31"
+ attribute \src "libresoc.v:49442.13-49442.31"
wire width 3 $1\core_xer_in[2:0]
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire $1\core_xer_out$next[0:0]$1971
- attribute \src "libresoc.v:49454.7-49454.26"
+ attribute \src "libresoc.v:49446.7-49446.26"
wire $1\core_xer_out[0:0]
- attribute \src "libresoc.v:49470.7-49470.30"
+ attribute \src "libresoc.v:49462.7-49462.30"
wire $1\cu_st__rel_o_dly[0:0]
- attribute \src "libresoc.v:51705.3-51713.6"
+ attribute \src "libresoc.v:51697.3-51705.6"
wire $1\d_cr_delay$next[0:0]$1808
- attribute \src "libresoc.v:49476.7-49476.24"
+ attribute \src "libresoc.v:49468.7-49468.24"
wire $1\d_cr_delay[0:0]
- attribute \src "libresoc.v:51666.3-51674.6"
+ attribute \src "libresoc.v:51658.3-51666.6"
wire $1\d_reg_delay$next[0:0]$1802
- attribute \src "libresoc.v:49480.7-49480.25"
+ attribute \src "libresoc.v:49472.7-49472.25"
wire $1\d_reg_delay[0:0]
- attribute \src "libresoc.v:51744.3-51752.6"
+ attribute \src "libresoc.v:51736.3-51744.6"
wire $1\d_xer_delay$next[0:0]$1814
- attribute \src "libresoc.v:49484.7-49484.25"
+ attribute \src "libresoc.v:49476.7-49476.25"
wire $1\d_xer_delay[0:0]
- attribute \src "libresoc.v:51982.3-52002.6"
+ attribute \src "libresoc.v:51974.3-51994.6"
wire width 64 $1\data_i[63:0]
- attribute \src "libresoc.v:52469.3-52487.6"
+ attribute \src "libresoc.v:52461.3-52479.6"
wire $1\dbg_core_stopped_i[0:0]
- attribute \src "libresoc.v:51724.3-51733.6"
+ attribute \src "libresoc.v:51716.3-51725.6"
wire $1\dbg_d_cr_ack[0:0]
- attribute \src "libresoc.v:51714.3-51723.6"
+ attribute \src "libresoc.v:51706.3-51715.6"
wire width 64 $1\dbg_d_cr_data[63:0]
- attribute \src "libresoc.v:51685.3-51694.6"
+ attribute \src "libresoc.v:51677.3-51686.6"
wire $1\dbg_d_gpr_ack[0:0]
- attribute \src "libresoc.v:51675.3-51684.6"
+ attribute \src "libresoc.v:51667.3-51676.6"
wire width 64 $1\dbg_d_gpr_data[63:0]
- attribute \src "libresoc.v:51763.3-51772.6"
+ attribute \src "libresoc.v:51755.3-51764.6"
wire $1\dbg_d_xer_ack[0:0]
- attribute \src "libresoc.v:51753.3-51762.6"
+ attribute \src "libresoc.v:51745.3-51754.6"
wire width 64 $1\dbg_d_xer_data[63:0]
- attribute \src "libresoc.v:51501.3-51509.6"
+ attribute \src "libresoc.v:51493.3-51501.6"
wire width 4 $1\dbg_dmi_addr_i$next[3:0]$1764
- attribute \src "libresoc.v:49522.13-49522.34"
+ attribute \src "libresoc.v:49514.13-49514.34"
wire width 4 $1\dbg_dmi_addr_i[3:0]
- attribute \src "libresoc.v:52019.3-52027.6"
+ attribute \src "libresoc.v:52011.3-52019.6"
wire width 64 $1\dbg_dmi_din$next[63:0]$1847
- attribute \src "libresoc.v:49526.14-49526.48"
+ attribute \src "libresoc.v:49518.14-49518.48"
wire width 64 $1\dbg_dmi_din[63:0]
- attribute \src "libresoc.v:51510.3-51518.6"
+ attribute \src "libresoc.v:51502.3-51510.6"
wire $1\dbg_dmi_req_i$next[0:0]$1767
- attribute \src "libresoc.v:49532.7-49532.27"
+ attribute \src "libresoc.v:49524.7-49524.27"
wire $1\dbg_dmi_req_i[0:0]
- attribute \src "libresoc.v:51914.3-51922.6"
+ attribute \src "libresoc.v:51906.3-51914.6"
wire $1\dbg_dmi_we_i$next[0:0]$1836
- attribute \src "libresoc.v:49536.7-49536.26"
+ attribute \src "libresoc.v:49528.7-49528.26"
wire $1\dbg_dmi_we_i[0:0]
- attribute \src "libresoc.v:51887.3-51902.6"
+ attribute \src "libresoc.v:51879.3-51894.6"
wire width 64 $1\dec2_cur_dec$next[63:0]$1831
- attribute \src "libresoc.v:49572.14-49572.49"
+ attribute \src "libresoc.v:49564.14-49564.49"
wire width 64 $1\dec2_cur_dec[63:0]
- attribute \src "libresoc.v:52194.3-52202.6"
+ attribute \src "libresoc.v:52186.3-52194.6"
wire $1\dec2_cur_eint$next[0:0]$2125
- attribute \src "libresoc.v:49576.7-49576.27"
+ attribute \src "libresoc.v:49568.7-49568.27"
wire $1\dec2_cur_eint[0:0]
- attribute \src "libresoc.v:51519.3-51539.6"
+ attribute \src "libresoc.v:51511.3-51531.6"
wire width 64 $1\dec2_cur_msr$next[63:0]$1770
- attribute \src "libresoc.v:49580.14-49580.49"
+ attribute \src "libresoc.v:49572.14-49572.49"
wire width 64 $1\dec2_cur_msr[63:0]
- attribute \src "libresoc.v:52353.3-52373.6"
+ attribute \src "libresoc.v:52345.3-52365.6"
wire width 64 $1\dec2_cur_pc$next[63:0]$2146
- attribute \src "libresoc.v:49584.14-49584.48"
+ attribute \src "libresoc.v:49576.14-49576.48"
wire width 64 $1\dec2_cur_pc[63:0]
- attribute \src "libresoc.v:51540.3-51558.6"
+ attribute \src "libresoc.v:51532.3-51550.6"
wire width 32 $1\dec2_raw_opcode_in[31:0]
- attribute \src "libresoc.v:52203.3-52212.6"
+ attribute \src "libresoc.v:52195.3-52204.6"
wire width 2 $1\delay$next[1:0]$2128
- attribute \src "libresoc.v:49993.13-49993.25"
+ attribute \src "libresoc.v:49985.13-49985.25"
wire width 2 $1\delay[1:0]
- attribute \src "libresoc.v:51646.3-51655.6"
+ attribute \src "libresoc.v:51638.3-51647.6"
wire width 5 $1\dmi__addr[4:0]
- attribute \src "libresoc.v:51656.3-51665.6"
+ attribute \src "libresoc.v:51648.3-51657.6"
wire $1\dmi__ren[0:0]
- attribute \src "libresoc.v:51803.3-51830.6"
+ attribute \src "libresoc.v:51795.3-51822.6"
wire width 2 $1\fsm_state$131$next[1:0]$1821
- attribute \src "libresoc.v:52404.3-52449.6"
+ attribute \src "libresoc.v:52396.3-52441.6"
wire width 2 $1\fsm_state$next[1:0]$2157
- attribute \src "libresoc.v:50015.13-50015.29"
+ attribute \src "libresoc.v:50007.13-50007.29"
wire width 2 $1\fsm_state[1:0]
- attribute \src "libresoc.v:51695.3-51704.6"
+ attribute \src "libresoc.v:51687.3-51696.6"
wire width 8 $1\full_rd2__ren[7:0]
- attribute \src "libresoc.v:51734.3-51743.6"
+ attribute \src "libresoc.v:51726.3-51735.6"
wire width 3 $1\full_rd__ren[2:0]
- attribute \src "libresoc.v:51591.3-51614.6"
+ attribute \src "libresoc.v:51583.3-51606.6"
wire width 32 $1\ilatch$next[31:0]$1793
- attribute \src "libresoc.v:50267.14-50267.28"
+ attribute \src "libresoc.v:50259.14-50259.28"
wire width 32 $1\ilatch[31:0]
- attribute \src "libresoc.v:52287.3-52302.6"
+ attribute \src "libresoc.v:52279.3-52294.6"
wire width 48 $1\imem_a_pc_i[47:0]
- attribute \src "libresoc.v:52303.3-52327.6"
+ attribute \src "libresoc.v:52295.3-52319.6"
wire $1\imem_a_valid_i[0:0]
- attribute \src "libresoc.v:52328.3-52352.6"
+ attribute \src "libresoc.v:52320.3-52344.6"
wire $1\imem_f_valid_i[0:0]
- attribute \src "libresoc.v:51842.3-51856.6"
+ attribute \src "libresoc.v:51834.3-51848.6"
wire width 3 $1\issue__addr$135[2:0]$1826
- attribute \src "libresoc.v:51773.3-51787.6"
+ attribute \src "libresoc.v:51765.3-51779.6"
wire width 3 $1\issue__addr[2:0]
- attribute \src "libresoc.v:51872.3-51886.6"
+ attribute \src "libresoc.v:51864.3-51878.6"
wire width 64 $1\issue__data_i[63:0]
- attribute \src "libresoc.v:51788.3-51802.6"
+ attribute \src "libresoc.v:51780.3-51794.6"
wire $1\issue__ren[0:0]
- attribute \src "libresoc.v:51857.3-51871.6"
+ attribute \src "libresoc.v:51849.3-51863.6"
wire $1\issue__wen[0:0]
- attribute \src "libresoc.v:51635.3-51645.6"
+ attribute \src "libresoc.v:51627.3-51637.6"
wire $1\issue_i[0:0]
- attribute \src "libresoc.v:51615.3-51634.6"
+ attribute \src "libresoc.v:51607.3-51626.6"
wire $1\ivalid_i[0:0]
- attribute \src "libresoc.v:52176.3-52184.6"
+ attribute \src "libresoc.v:52168.3-52176.6"
wire $1\jtag_dmi0__ack_o$next[0:0]$2119
- attribute \src "libresoc.v:50301.7-50301.30"
+ attribute \src "libresoc.v:50293.7-50293.30"
wire $1\jtag_dmi0__ack_o[0:0]
- attribute \src "libresoc.v:52185.3-52193.6"
+ attribute \src "libresoc.v:52177.3-52185.6"
wire width 64 $1\jtag_dmi0__dout$next[63:0]$2122
- attribute \src "libresoc.v:50309.14-50309.52"
+ attribute \src "libresoc.v:50301.14-50301.52"
wire width 64 $1\jtag_dmi0__dout[63:0]
- attribute \src "libresoc.v:52003.3-52018.6"
+ attribute \src "libresoc.v:51995.3-52010.6"
wire width 4 $1\msr__ren[3:0]
- attribute \src "libresoc.v:52374.3-52403.6"
+ attribute \src "libresoc.v:52366.3-52395.6"
wire $1\msr_read$next[0:0]$2151
- attribute \src "libresoc.v:50369.7-50369.22"
+ attribute \src "libresoc.v:50361.7-50361.22"
wire $1\msr_read[0:0]
- attribute \src "libresoc.v:51831.3-51841.6"
+ attribute \src "libresoc.v:51823.3-51833.6"
wire width 64 $1\new_dec[63:0]
- attribute \src "libresoc.v:51903.3-51913.6"
+ attribute \src "libresoc.v:51895.3-51905.6"
wire width 64 $1\new_tb[63:0]
- attribute \src "libresoc.v:51932.3-51947.6"
+ attribute \src "libresoc.v:51924.3-51939.6"
wire width 64 $1\pc[63:0]
- attribute \src "libresoc.v:52028.3-52052.6"
+ attribute \src "libresoc.v:52020.3-52044.6"
wire $1\pc_changed$next[0:0]$1850
- attribute \src "libresoc.v:50397.7-50397.24"
+ attribute \src "libresoc.v:50389.7-50389.24"
wire $1\pc_changed[0:0]
- attribute \src "libresoc.v:51923.3-51931.6"
+ attribute \src "libresoc.v:51915.3-51923.6"
wire $1\pc_ok_delay$next[0:0]$1839
- attribute \src "libresoc.v:50407.7-50407.25"
+ attribute \src "libresoc.v:50399.7-50399.25"
wire $1\pc_ok_delay[0:0]
- attribute \src "libresoc.v:52213.3-52249.6"
+ attribute \src "libresoc.v:52205.3-52241.6"
wire width 32 $1\raw_insn_i$next[31:0]$2131
- attribute \src "libresoc.v:50421.14-50421.32"
+ attribute \src "libresoc.v:50413.14-50413.32"
wire width 32 $1\raw_insn_i[31:0]
- attribute \src "libresoc.v:51961.3-51981.6"
+ attribute \src "libresoc.v:51953.3-51973.6"
wire width 4 $1\wen[3:0]
- attribute \src "libresoc.v:52250.3-52286.6"
+ attribute \src "libresoc.v:52242.3-52278.6"
wire $2\bigendian_i$next[0:0]$2138
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire width 8 $2\core_asmcode$next[7:0]$1972
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire width 64 $2\core_core_cia$next[63:0]$1973
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire width 8 $2\core_core_cr_rd$next[7:0]$1974
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire $2\core_core_cr_rd_ok$next[0:0]$1975
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire width 8 $2\core_core_cr_wr$next[7:0]$1976
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire $2\core_core_cr_wr_ok$next[0:0]$1977
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire $2\core_core_exc_$signal$50$next[0:0]$1978
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire $2\core_core_exc_$signal$51$next[0:0]$1979
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire $2\core_core_exc_$signal$52$next[0:0]$1980
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire $2\core_core_exc_$signal$53$next[0:0]$1981
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire $2\core_core_exc_$signal$54$next[0:0]$1982
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire $2\core_core_exc_$signal$55$next[0:0]$1983
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire $2\core_core_exc_$signal$56$next[0:0]$1984
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire $2\core_core_exc_$signal$next[0:0]$1985
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire width 12 $2\core_core_fn_unit$next[11:0]$1986
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire width 2 $2\core_core_input_carry$next[1:0]$1987
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire width 32 $2\core_core_insn$next[31:0]$1988
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire width 7 $2\core_core_insn_type$next[6:0]$1989
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire $2\core_core_is_32bit$next[0:0]$1990
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire $2\core_core_lk$next[0:0]$1991
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire width 64 $2\core_core_msr$next[63:0]$1992
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire $2\core_core_oe$next[0:0]$1993
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire $2\core_core_oe_ok$next[0:0]$1994
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire $2\core_core_rc$next[0:0]$1995
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire $2\core_core_rc_ok$next[0:0]$1996
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire width 13 $2\core_core_trapaddr$next[12:0]$1997
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire width 8 $2\core_core_traptype$next[7:0]$1998
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire width 3 $2\core_cr_in1$next[2:0]$1999
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire $2\core_cr_in1_ok$next[0:0]$2000
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire width 3 $2\core_cr_in2$48$next[2:0]$2001
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire width 3 $2\core_cr_in2$next[2:0]$2002
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire $2\core_cr_in2_ok$49$next[0:0]$2003
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire $2\core_cr_in2_ok$next[0:0]$2004
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire width 3 $2\core_cr_out$next[2:0]$2005
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire $2\core_cr_out_ok$next[0:0]$2006
- attribute \src "libresoc.v:51559.3-51590.6"
+ attribute \src "libresoc.v:51551.3-51582.6"
wire width 64 $2\core_dec$next[63:0]$1783
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire width 5 $2\core_ea$next[4:0]$2007
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire $2\core_ea_ok$next[0:0]$2008
- attribute \src "libresoc.v:51559.3-51590.6"
+ attribute \src "libresoc.v:51551.3-51582.6"
wire $2\core_eint$next[0:0]$1784
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire width 3 $2\core_fast1$next[2:0]$2009
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire $2\core_fast1_ok$next[0:0]$2010
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire width 3 $2\core_fast2$next[2:0]$2011
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire $2\core_fast2_ok$next[0:0]$2012
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire width 3 $2\core_fasto1$next[2:0]$2013
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire $2\core_fasto1_ok$next[0:0]$2014
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire width 3 $2\core_fasto2$next[2:0]$2015
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire $2\core_fasto2_ok$next[0:0]$2016
- attribute \src "libresoc.v:51559.3-51590.6"
+ attribute \src "libresoc.v:51551.3-51582.6"
wire width 64 $2\core_msr$next[63:0]$1785
- attribute \src "libresoc.v:51559.3-51590.6"
+ attribute \src "libresoc.v:51551.3-51582.6"
wire width 64 $2\core_pc$next[63:0]$1786
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire width 5 $2\core_reg1$next[4:0]$2017
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire $2\core_reg1_ok$next[0:0]$2018
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire width 5 $2\core_reg2$next[4:0]$2019
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire $2\core_reg2_ok$next[0:0]$2020
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire width 5 $2\core_reg3$next[4:0]$2021
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire $2\core_reg3_ok$next[0:0]$2022
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire width 5 $2\core_rego$next[4:0]$2023
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire $2\core_rego_ok$next[0:0]$2024
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire width 10 $2\core_spr1$next[9:0]$2025
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire $2\core_spr1_ok$next[0:0]$2026
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire width 10 $2\core_spro$next[9:0]$2027
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire $2\core_spro_ok$next[0:0]$2028
- attribute \src "libresoc.v:52450.3-52468.6"
+ attribute \src "libresoc.v:52442.3-52460.6"
wire $2\core_stopped_i[0:0]
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire width 3 $2\core_xer_in$next[2:0]$2029
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire $2\core_xer_out$next[0:0]$2030
- attribute \src "libresoc.v:51982.3-52002.6"
+ attribute \src "libresoc.v:51974.3-51994.6"
wire width 64 $2\data_i[63:0]
- attribute \src "libresoc.v:52469.3-52487.6"
+ attribute \src "libresoc.v:52461.3-52479.6"
wire $2\dbg_core_stopped_i[0:0]
- attribute \src "libresoc.v:51887.3-51902.6"
+ attribute \src "libresoc.v:51879.3-51894.6"
wire width 64 $2\dec2_cur_dec$next[63:0]$1832
- attribute \src "libresoc.v:51519.3-51539.6"
+ attribute \src "libresoc.v:51511.3-51531.6"
wire width 64 $2\dec2_cur_msr$next[63:0]$1771
- attribute \src "libresoc.v:52353.3-52373.6"
+ attribute \src "libresoc.v:52345.3-52365.6"
wire width 64 $2\dec2_cur_pc$next[63:0]$2147
- attribute \src "libresoc.v:51540.3-51558.6"
+ attribute \src "libresoc.v:51532.3-51550.6"
wire width 32 $2\dec2_raw_opcode_in[31:0]
- attribute \src "libresoc.v:51803.3-51830.6"
+ attribute \src "libresoc.v:51795.3-51822.6"
wire width 2 $2\fsm_state$131$next[1:0]$1822
- attribute \src "libresoc.v:52404.3-52449.6"
+ attribute \src "libresoc.v:52396.3-52441.6"
wire width 2 $2\fsm_state$next[1:0]$2158
- attribute \src "libresoc.v:51591.3-51614.6"
+ attribute \src "libresoc.v:51583.3-51606.6"
wire width 32 $2\ilatch$next[31:0]$1794
- attribute \src "libresoc.v:52287.3-52302.6"
+ attribute \src "libresoc.v:52279.3-52294.6"
wire width 48 $2\imem_a_pc_i[47:0]
- attribute \src "libresoc.v:52303.3-52327.6"
+ attribute \src "libresoc.v:52295.3-52319.6"
wire $2\imem_a_valid_i[0:0]
- attribute \src "libresoc.v:52328.3-52352.6"
+ attribute \src "libresoc.v:52320.3-52344.6"
wire $2\imem_f_valid_i[0:0]
- attribute \src "libresoc.v:51615.3-51634.6"
+ attribute \src "libresoc.v:51607.3-51626.6"
wire $2\ivalid_i[0:0]
- attribute \src "libresoc.v:52003.3-52018.6"
+ attribute \src "libresoc.v:51995.3-52010.6"
wire width 4 $2\msr__ren[3:0]
- attribute \src "libresoc.v:52374.3-52403.6"
+ attribute \src "libresoc.v:52366.3-52395.6"
wire $2\msr_read$next[0:0]$2152
- attribute \src "libresoc.v:51932.3-51947.6"
+ attribute \src "libresoc.v:51924.3-51939.6"
wire width 64 $2\pc[63:0]
- attribute \src "libresoc.v:52028.3-52052.6"
+ attribute \src "libresoc.v:52020.3-52044.6"
wire $2\pc_changed$next[0:0]$1851
- attribute \src "libresoc.v:52213.3-52249.6"
+ attribute \src "libresoc.v:52205.3-52241.6"
wire width 32 $2\raw_insn_i$next[31:0]$2132
- attribute \src "libresoc.v:51961.3-51981.6"
+ attribute \src "libresoc.v:51953.3-51973.6"
wire width 4 $2\wen[3:0]
- attribute \src "libresoc.v:52250.3-52286.6"
+ attribute \src "libresoc.v:52242.3-52278.6"
wire $3\bigendian_i$next[0:0]$2139
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire width 8 $3\core_asmcode$next[7:0]$2031
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire width 64 $3\core_core_cia$next[63:0]$2032
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire width 8 $3\core_core_cr_rd$next[7:0]$2033
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire $3\core_core_cr_rd_ok$next[0:0]$2034
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire width 8 $3\core_core_cr_wr$next[7:0]$2035
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire $3\core_core_cr_wr_ok$next[0:0]$2036
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire $3\core_core_exc_$signal$50$next[0:0]$2037
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire $3\core_core_exc_$signal$51$next[0:0]$2038
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire $3\core_core_exc_$signal$52$next[0:0]$2039
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire $3\core_core_exc_$signal$53$next[0:0]$2040
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire $3\core_core_exc_$signal$54$next[0:0]$2041
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire $3\core_core_exc_$signal$55$next[0:0]$2042
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire $3\core_core_exc_$signal$56$next[0:0]$2043
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire $3\core_core_exc_$signal$next[0:0]$2044
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire width 12 $3\core_core_fn_unit$next[11:0]$2045
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire width 2 $3\core_core_input_carry$next[1:0]$2046
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire width 32 $3\core_core_insn$next[31:0]$2047
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire width 7 $3\core_core_insn_type$next[6:0]$2048
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire $3\core_core_is_32bit$next[0:0]$2049
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire $3\core_core_lk$next[0:0]$2050
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire width 64 $3\core_core_msr$next[63:0]$2051
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire $3\core_core_oe$next[0:0]$2052
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire $3\core_core_oe_ok$next[0:0]$2053
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire $3\core_core_rc$next[0:0]$2054
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire $3\core_core_rc_ok$next[0:0]$2055
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire width 13 $3\core_core_trapaddr$next[12:0]$2056
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire width 8 $3\core_core_traptype$next[7:0]$2057
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire width 3 $3\core_cr_in1$next[2:0]$2058
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire $3\core_cr_in1_ok$next[0:0]$2059
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire width 3 $3\core_cr_in2$48$next[2:0]$2060
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire width 3 $3\core_cr_in2$next[2:0]$2061
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire $3\core_cr_in2_ok$49$next[0:0]$2062
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire $3\core_cr_in2_ok$next[0:0]$2063
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire width 3 $3\core_cr_out$next[2:0]$2064
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire $3\core_cr_out_ok$next[0:0]$2065
- attribute \src "libresoc.v:51559.3-51590.6"
+ attribute \src "libresoc.v:51551.3-51582.6"
wire width 64 $3\core_dec$next[63:0]$1787
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire width 5 $3\core_ea$next[4:0]$2066
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire $3\core_ea_ok$next[0:0]$2067
- attribute \src "libresoc.v:51559.3-51590.6"
+ attribute \src "libresoc.v:51551.3-51582.6"
wire $3\core_eint$next[0:0]$1788
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire width 3 $3\core_fast1$next[2:0]$2068
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire $3\core_fast1_ok$next[0:0]$2069
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire width 3 $3\core_fast2$next[2:0]$2070
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire $3\core_fast2_ok$next[0:0]$2071
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire width 3 $3\core_fasto1$next[2:0]$2072
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire $3\core_fasto1_ok$next[0:0]$2073
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire width 3 $3\core_fasto2$next[2:0]$2074
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire $3\core_fasto2_ok$next[0:0]$2075
- attribute \src "libresoc.v:51559.3-51590.6"
+ attribute \src "libresoc.v:51551.3-51582.6"
wire width 64 $3\core_msr$next[63:0]$1789
- attribute \src "libresoc.v:51559.3-51590.6"
+ attribute \src "libresoc.v:51551.3-51582.6"
wire width 64 $3\core_pc$next[63:0]$1790
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire width 5 $3\core_reg1$next[4:0]$2076
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire $3\core_reg1_ok$next[0:0]$2077
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire width 5 $3\core_reg2$next[4:0]$2078
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire $3\core_reg2_ok$next[0:0]$2079
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire width 5 $3\core_reg3$next[4:0]$2080
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire $3\core_reg3_ok$next[0:0]$2081
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire width 5 $3\core_rego$next[4:0]$2082
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire $3\core_rego_ok$next[0:0]$2083
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire width 10 $3\core_spr1$next[9:0]$2084
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire $3\core_spr1_ok$next[0:0]$2085
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire width 10 $3\core_spro$next[9:0]$2086
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire $3\core_spro_ok$next[0:0]$2087
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire width 3 $3\core_xer_in$next[2:0]$2088
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire $3\core_xer_out$next[0:0]$2089
- attribute \src "libresoc.v:51982.3-52002.6"
+ attribute \src "libresoc.v:51974.3-51994.6"
wire width 64 $3\data_i[63:0]
- attribute \src "libresoc.v:51519.3-51539.6"
+ attribute \src "libresoc.v:51511.3-51531.6"
wire width 64 $3\dec2_cur_msr$next[63:0]$1772
- attribute \src "libresoc.v:52353.3-52373.6"
+ attribute \src "libresoc.v:52345.3-52365.6"
wire width 64 $3\dec2_cur_pc$next[63:0]$2148
- attribute \src "libresoc.v:52404.3-52449.6"
+ attribute \src "libresoc.v:52396.3-52441.6"
wire width 2 $3\fsm_state$next[1:0]$2159
- attribute \src "libresoc.v:51591.3-51614.6"
+ attribute \src "libresoc.v:51583.3-51606.6"
wire width 32 $3\ilatch$next[31:0]$1795
- attribute \src "libresoc.v:52303.3-52327.6"
+ attribute \src "libresoc.v:52295.3-52319.6"
wire $3\imem_a_valid_i[0:0]
- attribute \src "libresoc.v:52328.3-52352.6"
+ attribute \src "libresoc.v:52320.3-52344.6"
wire $3\imem_f_valid_i[0:0]
- attribute \src "libresoc.v:52374.3-52403.6"
+ attribute \src "libresoc.v:52366.3-52395.6"
wire $3\msr_read$next[0:0]$2153
- attribute \src "libresoc.v:52028.3-52052.6"
+ attribute \src "libresoc.v:52020.3-52044.6"
wire $3\pc_changed$next[0:0]$1852
- attribute \src "libresoc.v:52213.3-52249.6"
+ attribute \src "libresoc.v:52205.3-52241.6"
wire width 32 $3\raw_insn_i$next[31:0]$2133
- attribute \src "libresoc.v:51961.3-51981.6"
+ attribute \src "libresoc.v:51953.3-51973.6"
wire width 4 $3\wen[3:0]
- attribute \src "libresoc.v:52250.3-52286.6"
+ attribute \src "libresoc.v:52242.3-52278.6"
wire $4\bigendian_i$next[0:0]$2140
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire $4\core_core_cr_rd_ok$next[0:0]$2090
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire $4\core_core_cr_wr_ok$next[0:0]$2091
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire $4\core_core_exc_$signal$50$next[0:0]$2092
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire $4\core_core_exc_$signal$51$next[0:0]$2093
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire $4\core_core_exc_$signal$52$next[0:0]$2094
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire $4\core_core_exc_$signal$53$next[0:0]$2095
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire $4\core_core_exc_$signal$54$next[0:0]$2096
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire $4\core_core_exc_$signal$55$next[0:0]$2097
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire $4\core_core_exc_$signal$56$next[0:0]$2098
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire $4\core_core_exc_$signal$next[0:0]$2099
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire $4\core_core_oe_ok$next[0:0]$2100
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire $4\core_core_rc_ok$next[0:0]$2101
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire $4\core_cr_in1_ok$next[0:0]$2102
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire $4\core_cr_in2_ok$49$next[0:0]$2103
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire $4\core_cr_in2_ok$next[0:0]$2104
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire $4\core_cr_out_ok$next[0:0]$2105
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire $4\core_ea_ok$next[0:0]$2106
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire $4\core_fast1_ok$next[0:0]$2107
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire $4\core_fast2_ok$next[0:0]$2108
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire $4\core_fasto1_ok$next[0:0]$2109
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire $4\core_fasto2_ok$next[0:0]$2110
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire $4\core_reg1_ok$next[0:0]$2111
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire $4\core_reg2_ok$next[0:0]$2112
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire $4\core_reg3_ok$next[0:0]$2113
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire $4\core_rego_ok$next[0:0]$2114
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire $4\core_spr1_ok$next[0:0]$2115
- attribute \src "libresoc.v:52053.3-52175.6"
+ attribute \src "libresoc.v:52045.3-52167.6"
wire $4\core_spro_ok$next[0:0]$2116
- attribute \src "libresoc.v:52404.3-52449.6"
+ attribute \src "libresoc.v:52396.3-52441.6"
wire width 2 $4\fsm_state$next[1:0]$2160
- attribute \src "libresoc.v:52374.3-52403.6"
+ attribute \src "libresoc.v:52366.3-52395.6"
wire $4\msr_read$next[0:0]$2154
- attribute \src "libresoc.v:52213.3-52249.6"
+ attribute \src "libresoc.v:52205.3-52241.6"
wire width 32 $4\raw_insn_i$next[31:0]$2134
- attribute \src "libresoc.v:52404.3-52449.6"
+ attribute \src "libresoc.v:52396.3-52441.6"
wire width 2 $5\fsm_state$next[1:0]$2161
- attribute \src "libresoc.v:50816.19-50816.110"
- wire width 65 $add$libresoc.v:50816$1626_Y
- attribute \src "libresoc.v:50823.18-50823.107"
- wire width 65 $add$libresoc.v:50823$1633_Y
- attribute \src "libresoc.v:50798.18-50798.101"
- wire $and$libresoc.v:50798$1606_Y
- attribute \src "libresoc.v:50802.19-50802.104"
- wire $and$libresoc.v:50802$1610_Y
- attribute \src "libresoc.v:50806.19-50806.104"
- wire $and$libresoc.v:50806$1614_Y
- attribute \src "libresoc.v:50822.18-50822.104"
- wire $and$libresoc.v:50822$1632_Y
+ attribute \src "libresoc.v:50808.19-50808.110"
+ wire width 65 $add$libresoc.v:50808$1626_Y
+ attribute \src "libresoc.v:50815.18-50815.107"
+ wire width 65 $add$libresoc.v:50815$1633_Y
+ attribute \src "libresoc.v:50790.18-50790.101"
+ wire $and$libresoc.v:50790$1606_Y
+ attribute \src "libresoc.v:50794.19-50794.104"
+ wire $and$libresoc.v:50794$1610_Y
+ attribute \src "libresoc.v:50798.19-50798.104"
+ wire $and$libresoc.v:50798$1614_Y
+ attribute \src "libresoc.v:50814.18-50814.104"
+ wire $and$libresoc.v:50814$1632_Y
+ attribute \src "libresoc.v:50823.18-50823.101"
+ wire $and$libresoc.v:50823$1641_Y
+ attribute \src "libresoc.v:50824.18-50824.109"
+ wire width 4 $and$libresoc.v:50824$1642_Y
attribute \src "libresoc.v:50831.18-50831.101"
- wire $and$libresoc.v:50831$1641_Y
- attribute \src "libresoc.v:50832.18-50832.109"
- wire width 4 $and$libresoc.v:50832$1642_Y
- attribute \src "libresoc.v:50839.18-50839.101"
- wire $and$libresoc.v:50839$1649_Y
- attribute \src "libresoc.v:50842.18-50842.101"
- wire $and$libresoc.v:50842$1652_Y
- attribute \src "libresoc.v:50845.18-50845.101"
- wire $and$libresoc.v:50845$1655_Y
- attribute \src "libresoc.v:50848.18-50848.101"
- wire $and$libresoc.v:50848$1658_Y
- attribute \src "libresoc.v:50851.18-50851.101"
- wire $and$libresoc.v:50851$1661_Y
- attribute \src "libresoc.v:50813.19-50813.109"
- wire width 64 $extend$libresoc.v:50813$1621_Y
- attribute \src "libresoc.v:50814.19-50814.108"
- wire width 64 $extend$libresoc.v:50814$1623_Y
- attribute \src "libresoc.v:50808.19-50808.111"
- wire width 7 $mul$libresoc.v:50808$1616_Y
- attribute \src "libresoc.v:50810.19-50810.111"
- wire width 7 $mul$libresoc.v:50810$1618_Y
- attribute \src "libresoc.v:50803.18-50803.102"
- wire $ne$libresoc.v:50803$1611_Y
- attribute \src "libresoc.v:50812.19-50812.118"
- wire $ne$libresoc.v:50812$1620_Y
- attribute \src "libresoc.v:50820.18-50820.102"
- wire $ne$libresoc.v:50820$1630_Y
- attribute \src "libresoc.v:50799.19-50799.102"
- wire $not$libresoc.v:50799$1607_Y
- attribute \src "libresoc.v:50800.19-50800.107"
- wire $not$libresoc.v:50800$1608_Y
- attribute \src "libresoc.v:50801.19-50801.109"
- wire $not$libresoc.v:50801$1609_Y
- attribute \src "libresoc.v:50804.19-50804.107"
- wire $not$libresoc.v:50804$1612_Y
+ wire $and$libresoc.v:50831$1649_Y
+ attribute \src "libresoc.v:50834.18-50834.101"
+ wire $and$libresoc.v:50834$1652_Y
+ attribute \src "libresoc.v:50837.18-50837.101"
+ wire $and$libresoc.v:50837$1655_Y
+ attribute \src "libresoc.v:50840.18-50840.101"
+ wire $and$libresoc.v:50840$1658_Y
+ attribute \src "libresoc.v:50843.18-50843.101"
+ wire $and$libresoc.v:50843$1661_Y
attribute \src "libresoc.v:50805.19-50805.109"
- wire $not$libresoc.v:50805$1613_Y
- attribute \src "libresoc.v:50807.19-50807.100"
- wire $not$libresoc.v:50807$1615_Y
- attribute \src "libresoc.v:50821.18-50821.103"
- wire $not$libresoc.v:50821$1631_Y
- attribute \src "libresoc.v:50824.18-50824.98"
- wire $not$libresoc.v:50824$1634_Y
- attribute \src "libresoc.v:50825.18-50825.101"
- wire $not$libresoc.v:50825$1635_Y
+ wire width 64 $extend$libresoc.v:50805$1621_Y
+ attribute \src "libresoc.v:50806.19-50806.108"
+ wire width 64 $extend$libresoc.v:50806$1623_Y
+ attribute \src "libresoc.v:50800.19-50800.111"
+ wire width 7 $mul$libresoc.v:50800$1616_Y
+ attribute \src "libresoc.v:50802.19-50802.111"
+ wire width 7 $mul$libresoc.v:50802$1618_Y
+ attribute \src "libresoc.v:50795.18-50795.102"
+ wire $ne$libresoc.v:50795$1611_Y
+ attribute \src "libresoc.v:50804.19-50804.118"
+ wire $ne$libresoc.v:50804$1620_Y
+ attribute \src "libresoc.v:50812.18-50812.102"
+ wire $ne$libresoc.v:50812$1630_Y
+ attribute \src "libresoc.v:50791.19-50791.102"
+ wire $not$libresoc.v:50791$1607_Y
+ attribute \src "libresoc.v:50792.19-50792.107"
+ wire $not$libresoc.v:50792$1608_Y
+ attribute \src "libresoc.v:50793.19-50793.109"
+ wire $not$libresoc.v:50793$1609_Y
+ attribute \src "libresoc.v:50796.19-50796.107"
+ wire $not$libresoc.v:50796$1612_Y
+ attribute \src "libresoc.v:50797.19-50797.109"
+ wire $not$libresoc.v:50797$1613_Y
+ attribute \src "libresoc.v:50799.19-50799.100"
+ wire $not$libresoc.v:50799$1615_Y
+ attribute \src "libresoc.v:50813.18-50813.103"
+ wire $not$libresoc.v:50813$1631_Y
+ attribute \src "libresoc.v:50816.18-50816.98"
+ wire $not$libresoc.v:50816$1634_Y
+ attribute \src "libresoc.v:50817.18-50817.101"
+ wire $not$libresoc.v:50817$1635_Y
+ attribute \src "libresoc.v:50818.18-50818.101"
+ wire $not$libresoc.v:50818$1636_Y
+ attribute \src "libresoc.v:50819.18-50819.101"
+ wire $not$libresoc.v:50819$1637_Y
+ attribute \src "libresoc.v:50820.18-50820.101"
+ wire $not$libresoc.v:50820$1638_Y
+ attribute \src "libresoc.v:50821.18-50821.106"
+ wire $not$libresoc.v:50821$1639_Y
+ attribute \src "libresoc.v:50822.18-50822.108"
+ wire $not$libresoc.v:50822$1640_Y
attribute \src "libresoc.v:50826.18-50826.101"
- wire $not$libresoc.v:50826$1636_Y
+ wire $not$libresoc.v:50826$1644_Y
attribute \src "libresoc.v:50827.18-50827.101"
- wire $not$libresoc.v:50827$1637_Y
+ wire $not$libresoc.v:50827$1645_Y
attribute \src "libresoc.v:50828.18-50828.101"
- wire $not$libresoc.v:50828$1638_Y
+ wire $not$libresoc.v:50828$1646_Y
attribute \src "libresoc.v:50829.18-50829.106"
- wire $not$libresoc.v:50829$1639_Y
+ wire $not$libresoc.v:50829$1647_Y
attribute \src "libresoc.v:50830.18-50830.108"
- wire $not$libresoc.v:50830$1640_Y
- attribute \src "libresoc.v:50834.18-50834.101"
- wire $not$libresoc.v:50834$1644_Y
- attribute \src "libresoc.v:50835.18-50835.101"
- wire $not$libresoc.v:50835$1645_Y
- attribute \src "libresoc.v:50836.18-50836.101"
- wire $not$libresoc.v:50836$1646_Y
- attribute \src "libresoc.v:50837.18-50837.106"
- wire $not$libresoc.v:50837$1647_Y
- attribute \src "libresoc.v:50838.18-50838.108"
- wire $not$libresoc.v:50838$1648_Y
- attribute \src "libresoc.v:50840.18-50840.106"
- wire $not$libresoc.v:50840$1650_Y
- attribute \src "libresoc.v:50841.18-50841.108"
- wire $not$libresoc.v:50841$1651_Y
- attribute \src "libresoc.v:50843.18-50843.106"
- wire $not$libresoc.v:50843$1653_Y
- attribute \src "libresoc.v:50844.18-50844.108"
- wire $not$libresoc.v:50844$1654_Y
- attribute \src "libresoc.v:50846.18-50846.106"
- wire $not$libresoc.v:50846$1656_Y
- attribute \src "libresoc.v:50847.18-50847.108"
- wire $not$libresoc.v:50847$1657_Y
- attribute \src "libresoc.v:50849.18-50849.106"
- wire $not$libresoc.v:50849$1659_Y
- attribute \src "libresoc.v:50850.18-50850.108"
- wire $not$libresoc.v:50850$1660_Y
- attribute \src "libresoc.v:50852.18-50852.99"
- wire $not$libresoc.v:50852$1662_Y
- attribute \src "libresoc.v:50853.18-50853.106"
- wire $not$libresoc.v:50853$1663_Y
- attribute \src "libresoc.v:50854.18-50854.108"
- wire $not$libresoc.v:50854$1664_Y
- attribute \src "libresoc.v:50818.18-50818.110"
- wire $or$libresoc.v:50818$1628_Y
- attribute \src "libresoc.v:50819.18-50819.100"
- wire $or$libresoc.v:50819$1629_Y
- attribute \src "libresoc.v:50813.19-50813.109"
- wire width 64 $pos$libresoc.v:50813$1622_Y
- attribute \src "libresoc.v:50814.19-50814.108"
- wire width 64 $pos$libresoc.v:50814$1624_Y
- attribute \src "libresoc.v:50833.18-50833.91"
- wire $reduce_or$libresoc.v:50833$1643_Y
- attribute \src "libresoc.v:50809.19-50809.42"
- wire width 64 $shr$libresoc.v:50809$1617_Y
- attribute \src "libresoc.v:50811.19-50811.42"
- wire width 64 $shr$libresoc.v:50811$1619_Y
- attribute \src "libresoc.v:50815.19-50815.110"
- wire width 65 $sub$libresoc.v:50815$1625_Y
- attribute \src "libresoc.v:50817.18-50817.101"
- wire width 3 $sub$libresoc.v:50817$1627_Y
+ wire $not$libresoc.v:50830$1648_Y
+ attribute \src "libresoc.v:50832.18-50832.106"
+ wire $not$libresoc.v:50832$1650_Y
+ attribute \src "libresoc.v:50833.18-50833.108"
+ wire $not$libresoc.v:50833$1651_Y
+ attribute \src "libresoc.v:50835.18-50835.106"
+ wire $not$libresoc.v:50835$1653_Y
+ attribute \src "libresoc.v:50836.18-50836.108"
+ wire $not$libresoc.v:50836$1654_Y
+ attribute \src "libresoc.v:50838.18-50838.106"
+ wire $not$libresoc.v:50838$1656_Y
+ attribute \src "libresoc.v:50839.18-50839.108"
+ wire $not$libresoc.v:50839$1657_Y
+ attribute \src "libresoc.v:50841.18-50841.106"
+ wire $not$libresoc.v:50841$1659_Y
+ attribute \src "libresoc.v:50842.18-50842.108"
+ wire $not$libresoc.v:50842$1660_Y
+ attribute \src "libresoc.v:50844.18-50844.99"
+ wire $not$libresoc.v:50844$1662_Y
+ attribute \src "libresoc.v:50845.18-50845.106"
+ wire $not$libresoc.v:50845$1663_Y
+ attribute \src "libresoc.v:50846.18-50846.108"
+ wire $not$libresoc.v:50846$1664_Y
+ attribute \src "libresoc.v:50810.18-50810.110"
+ wire $or$libresoc.v:50810$1628_Y
+ attribute \src "libresoc.v:50811.18-50811.100"
+ wire $or$libresoc.v:50811$1629_Y
+ attribute \src "libresoc.v:50805.19-50805.109"
+ wire width 64 $pos$libresoc.v:50805$1622_Y
+ attribute \src "libresoc.v:50806.19-50806.108"
+ wire width 64 $pos$libresoc.v:50806$1624_Y
+ attribute \src "libresoc.v:50825.18-50825.91"
+ wire $reduce_or$libresoc.v:50825$1643_Y
+ attribute \src "libresoc.v:50801.19-50801.42"
+ wire width 64 $shr$libresoc.v:50801$1617_Y
+ attribute \src "libresoc.v:50803.19-50803.42"
+ wire width 64 $shr$libresoc.v:50803$1619_Y
+ attribute \src "libresoc.v:50807.19-50807.110"
+ wire width 65 $sub$libresoc.v:50807$1625_Y
+ attribute \src "libresoc.v:50809.18-50809.101"
+ wire width 3 $sub$libresoc.v:50809$1627_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:174"
wire \$10
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:311"
wire \imem_f_valid_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:92"
wire \imem_wb_icache_en
- attribute \src "libresoc.v:48741.7-48741.15"
+ attribute \src "libresoc.v:48733.7-48733.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:237"
wire width 16 input 344 \int_level_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:45"
wire width 4 \xics_ics_icp_o_src
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:409"
- cell $add $add$libresoc.v:50816$1626
+ cell $add $add$libresoc.v:50808$1626
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \Y_WIDTH 65
connect \A \issue__data_o
connect \B 1'1
- connect \Y $add$libresoc.v:50816$1626_Y
+ connect \Y $add$libresoc.v:50808$1626_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:201"
- cell $add $add$libresoc.v:50823$1633
+ cell $add $add$libresoc.v:50815$1633
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \Y_WIDTH 65
connect \A \dec2_cur_pc
connect \B 3'100
- connect \Y $add$libresoc.v:50823$1633_Y
+ connect \Y $add$libresoc.v:50815$1633_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253"
- cell $and $and$libresoc.v:50798$1606
+ cell $and $and$libresoc.v:50790$1606
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$95
connect \B \$97
- connect \Y $and$libresoc.v:50798$1606_Y
+ connect \Y $and$libresoc.v:50790$1606_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253"
- cell $and $and$libresoc.v:50802$1610
+ cell $and $and$libresoc.v:50794$1610
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$103
connect \B \$105
- connect \Y $and$libresoc.v:50802$1610_Y
+ connect \Y $and$libresoc.v:50794$1610_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253"
- cell $and $and$libresoc.v:50806$1614
+ cell $and $and$libresoc.v:50798$1614
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$109
connect \B \$111
- connect \Y $and$libresoc.v:50806$1614_Y
+ connect \Y $and$libresoc.v:50798$1614_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
- cell $and $and$libresoc.v:50822$1632
+ cell $and $and$libresoc.v:50814$1632
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_st__rel_o
connect \B \$21
- connect \Y $and$libresoc.v:50822$1632_Y
+ connect \Y $and$libresoc.v:50814$1632_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253"
- cell $and $and$libresoc.v:50831$1641
+ cell $and $and$libresoc.v:50823$1641
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$38
connect \B \$40
- connect \Y $and$libresoc.v:50831$1641_Y
+ connect \Y $and$libresoc.v:50823$1641_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:309"
- cell $and $and$libresoc.v:50832$1642
+ cell $and $and$libresoc.v:50824$1642
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \state_nia_wen
connect \B 1'1
- connect \Y $and$libresoc.v:50832$1642_Y
+ connect \Y $and$libresoc.v:50824$1642_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253"
- cell $and $and$libresoc.v:50839$1649
+ cell $and $and$libresoc.v:50831$1649
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$63
connect \B \$65
- connect \Y $and$libresoc.v:50839$1649_Y
+ connect \Y $and$libresoc.v:50831$1649_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253"
- cell $and $and$libresoc.v:50842$1652
+ cell $and $and$libresoc.v:50834$1652
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$69
connect \B \$71
- connect \Y $and$libresoc.v:50842$1652_Y
+ connect \Y $and$libresoc.v:50834$1652_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253"
- cell $and $and$libresoc.v:50845$1655
+ cell $and $and$libresoc.v:50837$1655
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$75
connect \B \$77
- connect \Y $and$libresoc.v:50845$1655_Y
+ connect \Y $and$libresoc.v:50837$1655_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253"
- cell $and $and$libresoc.v:50848$1658
+ cell $and $and$libresoc.v:50840$1658
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$81
connect \B \$83
- connect \Y $and$libresoc.v:50848$1658_Y
+ connect \Y $and$libresoc.v:50840$1658_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253"
- cell $and $and$libresoc.v:50851$1661
+ cell $and $and$libresoc.v:50843$1661
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$87
connect \B \$89
- connect \Y $and$libresoc.v:50851$1661_Y
+ connect \Y $and$libresoc.v:50843$1661_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- cell $pos $extend$libresoc.v:50813$1621
+ cell $pos $extend$libresoc.v:50805$1621
parameter \A_SIGNED 0
parameter \A_WIDTH 32
parameter \Y_WIDTH 64
connect \A \full_rd2__data_o
- connect \Y $extend$libresoc.v:50813$1621_Y
+ connect \Y $extend$libresoc.v:50805$1621_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- cell $pos $extend$libresoc.v:50814$1623
+ cell $pos $extend$libresoc.v:50806$1623
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \Y_WIDTH 64
connect \A \full_rd__data_o
- connect \Y $extend$libresoc.v:50814$1623_Y
+ connect \Y $extend$libresoc.v:50806$1623_Y
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/back/rtlil.py:609"
- cell $mul $mul$libresoc.v:50808$1616
+ cell $mul $mul$libresoc.v:50800$1616
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 7
connect \A \dec2_cur_pc [2]
connect \B 6'100000
- connect \Y $mul$libresoc.v:50808$1616_Y
+ connect \Y $mul$libresoc.v:50800$1616_Y
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/back/rtlil.py:609"
- cell $mul $mul$libresoc.v:50810$1618
+ cell $mul $mul$libresoc.v:50802$1618
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 7
connect \A \dec2_cur_pc [2]
connect \B 6'100000
- connect \Y $mul$libresoc.v:50810$1618_Y
+ connect \Y $mul$libresoc.v:50802$1618_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:174"
- cell $ne $ne$libresoc.v:50803$1611
+ cell $ne $ne$libresoc.v:50795$1611
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \delay
connect \B 1'0
- connect \Y $ne$libresoc.v:50803$1611_Y
+ connect \Y $ne$libresoc.v:50795$1611_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:307"
- cell $ne $ne$libresoc.v:50812$1620
+ cell $ne $ne$libresoc.v:50804$1620
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \core_core_insn_type
connect \B 7'0000001
- connect \Y $ne$libresoc.v:50812$1620_Y
+ connect \Y $ne$libresoc.v:50804$1620_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:180"
- cell $ne $ne$libresoc.v:50820$1630
+ cell $ne $ne$libresoc.v:50812$1630
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \delay
connect \B \$17
- connect \Y $ne$libresoc.v:50820$1630_Y
+ connect \Y $ne$libresoc.v:50812$1630_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:311"
- cell $not $not$libresoc.v:50799$1607
+ cell $not $not$libresoc.v:50791$1607
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \corebusy_o
- connect \Y $not$libresoc.v:50799$1607_Y
+ connect \Y $not$libresoc.v:50791$1607_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253"
- cell $not $not$libresoc.v:50800$1608
+ cell $not $not$libresoc.v:50792$1608
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \dbg_core_stop_o
- connect \Y $not$libresoc.v:50800$1608_Y
+ connect \Y $not$libresoc.v:50792$1608_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253"
- cell $not $not$libresoc.v:50801$1609
+ cell $not $not$libresoc.v:50793$1609
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \core_coresync_rst
- connect \Y $not$libresoc.v:50801$1609_Y
+ connect \Y $not$libresoc.v:50793$1609_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253"
- cell $not $not$libresoc.v:50804$1612
+ cell $not $not$libresoc.v:50796$1612
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \dbg_core_stop_o
- connect \Y $not$libresoc.v:50804$1612_Y
+ connect \Y $not$libresoc.v:50796$1612_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253"
- cell $not $not$libresoc.v:50805$1613
+ cell $not $not$libresoc.v:50797$1613
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \core_coresync_rst
- connect \Y $not$libresoc.v:50805$1613_Y
+ connect \Y $not$libresoc.v:50797$1613_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:275"
- cell $not $not$libresoc.v:50807$1615
+ cell $not $not$libresoc.v:50799$1615
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \msr_read
- connect \Y $not$libresoc.v:50807$1615_Y
+ connect \Y $not$libresoc.v:50799$1615_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
- cell $not $not$libresoc.v:50821$1631
+ cell $not $not$libresoc.v:50813$1631
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \cu_st__rel_o_dly
- connect \Y $not$libresoc.v:50821$1631_Y
+ connect \Y $not$libresoc.v:50813$1631_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:206"
- cell $not $not$libresoc.v:50824$1634
+ cell $not $not$libresoc.v:50816$1634
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \pc_i_ok
- connect \Y $not$libresoc.v:50824$1634_Y
+ connect \Y $not$libresoc.v:50816$1634_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:311"
- cell $not $not$libresoc.v:50825$1635
+ cell $not $not$libresoc.v:50817$1635
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \corebusy_o
- connect \Y $not$libresoc.v:50825$1635_Y
+ connect \Y $not$libresoc.v:50817$1635_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:315"
- cell $not $not$libresoc.v:50826$1636
+ cell $not $not$libresoc.v:50818$1636
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \pc_changed
- connect \Y $not$libresoc.v:50826$1636_Y
+ connect \Y $not$libresoc.v:50818$1636_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:311"
- cell $not $not$libresoc.v:50827$1637
+ cell $not $not$libresoc.v:50819$1637
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \corebusy_o
- connect \Y $not$libresoc.v:50827$1637_Y
+ connect \Y $not$libresoc.v:50819$1637_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:315"
- cell $not $not$libresoc.v:50828$1638
+ cell $not $not$libresoc.v:50820$1638
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \pc_changed
- connect \Y $not$libresoc.v:50828$1638_Y
+ connect \Y $not$libresoc.v:50820$1638_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253"
- cell $not $not$libresoc.v:50829$1639
+ cell $not $not$libresoc.v:50821$1639
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \dbg_core_stop_o
- connect \Y $not$libresoc.v:50829$1639_Y
+ connect \Y $not$libresoc.v:50821$1639_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253"
- cell $not $not$libresoc.v:50830$1640
+ cell $not $not$libresoc.v:50822$1640
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \core_coresync_rst
- connect \Y $not$libresoc.v:50830$1640_Y
+ connect \Y $not$libresoc.v:50822$1640_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:311"
- cell $not $not$libresoc.v:50834$1644
+ cell $not $not$libresoc.v:50826$1644
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \corebusy_o
- connect \Y $not$libresoc.v:50834$1644_Y
+ connect \Y $not$libresoc.v:50826$1644_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:311"
- cell $not $not$libresoc.v:50835$1645
+ cell $not $not$libresoc.v:50827$1645
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \corebusy_o
- connect \Y $not$libresoc.v:50835$1645_Y
+ connect \Y $not$libresoc.v:50827$1645_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:311"
- cell $not $not$libresoc.v:50836$1646
+ cell $not $not$libresoc.v:50828$1646
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \corebusy_o
- connect \Y $not$libresoc.v:50836$1646_Y
+ connect \Y $not$libresoc.v:50828$1646_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253"
- cell $not $not$libresoc.v:50837$1647
+ cell $not $not$libresoc.v:50829$1647
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \dbg_core_stop_o
- connect \Y $not$libresoc.v:50837$1647_Y
+ connect \Y $not$libresoc.v:50829$1647_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253"
- cell $not $not$libresoc.v:50838$1648
+ cell $not $not$libresoc.v:50830$1648
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \core_coresync_rst
- connect \Y $not$libresoc.v:50838$1648_Y
+ connect \Y $not$libresoc.v:50830$1648_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253"
- cell $not $not$libresoc.v:50840$1650
+ cell $not $not$libresoc.v:50832$1650
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \dbg_core_stop_o
- connect \Y $not$libresoc.v:50840$1650_Y
+ connect \Y $not$libresoc.v:50832$1650_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253"
- cell $not $not$libresoc.v:50841$1651
+ cell $not $not$libresoc.v:50833$1651
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \core_coresync_rst
- connect \Y $not$libresoc.v:50841$1651_Y
+ connect \Y $not$libresoc.v:50833$1651_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253"
- cell $not $not$libresoc.v:50843$1653
+ cell $not $not$libresoc.v:50835$1653
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \dbg_core_stop_o
- connect \Y $not$libresoc.v:50843$1653_Y
+ connect \Y $not$libresoc.v:50835$1653_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253"
- cell $not $not$libresoc.v:50844$1654
+ cell $not $not$libresoc.v:50836$1654
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \core_coresync_rst
- connect \Y $not$libresoc.v:50844$1654_Y
+ connect \Y $not$libresoc.v:50836$1654_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253"
- cell $not $not$libresoc.v:50846$1656
+ cell $not $not$libresoc.v:50838$1656
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \dbg_core_stop_o
- connect \Y $not$libresoc.v:50846$1656_Y
+ connect \Y $not$libresoc.v:50838$1656_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253"
- cell $not $not$libresoc.v:50847$1657
+ cell $not $not$libresoc.v:50839$1657
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \core_coresync_rst
- connect \Y $not$libresoc.v:50847$1657_Y
+ connect \Y $not$libresoc.v:50839$1657_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253"
- cell $not $not$libresoc.v:50849$1659
+ cell $not $not$libresoc.v:50841$1659
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \dbg_core_stop_o
- connect \Y $not$libresoc.v:50849$1659_Y
+ connect \Y $not$libresoc.v:50841$1659_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253"
- cell $not $not$libresoc.v:50850$1660
+ cell $not $not$libresoc.v:50842$1660
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \core_coresync_rst
- connect \Y $not$libresoc.v:50850$1660_Y
+ connect \Y $not$libresoc.v:50842$1660_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:275"
- cell $not $not$libresoc.v:50852$1662
+ cell $not $not$libresoc.v:50844$1662
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \msr_read
- connect \Y $not$libresoc.v:50852$1662_Y
+ connect \Y $not$libresoc.v:50844$1662_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253"
- cell $not $not$libresoc.v:50853$1663
+ cell $not $not$libresoc.v:50845$1663
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \dbg_core_stop_o
- connect \Y $not$libresoc.v:50853$1663_Y
+ connect \Y $not$libresoc.v:50845$1663_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253"
- cell $not $not$libresoc.v:50854$1664
+ cell $not $not$libresoc.v:50846$1664
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \core_coresync_rst
- connect \Y $not$libresoc.v:50854$1664_Y
+ connect \Y $not$libresoc.v:50846$1664_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:180"
- cell $or $or$libresoc.v:50818$1628
+ cell $or $or$libresoc.v:50810$1628
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A 1'0
connect \B \dbg_core_rst_o
- connect \Y $or$libresoc.v:50818$1628_Y
+ connect \Y $or$libresoc.v:50810$1628_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:180"
- cell $or $or$libresoc.v:50819$1629
+ cell $or $or$libresoc.v:50811$1629
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$15
connect \B \rst
- connect \Y $or$libresoc.v:50819$1629_Y
+ connect \Y $or$libresoc.v:50811$1629_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- cell $pos $pos$libresoc.v:50813$1622
+ cell $pos $pos$libresoc.v:50805$1622
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 64
- connect \A $extend$libresoc.v:50813$1621_Y
- connect \Y $pos$libresoc.v:50813$1622_Y
+ connect \A $extend$libresoc.v:50805$1621_Y
+ connect \Y $pos$libresoc.v:50805$1622_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- cell $pos $pos$libresoc.v:50814$1624
+ cell $pos $pos$libresoc.v:50806$1624
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 64
- connect \A $extend$libresoc.v:50814$1623_Y
- connect \Y $pos$libresoc.v:50814$1624_Y
+ connect \A $extend$libresoc.v:50806$1623_Y
+ connect \Y $pos$libresoc.v:50806$1624_Y
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
- cell $reduce_or $reduce_or$libresoc.v:50833$1643
+ cell $reduce_or $reduce_or$libresoc.v:50825$1643
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \Y_WIDTH 1
connect \A \$45
- connect \Y $reduce_or$libresoc.v:50833$1643_Y
+ connect \Y $reduce_or$libresoc.v:50825$1643_Y
end
- attribute \src "libresoc.v:50809.19-50809.42"
- cell $shr $shr$libresoc.v:50809$1617
+ attribute \src "libresoc.v:50801.19-50801.42"
+ cell $shr $shr$libresoc.v:50801$1617
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \Y_WIDTH 64
connect \A \imem_f_instr_o
connect \B \$118
- connect \Y $shr$libresoc.v:50809$1617_Y
+ connect \Y $shr$libresoc.v:50801$1617_Y
end
- attribute \src "libresoc.v:50811.19-50811.42"
- cell $shr $shr$libresoc.v:50811$1619
+ attribute \src "libresoc.v:50803.19-50803.42"
+ cell $shr $shr$libresoc.v:50803$1619
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \Y_WIDTH 64
connect \A \imem_f_instr_o
connect \B \$122
- connect \Y $shr$libresoc.v:50811$1619_Y
+ connect \Y $shr$libresoc.v:50803$1619_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:393"
- cell $sub $sub$libresoc.v:50815$1625
+ cell $sub $sub$libresoc.v:50807$1625
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \Y_WIDTH 65
connect \A \issue__data_o
connect \B 1'1
- connect \Y $sub$libresoc.v:50815$1625_Y
+ connect \Y $sub$libresoc.v:50807$1625_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:175"
- cell $sub $sub$libresoc.v:50817$1627
+ cell $sub $sub$libresoc.v:50809$1627
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \delay
connect \B 1'1
- connect \Y $sub$libresoc.v:50817$1627_Y
+ connect \Y $sub$libresoc.v:50809$1627_Y
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:51027.8-51030.4"
+ attribute \src "libresoc.v:51019.8-51022.4"
cell \core \core
connect \coresync_clk \coresync_clk
connect \coresync_rst \core_coresync_rst
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:51031.7-51056.4"
+ attribute \src "libresoc.v:51023.7-51048.4"
cell \dbg \dbg
connect \clk \clk
connect \core_dbg_msr \dbg_core_dbg_msr
connect \terminate_i \dbg_terminate_i
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:51057.8-51123.4"
+ attribute \src "libresoc.v:51049.8-51115.4"
cell \dec2 \dec2
connect \asmcode \dec2_asmcode
connect \bigendian \dec2_bigendian
connect \xer_out \dec2_xer_out
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:51124.8-51140.4"
+ attribute \src "libresoc.v:51116.8-51132.4"
cell \imem \imem
connect \a_pc_i \imem_a_pc_i
connect \a_valid_i \imem_a_valid_i
connect \wb_icache_en \imem_wb_icache_en
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:51141.8-51471.4"
+ attribute \src "libresoc.v:51133.8-51463.4"
cell \jtag \jtag
connect \TAP_bus__tck \TAP_bus__tck
connect \TAP_bus__tdi \TAP_bus__tdi
connect \wb_icache_en \imem_wb_icache_en
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:51472.12-51486.4"
+ attribute \src "libresoc.v:51464.12-51478.4"
cell \xics_icp \xics_icp
connect \clk \clk
connect \core_irq_o \xics_icp_core_irq_o
connect \rst \rst
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:51487.12-51500.4"
+ attribute \src "libresoc.v:51479.12-51492.4"
cell \xics_ics \xics_ics
connect \clk \clk
connect \icp_o_pri \xics_ics_icp_o_pri
connect \int_level_i \int_level_i
connect \rst \rst
end
- attribute \src "libresoc.v:48741.7-48741.20"
- process $proc$libresoc.v:48741$2164
+ attribute \src "libresoc.v:48733.7-48733.20"
+ process $proc$libresoc.v:48733$2164
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:48873.7-48873.25"
- process $proc$libresoc.v:48873$2165
+ attribute \src "libresoc.v:48865.7-48865.25"
+ process $proc$libresoc.v:48865$2165
assign { } { }
assign $1\bigendian_i[0:0] 1'0
sync always
sync init
update \bigendian_i $1\bigendian_i[0:0]
end
- attribute \src "libresoc.v:48885.13-48885.33"
- process $proc$libresoc.v:48885$2166
+ attribute \src "libresoc.v:48877.13-48877.33"
+ process $proc$libresoc.v:48877$2166
assign { } { }
assign $1\core_asmcode[7:0] 8'00000000
sync always
sync init
update \core_asmcode $1\core_asmcode[7:0]
end
- attribute \src "libresoc.v:48891.14-48891.50"
- process $proc$libresoc.v:48891$2167
+ attribute \src "libresoc.v:48883.14-48883.50"
+ process $proc$libresoc.v:48883$2167
assign { } { }
assign $1\core_core_cia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \core_core_cia $1\core_core_cia[63:0]
end
- attribute \src "libresoc.v:48895.13-48895.36"
- process $proc$libresoc.v:48895$2168
+ attribute \src "libresoc.v:48887.13-48887.36"
+ process $proc$libresoc.v:48887$2168
assign { } { }
assign $1\core_core_cr_rd[7:0] 8'00000000
sync always
sync init
update \core_core_cr_rd $1\core_core_cr_rd[7:0]
end
- attribute \src "libresoc.v:48899.7-48899.32"
- process $proc$libresoc.v:48899$2169
+ attribute \src "libresoc.v:48891.7-48891.32"
+ process $proc$libresoc.v:48891$2169
assign { } { }
assign $1\core_core_cr_rd_ok[0:0] 1'0
sync always
sync init
update \core_core_cr_rd_ok $1\core_core_cr_rd_ok[0:0]
end
- attribute \src "libresoc.v:48903.13-48903.36"
- process $proc$libresoc.v:48903$2170
+ attribute \src "libresoc.v:48895.13-48895.36"
+ process $proc$libresoc.v:48895$2170
assign { } { }
assign $1\core_core_cr_wr[7:0] 8'00000000
sync always
sync init
update \core_core_cr_wr $1\core_core_cr_wr[7:0]
end
- attribute \src "libresoc.v:48907.7-48907.32"
- process $proc$libresoc.v:48907$2171
+ attribute \src "libresoc.v:48899.7-48899.32"
+ process $proc$libresoc.v:48899$2171
assign { } { }
assign $1\core_core_cr_wr_ok[0:0] 1'0
sync always
sync init
update \core_core_cr_wr_ok $1\core_core_cr_wr_ok[0:0]
end
- attribute \src "libresoc.v:48911.7-48911.37"
- process $proc$libresoc.v:48911$2172
+ attribute \src "libresoc.v:48903.7-48903.37"
+ process $proc$libresoc.v:48903$2172
assign { } { }
assign $0\core_core_exc_$signal[0:0]$2173 1'0
sync always
sync init
update \core_core_exc_$signal $0\core_core_exc_$signal[0:0]$2173
end
- attribute \src "libresoc.v:48913.7-48913.40"
- process $proc$libresoc.v:48913$2174
+ attribute \src "libresoc.v:48905.7-48905.40"
+ process $proc$libresoc.v:48905$2174
assign { } { }
assign $0\core_core_exc_$signal$50[0:0]$2175 1'0
sync always
sync init
update \core_core_exc_$signal$50 $0\core_core_exc_$signal$50[0:0]$2175
end
- attribute \src "libresoc.v:48917.7-48917.40"
- process $proc$libresoc.v:48917$2176
+ attribute \src "libresoc.v:48909.7-48909.40"
+ process $proc$libresoc.v:48909$2176
assign { } { }
assign $0\core_core_exc_$signal$51[0:0]$2177 1'0
sync always
sync init
update \core_core_exc_$signal$51 $0\core_core_exc_$signal$51[0:0]$2177
end
- attribute \src "libresoc.v:48921.7-48921.40"
- process $proc$libresoc.v:48921$2178
+ attribute \src "libresoc.v:48913.7-48913.40"
+ process $proc$libresoc.v:48913$2178
assign { } { }
assign $0\core_core_exc_$signal$52[0:0]$2179 1'0
sync always
sync init
update \core_core_exc_$signal$52 $0\core_core_exc_$signal$52[0:0]$2179
end
- attribute \src "libresoc.v:48925.7-48925.40"
- process $proc$libresoc.v:48925$2180
+ attribute \src "libresoc.v:48917.7-48917.40"
+ process $proc$libresoc.v:48917$2180
assign { } { }
assign $0\core_core_exc_$signal$53[0:0]$2181 1'0
sync always
sync init
update \core_core_exc_$signal$53 $0\core_core_exc_$signal$53[0:0]$2181
end
- attribute \src "libresoc.v:48929.7-48929.40"
- process $proc$libresoc.v:48929$2182
+ attribute \src "libresoc.v:48921.7-48921.40"
+ process $proc$libresoc.v:48921$2182
assign { } { }
assign $0\core_core_exc_$signal$54[0:0]$2183 1'0
sync always
sync init
update \core_core_exc_$signal$54 $0\core_core_exc_$signal$54[0:0]$2183
end
- attribute \src "libresoc.v:48933.7-48933.40"
- process $proc$libresoc.v:48933$2184
+ attribute \src "libresoc.v:48925.7-48925.40"
+ process $proc$libresoc.v:48925$2184
assign { } { }
assign $0\core_core_exc_$signal$55[0:0]$2185 1'0
sync always
sync init
update \core_core_exc_$signal$55 $0\core_core_exc_$signal$55[0:0]$2185
end
- attribute \src "libresoc.v:48937.7-48937.40"
- process $proc$libresoc.v:48937$2186
+ attribute \src "libresoc.v:48929.7-48929.40"
+ process $proc$libresoc.v:48929$2186
assign { } { }
assign $0\core_core_exc_$signal$56[0:0]$2187 1'0
sync always
sync init
update \core_core_exc_$signal$56 $0\core_core_exc_$signal$56[0:0]$2187
end
- attribute \src "libresoc.v:48956.14-48956.41"
- process $proc$libresoc.v:48956$2188
+ attribute \src "libresoc.v:48948.14-48948.41"
+ process $proc$libresoc.v:48948$2188
assign { } { }
assign $1\core_core_fn_unit[11:0] 12'000000000000
sync always
sync init
update \core_core_fn_unit $1\core_core_fn_unit[11:0]
end
- attribute \src "libresoc.v:48964.13-48964.41"
- process $proc$libresoc.v:48964$2189
+ attribute \src "libresoc.v:48956.13-48956.41"
+ process $proc$libresoc.v:48956$2189
assign { } { }
assign $1\core_core_input_carry[1:0] 2'00
sync always
sync init
update \core_core_input_carry $1\core_core_input_carry[1:0]
end
- attribute \src "libresoc.v:48968.14-48968.36"
- process $proc$libresoc.v:48968$2190
+ attribute \src "libresoc.v:48960.14-48960.36"
+ process $proc$libresoc.v:48960$2190
assign { } { }
assign $1\core_core_insn[31:0] 0
sync always
sync init
update \core_core_insn $1\core_core_insn[31:0]
end
- attribute \src "libresoc.v:49046.13-49046.40"
- process $proc$libresoc.v:49046$2191
+ attribute \src "libresoc.v:49038.13-49038.40"
+ process $proc$libresoc.v:49038$2191
assign { } { }
assign $1\core_core_insn_type[6:0] 7'0000000
sync always
sync init
update \core_core_insn_type $1\core_core_insn_type[6:0]
end
- attribute \src "libresoc.v:49050.7-49050.32"
- process $proc$libresoc.v:49050$2192
+ attribute \src "libresoc.v:49042.7-49042.32"
+ process $proc$libresoc.v:49042$2192
assign { } { }
assign $1\core_core_is_32bit[0:0] 1'0
sync always
sync init
update \core_core_is_32bit $1\core_core_is_32bit[0:0]
end
- attribute \src "libresoc.v:49054.7-49054.26"
- process $proc$libresoc.v:49054$2193
+ attribute \src "libresoc.v:49046.7-49046.26"
+ process $proc$libresoc.v:49046$2193
assign { } { }
assign $1\core_core_lk[0:0] 1'0
sync always
sync init
update \core_core_lk $1\core_core_lk[0:0]
end
- attribute \src "libresoc.v:49058.14-49058.50"
- process $proc$libresoc.v:49058$2194
+ attribute \src "libresoc.v:49050.14-49050.50"
+ process $proc$libresoc.v:49050$2194
assign { } { }
assign $1\core_core_msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \core_core_msr $1\core_core_msr[63:0]
end
- attribute \src "libresoc.v:49062.7-49062.26"
- process $proc$libresoc.v:49062$2195
+ attribute \src "libresoc.v:49054.7-49054.26"
+ process $proc$libresoc.v:49054$2195
assign { } { }
assign $1\core_core_oe[0:0] 1'0
sync always
sync init
update \core_core_oe $1\core_core_oe[0:0]
end
- attribute \src "libresoc.v:49066.7-49066.29"
- process $proc$libresoc.v:49066$2196
+ attribute \src "libresoc.v:49058.7-49058.29"
+ process $proc$libresoc.v:49058$2196
assign { } { }
assign $1\core_core_oe_ok[0:0] 1'0
sync always
sync init
update \core_core_oe_ok $1\core_core_oe_ok[0:0]
end
- attribute \src "libresoc.v:49070.7-49070.26"
- process $proc$libresoc.v:49070$2197
+ attribute \src "libresoc.v:49062.7-49062.26"
+ process $proc$libresoc.v:49062$2197
assign { } { }
assign $1\core_core_rc[0:0] 1'0
sync always
sync init
update \core_core_rc $1\core_core_rc[0:0]
end
- attribute \src "libresoc.v:49074.7-49074.29"
- process $proc$libresoc.v:49074$2198
+ attribute \src "libresoc.v:49066.7-49066.29"
+ process $proc$libresoc.v:49066$2198
assign { } { }
assign $1\core_core_rc_ok[0:0] 1'0
sync always
sync init
update \core_core_rc_ok $1\core_core_rc_ok[0:0]
end
- attribute \src "libresoc.v:49078.14-49078.43"
- process $proc$libresoc.v:49078$2199
+ attribute \src "libresoc.v:49070.14-49070.43"
+ process $proc$libresoc.v:49070$2199
assign { } { }
assign $1\core_core_trapaddr[12:0] 13'0000000000000
sync always
sync init
update \core_core_trapaddr $1\core_core_trapaddr[12:0]
end
- attribute \src "libresoc.v:49082.13-49082.39"
- process $proc$libresoc.v:49082$2200
+ attribute \src "libresoc.v:49074.13-49074.39"
+ process $proc$libresoc.v:49074$2200
assign { } { }
assign $1\core_core_traptype[7:0] 8'00000000
sync always
sync init
update \core_core_traptype $1\core_core_traptype[7:0]
end
- attribute \src "libresoc.v:49088.13-49088.31"
- process $proc$libresoc.v:49088$2201
+ attribute \src "libresoc.v:49080.13-49080.31"
+ process $proc$libresoc.v:49080$2201
assign { } { }
assign $1\core_cr_in1[2:0] 3'000
sync always
sync init
update \core_cr_in1 $1\core_cr_in1[2:0]
end
- attribute \src "libresoc.v:49092.7-49092.28"
- process $proc$libresoc.v:49092$2202
+ attribute \src "libresoc.v:49084.7-49084.28"
+ process $proc$libresoc.v:49084$2202
assign { } { }
assign $1\core_cr_in1_ok[0:0] 1'0
sync always
sync init
update \core_cr_in1_ok $1\core_cr_in1_ok[0:0]
end
- attribute \src "libresoc.v:49096.13-49096.31"
- process $proc$libresoc.v:49096$2203
+ attribute \src "libresoc.v:49088.13-49088.31"
+ process $proc$libresoc.v:49088$2203
assign { } { }
assign $1\core_cr_in2[2:0] 3'000
sync always
sync init
update \core_cr_in2 $1\core_cr_in2[2:0]
end
- attribute \src "libresoc.v:49098.13-49098.36"
- process $proc$libresoc.v:49098$2204
+ attribute \src "libresoc.v:49090.13-49090.36"
+ process $proc$libresoc.v:49090$2204
assign { } { }
assign $0\core_cr_in2$48[2:0]$2205 3'000
sync always
sync init
update \core_cr_in2$48 $0\core_cr_in2$48[2:0]$2205
end
- attribute \src "libresoc.v:49104.7-49104.28"
- process $proc$libresoc.v:49104$2206
+ attribute \src "libresoc.v:49096.7-49096.28"
+ process $proc$libresoc.v:49096$2206
assign { } { }
assign $1\core_cr_in2_ok[0:0] 1'0
sync always
sync init
update \core_cr_in2_ok $1\core_cr_in2_ok[0:0]
end
- attribute \src "libresoc.v:49106.7-49106.33"
- process $proc$libresoc.v:49106$2207
+ attribute \src "libresoc.v:49098.7-49098.33"
+ process $proc$libresoc.v:49098$2207
assign { } { }
assign $0\core_cr_in2_ok$49[0:0]$2208 1'0
sync always
sync init
update \core_cr_in2_ok$49 $0\core_cr_in2_ok$49[0:0]$2208
end
- attribute \src "libresoc.v:49112.13-49112.31"
- process $proc$libresoc.v:49112$2209
+ attribute \src "libresoc.v:49104.13-49104.31"
+ process $proc$libresoc.v:49104$2209
assign { } { }
assign $1\core_cr_out[2:0] 3'000
sync always
sync init
update \core_cr_out $1\core_cr_out[2:0]
end
- attribute \src "libresoc.v:49116.7-49116.28"
- process $proc$libresoc.v:49116$2210
+ attribute \src "libresoc.v:49108.7-49108.28"
+ process $proc$libresoc.v:49108$2210
assign { } { }
assign $1\core_cr_out_ok[0:0] 1'0
sync always
sync init
update \core_cr_out_ok $1\core_cr_out_ok[0:0]
end
- attribute \src "libresoc.v:49120.14-49120.45"
- process $proc$libresoc.v:49120$2211
+ attribute \src "libresoc.v:49112.14-49112.45"
+ process $proc$libresoc.v:49112$2211
assign { } { }
assign $1\core_dec[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \core_dec $1\core_dec[63:0]
end
- attribute \src "libresoc.v:49124.13-49124.28"
- process $proc$libresoc.v:49124$2212
+ attribute \src "libresoc.v:49116.13-49116.28"
+ process $proc$libresoc.v:49116$2212
assign { } { }
assign $1\core_ea[4:0] 5'00000
sync always
sync init
update \core_ea $1\core_ea[4:0]
end
- attribute \src "libresoc.v:49128.7-49128.24"
- process $proc$libresoc.v:49128$2213
+ attribute \src "libresoc.v:49120.7-49120.24"
+ process $proc$libresoc.v:49120$2213
assign { } { }
assign $1\core_ea_ok[0:0] 1'0
sync always
sync init
update \core_ea_ok $1\core_ea_ok[0:0]
end
- attribute \src "libresoc.v:49132.7-49132.23"
- process $proc$libresoc.v:49132$2214
+ attribute \src "libresoc.v:49124.7-49124.23"
+ process $proc$libresoc.v:49124$2214
assign { } { }
assign $1\core_eint[0:0] 1'0
sync always
sync init
update \core_eint $1\core_eint[0:0]
end
- attribute \src "libresoc.v:49136.13-49136.30"
- process $proc$libresoc.v:49136$2215
+ attribute \src "libresoc.v:49128.13-49128.30"
+ process $proc$libresoc.v:49128$2215
assign { } { }
assign $1\core_fast1[2:0] 3'000
sync always
sync init
update \core_fast1 $1\core_fast1[2:0]
end
- attribute \src "libresoc.v:49140.7-49140.27"
- process $proc$libresoc.v:49140$2216
+ attribute \src "libresoc.v:49132.7-49132.27"
+ process $proc$libresoc.v:49132$2216
assign { } { }
assign $1\core_fast1_ok[0:0] 1'0
sync always
sync init
update \core_fast1_ok $1\core_fast1_ok[0:0]
end
- attribute \src "libresoc.v:49144.13-49144.30"
- process $proc$libresoc.v:49144$2217
+ attribute \src "libresoc.v:49136.13-49136.30"
+ process $proc$libresoc.v:49136$2217
assign { } { }
assign $1\core_fast2[2:0] 3'000
sync always
sync init
update \core_fast2 $1\core_fast2[2:0]
end
- attribute \src "libresoc.v:49148.7-49148.27"
- process $proc$libresoc.v:49148$2218
+ attribute \src "libresoc.v:49140.7-49140.27"
+ process $proc$libresoc.v:49140$2218
assign { } { }
assign $1\core_fast2_ok[0:0] 1'0
sync always
sync init
update \core_fast2_ok $1\core_fast2_ok[0:0]
end
- attribute \src "libresoc.v:49152.13-49152.31"
- process $proc$libresoc.v:49152$2219
+ attribute \src "libresoc.v:49144.13-49144.31"
+ process $proc$libresoc.v:49144$2219
assign { } { }
assign $1\core_fasto1[2:0] 3'000
sync always
sync init
update \core_fasto1 $1\core_fasto1[2:0]
end
- attribute \src "libresoc.v:49156.7-49156.28"
- process $proc$libresoc.v:49156$2220
+ attribute \src "libresoc.v:49148.7-49148.28"
+ process $proc$libresoc.v:49148$2220
assign { } { }
assign $1\core_fasto1_ok[0:0] 1'0
sync always
sync init
update \core_fasto1_ok $1\core_fasto1_ok[0:0]
end
- attribute \src "libresoc.v:49160.13-49160.31"
- process $proc$libresoc.v:49160$2221
+ attribute \src "libresoc.v:49152.13-49152.31"
+ process $proc$libresoc.v:49152$2221
assign { } { }
assign $1\core_fasto2[2:0] 3'000
sync always
sync init
update \core_fasto2 $1\core_fasto2[2:0]
end
- attribute \src "libresoc.v:49164.7-49164.28"
- process $proc$libresoc.v:49164$2222
+ attribute \src "libresoc.v:49156.7-49156.28"
+ process $proc$libresoc.v:49156$2222
assign { } { }
assign $1\core_fasto2_ok[0:0] 1'0
sync always
sync init
update \core_fasto2_ok $1\core_fasto2_ok[0:0]
end
- attribute \src "libresoc.v:49168.14-49168.45"
- process $proc$libresoc.v:49168$2223
+ attribute \src "libresoc.v:49160.14-49160.45"
+ process $proc$libresoc.v:49160$2223
assign { } { }
assign $1\core_msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \core_msr $1\core_msr[63:0]
end
- attribute \src "libresoc.v:49172.14-49172.44"
- process $proc$libresoc.v:49172$2224
+ attribute \src "libresoc.v:49164.14-49164.44"
+ process $proc$libresoc.v:49164$2224
assign { } { }
assign $1\core_pc[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \core_pc $1\core_pc[63:0]
end
- attribute \src "libresoc.v:49176.13-49176.30"
- process $proc$libresoc.v:49176$2225
+ attribute \src "libresoc.v:49168.13-49168.30"
+ process $proc$libresoc.v:49168$2225
assign { } { }
assign $1\core_reg1[4:0] 5'00000
sync always
sync init
update \core_reg1 $1\core_reg1[4:0]
end
- attribute \src "libresoc.v:49180.7-49180.26"
- process $proc$libresoc.v:49180$2226
+ attribute \src "libresoc.v:49172.7-49172.26"
+ process $proc$libresoc.v:49172$2226
assign { } { }
assign $1\core_reg1_ok[0:0] 1'0
sync always
sync init
update \core_reg1_ok $1\core_reg1_ok[0:0]
end
- attribute \src "libresoc.v:49184.13-49184.30"
- process $proc$libresoc.v:49184$2227
+ attribute \src "libresoc.v:49176.13-49176.30"
+ process $proc$libresoc.v:49176$2227
assign { } { }
assign $1\core_reg2[4:0] 5'00000
sync always
sync init
update \core_reg2 $1\core_reg2[4:0]
end
- attribute \src "libresoc.v:49188.7-49188.26"
- process $proc$libresoc.v:49188$2228
+ attribute \src "libresoc.v:49180.7-49180.26"
+ process $proc$libresoc.v:49180$2228
assign { } { }
assign $1\core_reg2_ok[0:0] 1'0
sync always
sync init
update \core_reg2_ok $1\core_reg2_ok[0:0]
end
- attribute \src "libresoc.v:49192.13-49192.30"
- process $proc$libresoc.v:49192$2229
+ attribute \src "libresoc.v:49184.13-49184.30"
+ process $proc$libresoc.v:49184$2229
assign { } { }
assign $1\core_reg3[4:0] 5'00000
sync always
sync init
update \core_reg3 $1\core_reg3[4:0]
end
- attribute \src "libresoc.v:49196.7-49196.26"
- process $proc$libresoc.v:49196$2230
+ attribute \src "libresoc.v:49188.7-49188.26"
+ process $proc$libresoc.v:49188$2230
assign { } { }
assign $1\core_reg3_ok[0:0] 1'0
sync always
sync init
update \core_reg3_ok $1\core_reg3_ok[0:0]
end
- attribute \src "libresoc.v:49200.13-49200.30"
- process $proc$libresoc.v:49200$2231
+ attribute \src "libresoc.v:49192.13-49192.30"
+ process $proc$libresoc.v:49192$2231
assign { } { }
assign $1\core_rego[4:0] 5'00000
sync always
sync init
update \core_rego $1\core_rego[4:0]
end
- attribute \src "libresoc.v:49204.7-49204.26"
- process $proc$libresoc.v:49204$2232
+ attribute \src "libresoc.v:49196.7-49196.26"
+ process $proc$libresoc.v:49196$2232
assign { } { }
assign $1\core_rego_ok[0:0] 1'0
sync always
sync init
update \core_rego_ok $1\core_rego_ok[0:0]
end
- attribute \src "libresoc.v:49319.13-49319.32"
- process $proc$libresoc.v:49319$2233
+ attribute \src "libresoc.v:49311.13-49311.32"
+ process $proc$libresoc.v:49311$2233
assign { } { }
assign $1\core_spr1[9:0] 10'0000000000
sync always
sync init
update \core_spr1 $1\core_spr1[9:0]
end
- attribute \src "libresoc.v:49323.7-49323.26"
- process $proc$libresoc.v:49323$2234
+ attribute \src "libresoc.v:49315.7-49315.26"
+ process $proc$libresoc.v:49315$2234
assign { } { }
assign $1\core_spr1_ok[0:0] 1'0
sync always
sync init
update \core_spr1_ok $1\core_spr1_ok[0:0]
end
- attribute \src "libresoc.v:49438.13-49438.32"
- process $proc$libresoc.v:49438$2235
+ attribute \src "libresoc.v:49430.13-49430.32"
+ process $proc$libresoc.v:49430$2235
assign { } { }
assign $1\core_spro[9:0] 10'0000000000
sync always
sync init
update \core_spro $1\core_spro[9:0]
end
- attribute \src "libresoc.v:49442.7-49442.26"
- process $proc$libresoc.v:49442$2236
+ attribute \src "libresoc.v:49434.7-49434.26"
+ process $proc$libresoc.v:49434$2236
assign { } { }
assign $1\core_spro_ok[0:0] 1'0
sync always
sync init
update \core_spro_ok $1\core_spro_ok[0:0]
end
- attribute \src "libresoc.v:49450.13-49450.31"
- process $proc$libresoc.v:49450$2237
+ attribute \src "libresoc.v:49442.13-49442.31"
+ process $proc$libresoc.v:49442$2237
assign { } { }
assign $1\core_xer_in[2:0] 3'000
sync always
sync init
update \core_xer_in $1\core_xer_in[2:0]
end
- attribute \src "libresoc.v:49454.7-49454.26"
- process $proc$libresoc.v:49454$2238
+ attribute \src "libresoc.v:49446.7-49446.26"
+ process $proc$libresoc.v:49446$2238
assign { } { }
assign $1\core_xer_out[0:0] 1'0
sync always
sync init
update \core_xer_out $1\core_xer_out[0:0]
end
- attribute \src "libresoc.v:49470.7-49470.30"
- process $proc$libresoc.v:49470$2239
+ attribute \src "libresoc.v:49462.7-49462.30"
+ process $proc$libresoc.v:49462$2239
assign { } { }
assign $1\cu_st__rel_o_dly[0:0] 1'0
sync always
sync init
update \cu_st__rel_o_dly $1\cu_st__rel_o_dly[0:0]
end
- attribute \src "libresoc.v:49476.7-49476.24"
- process $proc$libresoc.v:49476$2240
+ attribute \src "libresoc.v:49468.7-49468.24"
+ process $proc$libresoc.v:49468$2240
assign { } { }
assign $1\d_cr_delay[0:0] 1'0
sync always
sync init
update \d_cr_delay $1\d_cr_delay[0:0]
end
- attribute \src "libresoc.v:49480.7-49480.25"
- process $proc$libresoc.v:49480$2241
+ attribute \src "libresoc.v:49472.7-49472.25"
+ process $proc$libresoc.v:49472$2241
assign { } { }
assign $1\d_reg_delay[0:0] 1'0
sync always
sync init
update \d_reg_delay $1\d_reg_delay[0:0]
end
- attribute \src "libresoc.v:49484.7-49484.25"
- process $proc$libresoc.v:49484$2242
+ attribute \src "libresoc.v:49476.7-49476.25"
+ process $proc$libresoc.v:49476$2242
assign { } { }
assign $1\d_xer_delay[0:0] 1'0
sync always
sync init
update \d_xer_delay $1\d_xer_delay[0:0]
end
- attribute \src "libresoc.v:49522.13-49522.34"
- process $proc$libresoc.v:49522$2243
+ attribute \src "libresoc.v:49514.13-49514.34"
+ process $proc$libresoc.v:49514$2243
assign { } { }
assign $1\dbg_dmi_addr_i[3:0] 4'0000
sync always
sync init
update \dbg_dmi_addr_i $1\dbg_dmi_addr_i[3:0]
end
- attribute \src "libresoc.v:49526.14-49526.48"
- process $proc$libresoc.v:49526$2244
+ attribute \src "libresoc.v:49518.14-49518.48"
+ process $proc$libresoc.v:49518$2244
assign { } { }
assign $1\dbg_dmi_din[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \dbg_dmi_din $1\dbg_dmi_din[63:0]
end
- attribute \src "libresoc.v:49532.7-49532.27"
- process $proc$libresoc.v:49532$2245
+ attribute \src "libresoc.v:49524.7-49524.27"
+ process $proc$libresoc.v:49524$2245
assign { } { }
assign $1\dbg_dmi_req_i[0:0] 1'0
sync always
sync init
update \dbg_dmi_req_i $1\dbg_dmi_req_i[0:0]
end
- attribute \src "libresoc.v:49536.7-49536.26"
- process $proc$libresoc.v:49536$2246
+ attribute \src "libresoc.v:49528.7-49528.26"
+ process $proc$libresoc.v:49528$2246
assign { } { }
assign $1\dbg_dmi_we_i[0:0] 1'0
sync always
sync init
update \dbg_dmi_we_i $1\dbg_dmi_we_i[0:0]
end
- attribute \src "libresoc.v:49572.14-49572.49"
- process $proc$libresoc.v:49572$2247
+ attribute \src "libresoc.v:49564.14-49564.49"
+ process $proc$libresoc.v:49564$2247
assign { } { }
assign $1\dec2_cur_dec[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \dec2_cur_dec $1\dec2_cur_dec[63:0]
end
- attribute \src "libresoc.v:49576.7-49576.27"
- process $proc$libresoc.v:49576$2248
+ attribute \src "libresoc.v:49568.7-49568.27"
+ process $proc$libresoc.v:49568$2248
assign { } { }
assign $1\dec2_cur_eint[0:0] 1'0
sync always
sync init
update \dec2_cur_eint $1\dec2_cur_eint[0:0]
end
- attribute \src "libresoc.v:49580.14-49580.49"
- process $proc$libresoc.v:49580$2249
+ attribute \src "libresoc.v:49572.14-49572.49"
+ process $proc$libresoc.v:49572$2249
assign { } { }
assign $1\dec2_cur_msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \dec2_cur_msr $1\dec2_cur_msr[63:0]
end
- attribute \src "libresoc.v:49584.14-49584.48"
- process $proc$libresoc.v:49584$2250
+ attribute \src "libresoc.v:49576.14-49576.48"
+ process $proc$libresoc.v:49576$2250
assign { } { }
assign $1\dec2_cur_pc[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \dec2_cur_pc $1\dec2_cur_pc[63:0]
end
- attribute \src "libresoc.v:49993.13-49993.25"
- process $proc$libresoc.v:49993$2251
+ attribute \src "libresoc.v:49985.13-49985.25"
+ process $proc$libresoc.v:49985$2251
assign { } { }
assign $1\delay[1:0] 2'11
sync always
sync init
update \delay $1\delay[1:0]
end
- attribute \src "libresoc.v:50015.13-50015.29"
- process $proc$libresoc.v:50015$2252
+ attribute \src "libresoc.v:50007.13-50007.29"
+ process $proc$libresoc.v:50007$2252
assign { } { }
assign $1\fsm_state[1:0] 2'00
sync always
sync init
update \fsm_state $1\fsm_state[1:0]
end
- attribute \src "libresoc.v:50017.13-50017.35"
- process $proc$libresoc.v:50017$2253
+ attribute \src "libresoc.v:50009.13-50009.35"
+ process $proc$libresoc.v:50009$2253
assign { } { }
assign $0\fsm_state$131[1:0]$2254 2'00
sync always
sync init
update \fsm_state$131 $0\fsm_state$131[1:0]$2254
end
- attribute \src "libresoc.v:50267.14-50267.28"
- process $proc$libresoc.v:50267$2255
+ attribute \src "libresoc.v:50259.14-50259.28"
+ process $proc$libresoc.v:50259$2255
assign { } { }
assign $1\ilatch[31:0] 0
sync always
sync init
update \ilatch $1\ilatch[31:0]
end
- attribute \src "libresoc.v:50301.7-50301.30"
- process $proc$libresoc.v:50301$2256
+ attribute \src "libresoc.v:50293.7-50293.30"
+ process $proc$libresoc.v:50293$2256
assign { } { }
assign $1\jtag_dmi0__ack_o[0:0] 1'0
sync always
sync init
update \jtag_dmi0__ack_o $1\jtag_dmi0__ack_o[0:0]
end
- attribute \src "libresoc.v:50309.14-50309.52"
- process $proc$libresoc.v:50309$2257
+ attribute \src "libresoc.v:50301.14-50301.52"
+ process $proc$libresoc.v:50301$2257
assign { } { }
assign $1\jtag_dmi0__dout[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \jtag_dmi0__dout $1\jtag_dmi0__dout[63:0]
end
- attribute \src "libresoc.v:50369.7-50369.22"
- process $proc$libresoc.v:50369$2258
+ attribute \src "libresoc.v:50361.7-50361.22"
+ process $proc$libresoc.v:50361$2258
assign { } { }
assign $1\msr_read[0:0] 1'1
sync always
sync init
update \msr_read $1\msr_read[0:0]
end
- attribute \src "libresoc.v:50397.7-50397.24"
- process $proc$libresoc.v:50397$2259
+ attribute \src "libresoc.v:50389.7-50389.24"
+ process $proc$libresoc.v:50389$2259
assign { } { }
assign $1\pc_changed[0:0] 1'0
sync always
sync init
update \pc_changed $1\pc_changed[0:0]
end
- attribute \src "libresoc.v:50407.7-50407.25"
- process $proc$libresoc.v:50407$2260
+ attribute \src "libresoc.v:50399.7-50399.25"
+ process $proc$libresoc.v:50399$2260
assign { } { }
assign $1\pc_ok_delay[0:0] 1'0
sync always
sync init
update \pc_ok_delay $1\pc_ok_delay[0:0]
end
- attribute \src "libresoc.v:50421.14-50421.32"
- process $proc$libresoc.v:50421$2261
+ attribute \src "libresoc.v:50413.14-50413.32"
+ process $proc$libresoc.v:50413$2261
assign { } { }
assign $1\raw_insn_i[31:0] 0
sync always
sync init
update \raw_insn_i $1\raw_insn_i[31:0]
end
- attribute \src "libresoc.v:50855.3-50856.41"
- process $proc$libresoc.v:50855$1665
+ attribute \src "libresoc.v:50847.3-50848.41"
+ process $proc$libresoc.v:50847$1665
assign { } { }
assign $0\dec2_cur_dec[63:0] \dec2_cur_dec$next
sync posedge \clk
update \dec2_cur_dec $0\dec2_cur_dec[63:0]
end
- attribute \src "libresoc.v:50857.3-50858.33"
- process $proc$libresoc.v:50857$1666
+ attribute \src "libresoc.v:50849.3-50850.33"
+ process $proc$libresoc.v:50849$1666
assign { } { }
assign $0\core_dec[63:0] \core_dec$next
sync posedge \clk
update \core_dec $0\core_dec[63:0]
end
- attribute \src "libresoc.v:50859.3-50860.41"
- process $proc$libresoc.v:50859$1667
+ attribute \src "libresoc.v:50851.3-50852.41"
+ process $proc$libresoc.v:50851$1667
assign { } { }
assign $0\dec2_cur_msr[63:0] \dec2_cur_msr$next
sync posedge \clk
update \dec2_cur_msr $0\dec2_cur_msr[63:0]
end
- attribute \src "libresoc.v:50861.3-50862.35"
- process $proc$libresoc.v:50861$1668
+ attribute \src "libresoc.v:50853.3-50854.35"
+ process $proc$libresoc.v:50853$1668
assign { } { }
assign $0\fsm_state[1:0] \fsm_state$next
sync posedge \clk
update \fsm_state $0\fsm_state[1:0]
end
- attribute \src "libresoc.v:50863.3-50864.33"
- process $proc$libresoc.v:50863$1669
+ attribute \src "libresoc.v:50855.3-50856.33"
+ process $proc$libresoc.v:50855$1669
assign { } { }
assign $0\msr_read[0:0] \msr_read$next
sync posedge \clk
update \msr_read $0\msr_read[0:0]
end
- attribute \src "libresoc.v:50865.3-50866.39"
- process $proc$libresoc.v:50865$1670
+ attribute \src "libresoc.v:50857.3-50858.39"
+ process $proc$libresoc.v:50857$1670
assign { } { }
assign $0\dec2_cur_pc[63:0] \dec2_cur_pc$next
sync posedge \clk
update \dec2_cur_pc $0\dec2_cur_pc[63:0]
end
- attribute \src "libresoc.v:50867.3-50868.39"
- process $proc$libresoc.v:50867$1671
+ attribute \src "libresoc.v:50859.3-50860.39"
+ process $proc$libresoc.v:50859$1671
assign { } { }
assign $0\bigendian_i[0:0] \bigendian_i$next
sync posedge \clk
update \bigendian_i $0\bigendian_i[0:0]
end
- attribute \src "libresoc.v:50869.3-50870.37"
- process $proc$libresoc.v:50869$1672
+ attribute \src "libresoc.v:50861.3-50862.37"
+ process $proc$libresoc.v:50861$1672
assign { } { }
assign $0\raw_insn_i[31:0] \raw_insn_i$next
sync posedge \clk
update \raw_insn_i $0\raw_insn_i[31:0]
end
- attribute \src "libresoc.v:50871.3-50872.41"
- process $proc$libresoc.v:50871$1673
+ attribute \src "libresoc.v:50863.3-50864.41"
+ process $proc$libresoc.v:50863$1673
assign { } { }
assign $0\core_asmcode[7:0] \core_asmcode$next
sync posedge \clk
update \core_asmcode $0\core_asmcode[7:0]
end
- attribute \src "libresoc.v:50873.3-50874.35"
- process $proc$libresoc.v:50873$1674
+ attribute \src "libresoc.v:50865.3-50866.35"
+ process $proc$libresoc.v:50865$1674
assign { } { }
assign $0\core_rego[4:0] \core_rego$next
sync posedge \clk
update \core_rego $0\core_rego[4:0]
end
- attribute \src "libresoc.v:50875.3-50876.41"
- process $proc$libresoc.v:50875$1675
+ attribute \src "libresoc.v:50867.3-50868.41"
+ process $proc$libresoc.v:50867$1675
assign { } { }
assign $0\core_rego_ok[0:0] \core_rego_ok$next
sync posedge \clk
update \core_rego_ok $0\core_rego_ok[0:0]
end
- attribute \src "libresoc.v:50877.3-50878.45"
- process $proc$libresoc.v:50877$1676
+ attribute \src "libresoc.v:50869.3-50870.45"
+ process $proc$libresoc.v:50869$1676
assign { } { }
assign $0\fsm_state$131[1:0]$1677 \fsm_state$131$next
sync posedge \clk
update \fsm_state$131 $0\fsm_state$131[1:0]$1677
end
- attribute \src "libresoc.v:50879.3-50880.31"
- process $proc$libresoc.v:50879$1678
+ attribute \src "libresoc.v:50871.3-50872.31"
+ process $proc$libresoc.v:50871$1678
assign { } { }
assign $0\core_ea[4:0] \core_ea$next
sync posedge \clk
update \core_ea $0\core_ea[4:0]
end
- attribute \src "libresoc.v:50881.3-50882.37"
- process $proc$libresoc.v:50881$1679
+ attribute \src "libresoc.v:50873.3-50874.37"
+ process $proc$libresoc.v:50873$1679
assign { } { }
assign $0\core_ea_ok[0:0] \core_ea_ok$next
sync posedge \clk
update \core_ea_ok $0\core_ea_ok[0:0]
end
- attribute \src "libresoc.v:50883.3-50884.35"
- process $proc$libresoc.v:50883$1680
+ attribute \src "libresoc.v:50875.3-50876.35"
+ process $proc$libresoc.v:50875$1680
assign { } { }
assign $0\core_reg1[4:0] \core_reg1$next
sync posedge \clk
update \core_reg1 $0\core_reg1[4:0]
end
- attribute \src "libresoc.v:50885.3-50886.41"
- process $proc$libresoc.v:50885$1681
+ attribute \src "libresoc.v:50877.3-50878.41"
+ process $proc$libresoc.v:50877$1681
assign { } { }
assign $0\core_reg1_ok[0:0] \core_reg1_ok$next
sync posedge \clk
update \core_reg1_ok $0\core_reg1_ok[0:0]
end
- attribute \src "libresoc.v:50887.3-50888.35"
- process $proc$libresoc.v:50887$1682
+ attribute \src "libresoc.v:50879.3-50880.35"
+ process $proc$libresoc.v:50879$1682
assign { } { }
assign $0\core_reg2[4:0] \core_reg2$next
sync posedge \clk
update \core_reg2 $0\core_reg2[4:0]
end
- attribute \src "libresoc.v:50889.3-50890.41"
- process $proc$libresoc.v:50889$1683
+ attribute \src "libresoc.v:50881.3-50882.41"
+ process $proc$libresoc.v:50881$1683
assign { } { }
assign $0\core_reg2_ok[0:0] \core_reg2_ok$next
sync posedge \clk
update \core_reg2_ok $0\core_reg2_ok[0:0]
end
- attribute \src "libresoc.v:50891.3-50892.35"
- process $proc$libresoc.v:50891$1684
+ attribute \src "libresoc.v:50883.3-50884.35"
+ process $proc$libresoc.v:50883$1684
assign { } { }
assign $0\core_reg3[4:0] \core_reg3$next
sync posedge \clk
update \core_reg3 $0\core_reg3[4:0]
end
- attribute \src "libresoc.v:50893.3-50894.41"
- process $proc$libresoc.v:50893$1685
+ attribute \src "libresoc.v:50885.3-50886.41"
+ process $proc$libresoc.v:50885$1685
assign { } { }
assign $0\core_reg3_ok[0:0] \core_reg3_ok$next
sync posedge \clk
update \core_reg3_ok $0\core_reg3_ok[0:0]
end
- attribute \src "libresoc.v:50895.3-50896.35"
- process $proc$libresoc.v:50895$1686
+ attribute \src "libresoc.v:50887.3-50888.35"
+ process $proc$libresoc.v:50887$1686
assign { } { }
assign $0\core_spro[9:0] \core_spro$next
sync posedge \clk
update \core_spro $0\core_spro[9:0]
end
- attribute \src "libresoc.v:50897.3-50898.41"
- process $proc$libresoc.v:50897$1687
+ attribute \src "libresoc.v:50889.3-50890.41"
+ process $proc$libresoc.v:50889$1687
assign { } { }
assign $0\core_spro_ok[0:0] \core_spro_ok$next
sync posedge \clk
update \core_spro_ok $0\core_spro_ok[0:0]
end
- attribute \src "libresoc.v:50899.3-50900.39"
- process $proc$libresoc.v:50899$1688
+ attribute \src "libresoc.v:50891.3-50892.39"
+ process $proc$libresoc.v:50891$1688
assign { } { }
assign $0\d_xer_delay[0:0] \d_xer_delay$next
sync posedge \clk
update \d_xer_delay $0\d_xer_delay[0:0]
end
- attribute \src "libresoc.v:50901.3-50902.35"
- process $proc$libresoc.v:50901$1689
+ attribute \src "libresoc.v:50893.3-50894.35"
+ process $proc$libresoc.v:50893$1689
assign { } { }
assign $0\core_spr1[9:0] \core_spr1$next
sync posedge \clk
update \core_spr1 $0\core_spr1[9:0]
end
- attribute \src "libresoc.v:50903.3-50904.41"
- process $proc$libresoc.v:50903$1690
+ attribute \src "libresoc.v:50895.3-50896.41"
+ process $proc$libresoc.v:50895$1690
assign { } { }
assign $0\core_spr1_ok[0:0] \core_spr1_ok$next
sync posedge \clk
update \core_spr1_ok $0\core_spr1_ok[0:0]
end
- attribute \src "libresoc.v:50905.3-50906.39"
- process $proc$libresoc.v:50905$1691
+ attribute \src "libresoc.v:50897.3-50898.39"
+ process $proc$libresoc.v:50897$1691
assign { } { }
assign $0\core_xer_in[2:0] \core_xer_in$next
sync posedge \clk
update \core_xer_in $0\core_xer_in[2:0]
end
- attribute \src "libresoc.v:50907.3-50908.41"
- process $proc$libresoc.v:50907$1692
+ attribute \src "libresoc.v:50899.3-50900.41"
+ process $proc$libresoc.v:50899$1692
assign { } { }
assign $0\core_xer_out[0:0] \core_xer_out$next
sync posedge \clk
update \core_xer_out $0\core_xer_out[0:0]
end
- attribute \src "libresoc.v:50909.3-50910.37"
- process $proc$libresoc.v:50909$1693
+ attribute \src "libresoc.v:50901.3-50902.37"
+ process $proc$libresoc.v:50901$1693
assign { } { }
assign $0\core_fast1[2:0] \core_fast1$next
sync posedge \clk
update \core_fast1 $0\core_fast1[2:0]
end
- attribute \src "libresoc.v:50911.3-50912.43"
- process $proc$libresoc.v:50911$1694
+ attribute \src "libresoc.v:50903.3-50904.43"
+ process $proc$libresoc.v:50903$1694
assign { } { }
assign $0\core_fast1_ok[0:0] \core_fast1_ok$next
sync posedge \clk
update \core_fast1_ok $0\core_fast1_ok[0:0]
end
- attribute \src "libresoc.v:50913.3-50914.37"
- process $proc$libresoc.v:50913$1695
+ attribute \src "libresoc.v:50905.3-50906.37"
+ process $proc$libresoc.v:50905$1695
assign { } { }
assign $0\core_fast2[2:0] \core_fast2$next
sync posedge \clk
update \core_fast2 $0\core_fast2[2:0]
end
- attribute \src "libresoc.v:50915.3-50916.43"
- process $proc$libresoc.v:50915$1696
+ attribute \src "libresoc.v:50907.3-50908.43"
+ process $proc$libresoc.v:50907$1696
assign { } { }
assign $0\core_fast2_ok[0:0] \core_fast2_ok$next
sync posedge \clk
update \core_fast2_ok $0\core_fast2_ok[0:0]
end
- attribute \src "libresoc.v:50917.3-50918.39"
- process $proc$libresoc.v:50917$1697
+ attribute \src "libresoc.v:50909.3-50910.39"
+ process $proc$libresoc.v:50909$1697
assign { } { }
assign $0\core_fasto1[2:0] \core_fasto1$next
sync posedge \clk
update \core_fasto1 $0\core_fasto1[2:0]
end
- attribute \src "libresoc.v:50919.3-50920.45"
- process $proc$libresoc.v:50919$1698
+ attribute \src "libresoc.v:50911.3-50912.45"
+ process $proc$libresoc.v:50911$1698
assign { } { }
assign $0\core_fasto1_ok[0:0] \core_fasto1_ok$next
sync posedge \clk
update \core_fasto1_ok $0\core_fasto1_ok[0:0]
end
- attribute \src "libresoc.v:50921.3-50922.37"
- process $proc$libresoc.v:50921$1699
+ attribute \src "libresoc.v:50913.3-50914.37"
+ process $proc$libresoc.v:50913$1699
assign { } { }
assign $0\d_cr_delay[0:0] \d_cr_delay$next
sync posedge \clk
update \d_cr_delay $0\d_cr_delay[0:0]
end
- attribute \src "libresoc.v:50923.3-50924.39"
- process $proc$libresoc.v:50923$1700
+ attribute \src "libresoc.v:50915.3-50916.39"
+ process $proc$libresoc.v:50915$1700
assign { } { }
assign $0\core_fasto2[2:0] \core_fasto2$next
sync posedge \clk
update \core_fasto2 $0\core_fasto2[2:0]
end
- attribute \src "libresoc.v:50925.3-50926.45"
- process $proc$libresoc.v:50925$1701
+ attribute \src "libresoc.v:50917.3-50918.45"
+ process $proc$libresoc.v:50917$1701
assign { } { }
assign $0\core_fasto2_ok[0:0] \core_fasto2_ok$next
sync posedge \clk
update \core_fasto2_ok $0\core_fasto2_ok[0:0]
end
- attribute \src "libresoc.v:50927.3-50928.39"
- process $proc$libresoc.v:50927$1702
+ attribute \src "libresoc.v:50919.3-50920.39"
+ process $proc$libresoc.v:50919$1702
assign { } { }
assign $0\core_cr_in1[2:0] \core_cr_in1$next
sync posedge \clk
update \core_cr_in1 $0\core_cr_in1[2:0]
end
- attribute \src "libresoc.v:50929.3-50930.45"
- process $proc$libresoc.v:50929$1703
+ attribute \src "libresoc.v:50921.3-50922.45"
+ process $proc$libresoc.v:50921$1703
assign { } { }
assign $0\core_cr_in1_ok[0:0] \core_cr_in1_ok$next
sync posedge \clk
update \core_cr_in1_ok $0\core_cr_in1_ok[0:0]
end
- attribute \src "libresoc.v:50931.3-50932.39"
- process $proc$libresoc.v:50931$1704
+ attribute \src "libresoc.v:50923.3-50924.39"
+ process $proc$libresoc.v:50923$1704
assign { } { }
assign $0\core_cr_in2[2:0] \core_cr_in2$next
sync posedge \clk
update \core_cr_in2 $0\core_cr_in2[2:0]
end
- attribute \src "libresoc.v:50933.3-50934.45"
- process $proc$libresoc.v:50933$1705
+ attribute \src "libresoc.v:50925.3-50926.45"
+ process $proc$libresoc.v:50925$1705
assign { } { }
assign $0\core_cr_in2_ok[0:0] \core_cr_in2_ok$next
sync posedge \clk
update \core_cr_in2_ok $0\core_cr_in2_ok[0:0]
end
- attribute \src "libresoc.v:50935.3-50936.47"
- process $proc$libresoc.v:50935$1706
+ attribute \src "libresoc.v:50927.3-50928.47"
+ process $proc$libresoc.v:50927$1706
assign { } { }
assign $0\core_cr_in2$48[2:0]$1707 \core_cr_in2$48$next
sync posedge \clk
update \core_cr_in2$48 $0\core_cr_in2$48[2:0]$1707
end
- attribute \src "libresoc.v:50937.3-50938.53"
- process $proc$libresoc.v:50937$1708
+ attribute \src "libresoc.v:50929.3-50930.53"
+ process $proc$libresoc.v:50929$1708
assign { } { }
assign $0\core_cr_in2_ok$49[0:0]$1709 \core_cr_in2_ok$49$next
sync posedge \clk
update \core_cr_in2_ok$49 $0\core_cr_in2_ok$49[0:0]$1709
end
- attribute \src "libresoc.v:50939.3-50940.39"
- process $proc$libresoc.v:50939$1710
+ attribute \src "libresoc.v:50931.3-50932.39"
+ process $proc$libresoc.v:50931$1710
assign { } { }
assign $0\core_cr_out[2:0] \core_cr_out$next
sync posedge \clk
update \core_cr_out $0\core_cr_out[2:0]
end
- attribute \src "libresoc.v:50941.3-50942.45"
- process $proc$libresoc.v:50941$1711
+ attribute \src "libresoc.v:50933.3-50934.45"
+ process $proc$libresoc.v:50933$1711
assign { } { }
assign $0\core_cr_out_ok[0:0] \core_cr_out_ok$next
sync posedge \clk
update \core_cr_out_ok $0\core_cr_out_ok[0:0]
end
- attribute \src "libresoc.v:50943.3-50944.39"
- process $proc$libresoc.v:50943$1712
+ attribute \src "libresoc.v:50935.3-50936.39"
+ process $proc$libresoc.v:50935$1712
assign { } { }
assign $0\d_reg_delay[0:0] \d_reg_delay$next
sync posedge \clk
update \d_reg_delay $0\d_reg_delay[0:0]
end
- attribute \src "libresoc.v:50945.3-50946.43"
- process $proc$libresoc.v:50945$1713
+ attribute \src "libresoc.v:50937.3-50938.43"
+ process $proc$libresoc.v:50937$1713
assign { } { }
assign $0\core_core_msr[63:0] \core_core_msr$next
sync posedge \clk
update \core_core_msr $0\core_core_msr[63:0]
end
- attribute \src "libresoc.v:50947.3-50948.43"
- process $proc$libresoc.v:50947$1714
+ attribute \src "libresoc.v:50939.3-50940.43"
+ process $proc$libresoc.v:50939$1714
assign { } { }
assign $0\core_core_cia[63:0] \core_core_cia$next
sync posedge \clk
update \core_core_cia $0\core_core_cia[63:0]
end
- attribute \src "libresoc.v:50949.3-50950.45"
- process $proc$libresoc.v:50949$1715
+ attribute \src "libresoc.v:50941.3-50942.45"
+ process $proc$libresoc.v:50941$1715
assign { } { }
assign $0\core_core_insn[31:0] \core_core_insn$next
sync posedge \clk
update \core_core_insn $0\core_core_insn[31:0]
end
- attribute \src "libresoc.v:50951.3-50952.55"
- process $proc$libresoc.v:50951$1716
+ attribute \src "libresoc.v:50943.3-50944.55"
+ process $proc$libresoc.v:50943$1716
assign { } { }
assign $0\core_core_insn_type[6:0] \core_core_insn_type$next
sync posedge \clk
update \core_core_insn_type $0\core_core_insn_type[6:0]
end
- attribute \src "libresoc.v:50953.3-50954.51"
- process $proc$libresoc.v:50953$1717
+ attribute \src "libresoc.v:50945.3-50946.51"
+ process $proc$libresoc.v:50945$1717
assign { } { }
assign $0\core_core_fn_unit[11:0] \core_core_fn_unit$next
sync posedge \clk
update \core_core_fn_unit $0\core_core_fn_unit[11:0]
end
- attribute \src "libresoc.v:50955.3-50956.41"
- process $proc$libresoc.v:50955$1718
+ attribute \src "libresoc.v:50947.3-50948.41"
+ process $proc$libresoc.v:50947$1718
assign { } { }
assign $0\core_core_lk[0:0] \core_core_lk$next
sync posedge \clk
update \core_core_lk $0\core_core_lk[0:0]
end
- attribute \src "libresoc.v:50957.3-50958.41"
- process $proc$libresoc.v:50957$1719
+ attribute \src "libresoc.v:50949.3-50950.41"
+ process $proc$libresoc.v:50949$1719
assign { } { }
assign $0\core_core_rc[0:0] \core_core_rc$next
sync posedge \clk
update \core_core_rc $0\core_core_rc[0:0]
end
- attribute \src "libresoc.v:50959.3-50960.47"
- process $proc$libresoc.v:50959$1720
+ attribute \src "libresoc.v:50951.3-50952.47"
+ process $proc$libresoc.v:50951$1720
assign { } { }
assign $0\core_core_rc_ok[0:0] \core_core_rc_ok$next
sync posedge \clk
update \core_core_rc_ok $0\core_core_rc_ok[0:0]
end
- attribute \src "libresoc.v:50961.3-50962.41"
- process $proc$libresoc.v:50961$1721
+ attribute \src "libresoc.v:50953.3-50954.41"
+ process $proc$libresoc.v:50953$1721
assign { } { }
assign $0\core_core_oe[0:0] \core_core_oe$next
sync posedge \clk
update \core_core_oe $0\core_core_oe[0:0]
end
- attribute \src "libresoc.v:50963.3-50964.47"
- process $proc$libresoc.v:50963$1722
+ attribute \src "libresoc.v:50955.3-50956.47"
+ process $proc$libresoc.v:50955$1722
assign { } { }
assign $0\core_core_oe_ok[0:0] \core_core_oe_ok$next
sync posedge \clk
update \core_core_oe_ok $0\core_core_oe_ok[0:0]
end
- attribute \src "libresoc.v:50965.3-50966.29"
- process $proc$libresoc.v:50965$1723
+ attribute \src "libresoc.v:50957.3-50958.29"
+ process $proc$libresoc.v:50957$1723
assign { } { }
assign $0\ilatch[31:0] \ilatch$next
sync posedge \clk
update \ilatch $0\ilatch[31:0]
end
- attribute \src "libresoc.v:50967.3-50968.59"
- process $proc$libresoc.v:50967$1724
+ attribute \src "libresoc.v:50959.3-50960.59"
+ process $proc$libresoc.v:50959$1724
assign { } { }
assign $0\core_core_input_carry[1:0] \core_core_input_carry$next
sync posedge \clk
update \core_core_input_carry $0\core_core_input_carry[1:0]
end
- attribute \src "libresoc.v:50969.3-50970.53"
- process $proc$libresoc.v:50969$1725
+ attribute \src "libresoc.v:50961.3-50962.53"
+ process $proc$libresoc.v:50961$1725
assign { } { }
assign $0\core_core_traptype[7:0] \core_core_traptype$next
sync posedge \clk
update \core_core_traptype $0\core_core_traptype[7:0]
end
- attribute \src "libresoc.v:50971.3-50972.61"
- process $proc$libresoc.v:50971$1726
+ attribute \src "libresoc.v:50963.3-50964.61"
+ process $proc$libresoc.v:50963$1726
assign { } { }
assign $0\core_core_exc_$signal[0:0]$1727 \core_core_exc_$signal$next
sync posedge \clk
update \core_core_exc_$signal $0\core_core_exc_$signal[0:0]$1727
end
- attribute \src "libresoc.v:50973.3-50974.67"
- process $proc$libresoc.v:50973$1728
+ attribute \src "libresoc.v:50965.3-50966.67"
+ process $proc$libresoc.v:50965$1728
assign { } { }
assign $0\core_core_exc_$signal$50[0:0]$1729 \core_core_exc_$signal$50$next
sync posedge \clk
update \core_core_exc_$signal$50 $0\core_core_exc_$signal$50[0:0]$1729
end
- attribute \src "libresoc.v:50975.3-50976.67"
- process $proc$libresoc.v:50975$1730
+ attribute \src "libresoc.v:50967.3-50968.67"
+ process $proc$libresoc.v:50967$1730
assign { } { }
assign $0\core_core_exc_$signal$51[0:0]$1731 \core_core_exc_$signal$51$next
sync posedge \clk
update \core_core_exc_$signal$51 $0\core_core_exc_$signal$51[0:0]$1731
end
- attribute \src "libresoc.v:50977.3-50978.67"
- process $proc$libresoc.v:50977$1732
+ attribute \src "libresoc.v:50969.3-50970.67"
+ process $proc$libresoc.v:50969$1732
assign { } { }
assign $0\core_core_exc_$signal$52[0:0]$1733 \core_core_exc_$signal$52$next
sync posedge \clk
update \core_core_exc_$signal$52 $0\core_core_exc_$signal$52[0:0]$1733
end
- attribute \src "libresoc.v:50979.3-50980.67"
- process $proc$libresoc.v:50979$1734
+ attribute \src "libresoc.v:50971.3-50972.67"
+ process $proc$libresoc.v:50971$1734
assign { } { }
assign $0\core_core_exc_$signal$53[0:0]$1735 \core_core_exc_$signal$53$next
sync posedge \clk
update \core_core_exc_$signal$53 $0\core_core_exc_$signal$53[0:0]$1735
end
- attribute \src "libresoc.v:50981.3-50982.67"
- process $proc$libresoc.v:50981$1736
+ attribute \src "libresoc.v:50973.3-50974.67"
+ process $proc$libresoc.v:50973$1736
assign { } { }
assign $0\core_core_exc_$signal$54[0:0]$1737 \core_core_exc_$signal$54$next
sync posedge \clk
update \core_core_exc_$signal$54 $0\core_core_exc_$signal$54[0:0]$1737
end
- attribute \src "libresoc.v:50983.3-50984.67"
- process $proc$libresoc.v:50983$1738
+ attribute \src "libresoc.v:50975.3-50976.67"
+ process $proc$libresoc.v:50975$1738
assign { } { }
assign $0\core_core_exc_$signal$55[0:0]$1739 \core_core_exc_$signal$55$next
sync posedge \clk
update \core_core_exc_$signal$55 $0\core_core_exc_$signal$55[0:0]$1739
end
- attribute \src "libresoc.v:50985.3-50986.67"
- process $proc$libresoc.v:50985$1740
+ attribute \src "libresoc.v:50977.3-50978.67"
+ process $proc$libresoc.v:50977$1740
assign { } { }
assign $0\core_core_exc_$signal$56[0:0]$1741 \core_core_exc_$signal$56$next
sync posedge \clk
update \core_core_exc_$signal$56 $0\core_core_exc_$signal$56[0:0]$1741
end
- attribute \src "libresoc.v:50987.3-50988.31"
- process $proc$libresoc.v:50987$1742
+ attribute \src "libresoc.v:50979.3-50980.31"
+ process $proc$libresoc.v:50979$1742
assign { } { }
assign $0\core_pc[63:0] \core_pc$next
sync posedge \clk
update \core_pc $0\core_pc[63:0]
end
- attribute \src "libresoc.v:50989.3-50990.53"
- process $proc$libresoc.v:50989$1743
+ attribute \src "libresoc.v:50981.3-50982.53"
+ process $proc$libresoc.v:50981$1743
assign { } { }
assign $0\core_core_trapaddr[12:0] \core_core_trapaddr$next
sync posedge \clk
update \core_core_trapaddr $0\core_core_trapaddr[12:0]
end
- attribute \src "libresoc.v:50991.3-50992.47"
- process $proc$libresoc.v:50991$1744
+ attribute \src "libresoc.v:50983.3-50984.47"
+ process $proc$libresoc.v:50983$1744
assign { } { }
assign $0\core_core_cr_rd[7:0] \core_core_cr_rd$next
sync posedge \clk
update \core_core_cr_rd $0\core_core_cr_rd[7:0]
end
- attribute \src "libresoc.v:50993.3-50994.53"
- process $proc$libresoc.v:50993$1745
+ attribute \src "libresoc.v:50985.3-50986.53"
+ process $proc$libresoc.v:50985$1745
assign { } { }
assign $0\core_core_cr_rd_ok[0:0] \core_core_cr_rd_ok$next
sync posedge \clk
update \core_core_cr_rd_ok $0\core_core_cr_rd_ok[0:0]
end
- attribute \src "libresoc.v:50995.3-50996.47"
- process $proc$libresoc.v:50995$1746
+ attribute \src "libresoc.v:50987.3-50988.47"
+ process $proc$libresoc.v:50987$1746
assign { } { }
assign $0\core_core_cr_wr[7:0] \core_core_cr_wr$next
sync posedge \clk
update \core_core_cr_wr $0\core_core_cr_wr[7:0]
end
- attribute \src "libresoc.v:50997.3-50998.53"
- process $proc$libresoc.v:50997$1747
+ attribute \src "libresoc.v:50989.3-50990.53"
+ process $proc$libresoc.v:50989$1747
assign { } { }
assign $0\core_core_cr_wr_ok[0:0] \core_core_cr_wr_ok$next
sync posedge \clk
update \core_core_cr_wr_ok $0\core_core_cr_wr_ok[0:0]
end
- attribute \src "libresoc.v:50999.3-51000.53"
- process $proc$libresoc.v:50999$1748
+ attribute \src "libresoc.v:50991.3-50992.53"
+ process $proc$libresoc.v:50991$1748
assign { } { }
assign $0\core_core_is_32bit[0:0] \core_core_is_32bit$next
sync posedge \clk
update \core_core_is_32bit $0\core_core_is_32bit[0:0]
end
- attribute \src "libresoc.v:51001.3-51002.37"
- process $proc$libresoc.v:51001$1749
+ attribute \src "libresoc.v:50993.3-50994.37"
+ process $proc$libresoc.v:50993$1749
assign { } { }
assign $0\pc_changed[0:0] \pc_changed$next
sync posedge \clk
update \pc_changed $0\pc_changed[0:0]
end
- attribute \src "libresoc.v:51003.3-51004.39"
- process $proc$libresoc.v:51003$1750
+ attribute \src "libresoc.v:50995.3-50996.39"
+ process $proc$libresoc.v:50995$1750
assign { } { }
assign $0\pc_ok_delay[0:0] \pc_ok_delay$next
sync posedge \clk
update \pc_ok_delay $0\pc_ok_delay[0:0]
end
- attribute \src "libresoc.v:51005.3-51006.30"
- process $proc$libresoc.v:51005$1751
+ attribute \src "libresoc.v:50997.3-50998.30"
+ process $proc$libresoc.v:50997$1751
assign { } { }
assign $0\cu_st__rel_o_dly[0:0] 1'0
sync posedge \clk
update \cu_st__rel_o_dly $0\cu_st__rel_o_dly[0:0]
end
- attribute \src "libresoc.v:51007.3-51008.27"
- process $proc$libresoc.v:51007$1752
+ attribute \src "libresoc.v:50999.3-51000.27"
+ process $proc$libresoc.v:50999$1752
assign { } { }
assign $0\delay[1:0] \delay$next
sync posedge \por_clk
update \delay $0\delay[1:0]
end
- attribute \src "libresoc.v:51009.3-51010.33"
- process $proc$libresoc.v:51009$1753
+ attribute \src "libresoc.v:51001.3-51002.33"
+ process $proc$libresoc.v:51001$1753
assign { } { }
assign $0\core_msr[63:0] \core_msr$next
sync posedge \clk
update \core_msr $0\core_msr[63:0]
end
- attribute \src "libresoc.v:51011.3-51012.43"
- process $proc$libresoc.v:51011$1754
+ attribute \src "libresoc.v:51003.3-51004.43"
+ process $proc$libresoc.v:51003$1754
assign { } { }
assign $0\dec2_cur_eint[0:0] \dec2_cur_eint$next
sync posedge \clk
update \dec2_cur_eint $0\dec2_cur_eint[0:0]
end
- attribute \src "libresoc.v:51013.3-51014.47"
- process $proc$libresoc.v:51013$1755
+ attribute \src "libresoc.v:51005.3-51006.47"
+ process $proc$libresoc.v:51005$1755
assign { } { }
assign $0\jtag_dmi0__dout[63:0] \jtag_dmi0__dout$next
sync posedge \clk
update \jtag_dmi0__dout $0\jtag_dmi0__dout[63:0]
end
- attribute \src "libresoc.v:51015.3-51016.49"
- process $proc$libresoc.v:51015$1756
+ attribute \src "libresoc.v:51007.3-51008.49"
+ process $proc$libresoc.v:51007$1756
assign { } { }
assign $0\jtag_dmi0__ack_o[0:0] \jtag_dmi0__ack_o$next
sync posedge \clk
update \jtag_dmi0__ack_o $0\jtag_dmi0__ack_o[0:0]
end
- attribute \src "libresoc.v:51017.3-51018.39"
- process $proc$libresoc.v:51017$1757
+ attribute \src "libresoc.v:51009.3-51010.39"
+ process $proc$libresoc.v:51009$1757
assign { } { }
assign $0\dbg_dmi_din[63:0] \dbg_dmi_din$next
sync posedge \clk
update \dbg_dmi_din $0\dbg_dmi_din[63:0]
end
- attribute \src "libresoc.v:51019.3-51020.41"
- process $proc$libresoc.v:51019$1758
+ attribute \src "libresoc.v:51011.3-51012.41"
+ process $proc$libresoc.v:51011$1758
assign { } { }
assign $0\dbg_dmi_we_i[0:0] \dbg_dmi_we_i$next
sync posedge \clk
update \dbg_dmi_we_i $0\dbg_dmi_we_i[0:0]
end
- attribute \src "libresoc.v:51021.3-51022.43"
- process $proc$libresoc.v:51021$1759
+ attribute \src "libresoc.v:51013.3-51014.43"
+ process $proc$libresoc.v:51013$1759
assign { } { }
assign $0\dbg_dmi_req_i[0:0] \dbg_dmi_req_i$next
sync posedge \clk
update \dbg_dmi_req_i $0\dbg_dmi_req_i[0:0]
end
- attribute \src "libresoc.v:51023.3-51024.45"
- process $proc$libresoc.v:51023$1760
+ attribute \src "libresoc.v:51015.3-51016.45"
+ process $proc$libresoc.v:51015$1760
assign { } { }
assign $0\dbg_dmi_addr_i[3:0] \dbg_dmi_addr_i$next
sync posedge \clk
update \dbg_dmi_addr_i $0\dbg_dmi_addr_i[3:0]
end
- attribute \src "libresoc.v:51025.3-51026.35"
- process $proc$libresoc.v:51025$1761
+ attribute \src "libresoc.v:51017.3-51018.35"
+ process $proc$libresoc.v:51017$1761
assign { } { }
assign $0\core_eint[0:0] \core_eint$next
sync posedge \clk
update \core_eint $0\core_eint[0:0]
end
- attribute \src "libresoc.v:51501.3-51509.6"
- process $proc$libresoc.v:51501$1762
+ attribute \src "libresoc.v:51493.3-51501.6"
+ process $proc$libresoc.v:51493$1762
assign { } { }
assign { } { }
assign $0\dbg_dmi_addr_i$next[3:0]$1763 $1\dbg_dmi_addr_i$next[3:0]$1764
- attribute \src "libresoc.v:51502.5-51502.29"
+ attribute \src "libresoc.v:51494.5-51494.29"
switch \initial
- attribute \src "libresoc.v:51502.9-51502.17"
+ attribute \src "libresoc.v:51494.9-51494.17"
case 1'1
case
end
sync always
update \dbg_dmi_addr_i$next $0\dbg_dmi_addr_i$next[3:0]$1763
end
- attribute \src "libresoc.v:51510.3-51518.6"
- process $proc$libresoc.v:51510$1765
+ attribute \src "libresoc.v:51502.3-51510.6"
+ process $proc$libresoc.v:51502$1765
assign { } { }
assign { } { }
assign $0\dbg_dmi_req_i$next[0:0]$1766 $1\dbg_dmi_req_i$next[0:0]$1767
- attribute \src "libresoc.v:51511.5-51511.29"
+ attribute \src "libresoc.v:51503.5-51503.29"
switch \initial
- attribute \src "libresoc.v:51511.9-51511.17"
+ attribute \src "libresoc.v:51503.9-51503.17"
case 1'1
case
end
sync always
update \dbg_dmi_req_i$next $0\dbg_dmi_req_i$next[0:0]$1766
end
- attribute \src "libresoc.v:51519.3-51539.6"
- process $proc$libresoc.v:51519$1768
+ attribute \src "libresoc.v:51511.3-51531.6"
+ process $proc$libresoc.v:51511$1768
assign { } { }
assign { } { }
assign { } { }
assign $0\dec2_cur_msr$next[63:0]$1769 $3\dec2_cur_msr$next[63:0]$1772
- attribute \src "libresoc.v:51520.5-51520.29"
+ attribute \src "libresoc.v:51512.5-51512.29"
switch \initial
- attribute \src "libresoc.v:51520.9-51520.17"
+ attribute \src "libresoc.v:51512.9-51512.17"
case 1'1
case
end
sync always
update \dec2_cur_msr$next $0\dec2_cur_msr$next[63:0]$1769
end
- attribute \src "libresoc.v:51540.3-51558.6"
- process $proc$libresoc.v:51540$1773
+ attribute \src "libresoc.v:51532.3-51550.6"
+ process $proc$libresoc.v:51532$1773
assign { } { }
assign { } { }
assign $0\dec2_raw_opcode_in[31:0] $1\dec2_raw_opcode_in[31:0]
- attribute \src "libresoc.v:51541.5-51541.29"
+ attribute \src "libresoc.v:51533.5-51533.29"
switch \initial
- attribute \src "libresoc.v:51541.9-51541.17"
+ attribute \src "libresoc.v:51533.9-51533.17"
case 1'1
case
end
sync always
update \dec2_raw_opcode_in $0\dec2_raw_opcode_in[31:0]
end
- attribute \src "libresoc.v:51559.3-51590.6"
- process $proc$libresoc.v:51559$1774
+ attribute \src "libresoc.v:51551.3-51582.6"
+ process $proc$libresoc.v:51551$1774
assign { } { }
assign { } { }
assign { } { }
assign $0\core_eint$next[0:0]$1776 $3\core_eint$next[0:0]$1788
assign $0\core_msr$next[63:0]$1777 $3\core_msr$next[63:0]$1789
assign $0\core_pc$next[63:0]$1778 $3\core_pc$next[63:0]$1790
- attribute \src "libresoc.v:51560.5-51560.29"
+ attribute \src "libresoc.v:51552.5-51552.29"
switch \initial
- attribute \src "libresoc.v:51560.9-51560.17"
+ attribute \src "libresoc.v:51552.9-51552.17"
case 1'1
case
end
update \core_msr$next $0\core_msr$next[63:0]$1777
update \core_pc$next $0\core_pc$next[63:0]$1778
end
- attribute \src "libresoc.v:51591.3-51614.6"
- process $proc$libresoc.v:51591$1791
+ attribute \src "libresoc.v:51583.3-51606.6"
+ process $proc$libresoc.v:51583$1791
assign { } { }
assign { } { }
assign { } { }
assign $0\ilatch$next[31:0]$1792 $3\ilatch$next[31:0]$1795
- attribute \src "libresoc.v:51592.5-51592.29"
+ attribute \src "libresoc.v:51584.5-51584.29"
switch \initial
- attribute \src "libresoc.v:51592.9-51592.17"
+ attribute \src "libresoc.v:51584.9-51584.17"
case 1'1
case
end
sync always
update \ilatch$next $0\ilatch$next[31:0]$1792
end
- attribute \src "libresoc.v:51615.3-51634.6"
- process $proc$libresoc.v:51615$1796
+ attribute \src "libresoc.v:51607.3-51626.6"
+ process $proc$libresoc.v:51607$1796
assign { } { }
assign { } { }
assign $0\ivalid_i[0:0] $1\ivalid_i[0:0]
- attribute \src "libresoc.v:51616.5-51616.29"
+ attribute \src "libresoc.v:51608.5-51608.29"
switch \initial
- attribute \src "libresoc.v:51616.9-51616.17"
+ attribute \src "libresoc.v:51608.9-51608.17"
case 1'1
case
end
sync always
update \ivalid_i $0\ivalid_i[0:0]
end
- attribute \src "libresoc.v:51635.3-51645.6"
- process $proc$libresoc.v:51635$1797
+ attribute \src "libresoc.v:51627.3-51637.6"
+ process $proc$libresoc.v:51627$1797
assign { } { }
assign { } { }
assign $0\issue_i[0:0] $1\issue_i[0:0]
- attribute \src "libresoc.v:51636.5-51636.29"
+ attribute \src "libresoc.v:51628.5-51628.29"
switch \initial
- attribute \src "libresoc.v:51636.9-51636.17"
+ attribute \src "libresoc.v:51628.9-51628.17"
case 1'1
case
end
sync always
update \issue_i $0\issue_i[0:0]
end
- attribute \src "libresoc.v:51646.3-51655.6"
- process $proc$libresoc.v:51646$1798
+ attribute \src "libresoc.v:51638.3-51647.6"
+ process $proc$libresoc.v:51638$1798
assign { } { }
assign { } { }
assign $0\dmi__addr[4:0] $1\dmi__addr[4:0]
- attribute \src "libresoc.v:51647.5-51647.29"
+ attribute \src "libresoc.v:51639.5-51639.29"
switch \initial
- attribute \src "libresoc.v:51647.9-51647.17"
+ attribute \src "libresoc.v:51639.9-51639.17"
case 1'1
case
end
sync always
update \dmi__addr $0\dmi__addr[4:0]
end
- attribute \src "libresoc.v:51656.3-51665.6"
- process $proc$libresoc.v:51656$1799
+ attribute \src "libresoc.v:51648.3-51657.6"
+ process $proc$libresoc.v:51648$1799
assign { } { }
assign { } { }
assign $0\dmi__ren[0:0] $1\dmi__ren[0:0]
- attribute \src "libresoc.v:51657.5-51657.29"
+ attribute \src "libresoc.v:51649.5-51649.29"
switch \initial
- attribute \src "libresoc.v:51657.9-51657.17"
+ attribute \src "libresoc.v:51649.9-51649.17"
case 1'1
case
end
sync always
update \dmi__ren $0\dmi__ren[0:0]
end
- attribute \src "libresoc.v:51666.3-51674.6"
- process $proc$libresoc.v:51666$1800
+ attribute \src "libresoc.v:51658.3-51666.6"
+ process $proc$libresoc.v:51658$1800
assign { } { }
assign { } { }
assign $0\d_reg_delay$next[0:0]$1801 $1\d_reg_delay$next[0:0]$1802
- attribute \src "libresoc.v:51667.5-51667.29"
+ attribute \src "libresoc.v:51659.5-51659.29"
switch \initial
- attribute \src "libresoc.v:51667.9-51667.17"
+ attribute \src "libresoc.v:51659.9-51659.17"
case 1'1
case
end
sync always
update \d_reg_delay$next $0\d_reg_delay$next[0:0]$1801
end
- attribute \src "libresoc.v:51675.3-51684.6"
- process $proc$libresoc.v:51675$1803
+ attribute \src "libresoc.v:51667.3-51676.6"
+ process $proc$libresoc.v:51667$1803
assign { } { }
assign { } { }
assign $0\dbg_d_gpr_data[63:0] $1\dbg_d_gpr_data[63:0]
- attribute \src "libresoc.v:51676.5-51676.29"
+ attribute \src "libresoc.v:51668.5-51668.29"
switch \initial
- attribute \src "libresoc.v:51676.9-51676.17"
+ attribute \src "libresoc.v:51668.9-51668.17"
case 1'1
case
end
sync always
update \dbg_d_gpr_data $0\dbg_d_gpr_data[63:0]
end
- attribute \src "libresoc.v:51685.3-51694.6"
- process $proc$libresoc.v:51685$1804
+ attribute \src "libresoc.v:51677.3-51686.6"
+ process $proc$libresoc.v:51677$1804
assign { } { }
assign { } { }
assign $0\dbg_d_gpr_ack[0:0] $1\dbg_d_gpr_ack[0:0]
- attribute \src "libresoc.v:51686.5-51686.29"
+ attribute \src "libresoc.v:51678.5-51678.29"
switch \initial
- attribute \src "libresoc.v:51686.9-51686.17"
+ attribute \src "libresoc.v:51678.9-51678.17"
case 1'1
case
end
sync always
update \dbg_d_gpr_ack $0\dbg_d_gpr_ack[0:0]
end
- attribute \src "libresoc.v:51695.3-51704.6"
- process $proc$libresoc.v:51695$1805
+ attribute \src "libresoc.v:51687.3-51696.6"
+ process $proc$libresoc.v:51687$1805
assign { } { }
assign { } { }
assign $0\full_rd2__ren[7:0] $1\full_rd2__ren[7:0]
- attribute \src "libresoc.v:51696.5-51696.29"
+ attribute \src "libresoc.v:51688.5-51688.29"
switch \initial
- attribute \src "libresoc.v:51696.9-51696.17"
+ attribute \src "libresoc.v:51688.9-51688.17"
case 1'1
case
end
sync always
update \full_rd2__ren $0\full_rd2__ren[7:0]
end
- attribute \src "libresoc.v:51705.3-51713.6"
- process $proc$libresoc.v:51705$1806
+ attribute \src "libresoc.v:51697.3-51705.6"
+ process $proc$libresoc.v:51697$1806
assign { } { }
assign { } { }
assign $0\d_cr_delay$next[0:0]$1807 $1\d_cr_delay$next[0:0]$1808
- attribute \src "libresoc.v:51706.5-51706.29"
+ attribute \src "libresoc.v:51698.5-51698.29"
switch \initial
- attribute \src "libresoc.v:51706.9-51706.17"
+ attribute \src "libresoc.v:51698.9-51698.17"
case 1'1
case
end
sync always
update \d_cr_delay$next $0\d_cr_delay$next[0:0]$1807
end
- attribute \src "libresoc.v:51714.3-51723.6"
- process $proc$libresoc.v:51714$1809
+ attribute \src "libresoc.v:51706.3-51715.6"
+ process $proc$libresoc.v:51706$1809
assign { } { }
assign { } { }
assign $0\dbg_d_cr_data[63:0] $1\dbg_d_cr_data[63:0]
- attribute \src "libresoc.v:51715.5-51715.29"
+ attribute \src "libresoc.v:51707.5-51707.29"
switch \initial
- attribute \src "libresoc.v:51715.9-51715.17"
+ attribute \src "libresoc.v:51707.9-51707.17"
case 1'1
case
end
sync always
update \dbg_d_cr_data $0\dbg_d_cr_data[63:0]
end
- attribute \src "libresoc.v:51724.3-51733.6"
- process $proc$libresoc.v:51724$1810
+ attribute \src "libresoc.v:51716.3-51725.6"
+ process $proc$libresoc.v:51716$1810
assign { } { }
assign { } { }
assign $0\dbg_d_cr_ack[0:0] $1\dbg_d_cr_ack[0:0]
- attribute \src "libresoc.v:51725.5-51725.29"
+ attribute \src "libresoc.v:51717.5-51717.29"
switch \initial
- attribute \src "libresoc.v:51725.9-51725.17"
+ attribute \src "libresoc.v:51717.9-51717.17"
case 1'1
case
end
sync always
update \dbg_d_cr_ack $0\dbg_d_cr_ack[0:0]
end
- attribute \src "libresoc.v:51734.3-51743.6"
- process $proc$libresoc.v:51734$1811
+ attribute \src "libresoc.v:51726.3-51735.6"
+ process $proc$libresoc.v:51726$1811
assign { } { }
assign { } { }
assign $0\full_rd__ren[2:0] $1\full_rd__ren[2:0]
- attribute \src "libresoc.v:51735.5-51735.29"
+ attribute \src "libresoc.v:51727.5-51727.29"
switch \initial
- attribute \src "libresoc.v:51735.9-51735.17"
+ attribute \src "libresoc.v:51727.9-51727.17"
case 1'1
case
end
sync always
update \full_rd__ren $0\full_rd__ren[2:0]
end
- attribute \src "libresoc.v:51744.3-51752.6"
- process $proc$libresoc.v:51744$1812
+ attribute \src "libresoc.v:51736.3-51744.6"
+ process $proc$libresoc.v:51736$1812
assign { } { }
assign { } { }
assign $0\d_xer_delay$next[0:0]$1813 $1\d_xer_delay$next[0:0]$1814
- attribute \src "libresoc.v:51745.5-51745.29"
+ attribute \src "libresoc.v:51737.5-51737.29"
switch \initial
- attribute \src "libresoc.v:51745.9-51745.17"
+ attribute \src "libresoc.v:51737.9-51737.17"
case 1'1
case
end
sync always
update \d_xer_delay$next $0\d_xer_delay$next[0:0]$1813
end
- attribute \src "libresoc.v:51753.3-51762.6"
- process $proc$libresoc.v:51753$1815
+ attribute \src "libresoc.v:51745.3-51754.6"
+ process $proc$libresoc.v:51745$1815
assign { } { }
assign { } { }
assign $0\dbg_d_xer_data[63:0] $1\dbg_d_xer_data[63:0]
- attribute \src "libresoc.v:51754.5-51754.29"
+ attribute \src "libresoc.v:51746.5-51746.29"
switch \initial
- attribute \src "libresoc.v:51754.9-51754.17"
+ attribute \src "libresoc.v:51746.9-51746.17"
case 1'1
case
end
sync always
update \dbg_d_xer_data $0\dbg_d_xer_data[63:0]
end
- attribute \src "libresoc.v:51763.3-51772.6"
- process $proc$libresoc.v:51763$1816
+ attribute \src "libresoc.v:51755.3-51764.6"
+ process $proc$libresoc.v:51755$1816
assign { } { }
assign { } { }
assign $0\dbg_d_xer_ack[0:0] $1\dbg_d_xer_ack[0:0]
- attribute \src "libresoc.v:51764.5-51764.29"
+ attribute \src "libresoc.v:51756.5-51756.29"
switch \initial
- attribute \src "libresoc.v:51764.9-51764.17"
+ attribute \src "libresoc.v:51756.9-51756.17"
case 1'1
case
end
sync always
update \dbg_d_xer_ack $0\dbg_d_xer_ack[0:0]
end
- attribute \src "libresoc.v:51773.3-51787.6"
- process $proc$libresoc.v:51773$1817
+ attribute \src "libresoc.v:51765.3-51779.6"
+ process $proc$libresoc.v:51765$1817
assign { } { }
assign { } { }
assign $0\issue__addr[2:0] $1\issue__addr[2:0]
- attribute \src "libresoc.v:51774.5-51774.29"
+ attribute \src "libresoc.v:51766.5-51766.29"
switch \initial
- attribute \src "libresoc.v:51774.9-51774.17"
+ attribute \src "libresoc.v:51766.9-51766.17"
case 1'1
case
end
sync always
update \issue__addr $0\issue__addr[2:0]
end
- attribute \src "libresoc.v:51788.3-51802.6"
- process $proc$libresoc.v:51788$1818
+ attribute \src "libresoc.v:51780.3-51794.6"
+ process $proc$libresoc.v:51780$1818
assign { } { }
assign { } { }
assign $0\issue__ren[0:0] $1\issue__ren[0:0]
- attribute \src "libresoc.v:51789.5-51789.29"
+ attribute \src "libresoc.v:51781.5-51781.29"
switch \initial
- attribute \src "libresoc.v:51789.9-51789.17"
+ attribute \src "libresoc.v:51781.9-51781.17"
case 1'1
case
end
sync always
update \issue__ren $0\issue__ren[0:0]
end
- attribute \src "libresoc.v:51803.3-51830.6"
- process $proc$libresoc.v:51803$1819
+ attribute \src "libresoc.v:51795.3-51822.6"
+ process $proc$libresoc.v:51795$1819
assign { } { }
assign { } { }
assign { } { }
assign $0\fsm_state$131$next[1:0]$1820 $2\fsm_state$131$next[1:0]$1822
- attribute \src "libresoc.v:51804.5-51804.29"
+ attribute \src "libresoc.v:51796.5-51796.29"
switch \initial
- attribute \src "libresoc.v:51804.9-51804.17"
+ attribute \src "libresoc.v:51796.9-51796.17"
case 1'1
case
end
sync always
update \fsm_state$131$next $0\fsm_state$131$next[1:0]$1820
end
- attribute \src "libresoc.v:51831.3-51841.6"
- process $proc$libresoc.v:51831$1823
+ attribute \src "libresoc.v:51823.3-51833.6"
+ process $proc$libresoc.v:51823$1823
assign { } { }
assign { } { }
assign $0\new_dec[63:0] $1\new_dec[63:0]
- attribute \src "libresoc.v:51832.5-51832.29"
+ attribute \src "libresoc.v:51824.5-51824.29"
switch \initial
- attribute \src "libresoc.v:51832.9-51832.17"
+ attribute \src "libresoc.v:51824.9-51824.17"
case 1'1
case
end
sync always
update \new_dec $0\new_dec[63:0]
end
- attribute \src "libresoc.v:51842.3-51856.6"
- process $proc$libresoc.v:51842$1824
+ attribute \src "libresoc.v:51834.3-51848.6"
+ process $proc$libresoc.v:51834$1824
assign { } { }
assign { } { }
assign $0\issue__addr$135[2:0]$1825 $1\issue__addr$135[2:0]$1826
- attribute \src "libresoc.v:51843.5-51843.29"
+ attribute \src "libresoc.v:51835.5-51835.29"
switch \initial
- attribute \src "libresoc.v:51843.9-51843.17"
+ attribute \src "libresoc.v:51835.9-51835.17"
case 1'1
case
end
sync always
update \issue__addr$135 $0\issue__addr$135[2:0]$1825
end
- attribute \src "libresoc.v:51857.3-51871.6"
- process $proc$libresoc.v:51857$1827
+ attribute \src "libresoc.v:51849.3-51863.6"
+ process $proc$libresoc.v:51849$1827
assign { } { }
assign { } { }
assign $0\issue__wen[0:0] $1\issue__wen[0:0]
- attribute \src "libresoc.v:51858.5-51858.29"
+ attribute \src "libresoc.v:51850.5-51850.29"
switch \initial
- attribute \src "libresoc.v:51858.9-51858.17"
+ attribute \src "libresoc.v:51850.9-51850.17"
case 1'1
case
end
sync always
update \issue__wen $0\issue__wen[0:0]
end
- attribute \src "libresoc.v:51872.3-51886.6"
- process $proc$libresoc.v:51872$1828
+ attribute \src "libresoc.v:51864.3-51878.6"
+ process $proc$libresoc.v:51864$1828
assign { } { }
assign { } { }
assign $0\issue__data_i[63:0] $1\issue__data_i[63:0]
- attribute \src "libresoc.v:51873.5-51873.29"
+ attribute \src "libresoc.v:51865.5-51865.29"
switch \initial
- attribute \src "libresoc.v:51873.9-51873.17"
+ attribute \src "libresoc.v:51865.9-51865.17"
case 1'1
case
end
sync always
update \issue__data_i $0\issue__data_i[63:0]
end
- attribute \src "libresoc.v:51887.3-51902.6"
- process $proc$libresoc.v:51887$1829
+ attribute \src "libresoc.v:51879.3-51894.6"
+ process $proc$libresoc.v:51879$1829
assign { } { }
assign { } { }
assign { } { }
assign $0\dec2_cur_dec$next[63:0]$1830 $2\dec2_cur_dec$next[63:0]$1832
- attribute \src "libresoc.v:51888.5-51888.29"
+ attribute \src "libresoc.v:51880.5-51880.29"
switch \initial
- attribute \src "libresoc.v:51888.9-51888.17"
+ attribute \src "libresoc.v:51880.9-51880.17"
case 1'1
case
end
sync always
update \dec2_cur_dec$next $0\dec2_cur_dec$next[63:0]$1830
end
- attribute \src "libresoc.v:51903.3-51913.6"
- process $proc$libresoc.v:51903$1833
+ attribute \src "libresoc.v:51895.3-51905.6"
+ process $proc$libresoc.v:51895$1833
assign { } { }
assign { } { }
assign $0\new_tb[63:0] $1\new_tb[63:0]
- attribute \src "libresoc.v:51904.5-51904.29"
+ attribute \src "libresoc.v:51896.5-51896.29"
switch \initial
- attribute \src "libresoc.v:51904.9-51904.17"
+ attribute \src "libresoc.v:51896.9-51896.17"
case 1'1
case
end
sync always
update \new_tb $0\new_tb[63:0]
end
- attribute \src "libresoc.v:51914.3-51922.6"
- process $proc$libresoc.v:51914$1834
+ attribute \src "libresoc.v:51906.3-51914.6"
+ process $proc$libresoc.v:51906$1834
assign { } { }
assign { } { }
assign $0\dbg_dmi_we_i$next[0:0]$1835 $1\dbg_dmi_we_i$next[0:0]$1836
- attribute \src "libresoc.v:51915.5-51915.29"
+ attribute \src "libresoc.v:51907.5-51907.29"
switch \initial
- attribute \src "libresoc.v:51915.9-51915.17"
+ attribute \src "libresoc.v:51907.9-51907.17"
case 1'1
case
end
sync always
update \dbg_dmi_we_i$next $0\dbg_dmi_we_i$next[0:0]$1835
end
- attribute \src "libresoc.v:51923.3-51931.6"
- process $proc$libresoc.v:51923$1837
+ attribute \src "libresoc.v:51915.3-51923.6"
+ process $proc$libresoc.v:51915$1837
assign { } { }
assign { } { }
assign $0\pc_ok_delay$next[0:0]$1838 $1\pc_ok_delay$next[0:0]$1839
- attribute \src "libresoc.v:51924.5-51924.29"
+ attribute \src "libresoc.v:51916.5-51916.29"
switch \initial
- attribute \src "libresoc.v:51924.9-51924.17"
+ attribute \src "libresoc.v:51916.9-51916.17"
case 1'1
case
end
sync always
update \pc_ok_delay$next $0\pc_ok_delay$next[0:0]$1838
end
- attribute \src "libresoc.v:51932.3-51947.6"
- process $proc$libresoc.v:51932$1840
+ attribute \src "libresoc.v:51924.3-51939.6"
+ process $proc$libresoc.v:51924$1840
assign { } { }
assign { } { }
assign { } { }
assign $0\pc[63:0] $2\pc[63:0]
- attribute \src "libresoc.v:51933.5-51933.29"
+ attribute \src "libresoc.v:51925.5-51925.29"
switch \initial
- attribute \src "libresoc.v:51933.9-51933.17"
+ attribute \src "libresoc.v:51925.9-51925.17"
case 1'1
case
end
sync always
update \pc $0\pc[63:0]
end
- attribute \src "libresoc.v:51948.3-51960.6"
- process $proc$libresoc.v:51948$1841
+ attribute \src "libresoc.v:51940.3-51952.6"
+ process $proc$libresoc.v:51940$1841
assign { } { }
assign { } { }
assign $0\cia__ren[3:0] $1\cia__ren[3:0]
- attribute \src "libresoc.v:51949.5-51949.29"
+ attribute \src "libresoc.v:51941.5-51941.29"
switch \initial
- attribute \src "libresoc.v:51949.9-51949.17"
+ attribute \src "libresoc.v:51941.9-51941.17"
case 1'1
case
end
sync always
update \cia__ren $0\cia__ren[3:0]
end
- attribute \src "libresoc.v:51961.3-51981.6"
- process $proc$libresoc.v:51961$1842
+ attribute \src "libresoc.v:51953.3-51973.6"
+ process $proc$libresoc.v:51953$1842
assign { } { }
assign { } { }
assign $0\wen[3:0] $1\wen[3:0]
- attribute \src "libresoc.v:51962.5-51962.29"
+ attribute \src "libresoc.v:51954.5-51954.29"
switch \initial
- attribute \src "libresoc.v:51962.9-51962.17"
+ attribute \src "libresoc.v:51954.9-51954.17"
case 1'1
case
end
sync always
update \wen $0\wen[3:0]
end
- attribute \src "libresoc.v:51982.3-52002.6"
- process $proc$libresoc.v:51982$1843
+ attribute \src "libresoc.v:51974.3-51994.6"
+ process $proc$libresoc.v:51974$1843
assign { } { }
assign { } { }
assign $0\data_i[63:0] $1\data_i[63:0]
- attribute \src "libresoc.v:51983.5-51983.29"
+ attribute \src "libresoc.v:51975.5-51975.29"
switch \initial
- attribute \src "libresoc.v:51983.9-51983.17"
+ attribute \src "libresoc.v:51975.9-51975.17"
case 1'1
case
end
sync always
update \data_i $0\data_i[63:0]
end
- attribute \src "libresoc.v:52003.3-52018.6"
- process $proc$libresoc.v:52003$1844
+ attribute \src "libresoc.v:51995.3-52010.6"
+ process $proc$libresoc.v:51995$1844
assign { } { }
assign { } { }
assign $0\msr__ren[3:0] $1\msr__ren[3:0]
- attribute \src "libresoc.v:52004.5-52004.29"
+ attribute \src "libresoc.v:51996.5-51996.29"
switch \initial
- attribute \src "libresoc.v:52004.9-52004.17"
+ attribute \src "libresoc.v:51996.9-51996.17"
case 1'1
case
end
sync always
update \msr__ren $0\msr__ren[3:0]
end
- attribute \src "libresoc.v:52019.3-52027.6"
- process $proc$libresoc.v:52019$1845
+ attribute \src "libresoc.v:52011.3-52019.6"
+ process $proc$libresoc.v:52011$1845
assign { } { }
assign { } { }
assign $0\dbg_dmi_din$next[63:0]$1846 $1\dbg_dmi_din$next[63:0]$1847
- attribute \src "libresoc.v:52020.5-52020.29"
+ attribute \src "libresoc.v:52012.5-52012.29"
switch \initial
- attribute \src "libresoc.v:52020.9-52020.17"
+ attribute \src "libresoc.v:52012.9-52012.17"
case 1'1
case
end
sync always
update \dbg_dmi_din$next $0\dbg_dmi_din$next[63:0]$1846
end
- attribute \src "libresoc.v:52028.3-52052.6"
- process $proc$libresoc.v:52028$1848
+ attribute \src "libresoc.v:52020.3-52044.6"
+ process $proc$libresoc.v:52020$1848
assign { } { }
assign { } { }
assign { } { }
assign $0\pc_changed$next[0:0]$1849 $3\pc_changed$next[0:0]$1852
- attribute \src "libresoc.v:52029.5-52029.29"
+ attribute \src "libresoc.v:52021.5-52021.29"
switch \initial
- attribute \src "libresoc.v:52029.9-52029.17"
+ attribute \src "libresoc.v:52021.9-52021.17"
case 1'1
case
end
sync always
update \pc_changed$next $0\pc_changed$next[0:0]$1849
end
- attribute \src "libresoc.v:52053.3-52175.6"
- process $proc$libresoc.v:52053$1853
+ attribute \src "libresoc.v:52045.3-52167.6"
+ process $proc$libresoc.v:52045$1853
assign { } { }
assign { } { }
assign { } { }
assign $0\core_rego_ok$next[0:0]$1906 $4\core_rego_ok$next[0:0]$2114
assign $0\core_spr1_ok$next[0:0]$1908 $4\core_spr1_ok$next[0:0]$2115
assign $0\core_spro_ok$next[0:0]$1910 $4\core_spro_ok$next[0:0]$2116
- attribute \src "libresoc.v:52054.5-52054.29"
+ attribute \src "libresoc.v:52046.5-52046.29"
switch \initial
- attribute \src "libresoc.v:52054.9-52054.17"
+ attribute \src "libresoc.v:52046.9-52046.17"
case 1'1
case
end
update \core_xer_in$next $0\core_xer_in$next[2:0]$1911
update \core_xer_out$next $0\core_xer_out$next[0:0]$1912
end
- attribute \src "libresoc.v:52176.3-52184.6"
- process $proc$libresoc.v:52176$2117
+ attribute \src "libresoc.v:52168.3-52176.6"
+ process $proc$libresoc.v:52168$2117
assign { } { }
assign { } { }
assign $0\jtag_dmi0__ack_o$next[0:0]$2118 $1\jtag_dmi0__ack_o$next[0:0]$2119
- attribute \src "libresoc.v:52177.5-52177.29"
+ attribute \src "libresoc.v:52169.5-52169.29"
switch \initial
- attribute \src "libresoc.v:52177.9-52177.17"
+ attribute \src "libresoc.v:52169.9-52169.17"
case 1'1
case
end
sync always
update \jtag_dmi0__ack_o$next $0\jtag_dmi0__ack_o$next[0:0]$2118
end
- attribute \src "libresoc.v:52185.3-52193.6"
- process $proc$libresoc.v:52185$2120
+ attribute \src "libresoc.v:52177.3-52185.6"
+ process $proc$libresoc.v:52177$2120
assign { } { }
assign { } { }
assign $0\jtag_dmi0__dout$next[63:0]$2121 $1\jtag_dmi0__dout$next[63:0]$2122
- attribute \src "libresoc.v:52186.5-52186.29"
+ attribute \src "libresoc.v:52178.5-52178.29"
switch \initial
- attribute \src "libresoc.v:52186.9-52186.17"
+ attribute \src "libresoc.v:52178.9-52178.17"
case 1'1
case
end
sync always
update \jtag_dmi0__dout$next $0\jtag_dmi0__dout$next[63:0]$2121
end
- attribute \src "libresoc.v:52194.3-52202.6"
- process $proc$libresoc.v:52194$2123
+ attribute \src "libresoc.v:52186.3-52194.6"
+ process $proc$libresoc.v:52186$2123
assign { } { }
assign { } { }
assign $0\dec2_cur_eint$next[0:0]$2124 $1\dec2_cur_eint$next[0:0]$2125
- attribute \src "libresoc.v:52195.5-52195.29"
+ attribute \src "libresoc.v:52187.5-52187.29"
switch \initial
- attribute \src "libresoc.v:52195.9-52195.17"
+ attribute \src "libresoc.v:52187.9-52187.17"
case 1'1
case
end
sync always
update \dec2_cur_eint$next $0\dec2_cur_eint$next[0:0]$2124
end
- attribute \src "libresoc.v:52203.3-52212.6"
- process $proc$libresoc.v:52203$2126
+ attribute \src "libresoc.v:52195.3-52204.6"
+ process $proc$libresoc.v:52195$2126
assign { } { }
assign { } { }
assign $0\delay$next[1:0]$2127 $1\delay$next[1:0]$2128
- attribute \src "libresoc.v:52204.5-52204.29"
+ attribute \src "libresoc.v:52196.5-52196.29"
switch \initial
- attribute \src "libresoc.v:52204.9-52204.17"
+ attribute \src "libresoc.v:52196.9-52196.17"
case 1'1
case
end
sync always
update \delay$next $0\delay$next[1:0]$2127
end
- attribute \src "libresoc.v:52213.3-52249.6"
- process $proc$libresoc.v:52213$2129
+ attribute \src "libresoc.v:52205.3-52241.6"
+ process $proc$libresoc.v:52205$2129
assign { } { }
assign { } { }
assign { } { }
assign $0\raw_insn_i$next[31:0]$2130 $4\raw_insn_i$next[31:0]$2134
- attribute \src "libresoc.v:52214.5-52214.29"
+ attribute \src "libresoc.v:52206.5-52206.29"
switch \initial
- attribute \src "libresoc.v:52214.9-52214.17"
+ attribute \src "libresoc.v:52206.9-52206.17"
case 1'1
case
end
sync always
update \raw_insn_i$next $0\raw_insn_i$next[31:0]$2130
end
- attribute \src "libresoc.v:52250.3-52286.6"
- process $proc$libresoc.v:52250$2135
+ attribute \src "libresoc.v:52242.3-52278.6"
+ process $proc$libresoc.v:52242$2135
assign { } { }
assign { } { }
assign { } { }
assign $0\bigendian_i$next[0:0]$2136 $4\bigendian_i$next[0:0]$2140
- attribute \src "libresoc.v:52251.5-52251.29"
+ attribute \src "libresoc.v:52243.5-52243.29"
switch \initial
- attribute \src "libresoc.v:52251.9-52251.17"
+ attribute \src "libresoc.v:52243.9-52243.17"
case 1'1
case
end
sync always
update \bigendian_i$next $0\bigendian_i$next[0:0]$2136
end
- attribute \src "libresoc.v:52287.3-52302.6"
- process $proc$libresoc.v:52287$2141
+ attribute \src "libresoc.v:52279.3-52294.6"
+ process $proc$libresoc.v:52279$2141
assign { } { }
assign { } { }
assign $0\imem_a_pc_i[47:0] $1\imem_a_pc_i[47:0]
- attribute \src "libresoc.v:52288.5-52288.29"
+ attribute \src "libresoc.v:52280.5-52280.29"
switch \initial
- attribute \src "libresoc.v:52288.9-52288.17"
+ attribute \src "libresoc.v:52280.9-52280.17"
case 1'1
case
end
sync always
update \imem_a_pc_i $0\imem_a_pc_i[47:0]
end
- attribute \src "libresoc.v:52303.3-52327.6"
- process $proc$libresoc.v:52303$2142
+ attribute \src "libresoc.v:52295.3-52319.6"
+ process $proc$libresoc.v:52295$2142
assign { } { }
assign { } { }
assign $0\imem_a_valid_i[0:0] $1\imem_a_valid_i[0:0]
- attribute \src "libresoc.v:52304.5-52304.29"
+ attribute \src "libresoc.v:52296.5-52296.29"
switch \initial
- attribute \src "libresoc.v:52304.9-52304.17"
+ attribute \src "libresoc.v:52296.9-52296.17"
case 1'1
case
end
sync always
update \imem_a_valid_i $0\imem_a_valid_i[0:0]
end
- attribute \src "libresoc.v:52328.3-52352.6"
- process $proc$libresoc.v:52328$2143
+ attribute \src "libresoc.v:52320.3-52344.6"
+ process $proc$libresoc.v:52320$2143
assign { } { }
assign { } { }
assign $0\imem_f_valid_i[0:0] $1\imem_f_valid_i[0:0]
- attribute \src "libresoc.v:52329.5-52329.29"
+ attribute \src "libresoc.v:52321.5-52321.29"
switch \initial
- attribute \src "libresoc.v:52329.9-52329.17"
+ attribute \src "libresoc.v:52321.9-52321.17"
case 1'1
case
end
sync always
update \imem_f_valid_i $0\imem_f_valid_i[0:0]
end
- attribute \src "libresoc.v:52353.3-52373.6"
- process $proc$libresoc.v:52353$2144
+ attribute \src "libresoc.v:52345.3-52365.6"
+ process $proc$libresoc.v:52345$2144
assign { } { }
assign { } { }
assign { } { }
assign $0\dec2_cur_pc$next[63:0]$2145 $3\dec2_cur_pc$next[63:0]$2148
- attribute \src "libresoc.v:52354.5-52354.29"
+ attribute \src "libresoc.v:52346.5-52346.29"
switch \initial
- attribute \src "libresoc.v:52354.9-52354.17"
+ attribute \src "libresoc.v:52346.9-52346.17"
case 1'1
case
end
sync always
update \dec2_cur_pc$next $0\dec2_cur_pc$next[63:0]$2145
end
- attribute \src "libresoc.v:52374.3-52403.6"
- process $proc$libresoc.v:52374$2149
+ attribute \src "libresoc.v:52366.3-52395.6"
+ process $proc$libresoc.v:52366$2149
assign { } { }
assign { } { }
assign { } { }
assign $0\msr_read$next[0:0]$2150 $4\msr_read$next[0:0]$2154
- attribute \src "libresoc.v:52375.5-52375.29"
+ attribute \src "libresoc.v:52367.5-52367.29"
switch \initial
- attribute \src "libresoc.v:52375.9-52375.17"
+ attribute \src "libresoc.v:52367.9-52367.17"
case 1'1
case
end
sync always
update \msr_read$next $0\msr_read$next[0:0]$2150
end
- attribute \src "libresoc.v:52404.3-52449.6"
- process $proc$libresoc.v:52404$2155
+ attribute \src "libresoc.v:52396.3-52441.6"
+ process $proc$libresoc.v:52396$2155
assign { } { }
assign { } { }
assign { } { }
assign $0\fsm_state$next[1:0]$2156 $5\fsm_state$next[1:0]$2161
- attribute \src "libresoc.v:52405.5-52405.29"
+ attribute \src "libresoc.v:52397.5-52397.29"
switch \initial
- attribute \src "libresoc.v:52405.9-52405.17"
+ attribute \src "libresoc.v:52397.9-52397.17"
case 1'1
case
end
sync always
update \fsm_state$next $0\fsm_state$next[1:0]$2156
end
- attribute \src "libresoc.v:52450.3-52468.6"
- process $proc$libresoc.v:52450$2162
+ attribute \src "libresoc.v:52442.3-52460.6"
+ process $proc$libresoc.v:52442$2162
assign { } { }
assign { } { }
assign $0\core_stopped_i[0:0] $1\core_stopped_i[0:0]
- attribute \src "libresoc.v:52451.5-52451.29"
+ attribute \src "libresoc.v:52443.5-52443.29"
switch \initial
- attribute \src "libresoc.v:52451.9-52451.17"
+ attribute \src "libresoc.v:52443.9-52443.17"
case 1'1
case
end
sync always
update \core_stopped_i $0\core_stopped_i[0:0]
end
- attribute \src "libresoc.v:52469.3-52487.6"
- process $proc$libresoc.v:52469$2163
+ attribute \src "libresoc.v:52461.3-52479.6"
+ process $proc$libresoc.v:52461$2163
assign { } { }
assign { } { }
assign $0\dbg_core_stopped_i[0:0] $1\dbg_core_stopped_i[0:0]
- attribute \src "libresoc.v:52470.5-52470.29"
+ attribute \src "libresoc.v:52462.5-52462.29"
switch \initial
- attribute \src "libresoc.v:52470.9-52470.17"
+ attribute \src "libresoc.v:52462.9-52462.17"
case 1'1
case
end
sync always
update \dbg_core_stopped_i $0\dbg_core_stopped_i[0:0]
end
- connect \$99 $and$libresoc.v:50798$1606_Y
- connect \$101 $not$libresoc.v:50799$1607_Y
- connect \$103 $not$libresoc.v:50800$1608_Y
- connect \$105 $not$libresoc.v:50801$1609_Y
- connect \$107 $and$libresoc.v:50802$1610_Y
- connect \$10 $ne$libresoc.v:50803$1611_Y
- connect \$109 $not$libresoc.v:50804$1612_Y
- connect \$111 $not$libresoc.v:50805$1613_Y
- connect \$113 $and$libresoc.v:50806$1614_Y
- connect \$115 $not$libresoc.v:50807$1615_Y
- connect \$118 $mul$libresoc.v:50808$1616_Y
- connect \$117 $shr$libresoc.v:50809$1617_Y [31:0]
- connect \$122 $mul$libresoc.v:50810$1618_Y
- connect \$121 $shr$libresoc.v:50811$1619_Y [31:0]
- connect \$125 $ne$libresoc.v:50812$1620_Y
- connect \$127 $pos$libresoc.v:50813$1622_Y
- connect \$129 $pos$libresoc.v:50814$1624_Y
- connect \$133 $sub$libresoc.v:50815$1625_Y
- connect \$137 $add$libresoc.v:50816$1626_Y
- connect \$13 $sub$libresoc.v:50817$1627_Y
- connect \$15 $or$libresoc.v:50818$1628_Y
- connect \$17 $or$libresoc.v:50819$1629_Y
- connect \$19 $ne$libresoc.v:50820$1630_Y
- connect \$21 $not$libresoc.v:50821$1631_Y
- connect \$23 $and$libresoc.v:50822$1632_Y
- connect \$26 $add$libresoc.v:50823$1633_Y
- connect \$28 $not$libresoc.v:50824$1634_Y
- connect \$30 $not$libresoc.v:50825$1635_Y
- connect \$32 $not$libresoc.v:50826$1636_Y
- connect \$34 $not$libresoc.v:50827$1637_Y
- connect \$36 $not$libresoc.v:50828$1638_Y
- connect \$38 $not$libresoc.v:50829$1639_Y
- connect \$40 $not$libresoc.v:50830$1640_Y
- connect \$42 $and$libresoc.v:50831$1641_Y
- connect \$45 $and$libresoc.v:50832$1642_Y
- connect \$44 $reduce_or$libresoc.v:50833$1643_Y
- connect \$57 $not$libresoc.v:50834$1644_Y
- connect \$59 $not$libresoc.v:50835$1645_Y
- connect \$61 $not$libresoc.v:50836$1646_Y
- connect \$63 $not$libresoc.v:50837$1647_Y
- connect \$65 $not$libresoc.v:50838$1648_Y
- connect \$67 $and$libresoc.v:50839$1649_Y
- connect \$69 $not$libresoc.v:50840$1650_Y
- connect \$71 $not$libresoc.v:50841$1651_Y
- connect \$73 $and$libresoc.v:50842$1652_Y
- connect \$75 $not$libresoc.v:50843$1653_Y
- connect \$77 $not$libresoc.v:50844$1654_Y
- connect \$79 $and$libresoc.v:50845$1655_Y
- connect \$81 $not$libresoc.v:50846$1656_Y
- connect \$83 $not$libresoc.v:50847$1657_Y
- connect \$85 $and$libresoc.v:50848$1658_Y
- connect \$87 $not$libresoc.v:50849$1659_Y
- connect \$89 $not$libresoc.v:50850$1660_Y
- connect \$91 $and$libresoc.v:50851$1661_Y
- connect \$93 $not$libresoc.v:50852$1662_Y
- connect \$95 $not$libresoc.v:50853$1663_Y
- connect \$97 $not$libresoc.v:50854$1664_Y
+ connect \$99 $and$libresoc.v:50790$1606_Y
+ connect \$101 $not$libresoc.v:50791$1607_Y
+ connect \$103 $not$libresoc.v:50792$1608_Y
+ connect \$105 $not$libresoc.v:50793$1609_Y
+ connect \$107 $and$libresoc.v:50794$1610_Y
+ connect \$10 $ne$libresoc.v:50795$1611_Y
+ connect \$109 $not$libresoc.v:50796$1612_Y
+ connect \$111 $not$libresoc.v:50797$1613_Y
+ connect \$113 $and$libresoc.v:50798$1614_Y
+ connect \$115 $not$libresoc.v:50799$1615_Y
+ connect \$118 $mul$libresoc.v:50800$1616_Y
+ connect \$117 $shr$libresoc.v:50801$1617_Y [31:0]
+ connect \$122 $mul$libresoc.v:50802$1618_Y
+ connect \$121 $shr$libresoc.v:50803$1619_Y [31:0]
+ connect \$125 $ne$libresoc.v:50804$1620_Y
+ connect \$127 $pos$libresoc.v:50805$1622_Y
+ connect \$129 $pos$libresoc.v:50806$1624_Y
+ connect \$133 $sub$libresoc.v:50807$1625_Y
+ connect \$137 $add$libresoc.v:50808$1626_Y
+ connect \$13 $sub$libresoc.v:50809$1627_Y
+ connect \$15 $or$libresoc.v:50810$1628_Y
+ connect \$17 $or$libresoc.v:50811$1629_Y
+ connect \$19 $ne$libresoc.v:50812$1630_Y
+ connect \$21 $not$libresoc.v:50813$1631_Y
+ connect \$23 $and$libresoc.v:50814$1632_Y
+ connect \$26 $add$libresoc.v:50815$1633_Y
+ connect \$28 $not$libresoc.v:50816$1634_Y
+ connect \$30 $not$libresoc.v:50817$1635_Y
+ connect \$32 $not$libresoc.v:50818$1636_Y
+ connect \$34 $not$libresoc.v:50819$1637_Y
+ connect \$36 $not$libresoc.v:50820$1638_Y
+ connect \$38 $not$libresoc.v:50821$1639_Y
+ connect \$40 $not$libresoc.v:50822$1640_Y
+ connect \$42 $and$libresoc.v:50823$1641_Y
+ connect \$45 $and$libresoc.v:50824$1642_Y
+ connect \$44 $reduce_or$libresoc.v:50825$1643_Y
+ connect \$57 $not$libresoc.v:50826$1644_Y
+ connect \$59 $not$libresoc.v:50827$1645_Y
+ connect \$61 $not$libresoc.v:50828$1646_Y
+ connect \$63 $not$libresoc.v:50829$1647_Y
+ connect \$65 $not$libresoc.v:50830$1648_Y
+ connect \$67 $and$libresoc.v:50831$1649_Y
+ connect \$69 $not$libresoc.v:50832$1650_Y
+ connect \$71 $not$libresoc.v:50833$1651_Y
+ connect \$73 $and$libresoc.v:50834$1652_Y
+ connect \$75 $not$libresoc.v:50835$1653_Y
+ connect \$77 $not$libresoc.v:50836$1654_Y
+ connect \$79 $and$libresoc.v:50837$1655_Y
+ connect \$81 $not$libresoc.v:50838$1656_Y
+ connect \$83 $not$libresoc.v:50839$1657_Y
+ connect \$85 $and$libresoc.v:50840$1658_Y
+ connect \$87 $not$libresoc.v:50841$1659_Y
+ connect \$89 $not$libresoc.v:50842$1660_Y
+ connect \$91 $and$libresoc.v:50843$1661_Y
+ connect \$93 $not$libresoc.v:50844$1662_Y
+ connect \$95 $not$libresoc.v:50845$1663_Y
+ connect \$97 $not$libresoc.v:50846$1664_Y
connect \$12 \$13
connect \$25 \$26
connect \$132 \$133
connect \por_clk \clk
connect { \xics_icp_ics_i_pri \xics_icp_ics_i_src } { \xics_ics_icp_o_pri \xics_ics_icp_o_src }
end
-attribute \src "libresoc.v:52522.1-52836.10"
+attribute \src "libresoc.v:52514.1-52828.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.xics_icp"
attribute \generator "nMigen"
module \xics_icp
- attribute \src "libresoc.v:52700.3-52728.6"
+ attribute \src "libresoc.v:52692.3-52720.6"
wire width 32 $0\be_out[31:0]
- attribute \src "libresoc.v:52751.3-52759.6"
+ attribute \src "libresoc.v:52743.3-52751.6"
wire $0\core_irq_o$next[0:0]$2297
- attribute \src "libresoc.v:52642.3-52643.37"
+ attribute \src "libresoc.v:52634.3-52635.37"
wire $0\core_irq_o[0:0]
- attribute \src "libresoc.v:52770.3-52832.6"
+ attribute \src "libresoc.v:52762.3-52824.6"
wire width 8 $0\cppr$10[7:0]$2301
- attribute \src "libresoc.v:52656.3-52671.6"
+ attribute \src "libresoc.v:52648.3-52663.6"
wire width 8 $0\cppr$next[7:0]$2280
- attribute \src "libresoc.v:52646.3-52647.25"
+ attribute \src "libresoc.v:52638.3-52639.25"
wire width 8 $0\cppr[7:0]
- attribute \src "libresoc.v:52760.3-52769.6"
+ attribute \src "libresoc.v:52752.3-52761.6"
wire width 32 $0\icp_wb__dat_r[31:0]
- attribute \src "libresoc.v:52523.7-52523.20"
+ attribute \src "libresoc.v:52515.7-52515.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:52770.3-52832.6"
+ attribute \src "libresoc.v:52762.3-52824.6"
wire $0\irq$12[0:0]$2302
- attribute \src "libresoc.v:52656.3-52671.6"
+ attribute \src "libresoc.v:52648.3-52663.6"
wire $0\irq$next[0:0]$2281
- attribute \src "libresoc.v:52650.3-52651.23"
+ attribute \src "libresoc.v:52642.3-52643.23"
wire $0\irq[0:0]
- attribute \src "libresoc.v:52770.3-52832.6"
+ attribute \src "libresoc.v:52762.3-52824.6"
wire width 8 $0\mfrr$11[7:0]$2303
- attribute \src "libresoc.v:52656.3-52671.6"
+ attribute \src "libresoc.v:52648.3-52663.6"
wire width 8 $0\mfrr$next[7:0]$2282
- attribute \src "libresoc.v:52648.3-52649.25"
+ attribute \src "libresoc.v:52640.3-52641.25"
wire width 8 $0\mfrr[7:0]
- attribute \src "libresoc.v:52739.3-52750.6"
+ attribute \src "libresoc.v:52731.3-52742.6"
wire width 8 $0\min_pri[7:0]
- attribute \src "libresoc.v:52729.3-52738.6"
+ attribute \src "libresoc.v:52721.3-52730.6"
wire width 8 $0\pending_priority[7:0]
- attribute \src "libresoc.v:52770.3-52832.6"
+ attribute \src "libresoc.v:52762.3-52824.6"
wire $0\wb_ack$14[0:0]$2304
- attribute \src "libresoc.v:52656.3-52671.6"
+ attribute \src "libresoc.v:52648.3-52663.6"
wire $0\wb_ack$next[0:0]$2283
- attribute \src "libresoc.v:52654.3-52655.29"
+ attribute \src "libresoc.v:52646.3-52647.29"
wire $0\wb_ack[0:0]
- attribute \src "libresoc.v:52770.3-52832.6"
+ attribute \src "libresoc.v:52762.3-52824.6"
wire width 32 $0\wb_rd_data$13[31:0]$2305
- attribute \src "libresoc.v:52656.3-52671.6"
+ attribute \src "libresoc.v:52648.3-52663.6"
wire width 32 $0\wb_rd_data$next[31:0]$2284
- attribute \src "libresoc.v:52652.3-52653.37"
+ attribute \src "libresoc.v:52644.3-52645.37"
wire width 32 $0\wb_rd_data[31:0]
- attribute \src "libresoc.v:52672.3-52699.6"
+ attribute \src "libresoc.v:52664.3-52691.6"
wire $0\xirr_accept_rd[0:0]
- attribute \src "libresoc.v:52770.3-52832.6"
+ attribute \src "libresoc.v:52762.3-52824.6"
wire width 24 $0\xisr$9[23:0]$2306
- attribute \src "libresoc.v:52656.3-52671.6"
+ attribute \src "libresoc.v:52648.3-52663.6"
wire width 24 $0\xisr$next[23:0]$2285
- attribute \src "libresoc.v:52644.3-52645.25"
+ attribute \src "libresoc.v:52636.3-52637.25"
wire width 24 $0\xisr[23:0]
- attribute \src "libresoc.v:52700.3-52728.6"
+ attribute \src "libresoc.v:52692.3-52720.6"
wire width 32 $1\be_out[31:0]
- attribute \src "libresoc.v:52751.3-52759.6"
+ attribute \src "libresoc.v:52743.3-52751.6"
wire $1\core_irq_o$next[0:0]$2298
- attribute \src "libresoc.v:52552.7-52552.24"
+ attribute \src "libresoc.v:52544.7-52544.24"
wire $1\core_irq_o[0:0]
- attribute \src "libresoc.v:52770.3-52832.6"
+ attribute \src "libresoc.v:52762.3-52824.6"
wire width 8 $1\cppr$10[7:0]$2307
- attribute \src "libresoc.v:52656.3-52671.6"
+ attribute \src "libresoc.v:52648.3-52663.6"
wire width 8 $1\cppr$next[7:0]$2286
- attribute \src "libresoc.v:52556.13-52556.25"
+ attribute \src "libresoc.v:52548.13-52548.25"
wire width 8 $1\cppr[7:0]
- attribute \src "libresoc.v:52760.3-52769.6"
+ attribute \src "libresoc.v:52752.3-52761.6"
wire width 32 $1\icp_wb__dat_r[31:0]
- attribute \src "libresoc.v:52770.3-52832.6"
+ attribute \src "libresoc.v:52762.3-52824.6"
wire $1\irq$12[0:0]$2317
- attribute \src "libresoc.v:52656.3-52671.6"
+ attribute \src "libresoc.v:52648.3-52663.6"
wire $1\irq$next[0:0]$2287
- attribute \src "libresoc.v:52585.7-52585.17"
+ attribute \src "libresoc.v:52577.7-52577.17"
wire $1\irq[0:0]
- attribute \src "libresoc.v:52770.3-52832.6"
+ attribute \src "libresoc.v:52762.3-52824.6"
wire width 8 $1\mfrr$11[7:0]$2308
- attribute \src "libresoc.v:52656.3-52671.6"
+ attribute \src "libresoc.v:52648.3-52663.6"
wire width 8 $1\mfrr$next[7:0]$2288
- attribute \src "libresoc.v:52593.13-52593.25"
+ attribute \src "libresoc.v:52585.13-52585.25"
wire width 8 $1\mfrr[7:0]
- attribute \src "libresoc.v:52739.3-52750.6"
+ attribute \src "libresoc.v:52731.3-52742.6"
wire width 8 $1\min_pri[7:0]
- attribute \src "libresoc.v:52729.3-52738.6"
+ attribute \src "libresoc.v:52721.3-52730.6"
wire width 8 $1\pending_priority[7:0]
- attribute \src "libresoc.v:52770.3-52832.6"
+ attribute \src "libresoc.v:52762.3-52824.6"
wire $1\wb_ack$14[0:0]$2309
- attribute \src "libresoc.v:52656.3-52671.6"
+ attribute \src "libresoc.v:52648.3-52663.6"
wire $1\wb_ack$next[0:0]$2289
- attribute \src "libresoc.v:52607.7-52607.20"
+ attribute \src "libresoc.v:52599.7-52599.20"
wire $1\wb_ack[0:0]
- attribute \src "libresoc.v:52656.3-52671.6"
+ attribute \src "libresoc.v:52648.3-52663.6"
wire width 32 $1\wb_rd_data$next[31:0]$2290
- attribute \src "libresoc.v:52615.14-52615.32"
+ attribute \src "libresoc.v:52607.14-52607.32"
wire width 32 $1\wb_rd_data[31:0]
- attribute \src "libresoc.v:52672.3-52699.6"
+ attribute \src "libresoc.v:52664.3-52691.6"
wire $1\xirr_accept_rd[0:0]
- attribute \src "libresoc.v:52770.3-52832.6"
+ attribute \src "libresoc.v:52762.3-52824.6"
wire width 24 $1\xisr$9[23:0]$2314
- attribute \src "libresoc.v:52656.3-52671.6"
+ attribute \src "libresoc.v:52648.3-52663.6"
wire width 24 $1\xisr$next[23:0]$2291
- attribute \src "libresoc.v:52625.14-52625.31"
+ attribute \src "libresoc.v:52617.14-52617.31"
wire width 24 $1\xisr[23:0]
- attribute \src "libresoc.v:52700.3-52728.6"
+ attribute \src "libresoc.v:52692.3-52720.6"
wire width 32 $2\be_out[31:0]
- attribute \src "libresoc.v:52770.3-52832.6"
+ attribute \src "libresoc.v:52762.3-52824.6"
wire width 8 $2\cppr$10[7:0]$2310
- attribute \src "libresoc.v:52770.3-52832.6"
+ attribute \src "libresoc.v:52762.3-52824.6"
wire width 8 $2\mfrr$11[7:0]$2311
- attribute \src "libresoc.v:52672.3-52699.6"
+ attribute \src "libresoc.v:52664.3-52691.6"
wire $2\xirr_accept_rd[0:0]
- attribute \src "libresoc.v:52770.3-52832.6"
+ attribute \src "libresoc.v:52762.3-52824.6"
wire width 24 $2\xisr$9[23:0]$2315
- attribute \src "libresoc.v:52700.3-52728.6"
+ attribute \src "libresoc.v:52692.3-52720.6"
wire width 32 $3\be_out[31:0]
- attribute \src "libresoc.v:52770.3-52832.6"
+ attribute \src "libresoc.v:52762.3-52824.6"
wire width 8 $3\cppr$10[7:0]$2312
- attribute \src "libresoc.v:52770.3-52832.6"
+ attribute \src "libresoc.v:52762.3-52824.6"
wire width 8 $3\mfrr$11[7:0]$2313
- attribute \src "libresoc.v:52672.3-52699.6"
+ attribute \src "libresoc.v:52664.3-52691.6"
wire $3\xirr_accept_rd[0:0]
- attribute \src "libresoc.v:52770.3-52832.6"
+ attribute \src "libresoc.v:52762.3-52824.6"
wire width 8 $4\cppr$10[7:0]$2316
- attribute \src "libresoc.v:52672.3-52699.6"
+ attribute \src "libresoc.v:52664.3-52691.6"
wire $4\xirr_accept_rd[0:0]
- attribute \src "libresoc.v:52632.18-52632.116"
- wire $and$libresoc.v:52632$2262_Y
- attribute \src "libresoc.v:52636.18-52636.116"
- wire $and$libresoc.v:52636$2266_Y
- attribute \src "libresoc.v:52638.18-52638.116"
- wire $and$libresoc.v:52638$2268_Y
- attribute \src "libresoc.v:52641.17-52641.109"
- wire $and$libresoc.v:52641$2271_Y
- attribute \src "libresoc.v:52637.18-52637.110"
- wire $eq$libresoc.v:52637$2267_Y
- attribute \src "libresoc.v:52634.18-52634.114"
- wire $lt$libresoc.v:52634$2264_Y
- attribute \src "libresoc.v:52635.18-52635.109"
- wire $lt$libresoc.v:52635$2265_Y
- attribute \src "libresoc.v:52640.18-52640.114"
- wire $lt$libresoc.v:52640$2270_Y
- attribute \src "libresoc.v:52633.18-52633.109"
- wire $ne$libresoc.v:52633$2263_Y
- attribute \src "libresoc.v:52639.18-52639.109"
- wire $ne$libresoc.v:52639$2269_Y
+ attribute \src "libresoc.v:52624.18-52624.116"
+ wire $and$libresoc.v:52624$2262_Y
+ attribute \src "libresoc.v:52628.18-52628.116"
+ wire $and$libresoc.v:52628$2266_Y
+ attribute \src "libresoc.v:52630.18-52630.116"
+ wire $and$libresoc.v:52630$2268_Y
+ attribute \src "libresoc.v:52633.17-52633.109"
+ wire $and$libresoc.v:52633$2271_Y
+ attribute \src "libresoc.v:52629.18-52629.110"
+ wire $eq$libresoc.v:52629$2267_Y
+ attribute \src "libresoc.v:52626.18-52626.114"
+ wire $lt$libresoc.v:52626$2264_Y
+ attribute \src "libresoc.v:52627.18-52627.109"
+ wire $lt$libresoc.v:52627$2265_Y
+ attribute \src "libresoc.v:52632.18-52632.114"
+ wire $lt$libresoc.v:52632$2270_Y
+ attribute \src "libresoc.v:52625.18-52625.109"
+ wire $ne$libresoc.v:52625$2263_Y
+ attribute \src "libresoc.v:52631.18-52631.109"
+ wire $ne$libresoc.v:52631$2269_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117"
wire \$15
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:173"
wire width 8 input 3 \ics_i_pri
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:45"
wire width 4 input 2 \ics_i_src
- attribute \src "libresoc.v:52523.7-52523.15"
+ attribute \src "libresoc.v:52515.7-52515.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:64"
wire \irq
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:61"
wire width 24 \xisr$next
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117"
- cell $and $and$libresoc.v:52632$2262
+ cell $and $and$libresoc.v:52624$2262
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \icp_wb__cyc
connect \B \icp_wb__stb
- connect \Y $and$libresoc.v:52632$2262_Y
+ connect \Y $and$libresoc.v:52624$2262_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117"
- cell $and $and$libresoc.v:52636$2266
+ cell $and $and$libresoc.v:52628$2266
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \icp_wb__cyc
connect \B \icp_wb__stb
- connect \Y $and$libresoc.v:52636$2266_Y
+ connect \Y $and$libresoc.v:52628$2266_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117"
- cell $and $and$libresoc.v:52638$2268
+ cell $and $and$libresoc.v:52630$2268
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \icp_wb__cyc
connect \B \icp_wb__stb
- connect \Y $and$libresoc.v:52638$2268_Y
+ connect \Y $and$libresoc.v:52630$2268_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:96"
- cell $and $and$libresoc.v:52641$2271
+ cell $and $and$libresoc.v:52633$2271
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \wb_ack
connect \B \icp_wb__cyc
- connect \Y $and$libresoc.v:52641$2271_Y
+ connect \Y $and$libresoc.v:52633$2271_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:162"
- cell $eq $eq$libresoc.v:52637$2267
+ cell $eq $eq$libresoc.v:52629$2267
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \icp_wb__sel
connect \B 4'1111
- connect \Y $eq$libresoc.v:52637$2267_Y
+ connect \Y $eq$libresoc.v:52629$2267_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:178"
- cell $lt $lt$libresoc.v:52634$2264
+ cell $lt $lt$libresoc.v:52626$2264
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \mfrr
connect \B \pending_priority
- connect \Y $lt$libresoc.v:52634$2264_Y
+ connect \Y $lt$libresoc.v:52626$2264_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:195"
- cell $lt $lt$libresoc.v:52635$2265
+ cell $lt $lt$libresoc.v:52627$2265
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \min_pri
connect \B \cppr$10
- connect \Y $lt$libresoc.v:52635$2265_Y
+ connect \Y $lt$libresoc.v:52627$2265_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:178"
- cell $lt $lt$libresoc.v:52640$2270
+ cell $lt $lt$libresoc.v:52632$2270
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \mfrr
connect \B \pending_priority
- connect \Y $lt$libresoc.v:52640$2270_Y
+ connect \Y $lt$libresoc.v:52632$2270_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:173"
- cell $ne $ne$libresoc.v:52633$2263
+ cell $ne $ne$libresoc.v:52625$2263
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ics_i_pri
connect \B 8'11111111
- connect \Y $ne$libresoc.v:52633$2263_Y
+ connect \Y $ne$libresoc.v:52625$2263_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:173"
- cell $ne $ne$libresoc.v:52639$2269
+ cell $ne $ne$libresoc.v:52631$2269
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ics_i_pri
connect \B 8'11111111
- connect \Y $ne$libresoc.v:52639$2269_Y
+ connect \Y $ne$libresoc.v:52631$2269_Y
end
- attribute \src "libresoc.v:52523.7-52523.20"
- process $proc$libresoc.v:52523$2318
+ attribute \src "libresoc.v:52515.7-52515.20"
+ process $proc$libresoc.v:52515$2318
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:52552.7-52552.24"
- process $proc$libresoc.v:52552$2319
+ attribute \src "libresoc.v:52544.7-52544.24"
+ process $proc$libresoc.v:52544$2319
assign { } { }
assign $1\core_irq_o[0:0] 1'0
sync always
sync init
update \core_irq_o $1\core_irq_o[0:0]
end
- attribute \src "libresoc.v:52556.13-52556.25"
- process $proc$libresoc.v:52556$2320
+ attribute \src "libresoc.v:52548.13-52548.25"
+ process $proc$libresoc.v:52548$2320
assign { } { }
assign $1\cppr[7:0] 8'00000000
sync always
sync init
update \cppr $1\cppr[7:0]
end
- attribute \src "libresoc.v:52585.7-52585.17"
- process $proc$libresoc.v:52585$2321
+ attribute \src "libresoc.v:52577.7-52577.17"
+ process $proc$libresoc.v:52577$2321
assign { } { }
assign $1\irq[0:0] 1'0
sync always
sync init
update \irq $1\irq[0:0]
end
- attribute \src "libresoc.v:52593.13-52593.25"
- process $proc$libresoc.v:52593$2322
+ attribute \src "libresoc.v:52585.13-52585.25"
+ process $proc$libresoc.v:52585$2322
assign { } { }
assign $1\mfrr[7:0] 8'11111111
sync always
sync init
update \mfrr $1\mfrr[7:0]
end
- attribute \src "libresoc.v:52607.7-52607.20"
- process $proc$libresoc.v:52607$2323
+ attribute \src "libresoc.v:52599.7-52599.20"
+ process $proc$libresoc.v:52599$2323
assign { } { }
assign $1\wb_ack[0:0] 1'0
sync always
sync init
update \wb_ack $1\wb_ack[0:0]
end
- attribute \src "libresoc.v:52615.14-52615.32"
- process $proc$libresoc.v:52615$2324
+ attribute \src "libresoc.v:52607.14-52607.32"
+ process $proc$libresoc.v:52607$2324
assign { } { }
assign $1\wb_rd_data[31:0] 0
sync always
sync init
update \wb_rd_data $1\wb_rd_data[31:0]
end
- attribute \src "libresoc.v:52625.14-52625.31"
- process $proc$libresoc.v:52625$2325
+ attribute \src "libresoc.v:52617.14-52617.31"
+ process $proc$libresoc.v:52617$2325
assign { } { }
assign $1\xisr[23:0] 24'000000000000000000000000
sync always
sync init
update \xisr $1\xisr[23:0]
end
- attribute \src "libresoc.v:52642.3-52643.37"
- process $proc$libresoc.v:52642$2272
+ attribute \src "libresoc.v:52634.3-52635.37"
+ process $proc$libresoc.v:52634$2272
assign { } { }
assign $0\core_irq_o[0:0] \core_irq_o$next
sync posedge \clk
update \core_irq_o $0\core_irq_o[0:0]
end
- attribute \src "libresoc.v:52644.3-52645.25"
- process $proc$libresoc.v:52644$2273
+ attribute \src "libresoc.v:52636.3-52637.25"
+ process $proc$libresoc.v:52636$2273
assign { } { }
assign $0\xisr[23:0] \xisr$next
sync posedge \clk
update \xisr $0\xisr[23:0]
end
- attribute \src "libresoc.v:52646.3-52647.25"
- process $proc$libresoc.v:52646$2274
+ attribute \src "libresoc.v:52638.3-52639.25"
+ process $proc$libresoc.v:52638$2274
assign { } { }
assign $0\cppr[7:0] \cppr$next
sync posedge \clk
update \cppr $0\cppr[7:0]
end
- attribute \src "libresoc.v:52648.3-52649.25"
- process $proc$libresoc.v:52648$2275
+ attribute \src "libresoc.v:52640.3-52641.25"
+ process $proc$libresoc.v:52640$2275
assign { } { }
assign $0\mfrr[7:0] \mfrr$next
sync posedge \clk
update \mfrr $0\mfrr[7:0]
end
- attribute \src "libresoc.v:52650.3-52651.23"
- process $proc$libresoc.v:52650$2276
+ attribute \src "libresoc.v:52642.3-52643.23"
+ process $proc$libresoc.v:52642$2276
assign { } { }
assign $0\irq[0:0] \irq$next
sync posedge \clk
update \irq $0\irq[0:0]
end
- attribute \src "libresoc.v:52652.3-52653.37"
- process $proc$libresoc.v:52652$2277
+ attribute \src "libresoc.v:52644.3-52645.37"
+ process $proc$libresoc.v:52644$2277
assign { } { }
assign $0\wb_rd_data[31:0] \wb_rd_data$next
sync posedge \clk
update \wb_rd_data $0\wb_rd_data[31:0]
end
- attribute \src "libresoc.v:52654.3-52655.29"
- process $proc$libresoc.v:52654$2278
+ attribute \src "libresoc.v:52646.3-52647.29"
+ process $proc$libresoc.v:52646$2278
assign { } { }
assign $0\wb_ack[0:0] \wb_ack$next
sync posedge \clk
update \wb_ack $0\wb_ack[0:0]
end
- attribute \src "libresoc.v:52656.3-52671.6"
- process $proc$libresoc.v:52656$2279
+ attribute \src "libresoc.v:52648.3-52663.6"
+ process $proc$libresoc.v:52648$2279
assign { } { }
assign { } { }
assign { } { }
assign $0\wb_ack$next[0:0]$2283 $1\wb_ack$next[0:0]$2289
assign $0\wb_rd_data$next[31:0]$2284 $1\wb_rd_data$next[31:0]$2290
assign $0\xisr$next[23:0]$2285 $1\xisr$next[23:0]$2291
- attribute \src "libresoc.v:52657.5-52657.29"
+ attribute \src "libresoc.v:52649.5-52649.29"
switch \initial
- attribute \src "libresoc.v:52657.9-52657.17"
+ attribute \src "libresoc.v:52649.9-52649.17"
case 1'1
case
end
update \wb_rd_data$next $0\wb_rd_data$next[31:0]$2284
update \xisr$next $0\xisr$next[23:0]$2285
end
- attribute \src "libresoc.v:52672.3-52699.6"
- process $proc$libresoc.v:52672$2292
+ attribute \src "libresoc.v:52664.3-52691.6"
+ process $proc$libresoc.v:52664$2292
assign { } { }
assign { } { }
assign $0\xirr_accept_rd[0:0] $1\xirr_accept_rd[0:0]
- attribute \src "libresoc.v:52673.5-52673.29"
+ attribute \src "libresoc.v:52665.5-52665.29"
switch \initial
- attribute \src "libresoc.v:52673.9-52673.17"
+ attribute \src "libresoc.v:52665.9-52665.17"
case 1'1
case
end
sync always
update \xirr_accept_rd $0\xirr_accept_rd[0:0]
end
- attribute \src "libresoc.v:52700.3-52728.6"
- process $proc$libresoc.v:52700$2293
+ attribute \src "libresoc.v:52692.3-52720.6"
+ process $proc$libresoc.v:52692$2293
assign { } { }
assign { } { }
assign $0\be_out[31:0] $1\be_out[31:0]
- attribute \src "libresoc.v:52701.5-52701.29"
+ attribute \src "libresoc.v:52693.5-52693.29"
switch \initial
- attribute \src "libresoc.v:52701.9-52701.17"
+ attribute \src "libresoc.v:52693.9-52693.17"
case 1'1
case
end
sync always
update \be_out $0\be_out[31:0]
end
- attribute \src "libresoc.v:52729.3-52738.6"
- process $proc$libresoc.v:52729$2294
+ attribute \src "libresoc.v:52721.3-52730.6"
+ process $proc$libresoc.v:52721$2294
assign { } { }
assign { } { }
assign $0\pending_priority[7:0] $1\pending_priority[7:0]
- attribute \src "libresoc.v:52730.5-52730.29"
+ attribute \src "libresoc.v:52722.5-52722.29"
switch \initial
- attribute \src "libresoc.v:52730.9-52730.17"
+ attribute \src "libresoc.v:52722.9-52722.17"
case 1'1
case
end
sync always
update \pending_priority $0\pending_priority[7:0]
end
- attribute \src "libresoc.v:52739.3-52750.6"
- process $proc$libresoc.v:52739$2295
+ attribute \src "libresoc.v:52731.3-52742.6"
+ process $proc$libresoc.v:52731$2295
assign { } { }
assign $0\min_pri[7:0] $1\min_pri[7:0]
- attribute \src "libresoc.v:52740.5-52740.29"
+ attribute \src "libresoc.v:52732.5-52732.29"
switch \initial
- attribute \src "libresoc.v:52740.9-52740.17"
+ attribute \src "libresoc.v:52732.9-52732.17"
case 1'1
case
end
sync always
update \min_pri $0\min_pri[7:0]
end
- attribute \src "libresoc.v:52751.3-52759.6"
- process $proc$libresoc.v:52751$2296
+ attribute \src "libresoc.v:52743.3-52751.6"
+ process $proc$libresoc.v:52743$2296
assign { } { }
assign { } { }
assign $0\core_irq_o$next[0:0]$2297 $1\core_irq_o$next[0:0]$2298
- attribute \src "libresoc.v:52752.5-52752.29"
+ attribute \src "libresoc.v:52744.5-52744.29"
switch \initial
- attribute \src "libresoc.v:52752.9-52752.17"
+ attribute \src "libresoc.v:52744.9-52744.17"
case 1'1
case
end
sync always
update \core_irq_o$next $0\core_irq_o$next[0:0]$2297
end
- attribute \src "libresoc.v:52760.3-52769.6"
- process $proc$libresoc.v:52760$2299
+ attribute \src "libresoc.v:52752.3-52761.6"
+ process $proc$libresoc.v:52752$2299
assign { } { }
assign { } { }
assign $0\icp_wb__dat_r[31:0] $1\icp_wb__dat_r[31:0]
- attribute \src "libresoc.v:52761.5-52761.29"
+ attribute \src "libresoc.v:52753.5-52753.29"
switch \initial
- attribute \src "libresoc.v:52761.9-52761.17"
+ attribute \src "libresoc.v:52753.9-52753.17"
case 1'1
case
end
sync always
update \icp_wb__dat_r $0\icp_wb__dat_r[31:0]
end
- attribute \src "libresoc.v:52770.3-52832.6"
- process $proc$libresoc.v:52770$2300
+ attribute \src "libresoc.v:52762.3-52824.6"
+ process $proc$libresoc.v:52762$2300
assign { } { }
assign { } { }
assign { } { }
assign $0\cppr$10[7:0]$2301 $4\cppr$10[7:0]$2316
assign $0\wb_rd_data$13[31:0]$2305 { \be_out [7:0] \be_out [15:8] \be_out [23:16] \be_out [31:24] }
assign $0\irq$12[0:0]$2302 $1\irq$12[0:0]$2317
- attribute \src "libresoc.v:52771.5-52771.29"
+ attribute \src "libresoc.v:52763.5-52763.29"
switch \initial
- attribute \src "libresoc.v:52771.9-52771.17"
+ attribute \src "libresoc.v:52763.9-52763.17"
case 1'1
case
end
update \wb_rd_data$13 $0\wb_rd_data$13[31:0]$2305
update \xisr$9 $0\xisr$9[23:0]$2306
end
- connect \$15 $and$libresoc.v:52632$2262_Y
- connect \$17 $ne$libresoc.v:52633$2263_Y
- connect \$19 $lt$libresoc.v:52634$2264_Y
- connect \$21 $lt$libresoc.v:52635$2265_Y
- connect \$23 $and$libresoc.v:52636$2266_Y
- connect \$25 $eq$libresoc.v:52637$2267_Y
- connect \$27 $and$libresoc.v:52638$2268_Y
- connect \$29 $ne$libresoc.v:52639$2269_Y
- connect \$31 $lt$libresoc.v:52640$2270_Y
- connect \$7 $and$libresoc.v:52641$2271_Y
+ connect \$15 $and$libresoc.v:52624$2262_Y
+ connect \$17 $ne$libresoc.v:52625$2263_Y
+ connect \$19 $lt$libresoc.v:52626$2264_Y
+ connect \$21 $lt$libresoc.v:52627$2265_Y
+ connect \$23 $and$libresoc.v:52628$2266_Y
+ connect \$25 $eq$libresoc.v:52629$2267_Y
+ connect \$27 $and$libresoc.v:52630$2268_Y
+ connect \$29 $ne$libresoc.v:52631$2269_Y
+ connect \$31 $lt$libresoc.v:52632$2270_Y
+ connect \$7 $and$libresoc.v:52633$2271_Y
connect { \wb_ack$6 \wb_rd_data$5 \irq$4 \mfrr$3 \cppr$2 \xisr$1 } { \wb_ack$14 \wb_rd_data$13 \irq$12 \mfrr$11 \cppr$10 \xisr$9 }
connect \be_in { \icp_wb__dat_w [7:0] \icp_wb__dat_w [15:8] \icp_wb__dat_w [23:16] \icp_wb__dat_w [31:24] }
connect \icp_wb__ack \$7
end
-attribute \src "libresoc.v:52840.1-53889.10"
+attribute \src "libresoc.v:52832.1-53881.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.xics_ics"
attribute \generator "nMigen"
module \xics_ics
- attribute \src "libresoc.v:53770.3-53819.6"
+ attribute \src "libresoc.v:53762.3-53811.6"
wire width 32 $0\be_out[31:0]
- attribute \src "libresoc.v:53481.3-53490.6"
+ attribute \src "libresoc.v:53473.3-53482.6"
wire width 4 $0\cur_idx0[3:0]
- attribute \src "libresoc.v:53690.3-53699.6"
+ attribute \src "libresoc.v:53682.3-53691.6"
wire width 4 $0\cur_idx10[3:0]
- attribute \src "libresoc.v:53710.3-53719.6"
+ attribute \src "libresoc.v:53702.3-53711.6"
wire width 4 $0\cur_idx11[3:0]
- attribute \src "libresoc.v:53730.3-53739.6"
+ attribute \src "libresoc.v:53722.3-53731.6"
wire width 4 $0\cur_idx12[3:0]
- attribute \src "libresoc.v:53750.3-53759.6"
+ attribute \src "libresoc.v:53742.3-53751.6"
wire width 4 $0\cur_idx13[3:0]
- attribute \src "libresoc.v:53820.3-53829.6"
+ attribute \src "libresoc.v:53812.3-53821.6"
wire width 4 $0\cur_idx14[3:0]
- attribute \src "libresoc.v:53840.3-53849.6"
+ attribute \src "libresoc.v:53832.3-53841.6"
wire width 4 $0\cur_idx15[3:0]
- attribute \src "libresoc.v:53501.3-53510.6"
+ attribute \src "libresoc.v:53493.3-53502.6"
wire width 4 $0\cur_idx1[3:0]
- attribute \src "libresoc.v:53521.3-53530.6"
+ attribute \src "libresoc.v:53513.3-53522.6"
wire width 4 $0\cur_idx2[3:0]
- attribute \src "libresoc.v:53541.3-53550.6"
+ attribute \src "libresoc.v:53533.3-53542.6"
wire width 4 $0\cur_idx3[3:0]
- attribute \src "libresoc.v:53570.3-53579.6"
+ attribute \src "libresoc.v:53562.3-53571.6"
wire width 4 $0\cur_idx4[3:0]
- attribute \src "libresoc.v:53590.3-53599.6"
+ attribute \src "libresoc.v:53582.3-53591.6"
wire width 4 $0\cur_idx5[3:0]
- attribute \src "libresoc.v:53610.3-53619.6"
+ attribute \src "libresoc.v:53602.3-53611.6"
wire width 4 $0\cur_idx6[3:0]
- attribute \src "libresoc.v:53630.3-53639.6"
+ attribute \src "libresoc.v:53622.3-53631.6"
wire width 4 $0\cur_idx7[3:0]
- attribute \src "libresoc.v:53650.3-53659.6"
+ attribute \src "libresoc.v:53642.3-53651.6"
wire width 4 $0\cur_idx8[3:0]
- attribute \src "libresoc.v:53670.3-53679.6"
+ attribute \src "libresoc.v:53662.3-53671.6"
wire width 4 $0\cur_idx9[3:0]
- attribute \src "libresoc.v:53471.3-53480.6"
+ attribute \src "libresoc.v:53463.3-53472.6"
wire width 8 $0\cur_pri0[7:0]
- attribute \src "libresoc.v:53680.3-53689.6"
+ attribute \src "libresoc.v:53672.3-53681.6"
wire width 8 $0\cur_pri10[7:0]
- attribute \src "libresoc.v:53700.3-53709.6"
+ attribute \src "libresoc.v:53692.3-53701.6"
wire width 8 $0\cur_pri11[7:0]
- attribute \src "libresoc.v:53720.3-53729.6"
+ attribute \src "libresoc.v:53712.3-53721.6"
wire width 8 $0\cur_pri12[7:0]
- attribute \src "libresoc.v:53740.3-53749.6"
+ attribute \src "libresoc.v:53732.3-53741.6"
wire width 8 $0\cur_pri13[7:0]
- attribute \src "libresoc.v:53760.3-53769.6"
+ attribute \src "libresoc.v:53752.3-53761.6"
wire width 8 $0\cur_pri14[7:0]
- attribute \src "libresoc.v:53830.3-53839.6"
+ attribute \src "libresoc.v:53822.3-53831.6"
wire width 8 $0\cur_pri15[7:0]
- attribute \src "libresoc.v:53491.3-53500.6"
+ attribute \src "libresoc.v:53483.3-53492.6"
wire width 8 $0\cur_pri1[7:0]
- attribute \src "libresoc.v:53511.3-53520.6"
+ attribute \src "libresoc.v:53503.3-53512.6"
wire width 8 $0\cur_pri2[7:0]
- attribute \src "libresoc.v:53531.3-53540.6"
+ attribute \src "libresoc.v:53523.3-53532.6"
wire width 8 $0\cur_pri3[7:0]
- attribute \src "libresoc.v:53551.3-53560.6"
+ attribute \src "libresoc.v:53543.3-53552.6"
wire width 8 $0\cur_pri4[7:0]
- attribute \src "libresoc.v:53580.3-53589.6"
+ attribute \src "libresoc.v:53572.3-53581.6"
wire width 8 $0\cur_pri5[7:0]
- attribute \src "libresoc.v:53600.3-53609.6"
+ attribute \src "libresoc.v:53592.3-53601.6"
wire width 8 $0\cur_pri6[7:0]
- attribute \src "libresoc.v:53620.3-53629.6"
+ attribute \src "libresoc.v:53612.3-53621.6"
wire width 8 $0\cur_pri7[7:0]
- attribute \src "libresoc.v:53640.3-53649.6"
+ attribute \src "libresoc.v:53632.3-53641.6"
wire width 8 $0\cur_pri8[7:0]
- attribute \src "libresoc.v:53660.3-53669.6"
+ attribute \src "libresoc.v:53652.3-53661.6"
wire width 8 $0\cur_pri9[7:0]
- attribute \src "libresoc.v:53850.3-53859.6"
+ attribute \src "libresoc.v:53842.3-53851.6"
wire $0\ibit[0:0]
- attribute \src "libresoc.v:53361.3-53362.25"
+ attribute \src "libresoc.v:53353.3-53354.25"
wire width 8 $0\icp_o_pri[7:0]
- attribute \src "libresoc.v:53359.3-53360.28"
+ attribute \src "libresoc.v:53351.3-53352.28"
wire width 4 $0\icp_o_src[3:0]
- attribute \src "libresoc.v:53869.3-53877.6"
+ attribute \src "libresoc.v:53861.3-53869.6"
wire $0\ics_wb__ack$next[0:0]$2572
- attribute \src "libresoc.v:53353.3-53354.39"
+ attribute \src "libresoc.v:53345.3-53346.39"
wire $0\ics_wb__ack[0:0]
- attribute \src "libresoc.v:53860.3-53868.6"
+ attribute \src "libresoc.v:53852.3-53860.6"
wire width 32 $0\ics_wb__dat_r$next[31:0]$2569
- attribute \src "libresoc.v:53355.3-53356.43"
+ attribute \src "libresoc.v:53347.3-53348.43"
wire width 32 $0\ics_wb__dat_r[31:0]
- attribute \src "libresoc.v:52841.7-52841.20"
+ attribute \src "libresoc.v:52833.7-52833.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:53561.3-53569.6"
+ attribute \src "libresoc.v:53553.3-53561.6"
wire width 16 $0\int_level_l$next[15:0]$2541
- attribute \src "libresoc.v:53357.3-53358.39"
+ attribute \src "libresoc.v:53349.3-53350.39"
wire width 16 $0\int_level_l[15:0]
- attribute \src "libresoc.v:53385.3-53470.6"
+ attribute \src "libresoc.v:53377.3-53462.6"
wire width 8 $0\xive0_pri$next[7:0]$2451
- attribute \src "libresoc.v:53363.3-53364.35"
+ attribute \src "libresoc.v:53355.3-53356.35"
wire width 8 $0\xive0_pri[7:0]
- attribute \src "libresoc.v:53385.3-53470.6"
+ attribute \src "libresoc.v:53377.3-53462.6"
wire width 8 $0\xive10_pri$next[7:0]$2452
- attribute \src "libresoc.v:53383.3-53384.37"
+ attribute \src "libresoc.v:53375.3-53376.37"
wire width 8 $0\xive10_pri[7:0]
- attribute \src "libresoc.v:53385.3-53470.6"
+ attribute \src "libresoc.v:53377.3-53462.6"
wire width 8 $0\xive11_pri$next[7:0]$2453
- attribute \src "libresoc.v:53343.3-53344.37"
+ attribute \src "libresoc.v:53335.3-53336.37"
wire width 8 $0\xive11_pri[7:0]
- attribute \src "libresoc.v:53385.3-53470.6"
+ attribute \src "libresoc.v:53377.3-53462.6"
wire width 8 $0\xive12_pri$next[7:0]$2454
- attribute \src "libresoc.v:53345.3-53346.37"
+ attribute \src "libresoc.v:53337.3-53338.37"
wire width 8 $0\xive12_pri[7:0]
- attribute \src "libresoc.v:53385.3-53470.6"
+ attribute \src "libresoc.v:53377.3-53462.6"
wire width 8 $0\xive13_pri$next[7:0]$2455
- attribute \src "libresoc.v:53347.3-53348.37"
+ attribute \src "libresoc.v:53339.3-53340.37"
wire width 8 $0\xive13_pri[7:0]
- attribute \src "libresoc.v:53385.3-53470.6"
+ attribute \src "libresoc.v:53377.3-53462.6"
wire width 8 $0\xive14_pri$next[7:0]$2456
- attribute \src "libresoc.v:53349.3-53350.37"
+ attribute \src "libresoc.v:53341.3-53342.37"
wire width 8 $0\xive14_pri[7:0]
- attribute \src "libresoc.v:53385.3-53470.6"
+ attribute \src "libresoc.v:53377.3-53462.6"
wire width 8 $0\xive15_pri$next[7:0]$2457
- attribute \src "libresoc.v:53351.3-53352.37"
+ attribute \src "libresoc.v:53343.3-53344.37"
wire width 8 $0\xive15_pri[7:0]
- attribute \src "libresoc.v:53385.3-53470.6"
+ attribute \src "libresoc.v:53377.3-53462.6"
wire width 8 $0\xive1_pri$next[7:0]$2458
- attribute \src "libresoc.v:53365.3-53366.35"
+ attribute \src "libresoc.v:53357.3-53358.35"
wire width 8 $0\xive1_pri[7:0]
- attribute \src "libresoc.v:53385.3-53470.6"
+ attribute \src "libresoc.v:53377.3-53462.6"
wire width 8 $0\xive2_pri$next[7:0]$2459
- attribute \src "libresoc.v:53367.3-53368.35"
+ attribute \src "libresoc.v:53359.3-53360.35"
wire width 8 $0\xive2_pri[7:0]
- attribute \src "libresoc.v:53385.3-53470.6"
+ attribute \src "libresoc.v:53377.3-53462.6"
wire width 8 $0\xive3_pri$next[7:0]$2460
- attribute \src "libresoc.v:53369.3-53370.35"
+ attribute \src "libresoc.v:53361.3-53362.35"
wire width 8 $0\xive3_pri[7:0]
- attribute \src "libresoc.v:53385.3-53470.6"
+ attribute \src "libresoc.v:53377.3-53462.6"
wire width 8 $0\xive4_pri$next[7:0]$2461
- attribute \src "libresoc.v:53371.3-53372.35"
+ attribute \src "libresoc.v:53363.3-53364.35"
wire width 8 $0\xive4_pri[7:0]
- attribute \src "libresoc.v:53385.3-53470.6"
+ attribute \src "libresoc.v:53377.3-53462.6"
wire width 8 $0\xive5_pri$next[7:0]$2462
- attribute \src "libresoc.v:53373.3-53374.35"
+ attribute \src "libresoc.v:53365.3-53366.35"
wire width 8 $0\xive5_pri[7:0]
- attribute \src "libresoc.v:53385.3-53470.6"
+ attribute \src "libresoc.v:53377.3-53462.6"
wire width 8 $0\xive6_pri$next[7:0]$2463
- attribute \src "libresoc.v:53375.3-53376.35"
+ attribute \src "libresoc.v:53367.3-53368.35"
wire width 8 $0\xive6_pri[7:0]
- attribute \src "libresoc.v:53385.3-53470.6"
+ attribute \src "libresoc.v:53377.3-53462.6"
wire width 8 $0\xive7_pri$next[7:0]$2464
- attribute \src "libresoc.v:53377.3-53378.35"
+ attribute \src "libresoc.v:53369.3-53370.35"
wire width 8 $0\xive7_pri[7:0]
- attribute \src "libresoc.v:53385.3-53470.6"
+ attribute \src "libresoc.v:53377.3-53462.6"
wire width 8 $0\xive8_pri$next[7:0]$2465
- attribute \src "libresoc.v:53379.3-53380.35"
+ attribute \src "libresoc.v:53371.3-53372.35"
wire width 8 $0\xive8_pri[7:0]
- attribute \src "libresoc.v:53385.3-53470.6"
+ attribute \src "libresoc.v:53377.3-53462.6"
wire width 8 $0\xive9_pri$next[7:0]$2466
- attribute \src "libresoc.v:53381.3-53382.35"
+ attribute \src "libresoc.v:53373.3-53374.35"
wire width 8 $0\xive9_pri[7:0]
- attribute \src "libresoc.v:53770.3-53819.6"
+ attribute \src "libresoc.v:53762.3-53811.6"
wire width 32 $1\be_out[31:0]
- attribute \src "libresoc.v:53481.3-53490.6"
+ attribute \src "libresoc.v:53473.3-53482.6"
wire width 4 $1\cur_idx0[3:0]
- attribute \src "libresoc.v:53690.3-53699.6"
+ attribute \src "libresoc.v:53682.3-53691.6"
wire width 4 $1\cur_idx10[3:0]
- attribute \src "libresoc.v:53710.3-53719.6"
+ attribute \src "libresoc.v:53702.3-53711.6"
wire width 4 $1\cur_idx11[3:0]
- attribute \src "libresoc.v:53730.3-53739.6"
+ attribute \src "libresoc.v:53722.3-53731.6"
wire width 4 $1\cur_idx12[3:0]
- attribute \src "libresoc.v:53750.3-53759.6"
+ attribute \src "libresoc.v:53742.3-53751.6"
wire width 4 $1\cur_idx13[3:0]
- attribute \src "libresoc.v:53820.3-53829.6"
+ attribute \src "libresoc.v:53812.3-53821.6"
wire width 4 $1\cur_idx14[3:0]
- attribute \src "libresoc.v:53840.3-53849.6"
+ attribute \src "libresoc.v:53832.3-53841.6"
wire width 4 $1\cur_idx15[3:0]
- attribute \src "libresoc.v:53501.3-53510.6"
+ attribute \src "libresoc.v:53493.3-53502.6"
wire width 4 $1\cur_idx1[3:0]
- attribute \src "libresoc.v:53521.3-53530.6"
+ attribute \src "libresoc.v:53513.3-53522.6"
wire width 4 $1\cur_idx2[3:0]
- attribute \src "libresoc.v:53541.3-53550.6"
+ attribute \src "libresoc.v:53533.3-53542.6"
wire width 4 $1\cur_idx3[3:0]
- attribute \src "libresoc.v:53570.3-53579.6"
+ attribute \src "libresoc.v:53562.3-53571.6"
wire width 4 $1\cur_idx4[3:0]
- attribute \src "libresoc.v:53590.3-53599.6"
+ attribute \src "libresoc.v:53582.3-53591.6"
wire width 4 $1\cur_idx5[3:0]
- attribute \src "libresoc.v:53610.3-53619.6"
+ attribute \src "libresoc.v:53602.3-53611.6"
wire width 4 $1\cur_idx6[3:0]
- attribute \src "libresoc.v:53630.3-53639.6"
+ attribute \src "libresoc.v:53622.3-53631.6"
wire width 4 $1\cur_idx7[3:0]
- attribute \src "libresoc.v:53650.3-53659.6"
+ attribute \src "libresoc.v:53642.3-53651.6"
wire width 4 $1\cur_idx8[3:0]
- attribute \src "libresoc.v:53670.3-53679.6"
+ attribute \src "libresoc.v:53662.3-53671.6"
wire width 4 $1\cur_idx9[3:0]
- attribute \src "libresoc.v:53471.3-53480.6"
+ attribute \src "libresoc.v:53463.3-53472.6"
wire width 8 $1\cur_pri0[7:0]
- attribute \src "libresoc.v:53680.3-53689.6"
+ attribute \src "libresoc.v:53672.3-53681.6"
wire width 8 $1\cur_pri10[7:0]
- attribute \src "libresoc.v:53700.3-53709.6"
+ attribute \src "libresoc.v:53692.3-53701.6"
wire width 8 $1\cur_pri11[7:0]
- attribute \src "libresoc.v:53720.3-53729.6"
+ attribute \src "libresoc.v:53712.3-53721.6"
wire width 8 $1\cur_pri12[7:0]
- attribute \src "libresoc.v:53740.3-53749.6"
+ attribute \src "libresoc.v:53732.3-53741.6"
wire width 8 $1\cur_pri13[7:0]
- attribute \src "libresoc.v:53760.3-53769.6"
+ attribute \src "libresoc.v:53752.3-53761.6"
wire width 8 $1\cur_pri14[7:0]
- attribute \src "libresoc.v:53830.3-53839.6"
+ attribute \src "libresoc.v:53822.3-53831.6"
wire width 8 $1\cur_pri15[7:0]
- attribute \src "libresoc.v:53491.3-53500.6"
+ attribute \src "libresoc.v:53483.3-53492.6"
wire width 8 $1\cur_pri1[7:0]
- attribute \src "libresoc.v:53511.3-53520.6"
+ attribute \src "libresoc.v:53503.3-53512.6"
wire width 8 $1\cur_pri2[7:0]
- attribute \src "libresoc.v:53531.3-53540.6"
+ attribute \src "libresoc.v:53523.3-53532.6"
wire width 8 $1\cur_pri3[7:0]
- attribute \src "libresoc.v:53551.3-53560.6"
+ attribute \src "libresoc.v:53543.3-53552.6"
wire width 8 $1\cur_pri4[7:0]
- attribute \src "libresoc.v:53580.3-53589.6"
+ attribute \src "libresoc.v:53572.3-53581.6"
wire width 8 $1\cur_pri5[7:0]
- attribute \src "libresoc.v:53600.3-53609.6"
+ attribute \src "libresoc.v:53592.3-53601.6"
wire width 8 $1\cur_pri6[7:0]
- attribute \src "libresoc.v:53620.3-53629.6"
+ attribute \src "libresoc.v:53612.3-53621.6"
wire width 8 $1\cur_pri7[7:0]
- attribute \src "libresoc.v:53640.3-53649.6"
+ attribute \src "libresoc.v:53632.3-53641.6"
wire width 8 $1\cur_pri8[7:0]
- attribute \src "libresoc.v:53660.3-53669.6"
+ attribute \src "libresoc.v:53652.3-53661.6"
wire width 8 $1\cur_pri9[7:0]
- attribute \src "libresoc.v:53850.3-53859.6"
+ attribute \src "libresoc.v:53842.3-53851.6"
wire $1\ibit[0:0]
- attribute \src "libresoc.v:53122.13-53122.30"
+ attribute \src "libresoc.v:53114.13-53114.30"
wire width 8 $1\icp_o_pri[7:0]
- attribute \src "libresoc.v:53127.13-53127.29"
+ attribute \src "libresoc.v:53119.13-53119.29"
wire width 4 $1\icp_o_src[3:0]
- attribute \src "libresoc.v:53869.3-53877.6"
+ attribute \src "libresoc.v:53861.3-53869.6"
wire $1\ics_wb__ack$next[0:0]$2573
- attribute \src "libresoc.v:53136.7-53136.25"
+ attribute \src "libresoc.v:53128.7-53128.25"
wire $1\ics_wb__ack[0:0]
- attribute \src "libresoc.v:53860.3-53868.6"
+ attribute \src "libresoc.v:53852.3-53860.6"
wire width 32 $1\ics_wb__dat_r$next[31:0]$2570
- attribute \src "libresoc.v:53145.14-53145.35"
+ attribute \src "libresoc.v:53137.14-53137.35"
wire width 32 $1\ics_wb__dat_r[31:0]
- attribute \src "libresoc.v:53561.3-53569.6"
+ attribute \src "libresoc.v:53553.3-53561.6"
wire width 16 $1\int_level_l$next[15:0]$2542
- attribute \src "libresoc.v:53157.14-53157.36"
+ attribute \src "libresoc.v:53149.14-53149.36"
wire width 16 $1\int_level_l[15:0]
- attribute \src "libresoc.v:53385.3-53470.6"
+ attribute \src "libresoc.v:53377.3-53462.6"
wire width 8 $1\xive0_pri$next[7:0]$2467
- attribute \src "libresoc.v:53177.13-53177.30"
+ attribute \src "libresoc.v:53169.13-53169.30"
wire width 8 $1\xive0_pri[7:0]
- attribute \src "libresoc.v:53385.3-53470.6"
+ attribute \src "libresoc.v:53377.3-53462.6"
wire width 8 $1\xive10_pri$next[7:0]$2468
- attribute \src "libresoc.v:53181.13-53181.31"
+ attribute \src "libresoc.v:53173.13-53173.31"
wire width 8 $1\xive10_pri[7:0]
- attribute \src "libresoc.v:53385.3-53470.6"
+ attribute \src "libresoc.v:53377.3-53462.6"
wire width 8 $1\xive11_pri$next[7:0]$2469
- attribute \src "libresoc.v:53185.13-53185.31"
+ attribute \src "libresoc.v:53177.13-53177.31"
wire width 8 $1\xive11_pri[7:0]
- attribute \src "libresoc.v:53385.3-53470.6"
+ attribute \src "libresoc.v:53377.3-53462.6"
wire width 8 $1\xive12_pri$next[7:0]$2470
- attribute \src "libresoc.v:53189.13-53189.31"
+ attribute \src "libresoc.v:53181.13-53181.31"
wire width 8 $1\xive12_pri[7:0]
- attribute \src "libresoc.v:53385.3-53470.6"
+ attribute \src "libresoc.v:53377.3-53462.6"
wire width 8 $1\xive13_pri$next[7:0]$2471
- attribute \src "libresoc.v:53193.13-53193.31"
+ attribute \src "libresoc.v:53185.13-53185.31"
wire width 8 $1\xive13_pri[7:0]
- attribute \src "libresoc.v:53385.3-53470.6"
+ attribute \src "libresoc.v:53377.3-53462.6"
wire width 8 $1\xive14_pri$next[7:0]$2472
- attribute \src "libresoc.v:53197.13-53197.31"
+ attribute \src "libresoc.v:53189.13-53189.31"
wire width 8 $1\xive14_pri[7:0]
- attribute \src "libresoc.v:53385.3-53470.6"
+ attribute \src "libresoc.v:53377.3-53462.6"
wire width 8 $1\xive15_pri$next[7:0]$2473
- attribute \src "libresoc.v:53201.13-53201.31"
+ attribute \src "libresoc.v:53193.13-53193.31"
wire width 8 $1\xive15_pri[7:0]
- attribute \src "libresoc.v:53385.3-53470.6"
+ attribute \src "libresoc.v:53377.3-53462.6"
wire width 8 $1\xive1_pri$next[7:0]$2474
- attribute \src "libresoc.v:53205.13-53205.30"
+ attribute \src "libresoc.v:53197.13-53197.30"
wire width 8 $1\xive1_pri[7:0]
- attribute \src "libresoc.v:53385.3-53470.6"
+ attribute \src "libresoc.v:53377.3-53462.6"
wire width 8 $1\xive2_pri$next[7:0]$2475
- attribute \src "libresoc.v:53209.13-53209.30"
+ attribute \src "libresoc.v:53201.13-53201.30"
wire width 8 $1\xive2_pri[7:0]
- attribute \src "libresoc.v:53385.3-53470.6"
+ attribute \src "libresoc.v:53377.3-53462.6"
wire width 8 $1\xive3_pri$next[7:0]$2476
- attribute \src "libresoc.v:53213.13-53213.30"
+ attribute \src "libresoc.v:53205.13-53205.30"
wire width 8 $1\xive3_pri[7:0]
- attribute \src "libresoc.v:53385.3-53470.6"
+ attribute \src "libresoc.v:53377.3-53462.6"
wire width 8 $1\xive4_pri$next[7:0]$2477
- attribute \src "libresoc.v:53217.13-53217.30"
+ attribute \src "libresoc.v:53209.13-53209.30"
wire width 8 $1\xive4_pri[7:0]
- attribute \src "libresoc.v:53385.3-53470.6"
+ attribute \src "libresoc.v:53377.3-53462.6"
wire width 8 $1\xive5_pri$next[7:0]$2478
- attribute \src "libresoc.v:53221.13-53221.30"
+ attribute \src "libresoc.v:53213.13-53213.30"
wire width 8 $1\xive5_pri[7:0]
- attribute \src "libresoc.v:53385.3-53470.6"
+ attribute \src "libresoc.v:53377.3-53462.6"
wire width 8 $1\xive6_pri$next[7:0]$2479
- attribute \src "libresoc.v:53225.13-53225.30"
+ attribute \src "libresoc.v:53217.13-53217.30"
wire width 8 $1\xive6_pri[7:0]
- attribute \src "libresoc.v:53385.3-53470.6"
+ attribute \src "libresoc.v:53377.3-53462.6"
wire width 8 $1\xive7_pri$next[7:0]$2480
- attribute \src "libresoc.v:53229.13-53229.30"
+ attribute \src "libresoc.v:53221.13-53221.30"
wire width 8 $1\xive7_pri[7:0]
- attribute \src "libresoc.v:53385.3-53470.6"
+ attribute \src "libresoc.v:53377.3-53462.6"
wire width 8 $1\xive8_pri$next[7:0]$2481
- attribute \src "libresoc.v:53233.13-53233.30"
+ attribute \src "libresoc.v:53225.13-53225.30"
wire width 8 $1\xive8_pri[7:0]
- attribute \src "libresoc.v:53385.3-53470.6"
+ attribute \src "libresoc.v:53377.3-53462.6"
wire width 8 $1\xive9_pri$next[7:0]$2482
- attribute \src "libresoc.v:53237.13-53237.30"
+ attribute \src "libresoc.v:53229.13-53229.30"
wire width 8 $1\xive9_pri[7:0]
- attribute \src "libresoc.v:53770.3-53819.6"
+ attribute \src "libresoc.v:53762.3-53811.6"
wire width 32 $2\be_out[31:0]
- attribute \src "libresoc.v:53385.3-53470.6"
+ attribute \src "libresoc.v:53377.3-53462.6"
wire width 8 $2\xive0_pri$next[7:0]$2483
- attribute \src "libresoc.v:53385.3-53470.6"
+ attribute \src "libresoc.v:53377.3-53462.6"
wire width 8 $2\xive10_pri$next[7:0]$2484
- attribute \src "libresoc.v:53385.3-53470.6"
+ attribute \src "libresoc.v:53377.3-53462.6"
wire width 8 $2\xive11_pri$next[7:0]$2485
- attribute \src "libresoc.v:53385.3-53470.6"
+ attribute \src "libresoc.v:53377.3-53462.6"
wire width 8 $2\xive12_pri$next[7:0]$2486
- attribute \src "libresoc.v:53385.3-53470.6"
+ attribute \src "libresoc.v:53377.3-53462.6"
wire width 8 $2\xive13_pri$next[7:0]$2487
- attribute \src "libresoc.v:53385.3-53470.6"
+ attribute \src "libresoc.v:53377.3-53462.6"
wire width 8 $2\xive14_pri$next[7:0]$2488
- attribute \src "libresoc.v:53385.3-53470.6"
+ attribute \src "libresoc.v:53377.3-53462.6"
wire width 8 $2\xive15_pri$next[7:0]$2489
- attribute \src "libresoc.v:53385.3-53470.6"
+ attribute \src "libresoc.v:53377.3-53462.6"
wire width 8 $2\xive1_pri$next[7:0]$2490
- attribute \src "libresoc.v:53385.3-53470.6"
+ attribute \src "libresoc.v:53377.3-53462.6"
wire width 8 $2\xive2_pri$next[7:0]$2491
- attribute \src "libresoc.v:53385.3-53470.6"
+ attribute \src "libresoc.v:53377.3-53462.6"
wire width 8 $2\xive3_pri$next[7:0]$2492
- attribute \src "libresoc.v:53385.3-53470.6"
+ attribute \src "libresoc.v:53377.3-53462.6"
wire width 8 $2\xive4_pri$next[7:0]$2493
- attribute \src "libresoc.v:53385.3-53470.6"
+ attribute \src "libresoc.v:53377.3-53462.6"
wire width 8 $2\xive5_pri$next[7:0]$2494
- attribute \src "libresoc.v:53385.3-53470.6"
+ attribute \src "libresoc.v:53377.3-53462.6"
wire width 8 $2\xive6_pri$next[7:0]$2495
- attribute \src "libresoc.v:53385.3-53470.6"
+ attribute \src "libresoc.v:53377.3-53462.6"
wire width 8 $2\xive7_pri$next[7:0]$2496
- attribute \src "libresoc.v:53385.3-53470.6"
+ attribute \src "libresoc.v:53377.3-53462.6"
wire width 8 $2\xive8_pri$next[7:0]$2497
- attribute \src "libresoc.v:53385.3-53470.6"
+ attribute \src "libresoc.v:53377.3-53462.6"
wire width 8 $2\xive9_pri$next[7:0]$2498
- attribute \src "libresoc.v:53385.3-53470.6"
+ attribute \src "libresoc.v:53377.3-53462.6"
wire width 8 $3\xive0_pri$next[7:0]$2499
- attribute \src "libresoc.v:53385.3-53470.6"
+ attribute \src "libresoc.v:53377.3-53462.6"
wire width 8 $3\xive10_pri$next[7:0]$2500
- attribute \src "libresoc.v:53385.3-53470.6"
+ attribute \src "libresoc.v:53377.3-53462.6"
wire width 8 $3\xive11_pri$next[7:0]$2501
- attribute \src "libresoc.v:53385.3-53470.6"
+ attribute \src "libresoc.v:53377.3-53462.6"
wire width 8 $3\xive12_pri$next[7:0]$2502
- attribute \src "libresoc.v:53385.3-53470.6"
+ attribute \src "libresoc.v:53377.3-53462.6"
wire width 8 $3\xive13_pri$next[7:0]$2503
- attribute \src "libresoc.v:53385.3-53470.6"
+ attribute \src "libresoc.v:53377.3-53462.6"
wire width 8 $3\xive14_pri$next[7:0]$2504
- attribute \src "libresoc.v:53385.3-53470.6"
+ attribute \src "libresoc.v:53377.3-53462.6"
wire width 8 $3\xive15_pri$next[7:0]$2505
- attribute \src "libresoc.v:53385.3-53470.6"
+ attribute \src "libresoc.v:53377.3-53462.6"
wire width 8 $3\xive1_pri$next[7:0]$2506
- attribute \src "libresoc.v:53385.3-53470.6"
+ attribute \src "libresoc.v:53377.3-53462.6"
wire width 8 $3\xive2_pri$next[7:0]$2507
- attribute \src "libresoc.v:53385.3-53470.6"
+ attribute \src "libresoc.v:53377.3-53462.6"
wire width 8 $3\xive3_pri$next[7:0]$2508
- attribute \src "libresoc.v:53385.3-53470.6"
+ attribute \src "libresoc.v:53377.3-53462.6"
wire width 8 $3\xive4_pri$next[7:0]$2509
- attribute \src "libresoc.v:53385.3-53470.6"
+ attribute \src "libresoc.v:53377.3-53462.6"
wire width 8 $3\xive5_pri$next[7:0]$2510
- attribute \src "libresoc.v:53385.3-53470.6"
+ attribute \src "libresoc.v:53377.3-53462.6"
wire width 8 $3\xive6_pri$next[7:0]$2511
- attribute \src "libresoc.v:53385.3-53470.6"
+ attribute \src "libresoc.v:53377.3-53462.6"
wire width 8 $3\xive7_pri$next[7:0]$2512
- attribute \src "libresoc.v:53385.3-53470.6"
+ attribute \src "libresoc.v:53377.3-53462.6"
wire width 8 $3\xive8_pri$next[7:0]$2513
- attribute \src "libresoc.v:53385.3-53470.6"
+ attribute \src "libresoc.v:53377.3-53462.6"
wire width 8 $3\xive9_pri$next[7:0]$2514
- attribute \src "libresoc.v:53385.3-53470.6"
+ attribute \src "libresoc.v:53377.3-53462.6"
wire width 8 $4\xive0_pri$next[7:0]$2515
- attribute \src "libresoc.v:53385.3-53470.6"
+ attribute \src "libresoc.v:53377.3-53462.6"
wire width 8 $4\xive10_pri$next[7:0]$2516
- attribute \src "libresoc.v:53385.3-53470.6"
+ attribute \src "libresoc.v:53377.3-53462.6"
wire width 8 $4\xive11_pri$next[7:0]$2517
- attribute \src "libresoc.v:53385.3-53470.6"
+ attribute \src "libresoc.v:53377.3-53462.6"
wire width 8 $4\xive12_pri$next[7:0]$2518
- attribute \src "libresoc.v:53385.3-53470.6"
+ attribute \src "libresoc.v:53377.3-53462.6"
wire width 8 $4\xive13_pri$next[7:0]$2519
- attribute \src "libresoc.v:53385.3-53470.6"
+ attribute \src "libresoc.v:53377.3-53462.6"
wire width 8 $4\xive14_pri$next[7:0]$2520
- attribute \src "libresoc.v:53385.3-53470.6"
+ attribute \src "libresoc.v:53377.3-53462.6"
wire width 8 $4\xive15_pri$next[7:0]$2521
- attribute \src "libresoc.v:53385.3-53470.6"
+ attribute \src "libresoc.v:53377.3-53462.6"
wire width 8 $4\xive1_pri$next[7:0]$2522
- attribute \src "libresoc.v:53385.3-53470.6"
+ attribute \src "libresoc.v:53377.3-53462.6"
wire width 8 $4\xive2_pri$next[7:0]$2523
- attribute \src "libresoc.v:53385.3-53470.6"
+ attribute \src "libresoc.v:53377.3-53462.6"
wire width 8 $4\xive3_pri$next[7:0]$2524
- attribute \src "libresoc.v:53385.3-53470.6"
+ attribute \src "libresoc.v:53377.3-53462.6"
wire width 8 $4\xive4_pri$next[7:0]$2525
- attribute \src "libresoc.v:53385.3-53470.6"
+ attribute \src "libresoc.v:53377.3-53462.6"
wire width 8 $4\xive5_pri$next[7:0]$2526
- attribute \src "libresoc.v:53385.3-53470.6"
+ attribute \src "libresoc.v:53377.3-53462.6"
wire width 8 $4\xive6_pri$next[7:0]$2527
- attribute \src "libresoc.v:53385.3-53470.6"
+ attribute \src "libresoc.v:53377.3-53462.6"
wire width 8 $4\xive7_pri$next[7:0]$2528
- attribute \src "libresoc.v:53385.3-53470.6"
+ attribute \src "libresoc.v:53377.3-53462.6"
wire width 8 $4\xive8_pri$next[7:0]$2529
- attribute \src "libresoc.v:53385.3-53470.6"
+ attribute \src "libresoc.v:53377.3-53462.6"
wire width 8 $4\xive9_pri$next[7:0]$2530
- attribute \src "libresoc.v:53242.19-53242.113"
- wire $and$libresoc.v:53242$2328_Y
+ attribute \src "libresoc.v:53234.19-53234.113"
+ wire $and$libresoc.v:53234$2328_Y
+ attribute \src "libresoc.v:53236.19-53236.114"
+ wire $and$libresoc.v:53236$2330_Y
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- attribute \src "libresoc.v:53325.18-53325.117"
- wire width 8 $ternary$libresoc.v:53325$2411_Y
- attribute \src "libresoc.v:53327.18-53327.117"
- wire width 8 $ternary$libresoc.v:53327$2413_Y
+ wire width 8 $ternary$libresoc.v:53301$2395_Y
+ attribute \src "libresoc.v:53304.18-53304.116"
+ wire width 8 $ternary$libresoc.v:53304$2398_Y
+ attribute \src "libresoc.v:53306.18-53306.116"
+ wire width 8 $ternary$libresoc.v:53306$2400_Y
+ attribute \src "libresoc.v:53308.18-53308.117"
+ wire width 8 $ternary$libresoc.v:53308$2402_Y
+ attribute \src "libresoc.v:53310.18-53310.117"
+ wire width 8 $ternary$libresoc.v:53310$2404_Y
+ attribute \src "libresoc.v:53312.18-53312.117"
+ wire width 8 $ternary$libresoc.v:53312$2406_Y
+ attribute \src "libresoc.v:53315.18-53315.117"
+ wire width 8 $ternary$libresoc.v:53315$2409_Y
+ attribute \src "libresoc.v:53317.18-53317.117"
+ wire width 8 $ternary$libresoc.v:53317$2411_Y
+ attribute \src "libresoc.v:53319.18-53319.117"
+ wire width 8 $ternary$libresoc.v:53319$2413_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:293"
wire \$1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
wire input 7 \ics_wb__stb
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235"
wire input 11 \ics_wb__we
- attribute \src "libresoc.v:52841.7-52841.15"
+ attribute \src "libresoc.v:52833.7-52833.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:237"
wire width 16 input 5 \int_level_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221"
wire width 8 \xive9_pri$next
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:53242$2328
+ cell $and $and$libresoc.v:53234$2328
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [3]
connect \B \$99
- connect \Y $and$libresoc.v:53242$2328_Y
+ connect \Y $and$libresoc.v:53234$2328_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:53244$2330
+ cell $and $and$libresoc.v:53236$2330
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [3]
connect \B \$103
- connect \Y $and$libresoc.v:53244$2330_Y
+ connect \Y $and$libresoc.v:53236$2330_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:53246$2332
+ cell $and $and$libresoc.v:53238$2332
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [4]
connect \B \$107
- connect \Y $and$libresoc.v:53246$2332_Y
+ connect \Y $and$libresoc.v:53238$2332_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:53248$2334
+ cell $and $and$libresoc.v:53240$2334
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [4]
connect \B \$111
- connect \Y $and$libresoc.v:53248$2334_Y
+ connect \Y $and$libresoc.v:53240$2334_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:53250$2336
+ cell $and $and$libresoc.v:53242$2336
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [5]
connect \B \$115
- connect \Y $and$libresoc.v:53250$2336_Y
+ connect \Y $and$libresoc.v:53242$2336_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:53252$2338
+ cell $and $and$libresoc.v:53244$2338
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [5]
connect \B \$119
- connect \Y $and$libresoc.v:53252$2338_Y
+ connect \Y $and$libresoc.v:53244$2338_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:53254$2340
+ cell $and $and$libresoc.v:53246$2340
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [6]
connect \B \$123
- connect \Y $and$libresoc.v:53254$2340_Y
+ connect \Y $and$libresoc.v:53246$2340_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:53257$2343
+ cell $and $and$libresoc.v:53249$2343
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [6]
connect \B \$127
- connect \Y $and$libresoc.v:53257$2343_Y
+ connect \Y $and$libresoc.v:53249$2343_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:53259$2345
+ cell $and $and$libresoc.v:53251$2345
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [7]
connect \B \$131
- connect \Y $and$libresoc.v:53259$2345_Y
+ connect \Y $and$libresoc.v:53251$2345_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:53261$2347
+ cell $and $and$libresoc.v:53253$2347
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [7]
connect \B \$135
- connect \Y $and$libresoc.v:53261$2347_Y
+ connect \Y $and$libresoc.v:53253$2347_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:53264$2350
+ cell $and $and$libresoc.v:53256$2350
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [8]
connect \B \$139
- connect \Y $and$libresoc.v:53264$2350_Y
+ connect \Y $and$libresoc.v:53256$2350_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:53266$2352
+ cell $and $and$libresoc.v:53258$2352
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [8]
connect \B \$143
- connect \Y $and$libresoc.v:53266$2352_Y
+ connect \Y $and$libresoc.v:53258$2352_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:53268$2354
+ cell $and $and$libresoc.v:53260$2354
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [9]
connect \B \$147
- connect \Y $and$libresoc.v:53268$2354_Y
+ connect \Y $and$libresoc.v:53260$2354_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:53270$2356
+ cell $and $and$libresoc.v:53262$2356
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [9]
connect \B \$151
- connect \Y $and$libresoc.v:53270$2356_Y
+ connect \Y $and$libresoc.v:53262$2356_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:53272$2358
+ cell $and $and$libresoc.v:53264$2358
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [10]
connect \B \$155
- connect \Y $and$libresoc.v:53272$2358_Y
+ connect \Y $and$libresoc.v:53264$2358_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:53274$2360
+ cell $and $and$libresoc.v:53266$2360
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [10]
connect \B \$159
- connect \Y $and$libresoc.v:53274$2360_Y
+ connect \Y $and$libresoc.v:53266$2360_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:53276$2362
+ cell $and $and$libresoc.v:53268$2362
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [11]
connect \B \$163
- connect \Y $and$libresoc.v:53276$2362_Y
+ connect \Y $and$libresoc.v:53268$2362_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:53279$2365
+ cell $and $and$libresoc.v:53271$2365
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [11]
connect \B \$167
- connect \Y $and$libresoc.v:53279$2365_Y
+ connect \Y $and$libresoc.v:53271$2365_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:53281$2367
+ cell $and $and$libresoc.v:53273$2367
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [12]
connect \B \$171
- connect \Y $and$libresoc.v:53281$2367_Y
+ connect \Y $and$libresoc.v:53273$2367_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:53283$2369
+ cell $and $and$libresoc.v:53275$2369
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [12]
connect \B \$175
- connect \Y $and$libresoc.v:53283$2369_Y
+ connect \Y $and$libresoc.v:53275$2369_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:53286$2372
+ cell $and $and$libresoc.v:53278$2372
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [13]
connect \B \$179
- connect \Y $and$libresoc.v:53286$2372_Y
+ connect \Y $and$libresoc.v:53278$2372_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:53288$2374
+ cell $and $and$libresoc.v:53280$2374
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [13]
connect \B \$183
- connect \Y $and$libresoc.v:53288$2374_Y
+ connect \Y $and$libresoc.v:53280$2374_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:53290$2376
+ cell $and $and$libresoc.v:53282$2376
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [14]
connect \B \$187
- connect \Y $and$libresoc.v:53290$2376_Y
+ connect \Y $and$libresoc.v:53282$2376_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:53292$2378
+ cell $and $and$libresoc.v:53284$2378
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [14]
connect \B \$191
- connect \Y $and$libresoc.v:53292$2378_Y
+ connect \Y $and$libresoc.v:53284$2378_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:53294$2380
+ cell $and $and$libresoc.v:53286$2380
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [15]
connect \B \$195
- connect \Y $and$libresoc.v:53294$2380_Y
+ connect \Y $and$libresoc.v:53286$2380_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:53297$2383
+ cell $and $and$libresoc.v:53289$2383
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [15]
connect \B \$199
- connect \Y $and$libresoc.v:53297$2383_Y
+ connect \Y $and$libresoc.v:53289$2383_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:304"
- cell $and $and$libresoc.v:53321$2407
+ cell $and $and$libresoc.v:53313$2407
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ics_wb__cyc
connect \B \ics_wb__stb
- connect \Y $and$libresoc.v:53321$2407_Y
+ connect \Y $and$libresoc.v:53313$2407_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:341"
- cell $and $and$libresoc.v:53329$2415
+ cell $and $and$libresoc.v:53321$2415
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \wb_valid
connect \B \ics_wb__we
- connect \Y $and$libresoc.v:53329$2415_Y
+ connect \Y $and$libresoc.v:53321$2415_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:53331$2417
+ cell $and $and$libresoc.v:53323$2417
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [0]
connect \B \$75
- connect \Y $and$libresoc.v:53331$2417_Y
+ connect \Y $and$libresoc.v:53323$2417_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:53333$2419
+ cell $and $and$libresoc.v:53325$2419
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [0]
connect \B \$79
- connect \Y $and$libresoc.v:53333$2419_Y
+ connect \Y $and$libresoc.v:53325$2419_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:53335$2421
+ cell $and $and$libresoc.v:53327$2421
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [1]
connect \B \$83
- connect \Y $and$libresoc.v:53335$2421_Y
+ connect \Y $and$libresoc.v:53327$2421_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:53338$2424
+ cell $and $and$libresoc.v:53330$2424
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [1]
connect \B \$87
- connect \Y $and$libresoc.v:53338$2424_Y
+ connect \Y $and$libresoc.v:53330$2424_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:53340$2426
+ cell $and $and$libresoc.v:53332$2426
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [2]
connect \B \$91
- connect \Y $and$libresoc.v:53340$2426_Y
+ connect \Y $and$libresoc.v:53332$2426_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:53342$2428
+ cell $and $and$libresoc.v:53334$2428
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [2]
connect \B \$95
- connect \Y $and$libresoc.v:53342$2428_Y
+ connect \Y $and$libresoc.v:53334$2428_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $eq $eq$libresoc.v:53256$2342
+ cell $eq $eq$libresoc.v:53248$2342
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive1_pri
connect \B 8'11111111
- connect \Y $eq$libresoc.v:53256$2342_Y
+ connect \Y $eq$libresoc.v:53248$2342_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $eq $eq$libresoc.v:53278$2364
+ cell $eq $eq$libresoc.v:53270$2364
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive2_pri
connect \B 8'11111111
- connect \Y $eq$libresoc.v:53278$2364_Y
+ connect \Y $eq$libresoc.v:53270$2364_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:293"
- cell $eq $eq$libresoc.v:53295$2381
+ cell $eq $eq$libresoc.v:53287$2381
parameter \A_SIGNED 0
parameter \A_WIDTH 10
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ics_wb__adr [9:0]
connect \B 1'0
- connect \Y $eq$libresoc.v:53295$2381_Y
+ connect \Y $eq$libresoc.v:53287$2381_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $eq $eq$libresoc.v:53298$2384
+ cell $eq $eq$libresoc.v:53290$2384
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cur_pri15
connect \B 8'11111111
- connect \Y $eq$libresoc.v:53298$2384_Y
+ connect \Y $eq$libresoc.v:53290$2384_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $eq $eq$libresoc.v:53300$2386
+ cell $eq $eq$libresoc.v:53292$2386
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive3_pri
connect \B 8'11111111
- connect \Y $eq$libresoc.v:53300$2386_Y
+ connect \Y $eq$libresoc.v:53292$2386_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $eq $eq$libresoc.v:53302$2388
+ cell $eq $eq$libresoc.v:53294$2388
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive4_pri
connect \B 8'11111111
- connect \Y $eq$libresoc.v:53302$2388_Y
+ connect \Y $eq$libresoc.v:53294$2388_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $eq $eq$libresoc.v:53304$2390
+ cell $eq $eq$libresoc.v:53296$2390
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive5_pri
connect \B 8'11111111
- connect \Y $eq$libresoc.v:53304$2390_Y
+ connect \Y $eq$libresoc.v:53296$2390_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $eq $eq$libresoc.v:53306$2392
+ cell $eq $eq$libresoc.v:53298$2392
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive6_pri
connect \B 8'11111111
- connect \Y $eq$libresoc.v:53306$2392_Y
+ connect \Y $eq$libresoc.v:53298$2392_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $eq $eq$libresoc.v:53308$2394
+ cell $eq $eq$libresoc.v:53300$2394
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive7_pri
connect \B 8'11111111
- connect \Y $eq$libresoc.v:53308$2394_Y
+ connect \Y $eq$libresoc.v:53300$2394_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:294"
- cell $eq $eq$libresoc.v:53310$2396
+ cell $eq $eq$libresoc.v:53302$2396
parameter \A_SIGNED 0
parameter \A_WIDTH 10
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ics_wb__adr [9:0]
connect \B 3'100
- connect \Y $eq$libresoc.v:53310$2396_Y
+ connect \Y $eq$libresoc.v:53302$2396_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $eq $eq$libresoc.v:53311$2397
+ cell $eq $eq$libresoc.v:53303$2397
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive8_pri
connect \B 8'11111111
- connect \Y $eq$libresoc.v:53311$2397_Y
+ connect \Y $eq$libresoc.v:53303$2397_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $eq $eq$libresoc.v:53313$2399
+ cell $eq $eq$libresoc.v:53305$2399
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive9_pri
connect \B 8'11111111
- connect \Y $eq$libresoc.v:53313$2399_Y
+ connect \Y $eq$libresoc.v:53305$2399_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $eq $eq$libresoc.v:53315$2401
+ cell $eq $eq$libresoc.v:53307$2401
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive10_pri
connect \B 8'11111111
- connect \Y $eq$libresoc.v:53315$2401_Y
+ connect \Y $eq$libresoc.v:53307$2401_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $eq $eq$libresoc.v:53317$2403
+ cell $eq $eq$libresoc.v:53309$2403
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive11_pri
connect \B 8'11111111
- connect \Y $eq$libresoc.v:53317$2403_Y
+ connect \Y $eq$libresoc.v:53309$2403_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $eq $eq$libresoc.v:53319$2405
+ cell $eq $eq$libresoc.v:53311$2405
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive12_pri
connect \B 8'11111111
- connect \Y $eq$libresoc.v:53319$2405_Y
+ connect \Y $eq$libresoc.v:53311$2405_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $eq $eq$libresoc.v:53322$2408
+ cell $eq $eq$libresoc.v:53314$2408
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive13_pri
connect \B 8'11111111
- connect \Y $eq$libresoc.v:53322$2408_Y
+ connect \Y $eq$libresoc.v:53314$2408_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $eq $eq$libresoc.v:53324$2410
+ cell $eq $eq$libresoc.v:53316$2410
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive14_pri
connect \B 8'11111111
- connect \Y $eq$libresoc.v:53324$2410_Y
+ connect \Y $eq$libresoc.v:53316$2410_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $eq $eq$libresoc.v:53326$2412
+ cell $eq $eq$libresoc.v:53318$2412
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive15_pri
connect \B 8'11111111
- connect \Y $eq$libresoc.v:53326$2412_Y
+ connect \Y $eq$libresoc.v:53318$2412_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $eq $eq$libresoc.v:53337$2423
+ cell $eq $eq$libresoc.v:53329$2423
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive0_pri
connect \B 8'11111111
- connect \Y $eq$libresoc.v:53337$2423_Y
+ connect \Y $eq$libresoc.v:53329$2423_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:53241$2327
+ cell $lt $lt$libresoc.v:53233$2327
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive3_pri
connect \B \cur_pri2
- connect \Y $lt$libresoc.v:53241$2327_Y
+ connect \Y $lt$libresoc.v:53233$2327_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:53243$2329
+ cell $lt $lt$libresoc.v:53235$2329
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive3_pri
connect \B \cur_pri2
- connect \Y $lt$libresoc.v:53243$2329_Y
+ connect \Y $lt$libresoc.v:53235$2329_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:53245$2331
+ cell $lt $lt$libresoc.v:53237$2331
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive4_pri
connect \B \cur_pri3
- connect \Y $lt$libresoc.v:53245$2331_Y
+ connect \Y $lt$libresoc.v:53237$2331_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:53247$2333
+ cell $lt $lt$libresoc.v:53239$2333
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive4_pri
connect \B \cur_pri3
- connect \Y $lt$libresoc.v:53247$2333_Y
+ connect \Y $lt$libresoc.v:53239$2333_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:53249$2335
+ cell $lt $lt$libresoc.v:53241$2335
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive5_pri
connect \B \cur_pri4
- connect \Y $lt$libresoc.v:53249$2335_Y
+ connect \Y $lt$libresoc.v:53241$2335_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:53251$2337
+ cell $lt $lt$libresoc.v:53243$2337
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive5_pri
connect \B \cur_pri4
- connect \Y $lt$libresoc.v:53251$2337_Y
+ connect \Y $lt$libresoc.v:53243$2337_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:53253$2339
+ cell $lt $lt$libresoc.v:53245$2339
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive6_pri
connect \B \cur_pri5
- connect \Y $lt$libresoc.v:53253$2339_Y
+ connect \Y $lt$libresoc.v:53245$2339_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:53255$2341
+ cell $lt $lt$libresoc.v:53247$2341
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive6_pri
connect \B \cur_pri5
- connect \Y $lt$libresoc.v:53255$2341_Y
+ connect \Y $lt$libresoc.v:53247$2341_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:53258$2344
+ cell $lt $lt$libresoc.v:53250$2344
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive7_pri
connect \B \cur_pri6
- connect \Y $lt$libresoc.v:53258$2344_Y
+ connect \Y $lt$libresoc.v:53250$2344_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:53260$2346
+ cell $lt $lt$libresoc.v:53252$2346
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive7_pri
connect \B \cur_pri6
- connect \Y $lt$libresoc.v:53260$2346_Y
+ connect \Y $lt$libresoc.v:53252$2346_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:53263$2349
+ cell $lt $lt$libresoc.v:53255$2349
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive8_pri
connect \B \cur_pri7
- connect \Y $lt$libresoc.v:53263$2349_Y
+ connect \Y $lt$libresoc.v:53255$2349_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:53265$2351
+ cell $lt $lt$libresoc.v:53257$2351
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive8_pri
connect \B \cur_pri7
- connect \Y $lt$libresoc.v:53265$2351_Y
+ connect \Y $lt$libresoc.v:53257$2351_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:53267$2353
+ cell $lt $lt$libresoc.v:53259$2353
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive9_pri
connect \B \cur_pri8
- connect \Y $lt$libresoc.v:53267$2353_Y
+ connect \Y $lt$libresoc.v:53259$2353_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:53269$2355
+ cell $lt $lt$libresoc.v:53261$2355
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive9_pri
connect \B \cur_pri8
- connect \Y $lt$libresoc.v:53269$2355_Y
+ connect \Y $lt$libresoc.v:53261$2355_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:53271$2357
+ cell $lt $lt$libresoc.v:53263$2357
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive10_pri
connect \B \cur_pri9
- connect \Y $lt$libresoc.v:53271$2357_Y
+ connect \Y $lt$libresoc.v:53263$2357_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:53273$2359
+ cell $lt $lt$libresoc.v:53265$2359
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive10_pri
connect \B \cur_pri9
- connect \Y $lt$libresoc.v:53273$2359_Y
+ connect \Y $lt$libresoc.v:53265$2359_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:53275$2361
+ cell $lt $lt$libresoc.v:53267$2361
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive11_pri
connect \B \cur_pri10
- connect \Y $lt$libresoc.v:53275$2361_Y
+ connect \Y $lt$libresoc.v:53267$2361_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:53277$2363
+ cell $lt $lt$libresoc.v:53269$2363
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive11_pri
connect \B \cur_pri10
- connect \Y $lt$libresoc.v:53277$2363_Y
+ connect \Y $lt$libresoc.v:53269$2363_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:53280$2366
+ cell $lt $lt$libresoc.v:53272$2366
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive12_pri
connect \B \cur_pri11
- connect \Y $lt$libresoc.v:53280$2366_Y
+ connect \Y $lt$libresoc.v:53272$2366_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:53282$2368
+ cell $lt $lt$libresoc.v:53274$2368
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive12_pri
connect \B \cur_pri11
- connect \Y $lt$libresoc.v:53282$2368_Y
+ connect \Y $lt$libresoc.v:53274$2368_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:53285$2371
+ cell $lt $lt$libresoc.v:53277$2371
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive13_pri
connect \B \cur_pri12
- connect \Y $lt$libresoc.v:53285$2371_Y
+ connect \Y $lt$libresoc.v:53277$2371_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:53287$2373
+ cell $lt $lt$libresoc.v:53279$2373
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive13_pri
connect \B \cur_pri12
- connect \Y $lt$libresoc.v:53287$2373_Y
+ connect \Y $lt$libresoc.v:53279$2373_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:53289$2375
+ cell $lt $lt$libresoc.v:53281$2375
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive14_pri
connect \B \cur_pri13
- connect \Y $lt$libresoc.v:53289$2375_Y
+ connect \Y $lt$libresoc.v:53281$2375_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:53291$2377
+ cell $lt $lt$libresoc.v:53283$2377
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive14_pri
connect \B \cur_pri13
- connect \Y $lt$libresoc.v:53291$2377_Y
+ connect \Y $lt$libresoc.v:53283$2377_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:53293$2379
+ cell $lt $lt$libresoc.v:53285$2379
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive15_pri
connect \B \cur_pri14
- connect \Y $lt$libresoc.v:53293$2379_Y
+ connect \Y $lt$libresoc.v:53285$2379_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:53296$2382
+ cell $lt $lt$libresoc.v:53288$2382
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive15_pri
connect \B \cur_pri14
- connect \Y $lt$libresoc.v:53296$2382_Y
+ connect \Y $lt$libresoc.v:53288$2382_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:53330$2416
+ cell $lt $lt$libresoc.v:53322$2416
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive0_pri
connect \B \max_pri
- connect \Y $lt$libresoc.v:53330$2416_Y
+ connect \Y $lt$libresoc.v:53322$2416_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:53332$2418
+ cell $lt $lt$libresoc.v:53324$2418
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive0_pri
connect \B \max_pri
- connect \Y $lt$libresoc.v:53332$2418_Y
+ connect \Y $lt$libresoc.v:53324$2418_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:53334$2420
+ cell $lt $lt$libresoc.v:53326$2420
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive1_pri
connect \B \cur_pri0
- connect \Y $lt$libresoc.v:53334$2420_Y
+ connect \Y $lt$libresoc.v:53326$2420_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:53336$2422
+ cell $lt $lt$libresoc.v:53328$2422
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive1_pri
connect \B \cur_pri0
- connect \Y $lt$libresoc.v:53336$2422_Y
+ connect \Y $lt$libresoc.v:53328$2422_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:53339$2425
+ cell $lt $lt$libresoc.v:53331$2425
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive2_pri
connect \B \cur_pri1
- connect \Y $lt$libresoc.v:53339$2425_Y
+ connect \Y $lt$libresoc.v:53331$2425_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:53341$2427
+ cell $lt $lt$libresoc.v:53333$2427
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive2_pri
connect \B \cur_pri1
- connect \Y $lt$libresoc.v:53341$2427_Y
+ connect \Y $lt$libresoc.v:53333$2427_Y
end
- attribute \src "libresoc.v:53328.18-53328.40"
- cell $shr $shr$libresoc.v:53328$2414
+ attribute \src "libresoc.v:53320.18-53320.40"
+ cell $shr $shr$libresoc.v:53320$2414
parameter \A_SIGNED 0
parameter \A_WIDTH 16
parameter \B_SIGNED 0
parameter \Y_WIDTH 16
connect \A \int_level_l
connect \B \reg_idx
- connect \Y $shr$libresoc.v:53328$2414_Y
+ connect \Y $shr$libresoc.v:53320$2414_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $mux $ternary$libresoc.v:53240$2326
+ cell $mux $ternary$libresoc.v:53232$2326
parameter \WIDTH 8
connect \A \xive0_pri
connect \B 8'11111111
connect \S \$8
- connect \Y $ternary$libresoc.v:53240$2326_Y
+ connect \Y $ternary$libresoc.v:53232$2326_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $mux $ternary$libresoc.v:53262$2348
+ cell $mux $ternary$libresoc.v:53254$2348
parameter \WIDTH 8
connect \A \xive1_pri
connect \B 8'11111111
connect \S \$12
- connect \Y $ternary$libresoc.v:53262$2348_Y
+ connect \Y $ternary$libresoc.v:53254$2348_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $mux $ternary$libresoc.v:53284$2370
+ cell $mux $ternary$libresoc.v:53276$2370
parameter \WIDTH 8
connect \A \xive2_pri
connect \B 8'11111111
connect \S \$16
- connect \Y $ternary$libresoc.v:53284$2370_Y
+ connect \Y $ternary$libresoc.v:53276$2370_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $mux $ternary$libresoc.v:53299$2385
+ cell $mux $ternary$libresoc.v:53291$2385
parameter \WIDTH 8
connect \A \cur_pri15
connect \B 8'11111111
connect \S \$204
- connect \Y $ternary$libresoc.v:53299$2385_Y
+ connect \Y $ternary$libresoc.v:53291$2385_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $mux $ternary$libresoc.v:53301$2387
+ cell $mux $ternary$libresoc.v:53293$2387
parameter \WIDTH 8
connect \A \xive3_pri
connect \B 8'11111111
connect \S \$20
- connect \Y $ternary$libresoc.v:53301$2387_Y
+ connect \Y $ternary$libresoc.v:53293$2387_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $mux $ternary$libresoc.v:53303$2389
+ cell $mux $ternary$libresoc.v:53295$2389
parameter \WIDTH 8
connect \A \xive4_pri
connect \B 8'11111111
connect \S \$24
- connect \Y $ternary$libresoc.v:53303$2389_Y
+ connect \Y $ternary$libresoc.v:53295$2389_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $mux $ternary$libresoc.v:53305$2391
+ cell $mux $ternary$libresoc.v:53297$2391
parameter \WIDTH 8
connect \A \xive5_pri
connect \B 8'11111111
connect \S \$28
- connect \Y $ternary$libresoc.v:53305$2391_Y
+ connect \Y $ternary$libresoc.v:53297$2391_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $mux $ternary$libresoc.v:53307$2393
+ cell $mux $ternary$libresoc.v:53299$2393
parameter \WIDTH 8
connect \A \xive6_pri
connect \B 8'11111111
connect \S \$32
- connect \Y $ternary$libresoc.v:53307$2393_Y
+ connect \Y $ternary$libresoc.v:53299$2393_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $mux $ternary$libresoc.v:53309$2395
+ cell $mux $ternary$libresoc.v:53301$2395
parameter \WIDTH 8
connect \A \xive7_pri
connect \B 8'11111111
connect \S \$36
- connect \Y $ternary$libresoc.v:53309$2395_Y
+ connect \Y $ternary$libresoc.v:53301$2395_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $mux $ternary$libresoc.v:53312$2398
+ cell $mux $ternary$libresoc.v:53304$2398
parameter \WIDTH 8
connect \A \xive8_pri
connect \B 8'11111111
connect \S \$40
- connect \Y $ternary$libresoc.v:53312$2398_Y
+ connect \Y $ternary$libresoc.v:53304$2398_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $mux $ternary$libresoc.v:53314$2400
+ cell $mux $ternary$libresoc.v:53306$2400
parameter \WIDTH 8
connect \A \xive9_pri
connect \B 8'11111111
connect \S \$44
- connect \Y $ternary$libresoc.v:53314$2400_Y
+ connect \Y $ternary$libresoc.v:53306$2400_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $mux $ternary$libresoc.v:53316$2402
+ cell $mux $ternary$libresoc.v:53308$2402
parameter \WIDTH 8
connect \A \xive10_pri
connect \B 8'11111111
connect \S \$48
- connect \Y $ternary$libresoc.v:53316$2402_Y
+ connect \Y $ternary$libresoc.v:53308$2402_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $mux $ternary$libresoc.v:53318$2404
+ cell $mux $ternary$libresoc.v:53310$2404
parameter \WIDTH 8
connect \A \xive11_pri
connect \B 8'11111111
connect \S \$52
- connect \Y $ternary$libresoc.v:53318$2404_Y
+ connect \Y $ternary$libresoc.v:53310$2404_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $mux $ternary$libresoc.v:53320$2406
+ cell $mux $ternary$libresoc.v:53312$2406
parameter \WIDTH 8
connect \A \xive12_pri
connect \B 8'11111111
connect \S \$56
- connect \Y $ternary$libresoc.v:53320$2406_Y
+ connect \Y $ternary$libresoc.v:53312$2406_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $mux $ternary$libresoc.v:53323$2409
+ cell $mux $ternary$libresoc.v:53315$2409
parameter \WIDTH 8
connect \A \xive13_pri
connect \B 8'11111111
connect \S \$60
- connect \Y $ternary$libresoc.v:53323$2409_Y
+ connect \Y $ternary$libresoc.v:53315$2409_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $mux $ternary$libresoc.v:53325$2411
+ cell $mux $ternary$libresoc.v:53317$2411
parameter \WIDTH 8
connect \A \xive14_pri
connect \B 8'11111111
connect \S \$64
- connect \Y $ternary$libresoc.v:53325$2411_Y
+ connect \Y $ternary$libresoc.v:53317$2411_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $mux $ternary$libresoc.v:53327$2413
+ cell $mux $ternary$libresoc.v:53319$2413
parameter \WIDTH 8
connect \A \xive15_pri
connect \B 8'11111111
connect \S \$68
- connect \Y $ternary$libresoc.v:53327$2413_Y
+ connect \Y $ternary$libresoc.v:53319$2413_Y
end
- attribute \src "libresoc.v:52841.7-52841.20"
- process $proc$libresoc.v:52841$2574
+ attribute \src "libresoc.v:52833.7-52833.20"
+ process $proc$libresoc.v:52833$2574
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:53122.13-53122.30"
- process $proc$libresoc.v:53122$2575
+ attribute \src "libresoc.v:53114.13-53114.30"
+ process $proc$libresoc.v:53114$2575
assign { } { }
assign $1\icp_o_pri[7:0] 8'00000000
sync always
sync init
update \icp_o_pri $1\icp_o_pri[7:0]
end
- attribute \src "libresoc.v:53127.13-53127.29"
- process $proc$libresoc.v:53127$2576
+ attribute \src "libresoc.v:53119.13-53119.29"
+ process $proc$libresoc.v:53119$2576
assign { } { }
assign $1\icp_o_src[3:0] 4'0000
sync always
sync init
update \icp_o_src $1\icp_o_src[3:0]
end
- attribute \src "libresoc.v:53136.7-53136.25"
- process $proc$libresoc.v:53136$2577
+ attribute \src "libresoc.v:53128.7-53128.25"
+ process $proc$libresoc.v:53128$2577
assign { } { }
assign $1\ics_wb__ack[0:0] 1'0
sync always
sync init
update \ics_wb__ack $1\ics_wb__ack[0:0]
end
- attribute \src "libresoc.v:53145.14-53145.35"
- process $proc$libresoc.v:53145$2578
+ attribute \src "libresoc.v:53137.14-53137.35"
+ process $proc$libresoc.v:53137$2578
assign { } { }
assign $1\ics_wb__dat_r[31:0] 0
sync always
sync init
update \ics_wb__dat_r $1\ics_wb__dat_r[31:0]
end
- attribute \src "libresoc.v:53157.14-53157.36"
- process $proc$libresoc.v:53157$2579
+ attribute \src "libresoc.v:53149.14-53149.36"
+ process $proc$libresoc.v:53149$2579
assign { } { }
assign $1\int_level_l[15:0] 16'0000000000000000
sync always
sync init
update \int_level_l $1\int_level_l[15:0]
end
- attribute \src "libresoc.v:53177.13-53177.30"
- process $proc$libresoc.v:53177$2580
+ attribute \src "libresoc.v:53169.13-53169.30"
+ process $proc$libresoc.v:53169$2580
assign { } { }
assign $1\xive0_pri[7:0] 8'11111111
sync always
sync init
update \xive0_pri $1\xive0_pri[7:0]
end
- attribute \src "libresoc.v:53181.13-53181.31"
- process $proc$libresoc.v:53181$2581
+ attribute \src "libresoc.v:53173.13-53173.31"
+ process $proc$libresoc.v:53173$2581
assign { } { }
assign $1\xive10_pri[7:0] 8'11111111
sync always
sync init
update \xive10_pri $1\xive10_pri[7:0]
end
- attribute \src "libresoc.v:53185.13-53185.31"
- process $proc$libresoc.v:53185$2582
+ attribute \src "libresoc.v:53177.13-53177.31"
+ process $proc$libresoc.v:53177$2582
assign { } { }
assign $1\xive11_pri[7:0] 8'11111111
sync always
sync init
update \xive11_pri $1\xive11_pri[7:0]
end
- attribute \src "libresoc.v:53189.13-53189.31"
- process $proc$libresoc.v:53189$2583
+ attribute \src "libresoc.v:53181.13-53181.31"
+ process $proc$libresoc.v:53181$2583
assign { } { }
assign $1\xive12_pri[7:0] 8'11111111
sync always
sync init
update \xive12_pri $1\xive12_pri[7:0]
end
- attribute \src "libresoc.v:53193.13-53193.31"
- process $proc$libresoc.v:53193$2584
+ attribute \src "libresoc.v:53185.13-53185.31"
+ process $proc$libresoc.v:53185$2584
assign { } { }
assign $1\xive13_pri[7:0] 8'11111111
sync always
sync init
update \xive13_pri $1\xive13_pri[7:0]
end
- attribute \src "libresoc.v:53197.13-53197.31"
- process $proc$libresoc.v:53197$2585
+ attribute \src "libresoc.v:53189.13-53189.31"
+ process $proc$libresoc.v:53189$2585
assign { } { }
assign $1\xive14_pri[7:0] 8'11111111
sync always
sync init
update \xive14_pri $1\xive14_pri[7:0]
end
- attribute \src "libresoc.v:53201.13-53201.31"
- process $proc$libresoc.v:53201$2586
+ attribute \src "libresoc.v:53193.13-53193.31"
+ process $proc$libresoc.v:53193$2586
assign { } { }
assign $1\xive15_pri[7:0] 8'11111111
sync always
sync init
update \xive15_pri $1\xive15_pri[7:0]
end
- attribute \src "libresoc.v:53205.13-53205.30"
- process $proc$libresoc.v:53205$2587
+ attribute \src "libresoc.v:53197.13-53197.30"
+ process $proc$libresoc.v:53197$2587
assign { } { }
assign $1\xive1_pri[7:0] 8'11111111
sync always
sync init
update \xive1_pri $1\xive1_pri[7:0]
end
- attribute \src "libresoc.v:53209.13-53209.30"
- process $proc$libresoc.v:53209$2588
+ attribute \src "libresoc.v:53201.13-53201.30"
+ process $proc$libresoc.v:53201$2588
assign { } { }
assign $1\xive2_pri[7:0] 8'11111111
sync always
sync init
update \xive2_pri $1\xive2_pri[7:0]
end
- attribute \src "libresoc.v:53213.13-53213.30"
- process $proc$libresoc.v:53213$2589
+ attribute \src "libresoc.v:53205.13-53205.30"
+ process $proc$libresoc.v:53205$2589
assign { } { }
assign $1\xive3_pri[7:0] 8'11111111
sync always
sync init
update \xive3_pri $1\xive3_pri[7:0]
end
- attribute \src "libresoc.v:53217.13-53217.30"
- process $proc$libresoc.v:53217$2590
+ attribute \src "libresoc.v:53209.13-53209.30"
+ process $proc$libresoc.v:53209$2590
assign { } { }
assign $1\xive4_pri[7:0] 8'11111111
sync always
sync init
update \xive4_pri $1\xive4_pri[7:0]
end
- attribute \src "libresoc.v:53221.13-53221.30"
- process $proc$libresoc.v:53221$2591
+ attribute \src "libresoc.v:53213.13-53213.30"
+ process $proc$libresoc.v:53213$2591
assign { } { }
assign $1\xive5_pri[7:0] 8'11111111
sync always
sync init
update \xive5_pri $1\xive5_pri[7:0]
end
- attribute \src "libresoc.v:53225.13-53225.30"
- process $proc$libresoc.v:53225$2592
+ attribute \src "libresoc.v:53217.13-53217.30"
+ process $proc$libresoc.v:53217$2592
assign { } { }
assign $1\xive6_pri[7:0] 8'11111111
sync always
sync init
update \xive6_pri $1\xive6_pri[7:0]
end
- attribute \src "libresoc.v:53229.13-53229.30"
- process $proc$libresoc.v:53229$2593
+ attribute \src "libresoc.v:53221.13-53221.30"
+ process $proc$libresoc.v:53221$2593
assign { } { }
assign $1\xive7_pri[7:0] 8'11111111
sync always
sync init
update \xive7_pri $1\xive7_pri[7:0]
end
- attribute \src "libresoc.v:53233.13-53233.30"
- process $proc$libresoc.v:53233$2594
+ attribute \src "libresoc.v:53225.13-53225.30"
+ process $proc$libresoc.v:53225$2594
assign { } { }
assign $1\xive8_pri[7:0] 8'11111111
sync always
sync init
update \xive8_pri $1\xive8_pri[7:0]
end
- attribute \src "libresoc.v:53237.13-53237.30"
- process $proc$libresoc.v:53237$2595
+ attribute \src "libresoc.v:53229.13-53229.30"
+ process $proc$libresoc.v:53229$2595
assign { } { }
assign $1\xive9_pri[7:0] 8'11111111
sync always
sync init
update \xive9_pri $1\xive9_pri[7:0]
end
- attribute \src "libresoc.v:53343.3-53344.37"
- process $proc$libresoc.v:53343$2429
+ attribute \src "libresoc.v:53335.3-53336.37"
+ process $proc$libresoc.v:53335$2429
assign { } { }
assign $0\xive11_pri[7:0] \xive11_pri$next
sync posedge \clk
update \xive11_pri $0\xive11_pri[7:0]
end
- attribute \src "libresoc.v:53345.3-53346.37"
- process $proc$libresoc.v:53345$2430
+ attribute \src "libresoc.v:53337.3-53338.37"
+ process $proc$libresoc.v:53337$2430
assign { } { }
assign $0\xive12_pri[7:0] \xive12_pri$next
sync posedge \clk
update \xive12_pri $0\xive12_pri[7:0]
end
- attribute \src "libresoc.v:53347.3-53348.37"
- process $proc$libresoc.v:53347$2431
+ attribute \src "libresoc.v:53339.3-53340.37"
+ process $proc$libresoc.v:53339$2431
assign { } { }
assign $0\xive13_pri[7:0] \xive13_pri$next
sync posedge \clk
update \xive13_pri $0\xive13_pri[7:0]
end
- attribute \src "libresoc.v:53349.3-53350.37"
- process $proc$libresoc.v:53349$2432
+ attribute \src "libresoc.v:53341.3-53342.37"
+ process $proc$libresoc.v:53341$2432
assign { } { }
assign $0\xive14_pri[7:0] \xive14_pri$next
sync posedge \clk
update \xive14_pri $0\xive14_pri[7:0]
end
- attribute \src "libresoc.v:53351.3-53352.37"
- process $proc$libresoc.v:53351$2433
+ attribute \src "libresoc.v:53343.3-53344.37"
+ process $proc$libresoc.v:53343$2433
assign { } { }
assign $0\xive15_pri[7:0] \xive15_pri$next
sync posedge \clk
update \xive15_pri $0\xive15_pri[7:0]
end
- attribute \src "libresoc.v:53353.3-53354.39"
- process $proc$libresoc.v:53353$2434
+ attribute \src "libresoc.v:53345.3-53346.39"
+ process $proc$libresoc.v:53345$2434
assign { } { }
assign $0\ics_wb__ack[0:0] \ics_wb__ack$next
sync posedge \clk
update \ics_wb__ack $0\ics_wb__ack[0:0]
end
- attribute \src "libresoc.v:53355.3-53356.43"
- process $proc$libresoc.v:53355$2435
+ attribute \src "libresoc.v:53347.3-53348.43"
+ process $proc$libresoc.v:53347$2435
assign { } { }
assign $0\ics_wb__dat_r[31:0] \ics_wb__dat_r$next
sync posedge \clk
update \ics_wb__dat_r $0\ics_wb__dat_r[31:0]
end
- attribute \src "libresoc.v:53357.3-53358.39"
- process $proc$libresoc.v:53357$2436
+ attribute \src "libresoc.v:53349.3-53350.39"
+ process $proc$libresoc.v:53349$2436
assign { } { }
assign $0\int_level_l[15:0] \int_level_l$next
sync posedge \clk
update \int_level_l $0\int_level_l[15:0]
end
- attribute \src "libresoc.v:53359.3-53360.28"
- process $proc$libresoc.v:53359$2437
+ attribute \src "libresoc.v:53351.3-53352.28"
+ process $proc$libresoc.v:53351$2437
assign { } { }
assign $0\icp_o_src[3:0] \cur_idx15
sync posedge \clk
update \icp_o_src $0\icp_o_src[3:0]
end
- attribute \src "libresoc.v:53361.3-53362.25"
- process $proc$libresoc.v:53361$2438
+ attribute \src "libresoc.v:53353.3-53354.25"
+ process $proc$libresoc.v:53353$2438
assign { } { }
assign $0\icp_o_pri[7:0] \$203
sync posedge \clk
update \icp_o_pri $0\icp_o_pri[7:0]
end
- attribute \src "libresoc.v:53363.3-53364.35"
- process $proc$libresoc.v:53363$2439
+ attribute \src "libresoc.v:53355.3-53356.35"
+ process $proc$libresoc.v:53355$2439
assign { } { }
assign $0\xive0_pri[7:0] \xive0_pri$next
sync posedge \clk
update \xive0_pri $0\xive0_pri[7:0]
end
- attribute \src "libresoc.v:53365.3-53366.35"
- process $proc$libresoc.v:53365$2440
+ attribute \src "libresoc.v:53357.3-53358.35"
+ process $proc$libresoc.v:53357$2440
assign { } { }
assign $0\xive1_pri[7:0] \xive1_pri$next
sync posedge \clk
update \xive1_pri $0\xive1_pri[7:0]
end
- attribute \src "libresoc.v:53367.3-53368.35"
- process $proc$libresoc.v:53367$2441
+ attribute \src "libresoc.v:53359.3-53360.35"
+ process $proc$libresoc.v:53359$2441
assign { } { }
assign $0\xive2_pri[7:0] \xive2_pri$next
sync posedge \clk
update \xive2_pri $0\xive2_pri[7:0]
end
- attribute \src "libresoc.v:53369.3-53370.35"
- process $proc$libresoc.v:53369$2442
+ attribute \src "libresoc.v:53361.3-53362.35"
+ process $proc$libresoc.v:53361$2442
assign { } { }
assign $0\xive3_pri[7:0] \xive3_pri$next
sync posedge \clk
update \xive3_pri $0\xive3_pri[7:0]
end
- attribute \src "libresoc.v:53371.3-53372.35"
- process $proc$libresoc.v:53371$2443
+ attribute \src "libresoc.v:53363.3-53364.35"
+ process $proc$libresoc.v:53363$2443
assign { } { }
assign $0\xive4_pri[7:0] \xive4_pri$next
sync posedge \clk
update \xive4_pri $0\xive4_pri[7:0]
end
- attribute \src "libresoc.v:53373.3-53374.35"
- process $proc$libresoc.v:53373$2444
+ attribute \src "libresoc.v:53365.3-53366.35"
+ process $proc$libresoc.v:53365$2444
assign { } { }
assign $0\xive5_pri[7:0] \xive5_pri$next
sync posedge \clk
update \xive5_pri $0\xive5_pri[7:0]
end
- attribute \src "libresoc.v:53375.3-53376.35"
- process $proc$libresoc.v:53375$2445
+ attribute \src "libresoc.v:53367.3-53368.35"
+ process $proc$libresoc.v:53367$2445
assign { } { }
assign $0\xive6_pri[7:0] \xive6_pri$next
sync posedge \clk
update \xive6_pri $0\xive6_pri[7:0]
end
- attribute \src "libresoc.v:53377.3-53378.35"
- process $proc$libresoc.v:53377$2446
+ attribute \src "libresoc.v:53369.3-53370.35"
+ process $proc$libresoc.v:53369$2446
assign { } { }
assign $0\xive7_pri[7:0] \xive7_pri$next
sync posedge \clk
update \xive7_pri $0\xive7_pri[7:0]
end
- attribute \src "libresoc.v:53379.3-53380.35"
- process $proc$libresoc.v:53379$2447
+ attribute \src "libresoc.v:53371.3-53372.35"
+ process $proc$libresoc.v:53371$2447
assign { } { }
assign $0\xive8_pri[7:0] \xive8_pri$next
sync posedge \clk
update \xive8_pri $0\xive8_pri[7:0]
end
- attribute \src "libresoc.v:53381.3-53382.35"
- process $proc$libresoc.v:53381$2448
+ attribute \src "libresoc.v:53373.3-53374.35"
+ process $proc$libresoc.v:53373$2448
assign { } { }
assign $0\xive9_pri[7:0] \xive9_pri$next
sync posedge \clk
update \xive9_pri $0\xive9_pri[7:0]
end
- attribute \src "libresoc.v:53383.3-53384.37"
- process $proc$libresoc.v:53383$2449
+ attribute \src "libresoc.v:53375.3-53376.37"
+ process $proc$libresoc.v:53375$2449
assign { } { }
assign $0\xive10_pri[7:0] \xive10_pri$next
sync posedge \clk
update \xive10_pri $0\xive10_pri[7:0]
end
- attribute \src "libresoc.v:53385.3-53470.6"
- process $proc$libresoc.v:53385$2450
+ attribute \src "libresoc.v:53377.3-53462.6"
+ process $proc$libresoc.v:53377$2450
assign { } { }
assign { } { }
assign { } { }
assign $0\xive7_pri$next[7:0]$2464 $4\xive7_pri$next[7:0]$2528
assign $0\xive8_pri$next[7:0]$2465 $4\xive8_pri$next[7:0]$2529
assign $0\xive9_pri$next[7:0]$2466 $4\xive9_pri$next[7:0]$2530
- attribute \src "libresoc.v:53386.5-53386.29"
+ attribute \src "libresoc.v:53378.5-53378.29"
switch \initial
- attribute \src "libresoc.v:53386.9-53386.17"
+ attribute \src "libresoc.v:53378.9-53378.17"
case 1'1
case
end
update \xive8_pri$next $0\xive8_pri$next[7:0]$2465
update \xive9_pri$next $0\xive9_pri$next[7:0]$2466
end
- attribute \src "libresoc.v:53471.3-53480.6"
- process $proc$libresoc.v:53471$2531
+ attribute \src "libresoc.v:53463.3-53472.6"
+ process $proc$libresoc.v:53463$2531
assign { } { }
assign { } { }
assign $0\cur_pri0[7:0] $1\cur_pri0[7:0]
- attribute \src "libresoc.v:53472.5-53472.29"
+ attribute \src "libresoc.v:53464.5-53464.29"
switch \initial
- attribute \src "libresoc.v:53472.9-53472.17"
+ attribute \src "libresoc.v:53464.9-53464.17"
case 1'1
case
end
sync always
update \cur_pri0 $0\cur_pri0[7:0]
end
- attribute \src "libresoc.v:53481.3-53490.6"
- process $proc$libresoc.v:53481$2532
+ attribute \src "libresoc.v:53473.3-53482.6"
+ process $proc$libresoc.v:53473$2532
assign { } { }
assign { } { }
assign $0\cur_idx0[3:0] $1\cur_idx0[3:0]
- attribute \src "libresoc.v:53482.5-53482.29"
+ attribute \src "libresoc.v:53474.5-53474.29"
switch \initial
- attribute \src "libresoc.v:53482.9-53482.17"
+ attribute \src "libresoc.v:53474.9-53474.17"
case 1'1
case
end
sync always
update \cur_idx0 $0\cur_idx0[3:0]
end
- attribute \src "libresoc.v:53491.3-53500.6"
- process $proc$libresoc.v:53491$2533
+ attribute \src "libresoc.v:53483.3-53492.6"
+ process $proc$libresoc.v:53483$2533
assign { } { }
assign { } { }
assign $0\cur_pri1[7:0] $1\cur_pri1[7:0]
- attribute \src "libresoc.v:53492.5-53492.29"
+ attribute \src "libresoc.v:53484.5-53484.29"
switch \initial
- attribute \src "libresoc.v:53492.9-53492.17"
+ attribute \src "libresoc.v:53484.9-53484.17"
case 1'1
case
end
sync always
update \cur_pri1 $0\cur_pri1[7:0]
end
- attribute \src "libresoc.v:53501.3-53510.6"
- process $proc$libresoc.v:53501$2534
+ attribute \src "libresoc.v:53493.3-53502.6"
+ process $proc$libresoc.v:53493$2534
assign { } { }
assign { } { }
assign $0\cur_idx1[3:0] $1\cur_idx1[3:0]
- attribute \src "libresoc.v:53502.5-53502.29"
+ attribute \src "libresoc.v:53494.5-53494.29"
switch \initial
- attribute \src "libresoc.v:53502.9-53502.17"
+ attribute \src "libresoc.v:53494.9-53494.17"
case 1'1
case
end
sync always
update \cur_idx1 $0\cur_idx1[3:0]
end
- attribute \src "libresoc.v:53511.3-53520.6"
- process $proc$libresoc.v:53511$2535
+ attribute \src "libresoc.v:53503.3-53512.6"
+ process $proc$libresoc.v:53503$2535
assign { } { }
assign { } { }
assign $0\cur_pri2[7:0] $1\cur_pri2[7:0]
- attribute \src "libresoc.v:53512.5-53512.29"
+ attribute \src "libresoc.v:53504.5-53504.29"
switch \initial
- attribute \src "libresoc.v:53512.9-53512.17"
+ attribute \src "libresoc.v:53504.9-53504.17"
case 1'1
case
end
sync always
update \cur_pri2 $0\cur_pri2[7:0]
end
- attribute \src "libresoc.v:53521.3-53530.6"
- process $proc$libresoc.v:53521$2536
+ attribute \src "libresoc.v:53513.3-53522.6"
+ process $proc$libresoc.v:53513$2536
assign { } { }
assign { } { }
assign $0\cur_idx2[3:0] $1\cur_idx2[3:0]
- attribute \src "libresoc.v:53522.5-53522.29"
+ attribute \src "libresoc.v:53514.5-53514.29"
switch \initial
- attribute \src "libresoc.v:53522.9-53522.17"
+ attribute \src "libresoc.v:53514.9-53514.17"
case 1'1
case
end
sync always
update \cur_idx2 $0\cur_idx2[3:0]
end
- attribute \src "libresoc.v:53531.3-53540.6"
- process $proc$libresoc.v:53531$2537
+ attribute \src "libresoc.v:53523.3-53532.6"
+ process $proc$libresoc.v:53523$2537
assign { } { }
assign { } { }
assign $0\cur_pri3[7:0] $1\cur_pri3[7:0]
- attribute \src "libresoc.v:53532.5-53532.29"
+ attribute \src "libresoc.v:53524.5-53524.29"
switch \initial
- attribute \src "libresoc.v:53532.9-53532.17"
+ attribute \src "libresoc.v:53524.9-53524.17"
case 1'1
case
end
sync always
update \cur_pri3 $0\cur_pri3[7:0]
end
- attribute \src "libresoc.v:53541.3-53550.6"
- process $proc$libresoc.v:53541$2538
+ attribute \src "libresoc.v:53533.3-53542.6"
+ process $proc$libresoc.v:53533$2538
assign { } { }
assign { } { }
assign $0\cur_idx3[3:0] $1\cur_idx3[3:0]
- attribute \src "libresoc.v:53542.5-53542.29"
+ attribute \src "libresoc.v:53534.5-53534.29"
switch \initial
- attribute \src "libresoc.v:53542.9-53542.17"
+ attribute \src "libresoc.v:53534.9-53534.17"
case 1'1
case
end
sync always
update \cur_idx3 $0\cur_idx3[3:0]
end
- attribute \src "libresoc.v:53551.3-53560.6"
- process $proc$libresoc.v:53551$2539
+ attribute \src "libresoc.v:53543.3-53552.6"
+ process $proc$libresoc.v:53543$2539
assign { } { }
assign { } { }
assign $0\cur_pri4[7:0] $1\cur_pri4[7:0]
- attribute \src "libresoc.v:53552.5-53552.29"
+ attribute \src "libresoc.v:53544.5-53544.29"
switch \initial
- attribute \src "libresoc.v:53552.9-53552.17"
+ attribute \src "libresoc.v:53544.9-53544.17"
case 1'1
case
end
sync always
update \cur_pri4 $0\cur_pri4[7:0]
end
- attribute \src "libresoc.v:53561.3-53569.6"
- process $proc$libresoc.v:53561$2540
+ attribute \src "libresoc.v:53553.3-53561.6"
+ process $proc$libresoc.v:53553$2540
assign { } { }
assign { } { }
assign $0\int_level_l$next[15:0]$2541 $1\int_level_l$next[15:0]$2542
- attribute \src "libresoc.v:53562.5-53562.29"
+ attribute \src "libresoc.v:53554.5-53554.29"
switch \initial
- attribute \src "libresoc.v:53562.9-53562.17"
+ attribute \src "libresoc.v:53554.9-53554.17"
case 1'1
case
end
sync always
update \int_level_l$next $0\int_level_l$next[15:0]$2541
end
- attribute \src "libresoc.v:53570.3-53579.6"
- process $proc$libresoc.v:53570$2543
+ attribute \src "libresoc.v:53562.3-53571.6"
+ process $proc$libresoc.v:53562$2543
assign { } { }
assign { } { }
assign $0\cur_idx4[3:0] $1\cur_idx4[3:0]
- attribute \src "libresoc.v:53571.5-53571.29"
+ attribute \src "libresoc.v:53563.5-53563.29"
switch \initial
- attribute \src "libresoc.v:53571.9-53571.17"
+ attribute \src "libresoc.v:53563.9-53563.17"
case 1'1
case
end
sync always
update \cur_idx4 $0\cur_idx4[3:0]
end
- attribute \src "libresoc.v:53580.3-53589.6"
- process $proc$libresoc.v:53580$2544
+ attribute \src "libresoc.v:53572.3-53581.6"
+ process $proc$libresoc.v:53572$2544
assign { } { }
assign { } { }
assign $0\cur_pri5[7:0] $1\cur_pri5[7:0]
- attribute \src "libresoc.v:53581.5-53581.29"
+ attribute \src "libresoc.v:53573.5-53573.29"
switch \initial
- attribute \src "libresoc.v:53581.9-53581.17"
+ attribute \src "libresoc.v:53573.9-53573.17"
case 1'1
case
end
sync always
update \cur_pri5 $0\cur_pri5[7:0]
end
- attribute \src "libresoc.v:53590.3-53599.6"
- process $proc$libresoc.v:53590$2545
+ attribute \src "libresoc.v:53582.3-53591.6"
+ process $proc$libresoc.v:53582$2545
assign { } { }
assign { } { }
assign $0\cur_idx5[3:0] $1\cur_idx5[3:0]
- attribute \src "libresoc.v:53591.5-53591.29"
+ attribute \src "libresoc.v:53583.5-53583.29"
switch \initial
- attribute \src "libresoc.v:53591.9-53591.17"
+ attribute \src "libresoc.v:53583.9-53583.17"
case 1'1
case
end
sync always
update \cur_idx5 $0\cur_idx5[3:0]
end
- attribute \src "libresoc.v:53600.3-53609.6"
- process $proc$libresoc.v:53600$2546
+ attribute \src "libresoc.v:53592.3-53601.6"
+ process $proc$libresoc.v:53592$2546
assign { } { }
assign { } { }
assign $0\cur_pri6[7:0] $1\cur_pri6[7:0]
- attribute \src "libresoc.v:53601.5-53601.29"
+ attribute \src "libresoc.v:53593.5-53593.29"
switch \initial
- attribute \src "libresoc.v:53601.9-53601.17"
+ attribute \src "libresoc.v:53593.9-53593.17"
case 1'1
case
end
sync always
update \cur_pri6 $0\cur_pri6[7:0]
end
- attribute \src "libresoc.v:53610.3-53619.6"
- process $proc$libresoc.v:53610$2547
+ attribute \src "libresoc.v:53602.3-53611.6"
+ process $proc$libresoc.v:53602$2547
assign { } { }
assign { } { }
assign $0\cur_idx6[3:0] $1\cur_idx6[3:0]
- attribute \src "libresoc.v:53611.5-53611.29"
+ attribute \src "libresoc.v:53603.5-53603.29"
switch \initial
- attribute \src "libresoc.v:53611.9-53611.17"
+ attribute \src "libresoc.v:53603.9-53603.17"
case 1'1
case
end
sync always
update \cur_idx6 $0\cur_idx6[3:0]
end
- attribute \src "libresoc.v:53620.3-53629.6"
- process $proc$libresoc.v:53620$2548
+ attribute \src "libresoc.v:53612.3-53621.6"
+ process $proc$libresoc.v:53612$2548
assign { } { }
assign { } { }
assign $0\cur_pri7[7:0] $1\cur_pri7[7:0]
- attribute \src "libresoc.v:53621.5-53621.29"
+ attribute \src "libresoc.v:53613.5-53613.29"
switch \initial
- attribute \src "libresoc.v:53621.9-53621.17"
+ attribute \src "libresoc.v:53613.9-53613.17"
case 1'1
case
end
sync always
update \cur_pri7 $0\cur_pri7[7:0]
end
- attribute \src "libresoc.v:53630.3-53639.6"
- process $proc$libresoc.v:53630$2549
+ attribute \src "libresoc.v:53622.3-53631.6"
+ process $proc$libresoc.v:53622$2549
assign { } { }
assign { } { }
assign $0\cur_idx7[3:0] $1\cur_idx7[3:0]
- attribute \src "libresoc.v:53631.5-53631.29"
+ attribute \src "libresoc.v:53623.5-53623.29"
switch \initial
- attribute \src "libresoc.v:53631.9-53631.17"
+ attribute \src "libresoc.v:53623.9-53623.17"
case 1'1
case
end
sync always
update \cur_idx7 $0\cur_idx7[3:0]
end
- attribute \src "libresoc.v:53640.3-53649.6"
- process $proc$libresoc.v:53640$2550
+ attribute \src "libresoc.v:53632.3-53641.6"
+ process $proc$libresoc.v:53632$2550
assign { } { }
assign { } { }
assign $0\cur_pri8[7:0] $1\cur_pri8[7:0]
- attribute \src "libresoc.v:53641.5-53641.29"
+ attribute \src "libresoc.v:53633.5-53633.29"
switch \initial
- attribute \src "libresoc.v:53641.9-53641.17"
+ attribute \src "libresoc.v:53633.9-53633.17"
case 1'1
case
end
sync always
update \cur_pri8 $0\cur_pri8[7:0]
end
- attribute \src "libresoc.v:53650.3-53659.6"
- process $proc$libresoc.v:53650$2551
+ attribute \src "libresoc.v:53642.3-53651.6"
+ process $proc$libresoc.v:53642$2551
assign { } { }
assign { } { }
assign $0\cur_idx8[3:0] $1\cur_idx8[3:0]
- attribute \src "libresoc.v:53651.5-53651.29"
+ attribute \src "libresoc.v:53643.5-53643.29"
switch \initial
- attribute \src "libresoc.v:53651.9-53651.17"
+ attribute \src "libresoc.v:53643.9-53643.17"
case 1'1
case
end
sync always
update \cur_idx8 $0\cur_idx8[3:0]
end
- attribute \src "libresoc.v:53660.3-53669.6"
- process $proc$libresoc.v:53660$2552
+ attribute \src "libresoc.v:53652.3-53661.6"
+ process $proc$libresoc.v:53652$2552
assign { } { }
assign { } { }
assign $0\cur_pri9[7:0] $1\cur_pri9[7:0]
- attribute \src "libresoc.v:53661.5-53661.29"
+ attribute \src "libresoc.v:53653.5-53653.29"
switch \initial
- attribute \src "libresoc.v:53661.9-53661.17"
+ attribute \src "libresoc.v:53653.9-53653.17"
case 1'1
case
end
sync always
update \cur_pri9 $0\cur_pri9[7:0]
end
- attribute \src "libresoc.v:53670.3-53679.6"
- process $proc$libresoc.v:53670$2553
+ attribute \src "libresoc.v:53662.3-53671.6"
+ process $proc$libresoc.v:53662$2553
assign { } { }
assign { } { }
assign $0\cur_idx9[3:0] $1\cur_idx9[3:0]
- attribute \src "libresoc.v:53671.5-53671.29"
+ attribute \src "libresoc.v:53663.5-53663.29"
switch \initial
- attribute \src "libresoc.v:53671.9-53671.17"
+ attribute \src "libresoc.v:53663.9-53663.17"
case 1'1
case
end
sync always
update \cur_idx9 $0\cur_idx9[3:0]
end
- attribute \src "libresoc.v:53680.3-53689.6"
- process $proc$libresoc.v:53680$2554
+ attribute \src "libresoc.v:53672.3-53681.6"
+ process $proc$libresoc.v:53672$2554
assign { } { }
assign { } { }
assign $0\cur_pri10[7:0] $1\cur_pri10[7:0]
- attribute \src "libresoc.v:53681.5-53681.29"
+ attribute \src "libresoc.v:53673.5-53673.29"
switch \initial
- attribute \src "libresoc.v:53681.9-53681.17"
+ attribute \src "libresoc.v:53673.9-53673.17"
case 1'1
case
end
sync always
update \cur_pri10 $0\cur_pri10[7:0]
end
- attribute \src "libresoc.v:53690.3-53699.6"
- process $proc$libresoc.v:53690$2555
+ attribute \src "libresoc.v:53682.3-53691.6"
+ process $proc$libresoc.v:53682$2555
assign { } { }
assign { } { }
assign $0\cur_idx10[3:0] $1\cur_idx10[3:0]
- attribute \src "libresoc.v:53691.5-53691.29"
+ attribute \src "libresoc.v:53683.5-53683.29"
switch \initial
- attribute \src "libresoc.v:53691.9-53691.17"
+ attribute \src "libresoc.v:53683.9-53683.17"
case 1'1
case
end
sync always
update \cur_idx10 $0\cur_idx10[3:0]
end
- attribute \src "libresoc.v:53700.3-53709.6"
- process $proc$libresoc.v:53700$2556
+ attribute \src "libresoc.v:53692.3-53701.6"
+ process $proc$libresoc.v:53692$2556
assign { } { }
assign { } { }
assign $0\cur_pri11[7:0] $1\cur_pri11[7:0]
- attribute \src "libresoc.v:53701.5-53701.29"
+ attribute \src "libresoc.v:53693.5-53693.29"
switch \initial
- attribute \src "libresoc.v:53701.9-53701.17"
+ attribute \src "libresoc.v:53693.9-53693.17"
case 1'1
case
end
sync always
update \cur_pri11 $0\cur_pri11[7:0]
end
- attribute \src "libresoc.v:53710.3-53719.6"
- process $proc$libresoc.v:53710$2557
+ attribute \src "libresoc.v:53702.3-53711.6"
+ process $proc$libresoc.v:53702$2557
assign { } { }
assign { } { }
assign $0\cur_idx11[3:0] $1\cur_idx11[3:0]
- attribute \src "libresoc.v:53711.5-53711.29"
+ attribute \src "libresoc.v:53703.5-53703.29"
switch \initial
- attribute \src "libresoc.v:53711.9-53711.17"
+ attribute \src "libresoc.v:53703.9-53703.17"
case 1'1
case
end
sync always
update \cur_idx11 $0\cur_idx11[3:0]
end
- attribute \src "libresoc.v:53720.3-53729.6"
- process $proc$libresoc.v:53720$2558
+ attribute \src "libresoc.v:53712.3-53721.6"
+ process $proc$libresoc.v:53712$2558
assign { } { }
assign { } { }
assign $0\cur_pri12[7:0] $1\cur_pri12[7:0]
- attribute \src "libresoc.v:53721.5-53721.29"
+ attribute \src "libresoc.v:53713.5-53713.29"
switch \initial
- attribute \src "libresoc.v:53721.9-53721.17"
+ attribute \src "libresoc.v:53713.9-53713.17"
case 1'1
case
end
sync always
update \cur_pri12 $0\cur_pri12[7:0]
end
- attribute \src "libresoc.v:53730.3-53739.6"
- process $proc$libresoc.v:53730$2559
+ attribute \src "libresoc.v:53722.3-53731.6"
+ process $proc$libresoc.v:53722$2559
assign { } { }
assign { } { }
assign $0\cur_idx12[3:0] $1\cur_idx12[3:0]
- attribute \src "libresoc.v:53731.5-53731.29"
+ attribute \src "libresoc.v:53723.5-53723.29"
switch \initial
- attribute \src "libresoc.v:53731.9-53731.17"
+ attribute \src "libresoc.v:53723.9-53723.17"
case 1'1
case
end
sync always
update \cur_idx12 $0\cur_idx12[3:0]
end
- attribute \src "libresoc.v:53740.3-53749.6"
- process $proc$libresoc.v:53740$2560
+ attribute \src "libresoc.v:53732.3-53741.6"
+ process $proc$libresoc.v:53732$2560
assign { } { }
assign { } { }
assign $0\cur_pri13[7:0] $1\cur_pri13[7:0]
- attribute \src "libresoc.v:53741.5-53741.29"
+ attribute \src "libresoc.v:53733.5-53733.29"
switch \initial
- attribute \src "libresoc.v:53741.9-53741.17"
+ attribute \src "libresoc.v:53733.9-53733.17"
case 1'1
case
end
sync always
update \cur_pri13 $0\cur_pri13[7:0]
end
- attribute \src "libresoc.v:53750.3-53759.6"
- process $proc$libresoc.v:53750$2561
+ attribute \src "libresoc.v:53742.3-53751.6"
+ process $proc$libresoc.v:53742$2561
assign { } { }
assign { } { }
assign $0\cur_idx13[3:0] $1\cur_idx13[3:0]
- attribute \src "libresoc.v:53751.5-53751.29"
+ attribute \src "libresoc.v:53743.5-53743.29"
switch \initial
- attribute \src "libresoc.v:53751.9-53751.17"
+ attribute \src "libresoc.v:53743.9-53743.17"
case 1'1
case
end
sync always
update \cur_idx13 $0\cur_idx13[3:0]
end
- attribute \src "libresoc.v:53760.3-53769.6"
- process $proc$libresoc.v:53760$2562
+ attribute \src "libresoc.v:53752.3-53761.6"
+ process $proc$libresoc.v:53752$2562
assign { } { }
assign { } { }
assign $0\cur_pri14[7:0] $1\cur_pri14[7:0]
- attribute \src "libresoc.v:53761.5-53761.29"
+ attribute \src "libresoc.v:53753.5-53753.29"
switch \initial
- attribute \src "libresoc.v:53761.9-53761.17"
+ attribute \src "libresoc.v:53753.9-53753.17"
case 1'1
case
end
sync always
update \cur_pri14 $0\cur_pri14[7:0]
end
- attribute \src "libresoc.v:53770.3-53819.6"
- process $proc$libresoc.v:53770$2563
+ attribute \src "libresoc.v:53762.3-53811.6"
+ process $proc$libresoc.v:53762$2563
assign { } { }
assign { } { }
assign $0\be_out[31:0] $1\be_out[31:0]
- attribute \src "libresoc.v:53771.5-53771.29"
+ attribute \src "libresoc.v:53763.5-53763.29"
switch \initial
- attribute \src "libresoc.v:53771.9-53771.17"
+ attribute \src "libresoc.v:53763.9-53763.17"
case 1'1
case
end
sync always
update \be_out $0\be_out[31:0]
end
- attribute \src "libresoc.v:53820.3-53829.6"
- process $proc$libresoc.v:53820$2564
+ attribute \src "libresoc.v:53812.3-53821.6"
+ process $proc$libresoc.v:53812$2564
assign { } { }
assign { } { }
assign $0\cur_idx14[3:0] $1\cur_idx14[3:0]
- attribute \src "libresoc.v:53821.5-53821.29"
+ attribute \src "libresoc.v:53813.5-53813.29"
switch \initial
- attribute \src "libresoc.v:53821.9-53821.17"
+ attribute \src "libresoc.v:53813.9-53813.17"
case 1'1
case
end
sync always
update \cur_idx14 $0\cur_idx14[3:0]
end
- attribute \src "libresoc.v:53830.3-53839.6"
- process $proc$libresoc.v:53830$2565
+ attribute \src "libresoc.v:53822.3-53831.6"
+ process $proc$libresoc.v:53822$2565
assign { } { }
assign { } { }
assign $0\cur_pri15[7:0] $1\cur_pri15[7:0]
- attribute \src "libresoc.v:53831.5-53831.29"
+ attribute \src "libresoc.v:53823.5-53823.29"
switch \initial
- attribute \src "libresoc.v:53831.9-53831.17"
+ attribute \src "libresoc.v:53823.9-53823.17"
case 1'1
case
end
sync always
update \cur_pri15 $0\cur_pri15[7:0]
end
- attribute \src "libresoc.v:53840.3-53849.6"
- process $proc$libresoc.v:53840$2566
+ attribute \src "libresoc.v:53832.3-53841.6"
+ process $proc$libresoc.v:53832$2566
assign { } { }
assign { } { }
assign $0\cur_idx15[3:0] $1\cur_idx15[3:0]
- attribute \src "libresoc.v:53841.5-53841.29"
+ attribute \src "libresoc.v:53833.5-53833.29"
switch \initial
- attribute \src "libresoc.v:53841.9-53841.17"
+ attribute \src "libresoc.v:53833.9-53833.17"
case 1'1
case
end
sync always
update \cur_idx15 $0\cur_idx15[3:0]
end
- attribute \src "libresoc.v:53850.3-53859.6"
- process $proc$libresoc.v:53850$2567
+ attribute \src "libresoc.v:53842.3-53851.6"
+ process $proc$libresoc.v:53842$2567
assign { } { }
assign { } { }
assign $0\ibit[0:0] $1\ibit[0:0]
- attribute \src "libresoc.v:53851.5-53851.29"
+ attribute \src "libresoc.v:53843.5-53843.29"
switch \initial
- attribute \src "libresoc.v:53851.9-53851.17"
+ attribute \src "libresoc.v:53843.9-53843.17"
case 1'1
case
end
sync always
update \ibit $0\ibit[0:0]
end
- attribute \src "libresoc.v:53860.3-53868.6"
- process $proc$libresoc.v:53860$2568
+ attribute \src "libresoc.v:53852.3-53860.6"
+ process $proc$libresoc.v:53852$2568
assign { } { }
assign { } { }
assign $0\ics_wb__dat_r$next[31:0]$2569 $1\ics_wb__dat_r$next[31:0]$2570
- attribute \src "libresoc.v:53861.5-53861.29"
+ attribute \src "libresoc.v:53853.5-53853.29"
switch \initial
- attribute \src "libresoc.v:53861.9-53861.17"
+ attribute \src "libresoc.v:53853.9-53853.17"
case 1'1
case
end
sync always
update \ics_wb__dat_r$next $0\ics_wb__dat_r$next[31:0]$2569
end
- attribute \src "libresoc.v:53869.3-53877.6"
- process $proc$libresoc.v:53869$2571
+ attribute \src "libresoc.v:53861.3-53869.6"
+ process $proc$libresoc.v:53861$2571
assign { } { }
assign { } { }
assign $0\ics_wb__ack$next[0:0]$2572 $1\ics_wb__ack$next[0:0]$2573
- attribute \src "libresoc.v:53870.5-53870.29"
+ attribute \src "libresoc.v:53862.5-53862.29"
switch \initial
- attribute \src "libresoc.v:53870.9-53870.17"
+ attribute \src "libresoc.v:53862.9-53862.17"
case 1'1
case
end
sync always
update \ics_wb__ack$next $0\ics_wb__ack$next[0:0]$2572
end
- connect \$7 $ternary$libresoc.v:53240$2326_Y
- connect \$99 $lt$libresoc.v:53241$2327_Y
- connect \$101 $and$libresoc.v:53242$2328_Y
- connect \$103 $lt$libresoc.v:53243$2329_Y
- connect \$105 $and$libresoc.v:53244$2330_Y
- connect \$107 $lt$libresoc.v:53245$2331_Y
- connect \$109 $and$libresoc.v:53246$2332_Y
- connect \$111 $lt$libresoc.v:53247$2333_Y
- connect \$113 $and$libresoc.v:53248$2334_Y
- connect \$115 $lt$libresoc.v:53249$2335_Y
- connect \$117 $and$libresoc.v:53250$2336_Y
- connect \$119 $lt$libresoc.v:53251$2337_Y
- connect \$121 $and$libresoc.v:53252$2338_Y
- connect \$123 $lt$libresoc.v:53253$2339_Y
- connect \$125 $and$libresoc.v:53254$2340_Y
- connect \$127 $lt$libresoc.v:53255$2341_Y
- connect \$12 $eq$libresoc.v:53256$2342_Y
- connect \$129 $and$libresoc.v:53257$2343_Y
- connect \$131 $lt$libresoc.v:53258$2344_Y
- connect \$133 $and$libresoc.v:53259$2345_Y
- connect \$135 $lt$libresoc.v:53260$2346_Y
- connect \$137 $and$libresoc.v:53261$2347_Y
- connect \$11 $ternary$libresoc.v:53262$2348_Y
- connect \$139 $lt$libresoc.v:53263$2349_Y
- connect \$141 $and$libresoc.v:53264$2350_Y
- connect \$143 $lt$libresoc.v:53265$2351_Y
- connect \$145 $and$libresoc.v:53266$2352_Y
- connect \$147 $lt$libresoc.v:53267$2353_Y
- connect \$149 $and$libresoc.v:53268$2354_Y
- connect \$151 $lt$libresoc.v:53269$2355_Y
- connect \$153 $and$libresoc.v:53270$2356_Y
- connect \$155 $lt$libresoc.v:53271$2357_Y
- connect \$157 $and$libresoc.v:53272$2358_Y
- connect \$159 $lt$libresoc.v:53273$2359_Y
- connect \$161 $and$libresoc.v:53274$2360_Y
- connect \$163 $lt$libresoc.v:53275$2361_Y
- connect \$165 $and$libresoc.v:53276$2362_Y
- connect \$167 $lt$libresoc.v:53277$2363_Y
- connect \$16 $eq$libresoc.v:53278$2364_Y
- connect \$169 $and$libresoc.v:53279$2365_Y
- connect \$171 $lt$libresoc.v:53280$2366_Y
- connect \$173 $and$libresoc.v:53281$2367_Y
- connect \$175 $lt$libresoc.v:53282$2368_Y
- connect \$177 $and$libresoc.v:53283$2369_Y
- connect \$15 $ternary$libresoc.v:53284$2370_Y
- connect \$179 $lt$libresoc.v:53285$2371_Y
- connect \$181 $and$libresoc.v:53286$2372_Y
- connect \$183 $lt$libresoc.v:53287$2373_Y
- connect \$185 $and$libresoc.v:53288$2374_Y
- connect \$187 $lt$libresoc.v:53289$2375_Y
- connect \$189 $and$libresoc.v:53290$2376_Y
- connect \$191 $lt$libresoc.v:53291$2377_Y
- connect \$193 $and$libresoc.v:53292$2378_Y
- connect \$195 $lt$libresoc.v:53293$2379_Y
- connect \$197 $and$libresoc.v:53294$2380_Y
- connect \$1 $eq$libresoc.v:53295$2381_Y
- connect \$199 $lt$libresoc.v:53296$2382_Y
- connect \$201 $and$libresoc.v:53297$2383_Y
- connect \$204 $eq$libresoc.v:53298$2384_Y
- connect \$203 $ternary$libresoc.v:53299$2385_Y
- connect \$20 $eq$libresoc.v:53300$2386_Y
- connect \$19 $ternary$libresoc.v:53301$2387_Y
- connect \$24 $eq$libresoc.v:53302$2388_Y
- connect \$23 $ternary$libresoc.v:53303$2389_Y
- connect \$28 $eq$libresoc.v:53304$2390_Y
- connect \$27 $ternary$libresoc.v:53305$2391_Y
- connect \$32 $eq$libresoc.v:53306$2392_Y
- connect \$31 $ternary$libresoc.v:53307$2393_Y
- connect \$36 $eq$libresoc.v:53308$2394_Y
- connect \$35 $ternary$libresoc.v:53309$2395_Y
- connect \$3 $eq$libresoc.v:53310$2396_Y
- connect \$40 $eq$libresoc.v:53311$2397_Y
- connect \$39 $ternary$libresoc.v:53312$2398_Y
- connect \$44 $eq$libresoc.v:53313$2399_Y
- connect \$43 $ternary$libresoc.v:53314$2400_Y
- connect \$48 $eq$libresoc.v:53315$2401_Y
- connect \$47 $ternary$libresoc.v:53316$2402_Y
- connect \$52 $eq$libresoc.v:53317$2403_Y
- connect \$51 $ternary$libresoc.v:53318$2404_Y
- connect \$56 $eq$libresoc.v:53319$2405_Y
- connect \$55 $ternary$libresoc.v:53320$2406_Y
- connect \$5 $and$libresoc.v:53321$2407_Y
- connect \$60 $eq$libresoc.v:53322$2408_Y
- connect \$59 $ternary$libresoc.v:53323$2409_Y
- connect \$64 $eq$libresoc.v:53324$2410_Y
- connect \$63 $ternary$libresoc.v:53325$2411_Y
- connect \$68 $eq$libresoc.v:53326$2412_Y
- connect \$67 $ternary$libresoc.v:53327$2413_Y
- connect \$71 $shr$libresoc.v:53328$2414_Y [0]
- connect \$73 $and$libresoc.v:53329$2415_Y
- connect \$75 $lt$libresoc.v:53330$2416_Y
- connect \$77 $and$libresoc.v:53331$2417_Y
- connect \$79 $lt$libresoc.v:53332$2418_Y
- connect \$81 $and$libresoc.v:53333$2419_Y
- connect \$83 $lt$libresoc.v:53334$2420_Y
- connect \$85 $and$libresoc.v:53335$2421_Y
- connect \$87 $lt$libresoc.v:53336$2422_Y
- connect \$8 $eq$libresoc.v:53337$2423_Y
- connect \$89 $and$libresoc.v:53338$2424_Y
- connect \$91 $lt$libresoc.v:53339$2425_Y
- connect \$93 $and$libresoc.v:53340$2426_Y
- connect \$95 $lt$libresoc.v:53341$2427_Y
- connect \$97 $and$libresoc.v:53342$2428_Y
+ connect \$7 $ternary$libresoc.v:53232$2326_Y
+ connect \$99 $lt$libresoc.v:53233$2327_Y
+ connect \$101 $and$libresoc.v:53234$2328_Y
+ connect \$103 $lt$libresoc.v:53235$2329_Y
+ connect \$105 $and$libresoc.v:53236$2330_Y
+ connect \$107 $lt$libresoc.v:53237$2331_Y
+ connect \$109 $and$libresoc.v:53238$2332_Y
+ connect \$111 $lt$libresoc.v:53239$2333_Y
+ connect \$113 $and$libresoc.v:53240$2334_Y
+ connect \$115 $lt$libresoc.v:53241$2335_Y
+ connect \$117 $and$libresoc.v:53242$2336_Y
+ connect \$119 $lt$libresoc.v:53243$2337_Y
+ connect \$121 $and$libresoc.v:53244$2338_Y
+ connect \$123 $lt$libresoc.v:53245$2339_Y
+ connect \$125 $and$libresoc.v:53246$2340_Y
+ connect \$127 $lt$libresoc.v:53247$2341_Y
+ connect \$12 $eq$libresoc.v:53248$2342_Y
+ connect \$129 $and$libresoc.v:53249$2343_Y
+ connect \$131 $lt$libresoc.v:53250$2344_Y
+ connect \$133 $and$libresoc.v:53251$2345_Y
+ connect \$135 $lt$libresoc.v:53252$2346_Y
+ connect \$137 $and$libresoc.v:53253$2347_Y
+ connect \$11 $ternary$libresoc.v:53254$2348_Y
+ connect \$139 $lt$libresoc.v:53255$2349_Y
+ connect \$141 $and$libresoc.v:53256$2350_Y
+ connect \$143 $lt$libresoc.v:53257$2351_Y
+ connect \$145 $and$libresoc.v:53258$2352_Y
+ connect \$147 $lt$libresoc.v:53259$2353_Y
+ connect \$149 $and$libresoc.v:53260$2354_Y
+ connect \$151 $lt$libresoc.v:53261$2355_Y
+ connect \$153 $and$libresoc.v:53262$2356_Y
+ connect \$155 $lt$libresoc.v:53263$2357_Y
+ connect \$157 $and$libresoc.v:53264$2358_Y
+ connect \$159 $lt$libresoc.v:53265$2359_Y
+ connect \$161 $and$libresoc.v:53266$2360_Y
+ connect \$163 $lt$libresoc.v:53267$2361_Y
+ connect \$165 $and$libresoc.v:53268$2362_Y
+ connect \$167 $lt$libresoc.v:53269$2363_Y
+ connect \$16 $eq$libresoc.v:53270$2364_Y
+ connect \$169 $and$libresoc.v:53271$2365_Y
+ connect \$171 $lt$libresoc.v:53272$2366_Y
+ connect \$173 $and$libresoc.v:53273$2367_Y
+ connect \$175 $lt$libresoc.v:53274$2368_Y
+ connect \$177 $and$libresoc.v:53275$2369_Y
+ connect \$15 $ternary$libresoc.v:53276$2370_Y
+ connect \$179 $lt$libresoc.v:53277$2371_Y
+ connect \$181 $and$libresoc.v:53278$2372_Y
+ connect \$183 $lt$libresoc.v:53279$2373_Y
+ connect \$185 $and$libresoc.v:53280$2374_Y
+ connect \$187 $lt$libresoc.v:53281$2375_Y
+ connect \$189 $and$libresoc.v:53282$2376_Y
+ connect \$191 $lt$libresoc.v:53283$2377_Y
+ connect \$193 $and$libresoc.v:53284$2378_Y
+ connect \$195 $lt$libresoc.v:53285$2379_Y
+ connect \$197 $and$libresoc.v:53286$2380_Y
+ connect \$1 $eq$libresoc.v:53287$2381_Y
+ connect \$199 $lt$libresoc.v:53288$2382_Y
+ connect \$201 $and$libresoc.v:53289$2383_Y
+ connect \$204 $eq$libresoc.v:53290$2384_Y
+ connect \$203 $ternary$libresoc.v:53291$2385_Y
+ connect \$20 $eq$libresoc.v:53292$2386_Y
+ connect \$19 $ternary$libresoc.v:53293$2387_Y
+ connect \$24 $eq$libresoc.v:53294$2388_Y
+ connect \$23 $ternary$libresoc.v:53295$2389_Y
+ connect \$28 $eq$libresoc.v:53296$2390_Y
+ connect \$27 $ternary$libresoc.v:53297$2391_Y
+ connect \$32 $eq$libresoc.v:53298$2392_Y
+ connect \$31 $ternary$libresoc.v:53299$2393_Y
+ connect \$36 $eq$libresoc.v:53300$2394_Y
+ connect \$35 $ternary$libresoc.v:53301$2395_Y
+ connect \$3 $eq$libresoc.v:53302$2396_Y
+ connect \$40 $eq$libresoc.v:53303$2397_Y
+ connect \$39 $ternary$libresoc.v:53304$2398_Y
+ connect \$44 $eq$libresoc.v:53305$2399_Y
+ connect \$43 $ternary$libresoc.v:53306$2400_Y
+ connect \$48 $eq$libresoc.v:53307$2401_Y
+ connect \$47 $ternary$libresoc.v:53308$2402_Y
+ connect \$52 $eq$libresoc.v:53309$2403_Y
+ connect \$51 $ternary$libresoc.v:53310$2404_Y
+ connect \$56 $eq$libresoc.v:53311$2405_Y
+ connect \$55 $ternary$libresoc.v:53312$2406_Y
+ connect \$5 $and$libresoc.v:53313$2407_Y
+ connect \$60 $eq$libresoc.v:53314$2408_Y
+ connect \$59 $ternary$libresoc.v:53315$2409_Y
+ connect \$64 $eq$libresoc.v:53316$2410_Y
+ connect \$63 $ternary$libresoc.v:53317$2411_Y
+ connect \$68 $eq$libresoc.v:53318$2412_Y
+ connect \$67 $ternary$libresoc.v:53319$2413_Y
+ connect \$71 $shr$libresoc.v:53320$2414_Y [0]
+ connect \$73 $and$libresoc.v:53321$2415_Y
+ connect \$75 $lt$libresoc.v:53322$2416_Y
+ connect \$77 $and$libresoc.v:53323$2417_Y
+ connect \$79 $lt$libresoc.v:53324$2418_Y
+ connect \$81 $and$libresoc.v:53325$2419_Y
+ connect \$83 $lt$libresoc.v:53326$2420_Y
+ connect \$85 $and$libresoc.v:53327$2421_Y
+ connect \$87 $lt$libresoc.v:53328$2422_Y
+ connect \$8 $eq$libresoc.v:53329$2423_Y
+ connect \$89 $and$libresoc.v:53330$2424_Y
+ connect \$91 $lt$libresoc.v:53331$2425_Y
+ connect \$93 $and$libresoc.v:53332$2426_Y
+ connect \$95 $lt$libresoc.v:53333$2427_Y
+ connect \$97 $and$libresoc.v:53334$2428_Y
connect \icp_r_pri \$203
connect \icp_r_src \cur_idx15
connect \max_idx 4'0000
projects / soclayout.git / commitdiff