add SVSRR0 to FastRegsEnum

diff --git a/src/soc/regfile/regfiles.py b/src/soc/regfile/regfiles.py
index 1f45ab918bb2bfe1104bb57741e39de7f5549b80..26abc7797cb044dae28a541e5cb7d67519481cf5 100644 (file)
--- a/src/soc/regfile/regfiles.py
+++ b/src/soc/regfile/regfiles.py
@@ -90,7 +90,7 @@ class IntRegs(RegFileMem): #class IntRegs(RegFileArray):
 class FastRegs(RegFileMem, FastRegsEnum): #RegFileArray):
     """FastRegs
 
-    FAST regfile  - CTR, LR, TAR, SRR1, SRR2, XER, TB, DEC
+    FAST regfile  - CTR, LR, TAR, SRR1, SRR2, XER, TB, DEC, SVSRR0
 
     * QTY 6of 64-bit registers
     * 3R2W