intel/genxml: add PIPE_CONTROL command cache invalidate bit

This new bit invalidates the cache/prefetch of commands in the command
streamer. This will be useful for self modifying batches.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2775>

diff --git a/src/intel/genxml/gen11.xml b/src/intel/genxml/gen11.xml
index d778abcbfedf17a42171f3789c92e6f7479d21ab..5e87d5affc22fcac5e2a039d51e2ff3717e6c742 100644 (file)
--- a/src/intel/genxml/gen11.xml
+++ b/src/intel/genxml/gen11.xml
@@ -6272,6 +6272,7 @@
       <value name="GGTT" value="1"/>
     </field>
     <field name="Flush LLC" start="58" end="58" type="bool"/>
+    <field name="Command Cache Invalidate Enable" start="61" end="61" type="bool"/>
     <field name="Address" start="66" end="111" type="address"/>
     <field name="Immediate Data" start="128" end="191" type="uint"/>
   </instruction>

diff --git a/src/intel/genxml/gen12.xml b/src/intel/genxml/gen12.xml
index f5ccb1826812dec805f236e1652aa1b701f444c1..b8bada119c21681b4ccd9ab243313baef21b9fd8 100644 (file)
--- a/src/intel/genxml/gen12.xml
+++ b/src/intel/genxml/gen12.xml
@@ -6413,6 +6413,7 @@
     </field>
     <field name="Flush LLC" start="58" end="58" type="bool"/>
     <field name="Tile Cache Flush Enable" start="60" end="60" type="bool"/>
+    <field name="Command Cache Invalidate Enable" start="61" end="61" type="bool"/>
     <field name="Address" start="66" end="111" type="address"/>
     <field name="Immediate Data" start="128" end="191" type="uint"/>
   </instruction>