whoops reverse flexbus in/out AD

diff --git a/src/bsv/peripheral_gen/flexbus.py b/src/bsv/peripheral_gen/flexbus.py
index 82d67e452926e772760eadf24b932648fe071cec..3ab1f2b77e38042e25952051d2d37cb1e6bce421 100644 (file)
--- a/src/bsv/peripheral_gen/flexbus.py
+++ b/src/bsv/peripheral_gen/flexbus.py
@@ -50,8 +50,8 @@ class flexbus(PBase):
             ('bwe', 'm_BWEn'),
             ('tbst', 'm_TBSTn'),
             ('tsiz', 'm_TSIZ'),
-            ('ad_in', 'm_AD'),
-            ('ad_out', 'm_din'),
+            ('ad_out', 'm_AD'),
+            ('ad_in', 'm_din'),
             ('ad_en', 'm_OE32n'),
         ]:
             ret.append(template.format(ps, ptype, n, stype))