ilang file output change from alu_pipeline.il to div_pipeline.il

diff --git a/src/soc/fu/div/test/test_pipe_caller.py b/src/soc/fu/div/test/test_pipe_caller.py
index 2e66f90afb13ba12ae01609d76ea3eee6955ff38..4a25a5fa5fc600a32d4568a467486aba5516c061 100644 (file)
--- a/src/soc/fu/div/test/test_pipe_caller.py
+++ b/src/soc/fu/div/test/test_pipe_caller.py
@@ -190,7 +190,7 @@ class DIVTestCase(FHDLTestCase):
         pspec = DIVPipeSpec(id_wid=2)
         alu = DIVBasePipe(pspec)
         vl = rtlil.convert(alu, ports=alu.ports())
-        with open("alu_pipeline.il", "w") as f:
+        with open("div_pipeline.il", "w") as f:
             f.write(vl)