sort out adding SPBlock_512 SRAM verilog to ls180

diff --git a/experiments9/build_full_4ksram.sh b/experiments9/build_full_4ksram.sh
index b82447db75ea80bb358f707647d6bace5c470cbc..829664458a34f30e7aae49409cc099ac412e5e39 100755 (executable)
--- a/experiments9/build_full_4ksram.sh
+++ b/experiments9/build_full_4ksram.sh
@@ -21,9 +21,10 @@ rm *.vst *.ap
 
 # copies over a "full" core
 #cp non_generated/full_core_4_4ksram_ls180.il ls180.il
-cp non_generated/ls180.v ls180.v
+cp non_generated/full_core_4_4ksram_ls180.v ls180.v
 cp non_generated/full_core_4_4ksram_litex_ls180.v litex_ls180.v
 cp non_generated/full_core_4_4ksram_libresoc.v libresoc.v
+cp non_generated/SPBlock*.v* .
 touch mem.init
 touch mem_1.init
 touch mem_2.init
@@ -32,7 +33,7 @@ touch mem_4.init
 touch mem_5.init
 
 
-# make the vst from ilang
+# make the vst from verilog
 make vst
 
 # starts the build.

diff --git a/experiments9/non_generated/SPBlock_512W64B8W.v b/experiments9/non_generated/SPBlock_512W64B8W.v
new file mode 100644 (file)
index 0000000..ddab968
--- /dev/null
+++ b/experiments9/non_generated/SPBlock_512W64B8W.v
@@ -0,0 +1,7 @@
+(* blackbox = 1 *)
+module SPBlock_512W64B8W(input [8:0] a,
+                        input [63:0] d,
+                        output [63:0] q,
+                        input [7:0] we,
+                        input clk);
+endmodule // SPBlock_512W64B8W

diff --git a/experiments9/non_generated/SPBlock_512W64B8W.vbe b/experiments9/non_generated/SPBlock_512W64B8W.vbe
new file mode 100644 (file)
index 0000000..c752468
--- /dev/null
+++ b/experiments9/non_generated/SPBlock_512W64B8W.vbe
@@ -0,0 +1,19 @@
+
+-- Phony VHDL interface for SRAM block.
+
+entity SPBlock_512W64B8W is
+   port ( clk     : in  bit
+        ; we      : in  bit_vector( 7 downto 0)
+        ; a       : in  bit_vector( 8 downto 0)
+        ; d       : in  bit_vector(63 downto 0)
+        ; q       : out bit_vector(63 downto 0)
+        ; vdd     : in  bit
+        ; vss     : in  bit
+        );
+end SPBlock_512W64B8W;
+
+architecture behavioral of SPBlock_512W64B8W is
+
+begin
+
+end behavioral;

diff --git a/experiments9/non_generated/full_core_4_4ksram_ls180.v b/experiments9/non_generated/full_core_4_4ksram_ls180.v
new file mode 100644 (file)
index 0000000..6b3619a
--- /dev/null
+++ b/experiments9/non_generated/full_core_4_4ksram_ls180.v
@@ -0,0 +1,3 @@
+`include "litex_ls180.v"
+`include "SPBlock_512W64B8W.v"
+`include "libresoc.v"

diff --git a/experiments9/tsmc_c018/SPBlock_512W64B8W.v b/experiments9/tsmc_c018/SPBlock_512W64B8W.v
deleted file mode 100644 (file)
index ddab968..0000000
--- a/experiments9/tsmc_c018/SPBlock_512W64B8W.v
+++ /dev/null
@@ -1,7 +0,0 @@
-(* blackbox = 1 *)
-module SPBlock_512W64B8W(input [8:0] a,
-                        input [63:0] d,
-                        output [63:0] q,
-                        input [7:0] we,
-                        input clk);
-endmodule // SPBlock_512W64B8W

diff --git a/experiments9/tsmc_c018/SPBlock_512W64B8W.vbe b/experiments9/tsmc_c018/SPBlock_512W64B8W.vbe
deleted file mode 100644 (file)
index c752468..0000000
--- a/experiments9/tsmc_c018/SPBlock_512W64B8W.vbe
+++ /dev/null
@@ -1,19 +0,0 @@
-
--- Phony VHDL interface for SRAM block.
-
-entity SPBlock_512W64B8W is
-   port ( clk     : in  bit
-        ; we      : in  bit_vector( 7 downto 0)
-        ; a       : in  bit_vector( 8 downto 0)
-        ; d       : in  bit_vector(63 downto 0)
-        ; q       : out bit_vector(63 downto 0)
-        ; vdd     : in  bit
-        ; vss     : in  bit
-        );
-end SPBlock_512W64B8W;
-
-architecture behavioral of SPBlock_512W64B8W is
-
-begin
-
-end behavioral;

diff --git a/experiments9/tsmc_c018/build_full_4ksram.sh b/experiments9/tsmc_c018/build_full_4ksram.sh
index 7402934501d961399d0f06c6ac9fd81b9143e57d..3f96d1fea011c127eb4bfe178d7b048cad6f4cfa 100755 (executable)
--- a/experiments9/tsmc_c018/build_full_4ksram.sh
+++ b/experiments9/tsmc_c018/build_full_4ksram.sh
@@ -21,9 +21,10 @@ rm *.vst *.ap
 # copies over a "full" core with 4k SRAMs.  SPBlock_512W6B484.v should
 # already be in this directory
 #cp non_generated/full_core_4_4ksram_ls180.il ls180.il
-cp non_generated/ls180.v ls180.v
+cp non_generated/full_core_4_4ksram_ls180.v ls180.v
 cp non_generated/full_core_4_4ksram_litex_ls180.v litex_ls180.v
 cp non_generated/full_core_4_4ksram_libresoc.v libresoc.v
+cp non_generated/SPBlock*.v* .
 touch mem.init
 touch mem_1.init
 touch mem_2.init
@@ -32,17 +33,10 @@ touch mem_4.init
 touch mem_5.init
 
 
-# make the vst from ilang
+# make the vst from verilog
 make vst
 
 # starts the build.
 make lvx
 
 
-
-# make the vst from ilang
-make vst
-
-# starts the build.
-make lvx
-